1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31 #include <linux/netdevice.h>
34 #include "ixgbe_common.h"
35 #include "ixgbe_phy.h"
37 static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw);
38 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
39 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
40 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
41 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
42 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
43 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
45 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
46 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
48 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
49 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw);
51 static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index);
52 static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index);
53 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
54 static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
55 static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num);
58 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
59 * @hw: pointer to hardware structure
61 * Starts the hardware by filling the bus info structure and media type, clears
62 * all on chip counters, initializes receive address registers, multicast
63 * table, VLAN filter table, calls routine to set up link and flow control
64 * settings, and leaves transmit and receive units disabled and uninitialized
66 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
70 /* Set the media type */
71 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
73 /* Identify the PHY */
74 hw->phy.ops.identify(hw);
76 /* Clear the VLAN filter table */
77 hw->mac.ops.clear_vfta(hw);
79 /* Clear statistics registers */
80 hw->mac.ops.clear_hw_cntrs(hw);
82 /* Set No Snoop Disable */
83 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
84 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
85 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
86 IXGBE_WRITE_FLUSH(hw);
88 /* Setup flow control */
89 ixgbe_setup_fc(hw, 0);
91 /* Clear adapter stopped flag */
92 hw->adapter_stopped = false;
98 * ixgbe_init_hw_generic - Generic hardware initialization
99 * @hw: pointer to hardware structure
101 * Initialize the hardware by resetting the hardware, filling the bus info
102 * structure and media type, clears all on chip counters, initializes receive
103 * address registers, multicast table, VLAN filter table, calls routine to set
104 * up link and flow control settings, and leaves transmit and receive units
105 * disabled and uninitialized
107 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
111 /* Reset the hardware */
112 status = hw->mac.ops.reset_hw(hw);
116 status = hw->mac.ops.start_hw(hw);
123 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
124 * @hw: pointer to hardware structure
126 * Clears all hardware statistics counters by reading them from the hardware
127 * Statistics counters are clear on read.
129 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
133 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
134 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
135 IXGBE_READ_REG(hw, IXGBE_ERRBC);
136 IXGBE_READ_REG(hw, IXGBE_MSPDC);
137 for (i = 0; i < 8; i++)
138 IXGBE_READ_REG(hw, IXGBE_MPC(i));
140 IXGBE_READ_REG(hw, IXGBE_MLFC);
141 IXGBE_READ_REG(hw, IXGBE_MRFC);
142 IXGBE_READ_REG(hw, IXGBE_RLEC);
143 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
144 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
145 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
146 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
148 for (i = 0; i < 8; i++) {
149 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
150 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
151 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
152 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
155 IXGBE_READ_REG(hw, IXGBE_PRC64);
156 IXGBE_READ_REG(hw, IXGBE_PRC127);
157 IXGBE_READ_REG(hw, IXGBE_PRC255);
158 IXGBE_READ_REG(hw, IXGBE_PRC511);
159 IXGBE_READ_REG(hw, IXGBE_PRC1023);
160 IXGBE_READ_REG(hw, IXGBE_PRC1522);
161 IXGBE_READ_REG(hw, IXGBE_GPRC);
162 IXGBE_READ_REG(hw, IXGBE_BPRC);
163 IXGBE_READ_REG(hw, IXGBE_MPRC);
164 IXGBE_READ_REG(hw, IXGBE_GPTC);
165 IXGBE_READ_REG(hw, IXGBE_GORCL);
166 IXGBE_READ_REG(hw, IXGBE_GORCH);
167 IXGBE_READ_REG(hw, IXGBE_GOTCL);
168 IXGBE_READ_REG(hw, IXGBE_GOTCH);
169 for (i = 0; i < 8; i++)
170 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
171 IXGBE_READ_REG(hw, IXGBE_RUC);
172 IXGBE_READ_REG(hw, IXGBE_RFC);
173 IXGBE_READ_REG(hw, IXGBE_ROC);
174 IXGBE_READ_REG(hw, IXGBE_RJC);
175 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
176 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
177 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
178 IXGBE_READ_REG(hw, IXGBE_TORL);
179 IXGBE_READ_REG(hw, IXGBE_TORH);
180 IXGBE_READ_REG(hw, IXGBE_TPR);
181 IXGBE_READ_REG(hw, IXGBE_TPT);
182 IXGBE_READ_REG(hw, IXGBE_PTC64);
183 IXGBE_READ_REG(hw, IXGBE_PTC127);
184 IXGBE_READ_REG(hw, IXGBE_PTC255);
185 IXGBE_READ_REG(hw, IXGBE_PTC511);
186 IXGBE_READ_REG(hw, IXGBE_PTC1023);
187 IXGBE_READ_REG(hw, IXGBE_PTC1522);
188 IXGBE_READ_REG(hw, IXGBE_MPTC);
189 IXGBE_READ_REG(hw, IXGBE_BPTC);
190 for (i = 0; i < 16; i++) {
191 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
192 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
193 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
194 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
201 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
202 * @hw: pointer to hardware structure
203 * @pba_num: stores the part number from the EEPROM
205 * Reads the part number from the EEPROM.
207 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
212 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
214 hw_dbg(hw, "NVM Read Error\n");
217 *pba_num = (u32)(data << 16);
219 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
221 hw_dbg(hw, "NVM Read Error\n");
230 * ixgbe_get_mac_addr_generic - Generic get MAC address
231 * @hw: pointer to hardware structure
232 * @mac_addr: Adapter MAC address
234 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
235 * A reset of the adapter must be performed prior to calling this function
236 * in order for the MAC address to have been loaded from the EEPROM into RAR0
238 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
244 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
245 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
247 for (i = 0; i < 4; i++)
248 mac_addr[i] = (u8)(rar_low >> (i*8));
250 for (i = 0; i < 2; i++)
251 mac_addr[i+4] = (u8)(rar_high >> (i*8));
257 * ixgbe_get_bus_info_generic - Generic set PCI bus info
258 * @hw: pointer to hardware structure
260 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
262 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
264 struct ixgbe_adapter *adapter = hw->back;
265 struct ixgbe_mac_info *mac = &hw->mac;
268 hw->bus.type = ixgbe_bus_type_pci_express;
270 /* Get the negotiated link width and speed from PCI config space */
271 pci_read_config_word(adapter->pdev, IXGBE_PCI_LINK_STATUS,
274 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
275 case IXGBE_PCI_LINK_WIDTH_1:
276 hw->bus.width = ixgbe_bus_width_pcie_x1;
278 case IXGBE_PCI_LINK_WIDTH_2:
279 hw->bus.width = ixgbe_bus_width_pcie_x2;
281 case IXGBE_PCI_LINK_WIDTH_4:
282 hw->bus.width = ixgbe_bus_width_pcie_x4;
284 case IXGBE_PCI_LINK_WIDTH_8:
285 hw->bus.width = ixgbe_bus_width_pcie_x8;
288 hw->bus.width = ixgbe_bus_width_unknown;
292 switch (link_status & IXGBE_PCI_LINK_SPEED) {
293 case IXGBE_PCI_LINK_SPEED_2500:
294 hw->bus.speed = ixgbe_bus_speed_2500;
296 case IXGBE_PCI_LINK_SPEED_5000:
297 hw->bus.speed = ixgbe_bus_speed_5000;
300 hw->bus.speed = ixgbe_bus_speed_unknown;
304 mac->ops.set_lan_id(hw);
310 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
311 * @hw: pointer to the HW structure
313 * Determines the LAN function id by reading memory-mapped registers
314 * and swaps the port value if requested.
316 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
318 struct ixgbe_bus_info *bus = &hw->bus;
321 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
322 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
323 bus->lan_id = bus->func;
325 /* check for a port swap */
326 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
327 if (reg & IXGBE_FACTPS_LFS)
332 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
333 * @hw: pointer to hardware structure
335 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
336 * disables transmit and receive units. The adapter_stopped flag is used by
337 * the shared code and drivers to determine if the adapter is in a stopped
338 * state and should not touch the hardware.
340 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
342 u32 number_of_queues;
347 * Set the adapter_stopped flag so other driver functions stop touching
350 hw->adapter_stopped = true;
352 /* Disable the receive unit */
353 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
354 reg_val &= ~(IXGBE_RXCTRL_RXEN);
355 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
356 IXGBE_WRITE_FLUSH(hw);
359 /* Clear interrupt mask to stop from interrupts being generated */
360 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
362 /* Clear any pending interrupts */
363 IXGBE_READ_REG(hw, IXGBE_EICR);
365 /* Disable the transmit unit. Each queue must be disabled. */
366 number_of_queues = hw->mac.max_tx_queues;
367 for (i = 0; i < number_of_queues; i++) {
368 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
369 if (reg_val & IXGBE_TXDCTL_ENABLE) {
370 reg_val &= ~IXGBE_TXDCTL_ENABLE;
371 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val);
376 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
377 * access and verify no pending requests
379 if (ixgbe_disable_pcie_master(hw) != 0)
380 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
386 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
387 * @hw: pointer to hardware structure
388 * @index: led number to turn on
390 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
392 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
394 /* To turn on the LED, set mode to ON. */
395 led_reg &= ~IXGBE_LED_MODE_MASK(index);
396 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
397 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
398 IXGBE_WRITE_FLUSH(hw);
404 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
405 * @hw: pointer to hardware structure
406 * @index: led number to turn off
408 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
410 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
412 /* To turn off the LED, set mode to OFF. */
413 led_reg &= ~IXGBE_LED_MODE_MASK(index);
414 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
415 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
416 IXGBE_WRITE_FLUSH(hw);
422 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
423 * @hw: pointer to hardware structure
425 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
426 * ixgbe_hw struct in order to set up EEPROM access.
428 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
430 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
434 if (eeprom->type == ixgbe_eeprom_uninitialized) {
435 eeprom->type = ixgbe_eeprom_none;
436 /* Set default semaphore delay to 10ms which is a well
438 eeprom->semaphore_delay = 10;
441 * Check for EEPROM present first.
442 * If not present leave as none
444 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
445 if (eec & IXGBE_EEC_PRES) {
446 eeprom->type = ixgbe_eeprom_spi;
449 * SPI EEPROM is assumed here. This code would need to
450 * change if a future EEPROM is not SPI.
452 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
453 IXGBE_EEC_SIZE_SHIFT);
454 eeprom->word_size = 1 << (eeprom_size +
455 IXGBE_EEPROM_WORD_SIZE_SHIFT);
458 if (eec & IXGBE_EEC_ADDR_SIZE)
459 eeprom->address_bits = 16;
461 eeprom->address_bits = 8;
462 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
463 "%d\n", eeprom->type, eeprom->word_size,
464 eeprom->address_bits);
471 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
472 * @hw: pointer to hardware structure
473 * @offset: offset within the EEPROM to be written to
474 * @data: 16 bit word to be written to the EEPROM
476 * If ixgbe_eeprom_update_checksum is not called after this function, the
477 * EEPROM will most likely contain an invalid checksum.
479 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
482 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
484 hw->eeprom.ops.init_params(hw);
486 if (offset >= hw->eeprom.word_size) {
487 status = IXGBE_ERR_EEPROM;
491 /* Prepare the EEPROM for writing */
492 status = ixgbe_acquire_eeprom(hw);
495 if (ixgbe_ready_eeprom(hw) != 0) {
496 ixgbe_release_eeprom(hw);
497 status = IXGBE_ERR_EEPROM;
502 ixgbe_standby_eeprom(hw);
504 /* Send the WRITE ENABLE command (8 bit opcode ) */
505 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI,
506 IXGBE_EEPROM_OPCODE_BITS);
508 ixgbe_standby_eeprom(hw);
511 * Some SPI eeproms use the 8th address bit embedded in the
514 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
515 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
517 /* Send the Write command (8-bit opcode + addr) */
518 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
519 IXGBE_EEPROM_OPCODE_BITS);
520 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
521 hw->eeprom.address_bits);
524 data = (data >> 8) | (data << 8);
525 ixgbe_shift_out_eeprom_bits(hw, data, 16);
526 ixgbe_standby_eeprom(hw);
528 msleep(hw->eeprom.semaphore_delay);
529 /* Done with writing - release the EEPROM */
530 ixgbe_release_eeprom(hw);
538 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
539 * @hw: pointer to hardware structure
540 * @offset: offset within the EEPROM to be read
541 * @data: read 16 bit value from EEPROM
543 * Reads 16 bit value from EEPROM through bit-bang method
545 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
550 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
552 hw->eeprom.ops.init_params(hw);
554 if (offset >= hw->eeprom.word_size) {
555 status = IXGBE_ERR_EEPROM;
559 /* Prepare the EEPROM for reading */
560 status = ixgbe_acquire_eeprom(hw);
563 if (ixgbe_ready_eeprom(hw) != 0) {
564 ixgbe_release_eeprom(hw);
565 status = IXGBE_ERR_EEPROM;
570 ixgbe_standby_eeprom(hw);
573 * Some SPI eeproms use the 8th address bit embedded in the
576 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
577 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
579 /* Send the READ command (opcode + addr) */
580 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
581 IXGBE_EEPROM_OPCODE_BITS);
582 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
583 hw->eeprom.address_bits);
586 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
587 *data = (word_in >> 8) | (word_in << 8);
589 /* End this read operation */
590 ixgbe_release_eeprom(hw);
598 * ixgbe_read_eeprom_generic - Read EEPROM word using EERD
599 * @hw: pointer to hardware structure
600 * @offset: offset of word in the EEPROM to read
601 * @data: word read from the EEPROM
603 * Reads a 16 bit word from the EEPROM using the EERD register.
605 s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
610 hw->eeprom.ops.init_params(hw);
612 if (offset >= hw->eeprom.word_size) {
613 status = IXGBE_ERR_EEPROM;
617 eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) +
618 IXGBE_EEPROM_READ_REG_START;
620 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
621 status = ixgbe_poll_eeprom_eerd_done(hw);
624 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
625 IXGBE_EEPROM_READ_REG_DATA);
627 hw_dbg(hw, "Eeprom read timed out\n");
634 * ixgbe_poll_eeprom_eerd_done - Poll EERD status
635 * @hw: pointer to hardware structure
637 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
639 static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw)
643 s32 status = IXGBE_ERR_EEPROM;
645 for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) {
646 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
647 if (reg & IXGBE_EEPROM_READ_REG_DONE) {
657 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
658 * @hw: pointer to hardware structure
660 * Prepares EEPROM for access using bit-bang method. This function should
661 * be called before issuing a command to the EEPROM.
663 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
669 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
670 status = IXGBE_ERR_SWFW_SYNC;
673 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
675 /* Request EEPROM Access */
676 eec |= IXGBE_EEC_REQ;
677 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
679 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
680 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
681 if (eec & IXGBE_EEC_GNT)
686 /* Release if grant not acquired */
687 if (!(eec & IXGBE_EEC_GNT)) {
688 eec &= ~IXGBE_EEC_REQ;
689 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
690 hw_dbg(hw, "Could not acquire EEPROM grant\n");
692 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
693 status = IXGBE_ERR_EEPROM;
697 /* Setup EEPROM for Read/Write */
699 /* Clear CS and SK */
700 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
701 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
702 IXGBE_WRITE_FLUSH(hw);
709 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
710 * @hw: pointer to hardware structure
712 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
714 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
716 s32 status = IXGBE_ERR_EEPROM;
721 /* Set timeout value based on size of EEPROM */
722 timeout = hw->eeprom.word_size + 1;
724 /* Get SMBI software semaphore between device drivers first */
725 for (i = 0; i < timeout; i++) {
727 * If the SMBI bit is 0 when we read it, then the bit will be
728 * set and we have the semaphore
730 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
731 if (!(swsm & IXGBE_SWSM_SMBI)) {
738 /* Now get the semaphore between SW/FW through the SWESMBI bit */
740 for (i = 0; i < timeout; i++) {
741 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
743 /* Set the SW EEPROM semaphore bit to request access */
744 swsm |= IXGBE_SWSM_SWESMBI;
745 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
748 * If we set the bit successfully then we got the
751 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
752 if (swsm & IXGBE_SWSM_SWESMBI)
759 * Release semaphores and return error if SW EEPROM semaphore
760 * was not granted because we don't have access to the EEPROM
763 hw_dbg(hw, "Driver can't access the Eeprom - Semaphore "
765 ixgbe_release_eeprom_semaphore(hw);
766 status = IXGBE_ERR_EEPROM;
774 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
775 * @hw: pointer to hardware structure
777 * This function clears hardware semaphore bits.
779 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
783 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
785 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
786 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
787 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
788 IXGBE_WRITE_FLUSH(hw);
792 * ixgbe_ready_eeprom - Polls for EEPROM ready
793 * @hw: pointer to hardware structure
795 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
802 * Read "Status Register" repeatedly until the LSB is cleared. The
803 * EEPROM will signal that the command has been completed by clearing
804 * bit 0 of the internal status register. If it's not cleared within
805 * 5 milliseconds, then error out.
807 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
808 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
809 IXGBE_EEPROM_OPCODE_BITS);
810 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
811 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
815 ixgbe_standby_eeprom(hw);
819 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
820 * devices (and only 0-5mSec on 5V devices)
822 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
823 hw_dbg(hw, "SPI EEPROM Status error\n");
824 status = IXGBE_ERR_EEPROM;
831 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
832 * @hw: pointer to hardware structure
834 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
838 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
840 /* Toggle CS to flush commands */
842 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
843 IXGBE_WRITE_FLUSH(hw);
845 eec &= ~IXGBE_EEC_CS;
846 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
847 IXGBE_WRITE_FLUSH(hw);
852 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
853 * @hw: pointer to hardware structure
854 * @data: data to send to the EEPROM
855 * @count: number of bits to shift out
857 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
864 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
867 * Mask is used to shift "count" bits of "data" out to the EEPROM
868 * one bit at a time. Determine the starting bit based on count
870 mask = 0x01 << (count - 1);
872 for (i = 0; i < count; i++) {
874 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
875 * "1", and then raising and then lowering the clock (the SK
876 * bit controls the clock input to the EEPROM). A "0" is
877 * shifted out to the EEPROM by setting "DI" to "0" and then
878 * raising and then lowering the clock.
883 eec &= ~IXGBE_EEC_DI;
885 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
886 IXGBE_WRITE_FLUSH(hw);
890 ixgbe_raise_eeprom_clk(hw, &eec);
891 ixgbe_lower_eeprom_clk(hw, &eec);
894 * Shift mask to signify next bit of data to shift in to the
900 /* We leave the "DI" bit set to "0" when we leave this routine. */
901 eec &= ~IXGBE_EEC_DI;
902 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
903 IXGBE_WRITE_FLUSH(hw);
907 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
908 * @hw: pointer to hardware structure
910 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
917 * In order to read a register from the EEPROM, we need to shift
918 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
919 * the clock input to the EEPROM (setting the SK bit), and then reading
920 * the value of the "DO" bit. During this "shifting in" process the
921 * "DI" bit should always be clear.
923 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
925 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
927 for (i = 0; i < count; i++) {
929 ixgbe_raise_eeprom_clk(hw, &eec);
931 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
933 eec &= ~(IXGBE_EEC_DI);
934 if (eec & IXGBE_EEC_DO)
937 ixgbe_lower_eeprom_clk(hw, &eec);
944 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
945 * @hw: pointer to hardware structure
946 * @eec: EEC register's current value
948 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
951 * Raise the clock input to the EEPROM
952 * (setting the SK bit), then delay
954 *eec = *eec | IXGBE_EEC_SK;
955 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
956 IXGBE_WRITE_FLUSH(hw);
961 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
962 * @hw: pointer to hardware structure
963 * @eecd: EECD's current value
965 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
968 * Lower the clock input to the EEPROM (clearing the SK bit), then
971 *eec = *eec & ~IXGBE_EEC_SK;
972 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
973 IXGBE_WRITE_FLUSH(hw);
978 * ixgbe_release_eeprom - Release EEPROM, release semaphores
979 * @hw: pointer to hardware structure
981 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
985 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
987 eec |= IXGBE_EEC_CS; /* Pull CS high */
988 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
990 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
991 IXGBE_WRITE_FLUSH(hw);
995 /* Stop requesting EEPROM access */
996 eec &= ~IXGBE_EEC_REQ;
997 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
999 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1003 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum
1004 * @hw: pointer to hardware structure
1006 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw)
1015 /* Include 0x0-0x3F in the checksum */
1016 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
1017 if (hw->eeprom.ops.read(hw, i, &word) != 0) {
1018 hw_dbg(hw, "EEPROM read failed\n");
1024 /* Include all data from pointers except for the fw pointer */
1025 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
1026 hw->eeprom.ops.read(hw, i, &pointer);
1028 /* Make sure the pointer seems valid */
1029 if (pointer != 0xFFFF && pointer != 0) {
1030 hw->eeprom.ops.read(hw, pointer, &length);
1032 if (length != 0xFFFF && length != 0) {
1033 for (j = pointer+1; j <= pointer+length; j++) {
1034 hw->eeprom.ops.read(hw, j, &word);
1041 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1047 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
1048 * @hw: pointer to hardware structure
1049 * @checksum_val: calculated checksum
1051 * Performs checksum calculation and validates the EEPROM checksum. If the
1052 * caller does not need checksum_val, the value can be NULL.
1054 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1059 u16 read_checksum = 0;
1062 * Read the first word from the EEPROM. If this times out or fails, do
1063 * not continue or we could be in for a very long wait while every
1066 status = hw->eeprom.ops.read(hw, 0, &checksum);
1069 checksum = ixgbe_calc_eeprom_checksum(hw);
1071 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
1074 * Verify read checksum from EEPROM is the same as
1075 * calculated checksum
1077 if (read_checksum != checksum)
1078 status = IXGBE_ERR_EEPROM_CHECKSUM;
1080 /* If the user cares, return the calculated checksum */
1082 *checksum_val = checksum;
1084 hw_dbg(hw, "EEPROM read failed\n");
1091 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1092 * @hw: pointer to hardware structure
1094 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1100 * Read the first word from the EEPROM. If this times out or fails, do
1101 * not continue or we could be in for a very long wait while every
1104 status = hw->eeprom.ops.read(hw, 0, &checksum);
1107 checksum = ixgbe_calc_eeprom_checksum(hw);
1108 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1111 hw_dbg(hw, "EEPROM read failed\n");
1118 * ixgbe_validate_mac_addr - Validate MAC address
1119 * @mac_addr: pointer to MAC address.
1121 * Tests a MAC address to ensure it is a valid Individual Address
1123 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1127 /* Make sure it is not a multicast address */
1128 if (IXGBE_IS_MULTICAST(mac_addr))
1129 status = IXGBE_ERR_INVALID_MAC_ADDR;
1130 /* Not a broadcast address */
1131 else if (IXGBE_IS_BROADCAST(mac_addr))
1132 status = IXGBE_ERR_INVALID_MAC_ADDR;
1133 /* Reject the zero address */
1134 else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
1135 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)
1136 status = IXGBE_ERR_INVALID_MAC_ADDR;
1142 * ixgbe_set_rar_generic - Set Rx address register
1143 * @hw: pointer to hardware structure
1144 * @index: Receive address register to write
1145 * @addr: Address to put into receive address register
1146 * @vmdq: VMDq "set" or "pool" index
1147 * @enable_addr: set flag that address is active
1149 * Puts an ethernet address into a receive address register.
1151 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1154 u32 rar_low, rar_high;
1155 u32 rar_entries = hw->mac.num_rar_entries;
1157 /* setup VMDq pool selection before this RAR gets enabled */
1158 hw->mac.ops.set_vmdq(hw, index, vmdq);
1160 /* Make sure we are using a valid rar index range */
1161 if (index < rar_entries) {
1163 * HW expects these in little endian so we reverse the byte
1164 * order from network order (big endian) to little endian
1166 rar_low = ((u32)addr[0] |
1167 ((u32)addr[1] << 8) |
1168 ((u32)addr[2] << 16) |
1169 ((u32)addr[3] << 24));
1171 * Some parts put the VMDq setting in the extra RAH bits,
1172 * so save everything except the lower 16 bits that hold part
1173 * of the address and the address valid bit.
1175 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1176 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1177 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
1179 if (enable_addr != 0)
1180 rar_high |= IXGBE_RAH_AV;
1182 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1183 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1185 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1192 * ixgbe_clear_rar_generic - Remove Rx address register
1193 * @hw: pointer to hardware structure
1194 * @index: Receive address register to write
1196 * Clears an ethernet address from a receive address register.
1198 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1201 u32 rar_entries = hw->mac.num_rar_entries;
1203 /* Make sure we are using a valid rar index range */
1204 if (index < rar_entries) {
1206 * Some parts put the VMDq setting in the extra RAH bits,
1207 * so save everything except the lower 16 bits that hold part
1208 * of the address and the address valid bit.
1210 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1211 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1213 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1214 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1216 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1219 /* clear VMDq pool/queue selection for this RAR */
1220 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
1226 * ixgbe_enable_rar - Enable Rx address register
1227 * @hw: pointer to hardware structure
1228 * @index: index into the RAR table
1230 * Enables the select receive address register.
1232 static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index)
1236 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1237 rar_high |= IXGBE_RAH_AV;
1238 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1242 * ixgbe_disable_rar - Disable Rx address register
1243 * @hw: pointer to hardware structure
1244 * @index: index into the RAR table
1246 * Disables the select receive address register.
1248 static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index)
1252 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1253 rar_high &= (~IXGBE_RAH_AV);
1254 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1258 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
1259 * @hw: pointer to hardware structure
1261 * Places the MAC address in receive address register 0 and clears the rest
1262 * of the receive address registers. Clears the multicast table. Assumes
1263 * the receiver is in reset when the routine is called.
1265 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
1268 u32 rar_entries = hw->mac.num_rar_entries;
1271 * If the current mac address is valid, assume it is a software override
1272 * to the permanent address.
1273 * Otherwise, use the permanent address from the eeprom.
1275 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
1276 IXGBE_ERR_INVALID_MAC_ADDR) {
1277 /* Get the MAC address from the RAR0 for later reference */
1278 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
1280 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
1282 /* Setup the receive address. */
1283 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
1284 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
1286 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1288 hw->addr_ctrl.overflow_promisc = 0;
1290 hw->addr_ctrl.rar_used_count = 1;
1292 /* Zero out the other receive addresses. */
1293 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
1294 for (i = 1; i < rar_entries; i++) {
1295 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1296 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1300 hw->addr_ctrl.mc_addr_in_rar_count = 0;
1301 hw->addr_ctrl.mta_in_use = 0;
1302 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1304 hw_dbg(hw, " Clearing MTA\n");
1305 for (i = 0; i < hw->mac.mcft_size; i++)
1306 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1308 if (hw->mac.ops.init_uta_tables)
1309 hw->mac.ops.init_uta_tables(hw);
1315 * ixgbe_add_uc_addr - Adds a secondary unicast address.
1316 * @hw: pointer to hardware structure
1317 * @addr: new address
1319 * Adds it to unused receive address register or goes into promiscuous mode.
1321 static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
1323 u32 rar_entries = hw->mac.num_rar_entries;
1326 hw_dbg(hw, " UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
1327 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
1330 * Place this address in the RAR if there is room,
1331 * else put the controller into promiscuous mode
1333 if (hw->addr_ctrl.rar_used_count < rar_entries) {
1334 rar = hw->addr_ctrl.rar_used_count -
1335 hw->addr_ctrl.mc_addr_in_rar_count;
1336 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
1337 hw_dbg(hw, "Added a secondary address to RAR[%d]\n", rar);
1338 hw->addr_ctrl.rar_used_count++;
1340 hw->addr_ctrl.overflow_promisc++;
1343 hw_dbg(hw, "ixgbe_add_uc_addr Complete\n");
1347 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
1348 * @hw: pointer to hardware structure
1349 * @netdev: pointer to net device structure
1351 * The given list replaces any existing list. Clears the secondary addrs from
1352 * receive address registers. Uses unused receive address registers for the
1353 * first secondary addresses, and falls back to promiscuous mode as needed.
1355 * Drivers using secondary unicast addresses must set user_set_promisc when
1356 * manually putting the device into promiscuous mode.
1358 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw,
1359 struct net_device *netdev)
1362 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
1365 struct netdev_hw_addr *ha;
1368 * Clear accounting of old secondary address list,
1369 * don't count RAR[0]
1371 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
1372 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
1373 hw->addr_ctrl.overflow_promisc = 0;
1375 /* Zero out the other receive addresses */
1376 hw_dbg(hw, "Clearing RAR[1-%d]\n", uc_addr_in_use + 1);
1377 for (i = 0; i < uc_addr_in_use; i++) {
1378 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
1379 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
1382 /* Add the new addresses */
1383 netdev_for_each_uc_addr(ha, netdev) {
1384 hw_dbg(hw, " Adding the secondary addresses:\n");
1385 ixgbe_add_uc_addr(hw, ha->addr, 0);
1388 if (hw->addr_ctrl.overflow_promisc) {
1389 /* enable promisc if not already in overflow or set by user */
1390 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1391 hw_dbg(hw, " Entering address overflow promisc mode\n");
1392 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1393 fctrl |= IXGBE_FCTRL_UPE;
1394 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1397 /* only disable if set by overflow, not by user */
1398 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1399 hw_dbg(hw, " Leaving address overflow promisc mode\n");
1400 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1401 fctrl &= ~IXGBE_FCTRL_UPE;
1402 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1406 hw_dbg(hw, "ixgbe_update_uc_addr_list_generic Complete\n");
1411 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1412 * @hw: pointer to hardware structure
1413 * @mc_addr: the multicast address
1415 * Extracts the 12 bits, from a multicast address, to determine which
1416 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1417 * incoming rx multicast addresses, to determine the bit-vector to check in
1418 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
1419 * by the MO field of the MCSTCTRL. The MO field is set during initialization
1420 * to mc_filter_type.
1422 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1426 switch (hw->mac.mc_filter_type) {
1427 case 0: /* use bits [47:36] of the address */
1428 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1430 case 1: /* use bits [46:35] of the address */
1431 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1433 case 2: /* use bits [45:34] of the address */
1434 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1436 case 3: /* use bits [43:32] of the address */
1437 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1439 default: /* Invalid mc_filter_type */
1440 hw_dbg(hw, "MC filter type param set incorrectly\n");
1444 /* vector can only be 12-bits or boundary will be exceeded */
1450 * ixgbe_set_mta - Set bit-vector in multicast table
1451 * @hw: pointer to hardware structure
1452 * @hash_value: Multicast address hash value
1454 * Sets the bit-vector in the multicast table.
1456 static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1463 hw->addr_ctrl.mta_in_use++;
1465 vector = ixgbe_mta_vector(hw, mc_addr);
1466 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
1469 * The MTA is a register array of 128 32-bit registers. It is treated
1470 * like an array of 4096 bits. We want to set bit
1471 * BitArray[vector_value]. So we figure out what register the bit is
1472 * in, read it, OR in the new bit, then write back the new value. The
1473 * register is determined by the upper 7 bits of the vector value and
1474 * the bit within that register are determined by the lower 5 bits of
1477 vector_reg = (vector >> 5) & 0x7F;
1478 vector_bit = vector & 0x1F;
1479 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg));
1480 mta_reg |= (1 << vector_bit);
1481 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg);
1485 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
1486 * @hw: pointer to hardware structure
1487 * @netdev: pointer to net device structure
1489 * The given list replaces any existing list. Clears the MC addrs from receive
1490 * address registers and the multicast table. Uses unused receive address
1491 * registers for the first multicast addresses, and hashes the rest into the
1494 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
1495 struct net_device *netdev)
1497 struct netdev_hw_addr *ha;
1501 * Set the new number of MC addresses that we are being requested to
1504 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
1505 hw->addr_ctrl.mta_in_use = 0;
1508 hw_dbg(hw, " Clearing MTA\n");
1509 for (i = 0; i < hw->mac.mcft_size; i++)
1510 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1512 /* Add the new addresses */
1513 netdev_for_each_mc_addr(ha, netdev) {
1514 hw_dbg(hw, " Adding the multicast addresses:\n");
1515 ixgbe_set_mta(hw, ha->addr);
1519 if (hw->addr_ctrl.mta_in_use > 0)
1520 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
1521 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
1523 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
1528 * ixgbe_enable_mc_generic - Enable multicast address in RAR
1529 * @hw: pointer to hardware structure
1531 * Enables multicast address in RAR and the use of the multicast hash table.
1533 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
1536 u32 rar_entries = hw->mac.num_rar_entries;
1537 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
1539 if (a->mc_addr_in_rar_count > 0)
1540 for (i = (rar_entries - a->mc_addr_in_rar_count);
1541 i < rar_entries; i++)
1542 ixgbe_enable_rar(hw, i);
1544 if (a->mta_in_use > 0)
1545 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
1546 hw->mac.mc_filter_type);
1552 * ixgbe_disable_mc_generic - Disable multicast address in RAR
1553 * @hw: pointer to hardware structure
1555 * Disables multicast address in RAR and the use of the multicast hash table.
1557 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
1560 u32 rar_entries = hw->mac.num_rar_entries;
1561 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
1563 if (a->mc_addr_in_rar_count > 0)
1564 for (i = (rar_entries - a->mc_addr_in_rar_count);
1565 i < rar_entries; i++)
1566 ixgbe_disable_rar(hw, i);
1568 if (a->mta_in_use > 0)
1569 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1575 * ixgbe_fc_enable_generic - Enable flow control
1576 * @hw: pointer to hardware structure
1577 * @packetbuf_num: packet buffer number (0-7)
1579 * Enable flow control according to the current settings.
1581 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
1584 u32 mflcn_reg, fccfg_reg;
1589 if (hw->fc.requested_mode == ixgbe_fc_pfc)
1592 #endif /* CONFIG_DCB */
1593 /* Negotiate the fc mode to use */
1594 ret_val = ixgbe_fc_autoneg(hw);
1598 /* Disable any previous flow control settings */
1599 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
1600 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE);
1602 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
1603 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
1606 * The possible values of fc.current_mode are:
1607 * 0: Flow control is completely disabled
1608 * 1: Rx flow control is enabled (we can receive pause frames,
1609 * but not send pause frames).
1610 * 2: Tx flow control is enabled (we can send pause frames but
1611 * we do not support receiving pause frames).
1612 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1613 * 4: Priority Flow Control is enabled.
1616 switch (hw->fc.current_mode) {
1619 * Flow control is disabled by software override or autoneg.
1620 * The code below will actually disable it in the HW.
1623 case ixgbe_fc_rx_pause:
1625 * Rx Flow control is enabled and Tx Flow control is
1626 * disabled by software override. Since there really
1627 * isn't a way to advertise that we are capable of RX
1628 * Pause ONLY, we will advertise that we support both
1629 * symmetric and asymmetric Rx PAUSE. Later, we will
1630 * disable the adapter's ability to send PAUSE frames.
1632 mflcn_reg |= IXGBE_MFLCN_RFCE;
1634 case ixgbe_fc_tx_pause:
1636 * Tx Flow control is enabled, and Rx Flow control is
1637 * disabled by software override.
1639 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1642 /* Flow control (both Rx and Tx) is enabled by SW override. */
1643 mflcn_reg |= IXGBE_MFLCN_RFCE;
1644 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1650 #endif /* CONFIG_DCB */
1652 hw_dbg(hw, "Flow control param set incorrectly\n");
1653 ret_val = IXGBE_ERR_CONFIG;
1658 /* Set 802.3x based flow control settings. */
1659 mflcn_reg |= IXGBE_MFLCN_DPF;
1660 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
1661 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
1663 reg = IXGBE_READ_REG(hw, IXGBE_MTQC);
1664 /* Thresholds are different for link flow control when in DCB mode */
1665 if (reg & IXGBE_MTQC_RT_ENA) {
1666 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
1668 /* Always disable XON for LFC when in DCB mode */
1669 reg = (rx_pba_size >> 5) & 0xFFE0;
1670 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), reg);
1672 reg = (rx_pba_size >> 2) & 0xFFE0;
1673 if (hw->fc.current_mode & ixgbe_fc_tx_pause)
1674 reg |= IXGBE_FCRTH_FCEN;
1675 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), reg);
1678 * Set up and enable Rx high/low water mark thresholds,
1681 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
1682 if (hw->fc.send_xon) {
1684 IXGBE_FCRTL_82599(packetbuf_num),
1689 IXGBE_FCRTL_82599(packetbuf_num),
1693 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num),
1694 (hw->fc.high_water | IXGBE_FCRTH_FCEN));
1698 /* Configure pause time (2 TCs per register) */
1699 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
1700 if ((packetbuf_num & 1) == 0)
1701 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
1703 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
1704 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
1706 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
1713 * ixgbe_fc_autoneg - Configure flow control
1714 * @hw: pointer to hardware structure
1716 * Compares our advertised flow control capabilities to those advertised by
1717 * our link partner, and determines the proper flow control mode to use.
1719 s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
1722 ixgbe_link_speed speed;
1723 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
1724 u32 links2, anlp1_reg, autoc_reg, links;
1728 * AN should have completed when the cable was plugged in.
1729 * Look for reasons to bail out. Bail out if:
1730 * - FC autoneg is disabled, or if
1733 * Since we're being called from an LSC, link is already known to be up.
1734 * So use link_up_wait_to_complete=false.
1736 hw->mac.ops.check_link(hw, &speed, &link_up, false);
1738 if (hw->fc.disable_fc_autoneg || (!link_up)) {
1739 hw->fc.fc_was_autonegged = false;
1740 hw->fc.current_mode = hw->fc.requested_mode;
1745 * On backplane, bail out if
1746 * - backplane autoneg was not completed, or if
1747 * - we are 82599 and link partner is not AN enabled
1749 if (hw->phy.media_type == ixgbe_media_type_backplane) {
1750 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
1751 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
1752 hw->fc.fc_was_autonegged = false;
1753 hw->fc.current_mode = hw->fc.requested_mode;
1757 if (hw->mac.type == ixgbe_mac_82599EB) {
1758 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
1759 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
1760 hw->fc.fc_was_autonegged = false;
1761 hw->fc.current_mode = hw->fc.requested_mode;
1768 * On multispeed fiber at 1g, bail out if
1769 * - link is up but AN did not complete, or if
1770 * - link is up and AN completed but timed out
1772 if (hw->phy.multispeed_fiber && (speed == IXGBE_LINK_SPEED_1GB_FULL)) {
1773 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
1774 if (((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
1775 ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
1776 hw->fc.fc_was_autonegged = false;
1777 hw->fc.current_mode = hw->fc.requested_mode;
1784 * - copper or CX4 adapters
1785 * - fiber adapters running at 10gig
1787 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
1788 (hw->phy.media_type == ixgbe_media_type_cx4) ||
1789 ((hw->phy.media_type == ixgbe_media_type_fiber) &&
1790 (speed == IXGBE_LINK_SPEED_10GB_FULL))) {
1791 hw->fc.fc_was_autonegged = false;
1792 hw->fc.current_mode = hw->fc.requested_mode;
1797 * Read the AN advertisement and LP ability registers and resolve
1798 * local flow control settings accordingly
1800 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
1801 (hw->phy.media_type != ixgbe_media_type_backplane)) {
1802 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
1803 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
1804 if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1805 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) {
1807 * Now we need to check if the user selected Rx ONLY
1808 * of pause frames. In this case, we had to advertise
1809 * FULL flow control because we could not advertise RX
1810 * ONLY. Hence, we must now check to see if we need to
1811 * turn OFF the TRANSMISSION of PAUSE frames.
1813 if (hw->fc.requested_mode == ixgbe_fc_full) {
1814 hw->fc.current_mode = ixgbe_fc_full;
1815 hw_dbg(hw, "Flow Control = FULL.\n");
1817 hw->fc.current_mode = ixgbe_fc_rx_pause;
1818 hw_dbg(hw, "Flow Control=RX PAUSE only\n");
1820 } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1821 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1822 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1823 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1824 hw->fc.current_mode = ixgbe_fc_tx_pause;
1825 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
1826 } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1827 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1828 !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1829 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1830 hw->fc.current_mode = ixgbe_fc_rx_pause;
1831 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
1833 hw->fc.current_mode = ixgbe_fc_none;
1834 hw_dbg(hw, "Flow Control = NONE.\n");
1838 if (hw->phy.media_type == ixgbe_media_type_backplane) {
1840 * Read the 10g AN autoc and LP ability registers and resolve
1841 * local flow control settings accordingly
1843 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1844 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
1846 if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
1847 (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE)) {
1849 * Now we need to check if the user selected Rx ONLY
1850 * of pause frames. In this case, we had to advertise
1851 * FULL flow control because we could not advertise RX
1852 * ONLY. Hence, we must now check to see if we need to
1853 * turn OFF the TRANSMISSION of PAUSE frames.
1855 if (hw->fc.requested_mode == ixgbe_fc_full) {
1856 hw->fc.current_mode = ixgbe_fc_full;
1857 hw_dbg(hw, "Flow Control = FULL.\n");
1859 hw->fc.current_mode = ixgbe_fc_rx_pause;
1860 hw_dbg(hw, "Flow Control=RX PAUSE only\n");
1862 } else if (!(autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
1863 (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) &&
1864 (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) &&
1865 (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) {
1866 hw->fc.current_mode = ixgbe_fc_tx_pause;
1867 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
1868 } else if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
1869 (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) &&
1870 !(anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) &&
1871 (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) {
1872 hw->fc.current_mode = ixgbe_fc_rx_pause;
1873 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
1875 hw->fc.current_mode = ixgbe_fc_none;
1876 hw_dbg(hw, "Flow Control = NONE.\n");
1879 /* Record that current_mode is the result of a successful autoneg */
1880 hw->fc.fc_was_autonegged = true;
1887 * ixgbe_setup_fc - Set up flow control
1888 * @hw: pointer to hardware structure
1890 * Called at init time to set up flow control.
1892 static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
1898 if (hw->fc.requested_mode == ixgbe_fc_pfc) {
1899 hw->fc.current_mode = hw->fc.requested_mode;
1904 /* Validate the packetbuf configuration */
1905 if (packetbuf_num < 0 || packetbuf_num > 7) {
1906 hw_dbg(hw, "Invalid packet buffer number [%d], expected range "
1907 "is 0-7\n", packetbuf_num);
1908 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1913 * Validate the water mark configuration. Zero water marks are invalid
1914 * because it causes the controller to just blast out fc packets.
1916 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
1917 hw_dbg(hw, "Invalid water mark configuration\n");
1918 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1923 * Validate the requested mode. Strict IEEE mode does not allow
1924 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
1926 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
1927 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict "
1929 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1934 * 10gig parts do not have a word in the EEPROM to determine the
1935 * default flow control setting, so we explicitly set it to full.
1937 if (hw->fc.requested_mode == ixgbe_fc_default)
1938 hw->fc.requested_mode = ixgbe_fc_full;
1941 * Set up the 1G flow control advertisement registers so the HW will be
1942 * able to do fc autoneg once the cable is plugged in. If we end up
1943 * using 10g instead, this is harmless.
1945 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
1948 * The possible values of fc.requested_mode are:
1949 * 0: Flow control is completely disabled
1950 * 1: Rx flow control is enabled (we can receive pause frames,
1951 * but not send pause frames).
1952 * 2: Tx flow control is enabled (we can send pause frames but
1953 * we do not support receiving pause frames).
1954 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1956 * 4: Priority Flow Control is enabled.
1960 switch (hw->fc.requested_mode) {
1962 /* Flow control completely disabled by software override. */
1963 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1965 case ixgbe_fc_rx_pause:
1967 * Rx Flow control is enabled and Tx Flow control is
1968 * disabled by software override. Since there really
1969 * isn't a way to advertise that we are capable of RX
1970 * Pause ONLY, we will advertise that we support both
1971 * symmetric and asymmetric Rx PAUSE. Later, we will
1972 * disable the adapter's ability to send PAUSE frames.
1974 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1976 case ixgbe_fc_tx_pause:
1978 * Tx Flow control is enabled, and Rx Flow control is
1979 * disabled by software override.
1981 reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
1982 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
1985 /* Flow control (both Rx and Tx) is enabled by SW override. */
1986 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1992 #endif /* CONFIG_DCB */
1994 hw_dbg(hw, "Flow control param set incorrectly\n");
1995 ret_val = IXGBE_ERR_CONFIG;
2000 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
2001 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
2003 /* Disable AN timeout */
2004 if (hw->fc.strict_ieee)
2005 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
2007 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
2008 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
2011 * Set up the 10G flow control advertisement registers so the HW
2012 * can do fc autoneg once the cable is plugged in. If we end up
2013 * using 1g instead, this is harmless.
2015 reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2018 * The possible values of fc.requested_mode are:
2019 * 0: Flow control is completely disabled
2020 * 1: Rx flow control is enabled (we can receive pause frames,
2021 * but not send pause frames).
2022 * 2: Tx flow control is enabled (we can send pause frames but
2023 * we do not support receiving pause frames).
2024 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2027 switch (hw->fc.requested_mode) {
2029 /* Flow control completely disabled by software override. */
2030 reg &= ~(IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
2032 case ixgbe_fc_rx_pause:
2034 * Rx Flow control is enabled and Tx Flow control is
2035 * disabled by software override. Since there really
2036 * isn't a way to advertise that we are capable of RX
2037 * Pause ONLY, we will advertise that we support both
2038 * symmetric and asymmetric Rx PAUSE. Later, we will
2039 * disable the adapter's ability to send PAUSE frames.
2041 reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
2043 case ixgbe_fc_tx_pause:
2045 * Tx Flow control is enabled, and Rx Flow control is
2046 * disabled by software override.
2048 reg |= (IXGBE_AUTOC_ASM_PAUSE);
2049 reg &= ~(IXGBE_AUTOC_SYM_PAUSE);
2052 /* Flow control (both Rx and Tx) is enabled by SW override. */
2053 reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
2059 #endif /* CONFIG_DCB */
2061 hw_dbg(hw, "Flow control param set incorrectly\n");
2062 ret_val = IXGBE_ERR_CONFIG;
2067 * AUTOC restart handles negotiation of 1G and 10G. There is
2068 * no need to set the PCS1GCTL register.
2070 reg |= IXGBE_AUTOC_AN_RESTART;
2071 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg);
2072 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
2079 * ixgbe_disable_pcie_master - Disable PCI-express master access
2080 * @hw: pointer to hardware structure
2082 * Disables PCI-Express master access and verifies there are no pending
2083 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2084 * bit hasn't caused the master requests to be disabled, else 0
2085 * is returned signifying master requests disabled.
2087 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2091 u32 number_of_queues;
2092 s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
2094 /* Disable the receive unit by stopping each queue */
2095 number_of_queues = hw->mac.max_rx_queues;
2096 for (i = 0; i < number_of_queues; i++) {
2097 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
2098 if (reg_val & IXGBE_RXDCTL_ENABLE) {
2099 reg_val &= ~IXGBE_RXDCTL_ENABLE;
2100 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
2104 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL);
2105 reg_val |= IXGBE_CTRL_GIO_DIS;
2106 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val);
2108 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2109 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) {
2121 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
2122 * @hw: pointer to hardware structure
2123 * @mask: Mask to specify which semaphore to acquire
2125 * Acquires the SWFW semaphore thought the GSSR register for the specified
2126 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2128 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2132 u32 fwmask = mask << 5;
2136 if (ixgbe_get_eeprom_semaphore(hw))
2137 return IXGBE_ERR_SWFW_SYNC;
2139 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2140 if (!(gssr & (fwmask | swmask)))
2144 * Firmware currently using resource (fwmask) or other software
2145 * thread currently using resource (swmask)
2147 ixgbe_release_eeprom_semaphore(hw);
2153 hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n");
2154 return IXGBE_ERR_SWFW_SYNC;
2158 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2160 ixgbe_release_eeprom_semaphore(hw);
2165 * ixgbe_release_swfw_sync - Release SWFW semaphore
2166 * @hw: pointer to hardware structure
2167 * @mask: Mask to specify which semaphore to release
2169 * Releases the SWFW semaphore thought the GSSR register for the specified
2170 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2172 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2177 ixgbe_get_eeprom_semaphore(hw);
2179 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2181 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2183 ixgbe_release_eeprom_semaphore(hw);
2187 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2188 * @hw: pointer to hardware structure
2189 * @regval: register value to write to RXCTRL
2191 * Enables the Rx DMA unit
2193 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2195 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2201 * ixgbe_blink_led_start_generic - Blink LED based on index.
2202 * @hw: pointer to hardware structure
2203 * @index: led number to blink
2205 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2207 ixgbe_link_speed speed = 0;
2209 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2210 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2213 * Link must be up to auto-blink the LEDs;
2214 * Force it if link is down.
2216 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2219 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2220 autoc_reg |= IXGBE_AUTOC_FLU;
2221 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2225 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2226 led_reg |= IXGBE_LED_BLINK(index);
2227 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2228 IXGBE_WRITE_FLUSH(hw);
2234 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2235 * @hw: pointer to hardware structure
2236 * @index: led number to stop blinking
2238 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2240 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2241 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2243 autoc_reg &= ~IXGBE_AUTOC_FLU;
2244 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2245 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2247 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2248 led_reg &= ~IXGBE_LED_BLINK(index);
2249 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2250 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2251 IXGBE_WRITE_FLUSH(hw);