1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
33 #include "ixgbe_phy.h"
34 #include "ixgbe_mbx.h"
36 #define IXGBE_82599_MAX_TX_QUEUES 128
37 #define IXGBE_82599_MAX_RX_QUEUES 128
38 #define IXGBE_82599_RAR_ENTRIES 128
39 #define IXGBE_82599_MC_TBL_SIZE 128
40 #define IXGBE_82599_VFT_TBL_SIZE 128
41 #define IXGBE_82599_RX_PB_SIZE 512
43 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
44 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
46 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
47 ixgbe_link_speed speed,
49 bool autoneg_wait_to_complete);
50 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
51 ixgbe_link_speed speed,
53 bool autoneg_wait_to_complete);
54 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
55 bool autoneg_wait_to_complete);
56 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
57 ixgbe_link_speed speed,
59 bool autoneg_wait_to_complete);
60 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
61 ixgbe_link_speed speed,
63 bool autoneg_wait_to_complete);
64 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
65 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
67 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
69 struct ixgbe_mac_info *mac = &hw->mac;
71 /* enable the laser control functions for SFP+ fiber */
72 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
73 mac->ops.disable_tx_laser =
74 &ixgbe_disable_tx_laser_multispeed_fiber;
75 mac->ops.enable_tx_laser =
76 &ixgbe_enable_tx_laser_multispeed_fiber;
77 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
79 mac->ops.disable_tx_laser = NULL;
80 mac->ops.enable_tx_laser = NULL;
81 mac->ops.flap_tx_laser = NULL;
84 if (hw->phy.multispeed_fiber) {
85 /* Set up dual speed SFP+ support */
86 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
88 if ((mac->ops.get_media_type(hw) ==
89 ixgbe_media_type_backplane) &&
90 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
91 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
92 !ixgbe_verify_lesm_fw_enabled_82599(hw))
93 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
95 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
99 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
104 u16 list_offset, data_offset, data_value;
106 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
107 ixgbe_init_mac_link_ops_82599(hw);
109 hw->phy.ops.reset = NULL;
111 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
116 /* PHY config will finish before releasing the semaphore */
117 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
118 IXGBE_GSSR_MAC_CSR_SM);
120 ret_val = IXGBE_ERR_SWFW_SYNC;
124 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
125 while (data_value != 0xffff) {
126 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
127 IXGBE_WRITE_FLUSH(hw);
128 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
131 /* Release the semaphore */
132 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
134 * Delay obtaining semaphore again to allow FW access,
135 * semaphore_delay is in ms usleep_range needs us.
137 usleep_range(hw->eeprom.semaphore_delay * 1000,
138 hw->eeprom.semaphore_delay * 2000);
140 /* Now restart DSP by setting Restart_AN and clearing LMS */
141 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
142 IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
143 IXGBE_AUTOC_AN_RESTART));
145 /* Wait for AN to leave state 0 */
146 for (i = 0; i < 10; i++) {
147 usleep_range(4000, 8000);
148 reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
149 if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
152 if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) {
153 hw_dbg(hw, "sfp module setup not complete\n");
154 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
158 /* Restart DSP by setting Restart_AN and return to SFI mode */
159 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
160 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
161 IXGBE_AUTOC_AN_RESTART));
168 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
170 struct ixgbe_mac_info *mac = &hw->mac;
172 ixgbe_init_mac_link_ops_82599(hw);
174 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
175 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
176 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
177 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
178 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
179 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
185 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
186 * @hw: pointer to hardware structure
188 * Initialize any function pointers that were not able to be
189 * set during get_invariants because the PHY/SFP type was
190 * not known. Perform the SFP init if necessary.
193 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
195 struct ixgbe_mac_info *mac = &hw->mac;
196 struct ixgbe_phy_info *phy = &hw->phy;
199 /* Identify the PHY or SFP module */
200 ret_val = phy->ops.identify(hw);
202 /* Setup function pointers based on detected SFP module and speeds */
203 ixgbe_init_mac_link_ops_82599(hw);
205 /* If copper media, overwrite with copper function pointers */
206 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
207 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
208 mac->ops.get_link_capabilities =
209 &ixgbe_get_copper_link_capabilities_generic;
212 /* Set necessary function pointers based on phy type */
213 switch (hw->phy.type) {
215 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
216 phy->ops.get_firmware_version =
217 &ixgbe_get_phy_firmware_version_tnx;
220 phy->ops.get_firmware_version =
221 &ixgbe_get_phy_firmware_version_generic;
231 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
232 * @hw: pointer to hardware structure
233 * @speed: pointer to link speed
234 * @negotiation: true when autoneg or autotry is enabled
236 * Determines the link capabilities by reading the AUTOC register.
238 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
239 ixgbe_link_speed *speed,
245 /* Determine 1G link capabilities off of SFP+ type */
246 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
247 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) {
248 *speed = IXGBE_LINK_SPEED_1GB_FULL;
254 * Determine link capabilities based on the stored value of AUTOC,
255 * which represents EEPROM defaults. If AUTOC value has not been
256 * stored, use the current register value.
258 if (hw->mac.orig_link_settings_stored)
259 autoc = hw->mac.orig_autoc;
261 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
263 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
264 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
265 *speed = IXGBE_LINK_SPEED_1GB_FULL;
266 *negotiation = false;
269 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
270 *speed = IXGBE_LINK_SPEED_10GB_FULL;
271 *negotiation = false;
274 case IXGBE_AUTOC_LMS_1G_AN:
275 *speed = IXGBE_LINK_SPEED_1GB_FULL;
279 case IXGBE_AUTOC_LMS_10G_SERIAL:
280 *speed = IXGBE_LINK_SPEED_10GB_FULL;
281 *negotiation = false;
284 case IXGBE_AUTOC_LMS_KX4_KX_KR:
285 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
286 *speed = IXGBE_LINK_SPEED_UNKNOWN;
287 if (autoc & IXGBE_AUTOC_KR_SUPP)
288 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
289 if (autoc & IXGBE_AUTOC_KX4_SUPP)
290 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
291 if (autoc & IXGBE_AUTOC_KX_SUPP)
292 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
296 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
297 *speed = IXGBE_LINK_SPEED_100_FULL;
298 if (autoc & IXGBE_AUTOC_KR_SUPP)
299 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
300 if (autoc & IXGBE_AUTOC_KX4_SUPP)
301 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
302 if (autoc & IXGBE_AUTOC_KX_SUPP)
303 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
307 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
308 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
309 *negotiation = false;
313 status = IXGBE_ERR_LINK_SETUP;
318 if (hw->phy.multispeed_fiber) {
319 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
320 IXGBE_LINK_SPEED_1GB_FULL;
329 * ixgbe_get_media_type_82599 - Get media type
330 * @hw: pointer to hardware structure
332 * Returns the media type (fiber, copper, backplane)
334 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
336 enum ixgbe_media_type media_type;
338 /* Detect if there is a copper PHY attached. */
339 switch (hw->phy.type) {
340 case ixgbe_phy_cu_unknown:
343 media_type = ixgbe_media_type_copper;
349 switch (hw->device_id) {
350 case IXGBE_DEV_ID_82599_KX4:
351 case IXGBE_DEV_ID_82599_KX4_MEZZ:
352 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
353 case IXGBE_DEV_ID_82599_KR:
354 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
355 case IXGBE_DEV_ID_82599_XAUI_LOM:
356 /* Default device ID is mezzanine card KX/KX4 */
357 media_type = ixgbe_media_type_backplane;
359 case IXGBE_DEV_ID_82599_SFP:
360 case IXGBE_DEV_ID_82599_SFP_FCOE:
361 case IXGBE_DEV_ID_82599_SFP_EM:
362 case IXGBE_DEV_ID_82599_SFP_SF2:
363 media_type = ixgbe_media_type_fiber;
365 case IXGBE_DEV_ID_82599_CX4:
366 media_type = ixgbe_media_type_cx4;
368 case IXGBE_DEV_ID_82599_T3_LOM:
369 media_type = ixgbe_media_type_copper;
371 case IXGBE_DEV_ID_82599_LS:
372 media_type = ixgbe_media_type_fiber_lco;
375 media_type = ixgbe_media_type_unknown;
383 * ixgbe_start_mac_link_82599 - Setup MAC link settings
384 * @hw: pointer to hardware structure
385 * @autoneg_wait_to_complete: true when waiting for completion is needed
387 * Configures link settings based on values in the ixgbe_hw struct.
388 * Restarts the link. Performs autonegotiation if needed.
390 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
391 bool autoneg_wait_to_complete)
399 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
400 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
401 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
403 /* Only poll for autoneg to complete if specified to do so */
404 if (autoneg_wait_to_complete) {
405 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
406 IXGBE_AUTOC_LMS_KX4_KX_KR ||
407 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
408 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
409 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
410 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
411 links_reg = 0; /* Just in case Autoneg time = 0 */
412 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
413 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
414 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
418 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
419 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
420 hw_dbg(hw, "Autoneg did not complete.\n");
425 /* Add delay to filter out noises during initial link setup */
432 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
433 * @hw: pointer to hardware structure
435 * The base drivers may require better control over SFP+ module
436 * PHY states. This includes selectively shutting down the Tx
437 * laser on the PHY, effectively halting physical link.
439 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
441 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
443 /* Disable tx laser; allow 100us to go dark per spec */
444 esdp_reg |= IXGBE_ESDP_SDP3;
445 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
446 IXGBE_WRITE_FLUSH(hw);
451 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
452 * @hw: pointer to hardware structure
454 * The base drivers may require better control over SFP+ module
455 * PHY states. This includes selectively turning on the Tx
456 * laser on the PHY, effectively starting physical link.
458 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
460 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
462 /* Enable tx laser; allow 100ms to light up */
463 esdp_reg &= ~IXGBE_ESDP_SDP3;
464 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
465 IXGBE_WRITE_FLUSH(hw);
470 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
471 * @hw: pointer to hardware structure
473 * When the driver changes the link speeds that it can support,
474 * it sets autotry_restart to true to indicate that we need to
475 * initiate a new autotry session with the link partner. To do
476 * so, we set the speed then disable and re-enable the tx laser, to
477 * alert the link partner that it also needs to restart autotry on its
478 * end. This is consistent with true clause 37 autoneg, which also
479 * involves a loss of signal.
481 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
483 if (hw->mac.autotry_restart) {
484 ixgbe_disable_tx_laser_multispeed_fiber(hw);
485 ixgbe_enable_tx_laser_multispeed_fiber(hw);
486 hw->mac.autotry_restart = false;
491 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
492 * @hw: pointer to hardware structure
493 * @speed: new link speed
494 * @autoneg: true if autonegotiation enabled
495 * @autoneg_wait_to_complete: true when waiting for completion is needed
497 * Set the link speed in the AUTOC register and restarts link.
499 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
500 ixgbe_link_speed speed,
502 bool autoneg_wait_to_complete)
505 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
506 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
508 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
510 bool link_up = false;
513 /* Mask off requested but non-supported speeds */
514 status = hw->mac.ops.get_link_capabilities(hw, &link_speed,
522 * Try each speed one by one, highest priority first. We do this in
523 * software because 10gb fiber doesn't support speed autonegotiation.
525 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
527 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
529 /* If we already have link at this speed, just jump out */
530 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
535 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
538 /* Set the module link speed */
539 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
540 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
541 IXGBE_WRITE_FLUSH(hw);
543 /* Allow module to change analog characteristics (1G->10G) */
546 status = ixgbe_setup_mac_link_82599(hw,
547 IXGBE_LINK_SPEED_10GB_FULL,
549 autoneg_wait_to_complete);
553 /* Flap the tx laser if it has not already been done */
554 hw->mac.ops.flap_tx_laser(hw);
557 * Wait for the controller to acquire link. Per IEEE 802.3ap,
558 * Section 73.10.2, we may have to wait up to 500ms if KR is
559 * attempted. 82599 uses the same timing for 10g SFI.
561 for (i = 0; i < 5; i++) {
562 /* Wait for the link partner to also set speed */
565 /* If we have link, just jump out */
566 status = hw->mac.ops.check_link(hw, &link_speed,
576 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
578 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
579 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
581 /* If we already have link at this speed, just jump out */
582 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
587 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
590 /* Set the module link speed */
591 esdp_reg &= ~IXGBE_ESDP_SDP5;
592 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
593 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
594 IXGBE_WRITE_FLUSH(hw);
596 /* Allow module to change analog characteristics (10G->1G) */
599 status = ixgbe_setup_mac_link_82599(hw,
600 IXGBE_LINK_SPEED_1GB_FULL,
602 autoneg_wait_to_complete);
606 /* Flap the tx laser if it has not already been done */
607 hw->mac.ops.flap_tx_laser(hw);
609 /* Wait for the link partner to also set speed */
612 /* If we have link, just jump out */
613 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
623 * We didn't get link. Configure back to the highest speed we tried,
624 * (if there was more than one). We call ourselves back with just the
625 * single highest speed that the user requested.
628 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
631 autoneg_wait_to_complete);
634 /* Set autoneg_advertised value based on input link speed */
635 hw->phy.autoneg_advertised = 0;
637 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
638 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
640 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
641 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
647 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
648 * @hw: pointer to hardware structure
649 * @speed: new link speed
650 * @autoneg: true if autonegotiation enabled
651 * @autoneg_wait_to_complete: true when waiting for completion is needed
653 * Implements the Intel SmartSpeed algorithm.
655 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
656 ixgbe_link_speed speed, bool autoneg,
657 bool autoneg_wait_to_complete)
660 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
662 bool link_up = false;
663 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
665 /* Set autoneg_advertised value based on input link speed */
666 hw->phy.autoneg_advertised = 0;
668 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
669 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
671 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
672 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
674 if (speed & IXGBE_LINK_SPEED_100_FULL)
675 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
678 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
679 * autoneg advertisement if link is unable to be established at the
680 * highest negotiated rate. This can sometimes happen due to integrity
681 * issues with the physical media connection.
684 /* First, try to get link with full advertisement */
685 hw->phy.smart_speed_active = false;
686 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
687 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
688 autoneg_wait_to_complete);
693 * Wait for the controller to acquire link. Per IEEE 802.3ap,
694 * Section 73.10.2, we may have to wait up to 500ms if KR is
695 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
696 * Table 9 in the AN MAS.
698 for (i = 0; i < 5; i++) {
701 /* If we have link, just jump out */
702 status = hw->mac.ops.check_link(hw, &link_speed,
713 * We didn't get link. If we advertised KR plus one of KX4/KX
714 * (or BX4/BX), then disable KR and try again.
716 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
717 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
720 /* Turn SmartSpeed on to disable KR support */
721 hw->phy.smart_speed_active = true;
722 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
723 autoneg_wait_to_complete);
728 * Wait for the controller to acquire link. 600ms will allow for
729 * the AN link_fail_inhibit_timer as well for multiple cycles of
730 * parallel detect, both 10g and 1g. This allows for the maximum
731 * connect attempts as defined in the AN MAS table 73-7.
733 for (i = 0; i < 6; i++) {
736 /* If we have link, just jump out */
737 status = hw->mac.ops.check_link(hw, &link_speed,
746 /* We didn't get link. Turn SmartSpeed back off. */
747 hw->phy.smart_speed_active = false;
748 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
749 autoneg_wait_to_complete);
752 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
753 hw_dbg(hw, "Smartspeed has downgraded the link speed from "
754 "the maximum advertised\n");
759 * ixgbe_setup_mac_link_82599 - Set MAC link speed
760 * @hw: pointer to hardware structure
761 * @speed: new link speed
762 * @autoneg: true if autonegotiation enabled
763 * @autoneg_wait_to_complete: true when waiting for completion is needed
765 * Set the link speed in the AUTOC register and restarts link.
767 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
768 ixgbe_link_speed speed, bool autoneg,
769 bool autoneg_wait_to_complete)
772 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
773 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
774 u32 start_autoc = autoc;
776 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
777 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
778 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
781 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
783 /* Check to see if speed passed in is supported. */
784 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
788 speed &= link_capabilities;
790 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
791 status = IXGBE_ERR_LINK_SETUP;
795 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
796 if (hw->mac.orig_link_settings_stored)
797 orig_autoc = hw->mac.orig_autoc;
801 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
802 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
803 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
804 /* Set KX4/KX/KR support according to speed requested */
805 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
806 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
807 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
808 autoc |= IXGBE_AUTOC_KX4_SUPP;
809 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
810 (hw->phy.smart_speed_active == false))
811 autoc |= IXGBE_AUTOC_KR_SUPP;
812 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
813 autoc |= IXGBE_AUTOC_KX_SUPP;
814 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
815 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
816 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
817 /* Switch from 1G SFI to 10G SFI if requested */
818 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
819 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
820 autoc &= ~IXGBE_AUTOC_LMS_MASK;
821 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
823 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
824 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
825 /* Switch from 10G SFI to 1G SFI if requested */
826 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
827 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
828 autoc &= ~IXGBE_AUTOC_LMS_MASK;
830 autoc |= IXGBE_AUTOC_LMS_1G_AN;
832 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
836 if (autoc != start_autoc) {
838 autoc |= IXGBE_AUTOC_AN_RESTART;
839 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
841 /* Only poll for autoneg to complete if specified to do so */
842 if (autoneg_wait_to_complete) {
843 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
844 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
845 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
846 links_reg = 0; /*Just in case Autoneg time=0*/
847 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
849 IXGBE_READ_REG(hw, IXGBE_LINKS);
850 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
854 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
856 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
857 hw_dbg(hw, "Autoneg did not "
863 /* Add delay to filter out noises during initial link setup */
872 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
873 * @hw: pointer to hardware structure
874 * @speed: new link speed
875 * @autoneg: true if autonegotiation enabled
876 * @autoneg_wait_to_complete: true if waiting is needed to complete
878 * Restarts link on PHY and MAC based on settings passed in.
880 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
881 ixgbe_link_speed speed,
883 bool autoneg_wait_to_complete)
887 /* Setup the PHY according to input speed */
888 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
889 autoneg_wait_to_complete);
891 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
897 * ixgbe_reset_hw_82599 - Perform hardware reset
898 * @hw: pointer to hardware structure
900 * Resets the hardware by resetting the transmit and receive units, masks
901 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
904 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
912 /* Call adapter stop to disable tx/rx and clear interrupts */
913 hw->mac.ops.stop_adapter(hw);
915 /* PHY ops must be identified and initialized prior to reset */
917 /* Identify PHY and related function pointers */
918 status = hw->phy.ops.init(hw);
920 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
923 /* Setup SFP module if there is one present. */
924 if (hw->phy.sfp_setup_needed) {
925 status = hw->mac.ops.setup_sfp(hw);
926 hw->phy.sfp_setup_needed = false;
929 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
933 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
934 hw->phy.ops.reset(hw);
937 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
938 * access and verify no pending requests before reset
940 ixgbe_disable_pcie_master(hw);
944 * Issue global reset to the MAC. This needs to be a SW reset.
945 * If link reset is used, it might reset the MAC when mng is using it
947 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
948 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
949 IXGBE_WRITE_FLUSH(hw);
951 /* Poll for reset bit to self-clear indicating reset is complete */
952 for (i = 0; i < 10; i++) {
954 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
955 if (!(ctrl & IXGBE_CTRL_RST))
958 if (ctrl & IXGBE_CTRL_RST) {
959 status = IXGBE_ERR_RESET_FAILED;
960 hw_dbg(hw, "Reset polling failed to complete.\n");
964 * Double resets are required for recovery from certain error
965 * conditions. Between resets, it is necessary to stall to allow time
966 * for any pending HW events to complete. We use 1usec since that is
967 * what is needed for ixgbe_disable_pcie_master(). The second reset
968 * then clears out any effects of those events.
970 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
971 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
979 * Store the original AUTOC/AUTOC2 values if they have not been
980 * stored off yet. Otherwise restore the stored original
981 * values since the reset operation sets back to defaults.
983 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
984 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
985 if (hw->mac.orig_link_settings_stored == false) {
986 hw->mac.orig_autoc = autoc;
987 hw->mac.orig_autoc2 = autoc2;
988 hw->mac.orig_link_settings_stored = true;
990 if (autoc != hw->mac.orig_autoc)
991 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
992 IXGBE_AUTOC_AN_RESTART));
994 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
995 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
996 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
997 autoc2 |= (hw->mac.orig_autoc2 &
998 IXGBE_AUTOC2_UPPER_MASK);
999 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1003 /* Store the permanent mac address */
1004 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1007 * Store MAC address from RAR0, clear receive address registers, and
1008 * clear the multicast table. Also reset num_rar_entries to 128,
1009 * since we modify this value when programming the SAN MAC address.
1011 hw->mac.num_rar_entries = 128;
1012 hw->mac.ops.init_rx_addrs(hw);
1014 /* Store the permanent SAN mac address */
1015 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1017 /* Add the SAN MAC address to the RAR only if it's a valid address */
1018 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1019 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1020 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1022 /* Reserve the last RAR for the SAN MAC address */
1023 hw->mac.num_rar_entries--;
1026 /* Store the alternative WWNN/WWPN prefix */
1027 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1028 &hw->mac.wwpn_prefix);
1035 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1036 * @hw: pointer to hardware structure
1038 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1041 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1042 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1045 * Before starting reinitialization process,
1046 * FDIRCMD.CMD must be zero.
1048 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1049 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1050 IXGBE_FDIRCMD_CMD_MASK))
1054 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1055 hw_dbg(hw, "Flow Director previous command isn't complete, "
1056 "aborting table re-initialization.\n");
1057 return IXGBE_ERR_FDIR_REINIT_FAILED;
1060 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1061 IXGBE_WRITE_FLUSH(hw);
1063 * 82599 adapters flow director init flow cannot be restarted,
1064 * Workaround 82599 silicon errata by performing the following steps
1065 * before re-writing the FDIRCTRL control register with the same value.
1066 * - write 1 to bit 8 of FDIRCMD register &
1067 * - write 0 to bit 8 of FDIRCMD register
1069 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1070 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1071 IXGBE_FDIRCMD_CLEARHT));
1072 IXGBE_WRITE_FLUSH(hw);
1073 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1074 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1075 ~IXGBE_FDIRCMD_CLEARHT));
1076 IXGBE_WRITE_FLUSH(hw);
1078 * Clear FDIR Hash register to clear any leftover hashes
1079 * waiting to be programmed.
1081 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1082 IXGBE_WRITE_FLUSH(hw);
1084 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1085 IXGBE_WRITE_FLUSH(hw);
1087 /* Poll init-done after we write FDIRCTRL register */
1088 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1089 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1090 IXGBE_FDIRCTRL_INIT_DONE)
1094 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1095 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1096 return IXGBE_ERR_FDIR_REINIT_FAILED;
1099 /* Clear FDIR statistics registers (read to clear) */
1100 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1101 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1102 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1103 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1104 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1110 * ixgbe_set_fdir_rxpba_82599 - Initialize Flow Director Rx packet buffer
1111 * @hw: pointer to hardware structure
1112 * @pballoc: which mode to allocate filters with
1114 static s32 ixgbe_set_fdir_rxpba_82599(struct ixgbe_hw *hw, const u32 pballoc)
1116 u32 fdir_pbsize = hw->mac.rx_pb_size << IXGBE_RXPBSIZE_SHIFT;
1117 u32 current_rxpbsize = 0;
1120 /* reserve space for Flow Director filters */
1122 case IXGBE_FDIR_PBALLOC_256K:
1123 fdir_pbsize -= 256 << IXGBE_RXPBSIZE_SHIFT;
1125 case IXGBE_FDIR_PBALLOC_128K:
1126 fdir_pbsize -= 128 << IXGBE_RXPBSIZE_SHIFT;
1128 case IXGBE_FDIR_PBALLOC_64K:
1129 fdir_pbsize -= 64 << IXGBE_RXPBSIZE_SHIFT;
1131 case IXGBE_FDIR_PBALLOC_NONE:
1133 return IXGBE_ERR_PARAM;
1136 /* determine current RX packet buffer size */
1137 for (i = 0; i < 8; i++)
1138 current_rxpbsize += IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
1140 /* if there is already room for the filters do nothing */
1141 if (current_rxpbsize <= fdir_pbsize)
1144 if (current_rxpbsize > hw->mac.rx_pb_size) {
1146 * if rxpbsize is greater than max then HW max the Rx buffer
1147 * sizes are unconfigured or misconfigured since HW default is
1148 * to give the full buffer to each traffic class resulting in
1149 * the total size being buffer size 8x actual size
1151 * This assumes no DCB since the RXPBSIZE registers appear to
1154 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), fdir_pbsize);
1155 for (i = 1; i < 8; i++)
1156 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1159 * Since the Rx packet buffer appears to have already been
1160 * configured we need to shrink each packet buffer by enough
1161 * to make room for the filters. As such we take each rxpbsize
1162 * value and multiply it by a fraction representing the size
1163 * needed over the size we currently have.
1165 * We need to reduce fdir_pbsize and current_rxpbsize to
1166 * 1/1024 of their original values in order to avoid
1167 * overflowing the u32 being used to store rxpbsize.
1169 fdir_pbsize >>= IXGBE_RXPBSIZE_SHIFT;
1170 current_rxpbsize >>= IXGBE_RXPBSIZE_SHIFT;
1171 for (i = 0; i < 8; i++) {
1172 u32 rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
1173 rxpbsize *= fdir_pbsize;
1174 rxpbsize /= current_rxpbsize;
1175 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
1183 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1184 * @hw: pointer to hardware structure
1185 * @fdirctrl: value to write to flow director control register
1187 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1191 /* Prime the keys for hashing */
1192 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1193 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1196 * Poll init-done after we write the register. Estimated times:
1197 * 10G: PBALLOC = 11b, timing is 60us
1198 * 1G: PBALLOC = 11b, timing is 600us
1199 * 100M: PBALLOC = 11b, timing is 6ms
1201 * Multiple these timings by 4 if under full Rx load
1203 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1204 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1205 * this might not finish in our poll time, but we can live with that
1208 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1209 IXGBE_WRITE_FLUSH(hw);
1210 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1211 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1212 IXGBE_FDIRCTRL_INIT_DONE)
1214 usleep_range(1000, 2000);
1217 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1218 hw_dbg(hw, "Flow Director poll time exceeded!\n");
1222 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1223 * @hw: pointer to hardware structure
1224 * @fdirctrl: value to write to flow director control register, initially
1225 * contains just the value of the Rx packet buffer allocation
1227 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1231 /* Before enabling Flow Director, verify the Rx Packet Buffer size */
1232 err = ixgbe_set_fdir_rxpba_82599(hw, fdirctrl);
1237 * Continue setup of fdirctrl register bits:
1238 * Move the flexible bytes to use the ethertype - shift 6 words
1239 * Set the maximum length per hash bucket to 0xA filters
1240 * Send interrupt when 64 filters are left
1242 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1243 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1244 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1246 /* write hashes and fdirctrl register, poll for completion */
1247 ixgbe_fdir_enable_82599(hw, fdirctrl);
1253 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1254 * @hw: pointer to hardware structure
1255 * @fdirctrl: value to write to flow director control register, initially
1256 * contains just the value of the Rx packet buffer allocation
1258 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1262 /* Before enabling Flow Director, verify the Rx Packet Buffer size */
1263 err = ixgbe_set_fdir_rxpba_82599(hw, fdirctrl);
1268 * Continue setup of fdirctrl register bits:
1269 * Turn perfect match filtering on
1270 * Report hash in RSS field of Rx wb descriptor
1271 * Initialize the drop queue
1272 * Move the flexible bytes to use the ethertype - shift 6 words
1273 * Set the maximum length per hash bucket to 0xA filters
1274 * Send interrupt when 64 (0x4 * 16) filters are left
1276 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1277 IXGBE_FDIRCTRL_REPORT_STATUS |
1278 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1279 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1280 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1281 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1283 /* write hashes and fdirctrl register, poll for completion */
1284 ixgbe_fdir_enable_82599(hw, fdirctrl);
1290 * These defines allow us to quickly generate all of the necessary instructions
1291 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1292 * for values 0 through 15
1294 #define IXGBE_ATR_COMMON_HASH_KEY \
1295 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1296 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1299 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1300 common_hash ^= lo_hash_dword >> n; \
1301 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1302 bucket_hash ^= lo_hash_dword >> n; \
1303 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1304 sig_hash ^= lo_hash_dword << (16 - n); \
1305 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1306 common_hash ^= hi_hash_dword >> n; \
1307 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1308 bucket_hash ^= hi_hash_dword >> n; \
1309 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1310 sig_hash ^= hi_hash_dword << (16 - n); \
1314 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1315 * @stream: input bitstream to compute the hash on
1317 * This function is almost identical to the function above but contains
1318 * several optomizations such as unwinding all of the loops, letting the
1319 * compiler work out all of the conditional ifs since the keys are static
1320 * defines, and computing two keys at once since the hashed dword stream
1321 * will be the same for both keys.
1323 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1324 union ixgbe_atr_hash_dword common)
1326 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1327 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1329 /* record the flow_vm_vlan bits as they are a key part to the hash */
1330 flow_vm_vlan = ntohl(input.dword);
1332 /* generate common hash dword */
1333 hi_hash_dword = ntohl(common.dword);
1335 /* low dword is word swapped version of common */
1336 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1338 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1339 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1341 /* Process bits 0 and 16 */
1342 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1345 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1346 * delay this because bit 0 of the stream should not be processed
1347 * so we do not add the vlan until after bit 0 was processed
1349 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1351 /* Process remaining 30 bit of the key */
1352 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1353 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1354 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1355 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1356 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1357 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1358 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1359 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1360 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1361 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1362 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1363 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1364 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1365 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1366 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1368 /* combine common_hash result with signature and bucket hashes */
1369 bucket_hash ^= common_hash;
1370 bucket_hash &= IXGBE_ATR_HASH_MASK;
1372 sig_hash ^= common_hash << 16;
1373 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1375 /* return completed signature hash */
1376 return sig_hash ^ bucket_hash;
1380 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1381 * @hw: pointer to hardware structure
1382 * @input: unique input dword
1383 * @common: compressed common input dword
1384 * @queue: queue index to direct traffic to
1386 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1387 union ixgbe_atr_hash_dword input,
1388 union ixgbe_atr_hash_dword common,
1395 * Get the flow_type in order to program FDIRCMD properly
1396 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1398 switch (input.formatted.flow_type) {
1399 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1400 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1401 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1402 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1403 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1404 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1407 hw_dbg(hw, " Error on flow type input\n");
1408 return IXGBE_ERR_CONFIG;
1411 /* configure FDIRCMD register */
1412 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1413 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1414 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1415 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1418 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1419 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1421 fdirhashcmd = (u64)fdircmd << 32;
1422 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1423 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1425 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1430 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1433 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1434 bucket_hash ^= lo_hash_dword >> n; \
1435 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1436 bucket_hash ^= hi_hash_dword >> n; \
1440 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1441 * @atr_input: input bitstream to compute the hash on
1442 * @input_mask: mask for the input bitstream
1444 * This function serves two main purposes. First it applys the input_mask
1445 * to the atr_input resulting in a cleaned up atr_input data stream.
1446 * Secondly it computes the hash and stores it in the bkt_hash field at
1447 * the end of the input byte stream. This way it will be available for
1448 * future use without needing to recompute the hash.
1450 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1451 union ixgbe_atr_input *input_mask)
1454 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1455 u32 bucket_hash = 0;
1457 /* Apply masks to input data */
1458 input->dword_stream[0] &= input_mask->dword_stream[0];
1459 input->dword_stream[1] &= input_mask->dword_stream[1];
1460 input->dword_stream[2] &= input_mask->dword_stream[2];
1461 input->dword_stream[3] &= input_mask->dword_stream[3];
1462 input->dword_stream[4] &= input_mask->dword_stream[4];
1463 input->dword_stream[5] &= input_mask->dword_stream[5];
1464 input->dword_stream[6] &= input_mask->dword_stream[6];
1465 input->dword_stream[7] &= input_mask->dword_stream[7];
1466 input->dword_stream[8] &= input_mask->dword_stream[8];
1467 input->dword_stream[9] &= input_mask->dword_stream[9];
1468 input->dword_stream[10] &= input_mask->dword_stream[10];
1470 /* record the flow_vm_vlan bits as they are a key part to the hash */
1471 flow_vm_vlan = ntohl(input->dword_stream[0]);
1473 /* generate common hash dword */
1474 hi_hash_dword = ntohl(input->dword_stream[1] ^
1475 input->dword_stream[2] ^
1476 input->dword_stream[3] ^
1477 input->dword_stream[4] ^
1478 input->dword_stream[5] ^
1479 input->dword_stream[6] ^
1480 input->dword_stream[7] ^
1481 input->dword_stream[8] ^
1482 input->dword_stream[9] ^
1483 input->dword_stream[10]);
1485 /* low dword is word swapped version of common */
1486 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1488 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1489 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1491 /* Process bits 0 and 16 */
1492 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1495 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1496 * delay this because bit 0 of the stream should not be processed
1497 * so we do not add the vlan until after bit 0 was processed
1499 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1501 /* Process remaining 30 bit of the key */
1502 IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
1503 IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
1504 IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
1505 IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
1506 IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
1507 IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
1508 IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
1509 IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
1510 IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
1511 IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
1512 IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
1513 IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
1514 IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
1515 IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
1516 IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
1519 * Limit hash to 13 bits since max bucket count is 8K.
1520 * Store result at the end of the input stream.
1522 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1526 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1527 * @input_mask: mask to be bit swapped
1529 * The source and destination port masks for flow director are bit swapped
1530 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1531 * generate a correctly swapped value we need to bit swap the mask and that
1532 * is what is accomplished by this function.
1534 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1536 u32 mask = ntohs(input_mask->formatted.dst_port);
1537 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1538 mask |= ntohs(input_mask->formatted.src_port);
1539 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1540 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1541 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1542 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1546 * These two macros are meant to address the fact that we have registers
1547 * that are either all or in part big-endian. As a result on big-endian
1548 * systems we will end up byte swapping the value to little-endian before
1549 * it is byte swapped again and written to the hardware in the original
1550 * big-endian format.
1552 #define IXGBE_STORE_AS_BE32(_value) \
1553 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1554 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1556 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1557 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
1559 #define IXGBE_STORE_AS_BE16(_value) \
1560 ntohs(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1562 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1563 union ixgbe_atr_input *input_mask)
1565 /* mask IPv6 since it is currently not supported */
1566 u32 fdirm = IXGBE_FDIRM_DIPv6;
1570 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1571 * are zero, then assume a full mask for that field. Also assume that
1572 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1573 * cannot be masked out in this implementation.
1575 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1579 /* verify bucket hash is cleared on hash generation */
1580 if (input_mask->formatted.bkt_hash)
1581 hw_dbg(hw, " bucket hash should always be 0 in mask\n");
1583 /* Program FDIRM and verify partial masks */
1584 switch (input_mask->formatted.vm_pool & 0x7F) {
1586 fdirm |= IXGBE_FDIRM_POOL;
1590 hw_dbg(hw, " Error on vm pool mask\n");
1591 return IXGBE_ERR_CONFIG;
1594 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1596 fdirm |= IXGBE_FDIRM_L4P;
1597 if (input_mask->formatted.dst_port ||
1598 input_mask->formatted.src_port) {
1599 hw_dbg(hw, " Error on src/dst port mask\n");
1600 return IXGBE_ERR_CONFIG;
1602 case IXGBE_ATR_L4TYPE_MASK:
1605 hw_dbg(hw, " Error on flow type mask\n");
1606 return IXGBE_ERR_CONFIG;
1609 switch (ntohs(input_mask->formatted.vlan_id) & 0xEFFF) {
1611 /* mask VLAN ID, fall through to mask VLAN priority */
1612 fdirm |= IXGBE_FDIRM_VLANID;
1614 /* mask VLAN priority */
1615 fdirm |= IXGBE_FDIRM_VLANP;
1618 /* mask VLAN ID only, fall through */
1619 fdirm |= IXGBE_FDIRM_VLANID;
1621 /* no VLAN fields masked */
1624 hw_dbg(hw, " Error on VLAN mask\n");
1625 return IXGBE_ERR_CONFIG;
1628 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1630 /* Mask Flex Bytes, fall through */
1631 fdirm |= IXGBE_FDIRM_FLEX;
1635 hw_dbg(hw, " Error on flexible byte mask\n");
1636 return IXGBE_ERR_CONFIG;
1639 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1640 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1642 /* store the TCP/UDP port masks, bit reversed from port layout */
1643 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1645 /* write both the same so that UDP and TCP use the same mask */
1646 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1647 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1649 /* store source and destination IP masks (big-enian) */
1650 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1651 ~input_mask->formatted.src_ip[0]);
1652 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1653 ~input_mask->formatted.dst_ip[0]);
1658 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1659 union ixgbe_atr_input *input,
1660 u16 soft_id, u8 queue)
1662 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1664 /* currently IPv6 is not supported, must be programmed with 0 */
1665 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1666 input->formatted.src_ip[0]);
1667 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1668 input->formatted.src_ip[1]);
1669 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1670 input->formatted.src_ip[2]);
1672 /* record the source address (big-endian) */
1673 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1675 /* record the first 32 bits of the destination address (big-endian) */
1676 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1678 /* record source and destination port (little-endian)*/
1679 fdirport = ntohs(input->formatted.dst_port);
1680 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1681 fdirport |= ntohs(input->formatted.src_port);
1682 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1684 /* record vlan (little-endian) and flex_bytes(big-endian) */
1685 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1686 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1687 fdirvlan |= ntohs(input->formatted.vlan_id);
1688 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1690 /* configure FDIRHASH register */
1691 fdirhash = input->formatted.bkt_hash;
1692 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1693 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1696 * flush all previous writes to make certain registers are
1697 * programmed prior to issuing the command
1699 IXGBE_WRITE_FLUSH(hw);
1701 /* configure FDIRCMD register */
1702 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1703 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1704 if (queue == IXGBE_FDIR_DROP_QUEUE)
1705 fdircmd |= IXGBE_FDIRCMD_DROP;
1706 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1707 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1708 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1710 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1715 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1716 union ixgbe_atr_input *input,
1724 /* configure FDIRHASH register */
1725 fdirhash = input->formatted.bkt_hash;
1726 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1727 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1729 /* flush hash to HW */
1730 IXGBE_WRITE_FLUSH(hw);
1732 /* Query if filter is present */
1733 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1735 for (retry_count = 10; retry_count; retry_count--) {
1736 /* allow 10us for query to process */
1738 /* verify query completed successfully */
1739 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1740 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1745 err = IXGBE_ERR_FDIR_REINIT_FAILED;
1747 /* if filter exists in hardware then remove it */
1748 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1749 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1750 IXGBE_WRITE_FLUSH(hw);
1751 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1752 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1759 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1760 * @hw: pointer to hardware structure
1761 * @reg: analog register to read
1764 * Performs read operation to Omer analog register specified.
1766 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1770 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1772 IXGBE_WRITE_FLUSH(hw);
1774 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1775 *val = (u8)core_ctl;
1781 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1782 * @hw: pointer to hardware structure
1783 * @reg: atlas register to write
1784 * @val: value to write
1786 * Performs write operation to Omer analog register specified.
1788 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1792 core_ctl = (reg << 8) | val;
1793 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1794 IXGBE_WRITE_FLUSH(hw);
1801 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1802 * @hw: pointer to hardware structure
1804 * Starts the hardware using the generic start_hw function
1805 * and the generation start_hw function.
1806 * Then performs revision-specific operations, if any.
1808 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1812 ret_val = ixgbe_start_hw_generic(hw);
1816 ret_val = ixgbe_start_hw_gen2(hw);
1820 /* We need to run link autotry after the driver loads */
1821 hw->mac.autotry_restart = true;
1822 hw->mac.rx_pb_size = IXGBE_82599_RX_PB_SIZE;
1825 ret_val = ixgbe_verify_fw_version_82599(hw);
1831 * ixgbe_identify_phy_82599 - Get physical layer module
1832 * @hw: pointer to hardware structure
1834 * Determines the physical layer module found on the current adapter.
1835 * If PHY already detected, maintains current PHY type in hw struct,
1836 * otherwise executes the PHY detection routine.
1838 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1840 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1842 /* Detect PHY if not unknown - returns success if already detected. */
1843 status = ixgbe_identify_phy_generic(hw);
1845 /* 82599 10GBASE-T requires an external PHY */
1846 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1849 status = ixgbe_identify_sfp_module_generic(hw);
1852 /* Set PHY type none if no PHY detected */
1853 if (hw->phy.type == ixgbe_phy_unknown) {
1854 hw->phy.type = ixgbe_phy_none;
1858 /* Return error if SFP module has been detected but is not supported */
1859 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1860 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1867 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1868 * @hw: pointer to hardware structure
1870 * Determines physical layer capabilities of the current configuration.
1872 static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1874 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1875 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1876 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1877 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1878 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1879 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1880 u16 ext_ability = 0;
1881 u8 comp_codes_10g = 0;
1882 u8 comp_codes_1g = 0;
1884 hw->phy.ops.identify(hw);
1886 switch (hw->phy.type) {
1889 case ixgbe_phy_cu_unknown:
1890 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1892 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
1893 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1894 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
1895 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1896 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
1897 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1903 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1904 case IXGBE_AUTOC_LMS_1G_AN:
1905 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1906 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1907 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1908 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1911 /* SFI mode so read SFP module */
1914 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1915 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1916 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1917 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1918 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1919 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
1920 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
1923 case IXGBE_AUTOC_LMS_10G_SERIAL:
1924 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1925 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1927 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1930 case IXGBE_AUTOC_LMS_KX4_KX_KR:
1931 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1932 if (autoc & IXGBE_AUTOC_KX_SUPP)
1933 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1934 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1935 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1936 if (autoc & IXGBE_AUTOC_KR_SUPP)
1937 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1946 /* SFP check must be done last since DA modules are sometimes used to
1947 * test KR mode - we need to id KR mode correctly before SFP module.
1948 * Call identify_sfp because the pluggable module may have changed */
1949 hw->phy.ops.identify_sfp(hw);
1950 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1953 switch (hw->phy.type) {
1954 case ixgbe_phy_sfp_passive_tyco:
1955 case ixgbe_phy_sfp_passive_unknown:
1956 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1958 case ixgbe_phy_sfp_ftl_active:
1959 case ixgbe_phy_sfp_active_unknown:
1960 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1962 case ixgbe_phy_sfp_avago:
1963 case ixgbe_phy_sfp_ftl:
1964 case ixgbe_phy_sfp_intel:
1965 case ixgbe_phy_sfp_unknown:
1966 hw->phy.ops.read_i2c_eeprom(hw,
1967 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1968 hw->phy.ops.read_i2c_eeprom(hw,
1969 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1970 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1971 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1972 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1973 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1974 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1975 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1982 return physical_layer;
1986 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1987 * @hw: pointer to hardware structure
1988 * @regval: register value to write to RXCTRL
1990 * Enables the Rx DMA unit for 82599
1992 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
1994 #define IXGBE_MAX_SECRX_POLL 30
1999 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2000 * If traffic is incoming before we enable the Rx unit, it could hang
2001 * the Rx DMA unit. Therefore, make sure the security engine is
2002 * completely disabled prior to enabling the Rx unit.
2004 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2005 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2006 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2007 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2008 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2009 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2012 /* Use interrupt-safe sleep just in case */
2016 /* For informational purposes only */
2017 if (i >= IXGBE_MAX_SECRX_POLL)
2018 hw_dbg(hw, "Rx unit being enabled before security "
2019 "path fully disabled. Continuing with init.\n");
2021 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2022 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2023 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2024 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2025 IXGBE_WRITE_FLUSH(hw);
2031 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2032 * @hw: pointer to hardware structure
2034 * Verifies that installed the firmware version is 0.6 or higher
2035 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2037 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2038 * if the FW version is not supported.
2040 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2042 s32 status = IXGBE_ERR_EEPROM_VERSION;
2043 u16 fw_offset, fw_ptp_cfg_offset;
2046 /* firmware check is only necessary for SFI devices */
2047 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2049 goto fw_version_out;
2052 /* get the offset to the Firmware Module block */
2053 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2055 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2056 goto fw_version_out;
2058 /* get the offset to the Pass Through Patch Configuration block */
2059 hw->eeprom.ops.read(hw, (fw_offset +
2060 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2061 &fw_ptp_cfg_offset);
2063 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2064 goto fw_version_out;
2066 /* get the firmware version */
2067 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2068 IXGBE_FW_PATCH_VERSION_4),
2071 if (fw_version > 0x5)
2079 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2080 * @hw: pointer to hardware structure
2082 * Returns true if the LESM FW module is present and enabled. Otherwise
2083 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2085 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2087 bool lesm_enabled = false;
2088 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2091 /* get the offset to the Firmware Module block */
2092 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2094 if ((status != 0) ||
2095 (fw_offset == 0) || (fw_offset == 0xFFFF))
2098 /* get the offset to the LESM Parameters block */
2099 status = hw->eeprom.ops.read(hw, (fw_offset +
2100 IXGBE_FW_LESM_PARAMETERS_PTR),
2101 &fw_lesm_param_offset);
2103 if ((status != 0) ||
2104 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2107 /* get the lesm state word */
2108 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2109 IXGBE_FW_LESM_STATE_1),
2112 if ((status == 0) &&
2113 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2114 lesm_enabled = true;
2117 return lesm_enabled;
2121 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2122 * fastest available method
2124 * @hw: pointer to hardware structure
2125 * @offset: offset of word in EEPROM to read
2126 * @words: number of words
2127 * @data: word(s) read from the EEPROM
2129 * Retrieves 16 bit word(s) read from EEPROM
2131 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2132 u16 words, u16 *data)
2134 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2135 s32 ret_val = IXGBE_ERR_CONFIG;
2138 * If EEPROM is detected and can be addressed using 14 bits,
2139 * use EERD otherwise use bit bang
2141 if ((eeprom->type == ixgbe_eeprom_spi) &&
2142 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2143 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2146 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2154 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2155 * fastest available method
2157 * @hw: pointer to hardware structure
2158 * @offset: offset of word in the EEPROM to read
2159 * @data: word read from the EEPROM
2161 * Reads a 16 bit word from the EEPROM
2163 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2164 u16 offset, u16 *data)
2166 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2167 s32 ret_val = IXGBE_ERR_CONFIG;
2170 * If EEPROM is detected and can be addressed using 14 bits,
2171 * use EERD otherwise use bit bang
2173 if ((eeprom->type == ixgbe_eeprom_spi) &&
2174 (offset <= IXGBE_EERD_MAX_ADDR))
2175 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2177 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2182 static struct ixgbe_mac_operations mac_ops_82599 = {
2183 .init_hw = &ixgbe_init_hw_generic,
2184 .reset_hw = &ixgbe_reset_hw_82599,
2185 .start_hw = &ixgbe_start_hw_82599,
2186 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2187 .get_media_type = &ixgbe_get_media_type_82599,
2188 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2189 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2190 .get_mac_addr = &ixgbe_get_mac_addr_generic,
2191 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
2192 .get_device_caps = &ixgbe_get_device_caps_generic,
2193 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
2194 .stop_adapter = &ixgbe_stop_adapter_generic,
2195 .get_bus_info = &ixgbe_get_bus_info_generic,
2196 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2197 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2198 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2199 .setup_link = &ixgbe_setup_mac_link_82599,
2200 .set_rxpba = &ixgbe_set_rxpba_generic,
2201 .check_link = &ixgbe_check_mac_link_generic,
2202 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2203 .led_on = &ixgbe_led_on_generic,
2204 .led_off = &ixgbe_led_off_generic,
2205 .blink_led_start = &ixgbe_blink_led_start_generic,
2206 .blink_led_stop = &ixgbe_blink_led_stop_generic,
2207 .set_rar = &ixgbe_set_rar_generic,
2208 .clear_rar = &ixgbe_clear_rar_generic,
2209 .set_vmdq = &ixgbe_set_vmdq_generic,
2210 .clear_vmdq = &ixgbe_clear_vmdq_generic,
2211 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2212 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2213 .enable_mc = &ixgbe_enable_mc_generic,
2214 .disable_mc = &ixgbe_disable_mc_generic,
2215 .clear_vfta = &ixgbe_clear_vfta_generic,
2216 .set_vfta = &ixgbe_set_vfta_generic,
2217 .fc_enable = &ixgbe_fc_enable_generic,
2218 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic,
2219 .init_uta_tables = &ixgbe_init_uta_tables_generic,
2220 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2221 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
2222 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
2223 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
2224 .release_swfw_sync = &ixgbe_release_swfw_sync,
2228 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2229 .init_params = &ixgbe_init_eeprom_params_generic,
2230 .read = &ixgbe_read_eeprom_82599,
2231 .read_buffer = &ixgbe_read_eeprom_buffer_82599,
2232 .write = &ixgbe_write_eeprom_generic,
2233 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic,
2234 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
2235 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2236 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2239 static struct ixgbe_phy_operations phy_ops_82599 = {
2240 .identify = &ixgbe_identify_phy_82599,
2241 .identify_sfp = &ixgbe_identify_sfp_module_generic,
2242 .init = &ixgbe_init_phy_ops_82599,
2243 .reset = &ixgbe_reset_phy_generic,
2244 .read_reg = &ixgbe_read_phy_reg_generic,
2245 .write_reg = &ixgbe_write_phy_reg_generic,
2246 .setup_link = &ixgbe_setup_phy_link_generic,
2247 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2248 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2249 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2250 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2251 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2252 .check_overtemp = &ixgbe_tn_check_overtemp,
2255 struct ixgbe_info ixgbe_82599_info = {
2256 .mac = ixgbe_mac_82599EB,
2257 .get_invariants = &ixgbe_get_invariants_82599,
2258 .mac_ops = &mac_ops_82599,
2259 .eeprom_ops = &eeprom_ops_82599,
2260 .phy_ops = &phy_ops_82599,
2261 .mbx_ops = &mbx_ops_generic,