2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Driver for SGI's IOC3 based Ethernet cards as found in the PCI card.
8 * Copyright (C) 1999, 2000, 01, 03, 06 Ralf Baechle
9 * Copyright (C) 1995, 1999, 2000, 2001 by Silicon Graphics, Inc.
12 * o IOC3 ASIC specification 4.51, 1996-04-18
13 * o IEEE 802.3 specification, 2000 edition
14 * o DP38840A Specification, National Semiconductor, March 1997
18 * o Handle allocation failures in ioc3_alloc_skb() more gracefully.
19 * o Handle allocation failures in ioc3_init_rings().
20 * o Use prefetching for large packets. What is a good lower limit for
22 * o We're probably allocating a bit too much memory.
23 * o Use hardware checksums.
24 * o Convert to using a IOC3 meta driver.
25 * o Which PHYs might possibly be attached to the IOC3 in real live,
26 * which workarounds are required for them? Do we ever have Lucent's?
27 * o For the 2.5 branch kill the mii-tool ioctls.
30 #define IOC3_NAME "ioc3-eth"
31 #define IOC3_VERSION "2.6.3-4"
33 #include <linux/init.h>
34 #include <linux/delay.h>
35 #include <linux/kernel.h>
37 #include <linux/errno.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/crc32.h>
41 #include <linux/mii.h>
44 #include <linux/tcp.h>
45 #include <linux/udp.h>
46 #include <linux/dma-mapping.h>
48 #ifdef CONFIG_SERIAL_8250
49 #include <linux/serial_core.h>
50 #include <linux/serial_8250.h>
51 #include <linux/serial_reg.h>
54 #include <linux/netdevice.h>
55 #include <linux/etherdevice.h>
56 #include <linux/ethtool.h>
57 #include <linux/skbuff.h>
60 #include <asm/byteorder.h>
62 #include <asm/pgtable.h>
63 #include <asm/uaccess.h>
64 #include <asm/sn/types.h>
65 #include <asm/sn/ioc3.h>
66 #include <asm/pci/bridge.h>
69 * 64 RX buffers. This is tunable in the range of 16 <= x < 512. The
70 * value must be a power of two.
74 #define ETCSR_FD ((17<<ETCSR_IPGR2_SHIFT) | (11<<ETCSR_IPGR1_SHIFT) | 21)
75 #define ETCSR_HD ((21<<ETCSR_IPGR2_SHIFT) | (21<<ETCSR_IPGR1_SHIFT) | 21)
77 /* Private per NIC data of the driver. */
80 unsigned long *rxr; /* pointer to receiver ring */
81 struct ioc3_etxd *txr;
82 struct sk_buff *rx_skbs[512];
83 struct sk_buff *tx_skbs[128];
84 struct net_device_stats stats;
85 int rx_ci; /* RX consumer index */
86 int rx_pi; /* RX producer index */
87 int tx_ci; /* TX consumer index */
88 int tx_pi; /* TX producer index */
90 u32 emcr, ehar_h, ehar_l;
92 struct mii_if_info mii;
94 #define IOC3_FLAG_RX_CHECKSUMS 1
98 /* Members used by autonegotiation */
99 struct timer_list ioc3_timer;
102 static inline struct net_device *priv_netdev(struct ioc3_private *dev)
104 return (void *)dev - ((sizeof(struct net_device) + 31) & ~31);
107 static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
108 static void ioc3_set_multicast_list(struct net_device *dev);
109 static int ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev);
110 static void ioc3_timeout(struct net_device *dev);
111 static inline unsigned int ioc3_hash(const unsigned char *addr);
112 static inline void ioc3_stop(struct ioc3_private *ip);
113 static void ioc3_init(struct net_device *dev);
115 static const char ioc3_str[] = "IOC3 Ethernet";
116 static const struct ethtool_ops ioc3_ethtool_ops;
118 /* We use this to acquire receive skb's that we can DMA directly into. */
120 #define IOC3_CACHELINE 128UL
122 static inline unsigned long aligned_rx_skb_addr(unsigned long addr)
124 return (~addr + 1) & (IOC3_CACHELINE - 1UL);
127 static inline struct sk_buff * ioc3_alloc_skb(unsigned long length,
128 unsigned int gfp_mask)
132 skb = alloc_skb(length + IOC3_CACHELINE - 1, gfp_mask);
134 int offset = aligned_rx_skb_addr((unsigned long) skb->data);
136 skb_reserve(skb, offset);
142 static inline unsigned long ioc3_map(void *ptr, unsigned long vdev)
144 #ifdef CONFIG_SGI_IP27
145 vdev <<= 57; /* Shift to PCI64_ATTR_VIRTUAL */
147 return vdev | (0xaUL << PCI64_ATTR_TARG_SHFT) | PCI64_ATTR_PREF |
148 ((unsigned long)ptr & TO_PHYS_MASK);
150 return virt_to_bus(ptr);
154 /* BEWARE: The IOC3 documentation documents the size of rx buffers as
155 1644 while it's actually 1664. This one was nasty to track down ... */
157 #define RX_BUF_ALLOC_SIZE (1664 + RX_OFFSET + IOC3_CACHELINE)
159 /* DMA barrier to separate cached and uncached accesses. */
161 __asm__("sync" ::: "memory")
164 #define IOC3_SIZE 0x100000
167 * IOC3 is a big endian device
169 * Unorthodox but makes the users of these macros more readable - the pointer
170 * to the IOC3's memory mapped registers is expected as struct ioc3 * ioc3
171 * in the environment.
173 #define ioc3_r_mcr() be32_to_cpu(ioc3->mcr)
174 #define ioc3_w_mcr(v) do { ioc3->mcr = cpu_to_be32(v); } while (0)
175 #define ioc3_w_gpcr_s(v) do { ioc3->gpcr_s = cpu_to_be32(v); } while (0)
176 #define ioc3_r_emcr() be32_to_cpu(ioc3->emcr)
177 #define ioc3_w_emcr(v) do { ioc3->emcr = cpu_to_be32(v); } while (0)
178 #define ioc3_r_eisr() be32_to_cpu(ioc3->eisr)
179 #define ioc3_w_eisr(v) do { ioc3->eisr = cpu_to_be32(v); } while (0)
180 #define ioc3_r_eier() be32_to_cpu(ioc3->eier)
181 #define ioc3_w_eier(v) do { ioc3->eier = cpu_to_be32(v); } while (0)
182 #define ioc3_r_ercsr() be32_to_cpu(ioc3->ercsr)
183 #define ioc3_w_ercsr(v) do { ioc3->ercsr = cpu_to_be32(v); } while (0)
184 #define ioc3_r_erbr_h() be32_to_cpu(ioc3->erbr_h)
185 #define ioc3_w_erbr_h(v) do { ioc3->erbr_h = cpu_to_be32(v); } while (0)
186 #define ioc3_r_erbr_l() be32_to_cpu(ioc3->erbr_l)
187 #define ioc3_w_erbr_l(v) do { ioc3->erbr_l = cpu_to_be32(v); } while (0)
188 #define ioc3_r_erbar() be32_to_cpu(ioc3->erbar)
189 #define ioc3_w_erbar(v) do { ioc3->erbar = cpu_to_be32(v); } while (0)
190 #define ioc3_r_ercir() be32_to_cpu(ioc3->ercir)
191 #define ioc3_w_ercir(v) do { ioc3->ercir = cpu_to_be32(v); } while (0)
192 #define ioc3_r_erpir() be32_to_cpu(ioc3->erpir)
193 #define ioc3_w_erpir(v) do { ioc3->erpir = cpu_to_be32(v); } while (0)
194 #define ioc3_r_ertr() be32_to_cpu(ioc3->ertr)
195 #define ioc3_w_ertr(v) do { ioc3->ertr = cpu_to_be32(v); } while (0)
196 #define ioc3_r_etcsr() be32_to_cpu(ioc3->etcsr)
197 #define ioc3_w_etcsr(v) do { ioc3->etcsr = cpu_to_be32(v); } while (0)
198 #define ioc3_r_ersr() be32_to_cpu(ioc3->ersr)
199 #define ioc3_w_ersr(v) do { ioc3->ersr = cpu_to_be32(v); } while (0)
200 #define ioc3_r_etcdc() be32_to_cpu(ioc3->etcdc)
201 #define ioc3_w_etcdc(v) do { ioc3->etcdc = cpu_to_be32(v); } while (0)
202 #define ioc3_r_ebir() be32_to_cpu(ioc3->ebir)
203 #define ioc3_w_ebir(v) do { ioc3->ebir = cpu_to_be32(v); } while (0)
204 #define ioc3_r_etbr_h() be32_to_cpu(ioc3->etbr_h)
205 #define ioc3_w_etbr_h(v) do { ioc3->etbr_h = cpu_to_be32(v); } while (0)
206 #define ioc3_r_etbr_l() be32_to_cpu(ioc3->etbr_l)
207 #define ioc3_w_etbr_l(v) do { ioc3->etbr_l = cpu_to_be32(v); } while (0)
208 #define ioc3_r_etcir() be32_to_cpu(ioc3->etcir)
209 #define ioc3_w_etcir(v) do { ioc3->etcir = cpu_to_be32(v); } while (0)
210 #define ioc3_r_etpir() be32_to_cpu(ioc3->etpir)
211 #define ioc3_w_etpir(v) do { ioc3->etpir = cpu_to_be32(v); } while (0)
212 #define ioc3_r_emar_h() be32_to_cpu(ioc3->emar_h)
213 #define ioc3_w_emar_h(v) do { ioc3->emar_h = cpu_to_be32(v); } while (0)
214 #define ioc3_r_emar_l() be32_to_cpu(ioc3->emar_l)
215 #define ioc3_w_emar_l(v) do { ioc3->emar_l = cpu_to_be32(v); } while (0)
216 #define ioc3_r_ehar_h() be32_to_cpu(ioc3->ehar_h)
217 #define ioc3_w_ehar_h(v) do { ioc3->ehar_h = cpu_to_be32(v); } while (0)
218 #define ioc3_r_ehar_l() be32_to_cpu(ioc3->ehar_l)
219 #define ioc3_w_ehar_l(v) do { ioc3->ehar_l = cpu_to_be32(v); } while (0)
220 #define ioc3_r_micr() be32_to_cpu(ioc3->micr)
221 #define ioc3_w_micr(v) do { ioc3->micr = cpu_to_be32(v); } while (0)
222 #define ioc3_r_midr_r() be32_to_cpu(ioc3->midr_r)
223 #define ioc3_w_midr_r(v) do { ioc3->midr_r = cpu_to_be32(v); } while (0)
224 #define ioc3_r_midr_w() be32_to_cpu(ioc3->midr_w)
225 #define ioc3_w_midr_w(v) do { ioc3->midr_w = cpu_to_be32(v); } while (0)
227 static inline u32 mcr_pack(u32 pulse, u32 sample)
229 return (pulse << 10) | (sample << 2);
232 static int nic_wait(struct ioc3 *ioc3)
238 } while (!(mcr & 2));
243 static int nic_reset(struct ioc3 *ioc3)
247 ioc3_w_mcr(mcr_pack(500, 65));
248 presence = nic_wait(ioc3);
250 ioc3_w_mcr(mcr_pack(0, 500));
256 static inline int nic_read_bit(struct ioc3 *ioc3)
260 ioc3_w_mcr(mcr_pack(6, 13));
261 result = nic_wait(ioc3);
262 ioc3_w_mcr(mcr_pack(0, 100));
268 static inline void nic_write_bit(struct ioc3 *ioc3, int bit)
271 ioc3_w_mcr(mcr_pack(6, 110));
273 ioc3_w_mcr(mcr_pack(80, 30));
279 * Read a byte from an iButton device
281 static u32 nic_read_byte(struct ioc3 *ioc3)
286 for (i = 0; i < 8; i++)
287 result = (result >> 1) | (nic_read_bit(ioc3) << 7);
293 * Write a byte to an iButton device
295 static void nic_write_byte(struct ioc3 *ioc3, int byte)
299 for (i = 8; i; i--) {
303 nic_write_bit(ioc3, bit);
307 static u64 nic_find(struct ioc3 *ioc3, int *last)
309 int a, b, index, disc;
314 nic_write_byte(ioc3, 0xf0);
316 /* Algorithm from ``Book of iButton Standards''. */
317 for (index = 0, disc = 0; index < 64; index++) {
318 a = nic_read_bit(ioc3);
319 b = nic_read_bit(ioc3);
322 printk("NIC search failed (not fatal).\n");
328 if (index == *last) {
329 address |= 1UL << index;
330 } else if (index > *last) {
331 address &= ~(1UL << index);
333 } else if ((address & (1UL << index)) == 0)
335 nic_write_bit(ioc3, address & (1UL << index));
339 address |= 1UL << index;
341 address &= ~(1UL << index);
342 nic_write_bit(ioc3, a);
352 static int nic_init(struct ioc3 *ioc3)
354 const char *unknown = "unknown";
355 const char *type = unknown;
362 reg = nic_find(ioc3, &save);
364 switch (reg & 0xff) {
370 /* Let the caller try again. */
379 nic_write_byte(ioc3, 0x55);
380 for (i = 0; i < 8; i++)
381 nic_write_byte(ioc3, (reg >> (i << 3)) & 0xff);
383 reg >>= 8; /* Shift out type. */
384 for (i = 0; i < 6; i++) {
385 serial[i] = reg & 0xff;
392 printk("Found %s NIC", type);
393 if (type != unknown) {
394 printk (" registration number %02x:%02x:%02x:%02x:%02x:%02x,"
395 " CRC %02x", serial[0], serial[1], serial[2],
396 serial[3], serial[4], serial[5], crc);
404 * Read the NIC (Number-In-a-Can) device used to store the MAC address on
405 * SN0 / SN00 nodeboards and PCI cards.
407 static void ioc3_get_eaddr_nic(struct ioc3_private *ip)
409 struct ioc3 *ioc3 = ip->regs;
411 int tries = 2; /* There may be some problem with the battery? */
414 ioc3_w_gpcr_s(1 << 21);
423 printk("Failed to read MAC address\n");
428 nic_write_byte(ioc3, 0xf0);
429 nic_write_byte(ioc3, 0x00);
430 nic_write_byte(ioc3, 0x00);
432 for (i = 13; i >= 0; i--)
433 nic[i] = nic_read_byte(ioc3);
435 for (i = 2; i < 8; i++)
436 priv_netdev(ip)->dev_addr[i - 2] = nic[i];
440 * Ok, this is hosed by design. It's necessary to know what machine the
441 * NIC is in in order to know how to read the NIC address. We also have
442 * to know if it's a PCI card or a NIC in on the node board ...
444 static void ioc3_get_eaddr(struct ioc3_private *ip)
446 ioc3_get_eaddr_nic(ip);
448 printk("Ethernet address is %pM.\n", priv_netdev(ip)->dev_addr);
451 static void __ioc3_set_mac_address(struct net_device *dev)
453 struct ioc3_private *ip = netdev_priv(dev);
454 struct ioc3 *ioc3 = ip->regs;
456 ioc3_w_emar_h((dev->dev_addr[5] << 8) | dev->dev_addr[4]);
457 ioc3_w_emar_l((dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) |
458 (dev->dev_addr[1] << 8) | dev->dev_addr[0]);
461 static int ioc3_set_mac_address(struct net_device *dev, void *addr)
463 struct ioc3_private *ip = netdev_priv(dev);
464 struct sockaddr *sa = addr;
466 memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
468 spin_lock_irq(&ip->ioc3_lock);
469 __ioc3_set_mac_address(dev);
470 spin_unlock_irq(&ip->ioc3_lock);
476 * Caller must hold the ioc3_lock ever for MII readers. This is also
477 * used to protect the transmitter side but it's low contention.
479 static int ioc3_mdio_read(struct net_device *dev, int phy, int reg)
481 struct ioc3_private *ip = netdev_priv(dev);
482 struct ioc3 *ioc3 = ip->regs;
484 while (ioc3_r_micr() & MICR_BUSY);
485 ioc3_w_micr((phy << MICR_PHYADDR_SHIFT) | reg | MICR_READTRIG);
486 while (ioc3_r_micr() & MICR_BUSY);
488 return ioc3_r_midr_r() & MIDR_DATA_MASK;
491 static void ioc3_mdio_write(struct net_device *dev, int phy, int reg, int data)
493 struct ioc3_private *ip = netdev_priv(dev);
494 struct ioc3 *ioc3 = ip->regs;
496 while (ioc3_r_micr() & MICR_BUSY);
498 ioc3_w_micr((phy << MICR_PHYADDR_SHIFT) | reg);
499 while (ioc3_r_micr() & MICR_BUSY);
502 static int ioc3_mii_init(struct ioc3_private *ip);
504 static struct net_device_stats *ioc3_get_stats(struct net_device *dev)
506 struct ioc3_private *ip = netdev_priv(dev);
507 struct ioc3 *ioc3 = ip->regs;
509 ip->stats.collisions += (ioc3_r_etcdc() & ETCDC_COLLCNT_MASK);
513 static void ioc3_tcpudp_checksum(struct sk_buff *skb, uint32_t hwsum, int len)
515 struct ethhdr *eh = eth_hdr(skb);
516 uint32_t csum, ehsum;
523 * Did hardware handle the checksum at all? The cases we can handle
526 * - TCP and UDP checksums of IPv4 only.
527 * - IPv6 would be doable but we keep that for later ...
528 * - Only unfragmented packets. Did somebody already tell you
529 * fragmentation is evil?
530 * - don't care about packet size. Worst case when processing a
531 * malformed packet we'll try to access the packet at ip header +
532 * 64 bytes which is still inside the skb. Even in the unlikely
533 * case where the checksum is right the higher layers will still
534 * drop the packet as appropriate.
536 if (eh->h_proto != ntohs(ETH_P_IP))
539 ih = (struct iphdr *) ((char *)eh + ETH_HLEN);
540 if (ih->frag_off & htons(IP_MF | IP_OFFSET))
543 proto = ih->protocol;
544 if (proto != IPPROTO_TCP && proto != IPPROTO_UDP)
547 /* Same as tx - compute csum of pseudo header */
549 (ih->tot_len - (ih->ihl << 2)) +
550 htons((uint16_t)ih->protocol) +
551 (ih->saddr >> 16) + (ih->saddr & 0xffff) +
552 (ih->daddr >> 16) + (ih->daddr & 0xffff);
554 /* Sum up ethernet dest addr, src addr and protocol */
555 ew = (uint16_t *) eh;
556 ehsum = ew[0] + ew[1] + ew[2] + ew[3] + ew[4] + ew[5] + ew[6];
558 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
559 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
561 csum += 0xffff ^ ehsum;
563 /* In the next step we also subtract the 1's complement
564 checksum of the trailing ethernet CRC. */
565 cp = (char *)eh + len; /* points at trailing CRC */
567 csum += 0xffff ^ (uint16_t) ((cp[1] << 8) | cp[0]);
568 csum += 0xffff ^ (uint16_t) ((cp[3] << 8) | cp[2]);
570 csum += 0xffff ^ (uint16_t) ((cp[0] << 8) | cp[1]);
571 csum += 0xffff ^ (uint16_t) ((cp[2] << 8) | cp[3]);
574 csum = (csum & 0xffff) + (csum >> 16);
575 csum = (csum & 0xffff) + (csum >> 16);
578 skb->ip_summed = CHECKSUM_UNNECESSARY;
581 static inline void ioc3_rx(struct ioc3_private *ip)
583 struct sk_buff *skb, *new_skb;
584 struct ioc3 *ioc3 = ip->regs;
585 int rx_entry, n_entry, len;
586 struct ioc3_erxbuf *rxb;
590 rxr = (unsigned long *) ip->rxr; /* Ring base */
591 rx_entry = ip->rx_ci; /* RX consume index */
594 skb = ip->rx_skbs[rx_entry];
595 rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
596 w0 = be32_to_cpu(rxb->w0);
598 while (w0 & ERXBUF_V) {
599 err = be32_to_cpu(rxb->err); /* It's valid ... */
600 if (err & ERXBUF_GOODPKT) {
601 len = ((w0 >> ERXBUF_BYTECNT_SHIFT) & 0x7ff) - 4;
603 skb->protocol = eth_type_trans(skb, priv_netdev(ip));
605 new_skb = ioc3_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
607 /* Ouch, drop packet and just recycle packet
608 to keep the ring filled. */
609 ip->stats.rx_dropped++;
614 if (likely(ip->flags & IOC3_FLAG_RX_CHECKSUMS))
615 ioc3_tcpudp_checksum(skb,
616 w0 & ERXBUF_IPCKSUM_MASK, len);
620 ip->rx_skbs[rx_entry] = NULL; /* Poison */
622 /* Because we reserve afterwards. */
623 skb_put(new_skb, (1664 + RX_OFFSET));
624 rxb = (struct ioc3_erxbuf *) new_skb->data;
625 skb_reserve(new_skb, RX_OFFSET);
627 priv_netdev(ip)->last_rx = jiffies;
628 ip->stats.rx_packets++; /* Statistics */
629 ip->stats.rx_bytes += len;
631 /* The frame is invalid and the skb never
632 reached the network layer so we can just
635 ip->stats.rx_errors++;
637 if (err & ERXBUF_CRCERR) /* Statistics */
638 ip->stats.rx_crc_errors++;
639 if (err & ERXBUF_FRAMERR)
640 ip->stats.rx_frame_errors++;
642 ip->rx_skbs[n_entry] = new_skb;
643 rxr[n_entry] = cpu_to_be64(ioc3_map(rxb, 1));
644 rxb->w0 = 0; /* Clear valid flag */
645 n_entry = (n_entry + 1) & 511; /* Update erpir */
647 /* Now go on to the next ring entry. */
648 rx_entry = (rx_entry + 1) & 511;
649 skb = ip->rx_skbs[rx_entry];
650 rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
651 w0 = be32_to_cpu(rxb->w0);
653 ioc3_w_erpir((n_entry << 3) | ERPIR_ARM);
655 ip->rx_ci = rx_entry;
658 static inline void ioc3_tx(struct ioc3_private *ip)
660 unsigned long packets, bytes;
661 struct ioc3 *ioc3 = ip->regs;
662 int tx_entry, o_entry;
666 spin_lock(&ip->ioc3_lock);
667 etcir = ioc3_r_etcir();
669 tx_entry = (etcir >> 7) & 127;
674 while (o_entry != tx_entry) {
676 skb = ip->tx_skbs[o_entry];
678 dev_kfree_skb_irq(skb);
679 ip->tx_skbs[o_entry] = NULL;
681 o_entry = (o_entry + 1) & 127; /* Next */
683 etcir = ioc3_r_etcir(); /* More pkts sent? */
684 tx_entry = (etcir >> 7) & 127;
687 ip->stats.tx_packets += packets;
688 ip->stats.tx_bytes += bytes;
689 ip->txqlen -= packets;
691 if (ip->txqlen < 128)
692 netif_wake_queue(priv_netdev(ip));
695 spin_unlock(&ip->ioc3_lock);
699 * Deal with fatal IOC3 errors. This condition might be caused by a hard or
700 * software problems, so we should try to recover
701 * more gracefully if this ever happens. In theory we might be flooded
702 * with such error interrupts if something really goes wrong, so we might
703 * also consider to take the interface down.
705 static void ioc3_error(struct ioc3_private *ip, u32 eisr)
707 struct net_device *dev = priv_netdev(ip);
708 unsigned char *iface = dev->name;
710 spin_lock(&ip->ioc3_lock);
712 if (eisr & EISR_RXOFLO)
713 printk(KERN_ERR "%s: RX overflow.\n", iface);
714 if (eisr & EISR_RXBUFOFLO)
715 printk(KERN_ERR "%s: RX buffer overflow.\n", iface);
716 if (eisr & EISR_RXMEMERR)
717 printk(KERN_ERR "%s: RX PCI error.\n", iface);
718 if (eisr & EISR_RXPARERR)
719 printk(KERN_ERR "%s: RX SSRAM parity error.\n", iface);
720 if (eisr & EISR_TXBUFUFLO)
721 printk(KERN_ERR "%s: TX buffer underflow.\n", iface);
722 if (eisr & EISR_TXMEMERR)
723 printk(KERN_ERR "%s: TX PCI error.\n", iface);
729 netif_wake_queue(dev);
731 spin_unlock(&ip->ioc3_lock);
734 /* The interrupt handler does all of the Rx thread work and cleans up
735 after the Tx thread. */
736 static irqreturn_t ioc3_interrupt(int irq, void *_dev)
738 struct net_device *dev = (struct net_device *)_dev;
739 struct ioc3_private *ip = netdev_priv(dev);
740 struct ioc3 *ioc3 = ip->regs;
741 const u32 enabled = EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO |
742 EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO |
743 EISR_TXEXPLICIT | EISR_TXMEMERR;
746 eisr = ioc3_r_eisr() & enabled;
749 (void) ioc3_r_eisr(); /* Flush */
751 if (eisr & (EISR_RXOFLO | EISR_RXBUFOFLO | EISR_RXMEMERR |
752 EISR_RXPARERR | EISR_TXBUFUFLO | EISR_TXMEMERR))
753 ioc3_error(ip, eisr);
754 if (eisr & EISR_RXTIMERINT)
756 if (eisr & EISR_TXEXPLICIT)
762 static inline void ioc3_setup_duplex(struct ioc3_private *ip)
764 struct ioc3 *ioc3 = ip->regs;
766 if (ip->mii.full_duplex) {
767 ioc3_w_etcsr(ETCSR_FD);
768 ip->emcr |= EMCR_DUPLEX;
770 ioc3_w_etcsr(ETCSR_HD);
771 ip->emcr &= ~EMCR_DUPLEX;
773 ioc3_w_emcr(ip->emcr);
776 static void ioc3_timer(unsigned long data)
778 struct ioc3_private *ip = (struct ioc3_private *) data;
780 /* Print the link status if it has changed */
781 mii_check_media(&ip->mii, 1, 0);
782 ioc3_setup_duplex(ip);
784 ip->ioc3_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2s */
785 add_timer(&ip->ioc3_timer);
789 * Try to find a PHY. There is no apparent relation between the MII addresses
790 * in the SGI documentation and what we find in reality, so we simply probe
791 * for the PHY. It seems IOC3 PHYs usually live on address 31. One of my
792 * onboard IOC3s has the special oddity that probing doesn't seem to find it
793 * yet the interface seems to work fine, so if probing fails we for now will
794 * simply default to PHY 31 instead of bailing out.
796 static int ioc3_mii_init(struct ioc3_private *ip)
798 struct net_device *dev = priv_netdev(ip);
799 int i, found = 0, res = 0;
800 int ioc3_phy_workaround = 1;
803 for (i = 0; i < 32; i++) {
804 word = ioc3_mdio_read(dev, i, MII_PHYSID1);
806 if (word != 0xffff && word != 0x0000) {
808 break; /* Found a PHY */
813 if (ioc3_phy_workaround)
828 static void ioc3_mii_start(struct ioc3_private *ip)
830 ip->ioc3_timer.expires = jiffies + (12 * HZ)/10; /* 1.2 sec. */
831 ip->ioc3_timer.data = (unsigned long) ip;
832 ip->ioc3_timer.function = &ioc3_timer;
833 add_timer(&ip->ioc3_timer);
836 static inline void ioc3_clean_rx_ring(struct ioc3_private *ip)
841 for (i = ip->rx_ci; i & 15; i++) {
842 ip->rx_skbs[ip->rx_pi] = ip->rx_skbs[ip->rx_ci];
843 ip->rxr[ip->rx_pi++] = ip->rxr[ip->rx_ci++];
848 for (i = ip->rx_ci; i != ip->rx_pi; i = (i+1) & 511) {
849 struct ioc3_erxbuf *rxb;
850 skb = ip->rx_skbs[i];
851 rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
856 static inline void ioc3_clean_tx_ring(struct ioc3_private *ip)
861 for (i=0; i < 128; i++) {
862 skb = ip->tx_skbs[i];
864 ip->tx_skbs[i] = NULL;
865 dev_kfree_skb_any(skb);
873 static void ioc3_free_rings(struct ioc3_private *ip)
876 int rx_entry, n_entry;
879 ioc3_clean_tx_ring(ip);
880 free_pages((unsigned long)ip->txr, 2);
886 rx_entry = ip->rx_pi;
888 while (n_entry != rx_entry) {
889 skb = ip->rx_skbs[n_entry];
891 dev_kfree_skb_any(skb);
893 n_entry = (n_entry + 1) & 511;
895 free_page((unsigned long)ip->rxr);
900 static void ioc3_alloc_rings(struct net_device *dev)
902 struct ioc3_private *ip = netdev_priv(dev);
903 struct ioc3_erxbuf *rxb;
907 if (ip->rxr == NULL) {
908 /* Allocate and initialize rx ring. 4kb = 512 entries */
909 ip->rxr = (unsigned long *) get_zeroed_page(GFP_ATOMIC);
910 rxr = (unsigned long *) ip->rxr;
912 printk("ioc3_alloc_rings(): get_zeroed_page() failed!\n");
914 /* Now the rx buffers. The RX ring may be larger but
915 we only allocate 16 buffers for now. Need to tune
916 this for performance and memory later. */
917 for (i = 0; i < RX_BUFFS; i++) {
920 skb = ioc3_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
926 ip->rx_skbs[i] = skb;
928 /* Because we reserve afterwards. */
929 skb_put(skb, (1664 + RX_OFFSET));
930 rxb = (struct ioc3_erxbuf *) skb->data;
931 rxr[i] = cpu_to_be64(ioc3_map(rxb, 1));
932 skb_reserve(skb, RX_OFFSET);
935 ip->rx_pi = RX_BUFFS;
938 if (ip->txr == NULL) {
939 /* Allocate and initialize tx rings. 16kb = 128 bufs. */
940 ip->txr = (struct ioc3_etxd *)__get_free_pages(GFP_KERNEL, 2);
942 printk("ioc3_alloc_rings(): __get_free_pages() failed!\n");
948 static void ioc3_init_rings(struct net_device *dev)
950 struct ioc3_private *ip = netdev_priv(dev);
951 struct ioc3 *ioc3 = ip->regs;
955 ioc3_alloc_rings(dev);
957 ioc3_clean_rx_ring(ip);
958 ioc3_clean_tx_ring(ip);
960 /* Now the rx ring base, consume & produce registers. */
961 ring = ioc3_map(ip->rxr, 0);
962 ioc3_w_erbr_h(ring >> 32);
963 ioc3_w_erbr_l(ring & 0xffffffff);
964 ioc3_w_ercir(ip->rx_ci << 3);
965 ioc3_w_erpir((ip->rx_pi << 3) | ERPIR_ARM);
967 ring = ioc3_map(ip->txr, 0);
969 ip->txqlen = 0; /* nothing queued */
971 /* Now the tx ring base, consume & produce registers. */
972 ioc3_w_etbr_h(ring >> 32);
973 ioc3_w_etbr_l(ring & 0xffffffff);
974 ioc3_w_etpir(ip->tx_pi << 7);
975 ioc3_w_etcir(ip->tx_ci << 7);
976 (void) ioc3_r_etcir(); /* Flush */
979 static inline void ioc3_ssram_disc(struct ioc3_private *ip)
981 struct ioc3 *ioc3 = ip->regs;
982 volatile u32 *ssram0 = &ioc3->ssram[0x0000];
983 volatile u32 *ssram1 = &ioc3->ssram[0x4000];
984 unsigned int pattern = 0x5555;
986 /* Assume the larger size SSRAM and enable parity checking */
987 ioc3_w_emcr(ioc3_r_emcr() | (EMCR_BUFSIZ | EMCR_RAMPAR));
990 *ssram1 = ~pattern & IOC3_SSRAM_DM;
992 if ((*ssram0 & IOC3_SSRAM_DM) != pattern ||
993 (*ssram1 & IOC3_SSRAM_DM) != (~pattern & IOC3_SSRAM_DM)) {
994 /* set ssram size to 64 KB */
995 ip->emcr = EMCR_RAMPAR;
996 ioc3_w_emcr(ioc3_r_emcr() & ~EMCR_BUFSIZ);
998 ip->emcr = EMCR_BUFSIZ | EMCR_RAMPAR;
1001 static void ioc3_init(struct net_device *dev)
1003 struct ioc3_private *ip = netdev_priv(dev);
1004 struct ioc3 *ioc3 = ip->regs;
1006 del_timer_sync(&ip->ioc3_timer); /* Kill if running */
1008 ioc3_w_emcr(EMCR_RST); /* Reset */
1009 (void) ioc3_r_emcr(); /* Flush WB */
1010 udelay(4); /* Give it time ... */
1012 (void) ioc3_r_emcr();
1014 /* Misc registers */
1015 #ifdef CONFIG_SGI_IP27
1016 ioc3_w_erbar(PCI64_ATTR_BAR >> 32); /* Barrier on last store */
1018 ioc3_w_erbar(0); /* Let PCI API get it right */
1020 (void) ioc3_r_etcdc(); /* Clear on read */
1021 ioc3_w_ercsr(15); /* RX low watermark */
1022 ioc3_w_ertr(0); /* Interrupt immediately */
1023 __ioc3_set_mac_address(dev);
1024 ioc3_w_ehar_h(ip->ehar_h);
1025 ioc3_w_ehar_l(ip->ehar_l);
1026 ioc3_w_ersr(42); /* XXX should be random */
1028 ioc3_init_rings(dev);
1030 ip->emcr |= ((RX_OFFSET / 2) << EMCR_RXOFF_SHIFT) | EMCR_TXDMAEN |
1031 EMCR_TXEN | EMCR_RXDMAEN | EMCR_RXEN | EMCR_PADEN;
1032 ioc3_w_emcr(ip->emcr);
1033 ioc3_w_eier(EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO |
1034 EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO |
1035 EISR_TXEXPLICIT | EISR_TXMEMERR);
1036 (void) ioc3_r_eier();
1039 static inline void ioc3_stop(struct ioc3_private *ip)
1041 struct ioc3 *ioc3 = ip->regs;
1043 ioc3_w_emcr(0); /* Shutup */
1044 ioc3_w_eier(0); /* Disable interrupts */
1045 (void) ioc3_r_eier(); /* Flush */
1048 static int ioc3_open(struct net_device *dev)
1050 struct ioc3_private *ip = netdev_priv(dev);
1052 if (request_irq(dev->irq, ioc3_interrupt, IRQF_SHARED, ioc3_str, dev)) {
1053 printk(KERN_ERR "%s: Can't get irq %d\n", dev->name, dev->irq);
1063 netif_start_queue(dev);
1067 static int ioc3_close(struct net_device *dev)
1069 struct ioc3_private *ip = netdev_priv(dev);
1071 del_timer_sync(&ip->ioc3_timer);
1073 netif_stop_queue(dev);
1076 free_irq(dev->irq, dev);
1078 ioc3_free_rings(ip);
1083 * MENET cards have four IOC3 chips, which are attached to two sets of
1084 * PCI slot resources each: the primary connections are on slots
1085 * 0..3 and the secondaries are on 4..7
1087 * All four ethernets are brought out to connectors; six serial ports
1088 * (a pair from each of the first three IOC3s) are brought out to
1089 * MiniDINs; all other subdevices are left swinging in the wind, leave
1093 static int ioc3_adjacent_is_ioc3(struct pci_dev *pdev, int slot)
1095 struct pci_dev *dev = pci_get_slot(pdev->bus, PCI_DEVFN(slot, 0));
1099 if (dev->vendor == PCI_VENDOR_ID_SGI &&
1100 dev->device == PCI_DEVICE_ID_SGI_IOC3)
1108 static int ioc3_is_menet(struct pci_dev *pdev)
1110 return pdev->bus->parent == NULL &&
1111 ioc3_adjacent_is_ioc3(pdev, 0) &&
1112 ioc3_adjacent_is_ioc3(pdev, 1) &&
1113 ioc3_adjacent_is_ioc3(pdev, 2);
1116 #ifdef CONFIG_SERIAL_8250
1118 * Note about serial ports and consoles:
1119 * For console output, everyone uses the IOC3 UARTA (offset 0x178)
1120 * connected to the master node (look in ip27_setup_console() and
1121 * ip27prom_console_write()).
1123 * For serial (/dev/ttyS0 etc), we can not have hardcoded serial port
1124 * addresses on a partitioned machine. Since we currently use the ioc3
1125 * serial ports, we use dynamic serial port discovery that the serial.c
1126 * driver uses for pci/pnp ports (there is an entry for the SGI ioc3
1127 * boards in pci_boards[]). Unfortunately, UARTA's pio address is greater
1128 * than UARTB's, although UARTA on o200s has traditionally been known as
1129 * port 0. So, we just use one serial port from each ioc3 (since the
1130 * serial driver adds addresses to get to higher ports).
1132 * The first one to do a register_console becomes the preferred console
1133 * (if there is no kernel command line console= directive). /dev/console
1134 * (ie 5, 1) is then "aliased" into the device number returned by the
1135 * "device" routine referred to in this console structure
1136 * (ip27prom_console_dev).
1138 * Also look in ip27-pci.c:pci_fixup_ioc3() for some comments on working
1139 * around ioc3 oddities in this respect.
1141 * The IOC3 serials use a 22MHz clock rate with an additional divider which
1142 * can be programmed in the SCR register if the DLAB bit is set.
1144 * Register to interrupt zero because we share the interrupt with
1145 * the serial driver which we don't properly support yet.
1147 * Can't use UPF_IOREMAP as the whole of IOC3 resources have already been
1150 static void __devinit ioc3_8250_register(struct ioc3_uartregs __iomem *uart)
1152 #define COSMISC_CONSTANT 6
1154 struct uart_port port = {
1156 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
1159 .uartclk = (22000000 << 1) / COSMISC_CONSTANT,
1161 .membase = (unsigned char __iomem *) uart,
1162 .mapbase = (unsigned long) uart,
1167 uart->iu_lcr = lcr | UART_LCR_DLAB;
1168 uart->iu_scr = COSMISC_CONSTANT,
1171 serial8250_register_port(&port);
1174 static void __devinit ioc3_serial_probe(struct pci_dev *pdev, struct ioc3 *ioc3)
1177 * We need to recognice and treat the fourth MENET serial as it
1178 * does not have an SuperIO chip attached to it, therefore attempting
1179 * to access it will result in bus errors. We call something an
1180 * MENET if PCI slot 0, 1, 2 and 3 of a master PCI bus all have an IOC3
1181 * in it. This is paranoid but we want to avoid blowing up on a
1182 * showhorn PCI box that happens to have 4 IOC3 cards in it so it's
1183 * not paranoid enough ...
1185 if (ioc3_is_menet(pdev) && PCI_SLOT(pdev->devfn) == 3)
1189 * Switch IOC3 to PIO mode. It probably already was but let's be
1192 ioc3->gpcr_s = GPCR_UARTA_MODESEL | GPCR_UARTB_MODESEL;
1198 ioc3->sscr_a = ioc3->sscr_a & ~SSCR_DMA_EN;
1200 ioc3->sscr_b = ioc3->sscr_b & ~SSCR_DMA_EN;
1202 /* Disable all SA/B interrupts except for SA/B_INT in SIO_IEC. */
1203 ioc3->sio_iec &= ~ (SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL |
1204 SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER |
1205 SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS |
1206 SIO_IR_SA_TX_EXPLICIT | SIO_IR_SA_MEMERR);
1207 ioc3->sio_iec |= SIO_IR_SA_INT;
1209 ioc3->sio_iec &= ~ (SIO_IR_SB_TX_MT | SIO_IR_SB_RX_FULL |
1210 SIO_IR_SB_RX_HIGH | SIO_IR_SB_RX_TIMER |
1211 SIO_IR_SB_DELTA_DCD | SIO_IR_SB_DELTA_CTS |
1212 SIO_IR_SB_TX_EXPLICIT | SIO_IR_SB_MEMERR);
1213 ioc3->sio_iec |= SIO_IR_SB_INT;
1216 ioc3_8250_register(&ioc3->sregs.uarta);
1217 ioc3_8250_register(&ioc3->sregs.uartb);
1221 static int __devinit ioc3_probe(struct pci_dev *pdev,
1222 const struct pci_device_id *ent)
1224 unsigned int sw_physid1, sw_physid2;
1225 struct net_device *dev = NULL;
1226 struct ioc3_private *ip;
1228 unsigned long ioc3_base, ioc3_size;
1229 u32 vendor, model, rev;
1230 int err, pci_using_dac;
1232 /* Configure DMA attributes. */
1233 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1236 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1238 printk(KERN_ERR "%s: Unable to obtain 64 bit DMA "
1239 "for consistent allocations\n", pci_name(pdev));
1243 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1245 printk(KERN_ERR "%s: No usable DMA configuration, "
1246 "aborting.\n", pci_name(pdev));
1252 if (pci_enable_device(pdev))
1255 dev = alloc_etherdev(sizeof(struct ioc3_private));
1262 dev->features |= NETIF_F_HIGHDMA;
1264 err = pci_request_regions(pdev, "ioc3");
1268 SET_NETDEV_DEV(dev, &pdev->dev);
1270 ip = netdev_priv(dev);
1272 dev->irq = pdev->irq;
1274 ioc3_base = pci_resource_start(pdev, 0);
1275 ioc3_size = pci_resource_len(pdev, 0);
1276 ioc3 = (struct ioc3 *) ioremap(ioc3_base, ioc3_size);
1278 printk(KERN_CRIT "ioc3eth(%s): ioremap failed, goodbye.\n",
1285 #ifdef CONFIG_SERIAL_8250
1286 ioc3_serial_probe(pdev, ioc3);
1289 spin_lock_init(&ip->ioc3_lock);
1290 init_timer(&ip->ioc3_timer);
1297 ip->mii.phy_id_mask = 0x1f;
1298 ip->mii.reg_num_mask = 0x1f;
1300 ip->mii.mdio_read = ioc3_mdio_read;
1301 ip->mii.mdio_write = ioc3_mdio_write;
1305 if (ip->mii.phy_id == -1) {
1306 printk(KERN_CRIT "ioc3-eth(%s): Didn't find a PHY, goodbye.\n",
1313 ioc3_ssram_disc(ip);
1316 /* The IOC3-specific entries in the device structure. */
1317 dev->open = ioc3_open;
1318 dev->hard_start_xmit = ioc3_start_xmit;
1319 dev->tx_timeout = ioc3_timeout;
1320 dev->watchdog_timeo = 5 * HZ;
1321 dev->stop = ioc3_close;
1322 dev->get_stats = ioc3_get_stats;
1323 dev->do_ioctl = ioc3_ioctl;
1324 dev->set_multicast_list = ioc3_set_multicast_list;
1325 dev->set_mac_address = ioc3_set_mac_address;
1326 dev->ethtool_ops = &ioc3_ethtool_ops;
1327 dev->features = NETIF_F_IP_CSUM;
1329 sw_physid1 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID1);
1330 sw_physid2 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID2);
1332 err = register_netdev(dev);
1336 mii_check_media(&ip->mii, 1, 1);
1337 ioc3_setup_duplex(ip);
1339 vendor = (sw_physid1 << 12) | (sw_physid2 >> 4);
1340 model = (sw_physid2 >> 4) & 0x3f;
1341 rev = sw_physid2 & 0xf;
1342 printk(KERN_INFO "%s: Using PHY %d, vendor 0x%x, model %d, "
1343 "rev %d.\n", dev->name, ip->mii.phy_id, vendor, model, rev);
1344 printk(KERN_INFO "%s: IOC3 SSRAM has %d kbyte.\n", dev->name,
1345 ip->emcr & EMCR_BUFSIZ ? 128 : 64);
1351 del_timer_sync(&ip->ioc3_timer);
1352 ioc3_free_rings(ip);
1354 pci_release_regions(pdev);
1359 * We should call pci_disable_device(pdev); here if the IOC3 wasn't
1360 * such a weird device ...
1366 static void __devexit ioc3_remove_one (struct pci_dev *pdev)
1368 struct net_device *dev = pci_get_drvdata(pdev);
1369 struct ioc3_private *ip = netdev_priv(dev);
1370 struct ioc3 *ioc3 = ip->regs;
1372 unregister_netdev(dev);
1373 del_timer_sync(&ip->ioc3_timer);
1376 pci_release_regions(pdev);
1379 * We should call pci_disable_device(pdev); here if the IOC3 wasn't
1380 * such a weird device ...
1384 static struct pci_device_id ioc3_pci_tbl[] = {
1385 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, PCI_ANY_ID, PCI_ANY_ID },
1388 MODULE_DEVICE_TABLE(pci, ioc3_pci_tbl);
1390 static struct pci_driver ioc3_driver = {
1392 .id_table = ioc3_pci_tbl,
1393 .probe = ioc3_probe,
1394 .remove = __devexit_p(ioc3_remove_one),
1397 static int __init ioc3_init_module(void)
1399 return pci_register_driver(&ioc3_driver);
1402 static void __exit ioc3_cleanup_module(void)
1404 pci_unregister_driver(&ioc3_driver);
1407 static int ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev)
1410 struct ioc3_private *ip = netdev_priv(dev);
1411 struct ioc3 *ioc3 = ip->regs;
1413 struct ioc3_etxd *desc;
1418 * IOC3 has a fairly simple minded checksumming hardware which simply
1419 * adds up the 1's complement checksum for the entire packet and
1420 * inserts it at an offset which can be specified in the descriptor
1421 * into the transmit packet. This means we have to compensate for the
1422 * MAC header which should not be summed and the TCP/UDP pseudo headers
1425 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1426 const struct iphdr *ih = ip_hdr(skb);
1427 const int proto = ntohs(ih->protocol);
1429 uint32_t csum, ehsum;
1432 /* The MAC header. skb->mac seem the logic approach
1433 to find the MAC header - except it's a NULL pointer ... */
1434 eh = (uint16_t *) skb->data;
1436 /* Sum up dest addr, src addr and protocol */
1437 ehsum = eh[0] + eh[1] + eh[2] + eh[3] + eh[4] + eh[5] + eh[6];
1439 /* Fold ehsum. can't use csum_fold which negates also ... */
1440 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
1441 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
1443 /* Skip IP header; it's sum is always zero and was
1444 already filled in by ip_output.c */
1445 csum = csum_tcpudp_nofold(ih->saddr, ih->daddr,
1446 ih->tot_len - (ih->ihl << 2),
1447 proto, 0xffff ^ ehsum);
1449 csum = (csum & 0xffff) + (csum >> 16); /* Fold again */
1450 csum = (csum & 0xffff) + (csum >> 16);
1452 csoff = ETH_HLEN + (ih->ihl << 2);
1453 if (proto == IPPROTO_UDP) {
1454 csoff += offsetof(struct udphdr, check);
1455 udp_hdr(skb)->check = csum;
1457 if (proto == IPPROTO_TCP) {
1458 csoff += offsetof(struct tcphdr, check);
1459 tcp_hdr(skb)->check = csum;
1462 w0 = ETXD_DOCHECKSUM | (csoff << ETXD_CHKOFF_SHIFT);
1465 spin_lock_irq(&ip->ioc3_lock);
1467 data = (unsigned long) skb->data;
1470 produce = ip->tx_pi;
1471 desc = &ip->txr[produce];
1474 /* Short packet, let's copy it directly into the ring. */
1475 skb_copy_from_linear_data(skb, desc->data, skb->len);
1476 if (len < ETH_ZLEN) {
1477 /* Very short packet, pad with zeros at the end. */
1478 memset(desc->data + len, 0, ETH_ZLEN - len);
1481 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_D0V | w0);
1482 desc->bufcnt = cpu_to_be32(len);
1483 } else if ((data ^ (data + len - 1)) & 0x4000) {
1484 unsigned long b2 = (data | 0x3fffUL) + 1UL;
1485 unsigned long s1 = b2 - data;
1486 unsigned long s2 = data + len - b2;
1488 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE |
1489 ETXD_B1V | ETXD_B2V | w0);
1490 desc->bufcnt = cpu_to_be32((s1 << ETXD_B1CNT_SHIFT) |
1491 (s2 << ETXD_B2CNT_SHIFT));
1492 desc->p1 = cpu_to_be64(ioc3_map(skb->data, 1));
1493 desc->p2 = cpu_to_be64(ioc3_map((void *) b2, 1));
1495 /* Normal sized packet that doesn't cross a page boundary. */
1496 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_B1V | w0);
1497 desc->bufcnt = cpu_to_be32(len << ETXD_B1CNT_SHIFT);
1498 desc->p1 = cpu_to_be64(ioc3_map(skb->data, 1));
1503 dev->trans_start = jiffies;
1504 ip->tx_skbs[produce] = skb; /* Remember skb */
1505 produce = (produce + 1) & 127;
1506 ip->tx_pi = produce;
1507 ioc3_w_etpir(produce << 7); /* Fire ... */
1511 if (ip->txqlen >= 127)
1512 netif_stop_queue(dev);
1514 spin_unlock_irq(&ip->ioc3_lock);
1519 static void ioc3_timeout(struct net_device *dev)
1521 struct ioc3_private *ip = netdev_priv(dev);
1523 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
1525 spin_lock_irq(&ip->ioc3_lock);
1532 spin_unlock_irq(&ip->ioc3_lock);
1534 netif_wake_queue(dev);
1538 * Given a multicast ethernet address, this routine calculates the
1539 * address's bit index in the logical address filter mask
1542 static inline unsigned int ioc3_hash(const unsigned char *addr)
1544 unsigned int temp = 0;
1548 crc = ether_crc_le(ETH_ALEN, addr);
1550 crc &= 0x3f; /* bit reverse lowest 6 bits for hash index */
1551 for (bits = 6; --bits >= 0; ) {
1553 temp |= (crc & 0x1);
1560 static void ioc3_get_drvinfo (struct net_device *dev,
1561 struct ethtool_drvinfo *info)
1563 struct ioc3_private *ip = netdev_priv(dev);
1565 strcpy (info->driver, IOC3_NAME);
1566 strcpy (info->version, IOC3_VERSION);
1567 strcpy (info->bus_info, pci_name(ip->pdev));
1570 static int ioc3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1572 struct ioc3_private *ip = netdev_priv(dev);
1575 spin_lock_irq(&ip->ioc3_lock);
1576 rc = mii_ethtool_gset(&ip->mii, cmd);
1577 spin_unlock_irq(&ip->ioc3_lock);
1582 static int ioc3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1584 struct ioc3_private *ip = netdev_priv(dev);
1587 spin_lock_irq(&ip->ioc3_lock);
1588 rc = mii_ethtool_sset(&ip->mii, cmd);
1589 spin_unlock_irq(&ip->ioc3_lock);
1594 static int ioc3_nway_reset(struct net_device *dev)
1596 struct ioc3_private *ip = netdev_priv(dev);
1599 spin_lock_irq(&ip->ioc3_lock);
1600 rc = mii_nway_restart(&ip->mii);
1601 spin_unlock_irq(&ip->ioc3_lock);
1606 static u32 ioc3_get_link(struct net_device *dev)
1608 struct ioc3_private *ip = netdev_priv(dev);
1611 spin_lock_irq(&ip->ioc3_lock);
1612 rc = mii_link_ok(&ip->mii);
1613 spin_unlock_irq(&ip->ioc3_lock);
1618 static u32 ioc3_get_rx_csum(struct net_device *dev)
1620 struct ioc3_private *ip = netdev_priv(dev);
1622 return ip->flags & IOC3_FLAG_RX_CHECKSUMS;
1625 static int ioc3_set_rx_csum(struct net_device *dev, u32 data)
1627 struct ioc3_private *ip = netdev_priv(dev);
1629 spin_lock_bh(&ip->ioc3_lock);
1631 ip->flags |= IOC3_FLAG_RX_CHECKSUMS;
1633 ip->flags &= ~IOC3_FLAG_RX_CHECKSUMS;
1634 spin_unlock_bh(&ip->ioc3_lock);
1639 static const struct ethtool_ops ioc3_ethtool_ops = {
1640 .get_drvinfo = ioc3_get_drvinfo,
1641 .get_settings = ioc3_get_settings,
1642 .set_settings = ioc3_set_settings,
1643 .nway_reset = ioc3_nway_reset,
1644 .get_link = ioc3_get_link,
1645 .get_rx_csum = ioc3_get_rx_csum,
1646 .set_rx_csum = ioc3_set_rx_csum,
1647 .get_tx_csum = ethtool_op_get_tx_csum,
1648 .set_tx_csum = ethtool_op_set_tx_csum
1651 static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1653 struct ioc3_private *ip = netdev_priv(dev);
1656 spin_lock_irq(&ip->ioc3_lock);
1657 rc = generic_mii_ioctl(&ip->mii, if_mii(rq), cmd, NULL);
1658 spin_unlock_irq(&ip->ioc3_lock);
1663 static void ioc3_set_multicast_list(struct net_device *dev)
1665 struct dev_mc_list *dmi = dev->mc_list;
1666 struct ioc3_private *ip = netdev_priv(dev);
1667 struct ioc3 *ioc3 = ip->regs;
1671 netif_stop_queue(dev); /* Lock out others. */
1673 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1674 ip->emcr |= EMCR_PROMISC;
1675 ioc3_w_emcr(ip->emcr);
1676 (void) ioc3_r_emcr();
1678 ip->emcr &= ~EMCR_PROMISC;
1679 ioc3_w_emcr(ip->emcr); /* Clear promiscuous. */
1680 (void) ioc3_r_emcr();
1682 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
1683 /* Too many for hashing to make sense or we want all
1684 multicast packets anyway, so skip computing all the
1685 hashes and just accept all packets. */
1686 ip->ehar_h = 0xffffffff;
1687 ip->ehar_l = 0xffffffff;
1689 for (i = 0; i < dev->mc_count; i++) {
1690 char *addr = dmi->dmi_addr;
1696 ehar |= (1UL << ioc3_hash(addr));
1698 ip->ehar_h = ehar >> 32;
1699 ip->ehar_l = ehar & 0xffffffff;
1701 ioc3_w_ehar_h(ip->ehar_h);
1702 ioc3_w_ehar_l(ip->ehar_l);
1705 netif_wake_queue(dev); /* Let us get going again. */
1708 MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
1709 MODULE_DESCRIPTION("SGI IOC3 Ethernet driver");
1710 MODULE_LICENSE("GPL");
1712 module_init(ioc3_init_module);
1713 module_exit(ioc3_cleanup_module);