2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Driver for SGI's IOC3 based Ethernet cards as found in the PCI card.
8 * Copyright (C) 1999, 2000, 2001, 2003 Ralf Baechle
9 * Copyright (C) 1995, 1999, 2000, 2001 by Silicon Graphics, Inc.
12 * o IOC3 ASIC specification 4.51, 1996-04-18
13 * o IEEE 802.3 specification, 2000 edition
14 * o DP38840A Specification, National Semiconductor, March 1997
18 * o Handle allocation failures in ioc3_alloc_skb() more gracefully.
19 * o Handle allocation failures in ioc3_init_rings().
20 * o Use prefetching for large packets. What is a good lower limit for
22 * o We're probably allocating a bit too much memory.
23 * o Use hardware checksums.
24 * o Convert to using a IOC3 meta driver.
25 * o Which PHYs might possibly be attached to the IOC3 in real live,
26 * which workarounds are required for them? Do we ever have Lucent's?
27 * o For the 2.5 branch kill the mii-tool ioctls.
30 #define IOC3_NAME "ioc3-eth"
31 #define IOC3_VERSION "2.6.3-4"
33 #include <linux/init.h>
34 #include <linux/delay.h>
35 #include <linux/kernel.h>
37 #include <linux/errno.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/crc32.h>
41 #include <linux/mii.h>
44 #include <linux/tcp.h>
45 #include <linux/udp.h>
46 #include <linux/dma-mapping.h>
48 #ifdef CONFIG_SERIAL_8250
49 #include <linux/serial_core.h>
50 #include <linux/serial_8250.h>
53 #include <linux/netdevice.h>
54 #include <linux/etherdevice.h>
55 #include <linux/ethtool.h>
56 #include <linux/skbuff.h>
59 #include <asm/byteorder.h>
61 #include <asm/pgtable.h>
62 #include <asm/uaccess.h>
63 #include <asm/sn/types.h>
64 #include <asm/sn/sn0/addrs.h>
65 #include <asm/sn/sn0/hubni.h>
66 #include <asm/sn/sn0/hubio.h>
67 #include <asm/sn/klconfig.h>
68 #include <asm/sn/ioc3.h>
69 #include <asm/sn/sn0/ip27.h>
70 #include <asm/pci/bridge.h>
73 * 64 RX buffers. This is tunable in the range of 16 <= x < 512. The
74 * value must be a power of two.
78 #define ETCSR_FD ((17<<ETCSR_IPGR2_SHIFT) | (11<<ETCSR_IPGR1_SHIFT) | 21)
79 #define ETCSR_HD ((21<<ETCSR_IPGR2_SHIFT) | (21<<ETCSR_IPGR1_SHIFT) | 21)
81 /* Private per NIC data of the driver. */
84 unsigned long *rxr; /* pointer to receiver ring */
85 struct ioc3_etxd *txr;
86 struct sk_buff *rx_skbs[512];
87 struct sk_buff *tx_skbs[128];
88 struct net_device_stats stats;
89 int rx_ci; /* RX consumer index */
90 int rx_pi; /* RX producer index */
91 int tx_ci; /* TX consumer index */
92 int tx_pi; /* TX producer index */
94 u32 emcr, ehar_h, ehar_l;
96 struct mii_if_info mii;
99 /* Members used by autonegotiation */
100 struct timer_list ioc3_timer;
103 static inline struct net_device *priv_netdev(struct ioc3_private *dev)
105 return (void *)dev - ((sizeof(struct net_device) + 31) & ~31);
108 static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
109 static void ioc3_set_multicast_list(struct net_device *dev);
110 static int ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev);
111 static void ioc3_timeout(struct net_device *dev);
112 static inline unsigned int ioc3_hash(const unsigned char *addr);
113 static inline void ioc3_stop(struct ioc3_private *ip);
114 static void ioc3_init(struct net_device *dev);
116 static const char ioc3_str[] = "IOC3 Ethernet";
117 static const struct ethtool_ops ioc3_ethtool_ops;
119 /* We use this to acquire receive skb's that we can DMA directly into. */
121 #define IOC3_CACHELINE 128UL
123 static inline unsigned long aligned_rx_skb_addr(unsigned long addr)
125 return (~addr + 1) & (IOC3_CACHELINE - 1UL);
128 static inline struct sk_buff * ioc3_alloc_skb(unsigned long length,
129 unsigned int gfp_mask)
133 skb = alloc_skb(length + IOC3_CACHELINE - 1, gfp_mask);
135 int offset = aligned_rx_skb_addr((unsigned long) skb->data);
137 skb_reserve(skb, offset);
143 static inline unsigned long ioc3_map(void *ptr, unsigned long vdev)
145 #ifdef CONFIG_SGI_IP27
146 vdev <<= 57; /* Shift to PCI64_ATTR_VIRTUAL */
148 return vdev | (0xaUL << PCI64_ATTR_TARG_SHFT) | PCI64_ATTR_PREF |
149 ((unsigned long)ptr & TO_PHYS_MASK);
151 return virt_to_bus(ptr);
155 /* BEWARE: The IOC3 documentation documents the size of rx buffers as
156 1644 while it's actually 1664. This one was nasty to track down ... */
158 #define RX_BUF_ALLOC_SIZE (1664 + RX_OFFSET + IOC3_CACHELINE)
160 /* DMA barrier to separate cached and uncached accesses. */
162 __asm__("sync" ::: "memory")
165 #define IOC3_SIZE 0x100000
168 * IOC3 is a big endian device
170 * Unorthodox but makes the users of these macros more readable - the pointer
171 * to the IOC3's memory mapped registers is expected as struct ioc3 * ioc3
172 * in the environment.
174 #define ioc3_r_mcr() be32_to_cpu(ioc3->mcr)
175 #define ioc3_w_mcr(v) do { ioc3->mcr = cpu_to_be32(v); } while (0)
176 #define ioc3_w_gpcr_s(v) do { ioc3->gpcr_s = cpu_to_be32(v); } while (0)
177 #define ioc3_r_emcr() be32_to_cpu(ioc3->emcr)
178 #define ioc3_w_emcr(v) do { ioc3->emcr = cpu_to_be32(v); } while (0)
179 #define ioc3_r_eisr() be32_to_cpu(ioc3->eisr)
180 #define ioc3_w_eisr(v) do { ioc3->eisr = cpu_to_be32(v); } while (0)
181 #define ioc3_r_eier() be32_to_cpu(ioc3->eier)
182 #define ioc3_w_eier(v) do { ioc3->eier = cpu_to_be32(v); } while (0)
183 #define ioc3_r_ercsr() be32_to_cpu(ioc3->ercsr)
184 #define ioc3_w_ercsr(v) do { ioc3->ercsr = cpu_to_be32(v); } while (0)
185 #define ioc3_r_erbr_h() be32_to_cpu(ioc3->erbr_h)
186 #define ioc3_w_erbr_h(v) do { ioc3->erbr_h = cpu_to_be32(v); } while (0)
187 #define ioc3_r_erbr_l() be32_to_cpu(ioc3->erbr_l)
188 #define ioc3_w_erbr_l(v) do { ioc3->erbr_l = cpu_to_be32(v); } while (0)
189 #define ioc3_r_erbar() be32_to_cpu(ioc3->erbar)
190 #define ioc3_w_erbar(v) do { ioc3->erbar = cpu_to_be32(v); } while (0)
191 #define ioc3_r_ercir() be32_to_cpu(ioc3->ercir)
192 #define ioc3_w_ercir(v) do { ioc3->ercir = cpu_to_be32(v); } while (0)
193 #define ioc3_r_erpir() be32_to_cpu(ioc3->erpir)
194 #define ioc3_w_erpir(v) do { ioc3->erpir = cpu_to_be32(v); } while (0)
195 #define ioc3_r_ertr() be32_to_cpu(ioc3->ertr)
196 #define ioc3_w_ertr(v) do { ioc3->ertr = cpu_to_be32(v); } while (0)
197 #define ioc3_r_etcsr() be32_to_cpu(ioc3->etcsr)
198 #define ioc3_w_etcsr(v) do { ioc3->etcsr = cpu_to_be32(v); } while (0)
199 #define ioc3_r_ersr() be32_to_cpu(ioc3->ersr)
200 #define ioc3_w_ersr(v) do { ioc3->ersr = cpu_to_be32(v); } while (0)
201 #define ioc3_r_etcdc() be32_to_cpu(ioc3->etcdc)
202 #define ioc3_w_etcdc(v) do { ioc3->etcdc = cpu_to_be32(v); } while (0)
203 #define ioc3_r_ebir() be32_to_cpu(ioc3->ebir)
204 #define ioc3_w_ebir(v) do { ioc3->ebir = cpu_to_be32(v); } while (0)
205 #define ioc3_r_etbr_h() be32_to_cpu(ioc3->etbr_h)
206 #define ioc3_w_etbr_h(v) do { ioc3->etbr_h = cpu_to_be32(v); } while (0)
207 #define ioc3_r_etbr_l() be32_to_cpu(ioc3->etbr_l)
208 #define ioc3_w_etbr_l(v) do { ioc3->etbr_l = cpu_to_be32(v); } while (0)
209 #define ioc3_r_etcir() be32_to_cpu(ioc3->etcir)
210 #define ioc3_w_etcir(v) do { ioc3->etcir = cpu_to_be32(v); } while (0)
211 #define ioc3_r_etpir() be32_to_cpu(ioc3->etpir)
212 #define ioc3_w_etpir(v) do { ioc3->etpir = cpu_to_be32(v); } while (0)
213 #define ioc3_r_emar_h() be32_to_cpu(ioc3->emar_h)
214 #define ioc3_w_emar_h(v) do { ioc3->emar_h = cpu_to_be32(v); } while (0)
215 #define ioc3_r_emar_l() be32_to_cpu(ioc3->emar_l)
216 #define ioc3_w_emar_l(v) do { ioc3->emar_l = cpu_to_be32(v); } while (0)
217 #define ioc3_r_ehar_h() be32_to_cpu(ioc3->ehar_h)
218 #define ioc3_w_ehar_h(v) do { ioc3->ehar_h = cpu_to_be32(v); } while (0)
219 #define ioc3_r_ehar_l() be32_to_cpu(ioc3->ehar_l)
220 #define ioc3_w_ehar_l(v) do { ioc3->ehar_l = cpu_to_be32(v); } while (0)
221 #define ioc3_r_micr() be32_to_cpu(ioc3->micr)
222 #define ioc3_w_micr(v) do { ioc3->micr = cpu_to_be32(v); } while (0)
223 #define ioc3_r_midr_r() be32_to_cpu(ioc3->midr_r)
224 #define ioc3_w_midr_r(v) do { ioc3->midr_r = cpu_to_be32(v); } while (0)
225 #define ioc3_r_midr_w() be32_to_cpu(ioc3->midr_w)
226 #define ioc3_w_midr_w(v) do { ioc3->midr_w = cpu_to_be32(v); } while (0)
228 static inline u32 mcr_pack(u32 pulse, u32 sample)
230 return (pulse << 10) | (sample << 2);
233 static int nic_wait(struct ioc3 *ioc3)
239 } while (!(mcr & 2));
244 static int nic_reset(struct ioc3 *ioc3)
248 ioc3_w_mcr(mcr_pack(500, 65));
249 presence = nic_wait(ioc3);
251 ioc3_w_mcr(mcr_pack(0, 500));
257 static inline int nic_read_bit(struct ioc3 *ioc3)
261 ioc3_w_mcr(mcr_pack(6, 13));
262 result = nic_wait(ioc3);
263 ioc3_w_mcr(mcr_pack(0, 100));
269 static inline void nic_write_bit(struct ioc3 *ioc3, int bit)
272 ioc3_w_mcr(mcr_pack(6, 110));
274 ioc3_w_mcr(mcr_pack(80, 30));
280 * Read a byte from an iButton device
282 static u32 nic_read_byte(struct ioc3 *ioc3)
287 for (i = 0; i < 8; i++)
288 result = (result >> 1) | (nic_read_bit(ioc3) << 7);
294 * Write a byte to an iButton device
296 static void nic_write_byte(struct ioc3 *ioc3, int byte)
300 for (i = 8; i; i--) {
304 nic_write_bit(ioc3, bit);
308 static u64 nic_find(struct ioc3 *ioc3, int *last)
310 int a, b, index, disc;
315 nic_write_byte(ioc3, 0xf0);
317 /* Algorithm from ``Book of iButton Standards''. */
318 for (index = 0, disc = 0; index < 64; index++) {
319 a = nic_read_bit(ioc3);
320 b = nic_read_bit(ioc3);
323 printk("NIC search failed (not fatal).\n");
329 if (index == *last) {
330 address |= 1UL << index;
331 } else if (index > *last) {
332 address &= ~(1UL << index);
334 } else if ((address & (1UL << index)) == 0)
336 nic_write_bit(ioc3, address & (1UL << index));
340 address |= 1UL << index;
342 address &= ~(1UL << index);
343 nic_write_bit(ioc3, a);
353 static int nic_init(struct ioc3 *ioc3)
355 const char *unknown = "unknown";
356 const char *type = unknown;
363 reg = nic_find(ioc3, &save);
365 switch (reg & 0xff) {
371 /* Let the caller try again. */
380 nic_write_byte(ioc3, 0x55);
381 for (i = 0; i < 8; i++)
382 nic_write_byte(ioc3, (reg >> (i << 3)) & 0xff);
384 reg >>= 8; /* Shift out type. */
385 for (i = 0; i < 6; i++) {
386 serial[i] = reg & 0xff;
393 printk("Found %s NIC", type);
394 if (type != unknown) {
395 printk (" registration number %02x:%02x:%02x:%02x:%02x:%02x,"
396 " CRC %02x", serial[0], serial[1], serial[2],
397 serial[3], serial[4], serial[5], crc);
405 * Read the NIC (Number-In-a-Can) device used to store the MAC address on
406 * SN0 / SN00 nodeboards and PCI cards.
408 static void ioc3_get_eaddr_nic(struct ioc3_private *ip)
410 struct ioc3 *ioc3 = ip->regs;
412 int tries = 2; /* There may be some problem with the battery? */
415 ioc3_w_gpcr_s(1 << 21);
424 printk("Failed to read MAC address\n");
429 nic_write_byte(ioc3, 0xf0);
430 nic_write_byte(ioc3, 0x00);
431 nic_write_byte(ioc3, 0x00);
433 for (i = 13; i >= 0; i--)
434 nic[i] = nic_read_byte(ioc3);
436 for (i = 2; i < 8; i++)
437 priv_netdev(ip)->dev_addr[i - 2] = nic[i];
441 * Ok, this is hosed by design. It's necessary to know what machine the
442 * NIC is in in order to know how to read the NIC address. We also have
443 * to know if it's a PCI card or a NIC in on the node board ...
445 static void ioc3_get_eaddr(struct ioc3_private *ip)
450 ioc3_get_eaddr_nic(ip);
452 printk("Ethernet address is ");
453 for (i = 0; i < 6; i++) {
454 printk("%02x", priv_netdev(ip)->dev_addr[i]);
461 static void __ioc3_set_mac_address(struct net_device *dev)
463 struct ioc3_private *ip = netdev_priv(dev);
464 struct ioc3 *ioc3 = ip->regs;
466 ioc3_w_emar_h((dev->dev_addr[5] << 8) | dev->dev_addr[4]);
467 ioc3_w_emar_l((dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) |
468 (dev->dev_addr[1] << 8) | dev->dev_addr[0]);
471 static int ioc3_set_mac_address(struct net_device *dev, void *addr)
473 struct ioc3_private *ip = netdev_priv(dev);
474 struct sockaddr *sa = addr;
476 memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
478 spin_lock_irq(&ip->ioc3_lock);
479 __ioc3_set_mac_address(dev);
480 spin_unlock_irq(&ip->ioc3_lock);
486 * Caller must hold the ioc3_lock ever for MII readers. This is also
487 * used to protect the transmitter side but it's low contention.
489 static int ioc3_mdio_read(struct net_device *dev, int phy, int reg)
491 struct ioc3_private *ip = netdev_priv(dev);
492 struct ioc3 *ioc3 = ip->regs;
494 while (ioc3_r_micr() & MICR_BUSY);
495 ioc3_w_micr((phy << MICR_PHYADDR_SHIFT) | reg | MICR_READTRIG);
496 while (ioc3_r_micr() & MICR_BUSY);
498 return ioc3_r_midr_r() & MIDR_DATA_MASK;
501 static void ioc3_mdio_write(struct net_device *dev, int phy, int reg, int data)
503 struct ioc3_private *ip = netdev_priv(dev);
504 struct ioc3 *ioc3 = ip->regs;
506 while (ioc3_r_micr() & MICR_BUSY);
508 ioc3_w_micr((phy << MICR_PHYADDR_SHIFT) | reg);
509 while (ioc3_r_micr() & MICR_BUSY);
512 static int ioc3_mii_init(struct ioc3_private *ip);
514 static struct net_device_stats *ioc3_get_stats(struct net_device *dev)
516 struct ioc3_private *ip = netdev_priv(dev);
517 struct ioc3 *ioc3 = ip->regs;
519 ip->stats.collisions += (ioc3_r_etcdc() & ETCDC_COLLCNT_MASK);
523 #ifdef CONFIG_SGI_IOC3_ETH_HW_RX_CSUM
525 static void ioc3_tcpudp_checksum(struct sk_buff *skb, uint32_t hwsum, int len)
527 struct ethhdr *eh = eth_hdr(skb);
528 uint32_t csum, ehsum;
535 * Did hardware handle the checksum at all? The cases we can handle
538 * - TCP and UDP checksums of IPv4 only.
539 * - IPv6 would be doable but we keep that for later ...
540 * - Only unfragmented packets. Did somebody already tell you
541 * fragmentation is evil?
542 * - don't care about packet size. Worst case when processing a
543 * malformed packet we'll try to access the packet at ip header +
544 * 64 bytes which is still inside the skb. Even in the unlikely
545 * case where the checksum is right the higher layers will still
546 * drop the packet as appropriate.
548 if (eh->h_proto != ntohs(ETH_P_IP))
551 ih = (struct iphdr *) ((char *)eh + ETH_HLEN);
552 if (ih->frag_off & htons(IP_MF | IP_OFFSET))
555 proto = ih->protocol;
556 if (proto != IPPROTO_TCP && proto != IPPROTO_UDP)
559 /* Same as tx - compute csum of pseudo header */
561 (ih->tot_len - (ih->ihl << 2)) +
562 htons((uint16_t)ih->protocol) +
563 (ih->saddr >> 16) + (ih->saddr & 0xffff) +
564 (ih->daddr >> 16) + (ih->daddr & 0xffff);
566 /* Sum up ethernet dest addr, src addr and protocol */
567 ew = (uint16_t *) eh;
568 ehsum = ew[0] + ew[1] + ew[2] + ew[3] + ew[4] + ew[5] + ew[6];
570 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
571 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
573 csum += 0xffff ^ ehsum;
575 /* In the next step we also subtract the 1's complement
576 checksum of the trailing ethernet CRC. */
577 cp = (char *)eh + len; /* points at trailing CRC */
579 csum += 0xffff ^ (uint16_t) ((cp[1] << 8) | cp[0]);
580 csum += 0xffff ^ (uint16_t) ((cp[3] << 8) | cp[2]);
582 csum += 0xffff ^ (uint16_t) ((cp[0] << 8) | cp[1]);
583 csum += 0xffff ^ (uint16_t) ((cp[2] << 8) | cp[3]);
586 csum = (csum & 0xffff) + (csum >> 16);
587 csum = (csum & 0xffff) + (csum >> 16);
590 skb->ip_summed = CHECKSUM_UNNECESSARY;
592 #endif /* CONFIG_SGI_IOC3_ETH_HW_RX_CSUM */
594 static inline void ioc3_rx(struct ioc3_private *ip)
596 struct sk_buff *skb, *new_skb;
597 struct ioc3 *ioc3 = ip->regs;
598 int rx_entry, n_entry, len;
599 struct ioc3_erxbuf *rxb;
603 rxr = (unsigned long *) ip->rxr; /* Ring base */
604 rx_entry = ip->rx_ci; /* RX consume index */
607 skb = ip->rx_skbs[rx_entry];
608 rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
609 w0 = be32_to_cpu(rxb->w0);
611 while (w0 & ERXBUF_V) {
612 err = be32_to_cpu(rxb->err); /* It's valid ... */
613 if (err & ERXBUF_GOODPKT) {
614 len = ((w0 >> ERXBUF_BYTECNT_SHIFT) & 0x7ff) - 4;
616 skb->protocol = eth_type_trans(skb, priv_netdev(ip));
618 new_skb = ioc3_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
620 /* Ouch, drop packet and just recycle packet
621 to keep the ring filled. */
622 ip->stats.rx_dropped++;
627 #ifdef CONFIG_SGI_IOC3_ETH_HW_RX_CSUM
628 ioc3_tcpudp_checksum(skb, w0 & ERXBUF_IPCKSUM_MASK,len);
633 ip->rx_skbs[rx_entry] = NULL; /* Poison */
635 /* Because we reserve afterwards. */
636 skb_put(new_skb, (1664 + RX_OFFSET));
637 rxb = (struct ioc3_erxbuf *) new_skb->data;
638 skb_reserve(new_skb, RX_OFFSET);
640 priv_netdev(ip)->last_rx = jiffies;
641 ip->stats.rx_packets++; /* Statistics */
642 ip->stats.rx_bytes += len;
644 /* The frame is invalid and the skb never
645 reached the network layer so we can just
648 ip->stats.rx_errors++;
650 if (err & ERXBUF_CRCERR) /* Statistics */
651 ip->stats.rx_crc_errors++;
652 if (err & ERXBUF_FRAMERR)
653 ip->stats.rx_frame_errors++;
655 ip->rx_skbs[n_entry] = new_skb;
656 rxr[n_entry] = cpu_to_be64(ioc3_map(rxb, 1));
657 rxb->w0 = 0; /* Clear valid flag */
658 n_entry = (n_entry + 1) & 511; /* Update erpir */
660 /* Now go on to the next ring entry. */
661 rx_entry = (rx_entry + 1) & 511;
662 skb = ip->rx_skbs[rx_entry];
663 rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
664 w0 = be32_to_cpu(rxb->w0);
666 ioc3_w_erpir((n_entry << 3) | ERPIR_ARM);
668 ip->rx_ci = rx_entry;
671 static inline void ioc3_tx(struct ioc3_private *ip)
673 unsigned long packets, bytes;
674 struct ioc3 *ioc3 = ip->regs;
675 int tx_entry, o_entry;
679 spin_lock(&ip->ioc3_lock);
680 etcir = ioc3_r_etcir();
682 tx_entry = (etcir >> 7) & 127;
687 while (o_entry != tx_entry) {
689 skb = ip->tx_skbs[o_entry];
691 dev_kfree_skb_irq(skb);
692 ip->tx_skbs[o_entry] = NULL;
694 o_entry = (o_entry + 1) & 127; /* Next */
696 etcir = ioc3_r_etcir(); /* More pkts sent? */
697 tx_entry = (etcir >> 7) & 127;
700 ip->stats.tx_packets += packets;
701 ip->stats.tx_bytes += bytes;
702 ip->txqlen -= packets;
704 if (ip->txqlen < 128)
705 netif_wake_queue(priv_netdev(ip));
708 spin_unlock(&ip->ioc3_lock);
712 * Deal with fatal IOC3 errors. This condition might be caused by a hard or
713 * software problems, so we should try to recover
714 * more gracefully if this ever happens. In theory we might be flooded
715 * with such error interrupts if something really goes wrong, so we might
716 * also consider to take the interface down.
718 static void ioc3_error(struct ioc3_private *ip, u32 eisr)
720 struct net_device *dev = priv_netdev(ip);
721 unsigned char *iface = dev->name;
723 spin_lock(&ip->ioc3_lock);
725 if (eisr & EISR_RXOFLO)
726 printk(KERN_ERR "%s: RX overflow.\n", iface);
727 if (eisr & EISR_RXBUFOFLO)
728 printk(KERN_ERR "%s: RX buffer overflow.\n", iface);
729 if (eisr & EISR_RXMEMERR)
730 printk(KERN_ERR "%s: RX PCI error.\n", iface);
731 if (eisr & EISR_RXPARERR)
732 printk(KERN_ERR "%s: RX SSRAM parity error.\n", iface);
733 if (eisr & EISR_TXBUFUFLO)
734 printk(KERN_ERR "%s: TX buffer underflow.\n", iface);
735 if (eisr & EISR_TXMEMERR)
736 printk(KERN_ERR "%s: TX PCI error.\n", iface);
742 netif_wake_queue(dev);
744 spin_unlock(&ip->ioc3_lock);
747 /* The interrupt handler does all of the Rx thread work and cleans up
748 after the Tx thread. */
749 static irqreturn_t ioc3_interrupt(int irq, void *_dev)
751 struct net_device *dev = (struct net_device *)_dev;
752 struct ioc3_private *ip = netdev_priv(dev);
753 struct ioc3 *ioc3 = ip->regs;
754 const u32 enabled = EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO |
755 EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO |
756 EISR_TXEXPLICIT | EISR_TXMEMERR;
759 eisr = ioc3_r_eisr() & enabled;
762 (void) ioc3_r_eisr(); /* Flush */
764 if (eisr & (EISR_RXOFLO | EISR_RXBUFOFLO | EISR_RXMEMERR |
765 EISR_RXPARERR | EISR_TXBUFUFLO | EISR_TXMEMERR))
766 ioc3_error(ip, eisr);
767 if (eisr & EISR_RXTIMERINT)
769 if (eisr & EISR_TXEXPLICIT)
775 static inline void ioc3_setup_duplex(struct ioc3_private *ip)
777 struct ioc3 *ioc3 = ip->regs;
779 if (ip->mii.full_duplex) {
780 ioc3_w_etcsr(ETCSR_FD);
781 ip->emcr |= EMCR_DUPLEX;
783 ioc3_w_etcsr(ETCSR_HD);
784 ip->emcr &= ~EMCR_DUPLEX;
786 ioc3_w_emcr(ip->emcr);
789 static void ioc3_timer(unsigned long data)
791 struct ioc3_private *ip = (struct ioc3_private *) data;
793 /* Print the link status if it has changed */
794 mii_check_media(&ip->mii, 1, 0);
795 ioc3_setup_duplex(ip);
797 ip->ioc3_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2s */
798 add_timer(&ip->ioc3_timer);
802 * Try to find a PHY. There is no apparent relation between the MII addresses
803 * in the SGI documentation and what we find in reality, so we simply probe
804 * for the PHY. It seems IOC3 PHYs usually live on address 31. One of my
805 * onboard IOC3s has the special oddity that probing doesn't seem to find it
806 * yet the interface seems to work fine, so if probing fails we for now will
807 * simply default to PHY 31 instead of bailing out.
809 static int ioc3_mii_init(struct ioc3_private *ip)
811 struct net_device *dev = priv_netdev(ip);
812 int i, found = 0, res = 0;
813 int ioc3_phy_workaround = 1;
816 for (i = 0; i < 32; i++) {
817 word = ioc3_mdio_read(dev, i, MII_PHYSID1);
819 if (word != 0xffff && word != 0x0000) {
821 break; /* Found a PHY */
826 if (ioc3_phy_workaround)
841 static void ioc3_mii_start(struct ioc3_private *ip)
843 ip->ioc3_timer.expires = jiffies + (12 * HZ)/10; /* 1.2 sec. */
844 ip->ioc3_timer.data = (unsigned long) ip;
845 ip->ioc3_timer.function = &ioc3_timer;
846 add_timer(&ip->ioc3_timer);
849 static inline void ioc3_clean_rx_ring(struct ioc3_private *ip)
854 for (i = ip->rx_ci; i & 15; i++) {
855 ip->rx_skbs[ip->rx_pi] = ip->rx_skbs[ip->rx_ci];
856 ip->rxr[ip->rx_pi++] = ip->rxr[ip->rx_ci++];
861 for (i = ip->rx_ci; i != ip->rx_pi; i = (i+1) & 511) {
862 struct ioc3_erxbuf *rxb;
863 skb = ip->rx_skbs[i];
864 rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
869 static inline void ioc3_clean_tx_ring(struct ioc3_private *ip)
874 for (i=0; i < 128; i++) {
875 skb = ip->tx_skbs[i];
877 ip->tx_skbs[i] = NULL;
878 dev_kfree_skb_any(skb);
886 static void ioc3_free_rings(struct ioc3_private *ip)
889 int rx_entry, n_entry;
892 ioc3_clean_tx_ring(ip);
893 free_pages((unsigned long)ip->txr, 2);
899 rx_entry = ip->rx_pi;
901 while (n_entry != rx_entry) {
902 skb = ip->rx_skbs[n_entry];
904 dev_kfree_skb_any(skb);
906 n_entry = (n_entry + 1) & 511;
908 free_page((unsigned long)ip->rxr);
913 static void ioc3_alloc_rings(struct net_device *dev)
915 struct ioc3_private *ip = netdev_priv(dev);
916 struct ioc3_erxbuf *rxb;
920 if (ip->rxr == NULL) {
921 /* Allocate and initialize rx ring. 4kb = 512 entries */
922 ip->rxr = (unsigned long *) get_zeroed_page(GFP_ATOMIC);
923 rxr = (unsigned long *) ip->rxr;
925 printk("ioc3_alloc_rings(): get_zeroed_page() failed!\n");
927 /* Now the rx buffers. The RX ring may be larger but
928 we only allocate 16 buffers for now. Need to tune
929 this for performance and memory later. */
930 for (i = 0; i < RX_BUFFS; i++) {
933 skb = ioc3_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
939 ip->rx_skbs[i] = skb;
941 /* Because we reserve afterwards. */
942 skb_put(skb, (1664 + RX_OFFSET));
943 rxb = (struct ioc3_erxbuf *) skb->data;
944 rxr[i] = cpu_to_be64(ioc3_map(rxb, 1));
945 skb_reserve(skb, RX_OFFSET);
948 ip->rx_pi = RX_BUFFS;
951 if (ip->txr == NULL) {
952 /* Allocate and initialize tx rings. 16kb = 128 bufs. */
953 ip->txr = (struct ioc3_etxd *)__get_free_pages(GFP_KERNEL, 2);
955 printk("ioc3_alloc_rings(): __get_free_pages() failed!\n");
961 static void ioc3_init_rings(struct net_device *dev)
963 struct ioc3_private *ip = netdev_priv(dev);
964 struct ioc3 *ioc3 = ip->regs;
968 ioc3_alloc_rings(dev);
970 ioc3_clean_rx_ring(ip);
971 ioc3_clean_tx_ring(ip);
973 /* Now the rx ring base, consume & produce registers. */
974 ring = ioc3_map(ip->rxr, 0);
975 ioc3_w_erbr_h(ring >> 32);
976 ioc3_w_erbr_l(ring & 0xffffffff);
977 ioc3_w_ercir(ip->rx_ci << 3);
978 ioc3_w_erpir((ip->rx_pi << 3) | ERPIR_ARM);
980 ring = ioc3_map(ip->txr, 0);
982 ip->txqlen = 0; /* nothing queued */
984 /* Now the tx ring base, consume & produce registers. */
985 ioc3_w_etbr_h(ring >> 32);
986 ioc3_w_etbr_l(ring & 0xffffffff);
987 ioc3_w_etpir(ip->tx_pi << 7);
988 ioc3_w_etcir(ip->tx_ci << 7);
989 (void) ioc3_r_etcir(); /* Flush */
992 static inline void ioc3_ssram_disc(struct ioc3_private *ip)
994 struct ioc3 *ioc3 = ip->regs;
995 volatile u32 *ssram0 = &ioc3->ssram[0x0000];
996 volatile u32 *ssram1 = &ioc3->ssram[0x4000];
997 unsigned int pattern = 0x5555;
999 /* Assume the larger size SSRAM and enable parity checking */
1000 ioc3_w_emcr(ioc3_r_emcr() | (EMCR_BUFSIZ | EMCR_RAMPAR));
1003 *ssram1 = ~pattern & IOC3_SSRAM_DM;
1005 if ((*ssram0 & IOC3_SSRAM_DM) != pattern ||
1006 (*ssram1 & IOC3_SSRAM_DM) != (~pattern & IOC3_SSRAM_DM)) {
1007 /* set ssram size to 64 KB */
1008 ip->emcr = EMCR_RAMPAR;
1009 ioc3_w_emcr(ioc3_r_emcr() & ~EMCR_BUFSIZ);
1011 ip->emcr = EMCR_BUFSIZ | EMCR_RAMPAR;
1014 static void ioc3_init(struct net_device *dev)
1016 struct ioc3_private *ip = netdev_priv(dev);
1017 struct ioc3 *ioc3 = ip->regs;
1019 del_timer_sync(&ip->ioc3_timer); /* Kill if running */
1021 ioc3_w_emcr(EMCR_RST); /* Reset */
1022 (void) ioc3_r_emcr(); /* Flush WB */
1023 udelay(4); /* Give it time ... */
1025 (void) ioc3_r_emcr();
1027 /* Misc registers */
1028 #ifdef CONFIG_SGI_IP27
1029 ioc3_w_erbar(PCI64_ATTR_BAR >> 32); /* Barrier on last store */
1031 ioc3_w_erbar(0); /* Let PCI API get it right */
1033 (void) ioc3_r_etcdc(); /* Clear on read */
1034 ioc3_w_ercsr(15); /* RX low watermark */
1035 ioc3_w_ertr(0); /* Interrupt immediately */
1036 __ioc3_set_mac_address(dev);
1037 ioc3_w_ehar_h(ip->ehar_h);
1038 ioc3_w_ehar_l(ip->ehar_l);
1039 ioc3_w_ersr(42); /* XXX should be random */
1041 ioc3_init_rings(dev);
1043 ip->emcr |= ((RX_OFFSET / 2) << EMCR_RXOFF_SHIFT) | EMCR_TXDMAEN |
1044 EMCR_TXEN | EMCR_RXDMAEN | EMCR_RXEN | EMCR_PADEN;
1045 ioc3_w_emcr(ip->emcr);
1046 ioc3_w_eier(EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO |
1047 EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO |
1048 EISR_TXEXPLICIT | EISR_TXMEMERR);
1049 (void) ioc3_r_eier();
1052 static inline void ioc3_stop(struct ioc3_private *ip)
1054 struct ioc3 *ioc3 = ip->regs;
1056 ioc3_w_emcr(0); /* Shutup */
1057 ioc3_w_eier(0); /* Disable interrupts */
1058 (void) ioc3_r_eier(); /* Flush */
1061 static int ioc3_open(struct net_device *dev)
1063 struct ioc3_private *ip = netdev_priv(dev);
1065 if (request_irq(dev->irq, ioc3_interrupt, IRQF_SHARED, ioc3_str, dev)) {
1066 printk(KERN_ERR "%s: Can't get irq %d\n", dev->name, dev->irq);
1076 netif_start_queue(dev);
1080 static int ioc3_close(struct net_device *dev)
1082 struct ioc3_private *ip = netdev_priv(dev);
1084 del_timer_sync(&ip->ioc3_timer);
1086 netif_stop_queue(dev);
1089 free_irq(dev->irq, dev);
1091 ioc3_free_rings(ip);
1096 * MENET cards have four IOC3 chips, which are attached to two sets of
1097 * PCI slot resources each: the primary connections are on slots
1098 * 0..3 and the secondaries are on 4..7
1100 * All four ethernets are brought out to connectors; six serial ports
1101 * (a pair from each of the first three IOC3s) are brought out to
1102 * MiniDINs; all other subdevices are left swinging in the wind, leave
1106 static int ioc3_adjacent_is_ioc3(struct pci_dev *pdev, int slot)
1108 struct pci_dev *dev = pci_get_slot(pdev->bus, PCI_DEVFN(slot, 0));
1112 if (dev->vendor == PCI_VENDOR_ID_SGI &&
1113 dev->device == PCI_DEVICE_ID_SGI_IOC3)
1121 static int ioc3_is_menet(struct pci_dev *pdev)
1123 return pdev->bus->parent == NULL &&
1124 ioc3_adjacent_is_ioc3(pdev, 0) &&
1125 ioc3_adjacent_is_ioc3(pdev, 1) &&
1126 ioc3_adjacent_is_ioc3(pdev, 2);
1129 #ifdef CONFIG_SERIAL_8250
1131 * Note about serial ports and consoles:
1132 * For console output, everyone uses the IOC3 UARTA (offset 0x178)
1133 * connected to the master node (look in ip27_setup_console() and
1134 * ip27prom_console_write()).
1136 * For serial (/dev/ttyS0 etc), we can not have hardcoded serial port
1137 * addresses on a partitioned machine. Since we currently use the ioc3
1138 * serial ports, we use dynamic serial port discovery that the serial.c
1139 * driver uses for pci/pnp ports (there is an entry for the SGI ioc3
1140 * boards in pci_boards[]). Unfortunately, UARTA's pio address is greater
1141 * than UARTB's, although UARTA on o200s has traditionally been known as
1142 * port 0. So, we just use one serial port from each ioc3 (since the
1143 * serial driver adds addresses to get to higher ports).
1145 * The first one to do a register_console becomes the preferred console
1146 * (if there is no kernel command line console= directive). /dev/console
1147 * (ie 5, 1) is then "aliased" into the device number returned by the
1148 * "device" routine referred to in this console structure
1149 * (ip27prom_console_dev).
1151 * Also look in ip27-pci.c:pci_fixup_ioc3() for some comments on working
1152 * around ioc3 oddities in this respect.
1154 * The IOC3 serials use a 22MHz clock rate with an additional divider by 3.
1157 static void __devinit ioc3_serial_probe(struct pci_dev *pdev, struct ioc3 *ioc3)
1159 struct uart_port port;
1162 * We need to recognice and treat the fourth MENET serial as it
1163 * does not have an SuperIO chip attached to it, therefore attempting
1164 * to access it will result in bus errors. We call something an
1165 * MENET if PCI slot 0, 1, 2 and 3 of a master PCI bus all have an IOC3
1166 * in it. This is paranoid but we want to avoid blowing up on a
1167 * showhorn PCI box that happens to have 4 IOC3 cards in it so it's
1168 * not paranoid enough ...
1170 if (ioc3_is_menet(pdev) && PCI_SLOT(pdev->devfn) == 3)
1174 * Register to interrupt zero because we share the interrupt with
1175 * the serial driver which we don't properly support yet.
1177 * Can't use UPF_IOREMAP as the whole of IOC3 resources have already
1180 memset(&port, 0, sizeof(port));
1182 port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
1183 port.iotype = UPIO_MEM;
1185 port.uartclk = 22000000 / 3;
1187 port.membase = (unsigned char *) &ioc3->sregs.uarta;
1188 serial8250_register_port(&port);
1190 port.membase = (unsigned char *) &ioc3->sregs.uartb;
1191 serial8250_register_port(&port);
1195 static int ioc3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1197 unsigned int sw_physid1, sw_physid2;
1198 struct net_device *dev = NULL;
1199 struct ioc3_private *ip;
1201 unsigned long ioc3_base, ioc3_size;
1202 u32 vendor, model, rev;
1203 int err, pci_using_dac;
1205 /* Configure DMA attributes. */
1206 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1209 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1211 printk(KERN_ERR "%s: Unable to obtain 64 bit DMA "
1212 "for consistent allocations\n", pci_name(pdev));
1216 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1218 printk(KERN_ERR "%s: No usable DMA configuration, "
1219 "aborting.\n", pci_name(pdev));
1225 if (pci_enable_device(pdev))
1228 dev = alloc_etherdev(sizeof(struct ioc3_private));
1235 dev->features |= NETIF_F_HIGHDMA;
1237 err = pci_request_regions(pdev, "ioc3");
1241 SET_MODULE_OWNER(dev);
1242 SET_NETDEV_DEV(dev, &pdev->dev);
1244 ip = netdev_priv(dev);
1246 dev->irq = pdev->irq;
1248 ioc3_base = pci_resource_start(pdev, 0);
1249 ioc3_size = pci_resource_len(pdev, 0);
1250 ioc3 = (struct ioc3 *) ioremap(ioc3_base, ioc3_size);
1252 printk(KERN_CRIT "ioc3eth(%s): ioremap failed, goodbye.\n",
1259 #ifdef CONFIG_SERIAL_8250
1260 ioc3_serial_probe(pdev, ioc3);
1263 spin_lock_init(&ip->ioc3_lock);
1264 init_timer(&ip->ioc3_timer);
1271 ip->mii.phy_id_mask = 0x1f;
1272 ip->mii.reg_num_mask = 0x1f;
1274 ip->mii.mdio_read = ioc3_mdio_read;
1275 ip->mii.mdio_write = ioc3_mdio_write;
1279 if (ip->mii.phy_id == -1) {
1280 printk(KERN_CRIT "ioc3-eth(%s): Didn't find a PHY, goodbye.\n",
1287 ioc3_ssram_disc(ip);
1290 /* The IOC3-specific entries in the device structure. */
1291 dev->open = ioc3_open;
1292 dev->hard_start_xmit = ioc3_start_xmit;
1293 dev->tx_timeout = ioc3_timeout;
1294 dev->watchdog_timeo = 5 * HZ;
1295 dev->stop = ioc3_close;
1296 dev->get_stats = ioc3_get_stats;
1297 dev->do_ioctl = ioc3_ioctl;
1298 dev->set_multicast_list = ioc3_set_multicast_list;
1299 dev->set_mac_address = ioc3_set_mac_address;
1300 dev->ethtool_ops = &ioc3_ethtool_ops;
1301 #ifdef CONFIG_SGI_IOC3_ETH_HW_TX_CSUM
1302 dev->features = NETIF_F_IP_CSUM;
1305 sw_physid1 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID1);
1306 sw_physid2 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID2);
1308 err = register_netdev(dev);
1312 mii_check_media(&ip->mii, 1, 1);
1313 ioc3_setup_duplex(ip);
1315 vendor = (sw_physid1 << 12) | (sw_physid2 >> 4);
1316 model = (sw_physid2 >> 4) & 0x3f;
1317 rev = sw_physid2 & 0xf;
1318 printk(KERN_INFO "%s: Using PHY %d, vendor 0x%x, model %d, "
1319 "rev %d.\n", dev->name, ip->mii.phy_id, vendor, model, rev);
1320 printk(KERN_INFO "%s: IOC3 SSRAM has %d kbyte.\n", dev->name,
1321 ip->emcr & EMCR_BUFSIZ ? 128 : 64);
1327 del_timer_sync(&ip->ioc3_timer);
1328 ioc3_free_rings(ip);
1330 pci_release_regions(pdev);
1335 * We should call pci_disable_device(pdev); here if the IOC3 wasn't
1336 * such a weird device ...
1342 static void __devexit ioc3_remove_one (struct pci_dev *pdev)
1344 struct net_device *dev = pci_get_drvdata(pdev);
1345 struct ioc3_private *ip = netdev_priv(dev);
1346 struct ioc3 *ioc3 = ip->regs;
1348 unregister_netdev(dev);
1349 del_timer_sync(&ip->ioc3_timer);
1352 pci_release_regions(pdev);
1355 * We should call pci_disable_device(pdev); here if the IOC3 wasn't
1356 * such a weird device ...
1360 static struct pci_device_id ioc3_pci_tbl[] = {
1361 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, PCI_ANY_ID, PCI_ANY_ID },
1364 MODULE_DEVICE_TABLE(pci, ioc3_pci_tbl);
1366 static struct pci_driver ioc3_driver = {
1368 .id_table = ioc3_pci_tbl,
1369 .probe = ioc3_probe,
1370 .remove = __devexit_p(ioc3_remove_one),
1373 static int __init ioc3_init_module(void)
1375 return pci_register_driver(&ioc3_driver);
1378 static void __exit ioc3_cleanup_module(void)
1380 pci_unregister_driver(&ioc3_driver);
1383 static int ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev)
1386 struct ioc3_private *ip = netdev_priv(dev);
1387 struct ioc3 *ioc3 = ip->regs;
1389 struct ioc3_etxd *desc;
1393 #ifdef CONFIG_SGI_IOC3_ETH_HW_TX_CSUM
1395 * IOC3 has a fairly simple minded checksumming hardware which simply
1396 * adds up the 1's complement checksum for the entire packet and
1397 * inserts it at an offset which can be specified in the descriptor
1398 * into the transmit packet. This means we have to compensate for the
1399 * MAC header which should not be summed and the TCP/UDP pseudo headers
1402 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1403 const struct iphdr *ih = ip_hdr(skb);
1404 const int proto = ntohs(ih->protocol);
1406 uint32_t csum, ehsum;
1409 /* The MAC header. skb->mac seem the logic approach
1410 to find the MAC header - except it's a NULL pointer ... */
1411 eh = (uint16_t *) skb->data;
1413 /* Sum up dest addr, src addr and protocol */
1414 ehsum = eh[0] + eh[1] + eh[2] + eh[3] + eh[4] + eh[5] + eh[6];
1416 /* Fold ehsum. can't use csum_fold which negates also ... */
1417 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
1418 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
1420 /* Skip IP header; it's sum is always zero and was
1421 already filled in by ip_output.c */
1422 csum = csum_tcpudp_nofold(ih->saddr, ih->daddr,
1423 ih->tot_len - (ih->ihl << 2),
1424 proto, 0xffff ^ ehsum);
1426 csum = (csum & 0xffff) + (csum >> 16); /* Fold again */
1427 csum = (csum & 0xffff) + (csum >> 16);
1429 csoff = ETH_HLEN + (ih->ihl << 2);
1430 if (proto == IPPROTO_UDP) {
1431 csoff += offsetof(struct udphdr, check);
1432 udp_hdr(skb)->check = csum;
1434 if (proto == IPPROTO_TCP) {
1435 csoff += offsetof(struct tcphdr, check);
1436 tcp_hdr(skb)->check = csum;
1439 w0 = ETXD_DOCHECKSUM | (csoff << ETXD_CHKOFF_SHIFT);
1441 #endif /* CONFIG_SGI_IOC3_ETH_HW_TX_CSUM */
1443 spin_lock_irq(&ip->ioc3_lock);
1445 data = (unsigned long) skb->data;
1448 produce = ip->tx_pi;
1449 desc = &ip->txr[produce];
1452 /* Short packet, let's copy it directly into the ring. */
1453 skb_copy_from_linear_data(skb, desc->data, skb->len);
1454 if (len < ETH_ZLEN) {
1455 /* Very short packet, pad with zeros at the end. */
1456 memset(desc->data + len, 0, ETH_ZLEN - len);
1459 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_D0V | w0);
1460 desc->bufcnt = cpu_to_be32(len);
1461 } else if ((data ^ (data + len - 1)) & 0x4000) {
1462 unsigned long b2 = (data | 0x3fffUL) + 1UL;
1463 unsigned long s1 = b2 - data;
1464 unsigned long s2 = data + len - b2;
1466 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE |
1467 ETXD_B1V | ETXD_B2V | w0);
1468 desc->bufcnt = cpu_to_be32((s1 << ETXD_B1CNT_SHIFT) |
1469 (s2 << ETXD_B2CNT_SHIFT));
1470 desc->p1 = cpu_to_be64(ioc3_map(skb->data, 1));
1471 desc->p2 = cpu_to_be64(ioc3_map((void *) b2, 1));
1473 /* Normal sized packet that doesn't cross a page boundary. */
1474 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_B1V | w0);
1475 desc->bufcnt = cpu_to_be32(len << ETXD_B1CNT_SHIFT);
1476 desc->p1 = cpu_to_be64(ioc3_map(skb->data, 1));
1481 dev->trans_start = jiffies;
1482 ip->tx_skbs[produce] = skb; /* Remember skb */
1483 produce = (produce + 1) & 127;
1484 ip->tx_pi = produce;
1485 ioc3_w_etpir(produce << 7); /* Fire ... */
1489 if (ip->txqlen >= 127)
1490 netif_stop_queue(dev);
1492 spin_unlock_irq(&ip->ioc3_lock);
1497 static void ioc3_timeout(struct net_device *dev)
1499 struct ioc3_private *ip = netdev_priv(dev);
1501 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
1503 spin_lock_irq(&ip->ioc3_lock);
1510 spin_unlock_irq(&ip->ioc3_lock);
1512 netif_wake_queue(dev);
1516 * Given a multicast ethernet address, this routine calculates the
1517 * address's bit index in the logical address filter mask
1520 static inline unsigned int ioc3_hash(const unsigned char *addr)
1522 unsigned int temp = 0;
1526 crc = ether_crc_le(ETH_ALEN, addr);
1528 crc &= 0x3f; /* bit reverse lowest 6 bits for hash index */
1529 for (bits = 6; --bits >= 0; ) {
1531 temp |= (crc & 0x1);
1538 static void ioc3_get_drvinfo (struct net_device *dev,
1539 struct ethtool_drvinfo *info)
1541 struct ioc3_private *ip = netdev_priv(dev);
1543 strcpy (info->driver, IOC3_NAME);
1544 strcpy (info->version, IOC3_VERSION);
1545 strcpy (info->bus_info, pci_name(ip->pdev));
1548 static int ioc3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1550 struct ioc3_private *ip = netdev_priv(dev);
1553 spin_lock_irq(&ip->ioc3_lock);
1554 rc = mii_ethtool_gset(&ip->mii, cmd);
1555 spin_unlock_irq(&ip->ioc3_lock);
1560 static int ioc3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1562 struct ioc3_private *ip = netdev_priv(dev);
1565 spin_lock_irq(&ip->ioc3_lock);
1566 rc = mii_ethtool_sset(&ip->mii, cmd);
1567 spin_unlock_irq(&ip->ioc3_lock);
1572 static int ioc3_nway_reset(struct net_device *dev)
1574 struct ioc3_private *ip = netdev_priv(dev);
1577 spin_lock_irq(&ip->ioc3_lock);
1578 rc = mii_nway_restart(&ip->mii);
1579 spin_unlock_irq(&ip->ioc3_lock);
1584 static u32 ioc3_get_link(struct net_device *dev)
1586 struct ioc3_private *ip = netdev_priv(dev);
1589 spin_lock_irq(&ip->ioc3_lock);
1590 rc = mii_link_ok(&ip->mii);
1591 spin_unlock_irq(&ip->ioc3_lock);
1596 static const struct ethtool_ops ioc3_ethtool_ops = {
1597 .get_drvinfo = ioc3_get_drvinfo,
1598 .get_settings = ioc3_get_settings,
1599 .set_settings = ioc3_set_settings,
1600 .nway_reset = ioc3_nway_reset,
1601 .get_link = ioc3_get_link,
1604 static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1606 struct ioc3_private *ip = netdev_priv(dev);
1609 spin_lock_irq(&ip->ioc3_lock);
1610 rc = generic_mii_ioctl(&ip->mii, if_mii(rq), cmd, NULL);
1611 spin_unlock_irq(&ip->ioc3_lock);
1616 static void ioc3_set_multicast_list(struct net_device *dev)
1618 struct dev_mc_list *dmi = dev->mc_list;
1619 struct ioc3_private *ip = netdev_priv(dev);
1620 struct ioc3 *ioc3 = ip->regs;
1624 netif_stop_queue(dev); /* Lock out others. */
1626 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1627 ip->emcr |= EMCR_PROMISC;
1628 ioc3_w_emcr(ip->emcr);
1629 (void) ioc3_r_emcr();
1631 ip->emcr &= ~EMCR_PROMISC;
1632 ioc3_w_emcr(ip->emcr); /* Clear promiscuous. */
1633 (void) ioc3_r_emcr();
1635 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
1636 /* Too many for hashing to make sense or we want all
1637 multicast packets anyway, so skip computing all the
1638 hashes and just accept all packets. */
1639 ip->ehar_h = 0xffffffff;
1640 ip->ehar_l = 0xffffffff;
1642 for (i = 0; i < dev->mc_count; i++) {
1643 char *addr = dmi->dmi_addr;
1649 ehar |= (1UL << ioc3_hash(addr));
1651 ip->ehar_h = ehar >> 32;
1652 ip->ehar_l = ehar & 0xffffffff;
1654 ioc3_w_ehar_h(ip->ehar_h);
1655 ioc3_w_ehar_l(ip->ehar_l);
1658 netif_wake_queue(dev); /* Let us get going again. */
1661 MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
1662 MODULE_DESCRIPTION("SGI IOC3 Ethernet driver");
1663 MODULE_LICENSE("GPL");
1665 module_init(ioc3_init_module);
1666 module_exit(ioc3_cleanup_module);