drivers/net/igb/igb_main.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/module.h>
  29 #include <linux/types.h>
  30 #include <linux/init.h>
  31 #include <linux/vmalloc.h>
  32 #include <linux/pagemap.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/ipv6.h>
  35 #include <net/checksum.h>
  36 #include <net/ip6_checksum.h>
  37 #include <linux/mii.h>
  38 #include <linux/ethtool.h>
  39 #include <linux/if_vlan.h>
  40 #include <linux/pci.h>
  41 #include <linux/pci-aspm.h>
  42 #include <linux/delay.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/if_ether.h>
  45 #include <linux/aer.h>
  46 #ifdef CONFIG_IGB_DCA
  47 #include <linux/dca.h>
  48 #endif
  49 #include "igb.h"
  50
  51 #define DRV_VERSION "1.2.45-k2"
  52 char igb_driver_name[] = "igb";
  53 char igb_driver_version[] = DRV_VERSION;
  54 static const char igb_driver_string[] =
  55                                 "Intel(R) Gigabit Ethernet Network Driver";
  56 static const char igb_copyright[] = "Copyright (c) 2008 Intel Corporation.";
  57
  58 static const struct e1000_info *igb_info_tbl[] = {
  59         [board_82575] = &e1000_82575_info,
  60 };
  61
  62 static struct pci_device_id igb_pci_tbl[] = {
  63         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
  64         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
  65         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
  66         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
  67         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
  68         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
  69         /* required last entry */
  70         {0, }
  71 };
  72
  73 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
  74
  75 void igb_reset(struct igb_adapter *);
  76 static int igb_setup_all_tx_resources(struct igb_adapter *);
  77 static int igb_setup_all_rx_resources(struct igb_adapter *);
  78 static void igb_free_all_tx_resources(struct igb_adapter *);
  79 static void igb_free_all_rx_resources(struct igb_adapter *);
  80 void igb_update_stats(struct igb_adapter *);
  81 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
  82 static void __devexit igb_remove(struct pci_dev *pdev);
  83 static int igb_sw_init(struct igb_adapter *);
  84 static int igb_open(struct net_device *);
  85 static int igb_close(struct net_device *);
  86 static void igb_configure_tx(struct igb_adapter *);
  87 static void igb_configure_rx(struct igb_adapter *);
  88 static void igb_setup_rctl(struct igb_adapter *);
  89 static void igb_clean_all_tx_rings(struct igb_adapter *);
  90 static void igb_clean_all_rx_rings(struct igb_adapter *);
  91 static void igb_clean_tx_ring(struct igb_ring *);
  92 static void igb_clean_rx_ring(struct igb_ring *);
  93 static void igb_set_multi(struct net_device *);
  94 static void igb_update_phy_info(unsigned long);
  95 static void igb_watchdog(unsigned long);
  96 static void igb_watchdog_task(struct work_struct *);
  97 static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
  98                                   struct igb_ring *);
  99 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
 100 static struct net_device_stats *igb_get_stats(struct net_device *);
 101 static int igb_change_mtu(struct net_device *, int);
 102 static int igb_set_mac(struct net_device *, void *);
 103 static irqreturn_t igb_intr(int irq, void *);
 104 static irqreturn_t igb_intr_msi(int irq, void *);
 105 static irqreturn_t igb_msix_other(int irq, void *);
 106 static irqreturn_t igb_msix_rx(int irq, void *);
 107 static irqreturn_t igb_msix_tx(int irq, void *);
 108 static int igb_clean_rx_ring_msix(struct napi_struct *, int);
 109 #ifdef CONFIG_IGB_DCA
 110 static void igb_update_rx_dca(struct igb_ring *);
 111 static void igb_update_tx_dca(struct igb_ring *);
 112 static void igb_setup_dca(struct igb_adapter *);
 113 #endif /* CONFIG_IGB_DCA */
 114 static bool igb_clean_tx_irq(struct igb_ring *);
 115 static int igb_poll(struct napi_struct *, int);
 116 static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
 117 static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
 118 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
 119 static void igb_tx_timeout(struct net_device *);
 120 static void igb_reset_task(struct work_struct *);
 121 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
 122 static void igb_vlan_rx_add_vid(struct net_device *, u16);
 123 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
 124 static void igb_restore_vlan(struct igb_adapter *);
 125
 126 static int igb_suspend(struct pci_dev *, pm_message_t);
 127 #ifdef CONFIG_PM
 128 static int igb_resume(struct pci_dev *);
 129 #endif
 130 static void igb_shutdown(struct pci_dev *);
 131 #ifdef CONFIG_IGB_DCA
 132 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
 133 static struct notifier_block dca_notifier = {
 134         .notifier_call  = igb_notify_dca,
 135         .next           = NULL,
 136         .priority       = 0
 137 };
 138 #endif
 139
 140 #ifdef CONFIG_NET_POLL_CONTROLLER
 141 /* for netdump / net console */
 142 static void igb_netpoll(struct net_device *);
 143 #endif
 144
 145 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
 146                      pci_channel_state_t);
 147 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
 148 static void igb_io_resume(struct pci_dev *);
 149
 150 static struct pci_error_handlers igb_err_handler = {
 151         .error_detected = igb_io_error_detected,
 152         .slot_reset = igb_io_slot_reset,
 153         .resume = igb_io_resume,
 154 };
 155
 156
 157 static struct pci_driver igb_driver = {
 158         .name     = igb_driver_name,
 159         .id_table = igb_pci_tbl,
 160         .probe    = igb_probe,
 161         .remove   = __devexit_p(igb_remove),
 162 #ifdef CONFIG_PM
 163         /* Power Managment Hooks */
 164         .suspend  = igb_suspend,
 165         .resume   = igb_resume,
 166 #endif
 167         .shutdown = igb_shutdown,
 168         .err_handler = &igb_err_handler
 169 };
 170
 171 static int global_quad_port_a; /* global quad port a indication */
 172
 173 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
 174 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
 175 MODULE_LICENSE("GPL");
 176 MODULE_VERSION(DRV_VERSION);
 177
 178 #ifdef DEBUG
 179 /**
 180  * igb_get_hw_dev_name - return device name string
 181  * used by hardware layer to print debugging information
 182  **/
 183 char *igb_get_hw_dev_name(struct e1000_hw *hw)
 184 {
 185         struct igb_adapter *adapter = hw->back;
 186         return adapter->netdev->name;
 187 }
 188 #endif
 189
 190 /**
 191  * igb_init_module - Driver Registration Routine
 192  *
 193  * igb_init_module is the first routine called when the driver is
 194  * loaded. All it does is register with the PCI subsystem.
 195  **/
 196 static int __init igb_init_module(void)
 197 {
 198         int ret;
 199         printk(KERN_INFO "%s - version %s\n",
 200                igb_driver_string, igb_driver_version);
 201
 202         printk(KERN_INFO "%s\n", igb_copyright);
 203
 204         global_quad_port_a = 0;
 205
 206 #ifdef CONFIG_IGB_DCA
 207         dca_register_notify(&dca_notifier);
 208 #endif
 209
 210         ret = pci_register_driver(&igb_driver);
 211         return ret;
 212 }
 213
 214 module_init(igb_init_module);
 215
 216 /**
 217  * igb_exit_module - Driver Exit Cleanup Routine
 218  *
 219  * igb_exit_module is called just before the driver is removed
 220  * from memory.
 221  **/
 222 static void __exit igb_exit_module(void)
 223 {
 224 #ifdef CONFIG_IGB_DCA
 225         dca_unregister_notify(&dca_notifier);
 226 #endif
 227         pci_unregister_driver(&igb_driver);
 228 }
 229
 230 module_exit(igb_exit_module);
 231
 232 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
 233 /**
 234  * igb_cache_ring_register - Descriptor ring to register mapping
 235  * @adapter: board private structure to initialize
 236  *
 237  * Once we know the feature-set enabled for the device, we'll cache
 238  * the register offset the descriptor ring is assigned to.
 239  **/
 240 static void igb_cache_ring_register(struct igb_adapter *adapter)
 241 {
 242         int i;
 243
 244         switch (adapter->hw.mac.type) {
 245         case e1000_82576:
 246                 /* The queues are allocated for virtualization such that VF 0
 247                  * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
 248                  * In order to avoid collision we start at the first free queue
 249                  * and continue consuming queues in the same sequence
 250                  */
 251                 for (i = 0; i < adapter->num_rx_queues; i++)
 252                         adapter->rx_ring[i].reg_idx = Q_IDX_82576(i);
 253                 for (i = 0; i < adapter->num_tx_queues; i++)
 254                         adapter->tx_ring[i].reg_idx = Q_IDX_82576(i);
 255                 break;
 256         case e1000_82575:
 257         default:
 258                 for (i = 0; i < adapter->num_rx_queues; i++)
 259                         adapter->rx_ring[i].reg_idx = i;
 260                 for (i = 0; i < adapter->num_tx_queues; i++)
 261                         adapter->tx_ring[i].reg_idx = i;
 262                 break;
 263         }
 264 }
 265
 266 /**
 267  * igb_alloc_queues - Allocate memory for all rings
 268  * @adapter: board private structure to initialize
 269  *
 270  * We allocate one ring per queue at run-time since we don't know the
 271  * number of queues at compile-time.
 272  **/
 273 static int igb_alloc_queues(struct igb_adapter *adapter)
 274 {
 275         int i;
 276
 277         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
 278                                    sizeof(struct igb_ring), GFP_KERNEL);
 279         if (!adapter->tx_ring)
 280                 return -ENOMEM;
 281
 282         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
 283                                    sizeof(struct igb_ring), GFP_KERNEL);
 284         if (!adapter->rx_ring) {
 285                 kfree(adapter->tx_ring);
 286                 return -ENOMEM;
 287         }
 288
 289         adapter->rx_ring->buddy = adapter->tx_ring;
 290
 291         for (i = 0; i < adapter->num_tx_queues; i++) {
 292                 struct igb_ring *ring = &(adapter->tx_ring[i]);
 293                 ring->count = adapter->tx_ring_count;
 294                 ring->adapter = adapter;
 295                 ring->queue_index = i;
 296         }
 297         for (i = 0; i < adapter->num_rx_queues; i++) {
 298                 struct igb_ring *ring = &(adapter->rx_ring[i]);
 299                 ring->count = adapter->rx_ring_count;
 300                 ring->adapter = adapter;
 301                 ring->queue_index = i;
 302                 ring->itr_register = E1000_ITR;
 303
 304                 /* set a default napi handler for each rx_ring */
 305                 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
 306         }
 307
 308         igb_cache_ring_register(adapter);
 309         return 0;
 310 }
 311
 312 static void igb_free_queues(struct igb_adapter *adapter)
 313 {
 314         int i;
 315
 316         for (i = 0; i < adapter->num_rx_queues; i++)
 317                 netif_napi_del(&adapter->rx_ring[i].napi);
 318
 319         kfree(adapter->tx_ring);
 320         kfree(adapter->rx_ring);
 321 }
 322
 323 #define IGB_N0_QUEUE -1
 324 static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
 325                               int tx_queue, int msix_vector)
 326 {
 327         u32 msixbm = 0;
 328         struct e1000_hw *hw = &adapter->hw;
 329         u32 ivar, index;
 330
 331         switch (hw->mac.type) {
 332         case e1000_82575:
 333                 /* The 82575 assigns vectors using a bitmask, which matches the
 334                    bitmask for the EICR/EIMS/EIMC registers.  To assign one
 335                    or more queues to a vector, we write the appropriate bits
 336                    into the MSIXBM register for that vector. */
 337                 if (rx_queue > IGB_N0_QUEUE) {
 338                         msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
 339                         adapter->rx_ring[rx_queue].eims_value = msixbm;
 340                 }
 341                 if (tx_queue > IGB_N0_QUEUE) {
 342                         msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
 343                         adapter->tx_ring[tx_queue].eims_value =
 344                                   E1000_EICR_TX_QUEUE0 << tx_queue;
 345                 }
 346                 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
 347                 break;
 348         case e1000_82576:
 349                 /* 82576 uses a table-based method for assigning vectors.
 350                    Each queue has a single entry in the table to which we write
 351                    a vector number along with a "valid" bit.  Sadly, the layout
 352                    of the table is somewhat counterintuitive. */
 353                 if (rx_queue > IGB_N0_QUEUE) {
 354                         index = (rx_queue >> 1);
 355                         ivar = array_rd32(E1000_IVAR0, index);
 356                         if (rx_queue & 0x1) {
 357                                 /* vector goes into third byte of register */
 358                                 ivar = ivar & 0xFF00FFFF;
 359                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
 360                         } else {
 361                                 /* vector goes into low byte of register */
 362                                 ivar = ivar & 0xFFFFFF00;
 363                                 ivar |= msix_vector | E1000_IVAR_VALID;
 364                         }
 365                         adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
 366                         array_wr32(E1000_IVAR0, index, ivar);
 367                 }
 368                 if (tx_queue > IGB_N0_QUEUE) {
 369                         index = (tx_queue >> 1);
 370                         ivar = array_rd32(E1000_IVAR0, index);
 371                         if (tx_queue & 0x1) {
 372                                 /* vector goes into high byte of register */
 373                                 ivar = ivar & 0x00FFFFFF;
 374                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
 375                         } else {
 376                                 /* vector goes into second byte of register */
 377                                 ivar = ivar & 0xFFFF00FF;
 378                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
 379                         }
 380                         adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
 381                         array_wr32(E1000_IVAR0, index, ivar);
 382                 }
 383                 break;
 384         default:
 385                 BUG();
 386                 break;
 387         }
 388 }
 389
 390 /**
 391  * igb_configure_msix - Configure MSI-X hardware
 392  *
 393  * igb_configure_msix sets up the hardware to properly
 394  * generate MSI-X interrupts.
 395  **/
 396 static void igb_configure_msix(struct igb_adapter *adapter)
 397 {
 398         u32 tmp;
 399         int i, vector = 0;
 400         struct e1000_hw *hw = &adapter->hw;
 401
 402         adapter->eims_enable_mask = 0;
 403         if (hw->mac.type == e1000_82576)
 404                 /* Turn on MSI-X capability first, or our settings
 405                  * won't stick.  And it will take days to debug. */
 406                 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
 407                                    E1000_GPIE_PBA | E1000_GPIE_EIAME |
 408                                    E1000_GPIE_NSICR);
 409
 410         for (i = 0; i < adapter->num_tx_queues; i++) {
 411                 struct igb_ring *tx_ring = &adapter->tx_ring[i];
 412                 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
 413                 adapter->eims_enable_mask |= tx_ring->eims_value;
 414                 if (tx_ring->itr_val)
 415                         writel(tx_ring->itr_val,
 416                                hw->hw_addr + tx_ring->itr_register);
 417                 else
 418                         writel(1, hw->hw_addr + tx_ring->itr_register);
 419         }
 420
 421         for (i = 0; i < adapter->num_rx_queues; i++) {
 422                 struct igb_ring *rx_ring = &adapter->rx_ring[i];
 423                 rx_ring->buddy = NULL;
 424                 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
 425                 adapter->eims_enable_mask |= rx_ring->eims_value;
 426                 if (rx_ring->itr_val)
 427                         writel(rx_ring->itr_val,
 428                                hw->hw_addr + rx_ring->itr_register);
 429                 else
 430                         writel(1, hw->hw_addr + rx_ring->itr_register);
 431         }
 432
 433
 434         /* set vector for other causes, i.e. link changes */
 435         switch (hw->mac.type) {
 436         case e1000_82575:
 437                 array_wr32(E1000_MSIXBM(0), vector++,
 438                                       E1000_EIMS_OTHER);
 439
 440                 tmp = rd32(E1000_CTRL_EXT);
 441                 /* enable MSI-X PBA support*/
 442                 tmp |= E1000_CTRL_EXT_PBA_CLR;
 443
 444                 /* Auto-Mask interrupts upon ICR read. */
 445                 tmp |= E1000_CTRL_EXT_EIAME;
 446                 tmp |= E1000_CTRL_EXT_IRCA;
 447
 448                 wr32(E1000_CTRL_EXT, tmp);
 449                 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
 450                 adapter->eims_other = E1000_EIMS_OTHER;
 451
 452                 break;
 453
 454         case e1000_82576:
 455                 tmp = (vector++ | E1000_IVAR_VALID) << 8;
 456                 wr32(E1000_IVAR_MISC, tmp);
 457
 458                 adapter->eims_enable_mask = (1 << (vector)) - 1;
 459                 adapter->eims_other = 1 << (vector - 1);
 460                 break;
 461         default:
 462                 /* do nothing, since nothing else supports MSI-X */
 463                 break;
 464         } /* switch (hw->mac.type) */
 465         wrfl();
 466 }
 467
 468 /**
 469  * igb_request_msix - Initialize MSI-X interrupts
 470  *
 471  * igb_request_msix allocates MSI-X vectors and requests interrupts from the
 472  * kernel.
 473  **/
 474 static int igb_request_msix(struct igb_adapter *adapter)
 475 {
 476         struct net_device *netdev = adapter->netdev;
 477         int i, err = 0, vector = 0;
 478
 479         vector = 0;
 480
 481         for (i = 0; i < adapter->num_tx_queues; i++) {
 482                 struct igb_ring *ring = &(adapter->tx_ring[i]);
 483                 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
 484                 err = request_irq(adapter->msix_entries[vector].vector,
 485                                   &igb_msix_tx, 0, ring->name,
 486                                   &(adapter->tx_ring[i]));
 487                 if (err)
 488                         goto out;
 489                 ring->itr_register = E1000_EITR(0) + (vector << 2);
 490                 ring->itr_val = 976; /* ~4000 ints/sec */
 491                 vector++;
 492         }
 493         for (i = 0; i < adapter->num_rx_queues; i++) {
 494                 struct igb_ring *ring = &(adapter->rx_ring[i]);
 495                 if (strlen(netdev->name) < (IFNAMSIZ - 5))
 496                         sprintf(ring->name, "%s-rx-%d", netdev->name, i);
 497                 else
 498                         memcpy(ring->name, netdev->name, IFNAMSIZ);
 499                 err = request_irq(adapter->msix_entries[vector].vector,
 500                                   &igb_msix_rx, 0, ring->name,
 501                                   &(adapter->rx_ring[i]));
 502                 if (err)
 503                         goto out;
 504                 ring->itr_register = E1000_EITR(0) + (vector << 2);
 505                 ring->itr_val = adapter->itr;
 506                 /* overwrite the poll routine for MSIX, we've already done
 507                  * netif_napi_add */
 508                 ring->napi.poll = &igb_clean_rx_ring_msix;
 509                 vector++;
 510         }
 511
 512         err = request_irq(adapter->msix_entries[vector].vector,
 513                           &igb_msix_other, 0, netdev->name, netdev);
 514         if (err)
 515                 goto out;
 516
 517         igb_configure_msix(adapter);
 518         return 0;
 519 out:
 520         return err;
 521 }
 522
 523 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
 524 {
 525         if (adapter->msix_entries) {
 526                 pci_disable_msix(adapter->pdev);
 527                 kfree(adapter->msix_entries);
 528                 adapter->msix_entries = NULL;
 529         } else if (adapter->flags & IGB_FLAG_HAS_MSI)
 530                 pci_disable_msi(adapter->pdev);
 531         return;
 532 }
 533
 534
 535 /**
 536  * igb_set_interrupt_capability - set MSI or MSI-X if supported
 537  *
 538  * Attempt to configure interrupts using the best available
 539  * capabilities of the hardware and kernel.
 540  **/
 541 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
 542 {
 543         int err;
 544         int numvecs, i;
 545
 546         numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
 547         adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
 548                                         GFP_KERNEL);
 549         if (!adapter->msix_entries)
 550                 goto msi_only;
 551
 552         for (i = 0; i < numvecs; i++)
 553                 adapter->msix_entries[i].entry = i;
 554
 555         err = pci_enable_msix(adapter->pdev,
 556                               adapter->msix_entries,
 557                               numvecs);
 558         if (err == 0)
 559                 goto out;
 560
 561         igb_reset_interrupt_capability(adapter);
 562
 563         /* If we can't do MSI-X, try MSI */
 564 msi_only:
 565         adapter->num_rx_queues = 1;
 566         adapter->num_tx_queues = 1;
 567         if (!pci_enable_msi(adapter->pdev))
 568                 adapter->flags |= IGB_FLAG_HAS_MSI;
 569 out:
 570         /* Notify the stack of the (possibly) reduced Tx Queue count. */
 571         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
 572         return;
 573 }
 574
 575 /**
 576  * igb_request_irq - initialize interrupts
 577  *
 578  * Attempts to configure interrupts using the best available
 579  * capabilities of the hardware and kernel.
 580  **/
 581 static int igb_request_irq(struct igb_adapter *adapter)
 582 {
 583         struct net_device *netdev = adapter->netdev;
 584         struct e1000_hw *hw = &adapter->hw;
 585         int err = 0;
 586
 587         if (adapter->msix_entries) {
 588                 err = igb_request_msix(adapter);
 589                 if (!err)
 590                         goto request_done;
 591                 /* fall back to MSI */
 592                 igb_reset_interrupt_capability(adapter);
 593                 if (!pci_enable_msi(adapter->pdev))
 594                         adapter->flags |= IGB_FLAG_HAS_MSI;
 595                 igb_free_all_tx_resources(adapter);
 596                 igb_free_all_rx_resources(adapter);
 597                 adapter->num_rx_queues = 1;
 598                 igb_alloc_queues(adapter);
 599         } else {
 600                 switch (hw->mac.type) {
 601                 case e1000_82575:
 602                         wr32(E1000_MSIXBM(0),
 603                              (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
 604                         break;
 605                 case e1000_82576:
 606                         wr32(E1000_IVAR0, E1000_IVAR_VALID);
 607                         break;
 608                 default:
 609                         break;
 610                 }
 611         }
 612
 613         if (adapter->flags & IGB_FLAG_HAS_MSI) {
 614                 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
 615                                   netdev->name, netdev);
 616                 if (!err)
 617                         goto request_done;
 618                 /* fall back to legacy interrupts */
 619                 igb_reset_interrupt_capability(adapter);
 620                 adapter->flags &= ~IGB_FLAG_HAS_MSI;
 621         }
 622
 623         err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
 624                           netdev->name, netdev);
 625
 626         if (err)
 627                 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
 628                         err);
 629
 630 request_done:
 631         return err;
 632 }
 633
 634 static void igb_free_irq(struct igb_adapter *adapter)
 635 {
 636         struct net_device *netdev = adapter->netdev;
 637
 638         if (adapter->msix_entries) {
 639                 int vector = 0, i;
 640
 641                 for (i = 0; i < adapter->num_tx_queues; i++)
 642                         free_irq(adapter->msix_entries[vector++].vector,
 643                                 &(adapter->tx_ring[i]));
 644                 for (i = 0; i < adapter->num_rx_queues; i++)
 645                         free_irq(adapter->msix_entries[vector++].vector,
 646                                 &(adapter->rx_ring[i]));
 647
 648                 free_irq(adapter->msix_entries[vector++].vector, netdev);
 649                 return;
 650         }
 651
 652         free_irq(adapter->pdev->irq, netdev);
 653 }
 654
 655 /**
 656  * igb_irq_disable - Mask off interrupt generation on the NIC
 657  * @adapter: board private structure
 658  **/
 659 static void igb_irq_disable(struct igb_adapter *adapter)
 660 {
 661         struct e1000_hw *hw = &adapter->hw;
 662
 663         if (adapter->msix_entries) {
 664                 wr32(E1000_EIAM, 0);
 665                 wr32(E1000_EIMC, ~0);
 666                 wr32(E1000_EIAC, 0);
 667         }
 668
 669         wr32(E1000_IAM, 0);
 670         wr32(E1000_IMC, ~0);
 671         wrfl();
 672         synchronize_irq(adapter->pdev->irq);
 673 }
 674
 675 /**
 676  * igb_irq_enable - Enable default interrupt generation settings
 677  * @adapter: board private structure
 678  **/
 679 static void igb_irq_enable(struct igb_adapter *adapter)
 680 {
 681         struct e1000_hw *hw = &adapter->hw;
 682
 683         if (adapter->msix_entries) {
 684                 wr32(E1000_EIAC, adapter->eims_enable_mask);
 685                 wr32(E1000_EIAM, adapter->eims_enable_mask);
 686                 wr32(E1000_EIMS, adapter->eims_enable_mask);
 687                 wr32(E1000_IMS, E1000_IMS_LSC);
 688         } else {
 689                 wr32(E1000_IMS, IMS_ENABLE_MASK);
 690                 wr32(E1000_IAM, IMS_ENABLE_MASK);
 691         }
 692 }
 693
 694 static void igb_update_mng_vlan(struct igb_adapter *adapter)
 695 {
 696         struct net_device *netdev = adapter->netdev;
 697         u16 vid = adapter->hw.mng_cookie.vlan_id;
 698         u16 old_vid = adapter->mng_vlan_id;
 699         if (adapter->vlgrp) {
 700                 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
 701                         if (adapter->hw.mng_cookie.status &
 702                                 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
 703                                 igb_vlan_rx_add_vid(netdev, vid);
 704                                 adapter->mng_vlan_id = vid;
 705                         } else
 706                                 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
 707
 708                         if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
 709                                         (vid != old_vid) &&
 710                             !vlan_group_get_device(adapter->vlgrp, old_vid))
 711                                 igb_vlan_rx_kill_vid(netdev, old_vid);
 712                 } else
 713                         adapter->mng_vlan_id = vid;
 714         }
 715 }
 716
 717 /**
 718  * igb_release_hw_control - release control of the h/w to f/w
 719  * @adapter: address of board private structure
 720  *
 721  * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
 722  * For ASF and Pass Through versions of f/w this means that the
 723  * driver is no longer loaded.
 724  *
 725  **/
 726 static void igb_release_hw_control(struct igb_adapter *adapter)
 727 {
 728         struct e1000_hw *hw = &adapter->hw;
 729         u32 ctrl_ext;
 730
 731         /* Let firmware take over control of h/w */
 732         ctrl_ext = rd32(E1000_CTRL_EXT);
 733         wr32(E1000_CTRL_EXT,
 734                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
 735 }
 736
 737
 738 /**
 739  * igb_get_hw_control - get control of the h/w from f/w
 740  * @adapter: address of board private structure
 741  *
 742  * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
 743  * For ASF and Pass Through versions of f/w this means that
 744  * the driver is loaded.
 745  *
 746  **/
 747 static void igb_get_hw_control(struct igb_adapter *adapter)
 748 {
 749         struct e1000_hw *hw = &adapter->hw;
 750         u32 ctrl_ext;
 751
 752         /* Let firmware know the driver has taken over */
 753         ctrl_ext = rd32(E1000_CTRL_EXT);
 754         wr32(E1000_CTRL_EXT,
 755                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
 756 }
 757
 758 /**
 759  * igb_configure - configure the hardware for RX and TX
 760  * @adapter: private board structure
 761  **/
 762 static void igb_configure(struct igb_adapter *adapter)
 763 {
 764         struct net_device *netdev = adapter->netdev;
 765         int i;
 766
 767         igb_get_hw_control(adapter);
 768         igb_set_multi(netdev);
 769
 770         igb_restore_vlan(adapter);
 771
 772         igb_configure_tx(adapter);
 773         igb_setup_rctl(adapter);
 774         igb_configure_rx(adapter);
 775
 776         igb_rx_fifo_flush_82575(&adapter->hw);
 777
 778         /* call IGB_DESC_UNUSED which always leaves
 779          * at least 1 descriptor unused to make sure
 780          * next_to_use != next_to_clean */
 781         for (i = 0; i < adapter->num_rx_queues; i++) {
 782                 struct igb_ring *ring = &adapter->rx_ring[i];
 783                 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
 784         }
 785
 786
 787         adapter->tx_queue_len = netdev->tx_queue_len;
 788 }
 789
 790
 791 /**
 792  * igb_up - Open the interface and prepare it to handle traffic
 793  * @adapter: board private structure
 794  **/
 795
 796 int igb_up(struct igb_adapter *adapter)
 797 {
 798         struct e1000_hw *hw = &adapter->hw;
 799         int i;
 800
 801         /* hardware has been reset, we need to reload some things */
 802         igb_configure(adapter);
 803
 804         clear_bit(__IGB_DOWN, &adapter->state);
 805
 806         for (i = 0; i < adapter->num_rx_queues; i++)
 807                 napi_enable(&adapter->rx_ring[i].napi);
 808         if (adapter->msix_entries)
 809                 igb_configure_msix(adapter);
 810
 811         /* Clear any pending interrupts. */
 812         rd32(E1000_ICR);
 813         igb_irq_enable(adapter);
 814
 815         /* Fire a link change interrupt to start the watchdog. */
 816         wr32(E1000_ICS, E1000_ICS_LSC);
 817         return 0;
 818 }
 819
 820 void igb_down(struct igb_adapter *adapter)
 821 {
 822         struct e1000_hw *hw = &adapter->hw;
 823         struct net_device *netdev = adapter->netdev;
 824         u32 tctl, rctl;
 825         int i;
 826
 827         /* signal that we're down so the interrupt handler does not
 828          * reschedule our watchdog timer */
 829         set_bit(__IGB_DOWN, &adapter->state);
 830
 831         /* disable receives in the hardware */
 832         rctl = rd32(E1000_RCTL);
 833         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
 834         /* flush and sleep below */
 835
 836         netif_tx_stop_all_queues(netdev);
 837
 838         /* disable transmits in the hardware */
 839         tctl = rd32(E1000_TCTL);
 840         tctl &= ~E1000_TCTL_EN;
 841         wr32(E1000_TCTL, tctl);
 842         /* flush both disables and wait for them to finish */
 843         wrfl();
 844         msleep(10);
 845
 846         for (i = 0; i < adapter->num_rx_queues; i++)
 847                 napi_disable(&adapter->rx_ring[i].napi);
 848
 849         igb_irq_disable(adapter);
 850
 851         del_timer_sync(&adapter->watchdog_timer);
 852         del_timer_sync(&adapter->phy_info_timer);
 853
 854         netdev->tx_queue_len = adapter->tx_queue_len;
 855         netif_carrier_off(netdev);
 856         adapter->link_speed = 0;
 857         adapter->link_duplex = 0;
 858
 859         if (!pci_channel_offline(adapter->pdev))
 860                 igb_reset(adapter);
 861         igb_clean_all_tx_rings(adapter);
 862         igb_clean_all_rx_rings(adapter);
 863 }
 864
 865 void igb_reinit_locked(struct igb_adapter *adapter)
 866 {
 867         WARN_ON(in_interrupt());
 868         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 869                 msleep(1);
 870         igb_down(adapter);
 871         igb_up(adapter);
 872         clear_bit(__IGB_RESETTING, &adapter->state);
 873 }
 874
 875 void igb_reset(struct igb_adapter *adapter)
 876 {
 877         struct e1000_hw *hw = &adapter->hw;
 878         struct e1000_mac_info *mac = &hw->mac;
 879         struct e1000_fc_info *fc = &hw->fc;
 880         u32 pba = 0, tx_space, min_tx_space, min_rx_space;
 881         u16 hwm;
 882
 883         /* Repartition Pba for greater than 9k mtu
 884          * To take effect CTRL.RST is required.
 885          */
 886         if (mac->type != e1000_82576) {
 887         pba = E1000_PBA_34K;
 888         }
 889         else {
 890                 pba = E1000_PBA_64K;
 891         }
 892
 893         if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
 894             (mac->type < e1000_82576)) {
 895                 /* adjust PBA for jumbo frames */
 896                 wr32(E1000_PBA, pba);
 897
 898                 /* To maintain wire speed transmits, the Tx FIFO should be
 899                  * large enough to accommodate two full transmit packets,
 900                  * rounded up to the next 1KB and expressed in KB.  Likewise,
 901                  * the Rx FIFO should be large enough to accommodate at least
 902                  * one full receive packet and is similarly rounded up and
 903                  * expressed in KB. */
 904                 pba = rd32(E1000_PBA);
 905                 /* upper 16 bits has Tx packet buffer allocation size in KB */
 906                 tx_space = pba >> 16;
 907                 /* lower 16 bits has Rx packet buffer allocation size in KB */
 908                 pba &= 0xffff;
 909                 /* the tx fifo also stores 16 bytes of information about the tx
 910                  * but don't include ethernet FCS because hardware appends it */
 911                 min_tx_space = (adapter->max_frame_size +
 912                                 sizeof(struct e1000_tx_desc) -
 913                                 ETH_FCS_LEN) * 2;
 914                 min_tx_space = ALIGN(min_tx_space, 1024);
 915                 min_tx_space >>= 10;
 916                 /* software strips receive CRC, so leave room for it */
 917                 min_rx_space = adapter->max_frame_size;
 918                 min_rx_space = ALIGN(min_rx_space, 1024);
 919                 min_rx_space >>= 10;
 920
 921                 /* If current Tx allocation is less than the min Tx FIFO size,
 922                  * and the min Tx FIFO size is less than the current Rx FIFO
 923                  * allocation, take space away from current Rx allocation */
 924                 if (tx_space < min_tx_space &&
 925                     ((min_tx_space - tx_space) < pba)) {
 926                         pba = pba - (min_tx_space - tx_space);
 927
 928                         /* if short on rx space, rx wins and must trump tx
 929                          * adjustment */
 930                         if (pba < min_rx_space)
 931                                 pba = min_rx_space;
 932                 }
 933                 wr32(E1000_PBA, pba);
 934         }
 935
 936         /* flow control settings */
 937         /* The high water mark must be low enough to fit one full frame
 938          * (or the size used for early receive) above it in the Rx FIFO.
 939          * Set it to the lower of:
 940          * - 90% of the Rx FIFO size, or
 941          * - the full Rx FIFO size minus one full frame */
 942         hwm = min(((pba << 10) * 9 / 10),
 943                         ((pba << 10) - 2 * adapter->max_frame_size));
 944
 945         if (mac->type < e1000_82576) {
 946                 fc->high_water = hwm & 0xFFF8;  /* 8-byte granularity */
 947                 fc->low_water = fc->high_water - 8;
 948         } else {
 949                 fc->high_water = hwm & 0xFFF0;  /* 16-byte granularity */
 950                 fc->low_water = fc->high_water - 16;
 951         }
 952         fc->pause_time = 0xFFFF;
 953         fc->send_xon = 1;
 954         fc->type = fc->original_type;
 955
 956         /* Allow time for pending master requests to run */
 957         adapter->hw.mac.ops.reset_hw(&adapter->hw);
 958         wr32(E1000_WUC, 0);
 959
 960         if (adapter->hw.mac.ops.init_hw(&adapter->hw))
 961                 dev_err(&adapter->pdev->dev, "Hardware Error\n");
 962
 963         igb_update_mng_vlan(adapter);
 964
 965         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
 966         wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
 967
 968         igb_reset_adaptive(&adapter->hw);
 969         igb_get_phy_info(&adapter->hw);
 970 }
 971
 972 /**
 973  * igb_is_need_ioport - determine if an adapter needs ioport resources or not
 974  * @pdev: PCI device information struct
 975  *
 976  * Returns true if an adapter needs ioport resources
 977  **/
 978 static int igb_is_need_ioport(struct pci_dev *pdev)
 979 {
 980         switch (pdev->device) {
 981         /* Currently there are no adapters that need ioport resources */
 982         default:
 983                 return false;
 984         }
 985 }
 986
 987 static const struct net_device_ops igb_netdev_ops = {
 988         .ndo_open               = igb_open,
 989         .ndo_stop               = igb_close,
 990         .ndo_start_xmit         = igb_xmit_frame_adv,
 991         .ndo_get_stats          = igb_get_stats,
 992         .ndo_set_multicast_list = igb_set_multi,
 993         .ndo_set_mac_address    = igb_set_mac,
 994         .ndo_change_mtu         = igb_change_mtu,
 995         .ndo_do_ioctl           = igb_ioctl,
 996         .ndo_tx_timeout         = igb_tx_timeout,
 997         .ndo_validate_addr      = eth_validate_addr,
 998         .ndo_vlan_rx_register   = igb_vlan_rx_register,
 999         .ndo_vlan_rx_add_vid    = igb_vlan_rx_add_vid,
1000         .ndo_vlan_rx_kill_vid   = igb_vlan_rx_kill_vid,
1001 #ifdef CONFIG_NET_POLL_CONTROLLER
1002         .ndo_poll_controller    = igb_netpoll,
1003 #endif
1004 };
1005
1006 /**
1007  * igb_probe - Device Initialization Routine
1008  * @pdev: PCI device information struct
1009  * @ent: entry in igb_pci_tbl
1010  *
1011  * Returns 0 on success, negative on failure
1012  *
1013  * igb_probe initializes an adapter identified by a pci_dev structure.
1014  * The OS initialization, configuring of the adapter private structure,
1015  * and a hardware reset occur.
1016  **/
1017 static int __devinit igb_probe(struct pci_dev *pdev,
1018                                const struct pci_device_id *ent)
1019 {
1020         struct net_device *netdev;
1021         struct igb_adapter *adapter;
1022         struct e1000_hw *hw;
1023         struct pci_dev *us_dev;
1024         const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1025         unsigned long mmio_start, mmio_len;
1026         int i, err, pci_using_dac, pos;
1027         u16 eeprom_data = 0, state = 0;
1028         u16 eeprom_apme_mask = IGB_EEPROM_APME;
1029         u32 part_num;
1030         int bars, need_ioport;
1031
1032         /* do not allocate ioport bars when not needed */
1033         need_ioport = igb_is_need_ioport(pdev);
1034         if (need_ioport) {
1035                 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
1036                 err = pci_enable_device(pdev);
1037         } else {
1038                 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1039                 err = pci_enable_device_mem(pdev);
1040         }
1041         if (err)
1042                 return err;
1043
1044         pci_using_dac = 0;
1045         err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1046         if (!err) {
1047                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1048                 if (!err)
1049                         pci_using_dac = 1;
1050         } else {
1051                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1052                 if (err) {
1053                         err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1054                         if (err) {
1055                                 dev_err(&pdev->dev, "No usable DMA "
1056                                         "configuration, aborting\n");
1057                                 goto err_dma;
1058                         }
1059                 }
1060         }
1061
1062         /* 82575 requires that the pci-e link partner disable the L0s state */
1063         switch (pdev->device) {
1064         case E1000_DEV_ID_82575EB_COPPER:
1065         case E1000_DEV_ID_82575EB_FIBER_SERDES:
1066         case E1000_DEV_ID_82575GB_QUAD_COPPER:
1067                 us_dev = pdev->bus->self;
1068                 pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP);
1069                 if (pos) {
1070                         pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1071                                              &state);
1072                         state &= ~PCIE_LINK_STATE_L0S;
1073                         pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1074                                               state);
1075                         dev_info(&pdev->dev,
1076                                  "Disabling ASPM L0s upstream switch port %s\n",
1077                                  pci_name(us_dev));
1078                 }
1079         default:
1080                 break;
1081         }
1082
1083         err = pci_request_selected_regions(pdev, bars, igb_driver_name);
1084         if (err)
1085                 goto err_pci_reg;
1086
1087         err = pci_enable_pcie_error_reporting(pdev);
1088         if (err) {
1089                 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1090                         "0x%x\n", err);
1091                 /* non-fatal, continue */
1092         }
1093
1094         pci_set_master(pdev);
1095         pci_save_state(pdev);
1096
1097         err = -ENOMEM;
1098         netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES);
1099         if (!netdev)
1100                 goto err_alloc_etherdev;
1101
1102         SET_NETDEV_DEV(netdev, &pdev->dev);
1103
1104         pci_set_drvdata(pdev, netdev);
1105         adapter = netdev_priv(netdev);
1106         adapter->netdev = netdev;
1107         adapter->pdev = pdev;
1108         hw = &adapter->hw;
1109         hw->back = adapter;
1110         adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1111         adapter->bars = bars;
1112         adapter->need_ioport = need_ioport;
1113
1114         mmio_start = pci_resource_start(pdev, 0);
1115         mmio_len = pci_resource_len(pdev, 0);
1116
1117         err = -EIO;
1118         adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1119         if (!adapter->hw.hw_addr)
1120                 goto err_ioremap;
1121
1122         netdev->netdev_ops = &igb_netdev_ops;
1123         igb_set_ethtool_ops(netdev);
1124         netdev->watchdog_timeo = 5 * HZ;
1125
1126         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1127
1128         netdev->mem_start = mmio_start;
1129         netdev->mem_end = mmio_start + mmio_len;
1130
1131         /* PCI config space info */
1132         hw->vendor_id = pdev->vendor;
1133         hw->device_id = pdev->device;
1134         hw->revision_id = pdev->revision;
1135         hw->subsystem_vendor_id = pdev->subsystem_vendor;
1136         hw->subsystem_device_id = pdev->subsystem_device;
1137
1138         /* setup the private structure */
1139         hw->back = adapter;
1140         /* Copy the default MAC, PHY and NVM function pointers */
1141         memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1142         memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1143         memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1144         /* Initialize skew-specific constants */
1145         err = ei->get_invariants(hw);
1146         if (err)
1147                 goto err_hw_init;
1148
1149         err = igb_sw_init(adapter);
1150         if (err)
1151                 goto err_sw_init;
1152
1153         igb_get_bus_info_pcie(hw);
1154
1155         /* set flags */
1156         switch (hw->mac.type) {
1157         case e1000_82575:
1158                 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1159                 break;
1160         case e1000_82576:
1161         default:
1162                 break;
1163         }
1164
1165         hw->phy.autoneg_wait_to_complete = false;
1166         hw->mac.adaptive_ifs = true;
1167
1168         /* Copper options */
1169         if (hw->phy.media_type == e1000_media_type_copper) {
1170                 hw->phy.mdix = AUTO_ALL_MODES;
1171                 hw->phy.disable_polarity_correction = false;
1172                 hw->phy.ms_type = e1000_ms_hw_default;
1173         }
1174
1175         if (igb_check_reset_block(hw))
1176                 dev_info(&pdev->dev,
1177                         "PHY reset is blocked due to SOL/IDER session.\n");
1178
1179         netdev->features = NETIF_F_SG |
1180                            NETIF_F_HW_CSUM |
1181                            NETIF_F_HW_VLAN_TX |
1182                            NETIF_F_HW_VLAN_RX |
1183                            NETIF_F_HW_VLAN_FILTER;
1184
1185         netdev->features |= NETIF_F_TSO;
1186         netdev->features |= NETIF_F_TSO6;
1187
1188 #ifdef CONFIG_IGB_LRO
1189         netdev->features |= NETIF_F_GRO;
1190 #endif
1191
1192         netdev->vlan_features |= NETIF_F_TSO;
1193         netdev->vlan_features |= NETIF_F_TSO6;
1194         netdev->vlan_features |= NETIF_F_HW_CSUM;
1195         netdev->vlan_features |= NETIF_F_SG;
1196
1197         if (pci_using_dac)
1198                 netdev->features |= NETIF_F_HIGHDMA;
1199
1200         adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1201
1202         /* before reading the NVM, reset the controller to put the device in a
1203          * known good starting state */
1204         hw->mac.ops.reset_hw(hw);
1205
1206         /* make sure the NVM is good */
1207         if (igb_validate_nvm_checksum(hw) < 0) {
1208                 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1209                 err = -EIO;
1210                 goto err_eeprom;
1211         }
1212
1213         /* copy the MAC address out of the NVM */
1214         if (hw->mac.ops.read_mac_addr(hw))
1215                 dev_err(&pdev->dev, "NVM Read Error\n");
1216
1217         memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1218         memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1219
1220         if (!is_valid_ether_addr(netdev->perm_addr)) {
1221                 dev_err(&pdev->dev, "Invalid MAC Address\n");
1222                 err = -EIO;
1223                 goto err_eeprom;
1224         }
1225
1226         init_timer(&adapter->watchdog_timer);
1227         adapter->watchdog_timer.function = &igb_watchdog;
1228         adapter->watchdog_timer.data = (unsigned long) adapter;
1229
1230         init_timer(&adapter->phy_info_timer);
1231         adapter->phy_info_timer.function = &igb_update_phy_info;
1232         adapter->phy_info_timer.data = (unsigned long) adapter;
1233
1234         INIT_WORK(&adapter->reset_task, igb_reset_task);
1235         INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1236
1237         /* Initialize link & ring properties that are user-changeable */
1238         adapter->tx_ring->count = 256;
1239         for (i = 0; i < adapter->num_tx_queues; i++)
1240                 adapter->tx_ring[i].count = adapter->tx_ring->count;
1241         adapter->rx_ring->count = 256;
1242         for (i = 0; i < adapter->num_rx_queues; i++)
1243                 adapter->rx_ring[i].count = adapter->rx_ring->count;
1244
1245         adapter->fc_autoneg = true;
1246         hw->mac.autoneg = true;
1247         hw->phy.autoneg_advertised = 0x2f;
1248
1249         hw->fc.original_type = e1000_fc_default;
1250         hw->fc.type = e1000_fc_default;
1251
1252         adapter->itr_setting = 3;
1253         adapter->itr = IGB_START_ITR;
1254
1255         igb_validate_mdi_setting(hw);
1256
1257         adapter->rx_csum = 1;
1258
1259         /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1260          * enable the ACPI Magic Packet filter
1261          */
1262
1263         if (hw->bus.func == 0 ||
1264             hw->device_id == E1000_DEV_ID_82575EB_COPPER)
1265                 hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL3_PORT_A, 1,
1266                                      &eeprom_data);
1267
1268         if (eeprom_data & eeprom_apme_mask)
1269                 adapter->eeprom_wol |= E1000_WUFC_MAG;
1270
1271         /* now that we have the eeprom settings, apply the special cases where
1272          * the eeprom may be wrong or the board simply won't support wake on
1273          * lan on a particular port */
1274         switch (pdev->device) {
1275         case E1000_DEV_ID_82575GB_QUAD_COPPER:
1276                 adapter->eeprom_wol = 0;
1277                 break;
1278         case E1000_DEV_ID_82575EB_FIBER_SERDES:
1279         case E1000_DEV_ID_82576_FIBER:
1280         case E1000_DEV_ID_82576_SERDES:
1281                 /* Wake events only supported on port A for dual fiber
1282                  * regardless of eeprom setting */
1283                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1284                         adapter->eeprom_wol = 0;
1285                 break;
1286         }
1287
1288         /* initialize the wol settings based on the eeprom settings */
1289         adapter->wol = adapter->eeprom_wol;
1290         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1291
1292         /* reset the hardware with the new settings */
1293         igb_reset(adapter);
1294
1295         /* let the f/w know that the h/w is now under the control of the
1296          * driver. */
1297         igb_get_hw_control(adapter);
1298
1299         /* tell the stack to leave us alone until igb_open() is called */
1300         netif_carrier_off(netdev);
1301         netif_tx_stop_all_queues(netdev);
1302
1303         strcpy(netdev->name, "eth%d");
1304         err = register_netdev(netdev);
1305         if (err)
1306                 goto err_register;
1307
1308 #ifdef CONFIG_IGB_DCA
1309         if (dca_add_requester(&pdev->dev) == 0) {
1310                 adapter->flags |= IGB_FLAG_DCA_ENABLED;
1311                 dev_info(&pdev->dev, "DCA enabled\n");
1312                 /* Always use CB2 mode, difference is masked
1313                  * in the CB driver. */
1314                 wr32(E1000_DCA_CTRL, 2);
1315                 igb_setup_dca(adapter);
1316         }
1317 #endif
1318
1319         dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1320         /* print bus type/speed/width info */
1321         dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
1322                  netdev->name,
1323                  ((hw->bus.speed == e1000_bus_speed_2500)
1324                   ? "2.5Gb/s" : "unknown"),
1325                  ((hw->bus.width == e1000_bus_width_pcie_x4)
1326                   ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1327                   ? "Width x1" : "unknown"),
1328                  netdev->dev_addr);
1329
1330         igb_read_part_num(hw, &part_num);
1331         dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1332                 (part_num >> 8), (part_num & 0xff));
1333
1334         dev_info(&pdev->dev,
1335                 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1336                 adapter->msix_entries ? "MSI-X" :
1337                 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
1338                 adapter->num_rx_queues, adapter->num_tx_queues);
1339
1340         return 0;
1341
1342 err_register:
1343         igb_release_hw_control(adapter);
1344 err_eeprom:
1345         if (!igb_check_reset_block(hw))
1346                 igb_reset_phy(hw);
1347
1348         if (hw->flash_address)
1349                 iounmap(hw->flash_address);
1350
1351         igb_remove_device(hw);
1352         igb_free_queues(adapter);
1353 err_sw_init:
1354 err_hw_init:
1355         iounmap(hw->hw_addr);
1356 err_ioremap:
1357         free_netdev(netdev);
1358 err_alloc_etherdev:
1359         pci_release_selected_regions(pdev, bars);
1360 err_pci_reg:
1361 err_dma:
1362         pci_disable_device(pdev);
1363         return err;
1364 }
1365
1366 /**
1367  * igb_remove - Device Removal Routine
1368  * @pdev: PCI device information struct
1369  *
1370  * igb_remove is called by the PCI subsystem to alert the driver
1371  * that it should release a PCI device.  The could be caused by a
1372  * Hot-Plug event, or because the driver is going to be removed from
1373  * memory.
1374  **/
1375 static void __devexit igb_remove(struct pci_dev *pdev)
1376 {
1377         struct net_device *netdev = pci_get_drvdata(pdev);
1378         struct igb_adapter *adapter = netdev_priv(netdev);
1379 #ifdef CONFIG_IGB_DCA
1380         struct e1000_hw *hw = &adapter->hw;
1381 #endif
1382         int err;
1383
1384         /* flush_scheduled work may reschedule our watchdog task, so
1385          * explicitly disable watchdog tasks from being rescheduled  */
1386         set_bit(__IGB_DOWN, &adapter->state);
1387         del_timer_sync(&adapter->watchdog_timer);
1388         del_timer_sync(&adapter->phy_info_timer);
1389
1390         flush_scheduled_work();
1391
1392 #ifdef CONFIG_IGB_DCA
1393         if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
1394                 dev_info(&pdev->dev, "DCA disabled\n");
1395                 dca_remove_requester(&pdev->dev);
1396                 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
1397                 wr32(E1000_DCA_CTRL, 1);
1398         }
1399 #endif
1400
1401         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
1402          * would have already happened in close and is redundant. */
1403         igb_release_hw_control(adapter);
1404
1405         unregister_netdev(netdev);
1406
1407         if (!igb_check_reset_block(&adapter->hw))
1408                 igb_reset_phy(&adapter->hw);
1409
1410         igb_remove_device(&adapter->hw);
1411         igb_reset_interrupt_capability(adapter);
1412
1413         igb_free_queues(adapter);
1414
1415         iounmap(adapter->hw.hw_addr);
1416         if (adapter->hw.flash_address)
1417                 iounmap(adapter->hw.flash_address);
1418         pci_release_selected_regions(pdev, adapter->bars);
1419
1420         free_netdev(netdev);
1421
1422         err = pci_disable_pcie_error_reporting(pdev);
1423         if (err)
1424                 dev_err(&pdev->dev,
1425                         "pci_disable_pcie_error_reporting failed 0x%x\n", err);
1426
1427         pci_disable_device(pdev);
1428 }
1429
1430 /**
1431  * igb_sw_init - Initialize general software structures (struct igb_adapter)
1432  * @adapter: board private structure to initialize
1433  *
1434  * igb_sw_init initializes the Adapter private data structure.
1435  * Fields are initialized based on PCI device information and
1436  * OS network device settings (MTU size).
1437  **/
1438 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1439 {
1440         struct e1000_hw *hw = &adapter->hw;
1441         struct net_device *netdev = adapter->netdev;
1442         struct pci_dev *pdev = adapter->pdev;
1443
1444         pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1445
1446         adapter->tx_ring_count = IGB_DEFAULT_TXD;
1447         adapter->rx_ring_count = IGB_DEFAULT_RXD;
1448         adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1449         adapter->rx_ps_hdr_size = 0; /* disable packet split */
1450         adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1451         adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1452
1453         /* Number of supported queues. */
1454         /* Having more queues than CPUs doesn't make sense. */
1455         adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
1456         adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
1457
1458         /* This call may decrease the number of queues depending on
1459          * interrupt mode. */
1460         igb_set_interrupt_capability(adapter);
1461
1462         if (igb_alloc_queues(adapter)) {
1463                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1464                 return -ENOMEM;
1465         }
1466
1467         /* Explicitly disable IRQ since the NIC can be in any state. */
1468         igb_irq_disable(adapter);
1469
1470         set_bit(__IGB_DOWN, &adapter->state);
1471         return 0;
1472 }
1473
1474 /**
1475  * igb_open - Called when a network interface is made active
1476  * @netdev: network interface device structure
1477  *
1478  * Returns 0 on success, negative value on failure
1479  *
1480  * The open entry point is called when a network interface is made
1481  * active by the system (IFF_UP).  At this point all resources needed
1482  * for transmit and receive operations are allocated, the interrupt
1483  * handler is registered with the OS, the watchdog timer is started,
1484  * and the stack is notified that the interface is ready.
1485  **/
1486 static int igb_open(struct net_device *netdev)
1487 {
1488         struct igb_adapter *adapter = netdev_priv(netdev);
1489         struct e1000_hw *hw = &adapter->hw;
1490         int err;
1491         int i;
1492
1493         /* disallow open during test */
1494         if (test_bit(__IGB_TESTING, &adapter->state))
1495                 return -EBUSY;
1496
1497         /* allocate transmit descriptors */
1498         err = igb_setup_all_tx_resources(adapter);
1499         if (err)
1500                 goto err_setup_tx;
1501
1502         /* allocate receive descriptors */
1503         err = igb_setup_all_rx_resources(adapter);
1504         if (err)
1505                 goto err_setup_rx;
1506
1507         /* e1000_power_up_phy(adapter); */
1508
1509         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1510         if ((adapter->hw.mng_cookie.status &
1511              E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1512                 igb_update_mng_vlan(adapter);
1513
1514         /* before we allocate an interrupt, we must be ready to handle it.
1515          * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1516          * as soon as we call pci_request_irq, so we have to setup our
1517          * clean_rx handler before we do so.  */
1518         igb_configure(adapter);
1519
1520         err = igb_request_irq(adapter);
1521         if (err)
1522                 goto err_req_irq;
1523
1524         /* From here on the code is the same as igb_up() */
1525         clear_bit(__IGB_DOWN, &adapter->state);
1526
1527         for (i = 0; i < adapter->num_rx_queues; i++)
1528                 napi_enable(&adapter->rx_ring[i].napi);
1529
1530         /* Clear any pending interrupts. */
1531         rd32(E1000_ICR);
1532
1533         igb_irq_enable(adapter);
1534
1535         netif_tx_start_all_queues(netdev);
1536
1537         /* Fire a link status change interrupt to start the watchdog. */
1538         wr32(E1000_ICS, E1000_ICS_LSC);
1539
1540         return 0;
1541
1542 err_req_irq:
1543         igb_release_hw_control(adapter);
1544         /* e1000_power_down_phy(adapter); */
1545         igb_free_all_rx_resources(adapter);
1546 err_setup_rx:
1547         igb_free_all_tx_resources(adapter);
1548 err_setup_tx:
1549         igb_reset(adapter);
1550
1551         return err;
1552 }
1553
1554 /**
1555  * igb_close - Disables a network interface
1556  * @netdev: network interface device structure
1557  *
1558  * Returns 0, this is not allowed to fail
1559  *
1560  * The close entry point is called when an interface is de-activated
1561  * by the OS.  The hardware is still under the driver's control, but
1562  * needs to be disabled.  A global MAC reset is issued to stop the
1563  * hardware, and all transmit and receive resources are freed.
1564  **/
1565 static int igb_close(struct net_device *netdev)
1566 {
1567         struct igb_adapter *adapter = netdev_priv(netdev);
1568
1569         WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1570         igb_down(adapter);
1571
1572         igb_free_irq(adapter);
1573
1574         igb_free_all_tx_resources(adapter);
1575         igb_free_all_rx_resources(adapter);
1576
1577         /* kill manageability vlan ID if supported, but not if a vlan with
1578          * the same ID is registered on the host OS (let 8021q kill it) */
1579         if ((adapter->hw.mng_cookie.status &
1580                           E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1581              !(adapter->vlgrp &&
1582                vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1583                 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1584
1585         return 0;
1586 }
1587
1588 /**
1589  * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1590  * @adapter: board private structure
1591  * @tx_ring: tx descriptor ring (for a specific queue) to setup
1592  *
1593  * Return 0 on success, negative on failure
1594  **/
1595
1596 int igb_setup_tx_resources(struct igb_adapter *adapter,
1597                            struct igb_ring *tx_ring)
1598 {
1599         struct pci_dev *pdev = adapter->pdev;
1600         int size;
1601
1602         size = sizeof(struct igb_buffer) * tx_ring->count;
1603         tx_ring->buffer_info = vmalloc(size);
1604         if (!tx_ring->buffer_info)
1605                 goto err;
1606         memset(tx_ring->buffer_info, 0, size);
1607
1608         /* round up to nearest 4K */
1609         tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
1610         tx_ring->size = ALIGN(tx_ring->size, 4096);
1611
1612         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1613                                              &tx_ring->dma);
1614
1615         if (!tx_ring->desc)
1616                 goto err;
1617
1618         tx_ring->adapter = adapter;
1619         tx_ring->next_to_use = 0;
1620         tx_ring->next_to_clean = 0;
1621         return 0;
1622
1623 err:
1624         vfree(tx_ring->buffer_info);
1625         dev_err(&adapter->pdev->dev,
1626                 "Unable to allocate memory for the transmit descriptor ring\n");
1627         return -ENOMEM;
1628 }
1629
1630 /**
1631  * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1632  *                                (Descriptors) for all queues
1633  * @adapter: board private structure
1634  *
1635  * Return 0 on success, negative on failure
1636  **/
1637 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1638 {
1639         int i, err = 0;
1640         int r_idx;
1641
1642         for (i = 0; i < adapter->num_tx_queues; i++) {
1643                 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1644                 if (err) {
1645                         dev_err(&adapter->pdev->dev,
1646                                 "Allocation for Tx Queue %u failed\n", i);
1647                         for (i--; i >= 0; i--)
1648                                 igb_free_tx_resources(&adapter->tx_ring[i]);
1649                         break;
1650                 }
1651         }
1652
1653         for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1654                 r_idx = i % adapter->num_tx_queues;
1655                 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1656         }
1657         return err;
1658 }
1659
1660 /**
1661  * igb_configure_tx - Configure transmit Unit after Reset
1662  * @adapter: board private structure
1663  *
1664  * Configure the Tx unit of the MAC after a reset.
1665  **/
1666 static void igb_configure_tx(struct igb_adapter *adapter)
1667 {
1668         u64 tdba;
1669         struct e1000_hw *hw = &adapter->hw;
1670         u32 tctl;
1671         u32 txdctl, txctrl;
1672         int i, j;
1673
1674         for (i = 0; i < adapter->num_tx_queues; i++) {
1675                 struct igb_ring *ring = &(adapter->tx_ring[i]);
1676                 j = ring->reg_idx;
1677                 wr32(E1000_TDLEN(j),
1678                                 ring->count * sizeof(struct e1000_tx_desc));
1679                 tdba = ring->dma;
1680                 wr32(E1000_TDBAL(j),
1681                                 tdba & 0x00000000ffffffffULL);
1682                 wr32(E1000_TDBAH(j), tdba >> 32);
1683
1684                 ring->head = E1000_TDH(j);
1685                 ring->tail = E1000_TDT(j);
1686                 writel(0, hw->hw_addr + ring->tail);
1687                 writel(0, hw->hw_addr + ring->head);
1688                 txdctl = rd32(E1000_TXDCTL(j));
1689                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1690                 wr32(E1000_TXDCTL(j), txdctl);
1691
1692                 /* Turn off Relaxed Ordering on head write-backs.  The
1693                  * writebacks MUST be delivered in order or it will
1694                  * completely screw up our bookeeping.
1695                  */
1696                 txctrl = rd32(E1000_DCA_TXCTRL(j));
1697                 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1698                 wr32(E1000_DCA_TXCTRL(j), txctrl);
1699         }
1700
1701
1702
1703         /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1704
1705         /* Program the Transmit Control Register */
1706
1707         tctl = rd32(E1000_TCTL);
1708         tctl &= ~E1000_TCTL_CT;
1709         tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1710                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1711
1712         igb_config_collision_dist(hw);
1713
1714         /* Setup Transmit Descriptor Settings for eop descriptor */
1715         adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1716
1717         /* Enable transmits */
1718         tctl |= E1000_TCTL_EN;
1719
1720         wr32(E1000_TCTL, tctl);
1721 }
1722
1723 /**
1724  * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1725  * @adapter: board private structure
1726  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
1727  *
1728  * Returns 0 on success, negative on failure
1729  **/
1730
1731 int igb_setup_rx_resources(struct igb_adapter *adapter,
1732                            struct igb_ring *rx_ring)
1733 {
1734         struct pci_dev *pdev = adapter->pdev;
1735         int size, desc_len;
1736
1737         size = sizeof(struct igb_buffer) * rx_ring->count;
1738         rx_ring->buffer_info = vmalloc(size);
1739         if (!rx_ring->buffer_info)
1740                 goto err;
1741         memset(rx_ring->buffer_info, 0, size);
1742
1743         desc_len = sizeof(union e1000_adv_rx_desc);
1744
1745         /* Round up to nearest 4K */
1746         rx_ring->size = rx_ring->count * desc_len;
1747         rx_ring->size = ALIGN(rx_ring->size, 4096);
1748
1749         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1750                                              &rx_ring->dma);
1751
1752         if (!rx_ring->desc)
1753                 goto err;
1754
1755         rx_ring->next_to_clean = 0;
1756         rx_ring->next_to_use = 0;
1757
1758         rx_ring->adapter = adapter;
1759
1760         return 0;
1761
1762 err:
1763         vfree(rx_ring->buffer_info);
1764         dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1765                 "the receive descriptor ring\n");
1766         return -ENOMEM;
1767 }
1768
1769 /**
1770  * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1771  *                                (Descriptors) for all queues
1772  * @adapter: board private structure
1773  *
1774  * Return 0 on success, negative on failure
1775  **/
1776 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1777 {
1778         int i, err = 0;
1779
1780         for (i = 0; i < adapter->num_rx_queues; i++) {
1781                 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1782                 if (err) {
1783                         dev_err(&adapter->pdev->dev,
1784                                 "Allocation for Rx Queue %u failed\n", i);
1785                         for (i--; i >= 0; i--)
1786                                 igb_free_rx_resources(&adapter->rx_ring[i]);
1787                         break;
1788                 }
1789         }
1790
1791         return err;
1792 }
1793
1794 /**
1795  * igb_setup_rctl - configure the receive control registers
1796  * @adapter: Board private structure
1797  **/
1798 static void igb_setup_rctl(struct igb_adapter *adapter)
1799 {
1800         struct e1000_hw *hw = &adapter->hw;
1801         u32 rctl;
1802         u32 srrctl = 0;
1803         int i, j;
1804
1805         rctl = rd32(E1000_RCTL);
1806
1807         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1808         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1809
1810         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
1811                 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1812
1813         /*
1814          * enable stripping of CRC. It's unlikely this will break BMC
1815          * redirection as it did with e1000. Newer features require
1816          * that the HW strips the CRC.
1817         */
1818         rctl |= E1000_RCTL_SECRC;
1819
1820         /*
1821          * disable store bad packets and clear size bits.
1822          */
1823         rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
1824
1825         /* enable LPE when to prevent packets larger than max_frame_size */
1826                 rctl |= E1000_RCTL_LPE;
1827
1828         /* Setup buffer sizes */
1829         switch (adapter->rx_buffer_len) {
1830         case IGB_RXBUFFER_256:
1831                 rctl |= E1000_RCTL_SZ_256;
1832                 break;
1833         case IGB_RXBUFFER_512:
1834                 rctl |= E1000_RCTL_SZ_512;
1835                 break;
1836         default:
1837                 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
1838                          >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1839                 break;
1840         }
1841
1842         /* 82575 and greater support packet-split where the protocol
1843          * header is placed in skb->data and the packet data is
1844          * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1845          * In the case of a non-split, skb->data is linearly filled,
1846          * followed by the page buffers.  Therefore, skb->data is
1847          * sized to hold the largest protocol header.
1848          */
1849         /* allocations using alloc_page take too long for regular MTU
1850          * so only enable packet split for jumbo frames */
1851         if (adapter->netdev->mtu > ETH_DATA_LEN) {
1852                 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
1853                 srrctl |= adapter->rx_ps_hdr_size <<
1854                          E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
1855                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1856         } else {
1857                 adapter->rx_ps_hdr_size = 0;
1858                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1859         }
1860
1861         for (i = 0; i < adapter->num_rx_queues; i++) {
1862                 j = adapter->rx_ring[i].reg_idx;
1863                 wr32(E1000_SRRCTL(j), srrctl);
1864         }
1865
1866         wr32(E1000_RCTL, rctl);
1867 }
1868
1869 /**
1870  * igb_configure_rx - Configure receive Unit after Reset
1871  * @adapter: board private structure
1872  *
1873  * Configure the Rx unit of the MAC after a reset.
1874  **/
1875 static void igb_configure_rx(struct igb_adapter *adapter)
1876 {
1877         u64 rdba;
1878         struct e1000_hw *hw = &adapter->hw;
1879         u32 rctl, rxcsum;
1880         u32 rxdctl;
1881         int i, j;
1882
1883         /* disable receives while setting up the descriptors */
1884         rctl = rd32(E1000_RCTL);
1885         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1886         wrfl();
1887         mdelay(10);
1888
1889         if (adapter->itr_setting > 3)
1890                 wr32(E1000_ITR, adapter->itr);
1891
1892         /* Setup the HW Rx Head and Tail Descriptor Pointers and
1893          * the Base and Length of the Rx Descriptor Ring */
1894         for (i = 0; i < adapter->num_rx_queues; i++) {
1895                 struct igb_ring *ring = &(adapter->rx_ring[i]);
1896                 j = ring->reg_idx;
1897                 rdba = ring->dma;
1898                 wr32(E1000_RDBAL(j),
1899                                 rdba & 0x00000000ffffffffULL);
1900                 wr32(E1000_RDBAH(j), rdba >> 32);
1901                 wr32(E1000_RDLEN(j),
1902                                ring->count * sizeof(union e1000_adv_rx_desc));
1903
1904                 ring->head = E1000_RDH(j);
1905                 ring->tail = E1000_RDT(j);
1906                 writel(0, hw->hw_addr + ring->tail);
1907                 writel(0, hw->hw_addr + ring->head);
1908
1909                 rxdctl = rd32(E1000_RXDCTL(j));
1910                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1911                 rxdctl &= 0xFFF00000;
1912                 rxdctl |= IGB_RX_PTHRESH;
1913                 rxdctl |= IGB_RX_HTHRESH << 8;
1914                 rxdctl |= IGB_RX_WTHRESH << 16;
1915                 wr32(E1000_RXDCTL(j), rxdctl);
1916         }
1917
1918         if (adapter->num_rx_queues > 1) {
1919                 u32 random[10];
1920                 u32 mrqc;
1921                 u32 j, shift;
1922                 union e1000_reta {
1923                         u32 dword;
1924                         u8  bytes[4];
1925                 } reta;
1926
1927                 get_random_bytes(&random[0], 40);
1928
1929                 if (hw->mac.type >= e1000_82576)
1930                         shift = 0;
1931                 else
1932                         shift = 6;
1933                 for (j = 0; j < (32 * 4); j++) {
1934                         reta.bytes[j & 3] =
1935                                 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
1936                         if ((j & 3) == 3)
1937                                 writel(reta.dword,
1938                                        hw->hw_addr + E1000_RETA(0) + (j & ~3));
1939                 }
1940                 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1941
1942                 /* Fill out hash function seeds */
1943                 for (j = 0; j < 10; j++)
1944                         array_wr32(E1000_RSSRK(0), j, random[j]);
1945
1946                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1947                          E1000_MRQC_RSS_FIELD_IPV4_TCP);
1948                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1949                          E1000_MRQC_RSS_FIELD_IPV6_TCP);
1950                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1951                          E1000_MRQC_RSS_FIELD_IPV6_UDP);
1952                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1953                          E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1954
1955
1956                 wr32(E1000_MRQC, mrqc);
1957
1958                 /* Multiqueue and raw packet checksumming are mutually
1959                  * exclusive.  Note that this not the same as TCP/IP
1960                  * checksumming, which works fine. */
1961                 rxcsum = rd32(E1000_RXCSUM);
1962                 rxcsum |= E1000_RXCSUM_PCSD;
1963                 wr32(E1000_RXCSUM, rxcsum);
1964         } else {
1965                 /* Enable Receive Checksum Offload for TCP and UDP */
1966                 rxcsum = rd32(E1000_RXCSUM);
1967                 if (adapter->rx_csum) {
1968                         rxcsum |= E1000_RXCSUM_TUOFL;
1969
1970                         /* Enable IPv4 payload checksum for UDP fragments
1971                          * Must be used in conjunction with packet-split. */
1972                         if (adapter->rx_ps_hdr_size)
1973                                 rxcsum |= E1000_RXCSUM_IPPCSE;
1974                 } else {
1975                         rxcsum &= ~E1000_RXCSUM_TUOFL;
1976                         /* don't need to clear IPPCSE as it defaults to 0 */
1977                 }
1978                 wr32(E1000_RXCSUM, rxcsum);
1979         }
1980
1981         if (adapter->vlgrp)
1982                 wr32(E1000_RLPML,
1983                                 adapter->max_frame_size + VLAN_TAG_SIZE);
1984         else
1985                 wr32(E1000_RLPML, adapter->max_frame_size);
1986
1987         /* Enable Receives */
1988         wr32(E1000_RCTL, rctl);
1989 }
1990
1991 /**
1992  * igb_free_tx_resources - Free Tx Resources per Queue
1993  * @tx_ring: Tx descriptor ring for a specific queue
1994  *
1995  * Free all transmit software resources
1996  **/
1997 void igb_free_tx_resources(struct igb_ring *tx_ring)
1998 {
1999         struct pci_dev *pdev = tx_ring->adapter->pdev;
2000
2001         igb_clean_tx_ring(tx_ring);
2002
2003         vfree(tx_ring->buffer_info);
2004         tx_ring->buffer_info = NULL;
2005
2006         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2007
2008         tx_ring->desc = NULL;
2009 }
2010
2011 /**
2012  * igb_free_all_tx_resources - Free Tx Resources for All Queues
2013  * @adapter: board private structure
2014  *
2015  * Free all transmit software resources
2016  **/
2017 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2018 {
2019         int i;
2020
2021         for (i = 0; i < adapter->num_tx_queues; i++)
2022                 igb_free_tx_resources(&adapter->tx_ring[i]);
2023 }
2024
2025 static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2026                                            struct igb_buffer *buffer_info)
2027 {
2028         if (buffer_info->dma) {
2029                 pci_unmap_page(adapter->pdev,
2030                                 buffer_info->dma,
2031                                 buffer_info->length,
2032                                 PCI_DMA_TODEVICE);
2033                 buffer_info->dma = 0;
2034         }
2035         if (buffer_info->skb) {
2036                 dev_kfree_skb_any(buffer_info->skb);
2037                 buffer_info->skb = NULL;
2038         }
2039         buffer_info->time_stamp = 0;
2040         /* buffer_info must be completely set up in the transmit path */
2041 }
2042
2043 /**
2044  * igb_clean_tx_ring - Free Tx Buffers
2045  * @tx_ring: ring to be cleaned
2046  **/
2047 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
2048 {
2049         struct igb_adapter *adapter = tx_ring->adapter;
2050         struct igb_buffer *buffer_info;
2051         unsigned long size;
2052         unsigned int i;
2053
2054         if (!tx_ring->buffer_info)
2055                 return;
2056         /* Free all the Tx ring sk_buffs */
2057
2058         for (i = 0; i < tx_ring->count; i++) {
2059                 buffer_info = &tx_ring->buffer_info[i];
2060                 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2061         }
2062
2063         size = sizeof(struct igb_buffer) * tx_ring->count;
2064         memset(tx_ring->buffer_info, 0, size);
2065
2066         /* Zero out the descriptor ring */
2067
2068         memset(tx_ring->desc, 0, tx_ring->size);
2069
2070         tx_ring->next_to_use = 0;
2071         tx_ring->next_to_clean = 0;
2072
2073         writel(0, adapter->hw.hw_addr + tx_ring->head);
2074         writel(0, adapter->hw.hw_addr + tx_ring->tail);
2075 }
2076
2077 /**
2078  * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2079  * @adapter: board private structure
2080  **/
2081 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2082 {
2083         int i;
2084
2085         for (i = 0; i < adapter->num_tx_queues; i++)
2086                 igb_clean_tx_ring(&adapter->tx_ring[i]);
2087 }
2088
2089 /**
2090  * igb_free_rx_resources - Free Rx Resources
2091  * @rx_ring: ring to clean the resources from
2092  *
2093  * Free all receive software resources
2094  **/
2095 void igb_free_rx_resources(struct igb_ring *rx_ring)
2096 {
2097         struct pci_dev *pdev = rx_ring->adapter->pdev;
2098
2099         igb_clean_rx_ring(rx_ring);
2100
2101         vfree(rx_ring->buffer_info);
2102         rx_ring->buffer_info = NULL;
2103
2104         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2105
2106         rx_ring->desc = NULL;
2107 }
2108
2109 /**
2110  * igb_free_all_rx_resources - Free Rx Resources for All Queues
2111  * @adapter: board private structure
2112  *
2113  * Free all receive software resources
2114  **/
2115 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2116 {
2117         int i;
2118
2119         for (i = 0; i < adapter->num_rx_queues; i++)
2120                 igb_free_rx_resources(&adapter->rx_ring[i]);
2121 }
2122
2123 /**
2124  * igb_clean_rx_ring - Free Rx Buffers per Queue
2125  * @rx_ring: ring to free buffers from
2126  **/
2127 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
2128 {
2129         struct igb_adapter *adapter = rx_ring->adapter;
2130         struct igb_buffer *buffer_info;
2131         struct pci_dev *pdev = adapter->pdev;
2132         unsigned long size;
2133         unsigned int i;
2134
2135         if (!rx_ring->buffer_info)
2136                 return;
2137         /* Free all the Rx ring sk_buffs */
2138         for (i = 0; i < rx_ring->count; i++) {
2139                 buffer_info = &rx_ring->buffer_info[i];
2140                 if (buffer_info->dma) {
2141                         if (adapter->rx_ps_hdr_size)
2142                                 pci_unmap_single(pdev, buffer_info->dma,
2143                                                  adapter->rx_ps_hdr_size,
2144                                                  PCI_DMA_FROMDEVICE);
2145                         else
2146                                 pci_unmap_single(pdev, buffer_info->dma,
2147                                                  adapter->rx_buffer_len,
2148                                                  PCI_DMA_FROMDEVICE);
2149                         buffer_info->dma = 0;
2150                 }
2151
2152                 if (buffer_info->skb) {
2153                         dev_kfree_skb(buffer_info->skb);
2154                         buffer_info->skb = NULL;
2155                 }
2156                 if (buffer_info->page) {
2157                         if (buffer_info->page_dma)
2158                                 pci_unmap_page(pdev, buffer_info->page_dma,
2159                                                PAGE_SIZE / 2,
2160                                                PCI_DMA_FROMDEVICE);
2161                         put_page(buffer_info->page);
2162                         buffer_info->page = NULL;
2163                         buffer_info->page_dma = 0;
2164                         buffer_info->page_offset = 0;
2165                 }
2166         }
2167
2168         size = sizeof(struct igb_buffer) * rx_ring->count;
2169         memset(rx_ring->buffer_info, 0, size);
2170
2171         /* Zero out the descriptor ring */
2172         memset(rx_ring->desc, 0, rx_ring->size);
2173
2174         rx_ring->next_to_clean = 0;
2175         rx_ring->next_to_use = 0;
2176
2177         writel(0, adapter->hw.hw_addr + rx_ring->head);
2178         writel(0, adapter->hw.hw_addr + rx_ring->tail);
2179 }
2180
2181 /**
2182  * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2183  * @adapter: board private structure
2184  **/
2185 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2186 {
2187         int i;
2188
2189         for (i = 0; i < adapter->num_rx_queues; i++)
2190                 igb_clean_rx_ring(&adapter->rx_ring[i]);
2191 }
2192
2193 /**
2194  * igb_set_mac - Change the Ethernet Address of the NIC
2195  * @netdev: network interface device structure
2196  * @p: pointer to an address structure
2197  *
2198  * Returns 0 on success, negative on failure
2199  **/
2200 static int igb_set_mac(struct net_device *netdev, void *p)
2201 {
2202         struct igb_adapter *adapter = netdev_priv(netdev);
2203         struct sockaddr *addr = p;
2204
2205         if (!is_valid_ether_addr(addr->sa_data))
2206                 return -EADDRNOTAVAIL;
2207
2208         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2209         memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
2210
2211         adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2212
2213         return 0;
2214 }
2215
2216 /**
2217  * igb_set_multi - Multicast and Promiscuous mode set
2218  * @netdev: network interface device structure
2219  *
2220  * The set_multi entry point is called whenever the multicast address
2221  * list or the network interface flags are updated.  This routine is
2222  * responsible for configuring the hardware for proper multicast,
2223  * promiscuous mode, and all-multi behavior.
2224  **/
2225 static void igb_set_multi(struct net_device *netdev)
2226 {
2227         struct igb_adapter *adapter = netdev_priv(netdev);
2228         struct e1000_hw *hw = &adapter->hw;
2229         struct e1000_mac_info *mac = &hw->mac;
2230         struct dev_mc_list *mc_ptr;
2231         u8  *mta_list;
2232         u32 rctl;
2233         int i;
2234
2235         /* Check for Promiscuous and All Multicast modes */
2236
2237         rctl = rd32(E1000_RCTL);
2238
2239         if (netdev->flags & IFF_PROMISC) {
2240                 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2241                 rctl &= ~E1000_RCTL_VFE;
2242         } else {
2243                 if (netdev->flags & IFF_ALLMULTI) {
2244                         rctl |= E1000_RCTL_MPE;
2245                         rctl &= ~E1000_RCTL_UPE;
2246                 } else
2247                         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2248                 rctl |= E1000_RCTL_VFE;
2249         }
2250         wr32(E1000_RCTL, rctl);
2251
2252         if (!netdev->mc_count) {
2253                 /* nothing to program, so clear mc list */
2254                 igb_update_mc_addr_list_82575(hw, NULL, 0, 1,
2255                                           mac->rar_entry_count);
2256                 return;
2257         }
2258
2259         mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2260         if (!mta_list)
2261                 return;
2262
2263         /* The shared function expects a packed array of only addresses. */
2264         mc_ptr = netdev->mc_list;
2265
2266         for (i = 0; i < netdev->mc_count; i++) {
2267                 if (!mc_ptr)
2268                         break;
2269                 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2270                 mc_ptr = mc_ptr->next;
2271         }
2272         igb_update_mc_addr_list_82575(hw, mta_list, i, 1,
2273                                       mac->rar_entry_count);
2274         kfree(mta_list);
2275 }
2276
2277 /* Need to wait a few seconds after link up to get diagnostic information from
2278  * the phy */
2279 static void igb_update_phy_info(unsigned long data)
2280 {
2281         struct igb_adapter *adapter = (struct igb_adapter *) data;
2282         igb_get_phy_info(&adapter->hw);
2283 }
2284
2285 /**
2286  * igb_watchdog - Timer Call-back
2287  * @data: pointer to adapter cast into an unsigned long
2288  **/
2289 static void igb_watchdog(unsigned long data)
2290 {
2291         struct igb_adapter *adapter = (struct igb_adapter *)data;
2292         /* Do the rest outside of interrupt context */
2293         schedule_work(&adapter->watchdog_task);
2294 }
2295
2296 static void igb_watchdog_task(struct work_struct *work)
2297 {
2298         struct igb_adapter *adapter = container_of(work,
2299                                         struct igb_adapter, watchdog_task);
2300         struct e1000_hw *hw = &adapter->hw;
2301
2302         struct net_device *netdev = adapter->netdev;
2303         struct igb_ring *tx_ring = adapter->tx_ring;
2304         struct e1000_mac_info *mac = &adapter->hw.mac;
2305         u32 link;
2306         u32 eics = 0;
2307         s32 ret_val;
2308         int i;
2309
2310         if ((netif_carrier_ok(netdev)) &&
2311             (rd32(E1000_STATUS) & E1000_STATUS_LU))
2312                 goto link_up;
2313
2314         ret_val = hw->mac.ops.check_for_link(&adapter->hw);
2315         if ((ret_val == E1000_ERR_PHY) &&
2316             (hw->phy.type == e1000_phy_igp_3) &&
2317             (rd32(E1000_CTRL) &
2318              E1000_PHY_CTRL_GBE_DISABLE))
2319                 dev_info(&adapter->pdev->dev,
2320                          "Gigabit has been disabled, downgrading speed\n");
2321
2322         if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
2323             !(rd32(E1000_TXCW) & E1000_TXCW_ANE))
2324                 link = mac->serdes_has_link;
2325         else
2326                 link = rd32(E1000_STATUS) &
2327                                       E1000_STATUS_LU;
2328
2329         if (link) {
2330                 if (!netif_carrier_ok(netdev)) {
2331                         u32 ctrl;
2332                         hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2333                                                    &adapter->link_speed,
2334                                                    &adapter->link_duplex);
2335
2336                         ctrl = rd32(E1000_CTRL);
2337                         /* Links status message must follow this format */
2338                         printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
2339                                  "Flow Control: %s\n",
2340                                  netdev->name,
2341                                  adapter->link_speed,
2342                                  adapter->link_duplex == FULL_DUPLEX ?
2343                                  "Full Duplex" : "Half Duplex",
2344                                  ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2345                                  E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2346                                  E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2347                                  E1000_CTRL_TFCE) ? "TX" : "None")));
2348
2349                         /* tweak tx_queue_len according to speed/duplex and
2350                          * adjust the timeout factor */
2351                         netdev->tx_queue_len = adapter->tx_queue_len;
2352                         adapter->tx_timeout_factor = 1;
2353                         switch (adapter->link_speed) {
2354                         case SPEED_10:
2355                                 netdev->tx_queue_len = 10;
2356                                 adapter->tx_timeout_factor = 14;
2357                                 break;
2358                         case SPEED_100:
2359                                 netdev->tx_queue_len = 100;
2360                                 /* maybe add some timeout factor ? */
2361                                 break;
2362                         }
2363
2364                         netif_carrier_on(netdev);
2365                         netif_tx_wake_all_queues(netdev);
2366
2367                         if (!test_bit(__IGB_DOWN, &adapter->state))
2368                                 mod_timer(&adapter->phy_info_timer,
2369                                           round_jiffies(jiffies + 2 * HZ));
2370                 }
2371         } else {
2372                 if (netif_carrier_ok(netdev)) {
2373                         adapter->link_speed = 0;
2374                         adapter->link_duplex = 0;
2375                         /* Links status message must follow this format */
2376                         printk(KERN_INFO "igb: %s NIC Link is Down\n",
2377                                netdev->name);
2378                         netif_carrier_off(netdev);
2379                         netif_tx_stop_all_queues(netdev);
2380                         if (!test_bit(__IGB_DOWN, &adapter->state))
2381                                 mod_timer(&adapter->phy_info_timer,
2382                                           round_jiffies(jiffies + 2 * HZ));
2383                 }
2384         }
2385
2386 link_up:
2387         igb_update_stats(adapter);
2388
2389         mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2390         adapter->tpt_old = adapter->stats.tpt;
2391         mac->collision_delta = adapter->stats.colc - adapter->colc_old;
2392         adapter->colc_old = adapter->stats.colc;
2393
2394         adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2395         adapter->gorc_old = adapter->stats.gorc;
2396         adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2397         adapter->gotc_old = adapter->stats.gotc;
2398
2399         igb_update_adaptive(&adapter->hw);
2400
2401         if (!netif_carrier_ok(netdev)) {
2402                 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2403                         /* We've lost link, so the controller stops DMA,
2404                          * but we've got queued Tx work that's never going
2405                          * to get done, so reset controller to flush Tx.
2406                          * (Do the reset outside of interrupt context). */
2407                         adapter->tx_timeout_count++;
2408                         schedule_work(&adapter->reset_task);
2409                 }
2410         }
2411
2412         /* Cause software interrupt to ensure rx ring is cleaned */
2413         if (adapter->msix_entries) {
2414                 for (i = 0; i < adapter->num_rx_queues; i++)
2415                         eics |= adapter->rx_ring[i].eims_value;
2416                 wr32(E1000_EICS, eics);
2417         } else {
2418                 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2419         }
2420
2421         /* Force detection of hung controller every watchdog period */
2422         tx_ring->detect_tx_hung = true;
2423
2424         /* Reset the timer */
2425         if (!test_bit(__IGB_DOWN, &adapter->state))
2426                 mod_timer(&adapter->watchdog_timer,
2427                           round_jiffies(jiffies + 2 * HZ));
2428 }
2429
2430 enum latency_range {
2431         lowest_latency = 0,
2432         low_latency = 1,
2433         bulk_latency = 2,
2434         latency_invalid = 255
2435 };
2436
2437
2438 /**
2439  * igb_update_ring_itr - update the dynamic ITR value based on packet size
2440  *
2441  *      Stores a new ITR value based on strictly on packet size.  This
2442  *      algorithm is less sophisticated than that used in igb_update_itr,
2443  *      due to the difficulty of synchronizing statistics across multiple
2444  *      receive rings.  The divisors and thresholds used by this fuction
2445  *      were determined based on theoretical maximum wire speed and testing
2446  *      data, in order to minimize response time while increasing bulk
2447  *      throughput.
2448  *      This functionality is controlled by the InterruptThrottleRate module
2449  *      parameter (see igb_param.c)
2450  *      NOTE:  This function is called only when operating in a multiqueue
2451  *             receive environment.
2452  * @rx_ring: pointer to ring
2453  **/
2454 static void igb_update_ring_itr(struct igb_ring *rx_ring)
2455 {
2456         int new_val = rx_ring->itr_val;
2457         int avg_wire_size = 0;
2458         struct igb_adapter *adapter = rx_ring->adapter;
2459
2460         if (!rx_ring->total_packets)
2461                 goto clear_counts; /* no packets, so don't do anything */
2462
2463         /* For non-gigabit speeds, just fix the interrupt rate at 4000
2464          * ints/sec - ITR timer value of 120 ticks.
2465          */
2466         if (adapter->link_speed != SPEED_1000) {
2467                 new_val = 120;
2468                 goto set_itr_val;
2469         }
2470         avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
2471
2472         /* Add 24 bytes to size to account for CRC, preamble, and gap */
2473         avg_wire_size += 24;
2474
2475         /* Don't starve jumbo frames */
2476         avg_wire_size = min(avg_wire_size, 3000);
2477
2478         /* Give a little boost to mid-size frames */
2479         if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2480                 new_val = avg_wire_size / 3;
2481         else
2482                 new_val = avg_wire_size / 2;
2483
2484 set_itr_val:
2485         if (new_val != rx_ring->itr_val) {
2486                 rx_ring->itr_val = new_val;
2487                 rx_ring->set_itr = 1;
2488         }
2489 clear_counts:
2490         rx_ring->total_bytes = 0;
2491         rx_ring->total_packets = 0;
2492 }
2493
2494 /**
2495  * igb_update_itr - update the dynamic ITR value based on statistics
2496  *      Stores a new ITR value based on packets and byte
2497  *      counts during the last interrupt.  The advantage of per interrupt
2498  *      computation is faster updates and more accurate ITR for the current
2499  *      traffic pattern.  Constants in this function were computed
2500  *      based on theoretical maximum wire speed and thresholds were set based
2501  *      on testing data as well as attempting to minimize response time
2502  *      while increasing bulk throughput.
2503  *      this functionality is controlled by the InterruptThrottleRate module
2504  *      parameter (see igb_param.c)
2505  *      NOTE:  These calculations are only valid when operating in a single-
2506  *             queue environment.
2507  * @adapter: pointer to adapter
2508  * @itr_setting: current adapter->itr
2509  * @packets: the number of packets during this measurement interval
2510  * @bytes: the number of bytes during this measurement interval
2511  **/
2512 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2513                                    int packets, int bytes)
2514 {
2515         unsigned int retval = itr_setting;
2516
2517         if (packets == 0)
2518                 goto update_itr_done;
2519
2520         switch (itr_setting) {
2521         case lowest_latency:
2522                 /* handle TSO and jumbo frames */
2523                 if (bytes/packets > 8000)
2524                         retval = bulk_latency;
2525                 else if ((packets < 5) && (bytes > 512))
2526                         retval = low_latency;
2527                 break;
2528         case low_latency:  /* 50 usec aka 20000 ints/s */
2529                 if (bytes > 10000) {
2530                         /* this if handles the TSO accounting */
2531                         if (bytes/packets > 8000) {
2532                                 retval = bulk_latency;
2533                         } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2534                                 retval = bulk_latency;
2535                         } else if ((packets > 35)) {
2536                                 retval = lowest_latency;
2537                         }
2538                 } else if (bytes/packets > 2000) {
2539                         retval = bulk_latency;
2540                 } else if (packets <= 2 && bytes < 512) {
2541                         retval = lowest_latency;
2542                 }
2543                 break;
2544         case bulk_latency: /* 250 usec aka 4000 ints/s */
2545                 if (bytes > 25000) {
2546                         if (packets > 35)
2547                                 retval = low_latency;
2548                 } else if (bytes < 6000) {
2549                         retval = low_latency;
2550                 }
2551                 break;
2552         }
2553
2554 update_itr_done:
2555         return retval;
2556 }
2557
2558 static void igb_set_itr(struct igb_adapter *adapter)
2559 {
2560         u16 current_itr;
2561         u32 new_itr = adapter->itr;
2562
2563         /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2564         if (adapter->link_speed != SPEED_1000) {
2565                 current_itr = 0;
2566                 new_itr = 4000;
2567                 goto set_itr_now;
2568         }
2569
2570         adapter->rx_itr = igb_update_itr(adapter,
2571                                     adapter->rx_itr,
2572                                     adapter->rx_ring->total_packets,
2573                                     adapter->rx_ring->total_bytes);
2574
2575         if (adapter->rx_ring->buddy) {
2576                 adapter->tx_itr = igb_update_itr(adapter,
2577                                             adapter->tx_itr,
2578                                             adapter->tx_ring->total_packets,
2579                                             adapter->tx_ring->total_bytes);
2580
2581                 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2582         } else {
2583                 current_itr = adapter->rx_itr;
2584         }
2585
2586         /* conservative mode (itr 3) eliminates the lowest_latency setting */
2587         if (adapter->itr_setting == 3 &&
2588             current_itr == lowest_latency)
2589                 current_itr = low_latency;
2590
2591         switch (current_itr) {
2592         /* counts and packets in update_itr are dependent on these numbers */
2593         case lowest_latency:
2594                 new_itr = 70000;
2595                 break;
2596         case low_latency:
2597                 new_itr = 20000; /* aka hwitr = ~200 */
2598                 break;
2599         case bulk_latency:
2600                 new_itr = 4000;
2601                 break;
2602         default:
2603                 break;
2604         }
2605
2606 set_itr_now:
2607         adapter->rx_ring->total_bytes = 0;
2608         adapter->rx_ring->total_packets = 0;
2609         if (adapter->rx_ring->buddy) {
2610                 adapter->rx_ring->buddy->total_bytes = 0;
2611                 adapter->rx_ring->buddy->total_packets = 0;
2612         }
2613
2614         if (new_itr != adapter->itr) {
2615                 /* this attempts to bias the interrupt rate towards Bulk
2616                  * by adding intermediate steps when interrupt rate is
2617                  * increasing */
2618                 new_itr = new_itr > adapter->itr ?
2619                              min(adapter->itr + (new_itr >> 2), new_itr) :
2620                              new_itr;
2621                 /* Don't write the value here; it resets the adapter's
2622                  * internal timer, and causes us to delay far longer than
2623                  * we should between interrupts.  Instead, we write the ITR
2624                  * value at the beginning of the next interrupt so the timing
2625                  * ends up being correct.
2626                  */
2627                 adapter->itr = new_itr;
2628                 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2629                 adapter->rx_ring->set_itr = 1;
2630         }
2631
2632         return;
2633 }
2634
2635
2636 #define IGB_TX_FLAGS_CSUM               0x00000001
2637 #define IGB_TX_FLAGS_VLAN               0x00000002
2638 #define IGB_TX_FLAGS_TSO                0x00000004
2639 #define IGB_TX_FLAGS_IPV4               0x00000008
2640 #define IGB_TX_FLAGS_VLAN_MASK  0xffff0000
2641 #define IGB_TX_FLAGS_VLAN_SHIFT 16
2642
2643 static inline int igb_tso_adv(struct igb_adapter *adapter,
2644                               struct igb_ring *tx_ring,
2645                               struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2646 {
2647         struct e1000_adv_tx_context_desc *context_desc;
2648         unsigned int i;
2649         int err;
2650         struct igb_buffer *buffer_info;
2651         u32 info = 0, tu_cmd = 0;
2652         u32 mss_l4len_idx, l4len;
2653         *hdr_len = 0;
2654
2655         if (skb_header_cloned(skb)) {
2656                 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2657                 if (err)
2658                         return err;
2659         }
2660
2661         l4len = tcp_hdrlen(skb);
2662         *hdr_len += l4len;
2663
2664         if (skb->protocol == htons(ETH_P_IP)) {
2665                 struct iphdr *iph = ip_hdr(skb);
2666                 iph->tot_len = 0;
2667                 iph->check = 0;
2668                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2669                                                          iph->daddr, 0,
2670                                                          IPPROTO_TCP,
2671                                                          0);
2672         } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2673                 ipv6_hdr(skb)->payload_len = 0;
2674                 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2675                                                        &ipv6_hdr(skb)->daddr,
2676                                                        0, IPPROTO_TCP, 0);
2677         }
2678
2679         i = tx_ring->next_to_use;
2680
2681         buffer_info = &tx_ring->buffer_info[i];
2682         context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2683         /* VLAN MACLEN IPLEN */
2684         if (tx_flags & IGB_TX_FLAGS_VLAN)
2685                 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2686         info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2687         *hdr_len += skb_network_offset(skb);
2688         info |= skb_network_header_len(skb);
2689         *hdr_len += skb_network_header_len(skb);
2690         context_desc->vlan_macip_lens = cpu_to_le32(info);
2691
2692         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2693         tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2694
2695         if (skb->protocol == htons(ETH_P_IP))
2696                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2697         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2698
2699         context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2700
2701         /* MSS L4LEN IDX */
2702         mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2703         mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2704
2705         /* Context index must be unique per ring. */
2706         if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2707                 mss_l4len_idx |= tx_ring->queue_index << 4;
2708
2709         context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2710         context_desc->seqnum_seed = 0;
2711
2712         buffer_info->time_stamp = jiffies;
2713         buffer_info->next_to_watch = i;
2714         buffer_info->dma = 0;
2715         i++;
2716         if (i == tx_ring->count)
2717                 i = 0;
2718
2719         tx_ring->next_to_use = i;
2720
2721         return true;
2722 }
2723
2724 static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2725                                         struct igb_ring *tx_ring,
2726                                         struct sk_buff *skb, u32 tx_flags)
2727 {
2728         struct e1000_adv_tx_context_desc *context_desc;
2729         unsigned int i;
2730         struct igb_buffer *buffer_info;
2731         u32 info = 0, tu_cmd = 0;
2732
2733         if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2734             (tx_flags & IGB_TX_FLAGS_VLAN)) {
2735                 i = tx_ring->next_to_use;
2736                 buffer_info = &tx_ring->buffer_info[i];
2737                 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2738
2739                 if (tx_flags & IGB_TX_FLAGS_VLAN)
2740                         info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2741                 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2742                 if (skb->ip_summed == CHECKSUM_PARTIAL)
2743                         info |= skb_network_header_len(skb);
2744
2745                 context_desc->vlan_macip_lens = cpu_to_le32(info);
2746
2747                 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2748
2749                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2750                         switch (skb->protocol) {
2751                         case cpu_to_be16(ETH_P_IP):
2752                                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2753                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2754                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2755                                 break;
2756                         case cpu_to_be16(ETH_P_IPV6):
2757                                 /* XXX what about other V6 headers?? */
2758                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2759                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2760                                 break;
2761                         default:
2762                                 if (unlikely(net_ratelimit()))
2763                                         dev_warn(&adapter->pdev->dev,
2764                                             "partial checksum but proto=%x!\n",
2765                                             skb->protocol);
2766                                 break;
2767                         }
2768                 }
2769
2770                 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2771                 context_desc->seqnum_seed = 0;
2772                 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2773                         context_desc->mss_l4len_idx =
2774                                 cpu_to_le32(tx_ring->queue_index << 4);
2775
2776                 buffer_info->time_stamp = jiffies;
2777                 buffer_info->next_to_watch = i;
2778                 buffer_info->dma = 0;
2779
2780                 i++;
2781                 if (i == tx_ring->count)
2782                         i = 0;
2783                 tx_ring->next_to_use = i;
2784
2785                 return true;
2786         }
2787
2788
2789         return false;
2790 }
2791
2792 #define IGB_MAX_TXD_PWR 16
2793 #define IGB_MAX_DATA_PER_TXD    (1<<IGB_MAX_TXD_PWR)
2794
2795 static inline int igb_tx_map_adv(struct igb_adapter *adapter,
2796                                  struct igb_ring *tx_ring, struct sk_buff *skb,
2797                                  unsigned int first)
2798 {
2799         struct igb_buffer *buffer_info;
2800         unsigned int len = skb_headlen(skb);
2801         unsigned int count = 0, i;
2802         unsigned int f;
2803
2804         i = tx_ring->next_to_use;
2805
2806         buffer_info = &tx_ring->buffer_info[i];
2807         BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2808         buffer_info->length = len;
2809         /* set time_stamp *before* dma to help avoid a possible race */
2810         buffer_info->time_stamp = jiffies;
2811         buffer_info->next_to_watch = i;
2812         buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2813                                           PCI_DMA_TODEVICE);
2814         count++;
2815         i++;
2816         if (i == tx_ring->count)
2817                 i = 0;
2818
2819         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2820                 struct skb_frag_struct *frag;
2821
2822                 frag = &skb_shinfo(skb)->frags[f];
2823                 len = frag->size;
2824
2825                 buffer_info = &tx_ring->buffer_info[i];
2826                 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2827                 buffer_info->length = len;
2828                 buffer_info->time_stamp = jiffies;
2829                 buffer_info->next_to_watch = i;
2830                 buffer_info->dma = pci_map_page(adapter->pdev,
2831                                                 frag->page,
2832                                                 frag->page_offset,
2833                                                 len,
2834                                                 PCI_DMA_TODEVICE);
2835
2836                 count++;
2837                 i++;
2838                 if (i == tx_ring->count)
2839                         i = 0;
2840         }
2841
2842         i = ((i == 0) ? tx_ring->count - 1 : i - 1);
2843         tx_ring->buffer_info[i].skb = skb;
2844         tx_ring->buffer_info[first].next_to_watch = i;
2845
2846         return count;
2847 }
2848
2849 static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2850                                     struct igb_ring *tx_ring,
2851                                     int tx_flags, int count, u32 paylen,
2852                                     u8 hdr_len)
2853 {
2854         union e1000_adv_tx_desc *tx_desc = NULL;
2855         struct igb_buffer *buffer_info;
2856         u32 olinfo_status = 0, cmd_type_len;
2857         unsigned int i;
2858
2859         cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2860                         E1000_ADVTXD_DCMD_DEXT);
2861
2862         if (tx_flags & IGB_TX_FLAGS_VLAN)
2863                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2864
2865         if (tx_flags & IGB_TX_FLAGS_TSO) {
2866                 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2867
2868                 /* insert tcp checksum */
2869                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2870
2871                 /* insert ip checksum */
2872                 if (tx_flags & IGB_TX_FLAGS_IPV4)
2873                         olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2874
2875         } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2876                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2877         }
2878
2879         if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
2880             (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2881                          IGB_TX_FLAGS_VLAN)))
2882                 olinfo_status |= tx_ring->queue_index << 4;
2883
2884         olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2885
2886         i = tx_ring->next_to_use;
2887         while (count--) {
2888                 buffer_info = &tx_ring->buffer_info[i];
2889                 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2890                 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2891                 tx_desc->read.cmd_type_len =
2892                         cpu_to_le32(cmd_type_len | buffer_info->length);
2893                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2894                 i++;
2895                 if (i == tx_ring->count)
2896                         i = 0;
2897         }
2898
2899         tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2900         /* Force memory writes to complete before letting h/w
2901          * know there are new descriptors to fetch.  (Only
2902          * applicable for weak-ordered memory model archs,
2903          * such as IA-64). */
2904         wmb();
2905
2906         tx_ring->next_to_use = i;
2907         writel(i, adapter->hw.hw_addr + tx_ring->tail);
2908         /* we need this if more than one processor can write to our tail
2909          * at a time, it syncronizes IO on IA64/Altix systems */
2910         mmiowb();
2911 }
2912
2913 static int __igb_maybe_stop_tx(struct net_device *netdev,
2914                                struct igb_ring *tx_ring, int size)
2915 {
2916         struct igb_adapter *adapter = netdev_priv(netdev);
2917
2918         netif_stop_subqueue(netdev, tx_ring->queue_index);
2919
2920         /* Herbert's original patch had:
2921          *  smp_mb__after_netif_stop_queue();
2922          * but since that doesn't exist yet, just open code it. */
2923         smp_mb();
2924
2925         /* We need to check again in a case another CPU has just
2926          * made room available. */
2927         if (IGB_DESC_UNUSED(tx_ring) < size)
2928                 return -EBUSY;
2929
2930         /* A reprieve! */
2931         netif_wake_subqueue(netdev, tx_ring->queue_index);
2932         ++adapter->restart_queue;
2933         return 0;
2934 }
2935
2936 static int igb_maybe_stop_tx(struct net_device *netdev,
2937                              struct igb_ring *tx_ring, int size)
2938 {
2939         if (IGB_DESC_UNUSED(tx_ring) >= size)
2940                 return 0;
2941         return __igb_maybe_stop_tx(netdev, tx_ring, size);
2942 }
2943
2944 #define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2945
2946 static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2947                                    struct net_device *netdev,
2948                                    struct igb_ring *tx_ring)
2949 {
2950         struct igb_adapter *adapter = netdev_priv(netdev);
2951         unsigned int first;
2952         unsigned int tx_flags = 0;
2953         unsigned int len;
2954         u8 hdr_len = 0;
2955         int tso = 0;
2956
2957         len = skb_headlen(skb);
2958
2959         if (test_bit(__IGB_DOWN, &adapter->state)) {
2960                 dev_kfree_skb_any(skb);
2961                 return NETDEV_TX_OK;
2962         }
2963
2964         if (skb->len <= 0) {
2965                 dev_kfree_skb_any(skb);
2966                 return NETDEV_TX_OK;
2967         }
2968
2969         /* need: 1 descriptor per page,
2970          *       + 2 desc gap to keep tail from touching head,
2971          *       + 1 desc for skb->data,
2972          *       + 1 desc for context descriptor,
2973          * otherwise try next time */
2974         if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2975                 /* this is a hard error */
2976                 return NETDEV_TX_BUSY;
2977         }
2978         skb_orphan(skb);
2979
2980         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2981                 tx_flags |= IGB_TX_FLAGS_VLAN;
2982                 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2983         }
2984
2985         if (skb->protocol == htons(ETH_P_IP))
2986                 tx_flags |= IGB_TX_FLAGS_IPV4;
2987
2988         first = tx_ring->next_to_use;
2989
2990         tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2991                                               &hdr_len) : 0;
2992
2993         if (tso < 0) {
2994                 dev_kfree_skb_any(skb);
2995                 return NETDEV_TX_OK;
2996         }
2997
2998         if (tso)
2999                 tx_flags |= IGB_TX_FLAGS_TSO;
3000         else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
3001                         if (skb->ip_summed == CHECKSUM_PARTIAL)
3002                                 tx_flags |= IGB_TX_FLAGS_CSUM;
3003
3004         igb_tx_queue_adv(adapter, tx_ring, tx_flags,
3005                          igb_tx_map_adv(adapter, tx_ring, skb, first),
3006                          skb->len, hdr_len);
3007
3008         netdev->trans_start = jiffies;
3009
3010         /* Make sure there is space in the ring for the next send. */
3011         igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3012
3013         return NETDEV_TX_OK;
3014 }
3015
3016 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3017 {
3018         struct igb_adapter *adapter = netdev_priv(netdev);
3019         struct igb_ring *tx_ring;
3020
3021         int r_idx = 0;
3022         r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1);
3023         tx_ring = adapter->multi_tx_table[r_idx];
3024
3025         /* This goes back to the question of how to logically map a tx queue
3026          * to a flow.  Right now, performance is impacted slightly negatively
3027          * if using multiple tx queues.  If the stack breaks away from a
3028          * single qdisc implementation, we can look at this again. */
3029         return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3030 }
3031
3032 /**
3033  * igb_tx_timeout - Respond to a Tx Hang
3034  * @netdev: network interface device structure
3035  **/
3036 static void igb_tx_timeout(struct net_device *netdev)
3037 {
3038         struct igb_adapter *adapter = netdev_priv(netdev);
3039         struct e1000_hw *hw = &adapter->hw;
3040
3041         /* Do the reset outside of interrupt context */
3042         adapter->tx_timeout_count++;
3043         schedule_work(&adapter->reset_task);
3044         wr32(E1000_EICS, adapter->eims_enable_mask &
3045                 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
3046 }
3047
3048 static void igb_reset_task(struct work_struct *work)
3049 {
3050         struct igb_adapter *adapter;
3051         adapter = container_of(work, struct igb_adapter, reset_task);
3052
3053         igb_reinit_locked(adapter);
3054 }
3055
3056 /**
3057  * igb_get_stats - Get System Network Statistics
3058  * @netdev: network interface device structure
3059  *
3060  * Returns the address of the device statistics structure.
3061  * The statistics are actually updated from the timer callback.
3062  **/
3063 static struct net_device_stats *
3064 igb_get_stats(struct net_device *netdev)
3065 {
3066         struct igb_adapter *adapter = netdev_priv(netdev);
3067
3068         /* only return the current stats */
3069         return &adapter->net_stats;
3070 }
3071
3072 /**
3073  * igb_change_mtu - Change the Maximum Transfer Unit
3074  * @netdev: network interface device structure
3075  * @new_mtu: new value for maximum frame size
3076  *
3077  * Returns 0 on success, negative on failure
3078  **/
3079 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3080 {
3081         struct igb_adapter *adapter = netdev_priv(netdev);
3082         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3083
3084         if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3085             (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3086                 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3087                 return -EINVAL;
3088         }
3089
3090 #define MAX_STD_JUMBO_FRAME_SIZE 9234
3091         if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3092                 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3093                 return -EINVAL;
3094         }
3095
3096         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3097                 msleep(1);
3098         /* igb_down has a dependency on max_frame_size */
3099         adapter->max_frame_size = max_frame;
3100         if (netif_running(netdev))
3101                 igb_down(adapter);
3102
3103         /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3104          * means we reserve 2 more, this pushes us to allocate from the next
3105          * larger slab size.
3106          * i.e. RXBUFFER_2048 --> size-4096 slab
3107          */
3108
3109         if (max_frame <= IGB_RXBUFFER_256)
3110                 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3111         else if (max_frame <= IGB_RXBUFFER_512)
3112                 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3113         else if (max_frame <= IGB_RXBUFFER_1024)
3114                 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3115         else if (max_frame <= IGB_RXBUFFER_2048)
3116                 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3117         else
3118 #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3119                 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3120 #else
3121                 adapter->rx_buffer_len = PAGE_SIZE / 2;
3122 #endif
3123         /* adjust allocation if LPE protects us, and we aren't using SBP */
3124         if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3125              (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3126                 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3127
3128         dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3129                  netdev->mtu, new_mtu);
3130         netdev->mtu = new_mtu;
3131
3132         if (netif_running(netdev))
3133                 igb_up(adapter);
3134         else
3135                 igb_reset(adapter);
3136
3137         clear_bit(__IGB_RESETTING, &adapter->state);
3138
3139         return 0;
3140 }
3141
3142 /**
3143  * igb_update_stats - Update the board statistics counters
3144  * @adapter: board private structure
3145  **/
3146
3147 void igb_update_stats(struct igb_adapter *adapter)
3148 {
3149         struct e1000_hw *hw = &adapter->hw;
3150         struct pci_dev *pdev = adapter->pdev;
3151         u16 phy_tmp;
3152
3153 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3154
3155         /*
3156          * Prevent stats update while adapter is being reset, or if the pci
3157          * connection is down.
3158          */
3159         if (adapter->link_speed == 0)
3160                 return;
3161         if (pci_channel_offline(pdev))
3162                 return;
3163
3164         adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3165         adapter->stats.gprc += rd32(E1000_GPRC);
3166         adapter->stats.gorc += rd32(E1000_GORCL);
3167         rd32(E1000_GORCH); /* clear GORCL */
3168         adapter->stats.bprc += rd32(E1000_BPRC);
3169         adapter->stats.mprc += rd32(E1000_MPRC);
3170         adapter->stats.roc += rd32(E1000_ROC);
3171
3172         adapter->stats.prc64 += rd32(E1000_PRC64);
3173         adapter->stats.prc127 += rd32(E1000_PRC127);
3174         adapter->stats.prc255 += rd32(E1000_PRC255);
3175         adapter->stats.prc511 += rd32(E1000_PRC511);
3176         adapter->stats.prc1023 += rd32(E1000_PRC1023);
3177         adapter->stats.prc1522 += rd32(E1000_PRC1522);
3178         adapter->stats.symerrs += rd32(E1000_SYMERRS);
3179         adapter->stats.sec += rd32(E1000_SEC);
3180
3181         adapter->stats.mpc += rd32(E1000_MPC);
3182         adapter->stats.scc += rd32(E1000_SCC);
3183         adapter->stats.ecol += rd32(E1000_ECOL);
3184         adapter->stats.mcc += rd32(E1000_MCC);
3185         adapter->stats.latecol += rd32(E1000_LATECOL);
3186         adapter->stats.dc += rd32(E1000_DC);
3187         adapter->stats.rlec += rd32(E1000_RLEC);
3188         adapter->stats.xonrxc += rd32(E1000_XONRXC);
3189         adapter->stats.xontxc += rd32(E1000_XONTXC);
3190         adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3191         adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3192         adapter->stats.fcruc += rd32(E1000_FCRUC);
3193         adapter->stats.gptc += rd32(E1000_GPTC);
3194         adapter->stats.gotc += rd32(E1000_GOTCL);
3195         rd32(E1000_GOTCH); /* clear GOTCL */
3196         adapter->stats.rnbc += rd32(E1000_RNBC);
3197         adapter->stats.ruc += rd32(E1000_RUC);
3198         adapter->stats.rfc += rd32(E1000_RFC);
3199         adapter->stats.rjc += rd32(E1000_RJC);
3200         adapter->stats.tor += rd32(E1000_TORH);
3201         adapter->stats.tot += rd32(E1000_TOTH);
3202         adapter->stats.tpr += rd32(E1000_TPR);
3203
3204         adapter->stats.ptc64 += rd32(E1000_PTC64);
3205         adapter->stats.ptc127 += rd32(E1000_PTC127);
3206         adapter->stats.ptc255 += rd32(E1000_PTC255);
3207         adapter->stats.ptc511 += rd32(E1000_PTC511);
3208         adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3209         adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3210
3211         adapter->stats.mptc += rd32(E1000_MPTC);
3212         adapter->stats.bptc += rd32(E1000_BPTC);
3213
3214         /* used for adaptive IFS */
3215
3216         hw->mac.tx_packet_delta = rd32(E1000_TPT);
3217         adapter->stats.tpt += hw->mac.tx_packet_delta;
3218         hw->mac.collision_delta = rd32(E1000_COLC);
3219         adapter->stats.colc += hw->mac.collision_delta;
3220
3221         adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3222         adapter->stats.rxerrc += rd32(E1000_RXERRC);
3223         adapter->stats.tncrs += rd32(E1000_TNCRS);
3224         adapter->stats.tsctc += rd32(E1000_TSCTC);
3225         adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3226
3227         adapter->stats.iac += rd32(E1000_IAC);
3228         adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3229         adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3230         adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3231         adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3232         adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3233         adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3234         adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3235         adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3236
3237         /* Fill out the OS statistics structure */
3238         adapter->net_stats.multicast = adapter->stats.mprc;
3239         adapter->net_stats.collisions = adapter->stats.colc;
3240
3241         /* Rx Errors */
3242
3243         /* RLEC on some newer hardware can be incorrect so build
3244         * our own version based on RUC and ROC */
3245         adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3246                 adapter->stats.crcerrs + adapter->stats.algnerrc +
3247                 adapter->stats.ruc + adapter->stats.roc +
3248                 adapter->stats.cexterr;
3249         adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3250                                               adapter->stats.roc;
3251         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3252         adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3253         adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3254
3255         /* Tx Errors */
3256         adapter->net_stats.tx_errors = adapter->stats.ecol +
3257                                        adapter->stats.latecol;
3258         adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3259         adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3260         adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3261
3262         /* Tx Dropped needs to be maintained elsewhere */
3263
3264         /* Phy Stats */
3265         if (hw->phy.media_type == e1000_media_type_copper) {
3266                 if ((adapter->link_speed == SPEED_1000) &&
3267                    (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
3268                                               &phy_tmp))) {
3269                         phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3270                         adapter->phy_stats.idle_errors += phy_tmp;
3271                 }
3272         }
3273
3274         /* Management Stats */
3275         adapter->stats.mgptc += rd32(E1000_MGTPTC);
3276         adapter->stats.mgprc += rd32(E1000_MGTPRC);
3277         adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3278 }
3279
3280
3281 static irqreturn_t igb_msix_other(int irq, void *data)
3282 {
3283         struct net_device *netdev = data;
3284         struct igb_adapter *adapter = netdev_priv(netdev);
3285         struct e1000_hw *hw = &adapter->hw;
3286         u32 icr = rd32(E1000_ICR);
3287
3288         /* reading ICR causes bit 31 of EICR to be cleared */
3289         if (!(icr & E1000_ICR_LSC))
3290                 goto no_link_interrupt;
3291         hw->mac.get_link_status = 1;
3292         /* guard against interrupt when we're going down */
3293         if (!test_bit(__IGB_DOWN, &adapter->state))
3294                 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3295
3296 no_link_interrupt:
3297         wr32(E1000_IMS, E1000_IMS_LSC);
3298         wr32(E1000_EIMS, adapter->eims_other);
3299
3300         return IRQ_HANDLED;
3301 }
3302
3303 static irqreturn_t igb_msix_tx(int irq, void *data)
3304 {
3305         struct igb_ring *tx_ring = data;
3306         struct igb_adapter *adapter = tx_ring->adapter;
3307         struct e1000_hw *hw = &adapter->hw;
3308
3309 #ifdef CONFIG_IGB_DCA
3310         if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3311                 igb_update_tx_dca(tx_ring);
3312 #endif
3313         tx_ring->total_bytes = 0;
3314         tx_ring->total_packets = 0;
3315
3316         /* auto mask will automatically reenable the interrupt when we write
3317          * EICS */
3318         if (!igb_clean_tx_irq(tx_ring))
3319                 /* Ring was not completely cleaned, so fire another interrupt */
3320                 wr32(E1000_EICS, tx_ring->eims_value);
3321         else
3322                 wr32(E1000_EIMS, tx_ring->eims_value);
3323
3324         return IRQ_HANDLED;
3325 }
3326
3327 static void igb_write_itr(struct igb_ring *ring)
3328 {
3329         struct e1000_hw *hw = &ring->adapter->hw;
3330         if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3331                 switch (hw->mac.type) {
3332                 case e1000_82576:
3333                         wr32(ring->itr_register,
3334                              ring->itr_val |
3335                              0x80000000);
3336                         break;
3337                 default:
3338                         wr32(ring->itr_register,
3339                              ring->itr_val |
3340                              (ring->itr_val << 16));
3341                         break;
3342                 }
3343                 ring->set_itr = 0;
3344         }
3345 }
3346
3347 static irqreturn_t igb_msix_rx(int irq, void *data)
3348 {
3349         struct igb_ring *rx_ring = data;
3350
3351         /* Write the ITR value calculated at the end of the
3352          * previous interrupt.
3353          */
3354
3355         igb_write_itr(rx_ring);
3356
3357         if (napi_schedule_prep(&rx_ring->napi))
3358                 __napi_schedule(&rx_ring->napi);
3359
3360 #ifdef CONFIG_IGB_DCA
3361         if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
3362                 igb_update_rx_dca(rx_ring);
3363 #endif
3364                 return IRQ_HANDLED;
3365 }
3366
3367 #ifdef CONFIG_IGB_DCA
3368 static void igb_update_rx_dca(struct igb_ring *rx_ring)
3369 {
3370         u32 dca_rxctrl;
3371         struct igb_adapter *adapter = rx_ring->adapter;
3372         struct e1000_hw *hw = &adapter->hw;
3373         int cpu = get_cpu();
3374         int q = rx_ring->reg_idx;
3375
3376         if (rx_ring->cpu != cpu) {
3377                 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
3378                 if (hw->mac.type == e1000_82576) {
3379                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3380                         dca_rxctrl |= dca_get_tag(cpu) <<
3381                                       E1000_DCA_RXCTRL_CPUID_SHIFT;
3382                 } else {
3383                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3384                         dca_rxctrl |= dca_get_tag(cpu);
3385                 }
3386                 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3387                 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3388                 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3389                 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3390                 rx_ring->cpu = cpu;
3391         }
3392         put_cpu();
3393 }
3394
3395 static void igb_update_tx_dca(struct igb_ring *tx_ring)
3396 {
3397         u32 dca_txctrl;
3398         struct igb_adapter *adapter = tx_ring->adapter;
3399         struct e1000_hw *hw = &adapter->hw;
3400         int cpu = get_cpu();
3401         int q = tx_ring->reg_idx;
3402
3403         if (tx_ring->cpu != cpu) {
3404                 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
3405                 if (hw->mac.type == e1000_82576) {
3406                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3407                         dca_txctrl |= dca_get_tag(cpu) <<
3408                                       E1000_DCA_TXCTRL_CPUID_SHIFT;
3409                 } else {
3410                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3411                         dca_txctrl |= dca_get_tag(cpu);
3412                 }
3413                 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3414                 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3415                 tx_ring->cpu = cpu;
3416         }
3417         put_cpu();
3418 }
3419
3420 static void igb_setup_dca(struct igb_adapter *adapter)
3421 {
3422         int i;
3423
3424         if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
3425                 return;
3426
3427         for (i = 0; i < adapter->num_tx_queues; i++) {
3428                 adapter->tx_ring[i].cpu = -1;
3429                 igb_update_tx_dca(&adapter->tx_ring[i]);
3430         }
3431         for (i = 0; i < adapter->num_rx_queues; i++) {
3432                 adapter->rx_ring[i].cpu = -1;
3433                 igb_update_rx_dca(&adapter->rx_ring[i]);
3434         }
3435 }
3436
3437 static int __igb_notify_dca(struct device *dev, void *data)
3438 {
3439         struct net_device *netdev = dev_get_drvdata(dev);
3440         struct igb_adapter *adapter = netdev_priv(netdev);
3441         struct e1000_hw *hw = &adapter->hw;
3442         unsigned long event = *(unsigned long *)data;
3443
3444         switch (event) {
3445         case DCA_PROVIDER_ADD:
3446                 /* if already enabled, don't do it again */
3447                 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3448                         break;
3449                 /* Always use CB2 mode, difference is masked
3450                  * in the CB driver. */
3451                 wr32(E1000_DCA_CTRL, 2);
3452                 if (dca_add_requester(dev) == 0) {
3453                         adapter->flags |= IGB_FLAG_DCA_ENABLED;
3454                         dev_info(&adapter->pdev->dev, "DCA enabled\n");
3455                         igb_setup_dca(adapter);
3456                         break;
3457                 }
3458                 /* Fall Through since DCA is disabled. */
3459         case DCA_PROVIDER_REMOVE:
3460                 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3461                         /* without this a class_device is left
3462                          * hanging around in the sysfs model */
3463                         dca_remove_requester(dev);
3464                         dev_info(&adapter->pdev->dev, "DCA disabled\n");
3465                         adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3466                         wr32(E1000_DCA_CTRL, 1);
3467                 }
3468                 break;
3469         }
3470
3471         return 0;
3472 }
3473
3474 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3475                           void *p)
3476 {
3477         int ret_val;
3478
3479         ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3480                                          __igb_notify_dca);
3481
3482         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3483 }
3484 #endif /* CONFIG_IGB_DCA */
3485
3486 /**
3487  * igb_intr_msi - Interrupt Handler
3488  * @irq: interrupt number
3489  * @data: pointer to a network interface device structure
3490  **/
3491 static irqreturn_t igb_intr_msi(int irq, void *data)
3492 {
3493         struct net_device *netdev = data;
3494         struct igb_adapter *adapter = netdev_priv(netdev);
3495         struct e1000_hw *hw = &adapter->hw;
3496         /* read ICR disables interrupts using IAM */
3497         u32 icr = rd32(E1000_ICR);
3498
3499         igb_write_itr(adapter->rx_ring);
3500
3501         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3502                 hw->mac.get_link_status = 1;
3503                 if (!test_bit(__IGB_DOWN, &adapter->state))
3504                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
3505         }
3506
3507         napi_schedule(&adapter->rx_ring[0].napi);
3508
3509         return IRQ_HANDLED;
3510 }
3511
3512 /**
3513  * igb_intr - Interrupt Handler
3514  * @irq: interrupt number
3515  * @data: pointer to a network interface device structure
3516  **/
3517 static irqreturn_t igb_intr(int irq, void *data)
3518 {
3519         struct net_device *netdev = data;
3520         struct igb_adapter *adapter = netdev_priv(netdev);
3521         struct e1000_hw *hw = &adapter->hw;
3522         /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
3523          * need for the IMC write */
3524         u32 icr = rd32(E1000_ICR);
3525         u32 eicr = 0;
3526         if (!icr)
3527                 return IRQ_NONE;  /* Not our interrupt */
3528
3529         igb_write_itr(adapter->rx_ring);
3530
3531         /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3532          * not set, then the adapter didn't send an interrupt */
3533         if (!(icr & E1000_ICR_INT_ASSERTED))
3534                 return IRQ_NONE;
3535
3536         eicr = rd32(E1000_EICR);
3537
3538         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3539                 hw->mac.get_link_status = 1;
3540                 /* guard against interrupt when we're going down */
3541                 if (!test_bit(__IGB_DOWN, &adapter->state))
3542                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
3543         }
3544
3545         napi_schedule(&adapter->rx_ring[0].napi);
3546
3547         return IRQ_HANDLED;
3548 }
3549
3550 /**
3551  * igb_poll - NAPI Rx polling callback
3552  * @napi: napi polling structure
3553  * @budget: count of how many packets we should handle
3554  **/
3555 static int igb_poll(struct napi_struct *napi, int budget)
3556 {
3557         struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3558         struct igb_adapter *adapter = rx_ring->adapter;
3559         struct net_device *netdev = adapter->netdev;
3560         int tx_clean_complete, work_done = 0;
3561
3562         /* this poll routine only supports one tx and one rx queue */
3563 #ifdef CONFIG_IGB_DCA
3564         if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3565                 igb_update_tx_dca(&adapter->tx_ring[0]);
3566 #endif
3567         tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]);
3568
3569 #ifdef CONFIG_IGB_DCA
3570         if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3571                 igb_update_rx_dca(&adapter->rx_ring[0]);
3572 #endif
3573         igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget);
3574
3575         /* If no Tx and not enough Rx work done, exit the polling mode */
3576         if ((tx_clean_complete && (work_done < budget)) ||
3577             !netif_running(netdev)) {
3578                 if (adapter->itr_setting & 3)
3579                         igb_set_itr(adapter);
3580                 napi_complete(napi);
3581                 if (!test_bit(__IGB_DOWN, &adapter->state))
3582                         igb_irq_enable(adapter);
3583                 return 0;
3584         }
3585
3586         return 1;
3587 }
3588
3589 static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3590 {
3591         struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3592         struct igb_adapter *adapter = rx_ring->adapter;
3593         struct e1000_hw *hw = &adapter->hw;
3594         struct net_device *netdev = adapter->netdev;
3595         int work_done = 0;
3596
3597 #ifdef CONFIG_IGB_DCA
3598         if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3599                 igb_update_rx_dca(rx_ring);
3600 #endif
3601         igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
3602
3603
3604         /* If not enough Rx work done, exit the polling mode */
3605         if ((work_done == 0) || !netif_running(netdev)) {
3606                 napi_complete(napi);
3607
3608                 if (adapter->itr_setting & 3) {
3609                         if (adapter->num_rx_queues == 1)
3610                                 igb_set_itr(adapter);
3611                         else
3612                                 igb_update_ring_itr(rx_ring);
3613                 }
3614
3615                 if (!test_bit(__IGB_DOWN, &adapter->state))
3616                         wr32(E1000_EIMS, rx_ring->eims_value);
3617
3618                 return 0;
3619         }
3620
3621         return 1;
3622 }
3623
3624 /**
3625  * igb_clean_tx_irq - Reclaim resources after transmit completes
3626  * @adapter: board private structure
3627  * returns true if ring is completely cleaned
3628  **/
3629 static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
3630 {
3631         struct igb_adapter *adapter = tx_ring->adapter;
3632         struct net_device *netdev = adapter->netdev;
3633         struct e1000_hw *hw = &adapter->hw;
3634         struct igb_buffer *buffer_info;
3635         struct sk_buff *skb;
3636         union e1000_adv_tx_desc *tx_desc, *eop_desc;
3637         unsigned int total_bytes = 0, total_packets = 0;
3638         unsigned int i, eop, count = 0;
3639         bool cleaned = false;
3640
3641         i = tx_ring->next_to_clean;
3642         eop = tx_ring->buffer_info[i].next_to_watch;
3643         eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3644
3645         while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
3646                (count < tx_ring->count)) {
3647                 for (cleaned = false; !cleaned; count++) {
3648                         tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3649                         buffer_info = &tx_ring->buffer_info[i];
3650                         cleaned = (i == eop);
3651                         skb = buffer_info->skb;
3652
3653                         if (skb) {
3654                                 unsigned int segs, bytecount;
3655                                 /* gso_segs is currently only valid for tcp */
3656                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
3657                                 /* multiply data chunks by size of headers */
3658                                 bytecount = ((segs - 1) * skb_headlen(skb)) +
3659                                             skb->len;
3660                                 total_packets += segs;
3661                                 total_bytes += bytecount;
3662                         }
3663
3664                         igb_unmap_and_free_tx_resource(adapter, buffer_info);
3665                         tx_desc->wb.status = 0;
3666
3667                         i++;
3668                         if (i == tx_ring->count)
3669                                 i = 0;
3670                 }
3671
3672                 eop = tx_ring->buffer_info[i].next_to_watch;
3673                 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3674         }
3675
3676         tx_ring->next_to_clean = i;
3677
3678         if (unlikely(count &&
3679                      netif_carrier_ok(netdev) &&
3680                      IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3681                 /* Make sure that anybody stopping the queue after this
3682                  * sees the new next_to_clean.
3683                  */
3684                 smp_mb();
3685                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3686                     !(test_bit(__IGB_DOWN, &adapter->state))) {
3687                         netif_wake_subqueue(netdev, tx_ring->queue_index);
3688                         ++adapter->restart_queue;
3689                 }
3690         }
3691
3692         if (tx_ring->detect_tx_hung) {
3693                 /* Detect a transmit hang in hardware, this serializes the
3694                  * check with the clearing of time_stamp and movement of i */
3695                 tx_ring->detect_tx_hung = false;
3696                 if (tx_ring->buffer_info[i].time_stamp &&
3697                     time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3698                                (adapter->tx_timeout_factor * HZ))
3699                     && !(rd32(E1000_STATUS) &
3700                          E1000_STATUS_TXOFF)) {
3701
3702                         /* detected Tx unit hang */
3703                         dev_err(&adapter->pdev->dev,
3704                                 "Detected Tx Unit Hang\n"
3705                                 "  Tx Queue             <%d>\n"
3706                                 "  TDH                  <%x>\n"
3707                                 "  TDT                  <%x>\n"
3708                                 "  next_to_use          <%x>\n"
3709                                 "  next_to_clean        <%x>\n"
3710                                 "buffer_info[next_to_clean]\n"
3711                                 "  time_stamp           <%lx>\n"
3712                                 "  next_to_watch        <%x>\n"
3713                                 "  jiffies              <%lx>\n"
3714                                 "  desc.status          <%x>\n",
3715                                 tx_ring->queue_index,
3716                                 readl(adapter->hw.hw_addr + tx_ring->head),
3717                                 readl(adapter->hw.hw_addr + tx_ring->tail),
3718                                 tx_ring->next_to_use,
3719                                 tx_ring->next_to_clean,
3720                                 tx_ring->buffer_info[i].time_stamp,
3721                                 eop,
3722                                 jiffies,
3723                                 eop_desc->wb.status);
3724                         netif_stop_subqueue(netdev, tx_ring->queue_index);
3725                 }
3726         }
3727         tx_ring->total_bytes += total_bytes;
3728         tx_ring->total_packets += total_packets;
3729         tx_ring->tx_stats.bytes += total_bytes;
3730         tx_ring->tx_stats.packets += total_packets;
3731         adapter->net_stats.tx_bytes += total_bytes;
3732         adapter->net_stats.tx_packets += total_packets;
3733         return (count < tx_ring->count);
3734 }
3735
3736 /**
3737  * igb_receive_skb - helper function to handle rx indications
3738  * @ring: pointer to receive ring receving this packet
3739  * @status: descriptor status field as written by hardware
3740  * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3741  * @skb: pointer to sk_buff to be indicated to stack
3742  **/
3743 static void igb_receive_skb(struct igb_ring *ring, u8 status,
3744                             union e1000_adv_rx_desc * rx_desc,
3745                             struct sk_buff *skb)
3746 {
3747         struct igb_adapter * adapter = ring->adapter;
3748         bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
3749
3750         skb_record_rx_queue(skb, ring->queue_index);
3751         if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
3752                 if (vlan_extracted)
3753                         vlan_gro_receive(&ring->napi, adapter->vlgrp,
3754                                          le16_to_cpu(rx_desc->wb.upper.vlan),
3755                                          skb);
3756                 else
3757                         napi_gro_receive(&ring->napi, skb);
3758         } else {
3759                 if (vlan_extracted)
3760                         vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3761                                           le16_to_cpu(rx_desc->wb.upper.vlan));
3762                 else
3763                         netif_receive_skb(skb);
3764         }
3765 }
3766
3767
3768 static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3769                                        u32 status_err, struct sk_buff *skb)
3770 {
3771         skb->ip_summed = CHECKSUM_NONE;
3772
3773         /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3774         if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3775                 return;
3776         /* TCP/UDP checksum error bit is set */
3777         if (status_err &
3778             (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3779                 /* let the stack verify checksum errors */
3780                 adapter->hw_csum_err++;
3781                 return;
3782         }
3783         /* It must be a TCP or UDP packet with a valid checksum */
3784         if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3785                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3786
3787         adapter->hw_csum_good++;
3788 }
3789
3790 static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3791                                  int *work_done, int budget)
3792 {
3793         struct igb_adapter *adapter = rx_ring->adapter;
3794         struct net_device *netdev = adapter->netdev;
3795         struct pci_dev *pdev = adapter->pdev;
3796         union e1000_adv_rx_desc *rx_desc , *next_rxd;
3797         struct igb_buffer *buffer_info , *next_buffer;
3798         struct sk_buff *skb;
3799         unsigned int i;
3800         u32 length, hlen, staterr;
3801         bool cleaned = false;
3802         int cleaned_count = 0;
3803         unsigned int total_bytes = 0, total_packets = 0;
3804
3805         i = rx_ring->next_to_clean;
3806         rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3807         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3808
3809         while (staterr & E1000_RXD_STAT_DD) {
3810                 if (*work_done >= budget)
3811                         break;
3812                 (*work_done)++;
3813                 buffer_info = &rx_ring->buffer_info[i];
3814
3815                 /* HW will not DMA in data larger than the given buffer, even
3816                  * if it parses the (NFS, of course) header to be larger.  In
3817                  * that case, it fills the header buffer and spills the rest
3818                  * into the page.
3819                  */
3820                 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
3821                   E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
3822                 if (hlen > adapter->rx_ps_hdr_size)
3823                         hlen = adapter->rx_ps_hdr_size;
3824
3825                 length = le16_to_cpu(rx_desc->wb.upper.length);
3826                 cleaned = true;
3827                 cleaned_count++;
3828
3829                 skb = buffer_info->skb;
3830                 prefetch(skb->data - NET_IP_ALIGN);
3831                 buffer_info->skb = NULL;
3832                 if (!adapter->rx_ps_hdr_size) {
3833                         pci_unmap_single(pdev, buffer_info->dma,
3834                                          adapter->rx_buffer_len +
3835                                            NET_IP_ALIGN,
3836                                          PCI_DMA_FROMDEVICE);
3837                         skb_put(skb, length);
3838                         goto send_up;
3839                 }
3840
3841                 if (!skb_shinfo(skb)->nr_frags) {
3842                         pci_unmap_single(pdev, buffer_info->dma,
3843                                          adapter->rx_ps_hdr_size +
3844                                            NET_IP_ALIGN,
3845                                          PCI_DMA_FROMDEVICE);
3846                         skb_put(skb, hlen);
3847                 }
3848
3849                 if (length) {
3850                         pci_unmap_page(pdev, buffer_info->page_dma,
3851                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
3852                         buffer_info->page_dma = 0;
3853
3854                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
3855                                                 buffer_info->page,
3856                                                 buffer_info->page_offset,
3857                                                 length);
3858
3859                         if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
3860                             (page_count(buffer_info->page) != 1))
3861                                 buffer_info->page = NULL;
3862                         else
3863                                 get_page(buffer_info->page);
3864
3865                         skb->len += length;
3866                         skb->data_len += length;
3867
3868                         skb->truesize += length;
3869                 }
3870 send_up:
3871                 i++;
3872                 if (i == rx_ring->count)
3873                         i = 0;
3874                 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3875                 prefetch(next_rxd);
3876                 next_buffer = &rx_ring->buffer_info[i];
3877
3878                 if (!(staterr & E1000_RXD_STAT_EOP)) {
3879                         buffer_info->skb = next_buffer->skb;
3880                         buffer_info->dma = next_buffer->dma;
3881                         next_buffer->skb = skb;
3882                         next_buffer->dma = 0;
3883                         goto next_desc;
3884                 }
3885
3886                 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3887                         dev_kfree_skb_irq(skb);
3888                         goto next_desc;
3889                 }
3890
3891                 total_bytes += skb->len;
3892                 total_packets++;
3893
3894                 igb_rx_checksum_adv(adapter, staterr, skb);
3895
3896                 skb->protocol = eth_type_trans(skb, netdev);
3897
3898                 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
3899
3900 next_desc:
3901                 rx_desc->wb.upper.status_error = 0;
3902
3903                 /* return some buffers to hardware, one at a time is too slow */
3904                 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3905                         igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
3906                         cleaned_count = 0;
3907                 }
3908
3909                 /* use prefetched values */
3910                 rx_desc = next_rxd;
3911                 buffer_info = next_buffer;
3912
3913                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3914         }
3915
3916         rx_ring->next_to_clean = i;
3917         cleaned_count = IGB_DESC_UNUSED(rx_ring);
3918
3919         if (cleaned_count)
3920                 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
3921
3922         rx_ring->total_packets += total_packets;
3923         rx_ring->total_bytes += total_bytes;
3924         rx_ring->rx_stats.packets += total_packets;
3925         rx_ring->rx_stats.bytes += total_bytes;
3926         adapter->net_stats.rx_bytes += total_bytes;
3927         adapter->net_stats.rx_packets += total_packets;
3928         return cleaned;
3929 }
3930
3931
3932 /**
3933  * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3934  * @adapter: address of board private structure
3935  **/
3936 static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
3937                                      int cleaned_count)
3938 {
3939         struct igb_adapter *adapter = rx_ring->adapter;
3940         struct net_device *netdev = adapter->netdev;
3941         struct pci_dev *pdev = adapter->pdev;
3942         union e1000_adv_rx_desc *rx_desc;
3943         struct igb_buffer *buffer_info;
3944         struct sk_buff *skb;
3945         unsigned int i;
3946
3947         i = rx_ring->next_to_use;
3948         buffer_info = &rx_ring->buffer_info[i];
3949
3950         while (cleaned_count--) {
3951                 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3952
3953                 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
3954                         if (!buffer_info->page) {
3955                                 buffer_info->page = alloc_page(GFP_ATOMIC);
3956                                 if (!buffer_info->page) {
3957                                         adapter->alloc_rx_buff_failed++;
3958                                         goto no_buffers;
3959                                 }
3960                                 buffer_info->page_offset = 0;
3961                         } else {
3962                                 buffer_info->page_offset ^= PAGE_SIZE / 2;
3963                         }
3964                         buffer_info->page_dma =
3965                                 pci_map_page(pdev,
3966                                              buffer_info->page,
3967                                              buffer_info->page_offset,
3968                                              PAGE_SIZE / 2,
3969                                              PCI_DMA_FROMDEVICE);
3970                 }
3971
3972                 if (!buffer_info->skb) {
3973                         int bufsz;
3974
3975                         if (adapter->rx_ps_hdr_size)
3976                                 bufsz = adapter->rx_ps_hdr_size;
3977                         else
3978                                 bufsz = adapter->rx_buffer_len;
3979                         bufsz += NET_IP_ALIGN;
3980                         skb = netdev_alloc_skb(netdev, bufsz);
3981
3982                         if (!skb) {
3983                                 adapter->alloc_rx_buff_failed++;
3984                                 goto no_buffers;
3985                         }
3986
3987                         /* Make buffer alignment 2 beyond a 16 byte boundary
3988                          * this will result in a 16 byte aligned IP header after
3989                          * the 14 byte MAC header is removed
3990                          */
3991                         skb_reserve(skb, NET_IP_ALIGN);
3992
3993                         buffer_info->skb = skb;
3994                         buffer_info->dma = pci_map_single(pdev, skb->data,
3995                                                           bufsz,
3996                                                           PCI_DMA_FROMDEVICE);
3997
3998                 }
3999                 /* Refresh the desc even if buffer_addrs didn't change because
4000                  * each write-back erases this info. */
4001                 if (adapter->rx_ps_hdr_size) {
4002                         rx_desc->read.pkt_addr =
4003                              cpu_to_le64(buffer_info->page_dma);
4004                         rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4005                 } else {
4006                         rx_desc->read.pkt_addr =
4007                              cpu_to_le64(buffer_info->dma);
4008                         rx_desc->read.hdr_addr = 0;
4009                 }
4010
4011                 i++;
4012                 if (i == rx_ring->count)
4013                         i = 0;
4014                 buffer_info = &rx_ring->buffer_info[i];
4015         }
4016
4017 no_buffers:
4018         if (rx_ring->next_to_use != i) {
4019                 rx_ring->next_to_use = i;
4020                 if (i == 0)
4021                         i = (rx_ring->count - 1);
4022                 else
4023                         i--;
4024
4025                 /* Force memory writes to complete before letting h/w
4026                  * know there are new descriptors to fetch.  (Only
4027                  * applicable for weak-ordered memory model archs,
4028                  * such as IA-64). */
4029                 wmb();
4030                 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4031         }
4032 }
4033
4034 /**
4035  * igb_mii_ioctl -
4036  * @netdev:
4037  * @ifreq:
4038  * @cmd:
4039  **/
4040 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4041 {
4042         struct igb_adapter *adapter = netdev_priv(netdev);
4043         struct mii_ioctl_data *data = if_mii(ifr);
4044
4045         if (adapter->hw.phy.media_type != e1000_media_type_copper)
4046                 return -EOPNOTSUPP;
4047
4048         switch (cmd) {
4049         case SIOCGMIIPHY:
4050                 data->phy_id = adapter->hw.phy.addr;
4051                 break;
4052         case SIOCGMIIREG:
4053                 if (!capable(CAP_NET_ADMIN))
4054                         return -EPERM;
4055                 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4056                                      &data->val_out))
4057                         return -EIO;
4058                 break;
4059         case SIOCSMIIREG:
4060         default:
4061                 return -EOPNOTSUPP;
4062         }
4063         return 0;
4064 }
4065
4066 /**
4067  * igb_ioctl -
4068  * @netdev:
4069  * @ifreq:
4070  * @cmd:
4071  **/
4072 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4073 {
4074         switch (cmd) {
4075         case SIOCGMIIPHY:
4076         case SIOCGMIIREG:
4077         case SIOCSMIIREG:
4078                 return igb_mii_ioctl(netdev, ifr, cmd);
4079         default:
4080                 return -EOPNOTSUPP;
4081         }
4082 }
4083
4084 static void igb_vlan_rx_register(struct net_device *netdev,
4085                                  struct vlan_group *grp)
4086 {
4087         struct igb_adapter *adapter = netdev_priv(netdev);
4088         struct e1000_hw *hw = &adapter->hw;
4089         u32 ctrl, rctl;
4090
4091         igb_irq_disable(adapter);
4092         adapter->vlgrp = grp;
4093
4094         if (grp) {
4095                 /* enable VLAN tag insert/strip */
4096                 ctrl = rd32(E1000_CTRL);
4097                 ctrl |= E1000_CTRL_VME;
4098                 wr32(E1000_CTRL, ctrl);
4099
4100                 /* enable VLAN receive filtering */
4101                 rctl = rd32(E1000_RCTL);
4102                 rctl &= ~E1000_RCTL_CFIEN;
4103                 wr32(E1000_RCTL, rctl);
4104                 igb_update_mng_vlan(adapter);
4105                 wr32(E1000_RLPML,
4106                                 adapter->max_frame_size + VLAN_TAG_SIZE);
4107         } else {
4108                 /* disable VLAN tag insert/strip */
4109                 ctrl = rd32(E1000_CTRL);
4110                 ctrl &= ~E1000_CTRL_VME;
4111                 wr32(E1000_CTRL, ctrl);
4112
4113                 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4114                         igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4115                         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4116                 }
4117                 wr32(E1000_RLPML,
4118                                 adapter->max_frame_size);
4119         }
4120
4121         if (!test_bit(__IGB_DOWN, &adapter->state))
4122                 igb_irq_enable(adapter);
4123 }
4124
4125 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4126 {
4127         struct igb_adapter *adapter = netdev_priv(netdev);
4128         struct e1000_hw *hw = &adapter->hw;
4129         u32 vfta, index;
4130
4131         if ((adapter->hw.mng_cookie.status &
4132              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4133             (vid == adapter->mng_vlan_id))
4134                 return;
4135         /* add VID to filter table */
4136         index = (vid >> 5) & 0x7F;
4137         vfta = array_rd32(E1000_VFTA, index);
4138         vfta |= (1 << (vid & 0x1F));
4139         igb_write_vfta(&adapter->hw, index, vfta);
4140 }
4141
4142 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4143 {
4144         struct igb_adapter *adapter = netdev_priv(netdev);
4145         struct e1000_hw *hw = &adapter->hw;
4146         u32 vfta, index;
4147
4148         igb_irq_disable(adapter);
4149         vlan_group_set_device(adapter->vlgrp, vid, NULL);
4150
4151         if (!test_bit(__IGB_DOWN, &adapter->state))
4152                 igb_irq_enable(adapter);
4153
4154         if ((adapter->hw.mng_cookie.status &
4155              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4156             (vid == adapter->mng_vlan_id)) {
4157                 /* release control to f/w */
4158                 igb_release_hw_control(adapter);
4159                 return;
4160         }
4161
4162         /* remove VID from filter table */
4163         index = (vid >> 5) & 0x7F;
4164         vfta = array_rd32(E1000_VFTA, index);
4165         vfta &= ~(1 << (vid & 0x1F));
4166         igb_write_vfta(&adapter->hw, index, vfta);
4167 }
4168
4169 static void igb_restore_vlan(struct igb_adapter *adapter)
4170 {
4171         igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4172
4173         if (adapter->vlgrp) {
4174                 u16 vid;
4175                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4176                         if (!vlan_group_get_device(adapter->vlgrp, vid))
4177                                 continue;
4178                         igb_vlan_rx_add_vid(adapter->netdev, vid);
4179                 }
4180         }
4181 }
4182
4183 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
4184 {
4185         struct e1000_mac_info *mac = &adapter->hw.mac;
4186
4187         mac->autoneg = 0;
4188
4189         /* Fiber NICs only allow 1000 gbps Full duplex */
4190         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
4191                 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4192                 dev_err(&adapter->pdev->dev,
4193                         "Unsupported Speed/Duplex configuration\n");
4194                 return -EINVAL;
4195         }
4196
4197         switch (spddplx) {
4198         case SPEED_10 + DUPLEX_HALF:
4199                 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4200                 break;
4201         case SPEED_10 + DUPLEX_FULL:
4202                 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4203                 break;
4204         case SPEED_100 + DUPLEX_HALF:
4205                 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4206                 break;
4207         case SPEED_100 + DUPLEX_FULL:
4208                 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4209                 break;
4210         case SPEED_1000 + DUPLEX_FULL:
4211                 mac->autoneg = 1;
4212                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
4213                 break;
4214         case SPEED_1000 + DUPLEX_HALF: /* not supported */
4215         default:
4216                 dev_err(&adapter->pdev->dev,
4217                         "Unsupported Speed/Duplex configuration\n");
4218                 return -EINVAL;
4219         }
4220         return 0;
4221 }
4222
4223
4224 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
4225 {
4226         struct net_device *netdev = pci_get_drvdata(pdev);
4227         struct igb_adapter *adapter = netdev_priv(netdev);
4228         struct e1000_hw *hw = &adapter->hw;
4229         u32 ctrl, rctl, status;
4230         u32 wufc = adapter->wol;
4231 #ifdef CONFIG_PM
4232         int retval = 0;
4233 #endif
4234
4235         netif_device_detach(netdev);
4236
4237         if (netif_running(netdev))
4238                 igb_close(netdev);
4239
4240         igb_reset_interrupt_capability(adapter);
4241
4242         igb_free_queues(adapter);
4243
4244 #ifdef CONFIG_PM
4245         retval = pci_save_state(pdev);
4246         if (retval)
4247                 return retval;
4248 #endif
4249
4250         status = rd32(E1000_STATUS);
4251         if (status & E1000_STATUS_LU)
4252                 wufc &= ~E1000_WUFC_LNKC;
4253
4254         if (wufc) {
4255                 igb_setup_rctl(adapter);
4256                 igb_set_multi(netdev);
4257
4258                 /* turn on all-multi mode if wake on multicast is enabled */
4259                 if (wufc & E1000_WUFC_MC) {
4260                         rctl = rd32(E1000_RCTL);
4261                         rctl |= E1000_RCTL_MPE;
4262                         wr32(E1000_RCTL, rctl);
4263                 }
4264
4265                 ctrl = rd32(E1000_CTRL);
4266                 /* advertise wake from D3Cold */
4267                 #define E1000_CTRL_ADVD3WUC 0x00100000
4268                 /* phy power management enable */
4269                 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4270                 ctrl |= E1000_CTRL_ADVD3WUC;
4271                 wr32(E1000_CTRL, ctrl);
4272
4273                 /* Allow time for pending master requests to run */
4274                 igb_disable_pcie_master(&adapter->hw);
4275
4276                 wr32(E1000_WUC, E1000_WUC_PME_EN);
4277                 wr32(E1000_WUFC, wufc);
4278         } else {
4279                 wr32(E1000_WUC, 0);
4280                 wr32(E1000_WUFC, 0);
4281         }
4282
4283         /* make sure adapter isn't asleep if manageability/wol is enabled */
4284         if (wufc || adapter->en_mng_pt) {
4285                 pci_enable_wake(pdev, PCI_D3hot, 1);
4286                 pci_enable_wake(pdev, PCI_D3cold, 1);
4287         } else {
4288                 igb_shutdown_fiber_serdes_link_82575(hw);
4289                 pci_enable_wake(pdev, PCI_D3hot, 0);
4290                 pci_enable_wake(pdev, PCI_D3cold, 0);
4291         }
4292
4293         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
4294          * would have already happened in close and is redundant. */
4295         igb_release_hw_control(adapter);
4296
4297         pci_disable_device(pdev);
4298
4299         pci_set_power_state(pdev, pci_choose_state(pdev, state));
4300
4301         return 0;
4302 }
4303
4304 #ifdef CONFIG_PM
4305 static int igb_resume(struct pci_dev *pdev)
4306 {
4307         struct net_device *netdev = pci_get_drvdata(pdev);
4308         struct igb_adapter *adapter = netdev_priv(netdev);
4309         struct e1000_hw *hw = &adapter->hw;
4310         u32 err;
4311
4312         pci_set_power_state(pdev, PCI_D0);
4313         pci_restore_state(pdev);
4314
4315         if (adapter->need_ioport)
4316                 err = pci_enable_device(pdev);
4317         else
4318                 err = pci_enable_device_mem(pdev);
4319         if (err) {
4320                 dev_err(&pdev->dev,
4321                         "igb: Cannot enable PCI device from suspend\n");
4322                 return err;
4323         }
4324         pci_set_master(pdev);
4325
4326         pci_enable_wake(pdev, PCI_D3hot, 0);
4327         pci_enable_wake(pdev, PCI_D3cold, 0);
4328
4329         igb_set_interrupt_capability(adapter);
4330
4331         if (igb_alloc_queues(adapter)) {
4332                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4333                 return -ENOMEM;
4334         }
4335
4336         /* e1000_power_up_phy(adapter); */
4337
4338         igb_reset(adapter);
4339         wr32(E1000_WUS, ~0);
4340
4341         if (netif_running(netdev)) {
4342                 err = igb_open(netdev);
4343                 if (err)
4344                         return err;
4345         }
4346
4347         netif_device_attach(netdev);
4348
4349         /* let the f/w know that the h/w is now under the control of the
4350          * driver. */
4351         igb_get_hw_control(adapter);
4352
4353         return 0;
4354 }
4355 #endif
4356
4357 static void igb_shutdown(struct pci_dev *pdev)
4358 {
4359         igb_suspend(pdev, PMSG_SUSPEND);
4360 }
4361
4362 #ifdef CONFIG_NET_POLL_CONTROLLER
4363 /*
4364  * Polling 'interrupt' - used by things like netconsole to send skbs
4365  * without having to re-enable interrupts. It's not called while
4366  * the interrupt routine is executing.
4367  */
4368 static void igb_netpoll(struct net_device *netdev)
4369 {
4370         struct igb_adapter *adapter = netdev_priv(netdev);
4371         int i;
4372         int work_done = 0;
4373
4374         igb_irq_disable(adapter);
4375         adapter->flags |= IGB_FLAG_IN_NETPOLL;
4376
4377         for (i = 0; i < adapter->num_tx_queues; i++)
4378                 igb_clean_tx_irq(&adapter->tx_ring[i]);
4379
4380         for (i = 0; i < adapter->num_rx_queues; i++)
4381                 igb_clean_rx_irq_adv(&adapter->rx_ring[i],
4382                                      &work_done,
4383                                      adapter->rx_ring[i].napi.weight);
4384
4385         adapter->flags &= ~IGB_FLAG_IN_NETPOLL;
4386         igb_irq_enable(adapter);
4387 }
4388 #endif /* CONFIG_NET_POLL_CONTROLLER */
4389
4390 /**
4391  * igb_io_error_detected - called when PCI error is detected
4392  * @pdev: Pointer to PCI device
4393  * @state: The current pci connection state
4394  *
4395  * This function is called after a PCI bus error affecting
4396  * this device has been detected.
4397  */
4398 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4399                                               pci_channel_state_t state)
4400 {
4401         struct net_device *netdev = pci_get_drvdata(pdev);
4402         struct igb_adapter *adapter = netdev_priv(netdev);
4403
4404         netif_device_detach(netdev);
4405
4406         if (netif_running(netdev))
4407                 igb_down(adapter);
4408         pci_disable_device(pdev);
4409
4410         /* Request a slot slot reset. */
4411         return PCI_ERS_RESULT_NEED_RESET;
4412 }
4413
4414 /**
4415  * igb_io_slot_reset - called after the pci bus has been reset.
4416  * @pdev: Pointer to PCI device
4417  *
4418  * Restart the card from scratch, as if from a cold-boot. Implementation
4419  * resembles the first-half of the igb_resume routine.
4420  */
4421 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4422 {
4423         struct net_device *netdev = pci_get_drvdata(pdev);
4424         struct igb_adapter *adapter = netdev_priv(netdev);
4425         struct e1000_hw *hw = &adapter->hw;
4426         pci_ers_result_t result;
4427         int err;
4428
4429         if (adapter->need_ioport)
4430                 err = pci_enable_device(pdev);
4431         else
4432                 err = pci_enable_device_mem(pdev);
4433
4434         if (err) {
4435                 dev_err(&pdev->dev,
4436                         "Cannot re-enable PCI device after reset.\n");
4437                 result = PCI_ERS_RESULT_DISCONNECT;
4438         } else {
4439                 pci_set_master(pdev);
4440                 pci_restore_state(pdev);
4441
4442                 pci_enable_wake(pdev, PCI_D3hot, 0);
4443                 pci_enable_wake(pdev, PCI_D3cold, 0);
4444
4445                 igb_reset(adapter);
4446                 wr32(E1000_WUS, ~0);
4447                 result = PCI_ERS_RESULT_RECOVERED;
4448         }
4449
4450         err = pci_cleanup_aer_uncorrect_error_status(pdev);
4451         if (err) {
4452                 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
4453                         "failed 0x%0x\n", err);
4454                 /* non-fatal, continue */
4455         }
4456
4457         return result;
4458 }
4459
4460 /**
4461  * igb_io_resume - called when traffic can start flowing again.
4462  * @pdev: Pointer to PCI device
4463  *
4464  * This callback is called when the error recovery driver tells us that
4465  * its OK to resume normal operation. Implementation resembles the
4466  * second-half of the igb_resume routine.
4467  */
4468 static void igb_io_resume(struct pci_dev *pdev)
4469 {
4470         struct net_device *netdev = pci_get_drvdata(pdev);
4471         struct igb_adapter *adapter = netdev_priv(netdev);
4472
4473         if (netif_running(netdev)) {
4474                 if (igb_up(adapter)) {
4475                         dev_err(&pdev->dev, "igb_up failed after reset\n");
4476                         return;
4477                 }
4478         }
4479
4480         netif_device_attach(netdev);
4481
4482         /* let the f/w know that the h/w is now under the control of the
4483          * driver. */
4484         igb_get_hw_control(adapter);
4485 }
4486
4487 /* igb_main.c */