drivers/net/igb/igb_ethtool.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 /* ethtool support for igb */
  29
  30 #include <linux/vmalloc.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/pci.h>
  33 #include <linux/delay.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/if_ether.h>
  36 #include <linux/ethtool.h>
  37
  38 #include "igb.h"
  39
  40 struct igb_stats {
  41         char stat_string[ETH_GSTRING_LEN];
  42         int sizeof_stat;
  43         int stat_offset;
  44 };
  45
  46 #define IGB_STAT(m) FIELD_SIZEOF(struct igb_adapter, m), \
  47                       offsetof(struct igb_adapter, m)
  48 static const struct igb_stats igb_gstrings_stats[] = {
  49         { "rx_packets", IGB_STAT(stats.gprc) },
  50         { "tx_packets", IGB_STAT(stats.gptc) },
  51         { "rx_bytes", IGB_STAT(stats.gorc) },
  52         { "tx_bytes", IGB_STAT(stats.gotc) },
  53         { "rx_broadcast", IGB_STAT(stats.bprc) },
  54         { "tx_broadcast", IGB_STAT(stats.bptc) },
  55         { "rx_multicast", IGB_STAT(stats.mprc) },
  56         { "tx_multicast", IGB_STAT(stats.mptc) },
  57         { "rx_errors", IGB_STAT(net_stats.rx_errors) },
  58         { "tx_errors", IGB_STAT(net_stats.tx_errors) },
  59         { "tx_dropped", IGB_STAT(net_stats.tx_dropped) },
  60         { "multicast", IGB_STAT(stats.mprc) },
  61         { "collisions", IGB_STAT(stats.colc) },
  62         { "rx_length_errors", IGB_STAT(net_stats.rx_length_errors) },
  63         { "rx_over_errors", IGB_STAT(net_stats.rx_over_errors) },
  64         { "rx_crc_errors", IGB_STAT(stats.crcerrs) },
  65         { "rx_frame_errors", IGB_STAT(net_stats.rx_frame_errors) },
  66         { "rx_no_buffer_count", IGB_STAT(stats.rnbc) },
  67         { "rx_missed_errors", IGB_STAT(stats.mpc) },
  68         { "tx_aborted_errors", IGB_STAT(stats.ecol) },
  69         { "tx_carrier_errors", IGB_STAT(stats.tncrs) },
  70         { "tx_fifo_errors", IGB_STAT(net_stats.tx_fifo_errors) },
  71         { "tx_heartbeat_errors", IGB_STAT(net_stats.tx_heartbeat_errors) },
  72         { "tx_window_errors", IGB_STAT(stats.latecol) },
  73         { "tx_abort_late_coll", IGB_STAT(stats.latecol) },
  74         { "tx_deferred_ok", IGB_STAT(stats.dc) },
  75         { "tx_single_coll_ok", IGB_STAT(stats.scc) },
  76         { "tx_multi_coll_ok", IGB_STAT(stats.mcc) },
  77         { "tx_timeout_count", IGB_STAT(tx_timeout_count) },
  78         { "tx_restart_queue", IGB_STAT(restart_queue) },
  79         { "rx_long_length_errors", IGB_STAT(stats.roc) },
  80         { "rx_short_length_errors", IGB_STAT(stats.ruc) },
  81         { "rx_align_errors", IGB_STAT(stats.algnerrc) },
  82         { "tx_tcp_seg_good", IGB_STAT(stats.tsctc) },
  83         { "tx_tcp_seg_failed", IGB_STAT(stats.tsctfc) },
  84         { "rx_flow_control_xon", IGB_STAT(stats.xonrxc) },
  85         { "rx_flow_control_xoff", IGB_STAT(stats.xoffrxc) },
  86         { "tx_flow_control_xon", IGB_STAT(stats.xontxc) },
  87         { "tx_flow_control_xoff", IGB_STAT(stats.xofftxc) },
  88         { "rx_long_byte_count", IGB_STAT(stats.gorc) },
  89         { "rx_csum_offload_good", IGB_STAT(hw_csum_good) },
  90         { "rx_csum_offload_errors", IGB_STAT(hw_csum_err) },
  91         { "tx_dma_out_of_sync", IGB_STAT(stats.doosync) },
  92         { "alloc_rx_buff_failed", IGB_STAT(alloc_rx_buff_failed) },
  93         { "tx_smbus", IGB_STAT(stats.mgptc) },
  94         { "rx_smbus", IGB_STAT(stats.mgprc) },
  95         { "dropped_smbus", IGB_STAT(stats.mgpdc) },
  96 };
  97
  98 #define IGB_QUEUE_STATS_LEN \
  99         ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues + \
 100          ((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues) * \
 101         (sizeof(struct igb_queue_stats) / sizeof(u64)))
 102 #define IGB_GLOBAL_STATS_LEN    \
 103         sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)
 104 #define IGB_STATS_LEN (IGB_GLOBAL_STATS_LEN + IGB_QUEUE_STATS_LEN)
 105 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
 106         "Register test  (offline)", "Eeprom test    (offline)",
 107         "Interrupt test (offline)", "Loopback test  (offline)",
 108         "Link test   (on/offline)"
 109 };
 110 #define IGB_TEST_LEN sizeof(igb_gstrings_test) / ETH_GSTRING_LEN
 111
 112 static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
 113 {
 114         struct igb_adapter *adapter = netdev_priv(netdev);
 115         struct e1000_hw *hw = &adapter->hw;
 116
 117         if (hw->phy.media_type == e1000_media_type_copper) {
 118
 119                 ecmd->supported = (SUPPORTED_10baseT_Half |
 120                                    SUPPORTED_10baseT_Full |
 121                                    SUPPORTED_100baseT_Half |
 122                                    SUPPORTED_100baseT_Full |
 123                                    SUPPORTED_1000baseT_Full|
 124                                    SUPPORTED_Autoneg |
 125                                    SUPPORTED_TP);
 126                 ecmd->advertising = ADVERTISED_TP;
 127
 128                 if (hw->mac.autoneg == 1) {
 129                         ecmd->advertising |= ADVERTISED_Autoneg;
 130                         /* the e1000 autoneg seems to match ethtool nicely */
 131                         ecmd->advertising |= hw->phy.autoneg_advertised;
 132                 }
 133
 134                 ecmd->port = PORT_TP;
 135                 ecmd->phy_address = hw->phy.addr;
 136         } else {
 137                 ecmd->supported   = (SUPPORTED_1000baseT_Full |
 138                                      SUPPORTED_FIBRE |
 139                                      SUPPORTED_Autoneg);
 140
 141                 ecmd->advertising = (ADVERTISED_1000baseT_Full |
 142                                      ADVERTISED_FIBRE |
 143                                      ADVERTISED_Autoneg);
 144
 145                 ecmd->port = PORT_FIBRE;
 146         }
 147
 148         ecmd->transceiver = XCVR_INTERNAL;
 149
 150         if (rd32(E1000_STATUS) & E1000_STATUS_LU) {
 151
 152                 adapter->hw.mac.ops.get_speed_and_duplex(hw,
 153                                         &adapter->link_speed,
 154                                         &adapter->link_duplex);
 155                 ecmd->speed = adapter->link_speed;
 156
 157                 /* unfortunately FULL_DUPLEX != DUPLEX_FULL
 158                  *          and HALF_DUPLEX != DUPLEX_HALF */
 159
 160                 if (adapter->link_duplex == FULL_DUPLEX)
 161                         ecmd->duplex = DUPLEX_FULL;
 162                 else
 163                         ecmd->duplex = DUPLEX_HALF;
 164         } else {
 165                 ecmd->speed = -1;
 166                 ecmd->duplex = -1;
 167         }
 168
 169         ecmd->autoneg = ((hw->phy.media_type == e1000_media_type_fiber) ||
 170                          hw->mac.autoneg) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
 171         return 0;
 172 }
 173
 174 static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
 175 {
 176         struct igb_adapter *adapter = netdev_priv(netdev);
 177         struct e1000_hw *hw = &adapter->hw;
 178
 179         /* When SoL/IDER sessions are active, autoneg/speed/duplex
 180          * cannot be changed */
 181         if (igb_check_reset_block(hw)) {
 182                 dev_err(&adapter->pdev->dev, "Cannot change link "
 183                         "characteristics when SoL/IDER is active.\n");
 184                 return -EINVAL;
 185         }
 186
 187         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 188                 msleep(1);
 189
 190         if (ecmd->autoneg == AUTONEG_ENABLE) {
 191                 hw->mac.autoneg = 1;
 192                 if (hw->phy.media_type == e1000_media_type_fiber)
 193                         hw->phy.autoneg_advertised = ADVERTISED_1000baseT_Full |
 194                                                      ADVERTISED_FIBRE |
 195                                                      ADVERTISED_Autoneg;
 196                 else
 197                         hw->phy.autoneg_advertised = ecmd->advertising |
 198                                                      ADVERTISED_TP |
 199                                                      ADVERTISED_Autoneg;
 200                 ecmd->advertising = hw->phy.autoneg_advertised;
 201         } else
 202                 if (igb_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
 203                         clear_bit(__IGB_RESETTING, &adapter->state);
 204                         return -EINVAL;
 205                 }
 206
 207         /* reset the link */
 208
 209         if (netif_running(adapter->netdev)) {
 210                 igb_down(adapter);
 211                 igb_up(adapter);
 212         } else
 213                 igb_reset(adapter);
 214
 215         clear_bit(__IGB_RESETTING, &adapter->state);
 216         return 0;
 217 }
 218
 219 static void igb_get_pauseparam(struct net_device *netdev,
 220                                struct ethtool_pauseparam *pause)
 221 {
 222         struct igb_adapter *adapter = netdev_priv(netdev);
 223         struct e1000_hw *hw = &adapter->hw;
 224
 225         pause->autoneg =
 226                 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
 227
 228         if (hw->fc.type == e1000_fc_rx_pause)
 229                 pause->rx_pause = 1;
 230         else if (hw->fc.type == e1000_fc_tx_pause)
 231                 pause->tx_pause = 1;
 232         else if (hw->fc.type == e1000_fc_full) {
 233                 pause->rx_pause = 1;
 234                 pause->tx_pause = 1;
 235         }
 236 }
 237
 238 static int igb_set_pauseparam(struct net_device *netdev,
 239                               struct ethtool_pauseparam *pause)
 240 {
 241         struct igb_adapter *adapter = netdev_priv(netdev);
 242         struct e1000_hw *hw = &adapter->hw;
 243         int retval = 0;
 244
 245         adapter->fc_autoneg = pause->autoneg;
 246
 247         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 248                 msleep(1);
 249
 250         if (pause->rx_pause && pause->tx_pause)
 251                 hw->fc.type = e1000_fc_full;
 252         else if (pause->rx_pause && !pause->tx_pause)
 253                 hw->fc.type = e1000_fc_rx_pause;
 254         else if (!pause->rx_pause && pause->tx_pause)
 255                 hw->fc.type = e1000_fc_tx_pause;
 256         else if (!pause->rx_pause && !pause->tx_pause)
 257                 hw->fc.type = e1000_fc_none;
 258
 259         hw->fc.original_type = hw->fc.type;
 260
 261         if (adapter->fc_autoneg == AUTONEG_ENABLE) {
 262                 if (netif_running(adapter->netdev)) {
 263                         igb_down(adapter);
 264                         igb_up(adapter);
 265                 } else
 266                         igb_reset(adapter);
 267         } else
 268                 retval = ((hw->phy.media_type == e1000_media_type_fiber) ?
 269                           igb_setup_link(hw) : igb_force_mac_fc(hw));
 270
 271         clear_bit(__IGB_RESETTING, &adapter->state);
 272         return retval;
 273 }
 274
 275 static u32 igb_get_rx_csum(struct net_device *netdev)
 276 {
 277         struct igb_adapter *adapter = netdev_priv(netdev);
 278         return adapter->rx_csum;
 279 }
 280
 281 static int igb_set_rx_csum(struct net_device *netdev, u32 data)
 282 {
 283         struct igb_adapter *adapter = netdev_priv(netdev);
 284         adapter->rx_csum = data;
 285
 286         return 0;
 287 }
 288
 289 static u32 igb_get_tx_csum(struct net_device *netdev)
 290 {
 291         return (netdev->features & NETIF_F_IP_CSUM) != 0;
 292 }
 293
 294 static int igb_set_tx_csum(struct net_device *netdev, u32 data)
 295 {
 296         if (data)
 297                 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
 298         else
 299                 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
 300
 301         return 0;
 302 }
 303
 304 static int igb_set_tso(struct net_device *netdev, u32 data)
 305 {
 306         struct igb_adapter *adapter = netdev_priv(netdev);
 307
 308         if (data) {
 309                 netdev->features |= NETIF_F_TSO;
 310                 netdev->features |= NETIF_F_TSO6;
 311         } else {
 312                 netdev->features &= ~NETIF_F_TSO;
 313                 netdev->features &= ~NETIF_F_TSO6;
 314         }
 315
 316         dev_info(&adapter->pdev->dev, "TSO is %s\n",
 317                  data ? "Enabled" : "Disabled");
 318         return 0;
 319 }
 320
 321 static u32 igb_get_msglevel(struct net_device *netdev)
 322 {
 323         struct igb_adapter *adapter = netdev_priv(netdev);
 324         return adapter->msg_enable;
 325 }
 326
 327 static void igb_set_msglevel(struct net_device *netdev, u32 data)
 328 {
 329         struct igb_adapter *adapter = netdev_priv(netdev);
 330         adapter->msg_enable = data;
 331 }
 332
 333 static int igb_get_regs_len(struct net_device *netdev)
 334 {
 335 #define IGB_REGS_LEN 551
 336         return IGB_REGS_LEN * sizeof(u32);
 337 }
 338
 339 static void igb_get_regs(struct net_device *netdev,
 340                          struct ethtool_regs *regs, void *p)
 341 {
 342         struct igb_adapter *adapter = netdev_priv(netdev);
 343         struct e1000_hw *hw = &adapter->hw;
 344         u32 *regs_buff = p;
 345         u8 i;
 346
 347         memset(p, 0, IGB_REGS_LEN * sizeof(u32));
 348
 349         regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
 350
 351         /* General Registers */
 352         regs_buff[0] = rd32(E1000_CTRL);
 353         regs_buff[1] = rd32(E1000_STATUS);
 354         regs_buff[2] = rd32(E1000_CTRL_EXT);
 355         regs_buff[3] = rd32(E1000_MDIC);
 356         regs_buff[4] = rd32(E1000_SCTL);
 357         regs_buff[5] = rd32(E1000_CONNSW);
 358         regs_buff[6] = rd32(E1000_VET);
 359         regs_buff[7] = rd32(E1000_LEDCTL);
 360         regs_buff[8] = rd32(E1000_PBA);
 361         regs_buff[9] = rd32(E1000_PBS);
 362         regs_buff[10] = rd32(E1000_FRTIMER);
 363         regs_buff[11] = rd32(E1000_TCPTIMER);
 364
 365         /* NVM Register */
 366         regs_buff[12] = rd32(E1000_EECD);
 367
 368         /* Interrupt */
 369         /* Reading EICS for EICR because they read the
 370          * same but EICS does not clear on read */
 371         regs_buff[13] = rd32(E1000_EICS);
 372         regs_buff[14] = rd32(E1000_EICS);
 373         regs_buff[15] = rd32(E1000_EIMS);
 374         regs_buff[16] = rd32(E1000_EIMC);
 375         regs_buff[17] = rd32(E1000_EIAC);
 376         regs_buff[18] = rd32(E1000_EIAM);
 377         /* Reading ICS for ICR because they read the
 378          * same but ICS does not clear on read */
 379         regs_buff[19] = rd32(E1000_ICS);
 380         regs_buff[20] = rd32(E1000_ICS);
 381         regs_buff[21] = rd32(E1000_IMS);
 382         regs_buff[22] = rd32(E1000_IMC);
 383         regs_buff[23] = rd32(E1000_IAC);
 384         regs_buff[24] = rd32(E1000_IAM);
 385         regs_buff[25] = rd32(E1000_IMIRVP);
 386
 387         /* Flow Control */
 388         regs_buff[26] = rd32(E1000_FCAL);
 389         regs_buff[27] = rd32(E1000_FCAH);
 390         regs_buff[28] = rd32(E1000_FCTTV);
 391         regs_buff[29] = rd32(E1000_FCRTL);
 392         regs_buff[30] = rd32(E1000_FCRTH);
 393         regs_buff[31] = rd32(E1000_FCRTV);
 394
 395         /* Receive */
 396         regs_buff[32] = rd32(E1000_RCTL);
 397         regs_buff[33] = rd32(E1000_RXCSUM);
 398         regs_buff[34] = rd32(E1000_RLPML);
 399         regs_buff[35] = rd32(E1000_RFCTL);
 400         regs_buff[36] = rd32(E1000_MRQC);
 401         regs_buff[37] = rd32(E1000_VT_CTL);
 402
 403         /* Transmit */
 404         regs_buff[38] = rd32(E1000_TCTL);
 405         regs_buff[39] = rd32(E1000_TCTL_EXT);
 406         regs_buff[40] = rd32(E1000_TIPG);
 407         regs_buff[41] = rd32(E1000_DTXCTL);
 408
 409         /* Wake Up */
 410         regs_buff[42] = rd32(E1000_WUC);
 411         regs_buff[43] = rd32(E1000_WUFC);
 412         regs_buff[44] = rd32(E1000_WUS);
 413         regs_buff[45] = rd32(E1000_IPAV);
 414         regs_buff[46] = rd32(E1000_WUPL);
 415
 416         /* MAC */
 417         regs_buff[47] = rd32(E1000_PCS_CFG0);
 418         regs_buff[48] = rd32(E1000_PCS_LCTL);
 419         regs_buff[49] = rd32(E1000_PCS_LSTAT);
 420         regs_buff[50] = rd32(E1000_PCS_ANADV);
 421         regs_buff[51] = rd32(E1000_PCS_LPAB);
 422         regs_buff[52] = rd32(E1000_PCS_NPTX);
 423         regs_buff[53] = rd32(E1000_PCS_LPABNP);
 424
 425         /* Statistics */
 426         regs_buff[54] = adapter->stats.crcerrs;
 427         regs_buff[55] = adapter->stats.algnerrc;
 428         regs_buff[56] = adapter->stats.symerrs;
 429         regs_buff[57] = adapter->stats.rxerrc;
 430         regs_buff[58] = adapter->stats.mpc;
 431         regs_buff[59] = adapter->stats.scc;
 432         regs_buff[60] = adapter->stats.ecol;
 433         regs_buff[61] = adapter->stats.mcc;
 434         regs_buff[62] = adapter->stats.latecol;
 435         regs_buff[63] = adapter->stats.colc;
 436         regs_buff[64] = adapter->stats.dc;
 437         regs_buff[65] = adapter->stats.tncrs;
 438         regs_buff[66] = adapter->stats.sec;
 439         regs_buff[67] = adapter->stats.htdpmc;
 440         regs_buff[68] = adapter->stats.rlec;
 441         regs_buff[69] = adapter->stats.xonrxc;
 442         regs_buff[70] = adapter->stats.xontxc;
 443         regs_buff[71] = adapter->stats.xoffrxc;
 444         regs_buff[72] = adapter->stats.xofftxc;
 445         regs_buff[73] = adapter->stats.fcruc;
 446         regs_buff[74] = adapter->stats.prc64;
 447         regs_buff[75] = adapter->stats.prc127;
 448         regs_buff[76] = adapter->stats.prc255;
 449         regs_buff[77] = adapter->stats.prc511;
 450         regs_buff[78] = adapter->stats.prc1023;
 451         regs_buff[79] = adapter->stats.prc1522;
 452         regs_buff[80] = adapter->stats.gprc;
 453         regs_buff[81] = adapter->stats.bprc;
 454         regs_buff[82] = adapter->stats.mprc;
 455         regs_buff[83] = adapter->stats.gptc;
 456         regs_buff[84] = adapter->stats.gorc;
 457         regs_buff[86] = adapter->stats.gotc;
 458         regs_buff[88] = adapter->stats.rnbc;
 459         regs_buff[89] = adapter->stats.ruc;
 460         regs_buff[90] = adapter->stats.rfc;
 461         regs_buff[91] = adapter->stats.roc;
 462         regs_buff[92] = adapter->stats.rjc;
 463         regs_buff[93] = adapter->stats.mgprc;
 464         regs_buff[94] = adapter->stats.mgpdc;
 465         regs_buff[95] = adapter->stats.mgptc;
 466         regs_buff[96] = adapter->stats.tor;
 467         regs_buff[98] = adapter->stats.tot;
 468         regs_buff[100] = adapter->stats.tpr;
 469         regs_buff[101] = adapter->stats.tpt;
 470         regs_buff[102] = adapter->stats.ptc64;
 471         regs_buff[103] = adapter->stats.ptc127;
 472         regs_buff[104] = adapter->stats.ptc255;
 473         regs_buff[105] = adapter->stats.ptc511;
 474         regs_buff[106] = adapter->stats.ptc1023;
 475         regs_buff[107] = adapter->stats.ptc1522;
 476         regs_buff[108] = adapter->stats.mptc;
 477         regs_buff[109] = adapter->stats.bptc;
 478         regs_buff[110] = adapter->stats.tsctc;
 479         regs_buff[111] = adapter->stats.iac;
 480         regs_buff[112] = adapter->stats.rpthc;
 481         regs_buff[113] = adapter->stats.hgptc;
 482         regs_buff[114] = adapter->stats.hgorc;
 483         regs_buff[116] = adapter->stats.hgotc;
 484         regs_buff[118] = adapter->stats.lenerrs;
 485         regs_buff[119] = adapter->stats.scvpc;
 486         regs_buff[120] = adapter->stats.hrmpc;
 487
 488         /* These should probably be added to e1000_regs.h instead */
 489         #define E1000_PSRTYPE_REG(_i) (0x05480 + ((_i) * 4))
 490         #define E1000_IP4AT_REG(_i)   (0x05840 + ((_i) * 8))
 491         #define E1000_IP6AT_REG(_i)   (0x05880 + ((_i) * 4))
 492         #define E1000_WUPM_REG(_i)    (0x05A00 + ((_i) * 4))
 493         #define E1000_FFMT_REG(_i)    (0x09000 + ((_i) * 8))
 494         #define E1000_FFVT_REG(_i)    (0x09800 + ((_i) * 8))
 495         #define E1000_FFLT_REG(_i)    (0x05F00 + ((_i) * 8))
 496
 497         for (i = 0; i < 4; i++)
 498                 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
 499         for (i = 0; i < 4; i++)
 500                 regs_buff[125 + i] = rd32(E1000_PSRTYPE_REG(i));
 501         for (i = 0; i < 4; i++)
 502                 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
 503         for (i = 0; i < 4; i++)
 504                 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
 505         for (i = 0; i < 4; i++)
 506                 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
 507         for (i = 0; i < 4; i++)
 508                 regs_buff[141 + i] = rd32(E1000_RDH(i));
 509         for (i = 0; i < 4; i++)
 510                 regs_buff[145 + i] = rd32(E1000_RDT(i));
 511         for (i = 0; i < 4; i++)
 512                 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
 513
 514         for (i = 0; i < 10; i++)
 515                 regs_buff[153 + i] = rd32(E1000_EITR(i));
 516         for (i = 0; i < 8; i++)
 517                 regs_buff[163 + i] = rd32(E1000_IMIR(i));
 518         for (i = 0; i < 8; i++)
 519                 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
 520         for (i = 0; i < 16; i++)
 521                 regs_buff[179 + i] = rd32(E1000_RAL(i));
 522         for (i = 0; i < 16; i++)
 523                 regs_buff[195 + i] = rd32(E1000_RAH(i));
 524
 525         for (i = 0; i < 4; i++)
 526                 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
 527         for (i = 0; i < 4; i++)
 528                 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
 529         for (i = 0; i < 4; i++)
 530                 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
 531         for (i = 0; i < 4; i++)
 532                 regs_buff[223 + i] = rd32(E1000_TDH(i));
 533         for (i = 0; i < 4; i++)
 534                 regs_buff[227 + i] = rd32(E1000_TDT(i));
 535         for (i = 0; i < 4; i++)
 536                 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
 537         for (i = 0; i < 4; i++)
 538                 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
 539         for (i = 0; i < 4; i++)
 540                 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
 541         for (i = 0; i < 4; i++)
 542                 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
 543
 544         for (i = 0; i < 4; i++)
 545                 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
 546         for (i = 0; i < 4; i++)
 547                 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
 548         for (i = 0; i < 32; i++)
 549                 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
 550         for (i = 0; i < 128; i++)
 551                 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
 552         for (i = 0; i < 128; i++)
 553                 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
 554         for (i = 0; i < 4; i++)
 555                 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
 556
 557         regs_buff[547] = rd32(E1000_TDFH);
 558         regs_buff[548] = rd32(E1000_TDFT);
 559         regs_buff[549] = rd32(E1000_TDFHS);
 560         regs_buff[550] = rd32(E1000_TDFPC);
 561
 562 }
 563
 564 static int igb_get_eeprom_len(struct net_device *netdev)
 565 {
 566         struct igb_adapter *adapter = netdev_priv(netdev);
 567         return adapter->hw.nvm.word_size * 2;
 568 }
 569
 570 static int igb_get_eeprom(struct net_device *netdev,
 571                           struct ethtool_eeprom *eeprom, u8 *bytes)
 572 {
 573         struct igb_adapter *adapter = netdev_priv(netdev);
 574         struct e1000_hw *hw = &adapter->hw;
 575         u16 *eeprom_buff;
 576         int first_word, last_word;
 577         int ret_val = 0;
 578         u16 i;
 579
 580         if (eeprom->len == 0)
 581                 return -EINVAL;
 582
 583         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
 584
 585         first_word = eeprom->offset >> 1;
 586         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
 587
 588         eeprom_buff = kmalloc(sizeof(u16) *
 589                         (last_word - first_word + 1), GFP_KERNEL);
 590         if (!eeprom_buff)
 591                 return -ENOMEM;
 592
 593         if (hw->nvm.type == e1000_nvm_eeprom_spi)
 594                 ret_val = hw->nvm.ops.read(hw, first_word,
 595                                             last_word - first_word + 1,
 596                                             eeprom_buff);
 597         else {
 598                 for (i = 0; i < last_word - first_word + 1; i++) {
 599                         ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
 600                                                     &eeprom_buff[i]);
 601                         if (ret_val)
 602                                 break;
 603                 }
 604         }
 605
 606         /* Device's eeprom is always little-endian, word addressable */
 607         for (i = 0; i < last_word - first_word + 1; i++)
 608                 le16_to_cpus(&eeprom_buff[i]);
 609
 610         memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
 611                         eeprom->len);
 612         kfree(eeprom_buff);
 613
 614         return ret_val;
 615 }
 616
 617 static int igb_set_eeprom(struct net_device *netdev,
 618                           struct ethtool_eeprom *eeprom, u8 *bytes)
 619 {
 620         struct igb_adapter *adapter = netdev_priv(netdev);
 621         struct e1000_hw *hw = &adapter->hw;
 622         u16 *eeprom_buff;
 623         void *ptr;
 624         int max_len, first_word, last_word, ret_val = 0;
 625         u16 i;
 626
 627         if (eeprom->len == 0)
 628                 return -EOPNOTSUPP;
 629
 630         if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
 631                 return -EFAULT;
 632
 633         max_len = hw->nvm.word_size * 2;
 634
 635         first_word = eeprom->offset >> 1;
 636         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
 637         eeprom_buff = kmalloc(max_len, GFP_KERNEL);
 638         if (!eeprom_buff)
 639                 return -ENOMEM;
 640
 641         ptr = (void *)eeprom_buff;
 642
 643         if (eeprom->offset & 1) {
 644                 /* need read/modify/write of first changed EEPROM word */
 645                 /* only the second byte of the word is being modified */
 646                 ret_val = hw->nvm.ops.read(hw, first_word, 1,
 647                                             &eeprom_buff[0]);
 648                 ptr++;
 649         }
 650         if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
 651                 /* need read/modify/write of last changed EEPROM word */
 652                 /* only the first byte of the word is being modified */
 653                 ret_val = hw->nvm.ops.read(hw, last_word, 1,
 654                                    &eeprom_buff[last_word - first_word]);
 655         }
 656
 657         /* Device's eeprom is always little-endian, word addressable */
 658         for (i = 0; i < last_word - first_word + 1; i++)
 659                 le16_to_cpus(&eeprom_buff[i]);
 660
 661         memcpy(ptr, bytes, eeprom->len);
 662
 663         for (i = 0; i < last_word - first_word + 1; i++)
 664                 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
 665
 666         ret_val = hw->nvm.ops.write(hw, first_word,
 667                                      last_word - first_word + 1, eeprom_buff);
 668
 669         /* Update the checksum over the first part of the EEPROM if needed
 670          * and flush shadow RAM for 82573 controllers */
 671         if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
 672                 igb_update_nvm_checksum(hw);
 673
 674         kfree(eeprom_buff);
 675         return ret_val;
 676 }
 677
 678 static void igb_get_drvinfo(struct net_device *netdev,
 679                             struct ethtool_drvinfo *drvinfo)
 680 {
 681         struct igb_adapter *adapter = netdev_priv(netdev);
 682         char firmware_version[32];
 683         u16 eeprom_data;
 684
 685         strncpy(drvinfo->driver,  igb_driver_name, 32);
 686         strncpy(drvinfo->version, igb_driver_version, 32);
 687
 688         /* EEPROM image version # is reported as firmware version # for
 689          * 82575 controllers */
 690         adapter->hw.nvm.ops.read(&adapter->hw, 5, 1, &eeprom_data);
 691         sprintf(firmware_version, "%d.%d-%d",
 692                 (eeprom_data & 0xF000) >> 12,
 693                 (eeprom_data & 0x0FF0) >> 4,
 694                 eeprom_data & 0x000F);
 695
 696         strncpy(drvinfo->fw_version, firmware_version, 32);
 697         strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
 698         drvinfo->n_stats = IGB_STATS_LEN;
 699         drvinfo->testinfo_len = IGB_TEST_LEN;
 700         drvinfo->regdump_len = igb_get_regs_len(netdev);
 701         drvinfo->eedump_len = igb_get_eeprom_len(netdev);
 702 }
 703
 704 static void igb_get_ringparam(struct net_device *netdev,
 705                               struct ethtool_ringparam *ring)
 706 {
 707         struct igb_adapter *adapter = netdev_priv(netdev);
 708
 709         ring->rx_max_pending = IGB_MAX_RXD;
 710         ring->tx_max_pending = IGB_MAX_TXD;
 711         ring->rx_mini_max_pending = 0;
 712         ring->rx_jumbo_max_pending = 0;
 713         ring->rx_pending = adapter->rx_ring_count;
 714         ring->tx_pending = adapter->tx_ring_count;
 715         ring->rx_mini_pending = 0;
 716         ring->rx_jumbo_pending = 0;
 717 }
 718
 719 static int igb_set_ringparam(struct net_device *netdev,
 720                              struct ethtool_ringparam *ring)
 721 {
 722         struct igb_adapter *adapter = netdev_priv(netdev);
 723         struct igb_ring *temp_ring;
 724         int i, err;
 725         u32 new_rx_count, new_tx_count;
 726
 727         if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
 728                 return -EINVAL;
 729
 730         new_rx_count = max(ring->rx_pending, (u32)IGB_MIN_RXD);
 731         new_rx_count = min(new_rx_count, (u32)IGB_MAX_RXD);
 732         new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
 733
 734         new_tx_count = max(ring->tx_pending, (u32)IGB_MIN_TXD);
 735         new_tx_count = min(new_tx_count, (u32)IGB_MAX_TXD);
 736         new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
 737
 738         if ((new_tx_count == adapter->tx_ring_count) &&
 739             (new_rx_count == adapter->rx_ring_count)) {
 740                 /* nothing to do */
 741                 return 0;
 742         }
 743
 744         if (adapter->num_tx_queues > adapter->num_rx_queues)
 745                 temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring));
 746         else
 747                 temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring));
 748         if (!temp_ring)
 749                 return -ENOMEM;
 750
 751         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 752                 msleep(1);
 753
 754         if (netif_running(adapter->netdev))
 755                 igb_down(adapter);
 756
 757         /*
 758          * We can't just free everything and then setup again,
 759          * because the ISRs in MSI-X mode get passed pointers
 760          * to the tx and rx ring structs.
 761          */
 762         if (new_tx_count != adapter->tx_ring_count) {
 763                 memcpy(temp_ring, adapter->tx_ring,
 764                        adapter->num_tx_queues * sizeof(struct igb_ring));
 765
 766                 for (i = 0; i < adapter->num_tx_queues; i++) {
 767                         temp_ring[i].count = new_tx_count;
 768                         err = igb_setup_tx_resources(adapter, &temp_ring[i]);
 769                         if (err) {
 770                                 while (i) {
 771                                         i--;
 772                                         igb_free_tx_resources(&temp_ring[i]);
 773                                 }
 774                                 goto err_setup;
 775                         }
 776                 }
 777
 778                 for (i = 0; i < adapter->num_tx_queues; i++)
 779                         igb_free_tx_resources(&adapter->tx_ring[i]);
 780
 781                 memcpy(adapter->tx_ring, temp_ring,
 782                        adapter->num_tx_queues * sizeof(struct igb_ring));
 783
 784                 adapter->tx_ring_count = new_tx_count;
 785         }
 786
 787         if (new_rx_count != adapter->rx_ring->count) {
 788                 memcpy(temp_ring, adapter->rx_ring,
 789                        adapter->num_rx_queues * sizeof(struct igb_ring));
 790
 791                 for (i = 0; i < adapter->num_rx_queues; i++) {
 792                         temp_ring[i].count = new_rx_count;
 793                         err = igb_setup_rx_resources(adapter, &temp_ring[i]);
 794                         if (err) {
 795                                 while (i) {
 796                                         i--;
 797                                         igb_free_rx_resources(&temp_ring[i]);
 798                                 }
 799                                 goto err_setup;
 800                         }
 801
 802                 }
 803
 804                 for (i = 0; i < adapter->num_rx_queues; i++)
 805                         igb_free_rx_resources(&adapter->rx_ring[i]);
 806
 807                 memcpy(adapter->rx_ring, temp_ring,
 808                        adapter->num_rx_queues * sizeof(struct igb_ring));
 809
 810                 adapter->rx_ring_count = new_rx_count;
 811         }
 812
 813         err = 0;
 814 err_setup:
 815         if (netif_running(adapter->netdev))
 816                 igb_up(adapter);
 817
 818         clear_bit(__IGB_RESETTING, &adapter->state);
 819         vfree(temp_ring);
 820         return err;
 821 }
 822
 823 /* ethtool register test data */
 824 struct igb_reg_test {
 825         u16 reg;
 826         u16 reg_offset;
 827         u16 array_len;
 828         u16 test_type;
 829         u32 mask;
 830         u32 write;
 831 };
 832
 833 /* In the hardware, registers are laid out either singly, in arrays
 834  * spaced 0x100 bytes apart, or in contiguous tables.  We assume
 835  * most tests take place on arrays or single registers (handled
 836  * as a single-element array) and special-case the tables.
 837  * Table tests are always pattern tests.
 838  *
 839  * We also make provision for some required setup steps by specifying
 840  * registers to be written without any read-back testing.
 841  */
 842
 843 #define PATTERN_TEST    1
 844 #define SET_READ_TEST   2
 845 #define WRITE_NO_TEST   3
 846 #define TABLE32_TEST    4
 847 #define TABLE64_TEST_LO 5
 848 #define TABLE64_TEST_HI 6
 849
 850 /* 82576 reg test */
 851 static struct igb_reg_test reg_test_82576[] = {
 852         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 853         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 854         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 855         { E1000_VET,       0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 856         { E1000_RDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 857         { E1000_RDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 858         { E1000_RDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 859         { E1000_RDBAL(4),  0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 860         { E1000_RDBAH(4),  0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 861         { E1000_RDLEN(4),  0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 862         /* Enable all RX queues before testing. */
 863         { E1000_RXDCTL(0), 0x100, 4,  WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
 864         { E1000_RXDCTL(4), 0x40, 12,  WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
 865         /* RDH is read-only for 82576, only test RDT. */
 866         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 867         { E1000_RDT(4),    0x40, 12,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 868         { E1000_RXDCTL(0), 0x100, 4,  WRITE_NO_TEST, 0, 0 },
 869         { E1000_RXDCTL(4), 0x40, 12,  WRITE_NO_TEST, 0, 0 },
 870         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
 871         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 872         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
 873         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 874         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 875         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 876         { E1000_TDBAL(4),  0x40, 12,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 877         { E1000_TDBAH(4),  0x40, 12,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 878         { E1000_TDLEN(4),  0x40, 12,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 879         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 880         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
 881         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
 882         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 883         { E1000_RA,        0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
 884         { E1000_RA,        0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
 885         { E1000_RA2,       0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
 886         { E1000_RA2,       0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
 887         { E1000_MTA,       0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 888         { 0, 0, 0, 0 }
 889 };
 890
 891 /* 82575 register test */
 892 static struct igb_reg_test reg_test_82575[] = {
 893         { E1000_FCAL,      0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 894         { E1000_FCAH,      0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 895         { E1000_FCT,       0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 896         { E1000_VET,       0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 897         { E1000_RDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 898         { E1000_RDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 899         { E1000_RDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
 900         /* Enable all four RX queues before testing. */
 901         { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
 902         /* RDH is read-only for 82575, only test RDT. */
 903         { E1000_RDT(0),    0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 904         { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
 905         { E1000_FCRTH,     0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
 906         { E1000_FCTTV,     0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 907         { E1000_TIPG,      0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
 908         { E1000_TDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 909         { E1000_TDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 910         { E1000_TDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
 911         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 912         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
 913         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
 914         { E1000_TCTL,      0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 915         { E1000_TXCW,      0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
 916         { E1000_RA,        0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
 917         { E1000_RA,        0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
 918         { E1000_MTA,       0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 919         { 0, 0, 0, 0 }
 920 };
 921
 922 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
 923                              int reg, u32 mask, u32 write)
 924 {
 925         struct e1000_hw *hw = &adapter->hw;
 926         u32 pat, val;
 927         u32 _test[] =
 928                 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
 929         for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
 930                 wr32(reg, (_test[pat] & write));
 931                 val = rd32(reg);
 932                 if (val != (_test[pat] & write & mask)) {
 933                         dev_err(&adapter->pdev->dev, "pattern test reg %04X "
 934                                 "failed: got 0x%08X expected 0x%08X\n",
 935                                 reg, val, (_test[pat] & write & mask));
 936                         *data = reg;
 937                         return 1;
 938                 }
 939         }
 940         return 0;
 941 }
 942
 943 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
 944                               int reg, u32 mask, u32 write)
 945 {
 946         struct e1000_hw *hw = &adapter->hw;
 947         u32 val;
 948         wr32(reg, write & mask);
 949         val = rd32(reg);
 950         if ((write & mask) != (val & mask)) {
 951                 dev_err(&adapter->pdev->dev, "set/check reg %04X test failed:"
 952                         " got 0x%08X expected 0x%08X\n", reg,
 953                         (val & mask), (write & mask));
 954                 *data = reg;
 955                 return 1;
 956         }
 957         return 0;
 958 }
 959
 960 #define REG_PATTERN_TEST(reg, mask, write) \
 961         do { \
 962                 if (reg_pattern_test(adapter, data, reg, mask, write)) \
 963                         return 1; \
 964         } while (0)
 965
 966 #define REG_SET_AND_CHECK(reg, mask, write) \
 967         do { \
 968                 if (reg_set_and_check(adapter, data, reg, mask, write)) \
 969                         return 1; \
 970         } while (0)
 971
 972 static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
 973 {
 974         struct e1000_hw *hw = &adapter->hw;
 975         struct igb_reg_test *test;
 976         u32 value, before, after;
 977         u32 i, toggle;
 978
 979         toggle = 0x7FFFF3FF;
 980
 981         switch (adapter->hw.mac.type) {
 982         case e1000_82576:
 983                 test = reg_test_82576;
 984                 break;
 985         default:
 986                 test = reg_test_82575;
 987                 break;
 988         }
 989
 990         /* Because the status register is such a special case,
 991          * we handle it separately from the rest of the register
 992          * tests.  Some bits are read-only, some toggle, and some
 993          * are writable on newer MACs.
 994          */
 995         before = rd32(E1000_STATUS);
 996         value = (rd32(E1000_STATUS) & toggle);
 997         wr32(E1000_STATUS, toggle);
 998         after = rd32(E1000_STATUS) & toggle;
 999         if (value != after) {
1000                 dev_err(&adapter->pdev->dev, "failed STATUS register test "
1001                         "got: 0x%08X expected: 0x%08X\n", after, value);
1002                 *data = 1;
1003                 return 1;
1004         }
1005         /* restore previous status */
1006         wr32(E1000_STATUS, before);
1007
1008         /* Perform the remainder of the register test, looping through
1009          * the test table until we either fail or reach the null entry.
1010          */
1011         while (test->reg) {
1012                 for (i = 0; i < test->array_len; i++) {
1013                         switch (test->test_type) {
1014                         case PATTERN_TEST:
1015                                 REG_PATTERN_TEST(test->reg +
1016                                                 (i * test->reg_offset),
1017                                                 test->mask,
1018                                                 test->write);
1019                                 break;
1020                         case SET_READ_TEST:
1021                                 REG_SET_AND_CHECK(test->reg +
1022                                                 (i * test->reg_offset),
1023                                                 test->mask,
1024                                                 test->write);
1025                                 break;
1026                         case WRITE_NO_TEST:
1027                                 writel(test->write,
1028                                     (adapter->hw.hw_addr + test->reg)
1029                                         + (i * test->reg_offset));
1030                                 break;
1031                         case TABLE32_TEST:
1032                                 REG_PATTERN_TEST(test->reg + (i * 4),
1033                                                 test->mask,
1034                                                 test->write);
1035                                 break;
1036                         case TABLE64_TEST_LO:
1037                                 REG_PATTERN_TEST(test->reg + (i * 8),
1038                                                 test->mask,
1039                                                 test->write);
1040                                 break;
1041                         case TABLE64_TEST_HI:
1042                                 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1043                                                 test->mask,
1044                                                 test->write);
1045                                 break;
1046                         }
1047                 }
1048                 test++;
1049         }
1050
1051         *data = 0;
1052         return 0;
1053 }
1054
1055 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1056 {
1057         u16 temp;
1058         u16 checksum = 0;
1059         u16 i;
1060
1061         *data = 0;
1062         /* Read and add up the contents of the EEPROM */
1063         for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1064                 if ((adapter->hw.nvm.ops.read(&adapter->hw, i, 1, &temp))
1065                     < 0) {
1066                         *data = 1;
1067                         break;
1068                 }
1069                 checksum += temp;
1070         }
1071
1072         /* If Checksum is not Correct return error else test passed */
1073         if ((checksum != (u16) NVM_SUM) && !(*data))
1074                 *data = 2;
1075
1076         return *data;
1077 }
1078
1079 static irqreturn_t igb_test_intr(int irq, void *data)
1080 {
1081         struct net_device *netdev = (struct net_device *) data;
1082         struct igb_adapter *adapter = netdev_priv(netdev);
1083         struct e1000_hw *hw = &adapter->hw;
1084
1085         adapter->test_icr |= rd32(E1000_ICR);
1086
1087         return IRQ_HANDLED;
1088 }
1089
1090 static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1091 {
1092         struct e1000_hw *hw = &adapter->hw;
1093         struct net_device *netdev = adapter->netdev;
1094         u32 mask, ics_mask, i = 0, shared_int = true;
1095         u32 irq = adapter->pdev->irq;
1096
1097         *data = 0;
1098
1099         /* Hook up test interrupt handler just for this test */
1100         if (adapter->msix_entries)
1101                 /* NOTE: we don't test MSI-X interrupts here, yet */
1102                 return 0;
1103
1104         if (adapter->flags & IGB_FLAG_HAS_MSI) {
1105                 shared_int = false;
1106                 if (request_irq(irq, &igb_test_intr, 0, netdev->name, netdev)) {
1107                         *data = 1;
1108                         return -1;
1109                 }
1110         } else if (!request_irq(irq, &igb_test_intr, IRQF_PROBE_SHARED,
1111                                 netdev->name, netdev)) {
1112                 shared_int = false;
1113         } else if (request_irq(irq, &igb_test_intr, IRQF_SHARED,
1114                  netdev->name, netdev)) {
1115                 *data = 1;
1116                 return -1;
1117         }
1118         dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1119                 (shared_int ? "shared" : "unshared"));
1120         /* Disable all the interrupts */
1121         wr32(E1000_IMC, 0xFFFFFFFF);
1122         msleep(10);
1123
1124         /* Define all writable bits for ICS */
1125         switch(hw->mac.type) {
1126         case e1000_82575:
1127                 ics_mask = 0x37F47EDD;
1128                 break;
1129         case e1000_82576:
1130                 ics_mask = 0x77D4FBFD;
1131                 break;
1132         default:
1133                 ics_mask = 0x7FFFFFFF;
1134                 break;
1135         }
1136
1137         /* Test each interrupt */
1138         for (; i < 31; i++) {
1139                 /* Interrupt to test */
1140                 mask = 1 << i;
1141
1142                 if (!(mask & ics_mask))
1143                         continue;
1144
1145                 if (!shared_int) {
1146                         /* Disable the interrupt to be reported in
1147                          * the cause register and then force the same
1148                          * interrupt and see if one gets posted.  If
1149                          * an interrupt was posted to the bus, the
1150                          * test failed.
1151                          */
1152                         adapter->test_icr = 0;
1153
1154                         /* Flush any pending interrupts */
1155                         wr32(E1000_ICR, ~0);
1156
1157                         wr32(E1000_IMC, mask);
1158                         wr32(E1000_ICS, mask);
1159                         msleep(10);
1160
1161                         if (adapter->test_icr & mask) {
1162                                 *data = 3;
1163                                 break;
1164                         }
1165                 }
1166
1167                 /* Enable the interrupt to be reported in
1168                  * the cause register and then force the same
1169                  * interrupt and see if one gets posted.  If
1170                  * an interrupt was not posted to the bus, the
1171                  * test failed.
1172                  */
1173                 adapter->test_icr = 0;
1174
1175                 /* Flush any pending interrupts */
1176                 wr32(E1000_ICR, ~0);
1177
1178                 wr32(E1000_IMS, mask);
1179                 wr32(E1000_ICS, mask);
1180                 msleep(10);
1181
1182                 if (!(adapter->test_icr & mask)) {
1183                         *data = 4;
1184                         break;
1185                 }
1186
1187                 if (!shared_int) {
1188                         /* Disable the other interrupts to be reported in
1189                          * the cause register and then force the other
1190                          * interrupts and see if any get posted.  If
1191                          * an interrupt was posted to the bus, the
1192                          * test failed.
1193                          */
1194                         adapter->test_icr = 0;
1195
1196                         /* Flush any pending interrupts */
1197                         wr32(E1000_ICR, ~0);
1198
1199                         wr32(E1000_IMC, ~mask);
1200                         wr32(E1000_ICS, ~mask);
1201                         msleep(10);
1202
1203                         if (adapter->test_icr & mask) {
1204                                 *data = 5;
1205                                 break;
1206                         }
1207                 }
1208         }
1209
1210         /* Disable all the interrupts */
1211         wr32(E1000_IMC, ~0);
1212         msleep(10);
1213
1214         /* Unhook test interrupt handler */
1215         free_irq(irq, netdev);
1216
1217         return *data;
1218 }
1219
1220 static void igb_free_desc_rings(struct igb_adapter *adapter)
1221 {
1222         struct igb_ring *tx_ring = &adapter->test_tx_ring;
1223         struct igb_ring *rx_ring = &adapter->test_rx_ring;
1224         struct pci_dev *pdev = adapter->pdev;
1225         int i;
1226
1227         if (tx_ring->desc && tx_ring->buffer_info) {
1228                 for (i = 0; i < tx_ring->count; i++) {
1229                         struct igb_buffer *buf = &(tx_ring->buffer_info[i]);
1230                         if (buf->dma)
1231                                 pci_unmap_single(pdev, buf->dma, buf->length,
1232                                                  PCI_DMA_TODEVICE);
1233                         if (buf->skb)
1234                                 dev_kfree_skb(buf->skb);
1235                 }
1236         }
1237
1238         if (rx_ring->desc && rx_ring->buffer_info) {
1239                 for (i = 0; i < rx_ring->count; i++) {
1240                         struct igb_buffer *buf = &(rx_ring->buffer_info[i]);
1241                         if (buf->dma)
1242                                 pci_unmap_single(pdev, buf->dma,
1243                                                  IGB_RXBUFFER_2048,
1244                                                  PCI_DMA_FROMDEVICE);
1245                         if (buf->skb)
1246                                 dev_kfree_skb(buf->skb);
1247                 }
1248         }
1249
1250         if (tx_ring->desc) {
1251                 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc,
1252                                     tx_ring->dma);
1253                 tx_ring->desc = NULL;
1254         }
1255         if (rx_ring->desc) {
1256                 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc,
1257                                     rx_ring->dma);
1258                 rx_ring->desc = NULL;
1259         }
1260
1261         kfree(tx_ring->buffer_info);
1262         tx_ring->buffer_info = NULL;
1263         kfree(rx_ring->buffer_info);
1264         rx_ring->buffer_info = NULL;
1265
1266         return;
1267 }
1268
1269 static int igb_setup_desc_rings(struct igb_adapter *adapter)
1270 {
1271         struct e1000_hw *hw = &adapter->hw;
1272         struct igb_ring *tx_ring = &adapter->test_tx_ring;
1273         struct igb_ring *rx_ring = &adapter->test_rx_ring;
1274         struct pci_dev *pdev = adapter->pdev;
1275         struct igb_buffer *buffer_info;
1276         u32 rctl;
1277         int i, ret_val;
1278
1279         /* Setup Tx descriptor ring and Tx buffers */
1280
1281         if (!tx_ring->count)
1282                 tx_ring->count = IGB_DEFAULT_TXD;
1283
1284         tx_ring->buffer_info = kcalloc(tx_ring->count,
1285                                        sizeof(struct igb_buffer),
1286                                        GFP_KERNEL);
1287         if (!tx_ring->buffer_info) {
1288                 ret_val = 1;
1289                 goto err_nomem;
1290         }
1291
1292         tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
1293         tx_ring->size = ALIGN(tx_ring->size, 4096);
1294         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1295                                              &tx_ring->dma);
1296         if (!tx_ring->desc) {
1297                 ret_val = 2;
1298                 goto err_nomem;
1299         }
1300         tx_ring->next_to_use = tx_ring->next_to_clean = 0;
1301
1302         wr32(E1000_TDBAL(0),
1303                         ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
1304         wr32(E1000_TDBAH(0), ((u64) tx_ring->dma >> 32));
1305         wr32(E1000_TDLEN(0),
1306                         tx_ring->count * sizeof(union e1000_adv_tx_desc));
1307         wr32(E1000_TDH(0), 0);
1308         wr32(E1000_TDT(0), 0);
1309         wr32(E1000_TCTL,
1310                         E1000_TCTL_PSP | E1000_TCTL_EN |
1311                         E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT |
1312                         E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT);
1313
1314         for (i = 0; i < tx_ring->count; i++) {
1315                 union e1000_adv_tx_desc *tx_desc;
1316                 struct sk_buff *skb;
1317                 unsigned int size = 1024;
1318
1319                 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
1320                 skb = alloc_skb(size, GFP_KERNEL);
1321                 if (!skb) {
1322                         ret_val = 3;
1323                         goto err_nomem;
1324                 }
1325                 skb_put(skb, size);
1326                 buffer_info = &tx_ring->buffer_info[i];
1327                 buffer_info->skb = skb;
1328                 buffer_info->length = skb->len;
1329                 buffer_info->dma = pci_map_single(pdev, skb->data, skb->len,
1330                                                   PCI_DMA_TODEVICE);
1331                 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
1332                 tx_desc->read.olinfo_status = cpu_to_le32(skb->len) <<
1333                                               E1000_ADVTXD_PAYLEN_SHIFT;
1334                 tx_desc->read.cmd_type_len = cpu_to_le32(skb->len);
1335                 tx_desc->read.cmd_type_len |= cpu_to_le32(E1000_TXD_CMD_EOP |
1336                                                           E1000_TXD_CMD_IFCS |
1337                                                           E1000_TXD_CMD_RS |
1338                                                           E1000_ADVTXD_DTYP_DATA |
1339                                                           E1000_ADVTXD_DCMD_DEXT);
1340         }
1341
1342         /* Setup Rx descriptor ring and Rx buffers */
1343
1344         if (!rx_ring->count)
1345                 rx_ring->count = IGB_DEFAULT_RXD;
1346
1347         rx_ring->buffer_info = kcalloc(rx_ring->count,
1348                                        sizeof(struct igb_buffer),
1349                                        GFP_KERNEL);
1350         if (!rx_ring->buffer_info) {
1351                 ret_val = 4;
1352                 goto err_nomem;
1353         }
1354
1355         rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
1356         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1357                                              &rx_ring->dma);
1358         if (!rx_ring->desc) {
1359                 ret_val = 5;
1360                 goto err_nomem;
1361         }
1362         rx_ring->next_to_use = rx_ring->next_to_clean = 0;
1363
1364         rctl = rd32(E1000_RCTL);
1365         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1366         wr32(E1000_RDBAL(0),
1367                         ((u64) rx_ring->dma & 0xFFFFFFFF));
1368         wr32(E1000_RDBAH(0),
1369                         ((u64) rx_ring->dma >> 32));
1370         wr32(E1000_RDLEN(0), rx_ring->size);
1371         wr32(E1000_RDH(0), 0);
1372         wr32(E1000_RDT(0), 0);
1373         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1374         rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
1375                 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1376         wr32(E1000_RCTL, rctl);
1377         wr32(E1000_SRRCTL(0), E1000_SRRCTL_DESCTYPE_ADV_ONEBUF);
1378
1379         for (i = 0; i < rx_ring->count; i++) {
1380                 union e1000_adv_rx_desc *rx_desc;
1381                 struct sk_buff *skb;
1382
1383                 buffer_info = &rx_ring->buffer_info[i];
1384                 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
1385                 skb = alloc_skb(IGB_RXBUFFER_2048 + NET_IP_ALIGN,
1386                                 GFP_KERNEL);
1387                 if (!skb) {
1388                         ret_val = 6;
1389                         goto err_nomem;
1390                 }
1391                 skb_reserve(skb, NET_IP_ALIGN);
1392                 buffer_info->skb = skb;
1393                 buffer_info->dma = pci_map_single(pdev, skb->data,
1394                                                   IGB_RXBUFFER_2048,
1395                                                   PCI_DMA_FROMDEVICE);
1396                 rx_desc->read.pkt_addr = cpu_to_le64(buffer_info->dma);
1397                 memset(skb->data, 0x00, skb->len);
1398         }
1399
1400         return 0;
1401
1402 err_nomem:
1403         igb_free_desc_rings(adapter);
1404         return ret_val;
1405 }
1406
1407 static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1408 {
1409         struct e1000_hw *hw = &adapter->hw;
1410
1411         /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1412         igb_write_phy_reg(hw, 29, 0x001F);
1413         igb_write_phy_reg(hw, 30, 0x8FFC);
1414         igb_write_phy_reg(hw, 29, 0x001A);
1415         igb_write_phy_reg(hw, 30, 0x8FF0);
1416 }
1417
1418 static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1419 {
1420         struct e1000_hw *hw = &adapter->hw;
1421         u32 ctrl_reg = 0;
1422
1423         hw->mac.autoneg = false;
1424
1425         if (hw->phy.type == e1000_phy_m88) {
1426                 /* Auto-MDI/MDIX Off */
1427                 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1428                 /* reset to update Auto-MDI/MDIX */
1429                 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1430                 /* autoneg off */
1431                 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1432         }
1433
1434         ctrl_reg = rd32(E1000_CTRL);
1435
1436         /* force 1000, set loopback */
1437         igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1438
1439         /* Now set up the MAC to the same speed/duplex as the PHY. */
1440         ctrl_reg = rd32(E1000_CTRL);
1441         ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1442         ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1443                      E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1444                      E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1445                      E1000_CTRL_FD |     /* Force Duplex to FULL */
1446                      E1000_CTRL_SLU);    /* Set link up enable bit */
1447
1448         if (hw->phy.type == e1000_phy_m88)
1449                 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1450
1451         wr32(E1000_CTRL, ctrl_reg);
1452
1453         /* Disable the receiver on the PHY so when a cable is plugged in, the
1454          * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1455          */
1456         if (hw->phy.type == e1000_phy_m88)
1457                 igb_phy_disable_receiver(adapter);
1458
1459         udelay(500);
1460
1461         return 0;
1462 }
1463
1464 static int igb_set_phy_loopback(struct igb_adapter *adapter)
1465 {
1466         return igb_integrated_phy_loopback(adapter);
1467 }
1468
1469 static int igb_setup_loopback_test(struct igb_adapter *adapter)
1470 {
1471         struct e1000_hw *hw = &adapter->hw;
1472         u32 reg;
1473
1474         if (hw->phy.media_type == e1000_media_type_fiber ||
1475             hw->phy.media_type == e1000_media_type_internal_serdes) {
1476                 reg = rd32(E1000_RCTL);
1477                 reg |= E1000_RCTL_LBM_TCVR;
1478                 wr32(E1000_RCTL, reg);
1479
1480                 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1481
1482                 reg = rd32(E1000_CTRL);
1483                 reg &= ~(E1000_CTRL_RFCE |
1484                          E1000_CTRL_TFCE |
1485                          E1000_CTRL_LRST);
1486                 reg |= E1000_CTRL_SLU |
1487                        E1000_CTRL_FD;
1488                 wr32(E1000_CTRL, reg);
1489
1490                 /* Unset switch control to serdes energy detect */
1491                 reg = rd32(E1000_CONNSW);
1492                 reg &= ~E1000_CONNSW_ENRGSRC;
1493                 wr32(E1000_CONNSW, reg);
1494
1495                 /* Set PCS register for forced speed */
1496                 reg = rd32(E1000_PCS_LCTL);
1497                 reg &= ~E1000_PCS_LCTL_AN_ENABLE;     /* Disable Autoneg*/
1498                 reg |= E1000_PCS_LCTL_FLV_LINK_UP |   /* Force link up */
1499                        E1000_PCS_LCTL_FSV_1000 |      /* Force 1000    */
1500                        E1000_PCS_LCTL_FDV_FULL |      /* SerDes Full duplex */
1501                        E1000_PCS_LCTL_FSD |           /* Force Speed */
1502                        E1000_PCS_LCTL_FORCE_LINK;     /* Force Link */
1503                 wr32(E1000_PCS_LCTL, reg);
1504
1505                 return 0;
1506         } else if (hw->phy.media_type == e1000_media_type_copper) {
1507                 return igb_set_phy_loopback(adapter);
1508         }
1509
1510         return 7;
1511 }
1512
1513 static void igb_loopback_cleanup(struct igb_adapter *adapter)
1514 {
1515         struct e1000_hw *hw = &adapter->hw;
1516         u32 rctl;
1517         u16 phy_reg;
1518
1519         rctl = rd32(E1000_RCTL);
1520         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1521         wr32(E1000_RCTL, rctl);
1522
1523         hw->mac.autoneg = true;
1524         igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1525         if (phy_reg & MII_CR_LOOPBACK) {
1526                 phy_reg &= ~MII_CR_LOOPBACK;
1527                 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
1528                 igb_phy_sw_reset(hw);
1529         }
1530 }
1531
1532 static void igb_create_lbtest_frame(struct sk_buff *skb,
1533                                     unsigned int frame_size)
1534 {
1535         memset(skb->data, 0xFF, frame_size);
1536         frame_size &= ~1;
1537         memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1538         memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1539         memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1540 }
1541
1542 static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1543 {
1544         frame_size &= ~1;
1545         if (*(skb->data + 3) == 0xFF)
1546                 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1547                    (*(skb->data + frame_size / 2 + 12) == 0xAF))
1548                         return 0;
1549         return 13;
1550 }
1551
1552 static int igb_run_loopback_test(struct igb_adapter *adapter)
1553 {
1554         struct e1000_hw *hw = &adapter->hw;
1555         struct igb_ring *tx_ring = &adapter->test_tx_ring;
1556         struct igb_ring *rx_ring = &adapter->test_rx_ring;
1557         struct pci_dev *pdev = adapter->pdev;
1558         int i, j, k, l, lc, good_cnt;
1559         int ret_val = 0;
1560         unsigned long time;
1561
1562         wr32(E1000_RDT(0), rx_ring->count - 1);
1563
1564         /* Calculate the loop count based on the largest descriptor ring
1565          * The idea is to wrap the largest ring a number of times using 64
1566          * send/receive pairs during each loop
1567          */
1568
1569         if (rx_ring->count <= tx_ring->count)
1570                 lc = ((tx_ring->count / 64) * 2) + 1;
1571         else
1572                 lc = ((rx_ring->count / 64) * 2) + 1;
1573
1574         k = l = 0;
1575         for (j = 0; j <= lc; j++) { /* loop count loop */
1576                 for (i = 0; i < 64; i++) { /* send the packets */
1577                         igb_create_lbtest_frame(tx_ring->buffer_info[k].skb,
1578                                                 1024);
1579                         pci_dma_sync_single_for_device(pdev,
1580                                 tx_ring->buffer_info[k].dma,
1581                                 tx_ring->buffer_info[k].length,
1582                                 PCI_DMA_TODEVICE);
1583                         k++;
1584                         if (k == tx_ring->count)
1585                                 k = 0;
1586                 }
1587                 wr32(E1000_TDT(0), k);
1588                 msleep(200);
1589                 time = jiffies; /* set the start time for the receive */
1590                 good_cnt = 0;
1591                 do { /* receive the sent packets */
1592                         pci_dma_sync_single_for_cpu(pdev,
1593                                         rx_ring->buffer_info[l].dma,
1594                                         IGB_RXBUFFER_2048,
1595                                         PCI_DMA_FROMDEVICE);
1596
1597                         ret_val = igb_check_lbtest_frame(
1598                                              rx_ring->buffer_info[l].skb, 1024);
1599                         if (!ret_val)
1600                                 good_cnt++;
1601                         l++;
1602                         if (l == rx_ring->count)
1603                                 l = 0;
1604                         /* time + 20 msecs (200 msecs on 2.4) is more than
1605                          * enough time to complete the receives, if it's
1606                          * exceeded, break and error off
1607                          */
1608                 } while (good_cnt < 64 && jiffies < (time + 20));
1609                 if (good_cnt != 64) {
1610                         ret_val = 13; /* ret_val is the same as mis-compare */
1611                         break;
1612                 }
1613                 if (jiffies >= (time + 20)) {
1614                         ret_val = 14; /* error code for time out error */
1615                         break;
1616                 }
1617         } /* end loop count loop */
1618         return ret_val;
1619 }
1620
1621 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1622 {
1623         /* PHY loopback cannot be performed if SoL/IDER
1624          * sessions are active */
1625         if (igb_check_reset_block(&adapter->hw)) {
1626                 dev_err(&adapter->pdev->dev,
1627                         "Cannot do PHY loopback test "
1628                         "when SoL/IDER is active.\n");
1629                 *data = 0;
1630                 goto out;
1631         }
1632         *data = igb_setup_desc_rings(adapter);
1633         if (*data)
1634                 goto out;
1635         *data = igb_setup_loopback_test(adapter);
1636         if (*data)
1637                 goto err_loopback;
1638         *data = igb_run_loopback_test(adapter);
1639         igb_loopback_cleanup(adapter);
1640
1641 err_loopback:
1642         igb_free_desc_rings(adapter);
1643 out:
1644         return *data;
1645 }
1646
1647 static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1648 {
1649         struct e1000_hw *hw = &adapter->hw;
1650         *data = 0;
1651         if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1652                 int i = 0;
1653                 hw->mac.serdes_has_link = false;
1654
1655                 /* On some blade server designs, link establishment
1656                  * could take as long as 2-3 minutes */
1657                 do {
1658                         hw->mac.ops.check_for_link(&adapter->hw);
1659                         if (hw->mac.serdes_has_link)
1660                                 return *data;
1661                         msleep(20);
1662                 } while (i++ < 3750);
1663
1664                 *data = 1;
1665         } else {
1666                 hw->mac.ops.check_for_link(&adapter->hw);
1667                 if (hw->mac.autoneg)
1668                         msleep(4000);
1669
1670                 if (!(rd32(E1000_STATUS) &
1671                       E1000_STATUS_LU))
1672                         *data = 1;
1673         }
1674         return *data;
1675 }
1676
1677 static void igb_diag_test(struct net_device *netdev,
1678                           struct ethtool_test *eth_test, u64 *data)
1679 {
1680         struct igb_adapter *adapter = netdev_priv(netdev);
1681         u16 autoneg_advertised;
1682         u8 forced_speed_duplex, autoneg;
1683         bool if_running = netif_running(netdev);
1684
1685         set_bit(__IGB_TESTING, &adapter->state);
1686         if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1687                 /* Offline tests */
1688
1689                 /* save speed, duplex, autoneg settings */
1690                 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1691                 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1692                 autoneg = adapter->hw.mac.autoneg;
1693
1694                 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1695
1696                 /* Link test performed before hardware reset so autoneg doesn't
1697                  * interfere with test result */
1698                 if (igb_link_test(adapter, &data[4]))
1699                         eth_test->flags |= ETH_TEST_FL_FAILED;
1700
1701                 if (if_running)
1702                         /* indicate we're in test mode */
1703                         dev_close(netdev);
1704                 else
1705                         igb_reset(adapter);
1706
1707                 if (igb_reg_test(adapter, &data[0]))
1708                         eth_test->flags |= ETH_TEST_FL_FAILED;
1709
1710                 igb_reset(adapter);
1711                 if (igb_eeprom_test(adapter, &data[1]))
1712                         eth_test->flags |= ETH_TEST_FL_FAILED;
1713
1714                 igb_reset(adapter);
1715                 if (igb_intr_test(adapter, &data[2]))
1716                         eth_test->flags |= ETH_TEST_FL_FAILED;
1717
1718                 igb_reset(adapter);
1719                 if (igb_loopback_test(adapter, &data[3]))
1720                         eth_test->flags |= ETH_TEST_FL_FAILED;
1721
1722                 /* restore speed, duplex, autoneg settings */
1723                 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
1724                 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
1725                 adapter->hw.mac.autoneg = autoneg;
1726
1727                 /* force this routine to wait until autoneg complete/timeout */
1728                 adapter->hw.phy.autoneg_wait_to_complete = true;
1729                 igb_reset(adapter);
1730                 adapter->hw.phy.autoneg_wait_to_complete = false;
1731
1732                 clear_bit(__IGB_TESTING, &adapter->state);
1733                 if (if_running)
1734                         dev_open(netdev);
1735         } else {
1736                 dev_info(&adapter->pdev->dev, "online testing starting\n");
1737                 /* Online tests */
1738                 if (igb_link_test(adapter, &data[4]))
1739                         eth_test->flags |= ETH_TEST_FL_FAILED;
1740
1741                 /* Online tests aren't run; pass by default */
1742                 data[0] = 0;
1743                 data[1] = 0;
1744                 data[2] = 0;
1745                 data[3] = 0;
1746
1747                 clear_bit(__IGB_TESTING, &adapter->state);
1748         }
1749         msleep_interruptible(4 * 1000);
1750 }
1751
1752 static int igb_wol_exclusion(struct igb_adapter *adapter,
1753                              struct ethtool_wolinfo *wol)
1754 {
1755         struct e1000_hw *hw = &adapter->hw;
1756         int retval = 1; /* fail by default */
1757
1758         switch (hw->device_id) {
1759         case E1000_DEV_ID_82575GB_QUAD_COPPER:
1760                 /* WoL not supported */
1761                 wol->supported = 0;
1762                 break;
1763         case E1000_DEV_ID_82575EB_FIBER_SERDES:
1764         case E1000_DEV_ID_82576_FIBER:
1765         case E1000_DEV_ID_82576_SERDES:
1766                 /* Wake events not supported on port B */
1767                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {
1768                         wol->supported = 0;
1769                         break;
1770                 }
1771                 /* return success for non excluded adapter ports */
1772                 retval = 0;
1773                 break;
1774         case E1000_DEV_ID_82576_QUAD_COPPER:
1775                 /* quad port adapters only support WoL on port A */
1776                 if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) {
1777                         wol->supported = 0;
1778                         break;
1779                 }
1780                 /* return success for non excluded adapter ports */
1781                 retval = 0;
1782                 break;
1783         default:
1784                 /* dual port cards only support WoL on port A from now on
1785                  * unless it was enabled in the eeprom for port B
1786                  * so exclude FUNC_1 ports from having WoL enabled */
1787                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1 &&
1788                     !adapter->eeprom_wol) {
1789                         wol->supported = 0;
1790                         break;
1791                 }
1792
1793                 retval = 0;
1794         }
1795
1796         return retval;
1797 }
1798
1799 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1800 {
1801         struct igb_adapter *adapter = netdev_priv(netdev);
1802
1803         wol->supported = WAKE_UCAST | WAKE_MCAST |
1804                          WAKE_BCAST | WAKE_MAGIC;
1805         wol->wolopts = 0;
1806
1807         /* this function will set ->supported = 0 and return 1 if wol is not
1808          * supported by this hardware */
1809         if (igb_wol_exclusion(adapter, wol) ||
1810             !device_can_wakeup(&adapter->pdev->dev))
1811                 return;
1812
1813         /* apply any specific unsupported masks here */
1814         switch (adapter->hw.device_id) {
1815         default:
1816                 break;
1817         }
1818
1819         if (adapter->wol & E1000_WUFC_EX)
1820                 wol->wolopts |= WAKE_UCAST;
1821         if (adapter->wol & E1000_WUFC_MC)
1822                 wol->wolopts |= WAKE_MCAST;
1823         if (adapter->wol & E1000_WUFC_BC)
1824                 wol->wolopts |= WAKE_BCAST;
1825         if (adapter->wol & E1000_WUFC_MAG)
1826                 wol->wolopts |= WAKE_MAGIC;
1827
1828         return;
1829 }
1830
1831 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1832 {
1833         struct igb_adapter *adapter = netdev_priv(netdev);
1834         struct e1000_hw *hw = &adapter->hw;
1835
1836         if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1837                 return -EOPNOTSUPP;
1838
1839         if (igb_wol_exclusion(adapter, wol) ||
1840             !device_can_wakeup(&adapter->pdev->dev))
1841                 return wol->wolopts ? -EOPNOTSUPP : 0;
1842
1843         switch (hw->device_id) {
1844         default:
1845                 break;
1846         }
1847
1848         /* these settings will always override what we currently have */
1849         adapter->wol = 0;
1850
1851         if (wol->wolopts & WAKE_UCAST)
1852                 adapter->wol |= E1000_WUFC_EX;
1853         if (wol->wolopts & WAKE_MCAST)
1854                 adapter->wol |= E1000_WUFC_MC;
1855         if (wol->wolopts & WAKE_BCAST)
1856                 adapter->wol |= E1000_WUFC_BC;
1857         if (wol->wolopts & WAKE_MAGIC)
1858                 adapter->wol |= E1000_WUFC_MAG;
1859
1860         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1861
1862         return 0;
1863 }
1864
1865 /* bit defines for adapter->led_status */
1866 #define IGB_LED_ON              0
1867
1868 static int igb_phys_id(struct net_device *netdev, u32 data)
1869 {
1870         struct igb_adapter *adapter = netdev_priv(netdev);
1871         struct e1000_hw *hw = &adapter->hw;
1872
1873         if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
1874                 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
1875
1876         igb_blink_led(hw);
1877         msleep_interruptible(data * 1000);
1878
1879         igb_led_off(hw);
1880         clear_bit(IGB_LED_ON, &adapter->led_status);
1881         igb_cleanup_led(hw);
1882
1883         return 0;
1884 }
1885
1886 static int igb_set_coalesce(struct net_device *netdev,
1887                             struct ethtool_coalesce *ec)
1888 {
1889         struct igb_adapter *adapter = netdev_priv(netdev);
1890         struct e1000_hw *hw = &adapter->hw;
1891         int i;
1892
1893         if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1894             ((ec->rx_coalesce_usecs > 3) &&
1895              (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1896             (ec->rx_coalesce_usecs == 2))
1897                 return -EINVAL;
1898
1899         /* convert to rate of irq's per second */
1900         if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3) {
1901                 adapter->itr_setting = ec->rx_coalesce_usecs;
1902                 adapter->itr = IGB_START_ITR;
1903         } else {
1904                 adapter->itr_setting = ec->rx_coalesce_usecs << 2;
1905                 adapter->itr = adapter->itr_setting;
1906         }
1907
1908         for (i = 0; i < adapter->num_rx_queues; i++)
1909                 wr32(adapter->rx_ring[i].itr_register, adapter->itr);
1910
1911         return 0;
1912 }
1913
1914 static int igb_get_coalesce(struct net_device *netdev,
1915                             struct ethtool_coalesce *ec)
1916 {
1917         struct igb_adapter *adapter = netdev_priv(netdev);
1918
1919         if (adapter->itr_setting <= 3)
1920                 ec->rx_coalesce_usecs = adapter->itr_setting;
1921         else
1922                 ec->rx_coalesce_usecs = adapter->itr_setting >> 2;
1923
1924         return 0;
1925 }
1926
1927
1928 static int igb_nway_reset(struct net_device *netdev)
1929 {
1930         struct igb_adapter *adapter = netdev_priv(netdev);
1931         if (netif_running(netdev))
1932                 igb_reinit_locked(adapter);
1933         return 0;
1934 }
1935
1936 static int igb_get_sset_count(struct net_device *netdev, int sset)
1937 {
1938         switch (sset) {
1939         case ETH_SS_STATS:
1940                 return IGB_STATS_LEN;
1941         case ETH_SS_TEST:
1942                 return IGB_TEST_LEN;
1943         default:
1944                 return -ENOTSUPP;
1945         }
1946 }
1947
1948 static void igb_get_ethtool_stats(struct net_device *netdev,
1949                                   struct ethtool_stats *stats, u64 *data)
1950 {
1951         struct igb_adapter *adapter = netdev_priv(netdev);
1952         u64 *queue_stat;
1953         int stat_count = sizeof(struct igb_queue_stats) / sizeof(u64);
1954         int j;
1955         int i;
1956
1957         igb_update_stats(adapter);
1958         for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
1959                 char *p = (char *)adapter+igb_gstrings_stats[i].stat_offset;
1960                 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
1961                         sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1962         }
1963         for (j = 0; j < adapter->num_tx_queues; j++) {
1964                 int k;
1965                 queue_stat = (u64 *)&adapter->tx_ring[j].tx_stats;
1966                 for (k = 0; k < stat_count; k++)
1967                         data[i + k] = queue_stat[k];
1968                 i += k;
1969         }
1970         for (j = 0; j < adapter->num_rx_queues; j++) {
1971                 int k;
1972                 queue_stat = (u64 *)&adapter->rx_ring[j].rx_stats;
1973                 for (k = 0; k < stat_count; k++)
1974                         data[i + k] = queue_stat[k];
1975                 i += k;
1976         }
1977 }
1978
1979 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
1980 {
1981         struct igb_adapter *adapter = netdev_priv(netdev);
1982         u8 *p = data;
1983         int i;
1984
1985         switch (stringset) {
1986         case ETH_SS_TEST:
1987                 memcpy(data, *igb_gstrings_test,
1988                         IGB_TEST_LEN*ETH_GSTRING_LEN);
1989                 break;
1990         case ETH_SS_STATS:
1991                 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
1992                         memcpy(p, igb_gstrings_stats[i].stat_string,
1993                                ETH_GSTRING_LEN);
1994                         p += ETH_GSTRING_LEN;
1995                 }
1996                 for (i = 0; i < adapter->num_tx_queues; i++) {
1997                         sprintf(p, "tx_queue_%u_packets", i);
1998                         p += ETH_GSTRING_LEN;
1999                         sprintf(p, "tx_queue_%u_bytes", i);
2000                         p += ETH_GSTRING_LEN;
2001                 }
2002                 for (i = 0; i < adapter->num_rx_queues; i++) {
2003                         sprintf(p, "rx_queue_%u_packets", i);
2004                         p += ETH_GSTRING_LEN;
2005                         sprintf(p, "rx_queue_%u_bytes", i);
2006                         p += ETH_GSTRING_LEN;
2007                 }
2008 /*              BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2009                 break;
2010         }
2011 }
2012
2013 static struct ethtool_ops igb_ethtool_ops = {
2014         .get_settings           = igb_get_settings,
2015         .set_settings           = igb_set_settings,
2016         .get_drvinfo            = igb_get_drvinfo,
2017         .get_regs_len           = igb_get_regs_len,
2018         .get_regs               = igb_get_regs,
2019         .get_wol                = igb_get_wol,
2020         .set_wol                = igb_set_wol,
2021         .get_msglevel           = igb_get_msglevel,
2022         .set_msglevel           = igb_set_msglevel,
2023         .nway_reset             = igb_nway_reset,
2024         .get_link               = ethtool_op_get_link,
2025         .get_eeprom_len         = igb_get_eeprom_len,
2026         .get_eeprom             = igb_get_eeprom,
2027         .set_eeprom             = igb_set_eeprom,
2028         .get_ringparam          = igb_get_ringparam,
2029         .set_ringparam          = igb_set_ringparam,
2030         .get_pauseparam         = igb_get_pauseparam,
2031         .set_pauseparam         = igb_set_pauseparam,
2032         .get_rx_csum            = igb_get_rx_csum,
2033         .set_rx_csum            = igb_set_rx_csum,
2034         .get_tx_csum            = igb_get_tx_csum,
2035         .set_tx_csum            = igb_set_tx_csum,
2036         .get_sg                 = ethtool_op_get_sg,
2037         .set_sg                 = ethtool_op_set_sg,
2038         .get_tso                = ethtool_op_get_tso,
2039         .set_tso                = igb_set_tso,
2040         .self_test              = igb_diag_test,
2041         .get_strings            = igb_get_strings,
2042         .phys_id                = igb_phys_id,
2043         .get_sset_count         = igb_get_sset_count,
2044         .get_ethtool_stats      = igb_get_ethtool_stats,
2045         .get_coalesce           = igb_get_coalesce,
2046         .set_coalesce           = igb_set_coalesce,
2047 };
2048
2049 void igb_set_ethtool_ops(struct net_device *netdev)
2050 {
2051         SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
2052 }