drivers/net/igb/e1000_hw.h

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #ifndef _E1000_HW_H_
  29 #define _E1000_HW_H_
  30
  31 #include <linux/types.h>
  32 #include <linux/delay.h>
  33 #include <linux/io.h>
  34
  35 #include "e1000_mac.h"
  36 #include "e1000_regs.h"
  37 #include "e1000_defines.h"
  38
  39 struct e1000_hw;
  40
  41 #define E1000_DEV_ID_82575EB_COPPER           0x10A7
  42 #define E1000_DEV_ID_82575EB_FIBER_SERDES     0x10A9
  43 #define E1000_DEV_ID_82575GB_QUAD_COPPER      0x10D6
  44
  45 #define E1000_REVISION_2 2
  46 #define E1000_REVISION_4 4
  47
  48 #define E1000_FUNC_1     1
  49
  50 enum e1000_mac_type {
  51         e1000_undefined = 0,
  52         e1000_82575,
  53         e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
  54 };
  55
  56 enum e1000_media_type {
  57         e1000_media_type_unknown = 0,
  58         e1000_media_type_copper = 1,
  59         e1000_media_type_fiber = 2,
  60         e1000_media_type_internal_serdes = 3,
  61         e1000_num_media_types
  62 };
  63
  64 enum e1000_nvm_type {
  65         e1000_nvm_unknown = 0,
  66         e1000_nvm_none,
  67         e1000_nvm_eeprom_spi,
  68         e1000_nvm_eeprom_microwire,
  69         e1000_nvm_flash_hw,
  70         e1000_nvm_flash_sw
  71 };
  72
  73 enum e1000_nvm_override {
  74         e1000_nvm_override_none = 0,
  75         e1000_nvm_override_spi_small,
  76         e1000_nvm_override_spi_large,
  77         e1000_nvm_override_microwire_small,
  78         e1000_nvm_override_microwire_large
  79 };
  80
  81 enum e1000_phy_type {
  82         e1000_phy_unknown = 0,
  83         e1000_phy_none,
  84         e1000_phy_m88,
  85         e1000_phy_igp,
  86         e1000_phy_igp_2,
  87         e1000_phy_gg82563,
  88         e1000_phy_igp_3,
  89         e1000_phy_ife,
  90 };
  91
  92 enum e1000_bus_type {
  93         e1000_bus_type_unknown = 0,
  94         e1000_bus_type_pci,
  95         e1000_bus_type_pcix,
  96         e1000_bus_type_pci_express,
  97         e1000_bus_type_reserved
  98 };
  99
 100 enum e1000_bus_speed {
 101         e1000_bus_speed_unknown = 0,
 102         e1000_bus_speed_33,
 103         e1000_bus_speed_66,
 104         e1000_bus_speed_100,
 105         e1000_bus_speed_120,
 106         e1000_bus_speed_133,
 107         e1000_bus_speed_2500,
 108         e1000_bus_speed_5000,
 109         e1000_bus_speed_reserved
 110 };
 111
 112 enum e1000_bus_width {
 113         e1000_bus_width_unknown = 0,
 114         e1000_bus_width_pcie_x1,
 115         e1000_bus_width_pcie_x2,
 116         e1000_bus_width_pcie_x4 = 4,
 117         e1000_bus_width_pcie_x8 = 8,
 118         e1000_bus_width_32,
 119         e1000_bus_width_64,
 120         e1000_bus_width_reserved
 121 };
 122
 123 enum e1000_1000t_rx_status {
 124         e1000_1000t_rx_status_not_ok = 0,
 125         e1000_1000t_rx_status_ok,
 126         e1000_1000t_rx_status_undefined = 0xFF
 127 };
 128
 129 enum e1000_rev_polarity {
 130         e1000_rev_polarity_normal = 0,
 131         e1000_rev_polarity_reversed,
 132         e1000_rev_polarity_undefined = 0xFF
 133 };
 134
 135 enum e1000_fc_type {
 136         e1000_fc_none = 0,
 137         e1000_fc_rx_pause,
 138         e1000_fc_tx_pause,
 139         e1000_fc_full,
 140         e1000_fc_default = 0xFF
 141 };
 142
 143
 144 /* Receive Descriptor */
 145 struct e1000_rx_desc {
 146         u64 buffer_addr; /* Address of the descriptor's data buffer */
 147         u16 length;      /* Length of data DMAed into data buffer */
 148         u16 csum;        /* Packet checksum */
 149         u8  status;      /* Descriptor status */
 150         u8  errors;      /* Descriptor Errors */
 151         u16 special;
 152 };
 153
 154 /* Receive Descriptor - Extended */
 155 union e1000_rx_desc_extended {
 156         struct {
 157                 u64 buffer_addr;
 158                 u64 reserved;
 159         } read;
 160         struct {
 161                 struct {
 162                         u32 mrq;              /* Multiple Rx Queues */
 163                         union {
 164                                 u32 rss;            /* RSS Hash */
 165                                 struct {
 166                                         u16 ip_id;  /* IP id */
 167                                         u16 csum;   /* Packet Checksum */
 168                                 } csum_ip;
 169                         } hi_dword;
 170                 } lower;
 171                 struct {
 172                         u32 status_error;     /* ext status/error */
 173                         u16 length;
 174                         u16 vlan;             /* VLAN tag */
 175                 } upper;
 176         } wb;  /* writeback */
 177 };
 178
 179 #define MAX_PS_BUFFERS 4
 180 /* Receive Descriptor - Packet Split */
 181 union e1000_rx_desc_packet_split {
 182         struct {
 183                 /* one buffer for protocol header(s), three data buffers */
 184                 u64 buffer_addr[MAX_PS_BUFFERS];
 185         } read;
 186         struct {
 187                 struct {
 188                         u32 mrq;              /* Multiple Rx Queues */
 189                         union {
 190                                 u32 rss;              /* RSS Hash */
 191                                 struct {
 192                                         u16 ip_id;    /* IP id */
 193                                         u16 csum;     /* Packet Checksum */
 194                                 } csum_ip;
 195                         } hi_dword;
 196                 } lower;
 197                 struct {
 198                         u32 status_error;     /* ext status/error */
 199                         u16 length0;          /* length of buffer 0 */
 200                         u16 vlan;             /* VLAN tag */
 201                 } middle;
 202                 struct {
 203                         u16 header_status;
 204                         u16 length[3];        /* length of buffers 1-3 */
 205                 } upper;
 206                 u64 reserved;
 207         } wb; /* writeback */
 208 };
 209
 210 /* Transmit Descriptor */
 211 struct e1000_tx_desc {
 212         u64 buffer_addr;      /* Address of the descriptor's data buffer */
 213         union {
 214                 u32 data;
 215                 struct {
 216                         u16 length;    /* Data buffer length */
 217                         u8 cso;        /* Checksum offset */
 218                         u8 cmd;        /* Descriptor control */
 219                 } flags;
 220         } lower;
 221         union {
 222                 u32 data;
 223                 struct {
 224                         u8 status;     /* Descriptor status */
 225                         u8 css;        /* Checksum start */
 226                         u16 special;
 227                 } fields;
 228         } upper;
 229 };
 230
 231 /* Offload Context Descriptor */
 232 struct e1000_context_desc {
 233         union {
 234                 u32 ip_config;
 235                 struct {
 236                         u8 ipcss;      /* IP checksum start */
 237                         u8 ipcso;      /* IP checksum offset */
 238                         u16 ipcse;     /* IP checksum end */
 239                 } ip_fields;
 240         } lower_setup;
 241         union {
 242                 u32 tcp_config;
 243                 struct {
 244                         u8 tucss;      /* TCP checksum start */
 245                         u8 tucso;      /* TCP checksum offset */
 246                         u16 tucse;     /* TCP checksum end */
 247                 } tcp_fields;
 248         } upper_setup;
 249         u32 cmd_and_length;
 250         union {
 251                 u32 data;
 252                 struct {
 253                         u8 status;     /* Descriptor status */
 254                         u8 hdr_len;    /* Header length */
 255                         u16 mss;       /* Maximum segment size */
 256                 } fields;
 257         } tcp_seg_setup;
 258 };
 259
 260 /* Offload data descriptor */
 261 struct e1000_data_desc {
 262         u64 buffer_addr;   /* Address of the descriptor's buffer address */
 263         union {
 264                 u32 data;
 265                 struct {
 266                         u16 length;    /* Data buffer length */
 267                         u8 typ_len_ext;
 268                         u8 cmd;
 269                 } flags;
 270         } lower;
 271         union {
 272                 u32 data;
 273                 struct {
 274                         u8 status;     /* Descriptor status */
 275                         u8 popts;      /* Packet Options */
 276                         u16 special;
 277                 } fields;
 278         } upper;
 279 };
 280
 281 /* Statistics counters collected by the MAC */
 282 struct e1000_hw_stats {
 283         u64 crcerrs;
 284         u64 algnerrc;
 285         u64 symerrs;
 286         u64 rxerrc;
 287         u64 mpc;
 288         u64 scc;
 289         u64 ecol;
 290         u64 mcc;
 291         u64 latecol;
 292         u64 colc;
 293         u64 dc;
 294         u64 tncrs;
 295         u64 sec;
 296         u64 cexterr;
 297         u64 rlec;
 298         u64 xonrxc;
 299         u64 xontxc;
 300         u64 xoffrxc;
 301         u64 xofftxc;
 302         u64 fcruc;
 303         u64 prc64;
 304         u64 prc127;
 305         u64 prc255;
 306         u64 prc511;
 307         u64 prc1023;
 308         u64 prc1522;
 309         u64 gprc;
 310         u64 bprc;
 311         u64 mprc;
 312         u64 gptc;
 313         u64 gorc;
 314         u64 gotc;
 315         u64 rnbc;
 316         u64 ruc;
 317         u64 rfc;
 318         u64 roc;
 319         u64 rjc;
 320         u64 mgprc;
 321         u64 mgpdc;
 322         u64 mgptc;
 323         u64 tor;
 324         u64 tot;
 325         u64 tpr;
 326         u64 tpt;
 327         u64 ptc64;
 328         u64 ptc127;
 329         u64 ptc255;
 330         u64 ptc511;
 331         u64 ptc1023;
 332         u64 ptc1522;
 333         u64 mptc;
 334         u64 bptc;
 335         u64 tsctc;
 336         u64 tsctfc;
 337         u64 iac;
 338         u64 icrxptc;
 339         u64 icrxatc;
 340         u64 ictxptc;
 341         u64 ictxatc;
 342         u64 ictxqec;
 343         u64 ictxqmtc;
 344         u64 icrxdmtc;
 345         u64 icrxoc;
 346         u64 cbtmpc;
 347         u64 htdpmc;
 348         u64 cbrdpc;
 349         u64 cbrmpc;
 350         u64 rpthc;
 351         u64 hgptc;
 352         u64 htcbdpc;
 353         u64 hgorc;
 354         u64 hgotc;
 355         u64 lenerrs;
 356         u64 scvpc;
 357         u64 hrmpc;
 358 };
 359
 360 struct e1000_phy_stats {
 361         u32 idle_errors;
 362         u32 receive_errors;
 363 };
 364
 365 struct e1000_host_mng_dhcp_cookie {
 366         u32 signature;
 367         u8  status;
 368         u8  reserved0;
 369         u16 vlan_id;
 370         u32 reserved1;
 371         u16 reserved2;
 372         u8  reserved3;
 373         u8  checksum;
 374 };
 375
 376 /* Host Interface "Rev 1" */
 377 struct e1000_host_command_header {
 378         u8 command_id;
 379         u8 command_length;
 380         u8 command_options;
 381         u8 checksum;
 382 };
 383
 384 #define E1000_HI_MAX_DATA_LENGTH     252
 385 struct e1000_host_command_info {
 386         struct e1000_host_command_header command_header;
 387         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 388 };
 389
 390 /* Host Interface "Rev 2" */
 391 struct e1000_host_mng_command_header {
 392         u8  command_id;
 393         u8  checksum;
 394         u16 reserved1;
 395         u16 reserved2;
 396         u16 command_length;
 397 };
 398
 399 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
 400 struct e1000_host_mng_command_info {
 401         struct e1000_host_mng_command_header command_header;
 402         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 403 };
 404
 405 #include "e1000_mac.h"
 406 #include "e1000_phy.h"
 407 #include "e1000_nvm.h"
 408
 409 struct e1000_mac_operations {
 410         s32  (*check_for_link)(struct e1000_hw *);
 411         s32  (*reset_hw)(struct e1000_hw *);
 412         s32  (*init_hw)(struct e1000_hw *);
 413         s32  (*setup_physical_interface)(struct e1000_hw *);
 414         void (*rar_set)(struct e1000_hw *, u8 *, u32);
 415         s32  (*read_mac_addr)(struct e1000_hw *);
 416         s32  (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *);
 417 };
 418
 419 struct e1000_phy_operations {
 420         s32  (*acquire_phy)(struct e1000_hw *);
 421         s32  (*force_speed_duplex)(struct e1000_hw *);
 422         s32  (*get_cfg_done)(struct e1000_hw *hw);
 423         s32  (*get_cable_length)(struct e1000_hw *);
 424         s32  (*get_phy_info)(struct e1000_hw *);
 425         s32  (*read_phy_reg)(struct e1000_hw *, u32, u16 *);
 426         void (*release_phy)(struct e1000_hw *);
 427         s32  (*reset_phy)(struct e1000_hw *);
 428         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 429         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 430         s32  (*write_phy_reg)(struct e1000_hw *, u32, u16);
 431 };
 432
 433 struct e1000_nvm_operations {
 434         s32  (*acquire_nvm)(struct e1000_hw *);
 435         s32  (*read_nvm)(struct e1000_hw *, u16, u16, u16 *);
 436         void (*release_nvm)(struct e1000_hw *);
 437         s32  (*write_nvm)(struct e1000_hw *, u16, u16, u16 *);
 438 };
 439
 440 struct e1000_info {
 441         s32 (*get_invariants)(struct e1000_hw *);
 442         struct e1000_mac_operations *mac_ops;
 443         struct e1000_phy_operations *phy_ops;
 444         struct e1000_nvm_operations *nvm_ops;
 445 };
 446
 447 extern const struct e1000_info e1000_82575_info;
 448
 449 struct e1000_mac_info {
 450         struct e1000_mac_operations ops;
 451
 452         u8 addr[6];
 453         u8 perm_addr[6];
 454
 455         enum e1000_mac_type type;
 456
 457         u32 collision_delta;
 458         u32 ledctl_default;
 459         u32 ledctl_mode1;
 460         u32 ledctl_mode2;
 461         u32 mc_filter_type;
 462         u32 tx_packet_delta;
 463         u32 txcw;
 464
 465         u16 current_ifs_val;
 466         u16 ifs_max_val;
 467         u16 ifs_min_val;
 468         u16 ifs_ratio;
 469         u16 ifs_step_size;
 470         u16 mta_reg_count;
 471         u16 rar_entry_count;
 472
 473         u8  forced_speed_duplex;
 474
 475         bool adaptive_ifs;
 476         bool arc_subsystem_valid;
 477         bool asf_firmware_present;
 478         bool autoneg;
 479         bool autoneg_failed;
 480         bool disable_av;
 481         bool disable_hw_init_bits;
 482         bool get_link_status;
 483         bool ifs_params_forced;
 484         bool in_ifs_mode;
 485         bool report_tx_early;
 486         bool serdes_has_link;
 487         bool tx_pkt_filtering;
 488 };
 489
 490 struct e1000_phy_info {
 491         struct e1000_phy_operations ops;
 492
 493         enum e1000_phy_type type;
 494
 495         enum e1000_1000t_rx_status local_rx;
 496         enum e1000_1000t_rx_status remote_rx;
 497         enum e1000_ms_type ms_type;
 498         enum e1000_ms_type original_ms_type;
 499         enum e1000_rev_polarity cable_polarity;
 500         enum e1000_smart_speed smart_speed;
 501
 502         u32 addr;
 503         u32 id;
 504         u32 reset_delay_us; /* in usec */
 505         u32 revision;
 506
 507         enum e1000_media_type media_type;
 508
 509         u16 autoneg_advertised;
 510         u16 autoneg_mask;
 511         u16 cable_length;
 512         u16 max_cable_length;
 513         u16 min_cable_length;
 514
 515         u8 mdix;
 516
 517         bool disable_polarity_correction;
 518         bool is_mdix;
 519         bool polarity_correction;
 520         bool reset_disable;
 521         bool speed_downgraded;
 522         bool autoneg_wait_to_complete;
 523 };
 524
 525 struct e1000_nvm_info {
 526         struct e1000_nvm_operations ops;
 527
 528         enum e1000_nvm_type type;
 529         enum e1000_nvm_override override;
 530
 531         u32 flash_bank_size;
 532         u32 flash_base_addr;
 533
 534         u16 word_size;
 535         u16 delay_usec;
 536         u16 address_bits;
 537         u16 opcode_bits;
 538         u16 page_size;
 539 };
 540
 541 struct e1000_bus_info {
 542         enum e1000_bus_type type;
 543         enum e1000_bus_speed speed;
 544         enum e1000_bus_width width;
 545
 546         u32 snoop;
 547
 548         u16 func;
 549         u16 pci_cmd_word;
 550 };
 551
 552 struct e1000_fc_info {
 553         u32 high_water;     /* Flow control high-water mark */
 554         u32 low_water;      /* Flow control low-water mark */
 555         u16 pause_time;     /* Flow control pause timer */
 556         bool send_xon;      /* Flow control send XON */
 557         bool strict_ieee;   /* Strict IEEE mode */
 558         enum e1000_fc_type type; /* Type of flow control */
 559         enum e1000_fc_type original_type;
 560 };
 561
 562 struct e1000_hw {
 563         void *back;
 564         void *dev_spec;
 565
 566         u8 __iomem *hw_addr;
 567         u8 __iomem *flash_address;
 568         unsigned long io_base;
 569
 570         struct e1000_mac_info  mac;
 571         struct e1000_fc_info   fc;
 572         struct e1000_phy_info  phy;
 573         struct e1000_nvm_info  nvm;
 574         struct e1000_bus_info  bus;
 575         struct e1000_host_mng_dhcp_cookie mng_cookie;
 576
 577         u32 dev_spec_size;
 578
 579         u16 device_id;
 580         u16 subsystem_vendor_id;
 581         u16 subsystem_device_id;
 582         u16 vendor_id;
 583
 584         u8  revision_id;
 585 };
 586
 587 #ifdef DEBUG
 588 extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
 589 #define hw_dbg(hw, format, arg...) \
 590         printk(KERN_DEBUG "%s: " format, igb_get_hw_dev_name(hw), ##arg)
 591 #else
 592 static inline int __attribute__ ((format (printf, 2, 3)))
 593 hw_dbg(struct e1000_hw *hw, const char *format, ...)
 594 {
 595         return 0;
 596 }
 597 #endif
 598
 599 #endif