1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
32 #include <linux/types.h>
33 #include <linux/if_ether.h>
35 #include "e1000_mac.h"
36 #include "e1000_82575.h"
38 static s32 igb_get_invariants_82575(struct e1000_hw *);
39 static s32 igb_acquire_phy_82575(struct e1000_hw *);
40 static void igb_release_phy_82575(struct e1000_hw *);
41 static s32 igb_acquire_nvm_82575(struct e1000_hw *);
42 static void igb_release_nvm_82575(struct e1000_hw *);
43 static s32 igb_check_for_link_82575(struct e1000_hw *);
44 static s32 igb_get_cfg_done_82575(struct e1000_hw *);
45 static s32 igb_init_hw_82575(struct e1000_hw *);
46 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
47 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
48 static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
49 static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
50 static s32 igb_reset_hw_82575(struct e1000_hw *);
51 static s32 igb_reset_hw_82580(struct e1000_hw *);
52 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
53 static s32 igb_setup_copper_link_82575(struct e1000_hw *);
54 static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
55 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
56 static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
57 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
58 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
60 static s32 igb_get_phy_id_82575(struct e1000_hw *);
61 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
62 static bool igb_sgmii_active_82575(struct e1000_hw *);
63 static s32 igb_reset_init_script_82575(struct e1000_hw *);
64 static s32 igb_read_mac_addr_82575(struct e1000_hw *);
65 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
66 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
67 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
68 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw);
69 static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw,
71 static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
73 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
74 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
75 static const u16 e1000_82580_rxpbs_table[] =
76 { 36, 72, 144, 1, 2, 4, 8, 16,
78 #define E1000_82580_RXPBS_TABLE_SIZE \
79 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
82 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
83 * @hw: pointer to the HW structure
85 * Called to determine if the I2C pins are being used for I2C or as an
86 * external MDIO interface since the two options are mutually exclusive.
88 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
91 bool ext_mdio = false;
93 switch (hw->mac.type) {
96 reg = rd32(E1000_MDIC);
97 ext_mdio = !!(reg & E1000_MDIC_DEST);
101 reg = rd32(E1000_MDICNFG);
102 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
110 static s32 igb_get_invariants_82575(struct e1000_hw *hw)
112 struct e1000_phy_info *phy = &hw->phy;
113 struct e1000_nvm_info *nvm = &hw->nvm;
114 struct e1000_mac_info *mac = &hw->mac;
115 struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
121 switch (hw->device_id) {
122 case E1000_DEV_ID_82575EB_COPPER:
123 case E1000_DEV_ID_82575EB_FIBER_SERDES:
124 case E1000_DEV_ID_82575GB_QUAD_COPPER:
125 mac->type = e1000_82575;
127 case E1000_DEV_ID_82576:
128 case E1000_DEV_ID_82576_NS:
129 case E1000_DEV_ID_82576_NS_SERDES:
130 case E1000_DEV_ID_82576_FIBER:
131 case E1000_DEV_ID_82576_SERDES:
132 case E1000_DEV_ID_82576_QUAD_COPPER:
133 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
134 case E1000_DEV_ID_82576_SERDES_QUAD:
135 mac->type = e1000_82576;
137 case E1000_DEV_ID_82580_COPPER:
138 case E1000_DEV_ID_82580_FIBER:
139 case E1000_DEV_ID_82580_QUAD_FIBER:
140 case E1000_DEV_ID_82580_SERDES:
141 case E1000_DEV_ID_82580_SGMII:
142 case E1000_DEV_ID_82580_COPPER_DUAL:
143 case E1000_DEV_ID_DH89XXCC_SGMII:
144 case E1000_DEV_ID_DH89XXCC_SERDES:
145 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
146 case E1000_DEV_ID_DH89XXCC_SFP:
147 mac->type = e1000_82580;
149 case E1000_DEV_ID_I350_COPPER:
150 case E1000_DEV_ID_I350_FIBER:
151 case E1000_DEV_ID_I350_SERDES:
152 case E1000_DEV_ID_I350_SGMII:
153 mac->type = e1000_i350;
156 return -E1000_ERR_MAC_INIT;
162 * The 82575 uses bits 22:23 for link mode. The mode can be changed
163 * based on the EEPROM. We cannot rely upon device ID. There
164 * is no distinguishable difference between fiber and internal
165 * SerDes mode on the 82575. There can be an external PHY attached
166 * on the SGMII interface. For this, we'll set sgmii_active to true.
168 phy->media_type = e1000_media_type_copper;
169 dev_spec->sgmii_active = false;
171 ctrl_ext = rd32(E1000_CTRL_EXT);
172 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
173 case E1000_CTRL_EXT_LINK_MODE_SGMII:
174 dev_spec->sgmii_active = true;
176 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
177 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
178 hw->phy.media_type = e1000_media_type_internal_serdes;
184 /* Set mta register count */
185 mac->mta_reg_count = 128;
186 /* Set rar entry count */
187 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
188 if (mac->type == e1000_82576)
189 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
190 if (mac->type == e1000_82580)
191 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
192 if (mac->type == e1000_i350)
193 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
195 if (mac->type >= e1000_82580)
196 mac->ops.reset_hw = igb_reset_hw_82580;
198 mac->ops.reset_hw = igb_reset_hw_82575;
199 /* Set if part includes ASF firmware */
200 mac->asf_firmware_present = true;
201 /* Set if manageability features are enabled. */
202 mac->arc_subsystem_valid =
203 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
205 /* enable EEE on i350 parts */
206 if (mac->type == e1000_i350)
207 dev_spec->eee_disable = false;
209 dev_spec->eee_disable = true;
210 /* physical interface link setup */
211 mac->ops.setup_physical_interface =
212 (hw->phy.media_type == e1000_media_type_copper)
213 ? igb_setup_copper_link_82575
214 : igb_setup_serdes_link_82575;
216 /* NVM initialization */
217 eecd = rd32(E1000_EECD);
219 nvm->opcode_bits = 8;
221 switch (nvm->override) {
222 case e1000_nvm_override_spi_large:
224 nvm->address_bits = 16;
226 case e1000_nvm_override_spi_small:
228 nvm->address_bits = 8;
231 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
232 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
236 nvm->type = e1000_nvm_eeprom_spi;
238 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
239 E1000_EECD_SIZE_EX_SHIFT);
242 * Added to a constant, "size" becomes the left-shift value
243 * for setting word_size.
245 size += NVM_WORD_SIZE_BASE_SHIFT;
248 * Check for invalid size
250 if ((hw->mac.type == e1000_82576) && (size > 15)) {
251 printk("igb: The NVM size is not valid, "
252 "defaulting to 32K.\n");
255 nvm->word_size = 1 << size;
256 if (nvm->word_size == (1 << 15))
257 nvm->page_size = 128;
259 /* NVM Function Pointers */
260 nvm->ops.acquire = igb_acquire_nvm_82575;
261 if (nvm->word_size < (1 << 15))
262 nvm->ops.read = igb_read_nvm_eerd;
264 nvm->ops.read = igb_read_nvm_spi;
266 nvm->ops.release = igb_release_nvm_82575;
267 switch (hw->mac.type) {
269 nvm->ops.validate = igb_validate_nvm_checksum_82580;
270 nvm->ops.update = igb_update_nvm_checksum_82580;
273 nvm->ops.validate = igb_validate_nvm_checksum_i350;
274 nvm->ops.update = igb_update_nvm_checksum_i350;
277 nvm->ops.validate = igb_validate_nvm_checksum;
278 nvm->ops.update = igb_update_nvm_checksum;
280 nvm->ops.write = igb_write_nvm_spi;
282 /* if part supports SR-IOV then initialize mailbox parameters */
286 igb_init_mbx_params_pf(hw);
292 /* setup PHY parameters */
293 if (phy->media_type != e1000_media_type_copper) {
294 phy->type = e1000_phy_none;
298 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
299 phy->reset_delay_us = 100;
301 ctrl_ext = rd32(E1000_CTRL_EXT);
303 /* PHY function pointers */
304 if (igb_sgmii_active_82575(hw)) {
305 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
306 ctrl_ext |= E1000_CTRL_I2C_ENA;
308 phy->ops.reset = igb_phy_hw_reset;
309 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
312 wr32(E1000_CTRL_EXT, ctrl_ext);
313 igb_reset_mdicnfg_82580(hw);
315 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
316 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
317 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
318 } else if (hw->mac.type >= e1000_82580) {
319 phy->ops.read_reg = igb_read_phy_reg_82580;
320 phy->ops.write_reg = igb_write_phy_reg_82580;
322 phy->ops.read_reg = igb_read_phy_reg_igp;
323 phy->ops.write_reg = igb_write_phy_reg_igp;
327 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
328 E1000_STATUS_FUNC_SHIFT;
330 /* Set phy->phy_addr and phy->id. */
331 ret_val = igb_get_phy_id_82575(hw);
335 /* Verify phy id and set remaining function pointers */
337 case I347AT4_E_PHY_ID:
338 case M88E1112_E_PHY_ID:
339 case M88E1111_I_PHY_ID:
340 phy->type = e1000_phy_m88;
341 phy->ops.get_phy_info = igb_get_phy_info_m88;
343 if (phy->id == I347AT4_E_PHY_ID ||
344 phy->id == M88E1112_E_PHY_ID)
345 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
347 phy->ops.get_cable_length = igb_get_cable_length_m88;
349 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
351 case IGP03E1000_E_PHY_ID:
352 phy->type = e1000_phy_igp_3;
353 phy->ops.get_phy_info = igb_get_phy_info_igp;
354 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
355 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
356 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
357 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
359 case I82580_I_PHY_ID:
361 phy->type = e1000_phy_82580;
362 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_82580;
363 phy->ops.get_cable_length = igb_get_cable_length_82580;
364 phy->ops.get_phy_info = igb_get_phy_info_82580;
367 return -E1000_ERR_PHY;
374 * igb_acquire_phy_82575 - Acquire rights to access PHY
375 * @hw: pointer to the HW structure
377 * Acquire access rights to the correct PHY. This is a
378 * function pointer entry point called by the api module.
380 static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
382 u16 mask = E1000_SWFW_PHY0_SM;
384 if (hw->bus.func == E1000_FUNC_1)
385 mask = E1000_SWFW_PHY1_SM;
386 else if (hw->bus.func == E1000_FUNC_2)
387 mask = E1000_SWFW_PHY2_SM;
388 else if (hw->bus.func == E1000_FUNC_3)
389 mask = E1000_SWFW_PHY3_SM;
391 return igb_acquire_swfw_sync_82575(hw, mask);
395 * igb_release_phy_82575 - Release rights to access PHY
396 * @hw: pointer to the HW structure
398 * A wrapper to release access rights to the correct PHY. This is a
399 * function pointer entry point called by the api module.
401 static void igb_release_phy_82575(struct e1000_hw *hw)
403 u16 mask = E1000_SWFW_PHY0_SM;
405 if (hw->bus.func == E1000_FUNC_1)
406 mask = E1000_SWFW_PHY1_SM;
407 else if (hw->bus.func == E1000_FUNC_2)
408 mask = E1000_SWFW_PHY2_SM;
409 else if (hw->bus.func == E1000_FUNC_3)
410 mask = E1000_SWFW_PHY3_SM;
412 igb_release_swfw_sync_82575(hw, mask);
416 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
417 * @hw: pointer to the HW structure
418 * @offset: register offset to be read
419 * @data: pointer to the read data
421 * Reads the PHY register at offset using the serial gigabit media independent
422 * interface and stores the retrieved information in data.
424 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
427 s32 ret_val = -E1000_ERR_PARAM;
429 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
430 hw_dbg("PHY Address %u is out of range\n", offset);
434 ret_val = hw->phy.ops.acquire(hw);
438 ret_val = igb_read_phy_reg_i2c(hw, offset, data);
440 hw->phy.ops.release(hw);
447 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
448 * @hw: pointer to the HW structure
449 * @offset: register offset to write to
450 * @data: data to write at register offset
452 * Writes the data to PHY register at the offset using the serial gigabit
453 * media independent interface.
455 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
458 s32 ret_val = -E1000_ERR_PARAM;
461 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
462 hw_dbg("PHY Address %d is out of range\n", offset);
466 ret_val = hw->phy.ops.acquire(hw);
470 ret_val = igb_write_phy_reg_i2c(hw, offset, data);
472 hw->phy.ops.release(hw);
479 * igb_get_phy_id_82575 - Retrieve PHY addr and id
480 * @hw: pointer to the HW structure
482 * Retrieves the PHY address and ID for both PHY's which do and do not use
485 static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
487 struct e1000_phy_info *phy = &hw->phy;
494 * For SGMII PHYs, we try the list of possible addresses until
495 * we find one that works. For non-SGMII PHYs
496 * (e.g. integrated copper PHYs), an address of 1 should
497 * work. The result of this function should mean phy->phy_addr
498 * and phy->id are set correctly.
500 if (!(igb_sgmii_active_82575(hw))) {
502 ret_val = igb_get_phy_id(hw);
506 if (igb_sgmii_uses_mdio_82575(hw)) {
507 switch (hw->mac.type) {
510 mdic = rd32(E1000_MDIC);
511 mdic &= E1000_MDIC_PHY_MASK;
512 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
516 mdic = rd32(E1000_MDICNFG);
517 mdic &= E1000_MDICNFG_PHY_MASK;
518 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
521 ret_val = -E1000_ERR_PHY;
525 ret_val = igb_get_phy_id(hw);
529 /* Power on sgmii phy if it is disabled */
530 ctrl_ext = rd32(E1000_CTRL_EXT);
531 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
536 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
537 * Therefore, we need to test 1-7
539 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
540 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
542 hw_dbg("Vendor ID 0x%08X read at address %u\n",
545 * At the time of this writing, The M88 part is
546 * the only supported SGMII PHY product.
548 if (phy_id == M88_VENDOR)
551 hw_dbg("PHY address %u was unreadable\n", phy->addr);
555 /* A valid PHY type couldn't be found. */
556 if (phy->addr == 8) {
558 ret_val = -E1000_ERR_PHY;
561 ret_val = igb_get_phy_id(hw);
564 /* restore previous sfp cage power state */
565 wr32(E1000_CTRL_EXT, ctrl_ext);
572 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
573 * @hw: pointer to the HW structure
575 * Resets the PHY using the serial gigabit media independent interface.
577 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
582 * This isn't a true "hard" reset, but is the only reset
583 * available to us at this time.
586 hw_dbg("Soft resetting SGMII attached PHY...\n");
589 * SFP documentation requires the following to configure the SPF module
590 * to work on SGMII. No further documentation is given.
592 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
596 ret_val = igb_phy_sw_reset(hw);
603 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
604 * @hw: pointer to the HW structure
605 * @active: true to enable LPLU, false to disable
607 * Sets the LPLU D0 state according to the active flag. When
608 * activating LPLU this function also disables smart speed
609 * and vice versa. LPLU will not be activated unless the
610 * device autonegotiation advertisement meets standards of
611 * either 10 or 10/100 or 10/100/1000 at all duplexes.
612 * This is a function pointer entry point only called by
613 * PHY setup routines.
615 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
617 struct e1000_phy_info *phy = &hw->phy;
621 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
626 data |= IGP02E1000_PM_D0_LPLU;
627 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
632 /* When LPLU is enabled, we should disable SmartSpeed */
633 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
635 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
636 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
641 data &= ~IGP02E1000_PM_D0_LPLU;
642 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
645 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
646 * during Dx states where the power conservation is most
647 * important. During driver activity we should enable
648 * SmartSpeed, so performance is maintained.
650 if (phy->smart_speed == e1000_smart_speed_on) {
651 ret_val = phy->ops.read_reg(hw,
652 IGP01E1000_PHY_PORT_CONFIG, &data);
656 data |= IGP01E1000_PSCFR_SMART_SPEED;
657 ret_val = phy->ops.write_reg(hw,
658 IGP01E1000_PHY_PORT_CONFIG, data);
661 } else if (phy->smart_speed == e1000_smart_speed_off) {
662 ret_val = phy->ops.read_reg(hw,
663 IGP01E1000_PHY_PORT_CONFIG, &data);
667 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
668 ret_val = phy->ops.write_reg(hw,
669 IGP01E1000_PHY_PORT_CONFIG, data);
680 * igb_acquire_nvm_82575 - Request for access to EEPROM
681 * @hw: pointer to the HW structure
683 * Acquire the necessary semaphores for exclusive access to the EEPROM.
684 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
685 * Return successful if access grant bit set, else clear the request for
686 * EEPROM access and return -E1000_ERR_NVM (-1).
688 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
692 ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
696 ret_val = igb_acquire_nvm(hw);
699 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
706 * igb_release_nvm_82575 - Release exclusive access to EEPROM
707 * @hw: pointer to the HW structure
709 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
710 * then release the semaphores acquired.
712 static void igb_release_nvm_82575(struct e1000_hw *hw)
715 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
719 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
720 * @hw: pointer to the HW structure
721 * @mask: specifies which semaphore to acquire
723 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
724 * will also specify which port we're acquiring the lock for.
726 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
730 u32 fwmask = mask << 16;
732 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
734 while (i < timeout) {
735 if (igb_get_hw_semaphore(hw)) {
736 ret_val = -E1000_ERR_SWFW_SYNC;
740 swfw_sync = rd32(E1000_SW_FW_SYNC);
741 if (!(swfw_sync & (fwmask | swmask)))
745 * Firmware currently using resource (fwmask)
746 * or other software thread using resource (swmask)
748 igb_put_hw_semaphore(hw);
754 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
755 ret_val = -E1000_ERR_SWFW_SYNC;
760 wr32(E1000_SW_FW_SYNC, swfw_sync);
762 igb_put_hw_semaphore(hw);
769 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
770 * @hw: pointer to the HW structure
771 * @mask: specifies which semaphore to acquire
773 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
774 * will also specify which port we're releasing the lock for.
776 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
780 while (igb_get_hw_semaphore(hw) != 0);
783 swfw_sync = rd32(E1000_SW_FW_SYNC);
785 wr32(E1000_SW_FW_SYNC, swfw_sync);
787 igb_put_hw_semaphore(hw);
791 * igb_get_cfg_done_82575 - Read config done bit
792 * @hw: pointer to the HW structure
794 * Read the management control register for the config done bit for
795 * completion status. NOTE: silicon which is EEPROM-less will fail trying
796 * to read the config done bit, so an error is *ONLY* logged and returns
797 * 0. If we were to return with error, EEPROM-less silicon
798 * would not be able to be reset or change link.
800 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
802 s32 timeout = PHY_CFG_TIMEOUT;
804 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
806 if (hw->bus.func == 1)
807 mask = E1000_NVM_CFG_DONE_PORT_1;
808 else if (hw->bus.func == E1000_FUNC_2)
809 mask = E1000_NVM_CFG_DONE_PORT_2;
810 else if (hw->bus.func == E1000_FUNC_3)
811 mask = E1000_NVM_CFG_DONE_PORT_3;
814 if (rd32(E1000_EEMNGCTL) & mask)
820 hw_dbg("MNG configuration cycle has not completed.\n");
822 /* If EEPROM is not marked present, init the PHY manually */
823 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
824 (hw->phy.type == e1000_phy_igp_3))
825 igb_phy_init_script_igp3(hw);
831 * igb_check_for_link_82575 - Check for link
832 * @hw: pointer to the HW structure
834 * If sgmii is enabled, then use the pcs register to determine link, otherwise
835 * use the generic interface for determining link.
837 static s32 igb_check_for_link_82575(struct e1000_hw *hw)
842 if (hw->phy.media_type != e1000_media_type_copper) {
843 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
846 * Use this flag to determine if link needs to be checked or
847 * not. If we have link clear the flag so that we do not
848 * continue to check for link.
850 hw->mac.get_link_status = !hw->mac.serdes_has_link;
852 ret_val = igb_check_for_copper_link(hw);
859 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
860 * @hw: pointer to the HW structure
862 void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
867 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
868 !igb_sgmii_active_82575(hw))
871 /* Enable PCS to turn on link */
872 reg = rd32(E1000_PCS_CFG0);
873 reg |= E1000_PCS_CFG_PCS_EN;
874 wr32(E1000_PCS_CFG0, reg);
876 /* Power up the laser */
877 reg = rd32(E1000_CTRL_EXT);
878 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
879 wr32(E1000_CTRL_EXT, reg);
881 /* flush the write to verify completion */
887 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
888 * @hw: pointer to the HW structure
889 * @speed: stores the current speed
890 * @duplex: stores the current duplex
892 * Using the physical coding sub-layer (PCS), retrieve the current speed and
893 * duplex, then store the values in the pointers provided.
895 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
898 struct e1000_mac_info *mac = &hw->mac;
901 /* Set up defaults for the return values of this function */
902 mac->serdes_has_link = false;
907 * Read the PCS Status register for link state. For non-copper mode,
908 * the status register is not accurate. The PCS status register is
911 pcs = rd32(E1000_PCS_LSTAT);
914 * The link up bit determines when link is up on autoneg. The sync ok
915 * gets set once both sides sync up and agree upon link. Stable link
916 * can be determined by checking for both link up and link sync ok
918 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
919 mac->serdes_has_link = true;
921 /* Detect and store PCS speed */
922 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
924 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
930 /* Detect and store PCS duplex */
931 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
932 *duplex = FULL_DUPLEX;
934 *duplex = HALF_DUPLEX;
942 * igb_shutdown_serdes_link_82575 - Remove link during power down
943 * @hw: pointer to the HW structure
945 * In the case of fiber serdes, shut down optics and PCS on driver unload
946 * when management pass thru is not enabled.
948 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
952 if (hw->phy.media_type != e1000_media_type_internal_serdes &&
953 igb_sgmii_active_82575(hw))
956 if (!igb_enable_mng_pass_thru(hw)) {
957 /* Disable PCS to turn off link */
958 reg = rd32(E1000_PCS_CFG0);
959 reg &= ~E1000_PCS_CFG_PCS_EN;
960 wr32(E1000_PCS_CFG0, reg);
962 /* shutdown the laser */
963 reg = rd32(E1000_CTRL_EXT);
964 reg |= E1000_CTRL_EXT_SDP3_DATA;
965 wr32(E1000_CTRL_EXT, reg);
967 /* flush the write to verify completion */
974 * igb_reset_hw_82575 - Reset hardware
975 * @hw: pointer to the HW structure
977 * This resets the hardware into a known state. This is a
978 * function pointer entry point called by the api module.
980 static s32 igb_reset_hw_82575(struct e1000_hw *hw)
986 * Prevent the PCI-E bus from sticking if there is no TLP connection
987 * on the last TLP read/write transaction when MAC is reset.
989 ret_val = igb_disable_pcie_master(hw);
991 hw_dbg("PCI-E Master disable polling has failed.\n");
993 /* set the completion timeout for interface */
994 ret_val = igb_set_pcie_completion_timeout(hw);
996 hw_dbg("PCI-E Set completion timeout has failed.\n");
999 hw_dbg("Masking off all interrupts\n");
1000 wr32(E1000_IMC, 0xffffffff);
1002 wr32(E1000_RCTL, 0);
1003 wr32(E1000_TCTL, E1000_TCTL_PSP);
1008 ctrl = rd32(E1000_CTRL);
1010 hw_dbg("Issuing a global reset to MAC\n");
1011 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1013 ret_val = igb_get_auto_rd_done(hw);
1016 * When auto config read does not complete, do not
1017 * return with an error. This can happen in situations
1018 * where there is no eeprom and prevents getting link.
1020 hw_dbg("Auto Read Done did not complete\n");
1023 /* If EEPROM is not present, run manual init scripts */
1024 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1025 igb_reset_init_script_82575(hw);
1027 /* Clear any pending interrupt events. */
1028 wr32(E1000_IMC, 0xffffffff);
1029 icr = rd32(E1000_ICR);
1031 /* Install any alternate MAC address into RAR0 */
1032 ret_val = igb_check_alt_mac_addr(hw);
1038 * igb_init_hw_82575 - Initialize hardware
1039 * @hw: pointer to the HW structure
1041 * This inits the hardware readying it for operation.
1043 static s32 igb_init_hw_82575(struct e1000_hw *hw)
1045 struct e1000_mac_info *mac = &hw->mac;
1047 u16 i, rar_count = mac->rar_entry_count;
1049 /* Initialize identification LED */
1050 ret_val = igb_id_led_init(hw);
1052 hw_dbg("Error initializing identification LED\n");
1053 /* This is not fatal and we should not stop init due to this */
1056 /* Disabling VLAN filtering */
1057 hw_dbg("Initializing the IEEE VLAN\n");
1060 /* Setup the receive address */
1061 igb_init_rx_addrs(hw, rar_count);
1063 /* Zero out the Multicast HASH table */
1064 hw_dbg("Zeroing the MTA\n");
1065 for (i = 0; i < mac->mta_reg_count; i++)
1066 array_wr32(E1000_MTA, i, 0);
1068 /* Zero out the Unicast HASH table */
1069 hw_dbg("Zeroing the UTA\n");
1070 for (i = 0; i < mac->uta_reg_count; i++)
1071 array_wr32(E1000_UTA, i, 0);
1073 /* Setup link and flow control */
1074 ret_val = igb_setup_link(hw);
1077 * Clear all of the statistics registers (clear on read). It is
1078 * important that we do this after we have tried to establish link
1079 * because the symbol error count will increment wildly if there
1082 igb_clear_hw_cntrs_82575(hw);
1088 * igb_setup_copper_link_82575 - Configure copper link settings
1089 * @hw: pointer to the HW structure
1091 * Configures the link for auto-neg or forced speed and duplex. Then we check
1092 * for link, once link is established calls to configure collision distance
1093 * and flow control are called.
1095 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1100 ctrl = rd32(E1000_CTRL);
1101 ctrl |= E1000_CTRL_SLU;
1102 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1103 wr32(E1000_CTRL, ctrl);
1105 ret_val = igb_setup_serdes_link_82575(hw);
1109 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1110 /* allow time for SFP cage time to power up phy */
1113 ret_val = hw->phy.ops.reset(hw);
1115 hw_dbg("Error resetting the PHY.\n");
1119 switch (hw->phy.type) {
1121 if (hw->phy.id == I347AT4_E_PHY_ID ||
1122 hw->phy.id == M88E1112_E_PHY_ID)
1123 ret_val = igb_copper_link_setup_m88_gen2(hw);
1125 ret_val = igb_copper_link_setup_m88(hw);
1127 case e1000_phy_igp_3:
1128 ret_val = igb_copper_link_setup_igp(hw);
1130 case e1000_phy_82580:
1131 ret_val = igb_copper_link_setup_82580(hw);
1134 ret_val = -E1000_ERR_PHY;
1141 ret_val = igb_setup_copper_link(hw);
1147 * igb_setup_serdes_link_82575 - Setup link for serdes
1148 * @hw: pointer to the HW structure
1150 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1151 * used on copper connections where the serialized gigabit media independent
1152 * interface (sgmii), or serdes fiber is being used. Configures the link
1153 * for auto-negotiation or forces speed/duplex.
1155 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1157 u32 ctrl_ext, ctrl_reg, reg;
1160 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1161 !igb_sgmii_active_82575(hw))
1165 * On the 82575, SerDes loopback mode persists until it is
1166 * explicitly turned off or a power cycle is performed. A read to
1167 * the register does not indicate its status. Therefore, we ensure
1168 * loopback mode is disabled during initialization.
1170 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1172 /* power on the sfp cage if present */
1173 ctrl_ext = rd32(E1000_CTRL_EXT);
1174 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1175 wr32(E1000_CTRL_EXT, ctrl_ext);
1177 ctrl_reg = rd32(E1000_CTRL);
1178 ctrl_reg |= E1000_CTRL_SLU;
1180 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1181 /* set both sw defined pins */
1182 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1184 /* Set switch control to serdes energy detect */
1185 reg = rd32(E1000_CONNSW);
1186 reg |= E1000_CONNSW_ENRGSRC;
1187 wr32(E1000_CONNSW, reg);
1190 reg = rd32(E1000_PCS_LCTL);
1192 /* default pcs_autoneg to the same setting as mac autoneg */
1193 pcs_autoneg = hw->mac.autoneg;
1195 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1196 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1197 /* sgmii mode lets the phy handle forcing speed/duplex */
1199 /* autoneg time out should be disabled for SGMII mode */
1200 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1202 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1203 /* disable PCS autoneg and support parallel detect only */
1204 pcs_autoneg = false;
1207 * non-SGMII modes only supports a speed of 1000/Full for the
1208 * link so it is best to just force the MAC and let the pcs
1209 * link either autoneg or be forced to 1000/Full
1211 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1212 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1214 /* set speed of 1000/Full if speed/duplex is forced */
1215 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1219 wr32(E1000_CTRL, ctrl_reg);
1222 * New SerDes mode allows for forcing speed or autonegotiating speed
1223 * at 1gb. Autoneg should be default set by most drivers. This is the
1224 * mode that will be compatible with older link partners and switches.
1225 * However, both are supported by the hardware and some drivers/tools.
1227 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1228 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1231 * We force flow control to prevent the CTRL register values from being
1232 * overwritten by the autonegotiated flow control values
1234 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1237 /* Set PCS register for autoneg */
1238 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1239 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1240 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1242 /* Set PCS register for forced link */
1243 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1245 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1248 wr32(E1000_PCS_LCTL, reg);
1250 if (!igb_sgmii_active_82575(hw))
1251 igb_force_mac_fc(hw);
1257 * igb_sgmii_active_82575 - Return sgmii state
1258 * @hw: pointer to the HW structure
1260 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1261 * which can be enabled for use in the embedded applications. Simply
1262 * return the current state of the sgmii interface.
1264 static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1266 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1267 return dev_spec->sgmii_active;
1271 * igb_reset_init_script_82575 - Inits HW defaults after reset
1272 * @hw: pointer to the HW structure
1274 * Inits recommended HW defaults after a reset when there is no EEPROM
1275 * detected. This is only for the 82575.
1277 static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1279 if (hw->mac.type == e1000_82575) {
1280 hw_dbg("Running reset init script for 82575\n");
1281 /* SerDes configuration via SERDESCTRL */
1282 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1283 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1284 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1285 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1287 /* CCM configuration via CCMCTL register */
1288 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1289 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1291 /* PCIe lanes configuration */
1292 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1293 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1294 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1295 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1297 /* PCIe PLL Configuration */
1298 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1299 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1300 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1307 * igb_read_mac_addr_82575 - Read device MAC address
1308 * @hw: pointer to the HW structure
1310 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1315 * If there's an alternate MAC address place it in RAR0
1316 * so that it will override the Si installed default perm
1319 ret_val = igb_check_alt_mac_addr(hw);
1323 ret_val = igb_read_mac_addr(hw);
1330 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1331 * @hw: pointer to the HW structure
1333 * In the case of a PHY power down to save power, or to turn off link during a
1334 * driver unload, or wake on lan is not enabled, remove the link.
1336 void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1338 /* If the management interface is not enabled, then power down */
1339 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1340 igb_power_down_phy_copper(hw);
1344 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1345 * @hw: pointer to the HW structure
1347 * Clears the hardware counters by reading the counter registers.
1349 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1351 igb_clear_hw_cntrs_base(hw);
1357 rd32(E1000_PRC1023);
1358 rd32(E1000_PRC1522);
1363 rd32(E1000_PTC1023);
1364 rd32(E1000_PTC1522);
1366 rd32(E1000_ALGNERRC);
1369 rd32(E1000_CEXTERR);
1380 rd32(E1000_ICRXPTC);
1381 rd32(E1000_ICRXATC);
1382 rd32(E1000_ICTXPTC);
1383 rd32(E1000_ICTXATC);
1384 rd32(E1000_ICTXQEC);
1385 rd32(E1000_ICTXQMTC);
1386 rd32(E1000_ICRXDMTC);
1393 rd32(E1000_HTCBDPC);
1398 rd32(E1000_LENERRS);
1400 /* This register should not be read in copper configurations */
1401 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1402 igb_sgmii_active_82575(hw))
1407 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1408 * @hw: pointer to the HW structure
1410 * After rx enable if managability is enabled then there is likely some
1411 * bad data at the start of the fifo and possibly in the DMA fifo. This
1412 * function clears the fifos and flushes any packets that came in as rx was
1415 void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1417 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1420 if (hw->mac.type != e1000_82575 ||
1421 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1424 /* Disable all RX queues */
1425 for (i = 0; i < 4; i++) {
1426 rxdctl[i] = rd32(E1000_RXDCTL(i));
1427 wr32(E1000_RXDCTL(i),
1428 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1430 /* Poll all queues to verify they have shut down */
1431 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1434 for (i = 0; i < 4; i++)
1435 rx_enabled |= rd32(E1000_RXDCTL(i));
1436 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1441 hw_dbg("Queue disable timed out after 10ms\n");
1443 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1444 * incoming packets are rejected. Set enable and wait 2ms so that
1445 * any packet that was coming in as RCTL.EN was set is flushed
1447 rfctl = rd32(E1000_RFCTL);
1448 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1450 rlpml = rd32(E1000_RLPML);
1451 wr32(E1000_RLPML, 0);
1453 rctl = rd32(E1000_RCTL);
1454 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1455 temp_rctl |= E1000_RCTL_LPE;
1457 wr32(E1000_RCTL, temp_rctl);
1458 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1462 /* Enable RX queues that were previously enabled and restore our
1465 for (i = 0; i < 4; i++)
1466 wr32(E1000_RXDCTL(i), rxdctl[i]);
1467 wr32(E1000_RCTL, rctl);
1470 wr32(E1000_RLPML, rlpml);
1471 wr32(E1000_RFCTL, rfctl);
1473 /* Flush receive errors generated by workaround */
1480 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1481 * @hw: pointer to the HW structure
1483 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1484 * however the hardware default for these parts is 500us to 1ms which is less
1485 * than the 10ms recommended by the pci-e spec. To address this we need to
1486 * increase the value to either 10ms to 200ms for capability version 1 config,
1487 * or 16ms to 55ms for version 2.
1489 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1491 u32 gcr = rd32(E1000_GCR);
1495 /* only take action if timeout value is defaulted to 0 */
1496 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1500 * if capababilities version is type 1 we can write the
1501 * timeout of 10ms to 200ms through the GCR register
1503 if (!(gcr & E1000_GCR_CAP_VER2)) {
1504 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1509 * for version 2 capabilities we need to write the config space
1510 * directly in order to set the completion timeout value for
1513 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1518 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
1520 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1523 /* disable completion timeout resend */
1524 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1526 wr32(E1000_GCR, gcr);
1531 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
1532 * @hw: pointer to the hardware struct
1533 * @enable: state to enter, either enabled or disabled
1534 * @pf: Physical Function pool - do not set anti-spoofing for the PF
1536 * enables/disables L2 switch anti-spoofing functionality.
1538 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
1542 switch (hw->mac.type) {
1545 dtxswc = rd32(E1000_DTXSWC);
1547 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
1548 E1000_DTXSWC_VLAN_SPOOF_MASK);
1549 /* The PF can spoof - it has to in order to
1550 * support emulation mode NICs */
1551 dtxswc ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
1553 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
1554 E1000_DTXSWC_VLAN_SPOOF_MASK);
1556 wr32(E1000_DTXSWC, dtxswc);
1564 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
1565 * @hw: pointer to the hardware struct
1566 * @enable: state to enter, either enabled or disabled
1568 * enables/disables L2 switch loopback functionality.
1570 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
1572 u32 dtxswc = rd32(E1000_DTXSWC);
1575 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1577 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1579 wr32(E1000_DTXSWC, dtxswc);
1583 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
1584 * @hw: pointer to the hardware struct
1585 * @enable: state to enter, either enabled or disabled
1587 * enables/disables replication of packets across multiple pools.
1589 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
1591 u32 vt_ctl = rd32(E1000_VT_CTL);
1594 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
1596 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
1598 wr32(E1000_VT_CTL, vt_ctl);
1602 * igb_read_phy_reg_82580 - Read 82580 MDI control register
1603 * @hw: pointer to the HW structure
1604 * @offset: register offset to be read
1605 * @data: pointer to the read data
1607 * Reads the MDI control register in the PHY at offset and stores the
1608 * information read to data.
1610 static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
1615 ret_val = hw->phy.ops.acquire(hw);
1619 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
1621 hw->phy.ops.release(hw);
1628 * igb_write_phy_reg_82580 - Write 82580 MDI control register
1629 * @hw: pointer to the HW structure
1630 * @offset: register offset to write to
1631 * @data: data to write to register at offset
1633 * Writes data to MDI control register in the PHY at offset.
1635 static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
1640 ret_val = hw->phy.ops.acquire(hw);
1644 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
1646 hw->phy.ops.release(hw);
1653 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
1654 * @hw: pointer to the HW structure
1656 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
1657 * the values found in the EEPROM. This addresses an issue in which these
1658 * bits are not restored from EEPROM after reset.
1660 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
1666 if (hw->mac.type != e1000_82580)
1668 if (!igb_sgmii_active_82575(hw))
1671 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
1672 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
1675 hw_dbg("NVM Read Error\n");
1679 mdicnfg = rd32(E1000_MDICNFG);
1680 if (nvm_data & NVM_WORD24_EXT_MDIO)
1681 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
1682 if (nvm_data & NVM_WORD24_COM_MDIO)
1683 mdicnfg |= E1000_MDICNFG_COM_MDIO;
1684 wr32(E1000_MDICNFG, mdicnfg);
1690 * igb_reset_hw_82580 - Reset hardware
1691 * @hw: pointer to the HW structure
1693 * This resets function or entire device (all ports, etc.)
1696 static s32 igb_reset_hw_82580(struct e1000_hw *hw)
1699 /* BH SW mailbox bit in SW_FW_SYNC */
1700 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
1702 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
1705 hw->dev_spec._82575.global_device_reset = false;
1707 /* Get current control state. */
1708 ctrl = rd32(E1000_CTRL);
1711 * Prevent the PCI-E bus from sticking if there is no TLP connection
1712 * on the last TLP read/write transaction when MAC is reset.
1714 ret_val = igb_disable_pcie_master(hw);
1716 hw_dbg("PCI-E Master disable polling has failed.\n");
1718 hw_dbg("Masking off all interrupts\n");
1719 wr32(E1000_IMC, 0xffffffff);
1720 wr32(E1000_RCTL, 0);
1721 wr32(E1000_TCTL, E1000_TCTL_PSP);
1726 /* Determine whether or not a global dev reset is requested */
1727 if (global_device_reset &&
1728 igb_acquire_swfw_sync_82575(hw, swmbsw_mask))
1729 global_device_reset = false;
1731 if (global_device_reset &&
1732 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
1733 ctrl |= E1000_CTRL_DEV_RST;
1735 ctrl |= E1000_CTRL_RST;
1737 wr32(E1000_CTRL, ctrl);
1739 /* Add delay to insure DEV_RST has time to complete */
1740 if (global_device_reset)
1743 ret_val = igb_get_auto_rd_done(hw);
1746 * When auto config read does not complete, do not
1747 * return with an error. This can happen in situations
1748 * where there is no eeprom and prevents getting link.
1750 hw_dbg("Auto Read Done did not complete\n");
1753 /* If EEPROM is not present, run manual init scripts */
1754 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1755 igb_reset_init_script_82575(hw);
1757 /* clear global device reset status bit */
1758 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
1760 /* Clear any pending interrupt events. */
1761 wr32(E1000_IMC, 0xffffffff);
1762 icr = rd32(E1000_ICR);
1764 ret_val = igb_reset_mdicnfg_82580(hw);
1766 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
1768 /* Install any alternate MAC address into RAR0 */
1769 ret_val = igb_check_alt_mac_addr(hw);
1771 /* Release semaphore */
1772 if (global_device_reset)
1773 igb_release_swfw_sync_82575(hw, swmbsw_mask);
1779 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
1780 * @data: data received by reading RXPBS register
1782 * The 82580 uses a table based approach for packet buffer allocation sizes.
1783 * This function converts the retrieved value into the correct table value
1784 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
1785 * 0x0 36 72 144 1 2 4 8 16
1786 * 0x8 35 70 140 rsv rsv rsv rsv rsv
1788 u16 igb_rxpbs_adjust_82580(u32 data)
1792 if (data < E1000_82580_RXPBS_TABLE_SIZE)
1793 ret_val = e1000_82580_rxpbs_table[data];
1799 * igb_validate_nvm_checksum_with_offset - Validate EEPROM
1801 * @hw: pointer to the HW structure
1802 * @offset: offset in words of the checksum protected region
1804 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
1805 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
1807 s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
1813 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
1814 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1816 hw_dbg("NVM Read Error\n");
1819 checksum += nvm_data;
1822 if (checksum != (u16) NVM_SUM) {
1823 hw_dbg("NVM Checksum Invalid\n");
1824 ret_val = -E1000_ERR_NVM;
1833 * igb_update_nvm_checksum_with_offset - Update EEPROM
1835 * @hw: pointer to the HW structure
1836 * @offset: offset in words of the checksum protected region
1838 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
1839 * up to the checksum. Then calculates the EEPROM checksum and writes the
1840 * value to the EEPROM.
1842 s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
1848 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
1849 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1851 hw_dbg("NVM Read Error while updating checksum.\n");
1854 checksum += nvm_data;
1856 checksum = (u16) NVM_SUM - checksum;
1857 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
1860 hw_dbg("NVM Write Error while updating checksum.\n");
1867 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
1868 * @hw: pointer to the HW structure
1870 * Calculates the EEPROM section checksum by reading/adding each word of
1871 * the EEPROM and then verifies that the sum of the EEPROM is
1874 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
1877 u16 eeprom_regions_count = 1;
1881 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
1883 hw_dbg("NVM Read Error\n");
1887 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
1888 /* if checksums compatibility bit is set validate checksums
1889 * for all 4 ports. */
1890 eeprom_regions_count = 4;
1893 for (j = 0; j < eeprom_regions_count; j++) {
1894 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
1895 ret_val = igb_validate_nvm_checksum_with_offset(hw,
1906 * igb_update_nvm_checksum_82580 - Update EEPROM checksum
1907 * @hw: pointer to the HW structure
1909 * Updates the EEPROM section checksums for all 4 ports by reading/adding
1910 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
1911 * checksum and writes the value to the EEPROM.
1913 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
1919 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
1921 hw_dbg("NVM Read Error while updating checksum"
1922 " compatibility bit.\n");
1926 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
1927 /* set compatibility bit to validate checksums appropriately */
1928 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
1929 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
1932 hw_dbg("NVM Write Error while updating checksum"
1933 " compatibility bit.\n");
1938 for (j = 0; j < 4; j++) {
1939 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
1940 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
1950 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
1951 * @hw: pointer to the HW structure
1953 * Calculates the EEPROM section checksum by reading/adding each word of
1954 * the EEPROM and then verifies that the sum of the EEPROM is
1957 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
1963 for (j = 0; j < 4; j++) {
1964 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
1965 ret_val = igb_validate_nvm_checksum_with_offset(hw,
1976 * igb_update_nvm_checksum_i350 - Update EEPROM checksum
1977 * @hw: pointer to the HW structure
1979 * Updates the EEPROM section checksums for all 4 ports by reading/adding
1980 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
1981 * checksum and writes the value to the EEPROM.
1983 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
1989 for (j = 0; j < 4; j++) {
1990 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
1991 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2001 * igb_set_eee_i350 - Enable/disable EEE support
2002 * @hw: pointer to the HW structure
2004 * Enable/disable EEE based on setting in dev_spec structure.
2007 s32 igb_set_eee_i350(struct e1000_hw *hw)
2010 u32 ipcnfg, eeer, ctrl_ext;
2012 ctrl_ext = rd32(E1000_CTRL_EXT);
2013 if ((hw->mac.type != e1000_i350) ||
2014 (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK))
2016 ipcnfg = rd32(E1000_IPCNFG);
2017 eeer = rd32(E1000_EEER);
2019 /* enable or disable per user setting */
2020 if (!(hw->dev_spec._82575.eee_disable)) {
2021 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN |
2022 E1000_IPCNFG_EEE_100M_AN);
2023 eeer |= (E1000_EEER_TX_LPI_EN |
2024 E1000_EEER_RX_LPI_EN |
2028 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2029 E1000_IPCNFG_EEE_100M_AN);
2030 eeer &= ~(E1000_EEER_TX_LPI_EN |
2031 E1000_EEER_RX_LPI_EN |
2034 wr32(E1000_IPCNFG, ipcnfg);
2035 wr32(E1000_EEER, eeer);
2041 static struct e1000_mac_operations e1000_mac_ops_82575 = {
2042 .init_hw = igb_init_hw_82575,
2043 .check_for_link = igb_check_for_link_82575,
2044 .rar_set = igb_rar_set,
2045 .read_mac_addr = igb_read_mac_addr_82575,
2046 .get_speed_and_duplex = igb_get_speed_and_duplex_copper,
2049 static struct e1000_phy_operations e1000_phy_ops_82575 = {
2050 .acquire = igb_acquire_phy_82575,
2051 .get_cfg_done = igb_get_cfg_done_82575,
2052 .release = igb_release_phy_82575,
2055 static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
2056 .acquire = igb_acquire_nvm_82575,
2057 .read = igb_read_nvm_eerd,
2058 .release = igb_release_nvm_82575,
2059 .write = igb_write_nvm_spi,
2062 const struct e1000_info e1000_82575_info = {
2063 .get_invariants = igb_get_invariants_82575,
2064 .mac_ops = &e1000_mac_ops_82575,
2065 .phy_ops = &e1000_phy_ops_82575,
2066 .nvm_ops = &e1000_nvm_ops_82575,