2 * drivers/net/ibm_newemac/core.c
4 * Driver for PowerPC 4xx on-chip ethernet controller.
6 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
7 * <benh@kernel.crashing.org>
9 * Based on the arch/ppc version of the driver:
11 * Copyright (c) 2004, 2005 Zultys Technologies.
12 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
14 * Based on original work by
15 * Matt Porter <mporter@kernel.crashing.org>
16 * (c) 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
17 * Armin Kuster <akuster@mvista.com>
18 * Johnnie Peters <jpeters@mvista.com>
20 * This program is free software; you can redistribute it and/or modify it
21 * under the terms of the GNU General Public License as published by the
22 * Free Software Foundation; either version 2 of the License, or (at your
23 * option) any later version.
27 #include <linux/module.h>
28 #include <linux/sched.h>
29 #include <linux/string.h>
30 #include <linux/errno.h>
31 #include <linux/delay.h>
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
36 #include <linux/crc32.h>
37 #include <linux/ethtool.h>
38 #include <linux/mii.h>
39 #include <linux/bitops.h>
40 #include <linux/workqueue.h>
43 #include <asm/processor.h>
46 #include <asm/uaccess.h>
48 #include <asm/dcr-regs.h>
53 * Lack of dma_unmap_???? calls is intentional.
55 * API-correct usage requires additional support state information to be
56 * maintained for every RX and TX buffer descriptor (BD). Unfortunately, due to
57 * EMAC design (e.g. TX buffer passed from network stack can be split into
58 * several BDs, dma_map_single/dma_map_page can be used to map particular BD),
59 * maintaining such information will add additional overhead.
60 * Current DMA API implementation for 4xx processors only ensures cache coherency
61 * and dma_unmap_???? routines are empty and are likely to stay this way.
62 * I decided to omit dma_unmap_??? calls because I don't want to add additional
63 * complexity just for the sake of following some abstract API, when it doesn't
64 * add any real benefit to the driver. I understand that this decision maybe
65 * controversial, but I really tried to make code API-correct and efficient
66 * at the same time and didn't come up with code I liked :(. --ebs
69 #define DRV_NAME "emac"
70 #define DRV_VERSION "3.54"
71 #define DRV_DESC "PPC 4xx OCP EMAC driver"
73 MODULE_DESCRIPTION(DRV_DESC);
75 ("Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>");
76 MODULE_LICENSE("GPL");
79 * PPC64 doesn't (yet) have a cacheable_memcpy
82 #define cacheable_memcpy(d,s,n) memcpy((d),(s),(n))
85 /* minimum number of free TX descriptors required to wake up TX process */
86 #define EMAC_TX_WAKEUP_THRESH (NUM_TX_BUFF / 4)
88 /* If packet size is less than this number, we allocate small skb and copy packet
89 * contents into it instead of just sending original big skb up
91 #define EMAC_RX_COPY_THRESH CONFIG_IBM_NEW_EMAC_RX_COPY_THRESHOLD
93 /* Since multiple EMACs share MDIO lines in various ways, we need
94 * to avoid re-using the same PHY ID in cases where the arch didn't
95 * setup precise phy_map entries
97 * XXX This is something that needs to be reworked as we can have multiple
98 * EMAC "sets" (multiple ASICs containing several EMACs) though we can
99 * probably require in that case to have explicit PHY IDs in the device-tree
101 static u32 busy_phy_map;
102 static DEFINE_MUTEX(emac_phy_map_lock);
104 /* This is the wait queue used to wait on any event related to probe, that
105 * is discovery of MALs, other EMACs, ZMII/RGMIIs, etc...
107 static DECLARE_WAIT_QUEUE_HEAD(emac_probe_wait);
109 /* Having stable interface names is a doomed idea. However, it would be nice
110 * if we didn't have completely random interface names at boot too :-) It's
111 * just a matter of making everybody's life easier. Since we are doing
112 * threaded probing, it's a bit harder though. The base idea here is that
113 * we make up a list of all emacs in the device-tree before we register the
114 * driver. Every emac will then wait for the previous one in the list to
115 * initialize before itself. We should also keep that list ordered by
117 * That list is only 4 entries long, meaning that additional EMACs don't
118 * get ordering guarantees unless EMAC_BOOT_LIST_SIZE is increased.
121 #define EMAC_BOOT_LIST_SIZE 4
122 static struct device_node *emac_boot_list[EMAC_BOOT_LIST_SIZE];
124 /* How long should I wait for dependent devices ? */
125 #define EMAC_PROBE_DEP_TIMEOUT (HZ * 5)
127 /* I don't want to litter system log with timeout errors
128 * when we have brain-damaged PHY.
130 static inline void emac_report_timeout_error(struct emac_instance *dev,
133 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX |
134 EMAC_FTR_460EX_PHY_CLK_FIX |
135 EMAC_FTR_440EP_PHY_CLK_FIX))
136 DBG(dev, "%s" NL, error);
137 else if (net_ratelimit())
138 printk(KERN_ERR "%s: %s\n", dev->ofdev->node->full_name, error);
141 /* EMAC PHY clock workaround:
142 * 440EP/440GR has more sane SDR0_MFR register implementation than 440GX,
143 * which allows controlling each EMAC clock
145 static inline void emac_rx_clk_tx(struct emac_instance *dev)
147 #ifdef CONFIG_PPC_DCR_NATIVE
148 if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
149 dcri_clrset(SDR0, SDR0_MFR,
150 0, SDR0_MFR_ECS >> dev->cell_index);
154 static inline void emac_rx_clk_default(struct emac_instance *dev)
156 #ifdef CONFIG_PPC_DCR_NATIVE
157 if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
158 dcri_clrset(SDR0, SDR0_MFR,
159 SDR0_MFR_ECS >> dev->cell_index, 0);
163 /* PHY polling intervals */
164 #define PHY_POLL_LINK_ON HZ
165 #define PHY_POLL_LINK_OFF (HZ / 5)
167 /* Graceful stop timeouts in us.
168 * We should allow up to 1 frame time (full-duplex, ignoring collisions)
170 #define STOP_TIMEOUT_10 1230
171 #define STOP_TIMEOUT_100 124
172 #define STOP_TIMEOUT_1000 13
173 #define STOP_TIMEOUT_1000_JUMBO 73
175 static unsigned char default_mcast_addr[] = {
176 0x01, 0x80, 0xC2, 0x00, 0x00, 0x01
179 /* Please, keep in sync with struct ibm_emac_stats/ibm_emac_error_stats */
180 static const char emac_stats_keys[EMAC_ETHTOOL_STATS_COUNT][ETH_GSTRING_LEN] = {
181 "rx_packets", "rx_bytes", "tx_packets", "tx_bytes", "rx_packets_csum",
182 "tx_packets_csum", "tx_undo", "rx_dropped_stack", "rx_dropped_oom",
183 "rx_dropped_error", "rx_dropped_resize", "rx_dropped_mtu",
184 "rx_stopped", "rx_bd_errors", "rx_bd_overrun", "rx_bd_bad_packet",
185 "rx_bd_runt_packet", "rx_bd_short_event", "rx_bd_alignment_error",
186 "rx_bd_bad_fcs", "rx_bd_packet_too_long", "rx_bd_out_of_range",
187 "rx_bd_in_range", "rx_parity", "rx_fifo_overrun", "rx_overrun",
188 "rx_bad_packet", "rx_runt_packet", "rx_short_event",
189 "rx_alignment_error", "rx_bad_fcs", "rx_packet_too_long",
190 "rx_out_of_range", "rx_in_range", "tx_dropped", "tx_bd_errors",
191 "tx_bd_bad_fcs", "tx_bd_carrier_loss", "tx_bd_excessive_deferral",
192 "tx_bd_excessive_collisions", "tx_bd_late_collision",
193 "tx_bd_multple_collisions", "tx_bd_single_collision",
194 "tx_bd_underrun", "tx_bd_sqe", "tx_parity", "tx_underrun", "tx_sqe",
198 static irqreturn_t emac_irq(int irq, void *dev_instance);
199 static void emac_clean_tx_ring(struct emac_instance *dev);
200 static void __emac_set_multicast_list(struct emac_instance *dev);
202 static inline int emac_phy_supports_gige(int phy_mode)
204 return phy_mode == PHY_MODE_GMII ||
205 phy_mode == PHY_MODE_RGMII ||
206 phy_mode == PHY_MODE_SGMII ||
207 phy_mode == PHY_MODE_TBI ||
208 phy_mode == PHY_MODE_RTBI;
211 static inline int emac_phy_gpcs(int phy_mode)
213 return phy_mode == PHY_MODE_SGMII ||
214 phy_mode == PHY_MODE_TBI ||
215 phy_mode == PHY_MODE_RTBI;
218 static inline void emac_tx_enable(struct emac_instance *dev)
220 struct emac_regs __iomem *p = dev->emacp;
223 DBG(dev, "tx_enable" NL);
225 r = in_be32(&p->mr0);
226 if (!(r & EMAC_MR0_TXE))
227 out_be32(&p->mr0, r | EMAC_MR0_TXE);
230 static void emac_tx_disable(struct emac_instance *dev)
232 struct emac_regs __iomem *p = dev->emacp;
235 DBG(dev, "tx_disable" NL);
237 r = in_be32(&p->mr0);
238 if (r & EMAC_MR0_TXE) {
239 int n = dev->stop_timeout;
240 out_be32(&p->mr0, r & ~EMAC_MR0_TXE);
241 while (!(in_be32(&p->mr0) & EMAC_MR0_TXI) && n) {
246 emac_report_timeout_error(dev, "TX disable timeout");
250 static void emac_rx_enable(struct emac_instance *dev)
252 struct emac_regs __iomem *p = dev->emacp;
255 if (unlikely(test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags)))
258 DBG(dev, "rx_enable" NL);
260 r = in_be32(&p->mr0);
261 if (!(r & EMAC_MR0_RXE)) {
262 if (unlikely(!(r & EMAC_MR0_RXI))) {
263 /* Wait if previous async disable is still in progress */
264 int n = dev->stop_timeout;
265 while (!(r = in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
270 emac_report_timeout_error(dev,
271 "RX disable timeout");
273 out_be32(&p->mr0, r | EMAC_MR0_RXE);
279 static void emac_rx_disable(struct emac_instance *dev)
281 struct emac_regs __iomem *p = dev->emacp;
284 DBG(dev, "rx_disable" NL);
286 r = in_be32(&p->mr0);
287 if (r & EMAC_MR0_RXE) {
288 int n = dev->stop_timeout;
289 out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
290 while (!(in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
295 emac_report_timeout_error(dev, "RX disable timeout");
299 static inline void emac_netif_stop(struct emac_instance *dev)
301 netif_tx_lock_bh(dev->ndev);
302 netif_addr_lock(dev->ndev);
304 netif_addr_unlock(dev->ndev);
305 netif_tx_unlock_bh(dev->ndev);
306 dev->ndev->trans_start = jiffies; /* prevent tx timeout */
307 mal_poll_disable(dev->mal, &dev->commac);
308 netif_tx_disable(dev->ndev);
311 static inline void emac_netif_start(struct emac_instance *dev)
313 netif_tx_lock_bh(dev->ndev);
314 netif_addr_lock(dev->ndev);
316 if (dev->mcast_pending && netif_running(dev->ndev))
317 __emac_set_multicast_list(dev);
318 netif_addr_unlock(dev->ndev);
319 netif_tx_unlock_bh(dev->ndev);
321 netif_wake_queue(dev->ndev);
323 /* NOTE: unconditional netif_wake_queue is only appropriate
324 * so long as all callers are assured to have free tx slots
325 * (taken from tg3... though the case where that is wrong is
326 * not terribly harmful)
328 mal_poll_enable(dev->mal, &dev->commac);
331 static inline void emac_rx_disable_async(struct emac_instance *dev)
333 struct emac_regs __iomem *p = dev->emacp;
336 DBG(dev, "rx_disable_async" NL);
338 r = in_be32(&p->mr0);
339 if (r & EMAC_MR0_RXE)
340 out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
343 static int emac_reset(struct emac_instance *dev)
345 struct emac_regs __iomem *p = dev->emacp;
348 DBG(dev, "reset" NL);
350 if (!dev->reset_failed) {
351 /* 40x erratum suggests stopping RX channel before reset,
354 emac_rx_disable(dev);
355 emac_tx_disable(dev);
358 #ifdef CONFIG_PPC_DCR_NATIVE
359 /* Enable internal clock source */
360 if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX))
361 dcri_clrset(SDR0, SDR0_ETH_CFG,
362 0, SDR0_ETH_CFG_ECS << dev->cell_index);
365 out_be32(&p->mr0, EMAC_MR0_SRST);
366 while ((in_be32(&p->mr0) & EMAC_MR0_SRST) && n)
369 #ifdef CONFIG_PPC_DCR_NATIVE
370 /* Enable external clock source */
371 if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX))
372 dcri_clrset(SDR0, SDR0_ETH_CFG,
373 SDR0_ETH_CFG_ECS << dev->cell_index, 0);
377 dev->reset_failed = 0;
380 emac_report_timeout_error(dev, "reset timeout");
381 dev->reset_failed = 1;
386 static void emac_hash_mc(struct emac_instance *dev)
388 const int regs = EMAC_XAHT_REGS(dev);
389 u32 *gaht_base = emac_gaht_base(dev);
391 struct netdev_hw_addr *ha;
394 DBG(dev, "hash_mc %d" NL, netdev_mc_count(dev->ndev));
396 memset(gaht_temp, 0, sizeof (gaht_temp));
398 netdev_for_each_mc_addr(ha, dev->ndev) {
400 DBG2(dev, "mc %pM" NL, ha->addr);
402 slot = EMAC_XAHT_CRC_TO_SLOT(dev,
403 ether_crc(ETH_ALEN, ha->addr));
404 reg = EMAC_XAHT_SLOT_TO_REG(dev, slot);
405 mask = EMAC_XAHT_SLOT_TO_MASK(dev, slot);
407 gaht_temp[reg] |= mask;
410 for (i = 0; i < regs; i++)
411 out_be32(gaht_base + i, gaht_temp[i]);
414 static inline u32 emac_iff2rmr(struct net_device *ndev)
416 struct emac_instance *dev = netdev_priv(ndev);
419 r = EMAC_RMR_SP | EMAC_RMR_SFCS | EMAC_RMR_IAE | EMAC_RMR_BAE;
421 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
426 if (ndev->flags & IFF_PROMISC)
428 else if (ndev->flags & IFF_ALLMULTI ||
429 (netdev_mc_count(ndev) > EMAC_XAHT_SLOTS(dev)))
431 else if (!netdev_mc_empty(ndev))
437 static u32 __emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
439 u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC_MR1_TR0_MULT;
441 DBG2(dev, "__emac_calc_base_mr1" NL);
445 ret |= EMAC_MR1_TFS_2K;
448 printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n",
449 dev->ndev->name, tx_size);
454 ret |= EMAC_MR1_RFS_16K;
457 ret |= EMAC_MR1_RFS_4K;
460 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
461 dev->ndev->name, rx_size);
467 static u32 __emac4_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
469 u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC4_MR1_TR |
470 EMAC4_MR1_OBCI(dev->opb_bus_freq / 1000000);
472 DBG2(dev, "__emac4_calc_base_mr1" NL);
476 ret |= EMAC4_MR1_TFS_16K;
479 ret |= EMAC4_MR1_TFS_4K;
482 ret |= EMAC4_MR1_TFS_2K;
485 printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n",
486 dev->ndev->name, tx_size);
491 ret |= EMAC4_MR1_RFS_16K;
494 ret |= EMAC4_MR1_RFS_4K;
497 ret |= EMAC4_MR1_RFS_2K;
500 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
501 dev->ndev->name, rx_size);
507 static u32 emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
509 return emac_has_feature(dev, EMAC_FTR_EMAC4) ?
510 __emac4_calc_base_mr1(dev, tx_size, rx_size) :
511 __emac_calc_base_mr1(dev, tx_size, rx_size);
514 static inline u32 emac_calc_trtr(struct emac_instance *dev, unsigned int size)
516 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
517 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT_EMAC4;
519 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT;
522 static inline u32 emac_calc_rwmr(struct emac_instance *dev,
523 unsigned int low, unsigned int high)
525 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
526 return (low << 22) | ( (high & 0x3ff) << 6);
528 return (low << 23) | ( (high & 0x1ff) << 7);
531 static int emac_configure(struct emac_instance *dev)
533 struct emac_regs __iomem *p = dev->emacp;
534 struct net_device *ndev = dev->ndev;
535 int tx_size, rx_size, link = netif_carrier_ok(dev->ndev);
538 DBG(dev, "configure" NL);
541 out_be32(&p->mr1, in_be32(&p->mr1)
542 | EMAC_MR1_FDE | EMAC_MR1_ILE);
544 } else if (emac_reset(dev) < 0)
547 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
548 tah_reset(dev->tah_dev);
550 DBG(dev, " link = %d duplex = %d, pause = %d, asym_pause = %d\n",
551 link, dev->phy.duplex, dev->phy.pause, dev->phy.asym_pause);
553 /* Default fifo sizes */
554 tx_size = dev->tx_fifo_size;
555 rx_size = dev->rx_fifo_size;
557 /* No link, force loopback */
559 mr1 = EMAC_MR1_FDE | EMAC_MR1_ILE;
561 /* Check for full duplex */
562 else if (dev->phy.duplex == DUPLEX_FULL)
563 mr1 |= EMAC_MR1_FDE | EMAC_MR1_MWSW_001;
565 /* Adjust fifo sizes, mr1 and timeouts based on link speed */
566 dev->stop_timeout = STOP_TIMEOUT_10;
567 switch (dev->phy.speed) {
569 if (emac_phy_gpcs(dev->phy.mode)) {
570 mr1 |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_MF_IPPA(
571 (dev->phy.gpcs_address != 0xffffffff) ?
572 dev->phy.gpcs_address : dev->phy.address);
574 /* Put some arbitrary OUI, Manuf & Rev IDs so we can
575 * identify this GPCS PHY later.
577 out_be32(&p->u1.emac4.ipcr, 0xdeadbeef);
579 mr1 |= EMAC_MR1_MF_1000;
581 /* Extended fifo sizes */
582 tx_size = dev->tx_fifo_size_gige;
583 rx_size = dev->rx_fifo_size_gige;
585 if (dev->ndev->mtu > ETH_DATA_LEN) {
586 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
587 mr1 |= EMAC4_MR1_JPSM;
589 mr1 |= EMAC_MR1_JPSM;
590 dev->stop_timeout = STOP_TIMEOUT_1000_JUMBO;
592 dev->stop_timeout = STOP_TIMEOUT_1000;
595 mr1 |= EMAC_MR1_MF_100;
596 dev->stop_timeout = STOP_TIMEOUT_100;
598 default: /* make gcc happy */
602 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
603 rgmii_set_speed(dev->rgmii_dev, dev->rgmii_port,
605 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
606 zmii_set_speed(dev->zmii_dev, dev->zmii_port, dev->phy.speed);
608 /* on 40x erratum forces us to NOT use integrated flow control,
609 * let's hope it works on 44x ;)
611 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x) &&
612 dev->phy.duplex == DUPLEX_FULL) {
614 mr1 |= EMAC_MR1_EIFC | EMAC_MR1_APP;
615 else if (dev->phy.asym_pause)
619 /* Add base settings & fifo sizes & program MR1 */
620 mr1 |= emac_calc_base_mr1(dev, tx_size, rx_size);
621 out_be32(&p->mr1, mr1);
623 /* Set individual MAC address */
624 out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]);
625 out_be32(&p->ialr, (ndev->dev_addr[2] << 24) |
626 (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) |
629 /* VLAN Tag Protocol ID */
630 out_be32(&p->vtpid, 0x8100);
632 /* Receive mode register */
633 r = emac_iff2rmr(ndev);
634 if (r & EMAC_RMR_MAE)
636 out_be32(&p->rmr, r);
638 /* FIFOs thresholds */
639 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
640 r = EMAC4_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1,
641 tx_size / 2 / dev->fifo_entry_size);
643 r = EMAC_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1,
644 tx_size / 2 / dev->fifo_entry_size);
645 out_be32(&p->tmr1, r);
646 out_be32(&p->trtr, emac_calc_trtr(dev, tx_size / 2));
648 /* PAUSE frame is sent when RX FIFO reaches its high-water mark,
649 there should be still enough space in FIFO to allow the our link
650 partner time to process this frame and also time to send PAUSE
653 Here is the worst case scenario for the RX FIFO "headroom"
654 (from "The Switch Book") (100Mbps, without preamble, inter-frame gap):
656 1) One maximum-length frame on TX 1522 bytes
657 2) One PAUSE frame time 64 bytes
658 3) PAUSE frame decode time allowance 64 bytes
659 4) One maximum-length frame on RX 1522 bytes
660 5) Round-trip propagation delay of the link (100Mb) 15 bytes
664 I chose to set high-water mark to RX_FIFO_SIZE / 4 (1024 bytes)
665 low-water mark to RX_FIFO_SIZE / 8 (512 bytes)
667 r = emac_calc_rwmr(dev, rx_size / 8 / dev->fifo_entry_size,
668 rx_size / 4 / dev->fifo_entry_size);
669 out_be32(&p->rwmr, r);
671 /* Set PAUSE timer to the maximum */
672 out_be32(&p->ptr, 0xffff);
675 r = EMAC_ISR_OVR | EMAC_ISR_BP | EMAC_ISR_SE |
676 EMAC_ISR_ALE | EMAC_ISR_BFCS | EMAC_ISR_PTLE | EMAC_ISR_ORE |
677 EMAC_ISR_IRE | EMAC_ISR_TE;
678 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
679 r |= EMAC4_ISR_TXPE | EMAC4_ISR_RXPE /* | EMAC4_ISR_TXUE |
681 out_be32(&p->iser, r);
683 /* We need to take GPCS PHY out of isolate mode after EMAC reset */
684 if (emac_phy_gpcs(dev->phy.mode)) {
685 if (dev->phy.gpcs_address != 0xffffffff)
686 emac_mii_reset_gpcs(&dev->phy);
688 emac_mii_reset_phy(&dev->phy);
694 static void emac_reinitialize(struct emac_instance *dev)
696 DBG(dev, "reinitialize" NL);
698 emac_netif_stop(dev);
699 if (!emac_configure(dev)) {
703 emac_netif_start(dev);
706 static void emac_full_tx_reset(struct emac_instance *dev)
708 DBG(dev, "full_tx_reset" NL);
710 emac_tx_disable(dev);
711 mal_disable_tx_channel(dev->mal, dev->mal_tx_chan);
712 emac_clean_tx_ring(dev);
713 dev->tx_cnt = dev->tx_slot = dev->ack_slot = 0;
717 mal_enable_tx_channel(dev->mal, dev->mal_tx_chan);
722 static void emac_reset_work(struct work_struct *work)
724 struct emac_instance *dev = container_of(work, struct emac_instance, reset_work);
726 DBG(dev, "reset_work" NL);
728 mutex_lock(&dev->link_lock);
730 emac_netif_stop(dev);
731 emac_full_tx_reset(dev);
732 emac_netif_start(dev);
734 mutex_unlock(&dev->link_lock);
737 static void emac_tx_timeout(struct net_device *ndev)
739 struct emac_instance *dev = netdev_priv(ndev);
741 DBG(dev, "tx_timeout" NL);
743 schedule_work(&dev->reset_work);
747 static inline int emac_phy_done(struct emac_instance *dev, u32 stacr)
749 int done = !!(stacr & EMAC_STACR_OC);
751 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
757 static int __emac_mdio_read(struct emac_instance *dev, u8 id, u8 reg)
759 struct emac_regs __iomem *p = dev->emacp;
761 int n, err = -ETIMEDOUT;
763 mutex_lock(&dev->mdio_lock);
765 DBG2(dev, "mdio_read(%02x,%02x)" NL, id, reg);
767 /* Enable proper MDIO port */
768 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
769 zmii_get_mdio(dev->zmii_dev, dev->zmii_port);
770 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
771 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port);
773 /* Wait for management interface to become idle */
775 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
778 DBG2(dev, " -> timeout wait idle\n");
783 /* Issue read command */
784 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
785 r = EMAC4_STACR_BASE(dev->opb_bus_freq);
787 r = EMAC_STACR_BASE(dev->opb_bus_freq);
788 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
790 if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR))
791 r |= EMACX_STACR_STAC_READ;
793 r |= EMAC_STACR_STAC_READ;
794 r |= (reg & EMAC_STACR_PRA_MASK)
795 | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT);
796 out_be32(&p->stacr, r);
798 /* Wait for read to complete */
800 while (!emac_phy_done(dev, (r = in_be32(&p->stacr)))) {
803 DBG2(dev, " -> timeout wait complete\n");
808 if (unlikely(r & EMAC_STACR_PHYE)) {
809 DBG(dev, "mdio_read(%02x, %02x) failed" NL, id, reg);
814 r = ((r >> EMAC_STACR_PHYD_SHIFT) & EMAC_STACR_PHYD_MASK);
816 DBG2(dev, "mdio_read -> %04x" NL, r);
819 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
820 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port);
821 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
822 zmii_put_mdio(dev->zmii_dev, dev->zmii_port);
823 mutex_unlock(&dev->mdio_lock);
825 return err == 0 ? r : err;
828 static void __emac_mdio_write(struct emac_instance *dev, u8 id, u8 reg,
831 struct emac_regs __iomem *p = dev->emacp;
833 int n, err = -ETIMEDOUT;
835 mutex_lock(&dev->mdio_lock);
837 DBG2(dev, "mdio_write(%02x,%02x,%04x)" NL, id, reg, val);
839 /* Enable proper MDIO port */
840 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
841 zmii_get_mdio(dev->zmii_dev, dev->zmii_port);
842 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
843 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port);
845 /* Wait for management interface to be idle */
847 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
850 DBG2(dev, " -> timeout wait idle\n");
855 /* Issue write command */
856 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
857 r = EMAC4_STACR_BASE(dev->opb_bus_freq);
859 r = EMAC_STACR_BASE(dev->opb_bus_freq);
860 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
862 if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR))
863 r |= EMACX_STACR_STAC_WRITE;
865 r |= EMAC_STACR_STAC_WRITE;
866 r |= (reg & EMAC_STACR_PRA_MASK) |
867 ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) |
868 (val << EMAC_STACR_PHYD_SHIFT);
869 out_be32(&p->stacr, r);
871 /* Wait for write to complete */
873 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
876 DBG2(dev, " -> timeout wait complete\n");
882 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
883 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port);
884 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
885 zmii_put_mdio(dev->zmii_dev, dev->zmii_port);
886 mutex_unlock(&dev->mdio_lock);
889 static int emac_mdio_read(struct net_device *ndev, int id, int reg)
891 struct emac_instance *dev = netdev_priv(ndev);
894 res = __emac_mdio_read((dev->mdio_instance &&
895 dev->phy.gpcs_address != id) ?
896 dev->mdio_instance : dev,
901 static void emac_mdio_write(struct net_device *ndev, int id, int reg, int val)
903 struct emac_instance *dev = netdev_priv(ndev);
905 __emac_mdio_write((dev->mdio_instance &&
906 dev->phy.gpcs_address != id) ?
907 dev->mdio_instance : dev,
908 (u8) id, (u8) reg, (u16) val);
912 static void __emac_set_multicast_list(struct emac_instance *dev)
914 struct emac_regs __iomem *p = dev->emacp;
915 u32 rmr = emac_iff2rmr(dev->ndev);
917 DBG(dev, "__multicast %08x" NL, rmr);
919 /* I decided to relax register access rules here to avoid
922 * There is a real problem with EMAC4 core if we use MWSW_001 bit
923 * in MR1 register and do a full EMAC reset.
924 * One TX BD status update is delayed and, after EMAC reset, it
925 * never happens, resulting in TX hung (it'll be recovered by TX
926 * timeout handler eventually, but this is just gross).
927 * So we either have to do full TX reset or try to cheat here :)
929 * The only required change is to RX mode register, so I *think* all
930 * we need is just to stop RX channel. This seems to work on all
933 * If we need the full reset, we might just trigger the workqueue
934 * and do it async... a bit nasty but should work --BenH
936 dev->mcast_pending = 0;
937 emac_rx_disable(dev);
938 if (rmr & EMAC_RMR_MAE)
940 out_be32(&p->rmr, rmr);
945 static void emac_set_multicast_list(struct net_device *ndev)
947 struct emac_instance *dev = netdev_priv(ndev);
949 DBG(dev, "multicast" NL);
951 BUG_ON(!netif_running(dev->ndev));
954 dev->mcast_pending = 1;
957 __emac_set_multicast_list(dev);
960 static int emac_resize_rx_ring(struct emac_instance *dev, int new_mtu)
962 int rx_sync_size = emac_rx_sync_size(new_mtu);
963 int rx_skb_size = emac_rx_skb_size(new_mtu);
966 mutex_lock(&dev->link_lock);
967 emac_netif_stop(dev);
968 emac_rx_disable(dev);
969 mal_disable_rx_channel(dev->mal, dev->mal_rx_chan);
971 if (dev->rx_sg_skb) {
972 ++dev->estats.rx_dropped_resize;
973 dev_kfree_skb(dev->rx_sg_skb);
974 dev->rx_sg_skb = NULL;
977 /* Make a first pass over RX ring and mark BDs ready, dropping
978 * non-processed packets on the way. We need this as a separate pass
979 * to simplify error recovery in the case of allocation failure later.
981 for (i = 0; i < NUM_RX_BUFF; ++i) {
982 if (dev->rx_desc[i].ctrl & MAL_RX_CTRL_FIRST)
983 ++dev->estats.rx_dropped_resize;
985 dev->rx_desc[i].data_len = 0;
986 dev->rx_desc[i].ctrl = MAL_RX_CTRL_EMPTY |
987 (i == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
990 /* Reallocate RX ring only if bigger skb buffers are required */
991 if (rx_skb_size <= dev->rx_skb_size)
994 /* Second pass, allocate new skbs */
995 for (i = 0; i < NUM_RX_BUFF; ++i) {
996 struct sk_buff *skb = alloc_skb(rx_skb_size, GFP_ATOMIC);
1002 BUG_ON(!dev->rx_skb[i]);
1003 dev_kfree_skb(dev->rx_skb[i]);
1005 skb_reserve(skb, EMAC_RX_SKB_HEADROOM + 2);
1006 dev->rx_desc[i].data_ptr =
1007 dma_map_single(&dev->ofdev->dev, skb->data - 2, rx_sync_size,
1008 DMA_FROM_DEVICE) + 2;
1009 dev->rx_skb[i] = skb;
1012 /* Check if we need to change "Jumbo" bit in MR1 */
1013 if ((new_mtu > ETH_DATA_LEN) ^ (dev->ndev->mtu > ETH_DATA_LEN)) {
1014 /* This is to prevent starting RX channel in emac_rx_enable() */
1015 set_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1017 dev->ndev->mtu = new_mtu;
1018 emac_full_tx_reset(dev);
1021 mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(new_mtu));
1024 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1026 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1027 emac_rx_enable(dev);
1028 emac_netif_start(dev);
1029 mutex_unlock(&dev->link_lock);
1034 /* Process ctx, rtnl_lock semaphore */
1035 static int emac_change_mtu(struct net_device *ndev, int new_mtu)
1037 struct emac_instance *dev = netdev_priv(ndev);
1040 if (new_mtu < EMAC_MIN_MTU || new_mtu > dev->max_mtu)
1043 DBG(dev, "change_mtu(%d)" NL, new_mtu);
1045 if (netif_running(ndev)) {
1046 /* Check if we really need to reinitalize RX ring */
1047 if (emac_rx_skb_size(ndev->mtu) != emac_rx_skb_size(new_mtu))
1048 ret = emac_resize_rx_ring(dev, new_mtu);
1052 ndev->mtu = new_mtu;
1053 dev->rx_skb_size = emac_rx_skb_size(new_mtu);
1054 dev->rx_sync_size = emac_rx_sync_size(new_mtu);
1060 static void emac_clean_tx_ring(struct emac_instance *dev)
1064 for (i = 0; i < NUM_TX_BUFF; ++i) {
1065 if (dev->tx_skb[i]) {
1066 dev_kfree_skb(dev->tx_skb[i]);
1067 dev->tx_skb[i] = NULL;
1068 if (dev->tx_desc[i].ctrl & MAL_TX_CTRL_READY)
1069 ++dev->estats.tx_dropped;
1071 dev->tx_desc[i].ctrl = 0;
1072 dev->tx_desc[i].data_ptr = 0;
1076 static void emac_clean_rx_ring(struct emac_instance *dev)
1080 for (i = 0; i < NUM_RX_BUFF; ++i)
1081 if (dev->rx_skb[i]) {
1082 dev->rx_desc[i].ctrl = 0;
1083 dev_kfree_skb(dev->rx_skb[i]);
1084 dev->rx_skb[i] = NULL;
1085 dev->rx_desc[i].data_ptr = 0;
1088 if (dev->rx_sg_skb) {
1089 dev_kfree_skb(dev->rx_sg_skb);
1090 dev->rx_sg_skb = NULL;
1094 static inline int emac_alloc_rx_skb(struct emac_instance *dev, int slot,
1097 struct sk_buff *skb = alloc_skb(dev->rx_skb_size, flags);
1101 dev->rx_skb[slot] = skb;
1102 dev->rx_desc[slot].data_len = 0;
1104 skb_reserve(skb, EMAC_RX_SKB_HEADROOM + 2);
1105 dev->rx_desc[slot].data_ptr =
1106 dma_map_single(&dev->ofdev->dev, skb->data - 2, dev->rx_sync_size,
1107 DMA_FROM_DEVICE) + 2;
1109 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
1110 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1115 static void emac_print_link_status(struct emac_instance *dev)
1117 if (netif_carrier_ok(dev->ndev))
1118 printk(KERN_INFO "%s: link is up, %d %s%s\n",
1119 dev->ndev->name, dev->phy.speed,
1120 dev->phy.duplex == DUPLEX_FULL ? "FDX" : "HDX",
1121 dev->phy.pause ? ", pause enabled" :
1122 dev->phy.asym_pause ? ", asymmetric pause enabled" : "");
1124 printk(KERN_INFO "%s: link is down\n", dev->ndev->name);
1127 /* Process ctx, rtnl_lock semaphore */
1128 static int emac_open(struct net_device *ndev)
1130 struct emac_instance *dev = netdev_priv(ndev);
1133 DBG(dev, "open" NL);
1135 /* Setup error IRQ handler */
1136 err = request_irq(dev->emac_irq, emac_irq, 0, "EMAC", dev);
1138 printk(KERN_ERR "%s: failed to request IRQ %d\n",
1139 ndev->name, dev->emac_irq);
1143 /* Allocate RX ring */
1144 for (i = 0; i < NUM_RX_BUFF; ++i)
1145 if (emac_alloc_rx_skb(dev, i, GFP_KERNEL)) {
1146 printk(KERN_ERR "%s: failed to allocate RX ring\n",
1151 dev->tx_cnt = dev->tx_slot = dev->ack_slot = dev->rx_slot = 0;
1152 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1153 dev->rx_sg_skb = NULL;
1155 mutex_lock(&dev->link_lock);
1158 /* Start PHY polling now.
1160 if (dev->phy.address >= 0) {
1161 int link_poll_interval;
1162 if (dev->phy.def->ops->poll_link(&dev->phy)) {
1163 dev->phy.def->ops->read_link(&dev->phy);
1164 emac_rx_clk_default(dev);
1165 netif_carrier_on(dev->ndev);
1166 link_poll_interval = PHY_POLL_LINK_ON;
1168 emac_rx_clk_tx(dev);
1169 netif_carrier_off(dev->ndev);
1170 link_poll_interval = PHY_POLL_LINK_OFF;
1172 dev->link_polling = 1;
1174 schedule_delayed_work(&dev->link_work, link_poll_interval);
1175 emac_print_link_status(dev);
1177 netif_carrier_on(dev->ndev);
1179 /* Required for Pause packet support in EMAC */
1180 dev_mc_add_global(ndev, default_mcast_addr);
1182 emac_configure(dev);
1183 mal_poll_add(dev->mal, &dev->commac);
1184 mal_enable_tx_channel(dev->mal, dev->mal_tx_chan);
1185 mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(ndev->mtu));
1186 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1187 emac_tx_enable(dev);
1188 emac_rx_enable(dev);
1189 emac_netif_start(dev);
1191 mutex_unlock(&dev->link_lock);
1195 emac_clean_rx_ring(dev);
1196 free_irq(dev->emac_irq, dev);
1203 static int emac_link_differs(struct emac_instance *dev)
1205 u32 r = in_be32(&dev->emacp->mr1);
1207 int duplex = r & EMAC_MR1_FDE ? DUPLEX_FULL : DUPLEX_HALF;
1208 int speed, pause, asym_pause;
1210 if (r & EMAC_MR1_MF_1000)
1212 else if (r & EMAC_MR1_MF_100)
1217 switch (r & (EMAC_MR1_EIFC | EMAC_MR1_APP)) {
1218 case (EMAC_MR1_EIFC | EMAC_MR1_APP):
1227 pause = asym_pause = 0;
1229 return speed != dev->phy.speed || duplex != dev->phy.duplex ||
1230 pause != dev->phy.pause || asym_pause != dev->phy.asym_pause;
1234 static void emac_link_timer(struct work_struct *work)
1236 struct emac_instance *dev =
1237 container_of(to_delayed_work(work),
1238 struct emac_instance, link_work);
1239 int link_poll_interval;
1241 mutex_lock(&dev->link_lock);
1242 DBG2(dev, "link timer" NL);
1247 if (dev->phy.def->ops->poll_link(&dev->phy)) {
1248 if (!netif_carrier_ok(dev->ndev)) {
1249 emac_rx_clk_default(dev);
1250 /* Get new link parameters */
1251 dev->phy.def->ops->read_link(&dev->phy);
1253 netif_carrier_on(dev->ndev);
1254 emac_netif_stop(dev);
1255 emac_full_tx_reset(dev);
1256 emac_netif_start(dev);
1257 emac_print_link_status(dev);
1259 link_poll_interval = PHY_POLL_LINK_ON;
1261 if (netif_carrier_ok(dev->ndev)) {
1262 emac_rx_clk_tx(dev);
1263 netif_carrier_off(dev->ndev);
1264 netif_tx_disable(dev->ndev);
1265 emac_reinitialize(dev);
1266 emac_print_link_status(dev);
1268 link_poll_interval = PHY_POLL_LINK_OFF;
1270 schedule_delayed_work(&dev->link_work, link_poll_interval);
1272 mutex_unlock(&dev->link_lock);
1275 static void emac_force_link_update(struct emac_instance *dev)
1277 netif_carrier_off(dev->ndev);
1279 if (dev->link_polling) {
1280 cancel_rearming_delayed_work(&dev->link_work);
1281 if (dev->link_polling)
1282 schedule_delayed_work(&dev->link_work, PHY_POLL_LINK_OFF);
1286 /* Process ctx, rtnl_lock semaphore */
1287 static int emac_close(struct net_device *ndev)
1289 struct emac_instance *dev = netdev_priv(ndev);
1291 DBG(dev, "close" NL);
1293 if (dev->phy.address >= 0) {
1294 dev->link_polling = 0;
1295 cancel_rearming_delayed_work(&dev->link_work);
1297 mutex_lock(&dev->link_lock);
1298 emac_netif_stop(dev);
1300 mutex_unlock(&dev->link_lock);
1302 emac_rx_disable(dev);
1303 emac_tx_disable(dev);
1304 mal_disable_rx_channel(dev->mal, dev->mal_rx_chan);
1305 mal_disable_tx_channel(dev->mal, dev->mal_tx_chan);
1306 mal_poll_del(dev->mal, &dev->commac);
1308 emac_clean_tx_ring(dev);
1309 emac_clean_rx_ring(dev);
1311 free_irq(dev->emac_irq, dev);
1313 netif_carrier_off(ndev);
1318 static inline u16 emac_tx_csum(struct emac_instance *dev,
1319 struct sk_buff *skb)
1321 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) &&
1322 (skb->ip_summed == CHECKSUM_PARTIAL)) {
1323 ++dev->stats.tx_packets_csum;
1324 return EMAC_TX_CTRL_TAH_CSUM;
1329 static inline int emac_xmit_finish(struct emac_instance *dev, int len)
1331 struct emac_regs __iomem *p = dev->emacp;
1332 struct net_device *ndev = dev->ndev;
1334 /* Send the packet out. If the if makes a significant perf
1335 * difference, then we can store the TMR0 value in "dev"
1338 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
1339 out_be32(&p->tmr0, EMAC4_TMR0_XMIT);
1341 out_be32(&p->tmr0, EMAC_TMR0_XMIT);
1343 if (unlikely(++dev->tx_cnt == NUM_TX_BUFF)) {
1344 netif_stop_queue(ndev);
1345 DBG2(dev, "stopped TX queue" NL);
1348 ndev->trans_start = jiffies;
1349 ++dev->stats.tx_packets;
1350 dev->stats.tx_bytes += len;
1352 return NETDEV_TX_OK;
1356 static int emac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1358 struct emac_instance *dev = netdev_priv(ndev);
1359 unsigned int len = skb->len;
1362 u16 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1363 MAL_TX_CTRL_LAST | emac_tx_csum(dev, skb);
1365 slot = dev->tx_slot++;
1366 if (dev->tx_slot == NUM_TX_BUFF) {
1368 ctrl |= MAL_TX_CTRL_WRAP;
1371 DBG2(dev, "xmit(%u) %d" NL, len, slot);
1373 dev->tx_skb[slot] = skb;
1374 dev->tx_desc[slot].data_ptr = dma_map_single(&dev->ofdev->dev,
1377 dev->tx_desc[slot].data_len = (u16) len;
1379 dev->tx_desc[slot].ctrl = ctrl;
1381 return emac_xmit_finish(dev, len);
1384 static inline int emac_xmit_split(struct emac_instance *dev, int slot,
1385 u32 pd, int len, int last, u16 base_ctrl)
1388 u16 ctrl = base_ctrl;
1389 int chunk = min(len, MAL_MAX_TX_SIZE);
1392 slot = (slot + 1) % NUM_TX_BUFF;
1395 ctrl |= MAL_TX_CTRL_LAST;
1396 if (slot == NUM_TX_BUFF - 1)
1397 ctrl |= MAL_TX_CTRL_WRAP;
1399 dev->tx_skb[slot] = NULL;
1400 dev->tx_desc[slot].data_ptr = pd;
1401 dev->tx_desc[slot].data_len = (u16) chunk;
1402 dev->tx_desc[slot].ctrl = ctrl;
1413 /* Tx lock BH disabled (SG version for TAH equipped EMACs) */
1414 static int emac_start_xmit_sg(struct sk_buff *skb, struct net_device *ndev)
1416 struct emac_instance *dev = netdev_priv(ndev);
1417 int nr_frags = skb_shinfo(skb)->nr_frags;
1418 int len = skb->len, chunk;
1423 /* This is common "fast" path */
1424 if (likely(!nr_frags && len <= MAL_MAX_TX_SIZE))
1425 return emac_start_xmit(skb, ndev);
1427 len -= skb->data_len;
1429 /* Note, this is only an *estimation*, we can still run out of empty
1430 * slots because of the additional fragmentation into
1431 * MAL_MAX_TX_SIZE-sized chunks
1433 if (unlikely(dev->tx_cnt + nr_frags + mal_tx_chunks(len) > NUM_TX_BUFF))
1436 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1437 emac_tx_csum(dev, skb);
1438 slot = dev->tx_slot;
1441 dev->tx_skb[slot] = NULL;
1442 chunk = min(len, MAL_MAX_TX_SIZE);
1443 dev->tx_desc[slot].data_ptr = pd =
1444 dma_map_single(&dev->ofdev->dev, skb->data, len, DMA_TO_DEVICE);
1445 dev->tx_desc[slot].data_len = (u16) chunk;
1448 slot = emac_xmit_split(dev, slot, pd + chunk, len, !nr_frags,
1451 for (i = 0; i < nr_frags; ++i) {
1452 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
1455 if (unlikely(dev->tx_cnt + mal_tx_chunks(len) >= NUM_TX_BUFF))
1458 pd = dma_map_page(&dev->ofdev->dev, frag->page, frag->page_offset, len,
1461 slot = emac_xmit_split(dev, slot, pd, len, i == nr_frags - 1,
1465 DBG2(dev, "xmit_sg(%u) %d - %d" NL, skb->len, dev->tx_slot, slot);
1467 /* Attach skb to the last slot so we don't release it too early */
1468 dev->tx_skb[slot] = skb;
1470 /* Send the packet out */
1471 if (dev->tx_slot == NUM_TX_BUFF - 1)
1472 ctrl |= MAL_TX_CTRL_WRAP;
1474 dev->tx_desc[dev->tx_slot].ctrl = ctrl;
1475 dev->tx_slot = (slot + 1) % NUM_TX_BUFF;
1477 return emac_xmit_finish(dev, skb->len);
1480 /* Well, too bad. Our previous estimation was overly optimistic.
1483 while (slot != dev->tx_slot) {
1484 dev->tx_desc[slot].ctrl = 0;
1487 slot = NUM_TX_BUFF - 1;
1489 ++dev->estats.tx_undo;
1492 netif_stop_queue(ndev);
1493 DBG2(dev, "stopped TX queue" NL);
1494 return NETDEV_TX_BUSY;
1498 static void emac_parse_tx_error(struct emac_instance *dev, u16 ctrl)
1500 struct emac_error_stats *st = &dev->estats;
1502 DBG(dev, "BD TX error %04x" NL, ctrl);
1505 if (ctrl & EMAC_TX_ST_BFCS)
1506 ++st->tx_bd_bad_fcs;
1507 if (ctrl & EMAC_TX_ST_LCS)
1508 ++st->tx_bd_carrier_loss;
1509 if (ctrl & EMAC_TX_ST_ED)
1510 ++st->tx_bd_excessive_deferral;
1511 if (ctrl & EMAC_TX_ST_EC)
1512 ++st->tx_bd_excessive_collisions;
1513 if (ctrl & EMAC_TX_ST_LC)
1514 ++st->tx_bd_late_collision;
1515 if (ctrl & EMAC_TX_ST_MC)
1516 ++st->tx_bd_multple_collisions;
1517 if (ctrl & EMAC_TX_ST_SC)
1518 ++st->tx_bd_single_collision;
1519 if (ctrl & EMAC_TX_ST_UR)
1520 ++st->tx_bd_underrun;
1521 if (ctrl & EMAC_TX_ST_SQE)
1525 static void emac_poll_tx(void *param)
1527 struct emac_instance *dev = param;
1530 DBG2(dev, "poll_tx, %d %d" NL, dev->tx_cnt, dev->ack_slot);
1532 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
1533 bad_mask = EMAC_IS_BAD_TX_TAH;
1535 bad_mask = EMAC_IS_BAD_TX;
1537 netif_tx_lock_bh(dev->ndev);
1540 int slot = dev->ack_slot, n = 0;
1542 ctrl = dev->tx_desc[slot].ctrl;
1543 if (!(ctrl & MAL_TX_CTRL_READY)) {
1544 struct sk_buff *skb = dev->tx_skb[slot];
1549 dev->tx_skb[slot] = NULL;
1551 slot = (slot + 1) % NUM_TX_BUFF;
1553 if (unlikely(ctrl & bad_mask))
1554 emac_parse_tx_error(dev, ctrl);
1560 dev->ack_slot = slot;
1561 if (netif_queue_stopped(dev->ndev) &&
1562 dev->tx_cnt < EMAC_TX_WAKEUP_THRESH)
1563 netif_wake_queue(dev->ndev);
1565 DBG2(dev, "tx %d pkts" NL, n);
1568 netif_tx_unlock_bh(dev->ndev);
1571 static inline void emac_recycle_rx_skb(struct emac_instance *dev, int slot,
1574 struct sk_buff *skb = dev->rx_skb[slot];
1576 DBG2(dev, "recycle %d %d" NL, slot, len);
1579 dma_map_single(&dev->ofdev->dev, skb->data - 2,
1580 EMAC_DMA_ALIGN(len + 2), DMA_FROM_DEVICE);
1582 dev->rx_desc[slot].data_len = 0;
1584 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
1585 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1588 static void emac_parse_rx_error(struct emac_instance *dev, u16 ctrl)
1590 struct emac_error_stats *st = &dev->estats;
1592 DBG(dev, "BD RX error %04x" NL, ctrl);
1595 if (ctrl & EMAC_RX_ST_OE)
1596 ++st->rx_bd_overrun;
1597 if (ctrl & EMAC_RX_ST_BP)
1598 ++st->rx_bd_bad_packet;
1599 if (ctrl & EMAC_RX_ST_RP)
1600 ++st->rx_bd_runt_packet;
1601 if (ctrl & EMAC_RX_ST_SE)
1602 ++st->rx_bd_short_event;
1603 if (ctrl & EMAC_RX_ST_AE)
1604 ++st->rx_bd_alignment_error;
1605 if (ctrl & EMAC_RX_ST_BFCS)
1606 ++st->rx_bd_bad_fcs;
1607 if (ctrl & EMAC_RX_ST_PTL)
1608 ++st->rx_bd_packet_too_long;
1609 if (ctrl & EMAC_RX_ST_ORE)
1610 ++st->rx_bd_out_of_range;
1611 if (ctrl & EMAC_RX_ST_IRE)
1612 ++st->rx_bd_in_range;
1615 static inline void emac_rx_csum(struct emac_instance *dev,
1616 struct sk_buff *skb, u16 ctrl)
1618 #ifdef CONFIG_IBM_NEW_EMAC_TAH
1619 if (!ctrl && dev->tah_dev) {
1620 skb->ip_summed = CHECKSUM_UNNECESSARY;
1621 ++dev->stats.rx_packets_csum;
1626 static inline int emac_rx_sg_append(struct emac_instance *dev, int slot)
1628 if (likely(dev->rx_sg_skb != NULL)) {
1629 int len = dev->rx_desc[slot].data_len;
1630 int tot_len = dev->rx_sg_skb->len + len;
1632 if (unlikely(tot_len + 2 > dev->rx_skb_size)) {
1633 ++dev->estats.rx_dropped_mtu;
1634 dev_kfree_skb(dev->rx_sg_skb);
1635 dev->rx_sg_skb = NULL;
1637 cacheable_memcpy(skb_tail_pointer(dev->rx_sg_skb),
1638 dev->rx_skb[slot]->data, len);
1639 skb_put(dev->rx_sg_skb, len);
1640 emac_recycle_rx_skb(dev, slot, len);
1644 emac_recycle_rx_skb(dev, slot, 0);
1648 /* NAPI poll context */
1649 static int emac_poll_rx(void *param, int budget)
1651 struct emac_instance *dev = param;
1652 int slot = dev->rx_slot, received = 0;
1654 DBG2(dev, "poll_rx(%d)" NL, budget);
1657 while (budget > 0) {
1659 struct sk_buff *skb;
1660 u16 ctrl = dev->rx_desc[slot].ctrl;
1662 if (ctrl & MAL_RX_CTRL_EMPTY)
1665 skb = dev->rx_skb[slot];
1667 len = dev->rx_desc[slot].data_len;
1669 if (unlikely(!MAL_IS_SINGLE_RX(ctrl)))
1672 ctrl &= EMAC_BAD_RX_MASK;
1673 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1674 emac_parse_rx_error(dev, ctrl);
1675 ++dev->estats.rx_dropped_error;
1676 emac_recycle_rx_skb(dev, slot, 0);
1681 if (len < ETH_HLEN) {
1682 ++dev->estats.rx_dropped_stack;
1683 emac_recycle_rx_skb(dev, slot, len);
1687 if (len && len < EMAC_RX_COPY_THRESH) {
1688 struct sk_buff *copy_skb =
1689 alloc_skb(len + EMAC_RX_SKB_HEADROOM + 2, GFP_ATOMIC);
1690 if (unlikely(!copy_skb))
1693 skb_reserve(copy_skb, EMAC_RX_SKB_HEADROOM + 2);
1694 cacheable_memcpy(copy_skb->data - 2, skb->data - 2,
1696 emac_recycle_rx_skb(dev, slot, len);
1698 } else if (unlikely(emac_alloc_rx_skb(dev, slot, GFP_ATOMIC)))
1703 skb->protocol = eth_type_trans(skb, dev->ndev);
1704 emac_rx_csum(dev, skb, ctrl);
1706 if (unlikely(netif_receive_skb(skb) == NET_RX_DROP))
1707 ++dev->estats.rx_dropped_stack;
1709 ++dev->stats.rx_packets;
1711 dev->stats.rx_bytes += len;
1712 slot = (slot + 1) % NUM_RX_BUFF;
1717 if (ctrl & MAL_RX_CTRL_FIRST) {
1718 BUG_ON(dev->rx_sg_skb);
1719 if (unlikely(emac_alloc_rx_skb(dev, slot, GFP_ATOMIC))) {
1720 DBG(dev, "rx OOM %d" NL, slot);
1721 ++dev->estats.rx_dropped_oom;
1722 emac_recycle_rx_skb(dev, slot, 0);
1724 dev->rx_sg_skb = skb;
1727 } else if (!emac_rx_sg_append(dev, slot) &&
1728 (ctrl & MAL_RX_CTRL_LAST)) {
1730 skb = dev->rx_sg_skb;
1731 dev->rx_sg_skb = NULL;
1733 ctrl &= EMAC_BAD_RX_MASK;
1734 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1735 emac_parse_rx_error(dev, ctrl);
1736 ++dev->estats.rx_dropped_error;
1744 DBG(dev, "rx OOM %d" NL, slot);
1745 /* Drop the packet and recycle skb */
1746 ++dev->estats.rx_dropped_oom;
1747 emac_recycle_rx_skb(dev, slot, 0);
1752 DBG2(dev, "rx %d BDs" NL, received);
1753 dev->rx_slot = slot;
1756 if (unlikely(budget && test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags))) {
1758 if (!(dev->rx_desc[slot].ctrl & MAL_RX_CTRL_EMPTY)) {
1759 DBG2(dev, "rx restart" NL);
1764 if (dev->rx_sg_skb) {
1765 DBG2(dev, "dropping partial rx packet" NL);
1766 ++dev->estats.rx_dropped_error;
1767 dev_kfree_skb(dev->rx_sg_skb);
1768 dev->rx_sg_skb = NULL;
1771 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1772 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1773 emac_rx_enable(dev);
1779 /* NAPI poll context */
1780 static int emac_peek_rx(void *param)
1782 struct emac_instance *dev = param;
1784 return !(dev->rx_desc[dev->rx_slot].ctrl & MAL_RX_CTRL_EMPTY);
1787 /* NAPI poll context */
1788 static int emac_peek_rx_sg(void *param)
1790 struct emac_instance *dev = param;
1792 int slot = dev->rx_slot;
1794 u16 ctrl = dev->rx_desc[slot].ctrl;
1795 if (ctrl & MAL_RX_CTRL_EMPTY)
1797 else if (ctrl & MAL_RX_CTRL_LAST)
1800 slot = (slot + 1) % NUM_RX_BUFF;
1802 /* I'm just being paranoid here :) */
1803 if (unlikely(slot == dev->rx_slot))
1809 static void emac_rxde(void *param)
1811 struct emac_instance *dev = param;
1813 ++dev->estats.rx_stopped;
1814 emac_rx_disable_async(dev);
1818 static irqreturn_t emac_irq(int irq, void *dev_instance)
1820 struct emac_instance *dev = dev_instance;
1821 struct emac_regs __iomem *p = dev->emacp;
1822 struct emac_error_stats *st = &dev->estats;
1825 spin_lock(&dev->lock);
1827 isr = in_be32(&p->isr);
1828 out_be32(&p->isr, isr);
1830 DBG(dev, "isr = %08x" NL, isr);
1832 if (isr & EMAC4_ISR_TXPE)
1834 if (isr & EMAC4_ISR_RXPE)
1836 if (isr & EMAC4_ISR_TXUE)
1838 if (isr & EMAC4_ISR_RXOE)
1839 ++st->rx_fifo_overrun;
1840 if (isr & EMAC_ISR_OVR)
1842 if (isr & EMAC_ISR_BP)
1843 ++st->rx_bad_packet;
1844 if (isr & EMAC_ISR_RP)
1845 ++st->rx_runt_packet;
1846 if (isr & EMAC_ISR_SE)
1847 ++st->rx_short_event;
1848 if (isr & EMAC_ISR_ALE)
1849 ++st->rx_alignment_error;
1850 if (isr & EMAC_ISR_BFCS)
1852 if (isr & EMAC_ISR_PTLE)
1853 ++st->rx_packet_too_long;
1854 if (isr & EMAC_ISR_ORE)
1855 ++st->rx_out_of_range;
1856 if (isr & EMAC_ISR_IRE)
1858 if (isr & EMAC_ISR_SQE)
1860 if (isr & EMAC_ISR_TE)
1863 spin_unlock(&dev->lock);
1868 static struct net_device_stats *emac_stats(struct net_device *ndev)
1870 struct emac_instance *dev = netdev_priv(ndev);
1871 struct emac_stats *st = &dev->stats;
1872 struct emac_error_stats *est = &dev->estats;
1873 struct net_device_stats *nst = &dev->nstats;
1874 unsigned long flags;
1876 DBG2(dev, "stats" NL);
1878 /* Compute "legacy" statistics */
1879 spin_lock_irqsave(&dev->lock, flags);
1880 nst->rx_packets = (unsigned long)st->rx_packets;
1881 nst->rx_bytes = (unsigned long)st->rx_bytes;
1882 nst->tx_packets = (unsigned long)st->tx_packets;
1883 nst->tx_bytes = (unsigned long)st->tx_bytes;
1884 nst->rx_dropped = (unsigned long)(est->rx_dropped_oom +
1885 est->rx_dropped_error +
1886 est->rx_dropped_resize +
1887 est->rx_dropped_mtu);
1888 nst->tx_dropped = (unsigned long)est->tx_dropped;
1890 nst->rx_errors = (unsigned long)est->rx_bd_errors;
1891 nst->rx_fifo_errors = (unsigned long)(est->rx_bd_overrun +
1892 est->rx_fifo_overrun +
1894 nst->rx_frame_errors = (unsigned long)(est->rx_bd_alignment_error +
1895 est->rx_alignment_error);
1896 nst->rx_crc_errors = (unsigned long)(est->rx_bd_bad_fcs +
1898 nst->rx_length_errors = (unsigned long)(est->rx_bd_runt_packet +
1899 est->rx_bd_short_event +
1900 est->rx_bd_packet_too_long +
1901 est->rx_bd_out_of_range +
1902 est->rx_bd_in_range +
1903 est->rx_runt_packet +
1904 est->rx_short_event +
1905 est->rx_packet_too_long +
1906 est->rx_out_of_range +
1909 nst->tx_errors = (unsigned long)(est->tx_bd_errors + est->tx_errors);
1910 nst->tx_fifo_errors = (unsigned long)(est->tx_bd_underrun +
1912 nst->tx_carrier_errors = (unsigned long)est->tx_bd_carrier_loss;
1913 nst->collisions = (unsigned long)(est->tx_bd_excessive_deferral +
1914 est->tx_bd_excessive_collisions +
1915 est->tx_bd_late_collision +
1916 est->tx_bd_multple_collisions);
1917 spin_unlock_irqrestore(&dev->lock, flags);
1921 static struct mal_commac_ops emac_commac_ops = {
1922 .poll_tx = &emac_poll_tx,
1923 .poll_rx = &emac_poll_rx,
1924 .peek_rx = &emac_peek_rx,
1928 static struct mal_commac_ops emac_commac_sg_ops = {
1929 .poll_tx = &emac_poll_tx,
1930 .poll_rx = &emac_poll_rx,
1931 .peek_rx = &emac_peek_rx_sg,
1935 /* Ethtool support */
1936 static int emac_ethtool_get_settings(struct net_device *ndev,
1937 struct ethtool_cmd *cmd)
1939 struct emac_instance *dev = netdev_priv(ndev);
1941 cmd->supported = dev->phy.features;
1942 cmd->port = PORT_MII;
1943 cmd->phy_address = dev->phy.address;
1945 dev->phy.address >= 0 ? XCVR_EXTERNAL : XCVR_INTERNAL;
1947 mutex_lock(&dev->link_lock);
1948 cmd->advertising = dev->phy.advertising;
1949 cmd->autoneg = dev->phy.autoneg;
1950 cmd->speed = dev->phy.speed;
1951 cmd->duplex = dev->phy.duplex;
1952 mutex_unlock(&dev->link_lock);
1957 static int emac_ethtool_set_settings(struct net_device *ndev,
1958 struct ethtool_cmd *cmd)
1960 struct emac_instance *dev = netdev_priv(ndev);
1961 u32 f = dev->phy.features;
1963 DBG(dev, "set_settings(%d, %d, %d, 0x%08x)" NL,
1964 cmd->autoneg, cmd->speed, cmd->duplex, cmd->advertising);
1966 /* Basic sanity checks */
1967 if (dev->phy.address < 0)
1969 if (cmd->autoneg != AUTONEG_ENABLE && cmd->autoneg != AUTONEG_DISABLE)
1971 if (cmd->autoneg == AUTONEG_ENABLE && cmd->advertising == 0)
1973 if (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL)
1976 if (cmd->autoneg == AUTONEG_DISABLE) {
1977 switch (cmd->speed) {
1979 if (cmd->duplex == DUPLEX_HALF &&
1980 !(f & SUPPORTED_10baseT_Half))
1982 if (cmd->duplex == DUPLEX_FULL &&
1983 !(f & SUPPORTED_10baseT_Full))
1987 if (cmd->duplex == DUPLEX_HALF &&
1988 !(f & SUPPORTED_100baseT_Half))
1990 if (cmd->duplex == DUPLEX_FULL &&
1991 !(f & SUPPORTED_100baseT_Full))
1995 if (cmd->duplex == DUPLEX_HALF &&
1996 !(f & SUPPORTED_1000baseT_Half))
1998 if (cmd->duplex == DUPLEX_FULL &&
1999 !(f & SUPPORTED_1000baseT_Full))
2006 mutex_lock(&dev->link_lock);
2007 dev->phy.def->ops->setup_forced(&dev->phy, cmd->speed,
2009 mutex_unlock(&dev->link_lock);
2012 if (!(f & SUPPORTED_Autoneg))
2015 mutex_lock(&dev->link_lock);
2016 dev->phy.def->ops->setup_aneg(&dev->phy,
2017 (cmd->advertising & f) |
2018 (dev->phy.advertising &
2020 ADVERTISED_Asym_Pause)));
2021 mutex_unlock(&dev->link_lock);
2023 emac_force_link_update(dev);
2028 static void emac_ethtool_get_ringparam(struct net_device *ndev,
2029 struct ethtool_ringparam *rp)
2031 rp->rx_max_pending = rp->rx_pending = NUM_RX_BUFF;
2032 rp->tx_max_pending = rp->tx_pending = NUM_TX_BUFF;
2035 static void emac_ethtool_get_pauseparam(struct net_device *ndev,
2036 struct ethtool_pauseparam *pp)
2038 struct emac_instance *dev = netdev_priv(ndev);
2040 mutex_lock(&dev->link_lock);
2041 if ((dev->phy.features & SUPPORTED_Autoneg) &&
2042 (dev->phy.advertising & (ADVERTISED_Pause | ADVERTISED_Asym_Pause)))
2045 if (dev->phy.duplex == DUPLEX_FULL) {
2047 pp->rx_pause = pp->tx_pause = 1;
2048 else if (dev->phy.asym_pause)
2051 mutex_unlock(&dev->link_lock);
2054 static u32 emac_ethtool_get_rx_csum(struct net_device *ndev)
2056 struct emac_instance *dev = netdev_priv(ndev);
2058 return dev->tah_dev != NULL;
2061 static int emac_get_regs_len(struct emac_instance *dev)
2063 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
2064 return sizeof(struct emac_ethtool_regs_subhdr) +
2065 EMAC4_ETHTOOL_REGS_SIZE(dev);
2067 return sizeof(struct emac_ethtool_regs_subhdr) +
2068 EMAC_ETHTOOL_REGS_SIZE(dev);
2071 static int emac_ethtool_get_regs_len(struct net_device *ndev)
2073 struct emac_instance *dev = netdev_priv(ndev);
2076 size = sizeof(struct emac_ethtool_regs_hdr) +
2077 emac_get_regs_len(dev) + mal_get_regs_len(dev->mal);
2078 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
2079 size += zmii_get_regs_len(dev->zmii_dev);
2080 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
2081 size += rgmii_get_regs_len(dev->rgmii_dev);
2082 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
2083 size += tah_get_regs_len(dev->tah_dev);
2088 static void *emac_dump_regs(struct emac_instance *dev, void *buf)
2090 struct emac_ethtool_regs_subhdr *hdr = buf;
2092 hdr->index = dev->cell_index;
2093 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) {
2094 hdr->version = EMAC4_ETHTOOL_REGS_VER;
2095 memcpy_fromio(hdr + 1, dev->emacp, EMAC4_ETHTOOL_REGS_SIZE(dev));
2096 return ((void *)(hdr + 1) + EMAC4_ETHTOOL_REGS_SIZE(dev));
2098 hdr->version = EMAC_ETHTOOL_REGS_VER;
2099 memcpy_fromio(hdr + 1, dev->emacp, EMAC_ETHTOOL_REGS_SIZE(dev));
2100 return ((void *)(hdr + 1) + EMAC_ETHTOOL_REGS_SIZE(dev));
2104 static void emac_ethtool_get_regs(struct net_device *ndev,
2105 struct ethtool_regs *regs, void *buf)
2107 struct emac_instance *dev = netdev_priv(ndev);
2108 struct emac_ethtool_regs_hdr *hdr = buf;
2110 hdr->components = 0;
2113 buf = mal_dump_regs(dev->mal, buf);
2114 buf = emac_dump_regs(dev, buf);
2115 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) {
2116 hdr->components |= EMAC_ETHTOOL_REGS_ZMII;
2117 buf = zmii_dump_regs(dev->zmii_dev, buf);
2119 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) {
2120 hdr->components |= EMAC_ETHTOOL_REGS_RGMII;
2121 buf = rgmii_dump_regs(dev->rgmii_dev, buf);
2123 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) {
2124 hdr->components |= EMAC_ETHTOOL_REGS_TAH;
2125 buf = tah_dump_regs(dev->tah_dev, buf);
2129 static int emac_ethtool_nway_reset(struct net_device *ndev)
2131 struct emac_instance *dev = netdev_priv(ndev);
2134 DBG(dev, "nway_reset" NL);
2136 if (dev->phy.address < 0)
2139 mutex_lock(&dev->link_lock);
2140 if (!dev->phy.autoneg) {
2145 dev->phy.def->ops->setup_aneg(&dev->phy, dev->phy.advertising);
2147 mutex_unlock(&dev->link_lock);
2148 emac_force_link_update(dev);
2152 static int emac_ethtool_get_sset_count(struct net_device *ndev, int stringset)
2154 if (stringset == ETH_SS_STATS)
2155 return EMAC_ETHTOOL_STATS_COUNT;
2160 static void emac_ethtool_get_strings(struct net_device *ndev, u32 stringset,
2163 if (stringset == ETH_SS_STATS)
2164 memcpy(buf, &emac_stats_keys, sizeof(emac_stats_keys));
2167 static void emac_ethtool_get_ethtool_stats(struct net_device *ndev,
2168 struct ethtool_stats *estats,
2171 struct emac_instance *dev = netdev_priv(ndev);
2173 memcpy(tmp_stats, &dev->stats, sizeof(dev->stats));
2174 tmp_stats += sizeof(dev->stats) / sizeof(u64);
2175 memcpy(tmp_stats, &dev->estats, sizeof(dev->estats));
2178 static void emac_ethtool_get_drvinfo(struct net_device *ndev,
2179 struct ethtool_drvinfo *info)
2181 struct emac_instance *dev = netdev_priv(ndev);
2183 strcpy(info->driver, "ibm_emac");
2184 strcpy(info->version, DRV_VERSION);
2185 info->fw_version[0] = '\0';
2186 sprintf(info->bus_info, "PPC 4xx EMAC-%d %s",
2187 dev->cell_index, dev->ofdev->node->full_name);
2188 info->regdump_len = emac_ethtool_get_regs_len(ndev);
2191 static const struct ethtool_ops emac_ethtool_ops = {
2192 .get_settings = emac_ethtool_get_settings,
2193 .set_settings = emac_ethtool_set_settings,
2194 .get_drvinfo = emac_ethtool_get_drvinfo,
2196 .get_regs_len = emac_ethtool_get_regs_len,
2197 .get_regs = emac_ethtool_get_regs,
2199 .nway_reset = emac_ethtool_nway_reset,
2201 .get_ringparam = emac_ethtool_get_ringparam,
2202 .get_pauseparam = emac_ethtool_get_pauseparam,
2204 .get_rx_csum = emac_ethtool_get_rx_csum,
2206 .get_strings = emac_ethtool_get_strings,
2207 .get_sset_count = emac_ethtool_get_sset_count,
2208 .get_ethtool_stats = emac_ethtool_get_ethtool_stats,
2210 .get_link = ethtool_op_get_link,
2211 .get_tx_csum = ethtool_op_get_tx_csum,
2212 .get_sg = ethtool_op_get_sg,
2215 static int emac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2217 struct emac_instance *dev = netdev_priv(ndev);
2218 struct mii_ioctl_data *data = if_mii(rq);
2220 DBG(dev, "ioctl %08x" NL, cmd);
2222 if (dev->phy.address < 0)
2227 data->phy_id = dev->phy.address;
2230 data->val_out = emac_mdio_read(ndev, dev->phy.address,
2235 emac_mdio_write(ndev, dev->phy.address, data->reg_num,
2243 struct emac_depentry {
2245 struct device_node *node;
2246 struct of_device *ofdev;
2250 #define EMAC_DEP_MAL_IDX 0
2251 #define EMAC_DEP_ZMII_IDX 1
2252 #define EMAC_DEP_RGMII_IDX 2
2253 #define EMAC_DEP_TAH_IDX 3
2254 #define EMAC_DEP_MDIO_IDX 4
2255 #define EMAC_DEP_PREV_IDX 5
2256 #define EMAC_DEP_COUNT 6
2258 static int __devinit emac_check_deps(struct emac_instance *dev,
2259 struct emac_depentry *deps)
2262 struct device_node *np;
2264 for (i = 0; i < EMAC_DEP_COUNT; i++) {
2265 /* no dependency on that item, allright */
2266 if (deps[i].phandle == 0) {
2270 /* special case for blist as the dependency might go away */
2271 if (i == EMAC_DEP_PREV_IDX) {
2272 np = *(dev->blist - 1);
2274 deps[i].phandle = 0;
2278 if (deps[i].node == NULL)
2279 deps[i].node = of_node_get(np);
2281 if (deps[i].node == NULL)
2282 deps[i].node = of_find_node_by_phandle(deps[i].phandle);
2283 if (deps[i].node == NULL)
2285 if (deps[i].ofdev == NULL)
2286 deps[i].ofdev = of_find_device_by_node(deps[i].node);
2287 if (deps[i].ofdev == NULL)
2289 if (deps[i].drvdata == NULL)
2290 deps[i].drvdata = dev_get_drvdata(&deps[i].ofdev->dev);
2291 if (deps[i].drvdata != NULL)
2294 return (there == EMAC_DEP_COUNT);
2297 static void emac_put_deps(struct emac_instance *dev)
2300 of_dev_put(dev->mal_dev);
2302 of_dev_put(dev->zmii_dev);
2304 of_dev_put(dev->rgmii_dev);
2306 of_dev_put(dev->mdio_dev);
2308 of_dev_put(dev->tah_dev);
2311 static int __devinit emac_of_bus_notify(struct notifier_block *nb,
2312 unsigned long action, void *data)
2314 /* We are only intereted in device addition */
2315 if (action == BUS_NOTIFY_BOUND_DRIVER)
2316 wake_up_all(&emac_probe_wait);
2320 static struct notifier_block emac_of_bus_notifier __devinitdata = {
2321 .notifier_call = emac_of_bus_notify
2324 static int __devinit emac_wait_deps(struct emac_instance *dev)
2326 struct emac_depentry deps[EMAC_DEP_COUNT];
2329 memset(&deps, 0, sizeof(deps));
2331 deps[EMAC_DEP_MAL_IDX].phandle = dev->mal_ph;
2332 deps[EMAC_DEP_ZMII_IDX].phandle = dev->zmii_ph;
2333 deps[EMAC_DEP_RGMII_IDX].phandle = dev->rgmii_ph;
2335 deps[EMAC_DEP_TAH_IDX].phandle = dev->tah_ph;
2337 deps[EMAC_DEP_MDIO_IDX].phandle = dev->mdio_ph;
2338 if (dev->blist && dev->blist > emac_boot_list)
2339 deps[EMAC_DEP_PREV_IDX].phandle = 0xffffffffu;
2340 bus_register_notifier(&of_platform_bus_type, &emac_of_bus_notifier);
2341 wait_event_timeout(emac_probe_wait,
2342 emac_check_deps(dev, deps),
2343 EMAC_PROBE_DEP_TIMEOUT);
2344 bus_unregister_notifier(&of_platform_bus_type, &emac_of_bus_notifier);
2345 err = emac_check_deps(dev, deps) ? 0 : -ENODEV;
2346 for (i = 0; i < EMAC_DEP_COUNT; i++) {
2348 of_node_put(deps[i].node);
2349 if (err && deps[i].ofdev)
2350 of_dev_put(deps[i].ofdev);
2353 dev->mal_dev = deps[EMAC_DEP_MAL_IDX].ofdev;
2354 dev->zmii_dev = deps[EMAC_DEP_ZMII_IDX].ofdev;
2355 dev->rgmii_dev = deps[EMAC_DEP_RGMII_IDX].ofdev;
2356 dev->tah_dev = deps[EMAC_DEP_TAH_IDX].ofdev;
2357 dev->mdio_dev = deps[EMAC_DEP_MDIO_IDX].ofdev;
2359 if (deps[EMAC_DEP_PREV_IDX].ofdev)
2360 of_dev_put(deps[EMAC_DEP_PREV_IDX].ofdev);
2364 static int __devinit emac_read_uint_prop(struct device_node *np, const char *name,
2365 u32 *val, int fatal)
2368 const u32 *prop = of_get_property(np, name, &len);
2369 if (prop == NULL || len < sizeof(u32)) {
2371 printk(KERN_ERR "%s: missing %s property\n",
2372 np->full_name, name);
2379 static int __devinit emac_init_phy(struct emac_instance *dev)
2381 struct device_node *np = dev->ofdev->node;
2382 struct net_device *ndev = dev->ndev;
2386 dev->phy.dev = ndev;
2387 dev->phy.mode = dev->phy_mode;
2389 /* PHY-less configuration.
2390 * XXX I probably should move these settings to the dev tree
2392 if (dev->phy_address == 0xffffffff && dev->phy_map == 0xffffffff) {
2395 /* PHY-less configuration.
2396 * XXX I probably should move these settings to the dev tree
2398 dev->phy.address = -1;
2399 dev->phy.features = SUPPORTED_MII;
2400 if (emac_phy_supports_gige(dev->phy_mode))
2401 dev->phy.features |= SUPPORTED_1000baseT_Full;
2403 dev->phy.features |= SUPPORTED_100baseT_Full;
2409 mutex_lock(&emac_phy_map_lock);
2410 phy_map = dev->phy_map | busy_phy_map;
2412 DBG(dev, "PHY maps %08x %08x" NL, dev->phy_map, busy_phy_map);
2414 dev->phy.mdio_read = emac_mdio_read;
2415 dev->phy.mdio_write = emac_mdio_write;
2417 /* Enable internal clock source */
2418 #ifdef CONFIG_PPC_DCR_NATIVE
2419 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2420 dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS);
2422 /* PHY clock workaround */
2423 emac_rx_clk_tx(dev);
2425 /* Enable internal clock source on 440GX*/
2426 #ifdef CONFIG_PPC_DCR_NATIVE
2427 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2428 dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS);
2430 /* Configure EMAC with defaults so we can at least use MDIO
2431 * This is needed mostly for 440GX
2433 if (emac_phy_gpcs(dev->phy.mode)) {
2435 * Make GPCS PHY address equal to EMAC index.
2436 * We probably should take into account busy_phy_map
2437 * and/or phy_map here.
2439 * Note that the busy_phy_map is currently global
2440 * while it should probably be per-ASIC...
2442 dev->phy.gpcs_address = dev->gpcs_address;
2443 if (dev->phy.gpcs_address == 0xffffffff)
2444 dev->phy.address = dev->cell_index;
2447 emac_configure(dev);
2449 if (dev->phy_address != 0xffffffff)
2450 phy_map = ~(1 << dev->phy_address);
2452 for (i = 0; i < 0x20; phy_map >>= 1, ++i)
2453 if (!(phy_map & 1)) {
2455 busy_phy_map |= 1 << i;
2457 /* Quick check if there is a PHY at the address */
2458 r = emac_mdio_read(dev->ndev, i, MII_BMCR);
2459 if (r == 0xffff || r < 0)
2461 if (!emac_mii_phy_probe(&dev->phy, i))
2465 /* Enable external clock source */
2466 #ifdef CONFIG_PPC_DCR_NATIVE
2467 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2468 dcri_clrset(SDR0, SDR0_MFR, SDR0_MFR_ECS, 0);
2470 mutex_unlock(&emac_phy_map_lock);
2472 printk(KERN_WARNING "%s: can't find PHY!\n", np->full_name);
2477 if (dev->phy.def->ops->init)
2478 dev->phy.def->ops->init(&dev->phy);
2480 /* Disable any PHY features not supported by the platform */
2481 dev->phy.def->features &= ~dev->phy_feat_exc;
2483 /* Setup initial link parameters */
2484 if (dev->phy.features & SUPPORTED_Autoneg) {
2485 adv = dev->phy.features;
2486 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x))
2487 adv |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
2488 /* Restart autonegotiation */
2489 dev->phy.def->ops->setup_aneg(&dev->phy, adv);
2491 u32 f = dev->phy.def->features;
2492 int speed = SPEED_10, fd = DUPLEX_HALF;
2494 /* Select highest supported speed/duplex */
2495 if (f & SUPPORTED_1000baseT_Full) {
2498 } else if (f & SUPPORTED_1000baseT_Half)
2500 else if (f & SUPPORTED_100baseT_Full) {
2503 } else if (f & SUPPORTED_100baseT_Half)
2505 else if (f & SUPPORTED_10baseT_Full)
2508 /* Force link parameters */
2509 dev->phy.def->ops->setup_forced(&dev->phy, speed, fd);
2514 static int __devinit emac_init_config(struct emac_instance *dev)
2516 struct device_node *np = dev->ofdev->node;
2519 const char *pm, *phy_modes[] = {
2521 [PHY_MODE_MII] = "mii",
2522 [PHY_MODE_RMII] = "rmii",
2523 [PHY_MODE_SMII] = "smii",
2524 [PHY_MODE_RGMII] = "rgmii",
2525 [PHY_MODE_TBI] = "tbi",
2526 [PHY_MODE_GMII] = "gmii",
2527 [PHY_MODE_RTBI] = "rtbi",
2528 [PHY_MODE_SGMII] = "sgmii",
2531 /* Read config from device-tree */
2532 if (emac_read_uint_prop(np, "mal-device", &dev->mal_ph, 1))
2534 if (emac_read_uint_prop(np, "mal-tx-channel", &dev->mal_tx_chan, 1))
2536 if (emac_read_uint_prop(np, "mal-rx-channel", &dev->mal_rx_chan, 1))
2538 if (emac_read_uint_prop(np, "cell-index", &dev->cell_index, 1))
2540 if (emac_read_uint_prop(np, "max-frame-size", &dev->max_mtu, 0))
2541 dev->max_mtu = 1500;
2542 if (emac_read_uint_prop(np, "rx-fifo-size", &dev->rx_fifo_size, 0))
2543 dev->rx_fifo_size = 2048;
2544 if (emac_read_uint_prop(np, "tx-fifo-size", &dev->tx_fifo_size, 0))
2545 dev->tx_fifo_size = 2048;
2546 if (emac_read_uint_prop(np, "rx-fifo-size-gige", &dev->rx_fifo_size_gige, 0))
2547 dev->rx_fifo_size_gige = dev->rx_fifo_size;
2548 if (emac_read_uint_prop(np, "tx-fifo-size-gige", &dev->tx_fifo_size_gige, 0))
2549 dev->tx_fifo_size_gige = dev->tx_fifo_size;
2550 if (emac_read_uint_prop(np, "phy-address", &dev->phy_address, 0))
2551 dev->phy_address = 0xffffffff;
2552 if (emac_read_uint_prop(np, "phy-map", &dev->phy_map, 0))
2553 dev->phy_map = 0xffffffff;
2554 if (emac_read_uint_prop(np, "gpcs-address", &dev->gpcs_address, 0))
2555 dev->gpcs_address = 0xffffffff;
2556 if (emac_read_uint_prop(np->parent, "clock-frequency", &dev->opb_bus_freq, 1))
2558 if (emac_read_uint_prop(np, "tah-device", &dev->tah_ph, 0))
2560 if (emac_read_uint_prop(np, "tah-channel", &dev->tah_port, 0))
2562 if (emac_read_uint_prop(np, "mdio-device", &dev->mdio_ph, 0))
2564 if (emac_read_uint_prop(np, "zmii-device", &dev->zmii_ph, 0))
2566 if (emac_read_uint_prop(np, "zmii-channel", &dev->zmii_port, 0))
2567 dev->zmii_port = 0xffffffff;
2568 if (emac_read_uint_prop(np, "rgmii-device", &dev->rgmii_ph, 0))
2570 if (emac_read_uint_prop(np, "rgmii-channel", &dev->rgmii_port, 0))
2571 dev->rgmii_port = 0xffffffff;
2572 if (emac_read_uint_prop(np, "fifo-entry-size", &dev->fifo_entry_size, 0))
2573 dev->fifo_entry_size = 16;
2574 if (emac_read_uint_prop(np, "mal-burst-size", &dev->mal_burst_size, 0))
2575 dev->mal_burst_size = 256;
2577 /* PHY mode needs some decoding */
2578 dev->phy_mode = PHY_MODE_NA;
2579 pm = of_get_property(np, "phy-mode", &plen);
2582 for (i = 0; i < ARRAY_SIZE(phy_modes); i++)
2583 if (!strcasecmp(pm, phy_modes[i])) {
2589 /* Backward compat with non-final DT */
2590 if (dev->phy_mode == PHY_MODE_NA && pm != NULL && plen == 4) {
2591 u32 nmode = *(const u32 *)pm;
2592 if (nmode > PHY_MODE_NA && nmode <= PHY_MODE_SGMII)
2593 dev->phy_mode = nmode;
2596 /* Check EMAC version */
2597 if (of_device_is_compatible(np, "ibm,emac4sync")) {
2598 dev->features |= (EMAC_FTR_EMAC4 | EMAC_FTR_EMAC4SYNC);
2599 if (of_device_is_compatible(np, "ibm,emac-460ex") ||
2600 of_device_is_compatible(np, "ibm,emac-460gt"))
2601 dev->features |= EMAC_FTR_460EX_PHY_CLK_FIX;
2602 if (of_device_is_compatible(np, "ibm,emac-405ex") ||
2603 of_device_is_compatible(np, "ibm,emac-405exr"))
2604 dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX;
2605 } else if (of_device_is_compatible(np, "ibm,emac4")) {
2606 dev->features |= EMAC_FTR_EMAC4;
2607 if (of_device_is_compatible(np, "ibm,emac-440gx"))
2608 dev->features |= EMAC_FTR_440GX_PHY_CLK_FIX;
2610 if (of_device_is_compatible(np, "ibm,emac-440ep") ||
2611 of_device_is_compatible(np, "ibm,emac-440gr"))
2612 dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX;
2613 if (of_device_is_compatible(np, "ibm,emac-405ez")) {
2614 #ifdef CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL
2615 dev->features |= EMAC_FTR_NO_FLOW_CONTROL_40x;
2617 printk(KERN_ERR "%s: Flow control not disabled!\n",
2625 /* Fixup some feature bits based on the device tree */
2626 if (of_get_property(np, "has-inverted-stacr-oc", NULL))
2627 dev->features |= EMAC_FTR_STACR_OC_INVERT;
2628 if (of_get_property(np, "has-new-stacr-staopc", NULL))
2629 dev->features |= EMAC_FTR_HAS_NEW_STACR;
2631 /* CAB lacks the appropriate properties */
2632 if (of_device_is_compatible(np, "ibm,emac-axon"))
2633 dev->features |= EMAC_FTR_HAS_NEW_STACR |
2634 EMAC_FTR_STACR_OC_INVERT;
2636 /* Enable TAH/ZMII/RGMII features as found */
2637 if (dev->tah_ph != 0) {
2638 #ifdef CONFIG_IBM_NEW_EMAC_TAH
2639 dev->features |= EMAC_FTR_HAS_TAH;
2641 printk(KERN_ERR "%s: TAH support not enabled !\n",
2647 if (dev->zmii_ph != 0) {
2648 #ifdef CONFIG_IBM_NEW_EMAC_ZMII
2649 dev->features |= EMAC_FTR_HAS_ZMII;
2651 printk(KERN_ERR "%s: ZMII support not enabled !\n",
2657 if (dev->rgmii_ph != 0) {
2658 #ifdef CONFIG_IBM_NEW_EMAC_RGMII
2659 dev->features |= EMAC_FTR_HAS_RGMII;
2661 printk(KERN_ERR "%s: RGMII support not enabled !\n",
2667 /* Read MAC-address */
2668 p = of_get_property(np, "local-mac-address", NULL);
2670 printk(KERN_ERR "%s: Can't find local-mac-address property\n",
2674 memcpy(dev->ndev->dev_addr, p, 6);
2676 /* IAHT and GAHT filter parameterization */
2677 if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) {
2678 dev->xaht_slots_shift = EMAC4SYNC_XAHT_SLOTS_SHIFT;
2679 dev->xaht_width_shift = EMAC4SYNC_XAHT_WIDTH_SHIFT;
2681 dev->xaht_slots_shift = EMAC4_XAHT_SLOTS_SHIFT;
2682 dev->xaht_width_shift = EMAC4_XAHT_WIDTH_SHIFT;
2685 DBG(dev, "features : 0x%08x / 0x%08x\n", dev->features, EMAC_FTRS_POSSIBLE);
2686 DBG(dev, "tx_fifo_size : %d (%d gige)\n", dev->tx_fifo_size, dev->tx_fifo_size_gige);
2687 DBG(dev, "rx_fifo_size : %d (%d gige)\n", dev->rx_fifo_size, dev->rx_fifo_size_gige);
2688 DBG(dev, "max_mtu : %d\n", dev->max_mtu);
2689 DBG(dev, "OPB freq : %d\n", dev->opb_bus_freq);
2694 static const struct net_device_ops emac_netdev_ops = {
2695 .ndo_open = emac_open,
2696 .ndo_stop = emac_close,
2697 .ndo_get_stats = emac_stats,
2698 .ndo_set_multicast_list = emac_set_multicast_list,
2699 .ndo_do_ioctl = emac_ioctl,
2700 .ndo_tx_timeout = emac_tx_timeout,
2701 .ndo_validate_addr = eth_validate_addr,
2702 .ndo_set_mac_address = eth_mac_addr,
2703 .ndo_start_xmit = emac_start_xmit,
2704 .ndo_change_mtu = eth_change_mtu,
2707 static const struct net_device_ops emac_gige_netdev_ops = {
2708 .ndo_open = emac_open,
2709 .ndo_stop = emac_close,
2710 .ndo_get_stats = emac_stats,
2711 .ndo_set_multicast_list = emac_set_multicast_list,
2712 .ndo_do_ioctl = emac_ioctl,
2713 .ndo_tx_timeout = emac_tx_timeout,
2714 .ndo_validate_addr = eth_validate_addr,
2715 .ndo_set_mac_address = eth_mac_addr,
2716 .ndo_start_xmit = emac_start_xmit_sg,
2717 .ndo_change_mtu = emac_change_mtu,
2720 static int __devinit emac_probe(struct of_device *ofdev,
2721 const struct of_device_id *match)
2723 struct net_device *ndev;
2724 struct emac_instance *dev;
2725 struct device_node *np = ofdev->node;
2726 struct device_node **blist = NULL;
2729 /* Skip unused/unwired EMACS. We leave the check for an unused
2730 * property here for now, but new flat device trees should set a
2731 * status property to "disabled" instead.
2733 if (of_get_property(np, "unused", NULL) || !of_device_is_available(np))
2736 /* Find ourselves in the bootlist if we are there */
2737 for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++)
2738 if (emac_boot_list[i] == np)
2739 blist = &emac_boot_list[i];
2741 /* Allocate our net_device structure */
2743 ndev = alloc_etherdev(sizeof(struct emac_instance));
2745 printk(KERN_ERR "%s: could not allocate ethernet device!\n",
2749 dev = netdev_priv(ndev);
2753 SET_NETDEV_DEV(ndev, &ofdev->dev);
2755 /* Initialize some embedded data structures */
2756 mutex_init(&dev->mdio_lock);
2757 mutex_init(&dev->link_lock);
2758 spin_lock_init(&dev->lock);
2759 INIT_WORK(&dev->reset_work, emac_reset_work);
2761 /* Init various config data based on device-tree */
2762 err = emac_init_config(dev);
2766 /* Get interrupts. EMAC irq is mandatory, WOL irq is optional */
2767 dev->emac_irq = irq_of_parse_and_map(np, 0);
2768 dev->wol_irq = irq_of_parse_and_map(np, 1);
2769 if (dev->emac_irq == NO_IRQ) {
2770 printk(KERN_ERR "%s: Can't map main interrupt\n", np->full_name);
2773 ndev->irq = dev->emac_irq;
2776 if (of_address_to_resource(np, 0, &dev->rsrc_regs)) {
2777 printk(KERN_ERR "%s: Can't get registers address\n",
2781 // TODO : request_mem_region
2782 dev->emacp = ioremap(dev->rsrc_regs.start,
2783 dev->rsrc_regs.end - dev->rsrc_regs.start + 1);
2784 if (dev->emacp == NULL) {
2785 printk(KERN_ERR "%s: Can't map device registers!\n",
2791 /* Wait for dependent devices */
2792 err = emac_wait_deps(dev);
2795 "%s: Timeout waiting for dependent devices\n",
2797 /* display more info about what's missing ? */
2800 dev->mal = dev_get_drvdata(&dev->mal_dev->dev);
2801 if (dev->mdio_dev != NULL)
2802 dev->mdio_instance = dev_get_drvdata(&dev->mdio_dev->dev);
2804 /* Register with MAL */
2805 dev->commac.ops = &emac_commac_ops;
2806 dev->commac.dev = dev;
2807 dev->commac.tx_chan_mask = MAL_CHAN_MASK(dev->mal_tx_chan);
2808 dev->commac.rx_chan_mask = MAL_CHAN_MASK(dev->mal_rx_chan);
2809 err = mal_register_commac(dev->mal, &dev->commac);
2811 printk(KERN_ERR "%s: failed to register with mal %s!\n",
2812 np->full_name, dev->mal_dev->node->full_name);
2815 dev->rx_skb_size = emac_rx_skb_size(ndev->mtu);
2816 dev->rx_sync_size = emac_rx_sync_size(ndev->mtu);
2818 /* Get pointers to BD rings */
2820 dev->mal->bd_virt + mal_tx_bd_offset(dev->mal, dev->mal_tx_chan);
2822 dev->mal->bd_virt + mal_rx_bd_offset(dev->mal, dev->mal_rx_chan);
2824 DBG(dev, "tx_desc %p" NL, dev->tx_desc);
2825 DBG(dev, "rx_desc %p" NL, dev->rx_desc);
2828 memset(dev->tx_desc, 0, NUM_TX_BUFF * sizeof(struct mal_descriptor));
2829 memset(dev->rx_desc, 0, NUM_RX_BUFF * sizeof(struct mal_descriptor));
2830 memset(dev->tx_skb, 0, NUM_TX_BUFF * sizeof(struct sk_buff *));
2831 memset(dev->rx_skb, 0, NUM_RX_BUFF * sizeof(struct sk_buff *));
2833 /* Attach to ZMII, if needed */
2834 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII) &&
2835 (err = zmii_attach(dev->zmii_dev, dev->zmii_port, &dev->phy_mode)) != 0)
2836 goto err_unreg_commac;
2838 /* Attach to RGMII, if needed */
2839 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII) &&
2840 (err = rgmii_attach(dev->rgmii_dev, dev->rgmii_port, dev->phy_mode)) != 0)
2841 goto err_detach_zmii;
2843 /* Attach to TAH, if needed */
2844 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) &&
2845 (err = tah_attach(dev->tah_dev, dev->tah_port)) != 0)
2846 goto err_detach_rgmii;
2848 /* Set some link defaults before we can find out real parameters */
2849 dev->phy.speed = SPEED_100;
2850 dev->phy.duplex = DUPLEX_FULL;
2851 dev->phy.autoneg = AUTONEG_DISABLE;
2852 dev->phy.pause = dev->phy.asym_pause = 0;
2853 dev->stop_timeout = STOP_TIMEOUT_100;
2854 INIT_DELAYED_WORK(&dev->link_work, emac_link_timer);
2856 /* Find PHY if any */
2857 err = emac_init_phy(dev);
2859 goto err_detach_tah;
2862 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
2863 ndev->watchdog_timeo = 5 * HZ;
2864 if (emac_phy_supports_gige(dev->phy_mode)) {
2865 ndev->netdev_ops = &emac_gige_netdev_ops;
2866 dev->commac.ops = &emac_commac_sg_ops;
2868 ndev->netdev_ops = &emac_netdev_ops;
2869 SET_ETHTOOL_OPS(ndev, &emac_ethtool_ops);
2871 netif_carrier_off(ndev);
2872 netif_stop_queue(ndev);
2874 err = register_netdev(ndev);
2876 printk(KERN_ERR "%s: failed to register net device (%d)!\n",
2877 np->full_name, err);
2878 goto err_detach_tah;
2881 /* Set our drvdata last as we don't want them visible until we are
2885 dev_set_drvdata(&ofdev->dev, dev);
2887 /* There's a new kid in town ! Let's tell everybody */
2888 wake_up_all(&emac_probe_wait);
2891 printk(KERN_INFO "%s: EMAC-%d %s, MAC %pM\n",
2892 ndev->name, dev->cell_index, np->full_name, ndev->dev_addr);
2894 if (dev->phy_mode == PHY_MODE_SGMII)
2895 printk(KERN_NOTICE "%s: in SGMII mode\n", ndev->name);
2897 if (dev->phy.address >= 0)
2898 printk("%s: found %s PHY (0x%02x)\n", ndev->name,
2899 dev->phy.def->name, dev->phy.address);
2901 emac_dbg_register(dev);
2906 /* I have a bad feeling about this ... */
2909 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
2910 tah_detach(dev->tah_dev, dev->tah_port);
2912 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
2913 rgmii_detach(dev->rgmii_dev, dev->rgmii_port);
2915 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
2916 zmii_detach(dev->zmii_dev, dev->zmii_port);
2918 mal_unregister_commac(dev->mal, &dev->commac);
2922 iounmap(dev->emacp);
2924 if (dev->wol_irq != NO_IRQ)
2925 irq_dispose_mapping(dev->wol_irq);
2926 if (dev->emac_irq != NO_IRQ)
2927 irq_dispose_mapping(dev->emac_irq);
2931 /* if we were on the bootlist, remove us as we won't show up and
2932 * wake up all waiters to notify them in case they were waiting
2937 wake_up_all(&emac_probe_wait);
2942 static int __devexit emac_remove(struct of_device *ofdev)
2944 struct emac_instance *dev = dev_get_drvdata(&ofdev->dev);
2946 DBG(dev, "remove" NL);
2948 dev_set_drvdata(&ofdev->dev, NULL);
2950 unregister_netdev(dev->ndev);
2952 flush_scheduled_work();
2954 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
2955 tah_detach(dev->tah_dev, dev->tah_port);
2956 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
2957 rgmii_detach(dev->rgmii_dev, dev->rgmii_port);
2958 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
2959 zmii_detach(dev->zmii_dev, dev->zmii_port);
2961 mal_unregister_commac(dev->mal, &dev->commac);
2964 emac_dbg_unregister(dev);
2965 iounmap(dev->emacp);
2967 if (dev->wol_irq != NO_IRQ)
2968 irq_dispose_mapping(dev->wol_irq);
2969 if (dev->emac_irq != NO_IRQ)
2970 irq_dispose_mapping(dev->emac_irq);
2977 /* XXX Features in here should be replaced by properties... */
2978 static struct of_device_id emac_match[] =
2982 .compatible = "ibm,emac",
2986 .compatible = "ibm,emac4",
2990 .compatible = "ibm,emac4sync",
2994 MODULE_DEVICE_TABLE(of, emac_match);
2996 static struct of_platform_driver emac_driver = {
2998 .match_table = emac_match,
3000 .probe = emac_probe,
3001 .remove = emac_remove,
3004 static void __init emac_make_bootlist(void)
3006 struct device_node *np = NULL;
3007 int j, max, i = 0, k;
3008 int cell_indices[EMAC_BOOT_LIST_SIZE];
3011 while((np = of_find_all_nodes(np)) != NULL) {
3014 if (of_match_node(emac_match, np) == NULL)
3016 if (of_get_property(np, "unused", NULL))
3018 idx = of_get_property(np, "cell-index", NULL);
3021 cell_indices[i] = *idx;
3022 emac_boot_list[i++] = of_node_get(np);
3023 if (i >= EMAC_BOOT_LIST_SIZE) {
3030 /* Bubble sort them (doh, what a creative algorithm :-) */
3031 for (i = 0; max > 1 && (i < (max - 1)); i++)
3032 for (j = i; j < max; j++) {
3033 if (cell_indices[i] > cell_indices[j]) {
3034 np = emac_boot_list[i];
3035 emac_boot_list[i] = emac_boot_list[j];
3036 emac_boot_list[j] = np;
3037 k = cell_indices[i];
3038 cell_indices[i] = cell_indices[j];
3039 cell_indices[j] = k;
3044 static int __init emac_init(void)
3048 printk(KERN_INFO DRV_DESC ", version " DRV_VERSION "\n");
3050 /* Init debug stuff */
3053 /* Build EMAC boot list */
3054 emac_make_bootlist();
3056 /* Init submodules */
3069 rc = of_register_platform_driver(&emac_driver);
3087 static void __exit emac_exit(void)
3091 of_unregister_platform_driver(&emac_driver);
3099 /* Destroy EMAC boot list */
3100 for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++)
3101 if (emac_boot_list[i])
3102 of_node_put(emac_boot_list[i]);
3105 module_init(emac_init);
3106 module_exit(emac_exit);