drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey. It's neither supported nor endorsed
   7  *      by NVIDIA Corp. Use at your own risk.
   8  *
   9  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
  10  * trademarks of NVIDIA Corporation in the United States and other
  11  * countries.
  12  *
  13  * Copyright (C) 2003,4,5 Manfred Spraul
  14  * Copyright (C) 2004 Andrew de Quincey (wol support)
  15  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  16  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  17  * Copyright (c) 2004 NVIDIA Corporation
  18  *
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License as published by
  21  * the Free Software Foundation; either version 2 of the License, or
  22  * (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  32  *
  33  * Changelog:
  34  *      0.01: 05 Oct 2003: First release that compiles without warnings.
  35  *      0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
  36  *                         Check all PCI BARs for the register window.
  37  *                         udelay added to mii_rw.
  38  *      0.03: 06 Oct 2003: Initialize dev->irq.
  39  *      0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
  40  *      0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
  41  *      0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
  42  *                         irq mask updated
  43  *      0.07: 14 Oct 2003: Further irq mask updates.
  44  *      0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
  45  *                         added into irq handler, NULL check for drain_ring.
  46  *      0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
  47  *                         requested interrupt sources.
  48  *      0.10: 20 Oct 2003: First cleanup for release.
  49  *      0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
  50  *                         MAC Address init fix, set_multicast cleanup.
  51  *      0.12: 23 Oct 2003: Cleanups for release.
  52  *      0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
  53  *                         Set link speed correctly. start rx before starting
  54  *                         tx (nv_start_rx sets the link speed).
  55  *      0.14: 25 Oct 2003: Nic dependant irq mask.
  56  *      0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
  57  *                         open.
  58  *      0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
  59  *                         increased to 1628 bytes.
  60  *      0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
  61  *                         the tx length.
  62  *      0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
  63  *      0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
  64  *                         addresses, really stop rx if already running
  65  *                         in nv_start_rx, clean up a bit.
  66  *      0.20: 07 Dec 2003: alloc fixes
  67  *      0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
  68  *      0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
  69  *                         on close.
  70  *      0.23: 26 Jan 2004: various small cleanups
  71  *      0.24: 27 Feb 2004: make driver even less anonymous in backtraces
  72  *      0.25: 09 Mar 2004: wol support
  73  *      0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
  74  *      0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
  75  *                         added CK804/MCP04 device IDs, code fixes
  76  *                         for registers, link status and other minor fixes.
  77  *      0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
  78  *      0.29: 31 Aug 2004: Add backup timer for link change notification.
  79  *      0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
  80  *                         into nv_close, otherwise reenabling for wol can
  81  *                         cause DMA to kfree'd memory.
  82  *      0.31: 14 Nov 2004: ethtool support for getting/setting link
  83  *                         capabilities.
  84  *      0.32: 16 Apr 2005: RX_ERROR4 handling added.
  85  *      0.33: 16 May 2005: Support for MCP51 added.
  86  *      0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
  87  *      0.35: 26 Jun 2005: Support for MCP55 added.
  88  *      0.36: 28 Jun 2005: Add jumbo frame support.
  89  *      0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
  90  *      0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
  91  *                         per-packet flags.
  92  *      0.39: 18 Jul 2005: Add 64bit descriptor support.
  93  *      0.40: 19 Jul 2005: Add support for mac address change.
  94  *      0.41: 30 Jul 2005: Write back original MAC in nv_close instead
  95  *                         of nv_remove
  96  *      0.42: 06 Aug 2005: Fix lack of link speed initialization
  97  *                         in the second (and later) nv_open call
  98  *      0.43: 10 Aug 2005: Add support for tx checksum.
  99  *      0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
 100  *      0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
 101  *      0.46: 20 Oct 2005: Add irq optimization modes.
 102  *      0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
 103  *      0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
 104  *      0.49: 10 Dec 2005: Fix tso for large buffers.
 105  *      0.50: 20 Jan 2006: Add 8021pq tagging support.
 106  *      0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
 107  *      0.52: 20 Jan 2006: Add MSI/MSIX support.
 108  *      0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
 109  *      0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
 110  *      0.55: 22 Mar 2006: Add flow control (pause frame).
 111  *      0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
 112  *      0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
 113  *
 114  * Known bugs:
 115  * We suspect that on some hardware no TX done interrupts are generated.
 116  * This means recovery from netif_stop_queue only happens if the hw timer
 117  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
 118  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
 119  * If your hardware reliably generates tx done interrupts, then you can remove
 120  * DEV_NEED_TIMERIRQ from the driver_data flags.
 121  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
 122  * superfluous timer interrupts from the nic.
 123  */
 124 #ifdef CONFIG_FORCEDETH_NAPI
 125 #define DRIVERNAPI "-NAPI"
 126 #else
 127 #define DRIVERNAPI
 128 #endif
 129 #define FORCEDETH_VERSION               "0.57"
 130 #define DRV_NAME                        "forcedeth"
 131
 132 #include <linux/module.h>
 133 #include <linux/types.h>
 134 #include <linux/pci.h>
 135 #include <linux/interrupt.h>
 136 #include <linux/netdevice.h>
 137 #include <linux/etherdevice.h>
 138 #include <linux/delay.h>
 139 #include <linux/spinlock.h>
 140 #include <linux/ethtool.h>
 141 #include <linux/timer.h>
 142 #include <linux/skbuff.h>
 143 #include <linux/mii.h>
 144 #include <linux/random.h>
 145 #include <linux/init.h>
 146 #include <linux/if_vlan.h>
 147 #include <linux/dma-mapping.h>
 148
 149 #include <asm/irq.h>
 150 #include <asm/io.h>
 151 #include <asm/uaccess.h>
 152 #include <asm/system.h>
 153
 154 #if 0
 155 #define dprintk                 printk
 156 #else
 157 #define dprintk(x...)           do { } while (0)
 158 #endif
 159
 160
 161 /*
 162  * Hardware access:
 163  */
 164
 165 #define DEV_NEED_TIMERIRQ       0x0001  /* set the timer irq flag in the irq mask */
 166 #define DEV_NEED_LINKTIMER      0x0002  /* poll link settings. Relies on the timer irq */
 167 #define DEV_HAS_LARGEDESC       0x0004  /* device supports jumbo frames and needs packet format 2 */
 168 #define DEV_HAS_HIGH_DMA        0x0008  /* device supports 64bit dma */
 169 #define DEV_HAS_CHECKSUM        0x0010  /* device supports tx and rx checksum offloads */
 170 #define DEV_HAS_VLAN            0x0020  /* device supports vlan tagging and striping */
 171 #define DEV_HAS_MSI             0x0040  /* device supports MSI */
 172 #define DEV_HAS_MSI_X           0x0080  /* device supports MSI-X */
 173 #define DEV_HAS_POWER_CNTRL     0x0100  /* device supports power savings */
 174 #define DEV_HAS_PAUSEFRAME_TX   0x0200  /* device supports tx pause frames */
 175 #define DEV_HAS_STATISTICS      0x0400  /* device supports hw statistics */
 176 #define DEV_HAS_TEST_EXTENDED   0x0800  /* device supports extended diagnostic test */
 177
 178 enum {
 179         NvRegIrqStatus = 0x000,
 180 #define NVREG_IRQSTAT_MIIEVENT  0x040
 181 #define NVREG_IRQSTAT_MASK              0x1ff
 182         NvRegIrqMask = 0x004,
 183 #define NVREG_IRQ_RX_ERROR              0x0001
 184 #define NVREG_IRQ_RX                    0x0002
 185 #define NVREG_IRQ_RX_NOBUF              0x0004
 186 #define NVREG_IRQ_TX_ERR                0x0008
 187 #define NVREG_IRQ_TX_OK                 0x0010
 188 #define NVREG_IRQ_TIMER                 0x0020
 189 #define NVREG_IRQ_LINK                  0x0040
 190 #define NVREG_IRQ_RX_FORCED             0x0080
 191 #define NVREG_IRQ_TX_FORCED             0x0100
 192 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 193 #define NVREG_IRQMASK_CPU               0x0040
 194 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 195 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 196 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK)
 197
 198 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
 199                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
 200                                         NVREG_IRQ_TX_FORCED))
 201
 202         NvRegUnknownSetupReg6 = 0x008,
 203 #define NVREG_UNKSETUP6_VAL             3
 204
 205 /*
 206  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 207  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 208  */
 209         NvRegPollingInterval = 0x00c,
 210 #define NVREG_POLL_DEFAULT_THROUGHPUT   970
 211 #define NVREG_POLL_DEFAULT_CPU  13
 212         NvRegMSIMap0 = 0x020,
 213         NvRegMSIMap1 = 0x024,
 214         NvRegMSIIrqMask = 0x030,
 215 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 216         NvRegMisc1 = 0x080,
 217 #define NVREG_MISC1_PAUSE_TX    0x01
 218 #define NVREG_MISC1_HD          0x02
 219 #define NVREG_MISC1_FORCE       0x3b0f3c
 220
 221         NvRegMacReset = 0x3c,
 222 #define NVREG_MAC_RESET_ASSERT  0x0F3
 223         NvRegTransmitterControl = 0x084,
 224 #define NVREG_XMITCTL_START     0x01
 225         NvRegTransmitterStatus = 0x088,
 226 #define NVREG_XMITSTAT_BUSY     0x01
 227
 228         NvRegPacketFilterFlags = 0x8c,
 229 #define NVREG_PFF_PAUSE_RX      0x08
 230 #define NVREG_PFF_ALWAYS        0x7F0000
 231 #define NVREG_PFF_PROMISC       0x80
 232 #define NVREG_PFF_MYADDR        0x20
 233 #define NVREG_PFF_LOOPBACK      0x10
 234
 235         NvRegOffloadConfig = 0x90,
 236 #define NVREG_OFFLOAD_HOMEPHY   0x601
 237 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 238         NvRegReceiverControl = 0x094,
 239 #define NVREG_RCVCTL_START      0x01
 240         NvRegReceiverStatus = 0x98,
 241 #define NVREG_RCVSTAT_BUSY      0x01
 242
 243         NvRegRandomSeed = 0x9c,
 244 #define NVREG_RNDSEED_MASK      0x00ff
 245 #define NVREG_RNDSEED_FORCE     0x7f00
 246 #define NVREG_RNDSEED_FORCE2    0x2d00
 247 #define NVREG_RNDSEED_FORCE3    0x7400
 248
 249         NvRegTxDeferral = 0xA0,
 250 #define NVREG_TX_DEFERRAL_DEFAULT       0x15050f
 251 #define NVREG_TX_DEFERRAL_RGMII_10_100  0x16070f
 252 #define NVREG_TX_DEFERRAL_RGMII_1000    0x14050f
 253         NvRegRxDeferral = 0xA4,
 254 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
 255         NvRegMacAddrA = 0xA8,
 256         NvRegMacAddrB = 0xAC,
 257         NvRegMulticastAddrA = 0xB0,
 258 #define NVREG_MCASTADDRA_FORCE  0x01
 259         NvRegMulticastAddrB = 0xB4,
 260         NvRegMulticastMaskA = 0xB8,
 261         NvRegMulticastMaskB = 0xBC,
 262
 263         NvRegPhyInterface = 0xC0,
 264 #define PHY_RGMII               0x10000000
 265
 266         NvRegTxRingPhysAddr = 0x100,
 267         NvRegRxRingPhysAddr = 0x104,
 268         NvRegRingSizes = 0x108,
 269 #define NVREG_RINGSZ_TXSHIFT 0
 270 #define NVREG_RINGSZ_RXSHIFT 16
 271         NvRegTransmitPoll = 0x10c,
 272 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
 273         NvRegLinkSpeed = 0x110,
 274 #define NVREG_LINKSPEED_FORCE 0x10000
 275 #define NVREG_LINKSPEED_10      1000
 276 #define NVREG_LINKSPEED_100     100
 277 #define NVREG_LINKSPEED_1000    50
 278 #define NVREG_LINKSPEED_MASK    (0xFFF)
 279         NvRegUnknownSetupReg5 = 0x130,
 280 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 281         NvRegTxWatermark = 0x13c,
 282 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
 283 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
 284 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
 285         NvRegTxRxControl = 0x144,
 286 #define NVREG_TXRXCTL_KICK      0x0001
 287 #define NVREG_TXRXCTL_BIT1      0x0002
 288 #define NVREG_TXRXCTL_BIT2      0x0004
 289 #define NVREG_TXRXCTL_IDLE      0x0008
 290 #define NVREG_TXRXCTL_RESET     0x0010
 291 #define NVREG_TXRXCTL_RXCHECK   0x0400
 292 #define NVREG_TXRXCTL_DESC_1    0
 293 #define NVREG_TXRXCTL_DESC_2    0x02100
 294 #define NVREG_TXRXCTL_DESC_3    0x02200
 295 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 296 #define NVREG_TXRXCTL_VLANINS   0x00080
 297         NvRegTxRingPhysAddrHigh = 0x148,
 298         NvRegRxRingPhysAddrHigh = 0x14C,
 299         NvRegTxPauseFrame = 0x170,
 300 #define NVREG_TX_PAUSEFRAME_DISABLE     0x1ff0080
 301 #define NVREG_TX_PAUSEFRAME_ENABLE      0x0c00030
 302         NvRegMIIStatus = 0x180,
 303 #define NVREG_MIISTAT_ERROR             0x0001
 304 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 305 #define NVREG_MIISTAT_MASK              0x000f
 306 #define NVREG_MIISTAT_MASK2             0x000f
 307         NvRegUnknownSetupReg4 = 0x184,
 308 #define NVREG_UNKSETUP4_VAL     8
 309
 310         NvRegAdapterControl = 0x188,
 311 #define NVREG_ADAPTCTL_START    0x02
 312 #define NVREG_ADAPTCTL_LINKUP   0x04
 313 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 314 #define NVREG_ADAPTCTL_RUNNING  0x100000
 315 #define NVREG_ADAPTCTL_PHYSHIFT 24
 316         NvRegMIISpeed = 0x18c,
 317 #define NVREG_MIISPEED_BIT8     (1<<8)
 318 #define NVREG_MIIDELAY  5
 319         NvRegMIIControl = 0x190,
 320 #define NVREG_MIICTL_INUSE      0x08000
 321 #define NVREG_MIICTL_WRITE      0x00400
 322 #define NVREG_MIICTL_ADDRSHIFT  5
 323         NvRegMIIData = 0x194,
 324         NvRegWakeUpFlags = 0x200,
 325 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 326 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 327 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 328 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 329 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 330 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 331 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 332 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 333 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 334 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 335 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 336
 337         NvRegPatternCRC = 0x204,
 338         NvRegPatternMask = 0x208,
 339         NvRegPowerCap = 0x268,
 340 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 341 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 342 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 343         NvRegPowerState = 0x26c,
 344 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 345 #define NVREG_POWERSTATE_VALID          0x0100
 346 #define NVREG_POWERSTATE_MASK           0x0003
 347 #define NVREG_POWERSTATE_D0             0x0000
 348 #define NVREG_POWERSTATE_D1             0x0001
 349 #define NVREG_POWERSTATE_D2             0x0002
 350 #define NVREG_POWERSTATE_D3             0x0003
 351         NvRegTxCnt = 0x280,
 352         NvRegTxZeroReXmt = 0x284,
 353         NvRegTxOneReXmt = 0x288,
 354         NvRegTxManyReXmt = 0x28c,
 355         NvRegTxLateCol = 0x290,
 356         NvRegTxUnderflow = 0x294,
 357         NvRegTxLossCarrier = 0x298,
 358         NvRegTxExcessDef = 0x29c,
 359         NvRegTxRetryErr = 0x2a0,
 360         NvRegRxFrameErr = 0x2a4,
 361         NvRegRxExtraByte = 0x2a8,
 362         NvRegRxLateCol = 0x2ac,
 363         NvRegRxRunt = 0x2b0,
 364         NvRegRxFrameTooLong = 0x2b4,
 365         NvRegRxOverflow = 0x2b8,
 366         NvRegRxFCSErr = 0x2bc,
 367         NvRegRxFrameAlignErr = 0x2c0,
 368         NvRegRxLenErr = 0x2c4,
 369         NvRegRxUnicast = 0x2c8,
 370         NvRegRxMulticast = 0x2cc,
 371         NvRegRxBroadcast = 0x2d0,
 372         NvRegTxDef = 0x2d4,
 373         NvRegTxFrame = 0x2d8,
 374         NvRegRxCnt = 0x2dc,
 375         NvRegTxPause = 0x2e0,
 376         NvRegRxPause = 0x2e4,
 377         NvRegRxDropFrame = 0x2e8,
 378         NvRegVlanControl = 0x300,
 379 #define NVREG_VLANCONTROL_ENABLE        0x2000
 380         NvRegMSIXMap0 = 0x3e0,
 381         NvRegMSIXMap1 = 0x3e4,
 382         NvRegMSIXIrqStatus = 0x3f0,
 383
 384         NvRegPowerState2 = 0x600,
 385 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F11
 386 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 387 };
 388
 389 /* Big endian: should work, but is untested */
 390 struct ring_desc {
 391         __le32 buf;
 392         __le32 flaglen;
 393 };
 394
 395 struct ring_desc_ex {
 396         __le32 bufhigh;
 397         __le32 buflow;
 398         __le32 txvlan;
 399         __le32 flaglen;
 400 };
 401
 402 union ring_type {
 403         struct ring_desc* orig;
 404         struct ring_desc_ex* ex;
 405 };
 406
 407 #define FLAG_MASK_V1 0xffff0000
 408 #define FLAG_MASK_V2 0xffffc000
 409 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 410 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 411
 412 #define NV_TX_LASTPACKET        (1<<16)
 413 #define NV_TX_RETRYERROR        (1<<19)
 414 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 415 #define NV_TX_DEFERRED          (1<<26)
 416 #define NV_TX_CARRIERLOST       (1<<27)
 417 #define NV_TX_LATECOLLISION     (1<<28)
 418 #define NV_TX_UNDERFLOW         (1<<29)
 419 #define NV_TX_ERROR             (1<<30)
 420 #define NV_TX_VALID             (1<<31)
 421
 422 #define NV_TX2_LASTPACKET       (1<<29)
 423 #define NV_TX2_RETRYERROR       (1<<18)
 424 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 425 #define NV_TX2_DEFERRED         (1<<25)
 426 #define NV_TX2_CARRIERLOST      (1<<26)
 427 #define NV_TX2_LATECOLLISION    (1<<27)
 428 #define NV_TX2_UNDERFLOW        (1<<28)
 429 /* error and valid are the same for both */
 430 #define NV_TX2_ERROR            (1<<30)
 431 #define NV_TX2_VALID            (1<<31)
 432 #define NV_TX2_TSO              (1<<28)
 433 #define NV_TX2_TSO_SHIFT        14
 434 #define NV_TX2_TSO_MAX_SHIFT    14
 435 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 436 #define NV_TX2_CHECKSUM_L3      (1<<27)
 437 #define NV_TX2_CHECKSUM_L4      (1<<26)
 438
 439 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 440
 441 #define NV_RX_DESCRIPTORVALID   (1<<16)
 442 #define NV_RX_MISSEDFRAME       (1<<17)
 443 #define NV_RX_SUBSTRACT1        (1<<18)
 444 #define NV_RX_ERROR1            (1<<23)
 445 #define NV_RX_ERROR2            (1<<24)
 446 #define NV_RX_ERROR3            (1<<25)
 447 #define NV_RX_ERROR4            (1<<26)
 448 #define NV_RX_CRCERR            (1<<27)
 449 #define NV_RX_OVERFLOW          (1<<28)
 450 #define NV_RX_FRAMINGERR        (1<<29)
 451 #define NV_RX_ERROR             (1<<30)
 452 #define NV_RX_AVAIL             (1<<31)
 453
 454 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 455 #define NV_RX2_CHECKSUMOK1      (0x10000000)
 456 #define NV_RX2_CHECKSUMOK2      (0x14000000)
 457 #define NV_RX2_CHECKSUMOK3      (0x18000000)
 458 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 459 #define NV_RX2_SUBSTRACT1       (1<<25)
 460 #define NV_RX2_ERROR1           (1<<18)
 461 #define NV_RX2_ERROR2           (1<<19)
 462 #define NV_RX2_ERROR3           (1<<20)
 463 #define NV_RX2_ERROR4           (1<<21)
 464 #define NV_RX2_CRCERR           (1<<22)
 465 #define NV_RX2_OVERFLOW         (1<<23)
 466 #define NV_RX2_FRAMINGERR       (1<<24)
 467 /* error and avail are the same for both */
 468 #define NV_RX2_ERROR            (1<<30)
 469 #define NV_RX2_AVAIL            (1<<31)
 470
 471 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 472 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 473
 474 /* Miscelaneous hardware related defines: */
 475 #define NV_PCI_REGSZ_VER1       0x270
 476 #define NV_PCI_REGSZ_VER2       0x604
 477
 478 /* various timeout delays: all in usec */
 479 #define NV_TXRX_RESET_DELAY     4
 480 #define NV_TXSTOP_DELAY1        10
 481 #define NV_TXSTOP_DELAY1MAX     500000
 482 #define NV_TXSTOP_DELAY2        100
 483 #define NV_RXSTOP_DELAY1        10
 484 #define NV_RXSTOP_DELAY1MAX     500000
 485 #define NV_RXSTOP_DELAY2        100
 486 #define NV_SETUP5_DELAY         5
 487 #define NV_SETUP5_DELAYMAX      50000
 488 #define NV_POWERUP_DELAY        5
 489 #define NV_POWERUP_DELAYMAX     5000
 490 #define NV_MIIBUSY_DELAY        50
 491 #define NV_MIIPHY_DELAY 10
 492 #define NV_MIIPHY_DELAYMAX      10000
 493 #define NV_MAC_RESET_DELAY      64
 494
 495 #define NV_WAKEUPPATTERNS       5
 496 #define NV_WAKEUPMASKENTRIES    4
 497
 498 /* General driver defaults */
 499 #define NV_WATCHDOG_TIMEO       (5*HZ)
 500
 501 #define RX_RING_DEFAULT         128
 502 #define TX_RING_DEFAULT         256
 503 #define RX_RING_MIN             128
 504 #define TX_RING_MIN             64
 505 #define RING_MAX_DESC_VER_1     1024
 506 #define RING_MAX_DESC_VER_2_3   16384
 507 /*
 508  * Difference between the get and put pointers for the tx ring.
 509  * This is used to throttle the amount of data outstanding in the
 510  * tx ring.
 511  */
 512 #define TX_LIMIT_DIFFERENCE     1
 513
 514 /* rx/tx mac addr + type + vlan + align + slack*/
 515 #define NV_RX_HEADERS           (64)
 516 /* even more slack. */
 517 #define NV_RX_ALLOC_PAD         (64)
 518
 519 /* maximum mtu size */
 520 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 521 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 522
 523 #define OOM_REFILL      (1+HZ/20)
 524 #define POLL_WAIT       (1+HZ/100)
 525 #define LINK_TIMEOUT    (3*HZ)
 526 #define STATS_INTERVAL  (10*HZ)
 527
 528 /*
 529  * desc_ver values:
 530  * The nic supports three different descriptor types:
 531  * - DESC_VER_1: Original
 532  * - DESC_VER_2: support for jumbo frames.
 533  * - DESC_VER_3: 64-bit format.
 534  */
 535 #define DESC_VER_1      1
 536 #define DESC_VER_2      2
 537 #define DESC_VER_3      3
 538
 539 /* PHY defines */
 540 #define PHY_OUI_MARVELL 0x5043
 541 #define PHY_OUI_CICADA  0x03f1
 542 #define PHYID1_OUI_MASK 0x03ff
 543 #define PHYID1_OUI_SHFT 6
 544 #define PHYID2_OUI_MASK 0xfc00
 545 #define PHYID2_OUI_SHFT 10
 546 #define PHYID2_MODEL_MASK               0x03f0
 547 #define PHY_MODEL_MARVELL_E3016         0x220
 548 #define PHY_MARVELL_E3016_INITMASK      0x0300
 549 #define PHY_INIT1       0x0f000
 550 #define PHY_INIT2       0x0e00
 551 #define PHY_INIT3       0x01000
 552 #define PHY_INIT4       0x0200
 553 #define PHY_INIT5       0x0004
 554 #define PHY_INIT6       0x02000
 555 #define PHY_GIGABIT     0x0100
 556
 557 #define PHY_TIMEOUT     0x1
 558 #define PHY_ERROR       0x2
 559
 560 #define PHY_100 0x1
 561 #define PHY_1000        0x2
 562 #define PHY_HALF        0x100
 563
 564 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 565 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 566 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 567 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 568 #define NV_PAUSEFRAME_RX_REQ     0x0010
 569 #define NV_PAUSEFRAME_TX_REQ     0x0020
 570 #define NV_PAUSEFRAME_AUTONEG    0x0040
 571
 572 /* MSI/MSI-X defines */
 573 #define NV_MSI_X_MAX_VECTORS  8
 574 #define NV_MSI_X_VECTORS_MASK 0x000f
 575 #define NV_MSI_CAPABLE        0x0010
 576 #define NV_MSI_X_CAPABLE      0x0020
 577 #define NV_MSI_ENABLED        0x0040
 578 #define NV_MSI_X_ENABLED      0x0080
 579
 580 #define NV_MSI_X_VECTOR_ALL   0x0
 581 #define NV_MSI_X_VECTOR_RX    0x0
 582 #define NV_MSI_X_VECTOR_TX    0x1
 583 #define NV_MSI_X_VECTOR_OTHER 0x2
 584
 585 /* statistics */
 586 struct nv_ethtool_str {
 587         char name[ETH_GSTRING_LEN];
 588 };
 589
 590 static const struct nv_ethtool_str nv_estats_str[] = {
 591         { "tx_bytes" },
 592         { "tx_zero_rexmt" },
 593         { "tx_one_rexmt" },
 594         { "tx_many_rexmt" },
 595         { "tx_late_collision" },
 596         { "tx_fifo_errors" },
 597         { "tx_carrier_errors" },
 598         { "tx_excess_deferral" },
 599         { "tx_retry_error" },
 600         { "tx_deferral" },
 601         { "tx_packets" },
 602         { "tx_pause" },
 603         { "rx_frame_error" },
 604         { "rx_extra_byte" },
 605         { "rx_late_collision" },
 606         { "rx_runt" },
 607         { "rx_frame_too_long" },
 608         { "rx_over_errors" },
 609         { "rx_crc_errors" },
 610         { "rx_frame_align_error" },
 611         { "rx_length_error" },
 612         { "rx_unicast" },
 613         { "rx_multicast" },
 614         { "rx_broadcast" },
 615         { "rx_bytes" },
 616         { "rx_pause" },
 617         { "rx_drop_frame" },
 618         { "rx_packets" },
 619         { "rx_errors_total" }
 620 };
 621
 622 struct nv_ethtool_stats {
 623         u64 tx_bytes;
 624         u64 tx_zero_rexmt;
 625         u64 tx_one_rexmt;
 626         u64 tx_many_rexmt;
 627         u64 tx_late_collision;
 628         u64 tx_fifo_errors;
 629         u64 tx_carrier_errors;
 630         u64 tx_excess_deferral;
 631         u64 tx_retry_error;
 632         u64 tx_deferral;
 633         u64 tx_packets;
 634         u64 tx_pause;
 635         u64 rx_frame_error;
 636         u64 rx_extra_byte;
 637         u64 rx_late_collision;
 638         u64 rx_runt;
 639         u64 rx_frame_too_long;
 640         u64 rx_over_errors;
 641         u64 rx_crc_errors;
 642         u64 rx_frame_align_error;
 643         u64 rx_length_error;
 644         u64 rx_unicast;
 645         u64 rx_multicast;
 646         u64 rx_broadcast;
 647         u64 rx_bytes;
 648         u64 rx_pause;
 649         u64 rx_drop_frame;
 650         u64 rx_packets;
 651         u64 rx_errors_total;
 652 };
 653
 654 /* diagnostics */
 655 #define NV_TEST_COUNT_BASE 3
 656 #define NV_TEST_COUNT_EXTENDED 4
 657
 658 static const struct nv_ethtool_str nv_etests_str[] = {
 659         { "link      (online/offline)" },
 660         { "register  (offline)       " },
 661         { "interrupt (offline)       " },
 662         { "loopback  (offline)       " }
 663 };
 664
 665 struct register_test {
 666         __le32 reg;
 667         __le32 mask;
 668 };
 669
 670 static const struct register_test nv_registers_test[] = {
 671         { NvRegUnknownSetupReg6, 0x01 },
 672         { NvRegMisc1, 0x03c },
 673         { NvRegOffloadConfig, 0x03ff },
 674         { NvRegMulticastAddrA, 0xffffffff },
 675         { NvRegTxWatermark, 0x0ff },
 676         { NvRegWakeUpFlags, 0x07777 },
 677         { 0,0 }
 678 };
 679
 680 /*
 681  * SMP locking:
 682  * All hardware access under dev->priv->lock, except the performance
 683  * critical parts:
 684  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 685  *      by the arch code for interrupts.
 686  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 687  *      needs dev->priv->lock :-(
 688  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 689  */
 690
 691 /* in dev: base, irq */
 692 struct fe_priv {
 693         spinlock_t lock;
 694
 695         /* General data:
 696          * Locking: spin_lock(&np->lock); */
 697         struct net_device_stats stats;
 698         struct nv_ethtool_stats estats;
 699         int in_shutdown;
 700         u32 linkspeed;
 701         int duplex;
 702         int autoneg;
 703         int fixed_mode;
 704         int phyaddr;
 705         int wolenabled;
 706         unsigned int phy_oui;
 707         unsigned int phy_model;
 708         u16 gigabit;
 709         int intr_test;
 710
 711         /* General data: RO fields */
 712         dma_addr_t ring_addr;
 713         struct pci_dev *pci_dev;
 714         u32 orig_mac[2];
 715         u32 irqmask;
 716         u32 desc_ver;
 717         u32 txrxctl_bits;
 718         u32 vlanctl_bits;
 719         u32 driver_data;
 720         u32 register_size;
 721
 722         void __iomem *base;
 723
 724         /* rx specific fields.
 725          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 726          */
 727         union ring_type rx_ring;
 728         unsigned int cur_rx, refill_rx;
 729         struct sk_buff **rx_skbuff;
 730         dma_addr_t *rx_dma;
 731         unsigned int rx_buf_sz;
 732         unsigned int pkt_limit;
 733         struct timer_list oom_kick;
 734         struct timer_list nic_poll;
 735         struct timer_list stats_poll;
 736         u32 nic_poll_irq;
 737         int rx_ring_size;
 738
 739         /* media detection workaround.
 740          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 741          */
 742         int need_linktimer;
 743         unsigned long link_timeout;
 744         /*
 745          * tx specific fields.
 746          */
 747         union ring_type tx_ring;
 748         unsigned int next_tx, nic_tx;
 749         struct sk_buff **tx_skbuff;
 750         dma_addr_t *tx_dma;
 751         unsigned int *tx_dma_len;
 752         u32 tx_flags;
 753         int tx_ring_size;
 754         int tx_limit_start;
 755         int tx_limit_stop;
 756
 757         /* vlan fields */
 758         struct vlan_group *vlangrp;
 759
 760         /* msi/msi-x fields */
 761         u32 msi_flags;
 762         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 763
 764         /* flow control */
 765         u32 pause_flags;
 766 };
 767
 768 /*
 769  * Maximum number of loops until we assume that a bit in the irq mask
 770  * is stuck. Overridable with module param.
 771  */
 772 static int max_interrupt_work = 5;
 773
 774 /*
 775  * Optimization can be either throuput mode or cpu mode
 776  *
 777  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 778  * CPU Mode: Interrupts are controlled by a timer.
 779  */
 780 enum {
 781         NV_OPTIMIZATION_MODE_THROUGHPUT,
 782         NV_OPTIMIZATION_MODE_CPU
 783 };
 784 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
 785
 786 /*
 787  * Poll interval for timer irq
 788  *
 789  * This interval determines how frequent an interrupt is generated.
 790  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 791  * Min = 0, and Max = 65535
 792  */
 793 static int poll_interval = -1;
 794
 795 /*
 796  * MSI interrupts
 797  */
 798 enum {
 799         NV_MSI_INT_DISABLED,
 800         NV_MSI_INT_ENABLED
 801 };
 802 static int msi = NV_MSI_INT_ENABLED;
 803
 804 /*
 805  * MSIX interrupts
 806  */
 807 enum {
 808         NV_MSIX_INT_DISABLED,
 809         NV_MSIX_INT_ENABLED
 810 };
 811 static int msix = NV_MSIX_INT_ENABLED;
 812
 813 /*
 814  * DMA 64bit
 815  */
 816 enum {
 817         NV_DMA_64BIT_DISABLED,
 818         NV_DMA_64BIT_ENABLED
 819 };
 820 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 821
 822 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 823 {
 824         return netdev_priv(dev);
 825 }
 826
 827 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 828 {
 829         return ((struct fe_priv *)netdev_priv(dev))->base;
 830 }
 831
 832 static inline void pci_push(u8 __iomem *base)
 833 {
 834         /* force out pending posted writes */
 835         readl(base);
 836 }
 837
 838 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 839 {
 840         return le32_to_cpu(prd->flaglen)
 841                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 842 }
 843
 844 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 845 {
 846         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
 847 }
 848
 849 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 850                                 int delay, int delaymax, const char *msg)
 851 {
 852         u8 __iomem *base = get_hwbase(dev);
 853
 854         pci_push(base);
 855         do {
 856                 udelay(delay);
 857                 delaymax -= delay;
 858                 if (delaymax < 0) {
 859                         if (msg)
 860                                 printk(msg);
 861                         return 1;
 862                 }
 863         } while ((readl(base + offset) & mask) != target);
 864         return 0;
 865 }
 866
 867 #define NV_SETUP_RX_RING 0x01
 868 #define NV_SETUP_TX_RING 0x02
 869
 870 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
 871 {
 872         struct fe_priv *np = get_nvpriv(dev);
 873         u8 __iomem *base = get_hwbase(dev);
 874
 875         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 876                 if (rxtx_flags & NV_SETUP_RX_RING) {
 877                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 878                 }
 879                 if (rxtx_flags & NV_SETUP_TX_RING) {
 880                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
 881                 }
 882         } else {
 883                 if (rxtx_flags & NV_SETUP_RX_RING) {
 884                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 885                         writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
 886                 }
 887                 if (rxtx_flags & NV_SETUP_TX_RING) {
 888                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
 889                         writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
 890                 }
 891         }
 892 }
 893
 894 static void free_rings(struct net_device *dev)
 895 {
 896         struct fe_priv *np = get_nvpriv(dev);
 897
 898         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 899                 if (np->rx_ring.orig)
 900                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
 901                                             np->rx_ring.orig, np->ring_addr);
 902         } else {
 903                 if (np->rx_ring.ex)
 904                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
 905                                             np->rx_ring.ex, np->ring_addr);
 906         }
 907         if (np->rx_skbuff)
 908                 kfree(np->rx_skbuff);
 909         if (np->rx_dma)
 910                 kfree(np->rx_dma);
 911         if (np->tx_skbuff)
 912                 kfree(np->tx_skbuff);
 913         if (np->tx_dma)
 914                 kfree(np->tx_dma);
 915         if (np->tx_dma_len)
 916                 kfree(np->tx_dma_len);
 917 }
 918
 919 static int using_multi_irqs(struct net_device *dev)
 920 {
 921         struct fe_priv *np = get_nvpriv(dev);
 922
 923         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
 924             ((np->msi_flags & NV_MSI_X_ENABLED) &&
 925              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
 926                 return 0;
 927         else
 928                 return 1;
 929 }
 930
 931 static void nv_enable_irq(struct net_device *dev)
 932 {
 933         struct fe_priv *np = get_nvpriv(dev);
 934
 935         if (!using_multi_irqs(dev)) {
 936                 if (np->msi_flags & NV_MSI_X_ENABLED)
 937                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 938                 else
 939                         enable_irq(dev->irq);
 940         } else {
 941                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 942                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 943                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
 944         }
 945 }
 946
 947 static void nv_disable_irq(struct net_device *dev)
 948 {
 949         struct fe_priv *np = get_nvpriv(dev);
 950
 951         if (!using_multi_irqs(dev)) {
 952                 if (np->msi_flags & NV_MSI_X_ENABLED)
 953                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 954                 else
 955                         disable_irq(dev->irq);
 956         } else {
 957                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 958                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 959                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
 960         }
 961 }
 962
 963 /* In MSIX mode, a write to irqmask behaves as XOR */
 964 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
 965 {
 966         u8 __iomem *base = get_hwbase(dev);
 967
 968         writel(mask, base + NvRegIrqMask);
 969 }
 970
 971 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
 972 {
 973         struct fe_priv *np = get_nvpriv(dev);
 974         u8 __iomem *base = get_hwbase(dev);
 975
 976         if (np->msi_flags & NV_MSI_X_ENABLED) {
 977                 writel(mask, base + NvRegIrqMask);
 978         } else {
 979                 if (np->msi_flags & NV_MSI_ENABLED)
 980                         writel(0, base + NvRegMSIIrqMask);
 981                 writel(0, base + NvRegIrqMask);
 982         }
 983 }
 984
 985 #define MII_READ        (-1)
 986 /* mii_rw: read/write a register on the PHY.
 987  *
 988  * Caller must guarantee serialization
 989  */
 990 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
 991 {
 992         u8 __iomem *base = get_hwbase(dev);
 993         u32 reg;
 994         int retval;
 995
 996         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
 997
 998         reg = readl(base + NvRegMIIControl);
 999         if (reg & NVREG_MIICTL_INUSE) {
1000                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1001                 udelay(NV_MIIBUSY_DELAY);
1002         }
1003
1004         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1005         if (value != MII_READ) {
1006                 writel(value, base + NvRegMIIData);
1007                 reg |= NVREG_MIICTL_WRITE;
1008         }
1009         writel(reg, base + NvRegMIIControl);
1010
1011         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1012                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1013                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1014                                 dev->name, miireg, addr);
1015                 retval = -1;
1016         } else if (value != MII_READ) {
1017                 /* it was a write operation - fewer failures are detectable */
1018                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1019                                 dev->name, value, miireg, addr);
1020                 retval = 0;
1021         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1022                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1023                                 dev->name, miireg, addr);
1024                 retval = -1;
1025         } else {
1026                 retval = readl(base + NvRegMIIData);
1027                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1028                                 dev->name, miireg, addr, retval);
1029         }
1030
1031         return retval;
1032 }
1033
1034 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1035 {
1036         struct fe_priv *np = netdev_priv(dev);
1037         u32 miicontrol;
1038         unsigned int tries = 0;
1039
1040         miicontrol = BMCR_RESET | bmcr_setup;
1041         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1042                 return -1;
1043         }
1044
1045         /* wait for 500ms */
1046         msleep(500);
1047
1048         /* must wait till reset is deasserted */
1049         while (miicontrol & BMCR_RESET) {
1050                 msleep(10);
1051                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1052                 /* FIXME: 100 tries seem excessive */
1053                 if (tries++ > 100)
1054                         return -1;
1055         }
1056         return 0;
1057 }
1058
1059 static int phy_init(struct net_device *dev)
1060 {
1061         struct fe_priv *np = get_nvpriv(dev);
1062         u8 __iomem *base = get_hwbase(dev);
1063         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1064
1065         /* phy errata for E3016 phy */
1066         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1067                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1068                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1069                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1070                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1071                         return PHY_ERROR;
1072                 }
1073         }
1074
1075         /* set advertise register */
1076         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1077         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1078         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1079                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1080                 return PHY_ERROR;
1081         }
1082
1083         /* get phy interface type */
1084         phyinterface = readl(base + NvRegPhyInterface);
1085
1086         /* see if gigabit phy */
1087         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1088         if (mii_status & PHY_GIGABIT) {
1089                 np->gigabit = PHY_GIGABIT;
1090                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1091                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1092                 if (phyinterface & PHY_RGMII)
1093                         mii_control_1000 |= ADVERTISE_1000FULL;
1094                 else
1095                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1096
1097                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1098                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1099                         return PHY_ERROR;
1100                 }
1101         }
1102         else
1103                 np->gigabit = 0;
1104
1105         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1106         mii_control |= BMCR_ANENABLE;
1107
1108         /* reset the phy
1109          * (certain phys need bmcr to be setup with reset)
1110          */
1111         if (phy_reset(dev, mii_control)) {
1112                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1113                 return PHY_ERROR;
1114         }
1115
1116         /* phy vendor specific configuration */
1117         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1118                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1119                 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
1120                 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
1121                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1122                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1123                         return PHY_ERROR;
1124                 }
1125                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1126                 phy_reserved |= PHY_INIT5;
1127                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1128                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1129                         return PHY_ERROR;
1130                 }
1131         }
1132         if (np->phy_oui == PHY_OUI_CICADA) {
1133                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1134                 phy_reserved |= PHY_INIT6;
1135                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1136                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1137                         return PHY_ERROR;
1138                 }
1139         }
1140         /* some phys clear out pause advertisment on reset, set it back */
1141         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1142
1143         /* restart auto negotiation */
1144         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1145         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1146         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1147                 return PHY_ERROR;
1148         }
1149
1150         return 0;
1151 }
1152
1153 static void nv_start_rx(struct net_device *dev)
1154 {
1155         struct fe_priv *np = netdev_priv(dev);
1156         u8 __iomem *base = get_hwbase(dev);
1157
1158         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1159         /* Already running? Stop it. */
1160         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
1161                 writel(0, base + NvRegReceiverControl);
1162                 pci_push(base);
1163         }
1164         writel(np->linkspeed, base + NvRegLinkSpeed);
1165         pci_push(base);
1166         writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
1167         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1168                                 dev->name, np->duplex, np->linkspeed);
1169         pci_push(base);
1170 }
1171
1172 static void nv_stop_rx(struct net_device *dev)
1173 {
1174         u8 __iomem *base = get_hwbase(dev);
1175
1176         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1177         writel(0, base + NvRegReceiverControl);
1178         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1179                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1180                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1181
1182         udelay(NV_RXSTOP_DELAY2);
1183         writel(0, base + NvRegLinkSpeed);
1184 }
1185
1186 static void nv_start_tx(struct net_device *dev)
1187 {
1188         u8 __iomem *base = get_hwbase(dev);
1189
1190         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1191         writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
1192         pci_push(base);
1193 }
1194
1195 static void nv_stop_tx(struct net_device *dev)
1196 {
1197         u8 __iomem *base = get_hwbase(dev);
1198
1199         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1200         writel(0, base + NvRegTransmitterControl);
1201         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1202                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1203                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1204
1205         udelay(NV_TXSTOP_DELAY2);
1206         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
1207 }
1208
1209 static void nv_txrx_reset(struct net_device *dev)
1210 {
1211         struct fe_priv *np = netdev_priv(dev);
1212         u8 __iomem *base = get_hwbase(dev);
1213
1214         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1215         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1216         pci_push(base);
1217         udelay(NV_TXRX_RESET_DELAY);
1218         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1219         pci_push(base);
1220 }
1221
1222 static void nv_mac_reset(struct net_device *dev)
1223 {
1224         struct fe_priv *np = netdev_priv(dev);
1225         u8 __iomem *base = get_hwbase(dev);
1226
1227         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1228         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1229         pci_push(base);
1230         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1231         pci_push(base);
1232         udelay(NV_MAC_RESET_DELAY);
1233         writel(0, base + NvRegMacReset);
1234         pci_push(base);
1235         udelay(NV_MAC_RESET_DELAY);
1236         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1237         pci_push(base);
1238 }
1239
1240 /*
1241  * nv_get_stats: dev->get_stats function
1242  * Get latest stats value from the nic.
1243  * Called with read_lock(&dev_base_lock) held for read -
1244  * only synchronized against unregister_netdevice.
1245  */
1246 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1247 {
1248         struct fe_priv *np = netdev_priv(dev);
1249
1250         /* It seems that the nic always generates interrupts and doesn't
1251          * accumulate errors internally. Thus the current values in np->stats
1252          * are already up to date.
1253          */
1254         return &np->stats;
1255 }
1256
1257 /*
1258  * nv_alloc_rx: fill rx ring entries.
1259  * Return 1 if the allocations for the skbs failed and the
1260  * rx engine is without Available descriptors
1261  */
1262 static int nv_alloc_rx(struct net_device *dev)
1263 {
1264         struct fe_priv *np = netdev_priv(dev);
1265         unsigned int refill_rx = np->refill_rx;
1266         int nr;
1267
1268         while (np->cur_rx != refill_rx) {
1269                 struct sk_buff *skb;
1270
1271                 nr = refill_rx % np->rx_ring_size;
1272                 if (np->rx_skbuff[nr] == NULL) {
1273
1274                         skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1275                         if (!skb)
1276                                 break;
1277
1278                         skb->dev = dev;
1279                         np->rx_skbuff[nr] = skb;
1280                 } else {
1281                         skb = np->rx_skbuff[nr];
1282                 }
1283                 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data,
1284                                         skb->end-skb->data, PCI_DMA_FROMDEVICE);
1285                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1286                         np->rx_ring.orig[nr].buf = cpu_to_le32(np->rx_dma[nr]);
1287                         wmb();
1288                         np->rx_ring.orig[nr].flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1289                 } else {
1290                         np->rx_ring.ex[nr].bufhigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
1291                         np->rx_ring.ex[nr].buflow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
1292                         wmb();
1293                         np->rx_ring.ex[nr].flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1294                 }
1295                 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
1296                                         dev->name, refill_rx);
1297                 refill_rx++;
1298         }
1299         np->refill_rx = refill_rx;
1300         if (np->cur_rx - refill_rx == np->rx_ring_size)
1301                 return 1;
1302         return 0;
1303 }
1304
1305 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1306 #ifdef CONFIG_FORCEDETH_NAPI
1307 static void nv_do_rx_refill(unsigned long data)
1308 {
1309         struct net_device *dev = (struct net_device *) data;
1310
1311         /* Just reschedule NAPI rx processing */
1312         netif_rx_schedule(dev);
1313 }
1314 #else
1315 static void nv_do_rx_refill(unsigned long data)
1316 {
1317         struct net_device *dev = (struct net_device *) data;
1318         struct fe_priv *np = netdev_priv(dev);
1319
1320         if (!using_multi_irqs(dev)) {
1321                 if (np->msi_flags & NV_MSI_X_ENABLED)
1322                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1323                 else
1324                         disable_irq(dev->irq);
1325         } else {
1326                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1327         }
1328         if (nv_alloc_rx(dev)) {
1329                 spin_lock_irq(&np->lock);
1330                 if (!np->in_shutdown)
1331                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1332                 spin_unlock_irq(&np->lock);
1333         }
1334         if (!using_multi_irqs(dev)) {
1335                 if (np->msi_flags & NV_MSI_X_ENABLED)
1336                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1337                 else
1338                         enable_irq(dev->irq);
1339         } else {
1340                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1341         }
1342 }
1343 #endif
1344
1345 static void nv_init_rx(struct net_device *dev)
1346 {
1347         struct fe_priv *np = netdev_priv(dev);
1348         int i;
1349
1350         np->cur_rx = np->rx_ring_size;
1351         np->refill_rx = 0;
1352         for (i = 0; i < np->rx_ring_size; i++)
1353                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1354                         np->rx_ring.orig[i].flaglen = 0;
1355                 else
1356                         np->rx_ring.ex[i].flaglen = 0;
1357 }
1358
1359 static void nv_init_tx(struct net_device *dev)
1360 {
1361         struct fe_priv *np = netdev_priv(dev);
1362         int i;
1363
1364         np->next_tx = np->nic_tx = 0;
1365         for (i = 0; i < np->tx_ring_size; i++) {
1366                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1367                         np->tx_ring.orig[i].flaglen = 0;
1368                 else
1369                         np->tx_ring.ex[i].flaglen = 0;
1370                 np->tx_skbuff[i] = NULL;
1371                 np->tx_dma[i] = 0;
1372         }
1373 }
1374
1375 static int nv_init_ring(struct net_device *dev)
1376 {
1377         nv_init_tx(dev);
1378         nv_init_rx(dev);
1379         return nv_alloc_rx(dev);
1380 }
1381
1382 static int nv_release_txskb(struct net_device *dev, unsigned int skbnr)
1383 {
1384         struct fe_priv *np = netdev_priv(dev);
1385
1386         dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d\n",
1387                 dev->name, skbnr);
1388
1389         if (np->tx_dma[skbnr]) {
1390                 pci_unmap_page(np->pci_dev, np->tx_dma[skbnr],
1391                                np->tx_dma_len[skbnr],
1392                                PCI_DMA_TODEVICE);
1393                 np->tx_dma[skbnr] = 0;
1394         }
1395
1396         if (np->tx_skbuff[skbnr]) {
1397                 dev_kfree_skb_any(np->tx_skbuff[skbnr]);
1398                 np->tx_skbuff[skbnr] = NULL;
1399                 return 1;
1400         } else {
1401                 return 0;
1402         }
1403 }
1404
1405 static void nv_drain_tx(struct net_device *dev)
1406 {
1407         struct fe_priv *np = netdev_priv(dev);
1408         unsigned int i;
1409
1410         for (i = 0; i < np->tx_ring_size; i++) {
1411                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1412                         np->tx_ring.orig[i].flaglen = 0;
1413                 else
1414                         np->tx_ring.ex[i].flaglen = 0;
1415                 if (nv_release_txskb(dev, i))
1416                         np->stats.tx_dropped++;
1417         }
1418 }
1419
1420 static void nv_drain_rx(struct net_device *dev)
1421 {
1422         struct fe_priv *np = netdev_priv(dev);
1423         int i;
1424         for (i = 0; i < np->rx_ring_size; i++) {
1425                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1426                         np->rx_ring.orig[i].flaglen = 0;
1427                 else
1428                         np->rx_ring.ex[i].flaglen = 0;
1429                 wmb();
1430                 if (np->rx_skbuff[i]) {
1431                         pci_unmap_single(np->pci_dev, np->rx_dma[i],
1432                                                 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1433                                                 PCI_DMA_FROMDEVICE);
1434                         dev_kfree_skb(np->rx_skbuff[i]);
1435                         np->rx_skbuff[i] = NULL;
1436                 }
1437         }
1438 }
1439
1440 static void drain_ring(struct net_device *dev)
1441 {
1442         nv_drain_tx(dev);
1443         nv_drain_rx(dev);
1444 }
1445
1446 /*
1447  * nv_start_xmit: dev->hard_start_xmit function
1448  * Called with netif_tx_lock held.
1449  */
1450 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1451 {
1452         struct fe_priv *np = netdev_priv(dev);
1453         u32 tx_flags = 0;
1454         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1455         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1456         unsigned int nr = (np->next_tx - 1) % np->tx_ring_size;
1457         unsigned int start_nr = np->next_tx % np->tx_ring_size;
1458         unsigned int i;
1459         u32 offset = 0;
1460         u32 bcnt;
1461         u32 size = skb->len-skb->data_len;
1462         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1463         u32 tx_flags_vlan = 0;
1464
1465         /* add fragments to entries count */
1466         for (i = 0; i < fragments; i++) {
1467                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1468                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1469         }
1470
1471         spin_lock_irq(&np->lock);
1472
1473         if ((np->next_tx - np->nic_tx + entries - 1) > np->tx_limit_stop) {
1474                 spin_unlock_irq(&np->lock);
1475                 netif_stop_queue(dev);
1476                 return NETDEV_TX_BUSY;
1477         }
1478
1479         /* setup the header buffer */
1480         do {
1481                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1482                 nr = (nr + 1) % np->tx_ring_size;
1483
1484                 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1485                                                 PCI_DMA_TODEVICE);
1486                 np->tx_dma_len[nr] = bcnt;
1487
1488                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1489                         np->tx_ring.orig[nr].buf = cpu_to_le32(np->tx_dma[nr]);
1490                         np->tx_ring.orig[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1491                 } else {
1492                         np->tx_ring.ex[nr].bufhigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1493                         np->tx_ring.ex[nr].buflow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1494                         np->tx_ring.ex[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1495                 }
1496                 tx_flags = np->tx_flags;
1497                 offset += bcnt;
1498                 size -= bcnt;
1499         } while (size);
1500
1501         /* setup the fragments */
1502         for (i = 0; i < fragments; i++) {
1503                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1504                 u32 size = frag->size;
1505                 offset = 0;
1506
1507                 do {
1508                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1509                         nr = (nr + 1) % np->tx_ring_size;
1510
1511                         np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1512                                                       PCI_DMA_TODEVICE);
1513                         np->tx_dma_len[nr] = bcnt;
1514
1515                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1516                                 np->tx_ring.orig[nr].buf = cpu_to_le32(np->tx_dma[nr]);
1517                                 np->tx_ring.orig[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1518                         } else {
1519                                 np->tx_ring.ex[nr].bufhigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1520                                 np->tx_ring.ex[nr].buflow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1521                                 np->tx_ring.ex[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1522                         }
1523                         offset += bcnt;
1524                         size -= bcnt;
1525                 } while (size);
1526         }
1527
1528         /* set last fragment flag  */
1529         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1530                 np->tx_ring.orig[nr].flaglen |= cpu_to_le32(tx_flags_extra);
1531         } else {
1532                 np->tx_ring.ex[nr].flaglen |= cpu_to_le32(tx_flags_extra);
1533         }
1534
1535         np->tx_skbuff[nr] = skb;
1536
1537 #ifdef NETIF_F_TSO
1538         if (skb_is_gso(skb))
1539                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1540         else
1541 #endif
1542         tx_flags_extra = (skb->ip_summed == CHECKSUM_HW ? (NV_TX2_CHECKSUM_L3|NV_TX2_CHECKSUM_L4) : 0);
1543
1544         /* vlan tag */
1545         if (np->vlangrp && vlan_tx_tag_present(skb)) {
1546                 tx_flags_vlan = NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb);
1547         }
1548
1549         /* set tx flags */
1550         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1551                 np->tx_ring.orig[start_nr].flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1552         } else {
1553                 np->tx_ring.ex[start_nr].txvlan = cpu_to_le32(tx_flags_vlan);
1554                 np->tx_ring.ex[start_nr].flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1555         }
1556
1557         dprintk(KERN_DEBUG "%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n",
1558                 dev->name, np->next_tx, entries, tx_flags_extra);
1559         {
1560                 int j;
1561                 for (j=0; j<64; j++) {
1562                         if ((j%16) == 0)
1563                                 dprintk("\n%03x:", j);
1564                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1565                 }
1566                 dprintk("\n");
1567         }
1568
1569         np->next_tx += entries;
1570
1571         dev->trans_start = jiffies;
1572         spin_unlock_irq(&np->lock);
1573         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1574         pci_push(get_hwbase(dev));
1575         return NETDEV_TX_OK;
1576 }
1577
1578 /*
1579  * nv_tx_done: check for completed packets, release the skbs.
1580  *
1581  * Caller must own np->lock.
1582  */
1583 static void nv_tx_done(struct net_device *dev)
1584 {
1585         struct fe_priv *np = netdev_priv(dev);
1586         u32 flags;
1587         unsigned int i;
1588         struct sk_buff *skb;
1589
1590         while (np->nic_tx != np->next_tx) {
1591                 i = np->nic_tx % np->tx_ring_size;
1592
1593                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1594                         flags = le32_to_cpu(np->tx_ring.orig[i].flaglen);
1595                 else
1596                         flags = le32_to_cpu(np->tx_ring.ex[i].flaglen);
1597
1598                 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, flags 0x%x.\n",
1599                                         dev->name, np->nic_tx, flags);
1600                 if (flags & NV_TX_VALID)
1601                         break;
1602                 if (np->desc_ver == DESC_VER_1) {
1603                         if (flags & NV_TX_LASTPACKET) {
1604                                 skb = np->tx_skbuff[i];
1605                                 if (flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1606                                              NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1607                                         if (flags & NV_TX_UNDERFLOW)
1608                                                 np->stats.tx_fifo_errors++;
1609                                         if (flags & NV_TX_CARRIERLOST)
1610                                                 np->stats.tx_carrier_errors++;
1611                                         np->stats.tx_errors++;
1612                                 } else {
1613                                         np->stats.tx_packets++;
1614                                         np->stats.tx_bytes += skb->len;
1615                                 }
1616                         }
1617                 } else {
1618                         if (flags & NV_TX2_LASTPACKET) {
1619                                 skb = np->tx_skbuff[i];
1620                                 if (flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1621                                              NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1622                                         if (flags & NV_TX2_UNDERFLOW)
1623                                                 np->stats.tx_fifo_errors++;
1624                                         if (flags & NV_TX2_CARRIERLOST)
1625                                                 np->stats.tx_carrier_errors++;
1626                                         np->stats.tx_errors++;
1627                                 } else {
1628                                         np->stats.tx_packets++;
1629                                         np->stats.tx_bytes += skb->len;
1630                                 }
1631                         }
1632                 }
1633                 nv_release_txskb(dev, i);
1634                 np->nic_tx++;
1635         }
1636         if (np->next_tx - np->nic_tx < np->tx_limit_start)
1637                 netif_wake_queue(dev);
1638 }
1639
1640 /*
1641  * nv_tx_timeout: dev->tx_timeout function
1642  * Called with netif_tx_lock held.
1643  */
1644 static void nv_tx_timeout(struct net_device *dev)
1645 {
1646         struct fe_priv *np = netdev_priv(dev);
1647         u8 __iomem *base = get_hwbase(dev);
1648         u32 status;
1649
1650         if (np->msi_flags & NV_MSI_X_ENABLED)
1651                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
1652         else
1653                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1654
1655         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
1656
1657         {
1658                 int i;
1659
1660                 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
1661                                 dev->name, (unsigned long)np->ring_addr,
1662                                 np->next_tx, np->nic_tx);
1663                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1664                 for (i=0;i<=np->register_size;i+= 32) {
1665                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1666                                         i,
1667                                         readl(base + i + 0), readl(base + i + 4),
1668                                         readl(base + i + 8), readl(base + i + 12),
1669                                         readl(base + i + 16), readl(base + i + 20),
1670                                         readl(base + i + 24), readl(base + i + 28));
1671                 }
1672                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1673                 for (i=0;i<np->tx_ring_size;i+= 4) {
1674                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1675                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1676                                        i,
1677                                        le32_to_cpu(np->tx_ring.orig[i].buf),
1678                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
1679                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
1680                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
1681                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
1682                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
1683                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
1684                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
1685                         } else {
1686                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1687                                        i,
1688                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
1689                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
1690                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
1691                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
1692                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
1693                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
1694                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
1695                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
1696                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
1697                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
1698                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
1699                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
1700                         }
1701                 }
1702         }
1703
1704         spin_lock_irq(&np->lock);
1705
1706         /* 1) stop tx engine */
1707         nv_stop_tx(dev);
1708
1709         /* 2) check that the packets were not sent already: */
1710         nv_tx_done(dev);
1711
1712         /* 3) if there are dead entries: clear everything */
1713         if (np->next_tx != np->nic_tx) {
1714                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1715                 nv_drain_tx(dev);
1716                 np->next_tx = np->nic_tx = 0;
1717                 setup_hw_rings(dev, NV_SETUP_TX_RING);
1718                 netif_wake_queue(dev);
1719         }
1720
1721         /* 4) restart tx engine */
1722         nv_start_tx(dev);
1723         spin_unlock_irq(&np->lock);
1724 }
1725
1726 /*
1727  * Called when the nic notices a mismatch between the actual data len on the
1728  * wire and the len indicated in the 802 header
1729  */
1730 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1731 {
1732         int hdrlen;     /* length of the 802 header */
1733         int protolen;   /* length as stored in the proto field */
1734
1735         /* 1) calculate len according to header */
1736         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
1737                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1738                 hdrlen = VLAN_HLEN;
1739         } else {
1740                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1741                 hdrlen = ETH_HLEN;
1742         }
1743         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1744                                 dev->name, datalen, protolen, hdrlen);
1745         if (protolen > ETH_DATA_LEN)
1746                 return datalen; /* Value in proto field not a len, no checks possible */
1747
1748         protolen += hdrlen;
1749         /* consistency checks: */
1750         if (datalen > ETH_ZLEN) {
1751                 if (datalen >= protolen) {
1752                         /* more data on wire than in 802 header, trim of
1753                          * additional data.
1754                          */
1755                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1756                                         dev->name, protolen);
1757                         return protolen;
1758                 } else {
1759                         /* less data on wire than mentioned in header.
1760                          * Discard the packet.
1761                          */
1762                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1763                                         dev->name);
1764                         return -1;
1765                 }
1766         } else {
1767                 /* short packet. Accept only if 802 values are also short */
1768                 if (protolen > ETH_ZLEN) {
1769                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1770                                         dev->name);
1771                         return -1;
1772                 }
1773                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1774                                 dev->name, datalen);
1775                 return datalen;
1776         }
1777 }
1778
1779 static int nv_rx_process(struct net_device *dev, int limit)
1780 {
1781         struct fe_priv *np = netdev_priv(dev);
1782         u32 flags;
1783         u32 vlanflags = 0;
1784         int count;
1785
1786         for (count = 0; count < limit; ++count) {
1787                 struct sk_buff *skb;
1788                 int len;
1789                 int i;
1790                 if (np->cur_rx - np->refill_rx >= np->rx_ring_size)
1791                         break;  /* we scanned the whole ring - do not continue */
1792
1793                 i = np->cur_rx % np->rx_ring_size;
1794                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1795                         flags = le32_to_cpu(np->rx_ring.orig[i].flaglen);
1796                         len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
1797                 } else {
1798                         flags = le32_to_cpu(np->rx_ring.ex[i].flaglen);
1799                         len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
1800                         vlanflags = le32_to_cpu(np->rx_ring.ex[i].buflow);
1801                 }
1802
1803                 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, flags 0x%x.\n",
1804                                         dev->name, np->cur_rx, flags);
1805
1806                 if (flags & NV_RX_AVAIL)
1807                         break;  /* still owned by hardware, */
1808
1809                 /*
1810                  * the packet is for us - immediately tear down the pci mapping.
1811                  * TODO: check if a prefetch of the first cacheline improves
1812                  * the performance.
1813                  */
1814                 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1815                                 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1816                                 PCI_DMA_FROMDEVICE);
1817
1818                 {
1819                         int j;
1820                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
1821                         for (j=0; j<64; j++) {
1822                                 if ((j%16) == 0)
1823                                         dprintk("\n%03x:", j);
1824                                 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1825                         }
1826                         dprintk("\n");
1827                 }
1828                 /* look at what we actually got: */
1829                 if (np->desc_ver == DESC_VER_1) {
1830                         if (!(flags & NV_RX_DESCRIPTORVALID))
1831                                 goto next_pkt;
1832
1833                         if (flags & NV_RX_ERROR) {
1834                                 if (flags & NV_RX_MISSEDFRAME) {
1835                                         np->stats.rx_missed_errors++;
1836                                         np->stats.rx_errors++;
1837                                         goto next_pkt;
1838                                 }
1839                                 if (flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1840                                         np->stats.rx_errors++;
1841                                         goto next_pkt;
1842                                 }
1843                                 if (flags & NV_RX_CRCERR) {
1844                                         np->stats.rx_crc_errors++;
1845                                         np->stats.rx_errors++;
1846                                         goto next_pkt;
1847                                 }
1848                                 if (flags & NV_RX_OVERFLOW) {
1849                                         np->stats.rx_over_errors++;
1850                                         np->stats.rx_errors++;
1851                                         goto next_pkt;
1852                                 }
1853                                 if (flags & NV_RX_ERROR4) {
1854                                         len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1855                                         if (len < 0) {
1856                                                 np->stats.rx_errors++;
1857                                                 goto next_pkt;
1858                                         }
1859                                 }
1860                                 /* framing errors are soft errors. */
1861                                 if (flags & NV_RX_FRAMINGERR) {
1862                                         if (flags & NV_RX_SUBSTRACT1) {
1863                                                 len--;
1864                                         }
1865                                 }
1866                         }
1867                 } else {
1868                         if (!(flags & NV_RX2_DESCRIPTORVALID))
1869                                 goto next_pkt;
1870
1871                         if (flags & NV_RX2_ERROR) {
1872                                 if (flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
1873                                         np->stats.rx_errors++;
1874                                         goto next_pkt;
1875                                 }
1876                                 if (flags & NV_RX2_CRCERR) {
1877                                         np->stats.rx_crc_errors++;
1878                                         np->stats.rx_errors++;
1879                                         goto next_pkt;
1880                                 }
1881                                 if (flags & NV_RX2_OVERFLOW) {
1882                                         np->stats.rx_over_errors++;
1883                                         np->stats.rx_errors++;
1884                                         goto next_pkt;
1885                                 }
1886                                 if (flags & NV_RX2_ERROR4) {
1887                                         len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1888                                         if (len < 0) {
1889                                                 np->stats.rx_errors++;
1890                                                 goto next_pkt;
1891                                         }
1892                                 }
1893                                 /* framing errors are soft errors */
1894                                 if (flags & NV_RX2_FRAMINGERR) {
1895                                         if (flags & NV_RX2_SUBSTRACT1) {
1896                                                 len--;
1897                                         }
1898                                 }
1899                         }
1900                         if (np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) {
1901                                 flags &= NV_RX2_CHECKSUMMASK;
1902                                 if (flags == NV_RX2_CHECKSUMOK1 ||
1903                                     flags == NV_RX2_CHECKSUMOK2 ||
1904                                     flags == NV_RX2_CHECKSUMOK3) {
1905                                         dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1906                                         np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1907                                 } else {
1908                                         dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1909                                 }
1910                         }
1911                 }
1912                 /* got a valid packet - forward it to the network core */
1913                 skb = np->rx_skbuff[i];
1914                 np->rx_skbuff[i] = NULL;
1915
1916                 skb_put(skb, len);
1917                 skb->protocol = eth_type_trans(skb, dev);
1918                 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1919                                         dev->name, np->cur_rx, len, skb->protocol);
1920 #ifdef CONFIG_FORCEDETH_NAPI
1921                 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
1922                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
1923                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
1924                 else
1925                         netif_receive_skb(skb);
1926 #else
1927                 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
1928                         vlan_hwaccel_rx(skb, np->vlangrp,
1929                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
1930                 else
1931                         netif_rx(skb);
1932 #endif
1933                 dev->last_rx = jiffies;
1934                 np->stats.rx_packets++;
1935                 np->stats.rx_bytes += len;
1936 next_pkt:
1937                 np->cur_rx++;
1938         }
1939
1940         return count;
1941 }
1942
1943 static void set_bufsize(struct net_device *dev)
1944 {
1945         struct fe_priv *np = netdev_priv(dev);
1946
1947         if (dev->mtu <= ETH_DATA_LEN)
1948                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
1949         else
1950                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
1951 }
1952
1953 /*
1954  * nv_change_mtu: dev->change_mtu function
1955  * Called with dev_base_lock held for read.
1956  */
1957 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1958 {
1959         struct fe_priv *np = netdev_priv(dev);
1960         int old_mtu;
1961
1962         if (new_mtu < 64 || new_mtu > np->pkt_limit)
1963                 return -EINVAL;
1964
1965         old_mtu = dev->mtu;
1966         dev->mtu = new_mtu;
1967
1968         /* return early if the buffer sizes will not change */
1969         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1970                 return 0;
1971         if (old_mtu == new_mtu)
1972                 return 0;
1973
1974         /* synchronized against open : rtnl_lock() held by caller */
1975         if (netif_running(dev)) {
1976                 u8 __iomem *base = get_hwbase(dev);
1977                 /*
1978                  * It seems that the nic preloads valid ring entries into an
1979                  * internal buffer. The procedure for flushing everything is
1980                  * guessed, there is probably a simpler approach.
1981                  * Changing the MTU is a rare event, it shouldn't matter.
1982                  */
1983                 nv_disable_irq(dev);
1984                 netif_tx_lock_bh(dev);
1985                 spin_lock(&np->lock);
1986                 /* stop engines */
1987                 nv_stop_rx(dev);
1988                 nv_stop_tx(dev);
1989                 nv_txrx_reset(dev);
1990                 /* drain rx queue */
1991                 nv_drain_rx(dev);
1992                 nv_drain_tx(dev);
1993                 /* reinit driver view of the rx queue */
1994                 set_bufsize(dev);
1995                 if (nv_init_ring(dev)) {
1996                         if (!np->in_shutdown)
1997                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1998                 }
1999                 /* reinit nic view of the rx queue */
2000                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2001                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2002                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2003                         base + NvRegRingSizes);
2004                 pci_push(base);
2005                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2006                 pci_push(base);
2007
2008                 /* restart rx engine */
2009                 nv_start_rx(dev);
2010                 nv_start_tx(dev);
2011                 spin_unlock(&np->lock);
2012                 netif_tx_unlock_bh(dev);
2013                 nv_enable_irq(dev);
2014         }
2015         return 0;
2016 }
2017
2018 static void nv_copy_mac_to_hw(struct net_device *dev)
2019 {
2020         u8 __iomem *base = get_hwbase(dev);
2021         u32 mac[2];
2022
2023         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2024                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2025         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2026
2027         writel(mac[0], base + NvRegMacAddrA);
2028         writel(mac[1], base + NvRegMacAddrB);
2029 }
2030
2031 /*
2032  * nv_set_mac_address: dev->set_mac_address function
2033  * Called with rtnl_lock() held.
2034  */
2035 static int nv_set_mac_address(struct net_device *dev, void *addr)
2036 {
2037         struct fe_priv *np = netdev_priv(dev);
2038         struct sockaddr *macaddr = (struct sockaddr*)addr;
2039
2040         if (!is_valid_ether_addr(macaddr->sa_data))
2041                 return -EADDRNOTAVAIL;
2042
2043         /* synchronized against open : rtnl_lock() held by caller */
2044         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2045
2046         if (netif_running(dev)) {
2047                 netif_tx_lock_bh(dev);
2048                 spin_lock_irq(&np->lock);
2049
2050                 /* stop rx engine */
2051                 nv_stop_rx(dev);
2052
2053                 /* set mac address */
2054                 nv_copy_mac_to_hw(dev);
2055
2056                 /* restart rx engine */
2057                 nv_start_rx(dev);
2058                 spin_unlock_irq(&np->lock);
2059                 netif_tx_unlock_bh(dev);
2060         } else {
2061                 nv_copy_mac_to_hw(dev);
2062         }
2063         return 0;
2064 }
2065
2066 /*
2067  * nv_set_multicast: dev->set_multicast function
2068  * Called with netif_tx_lock held.
2069  */
2070 static void nv_set_multicast(struct net_device *dev)
2071 {
2072         struct fe_priv *np = netdev_priv(dev);
2073         u8 __iomem *base = get_hwbase(dev);
2074         u32 addr[2];
2075         u32 mask[2];
2076         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2077
2078         memset(addr, 0, sizeof(addr));
2079         memset(mask, 0, sizeof(mask));
2080
2081         if (dev->flags & IFF_PROMISC) {
2082                 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
2083                 pff |= NVREG_PFF_PROMISC;
2084         } else {
2085                 pff |= NVREG_PFF_MYADDR;
2086
2087                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2088                         u32 alwaysOff[2];
2089                         u32 alwaysOn[2];
2090
2091                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2092                         if (dev->flags & IFF_ALLMULTI) {
2093                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2094                         } else {
2095                                 struct dev_mc_list *walk;
2096
2097                                 walk = dev->mc_list;
2098                                 while (walk != NULL) {
2099                                         u32 a, b;
2100                                         a = le32_to_cpu(*(u32 *) walk->dmi_addr);
2101                                         b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
2102                                         alwaysOn[0] &= a;
2103                                         alwaysOff[0] &= ~a;
2104                                         alwaysOn[1] &= b;
2105                                         alwaysOff[1] &= ~b;
2106                                         walk = walk->next;
2107                                 }
2108                         }
2109                         addr[0] = alwaysOn[0];
2110                         addr[1] = alwaysOn[1];
2111                         mask[0] = alwaysOn[0] | alwaysOff[0];
2112                         mask[1] = alwaysOn[1] | alwaysOff[1];
2113                 }
2114         }
2115         addr[0] |= NVREG_MCASTADDRA_FORCE;
2116         pff |= NVREG_PFF_ALWAYS;
2117         spin_lock_irq(&np->lock);
2118         nv_stop_rx(dev);
2119         writel(addr[0], base + NvRegMulticastAddrA);
2120         writel(addr[1], base + NvRegMulticastAddrB);
2121         writel(mask[0], base + NvRegMulticastMaskA);
2122         writel(mask[1], base + NvRegMulticastMaskB);
2123         writel(pff, base + NvRegPacketFilterFlags);
2124         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2125                 dev->name);
2126         nv_start_rx(dev);
2127         spin_unlock_irq(&np->lock);
2128 }
2129
2130 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2131 {
2132         struct fe_priv *np = netdev_priv(dev);
2133         u8 __iomem *base = get_hwbase(dev);
2134
2135         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2136
2137         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2138                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2139                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2140                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2141                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2142                 } else {
2143                         writel(pff, base + NvRegPacketFilterFlags);
2144                 }
2145         }
2146         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2147                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2148                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2149                         writel(NVREG_TX_PAUSEFRAME_ENABLE,  base + NvRegTxPauseFrame);
2150                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2151                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2152                 } else {
2153                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
2154                         writel(regmisc, base + NvRegMisc1);
2155                 }
2156         }
2157 }
2158
2159 /**
2160  * nv_update_linkspeed: Setup the MAC according to the link partner
2161  * @dev: Network device to be configured
2162  *
2163  * The function queries the PHY and checks if there is a link partner.
2164  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2165  * set to 10 MBit HD.
2166  *
2167  * The function returns 0 if there is no link partner and 1 if there is
2168  * a good link partner.
2169  */
2170 static int nv_update_linkspeed(struct net_device *dev)
2171 {
2172         struct fe_priv *np = netdev_priv(dev);
2173         u8 __iomem *base = get_hwbase(dev);
2174         int adv = 0;
2175         int lpa = 0;
2176         int adv_lpa, adv_pause, lpa_pause;
2177         int newls = np->linkspeed;
2178         int newdup = np->duplex;
2179         int mii_status;
2180         int retval = 0;
2181         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
2182
2183         /* BMSR_LSTATUS is latched, read it twice:
2184          * we want the current value.
2185          */
2186         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2187         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2188
2189         if (!(mii_status & BMSR_LSTATUS)) {
2190                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2191                                 dev->name);
2192                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2193                 newdup = 0;
2194                 retval = 0;
2195                 goto set_speed;
2196         }
2197
2198         if (np->autoneg == 0) {
2199                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2200                                 dev->name, np->fixed_mode);
2201                 if (np->fixed_mode & LPA_100FULL) {
2202                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2203                         newdup = 1;
2204                 } else if (np->fixed_mode & LPA_100HALF) {
2205                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2206                         newdup = 0;
2207                 } else if (np->fixed_mode & LPA_10FULL) {
2208                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2209                         newdup = 1;
2210                 } else {
2211                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2212                         newdup = 0;
2213                 }
2214                 retval = 1;
2215                 goto set_speed;
2216         }
2217         /* check auto negotiation is complete */
2218         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2219                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2220                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2221                 newdup = 0;
2222                 retval = 0;
2223                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2224                 goto set_speed;
2225         }
2226
2227         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2228         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2229         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2230                                 dev->name, adv, lpa);
2231
2232         retval = 1;
2233         if (np->gigabit == PHY_GIGABIT) {
2234                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2235                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2236
2237                 if ((control_1000 & ADVERTISE_1000FULL) &&
2238                         (status_1000 & LPA_1000FULL)) {
2239                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2240                                 dev->name);
2241                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2242                         newdup = 1;
2243                         goto set_speed;
2244                 }
2245         }
2246
2247         /* FIXME: handle parallel detection properly */
2248         adv_lpa = lpa & adv;
2249         if (adv_lpa & LPA_100FULL) {
2250                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2251                 newdup = 1;
2252         } else if (adv_lpa & LPA_100HALF) {
2253                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2254                 newdup = 0;
2255         } else if (adv_lpa & LPA_10FULL) {
2256                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2257                 newdup = 1;
2258         } else if (adv_lpa & LPA_10HALF) {
2259                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2260                 newdup = 0;
2261         } else {
2262                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2263                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2264                 newdup = 0;
2265         }
2266
2267 set_speed:
2268         if (np->duplex == newdup && np->linkspeed == newls)
2269                 return retval;
2270
2271         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2272                         dev->name, np->linkspeed, np->duplex, newls, newdup);
2273
2274         np->duplex = newdup;
2275         np->linkspeed = newls;
2276
2277         if (np->gigabit == PHY_GIGABIT) {
2278                 phyreg = readl(base + NvRegRandomSeed);
2279                 phyreg &= ~(0x3FF00);
2280                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2281                         phyreg |= NVREG_RNDSEED_FORCE3;
2282                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2283                         phyreg |= NVREG_RNDSEED_FORCE2;
2284                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2285                         phyreg |= NVREG_RNDSEED_FORCE;
2286                 writel(phyreg, base + NvRegRandomSeed);
2287         }
2288
2289         phyreg = readl(base + NvRegPhyInterface);
2290         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2291         if (np->duplex == 0)
2292                 phyreg |= PHY_HALF;
2293         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2294                 phyreg |= PHY_100;
2295         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2296                 phyreg |= PHY_1000;
2297         writel(phyreg, base + NvRegPhyInterface);
2298
2299         if (phyreg & PHY_RGMII) {
2300                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2301                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
2302                 else
2303                         txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
2304         } else {
2305                 txreg = NVREG_TX_DEFERRAL_DEFAULT;
2306         }
2307         writel(txreg, base + NvRegTxDeferral);
2308
2309         if (np->desc_ver == DESC_VER_1) {
2310                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
2311         } else {
2312                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2313                         txreg = NVREG_TX_WM_DESC2_3_1000;
2314                 else
2315                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
2316         }
2317         writel(txreg, base + NvRegTxWatermark);
2318
2319         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2320                 base + NvRegMisc1);
2321         pci_push(base);
2322         writel(np->linkspeed, base + NvRegLinkSpeed);
2323         pci_push(base);
2324
2325         pause_flags = 0;
2326         /* setup pause frame */
2327         if (np->duplex != 0) {
2328                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
2329                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
2330                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
2331
2332                         switch (adv_pause) {
2333                         case ADVERTISE_PAUSE_CAP:
2334                                 if (lpa_pause & LPA_PAUSE_CAP) {
2335                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2336                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2337                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2338                                 }
2339                                 break;
2340                         case ADVERTISE_PAUSE_ASYM:
2341                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
2342                                 {
2343                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2344                                 }
2345                                 break;
2346                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
2347                                 if (lpa_pause & LPA_PAUSE_CAP)
2348                                 {
2349                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
2350                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2351                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2352                                 }
2353                                 if (lpa_pause == LPA_PAUSE_ASYM)
2354                                 {
2355                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2356                                 }
2357                                 break;
2358                         }
2359                 } else {
2360                         pause_flags = np->pause_flags;
2361                 }
2362         }
2363         nv_update_pause(dev, pause_flags);
2364
2365         return retval;
2366 }
2367
2368 static void nv_linkchange(struct net_device *dev)
2369 {
2370         if (nv_update_linkspeed(dev)) {
2371                 if (!netif_carrier_ok(dev)) {
2372                         netif_carrier_on(dev);
2373                         printk(KERN_INFO "%s: link up.\n", dev->name);
2374                         nv_start_rx(dev);
2375                 }
2376         } else {
2377                 if (netif_carrier_ok(dev)) {
2378                         netif_carrier_off(dev);
2379                         printk(KERN_INFO "%s: link down.\n", dev->name);
2380                         nv_stop_rx(dev);
2381                 }
2382         }
2383 }
2384
2385 static void nv_link_irq(struct net_device *dev)
2386 {
2387         u8 __iomem *base = get_hwbase(dev);
2388         u32 miistat;
2389
2390         miistat = readl(base + NvRegMIIStatus);
2391         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2392         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
2393
2394         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
2395                 nv_linkchange(dev);
2396         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
2397 }
2398
2399 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
2400 {
2401         struct net_device *dev = (struct net_device *) data;
2402         struct fe_priv *np = netdev_priv(dev);
2403         u8 __iomem *base = get_hwbase(dev);
2404         u32 events;
2405         int i;
2406
2407         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
2408
2409         for (i=0; ; i++) {
2410                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2411                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2412                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2413                 } else {
2414                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2415                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2416                 }
2417                 pci_push(base);
2418                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2419                 if (!(events & np->irqmask))
2420                         break;
2421
2422                 spin_lock(&np->lock);
2423                 nv_tx_done(dev);
2424                 spin_unlock(&np->lock);
2425
2426                 if (events & NVREG_IRQ_LINK) {
2427                         spin_lock(&np->lock);
2428                         nv_link_irq(dev);
2429                         spin_unlock(&np->lock);
2430                 }
2431                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2432                         spin_lock(&np->lock);
2433                         nv_linkchange(dev);
2434                         spin_unlock(&np->lock);
2435                         np->link_timeout = jiffies + LINK_TIMEOUT;
2436                 }
2437                 if (events & (NVREG_IRQ_TX_ERR)) {
2438                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2439                                                 dev->name, events);
2440                 }
2441                 if (events & (NVREG_IRQ_UNKNOWN)) {
2442                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2443                                                 dev->name, events);
2444                 }
2445 #ifdef CONFIG_FORCEDETH_NAPI
2446                 if (events & NVREG_IRQ_RX_ALL) {
2447                         netif_rx_schedule(dev);
2448
2449                         /* Disable furthur receive irq's */
2450                         spin_lock(&np->lock);
2451                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
2452
2453                         if (np->msi_flags & NV_MSI_X_ENABLED)
2454                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2455                         else
2456                                 writel(np->irqmask, base + NvRegIrqMask);
2457                         spin_unlock(&np->lock);
2458                 }
2459 #else
2460                 nv_rx_process(dev, dev->weight);
2461                 if (nv_alloc_rx(dev)) {
2462                         spin_lock(&np->lock);
2463                         if (!np->in_shutdown)
2464                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2465                         spin_unlock(&np->lock);
2466                 }
2467 #endif
2468                 if (i > max_interrupt_work) {
2469                         spin_lock(&np->lock);
2470                         /* disable interrupts on the nic */
2471                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
2472                                 writel(0, base + NvRegIrqMask);
2473                         else
2474                                 writel(np->irqmask, base + NvRegIrqMask);
2475                         pci_push(base);
2476
2477                         if (!np->in_shutdown) {
2478                                 np->nic_poll_irq = np->irqmask;
2479                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2480                         }
2481                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
2482                         spin_unlock(&np->lock);
2483                         break;
2484                 }
2485
2486         }
2487         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
2488
2489         return IRQ_RETVAL(i);
2490 }
2491
2492 static irqreturn_t nv_nic_irq_tx(int foo, void *data, struct pt_regs *regs)
2493 {
2494         struct net_device *dev = (struct net_device *) data;
2495         struct fe_priv *np = netdev_priv(dev);
2496         u8 __iomem *base = get_hwbase(dev);
2497         u32 events;
2498         int i;
2499
2500         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
2501
2502         for (i=0; ; i++) {
2503                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
2504                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
2505                 pci_push(base);
2506                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
2507                 if (!(events & np->irqmask))
2508                         break;
2509
2510                 spin_lock_irq(&np->lock);
2511                 nv_tx_done(dev);
2512                 spin_unlock_irq(&np->lock);
2513
2514                 if (events & (NVREG_IRQ_TX_ERR)) {
2515                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2516                                                 dev->name, events);
2517                 }
2518                 if (i > max_interrupt_work) {
2519                         spin_lock_irq(&np->lock);
2520                         /* disable interrupts on the nic */
2521                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
2522                         pci_push(base);
2523
2524                         if (!np->in_shutdown) {
2525                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
2526                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2527                         }
2528                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
2529                         spin_unlock_irq(&np->lock);
2530                         break;
2531                 }
2532
2533         }
2534         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
2535
2536         return IRQ_RETVAL(i);
2537 }
2538
2539 #ifdef CONFIG_FORCEDETH_NAPI
2540 static int nv_napi_poll(struct net_device *dev, int *budget)
2541 {
2542         int pkts, limit = min(*budget, dev->quota);
2543         struct fe_priv *np = netdev_priv(dev);
2544         u8 __iomem *base = get_hwbase(dev);
2545
2546         pkts = nv_rx_process(dev, limit);
2547
2548         if (nv_alloc_rx(dev)) {
2549                 spin_lock_irq(&np->lock);
2550                 if (!np->in_shutdown)
2551                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2552                 spin_unlock_irq(&np->lock);
2553         }
2554
2555         if (pkts < limit) {
2556                 /* all done, no more packets present */
2557                 netif_rx_complete(dev);
2558
2559                 /* re-enable receive interrupts */
2560                 spin_lock_irq(&np->lock);
2561                 np->irqmask |= NVREG_IRQ_RX_ALL;
2562                 if (np->msi_flags & NV_MSI_X_ENABLED)
2563                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2564                 else
2565                         writel(np->irqmask, base + NvRegIrqMask);
2566                 spin_unlock_irq(&np->lock);
2567                 return 0;
2568         } else {
2569                 /* used up our quantum, so reschedule */
2570                 dev->quota -= pkts;
2571                 *budget -= pkts;
2572                 return 1;
2573         }
2574 }
2575 #endif
2576
2577 #ifdef CONFIG_FORCEDETH_NAPI
2578 static irqreturn_t nv_nic_irq_rx(int foo, void *data, struct pt_regs *regs)
2579 {
2580         struct net_device *dev = (struct net_device *) data;
2581         u8 __iomem *base = get_hwbase(dev);
2582         u32 events;
2583
2584         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
2585         writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
2586
2587         if (events) {
2588                 netif_rx_schedule(dev);
2589                 /* disable receive interrupts on the nic */
2590                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2591                 pci_push(base);
2592         }
2593         return IRQ_HANDLED;
2594 }
2595 #else
2596 static irqreturn_t nv_nic_irq_rx(int foo, void *data, struct pt_regs *regs)
2597 {
2598         struct net_device *dev = (struct net_device *) data;
2599         struct fe_priv *np = netdev_priv(dev);
2600         u8 __iomem *base = get_hwbase(dev);
2601         u32 events;
2602         int i;
2603
2604         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
2605
2606         for (i=0; ; i++) {
2607                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
2608                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
2609                 pci_push(base);
2610                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
2611                 if (!(events & np->irqmask))
2612                         break;
2613
2614                 nv_rx_process(dev, dev->weight);
2615                 if (nv_alloc_rx(dev)) {
2616                         spin_lock_irq(&np->lock);
2617                         if (!np->in_shutdown)
2618                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2619                         spin_unlock_irq(&np->lock);
2620                 }
2621
2622                 if (i > max_interrupt_work) {
2623                         spin_lock_irq(&np->lock);
2624                         /* disable interrupts on the nic */
2625                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2626                         pci_push(base);
2627
2628                         if (!np->in_shutdown) {
2629                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
2630                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2631                         }
2632                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
2633                         spin_unlock_irq(&np->lock);
2634                         break;
2635                 }
2636         }
2637         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
2638
2639         return IRQ_RETVAL(i);
2640 }
2641 #endif
2642
2643 static irqreturn_t nv_nic_irq_other(int foo, void *data, struct pt_regs *regs)
2644 {
2645         struct net_device *dev = (struct net_device *) data;
2646         struct fe_priv *np = netdev_priv(dev);
2647         u8 __iomem *base = get_hwbase(dev);
2648         u32 events;
2649         int i;
2650
2651         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
2652
2653         for (i=0; ; i++) {
2654                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
2655                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
2656                 pci_push(base);
2657                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2658                 if (!(events & np->irqmask))
2659                         break;
2660
2661                 if (events & NVREG_IRQ_LINK) {
2662                         spin_lock_irq(&np->lock);
2663                         nv_link_irq(dev);
2664                         spin_unlock_irq(&np->lock);
2665                 }
2666                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2667                         spin_lock_irq(&np->lock);
2668                         nv_linkchange(dev);
2669                         spin_unlock_irq(&np->lock);
2670                         np->link_timeout = jiffies + LINK_TIMEOUT;
2671                 }
2672                 if (events & (NVREG_IRQ_UNKNOWN)) {
2673                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2674                                                 dev->name, events);
2675                 }
2676                 if (i > max_interrupt_work) {
2677                         spin_lock_irq(&np->lock);
2678                         /* disable interrupts on the nic */
2679                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
2680                         pci_push(base);
2681
2682                         if (!np->in_shutdown) {
2683                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
2684                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2685                         }
2686                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
2687                         spin_unlock_irq(&np->lock);
2688                         break;
2689                 }
2690
2691         }
2692         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
2693
2694         return IRQ_RETVAL(i);
2695 }
2696
2697 static irqreturn_t nv_nic_irq_test(int foo, void *data, struct pt_regs *regs)
2698 {
2699         struct net_device *dev = (struct net_device *) data;
2700         struct fe_priv *np = netdev_priv(dev);
2701         u8 __iomem *base = get_hwbase(dev);
2702         u32 events;
2703
2704         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
2705
2706         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2707                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2708                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
2709         } else {
2710                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2711                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
2712         }
2713         pci_push(base);
2714         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2715         if (!(events & NVREG_IRQ_TIMER))
2716                 return IRQ_RETVAL(0);
2717
2718         spin_lock(&np->lock);
2719         np->intr_test = 1;
2720         spin_unlock(&np->lock);
2721
2722         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
2723
2724         return IRQ_RETVAL(1);
2725 }
2726
2727 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
2728 {
2729         u8 __iomem *base = get_hwbase(dev);
2730         int i;
2731         u32 msixmap = 0;
2732
2733         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
2734          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
2735          * the remaining 8 interrupts.
2736          */
2737         for (i = 0; i < 8; i++) {
2738                 if ((irqmask >> i) & 0x1) {
2739                         msixmap |= vector << (i << 2);
2740                 }
2741         }
2742         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
2743
2744         msixmap = 0;
2745         for (i = 0; i < 8; i++) {
2746                 if ((irqmask >> (i + 8)) & 0x1) {
2747                         msixmap |= vector << (i << 2);
2748                 }
2749         }
2750         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
2751 }
2752
2753 static int nv_request_irq(struct net_device *dev, int intr_test)
2754 {
2755         struct fe_priv *np = get_nvpriv(dev);
2756         u8 __iomem *base = get_hwbase(dev);
2757         int ret = 1;
2758         int i;
2759
2760         if (np->msi_flags & NV_MSI_X_CAPABLE) {
2761                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2762                         np->msi_x_entry[i].entry = i;
2763                 }
2764                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
2765                         np->msi_flags |= NV_MSI_X_ENABLED;
2766                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
2767                                 /* Request irq for rx handling */
2768                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
2769                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
2770                                         pci_disable_msix(np->pci_dev);
2771                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2772                                         goto out_err;
2773                                 }
2774                                 /* Request irq for tx handling */
2775                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
2776                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
2777                                         pci_disable_msix(np->pci_dev);
2778                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2779                                         goto out_free_rx;
2780                                 }
2781                                 /* Request irq for link and timer handling */
2782                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
2783                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
2784                                         pci_disable_msix(np->pci_dev);
2785                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2786                                         goto out_free_tx;
2787                                 }
2788                                 /* map interrupts to their respective vector */
2789                                 writel(0, base + NvRegMSIXMap0);
2790                                 writel(0, base + NvRegMSIXMap1);
2791                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
2792                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
2793                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
2794                         } else {
2795                                 /* Request irq for all interrupts */
2796                                 if ((!intr_test &&
2797                                      request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2798                                     (intr_test &&
2799                                      request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
2800                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2801                                         pci_disable_msix(np->pci_dev);
2802                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2803                                         goto out_err;
2804                                 }
2805
2806                                 /* map interrupts to vector 0 */
2807                                 writel(0, base + NvRegMSIXMap0);
2808                                 writel(0, base + NvRegMSIXMap1);
2809                         }
2810                 }
2811         }
2812         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
2813                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
2814                         np->msi_flags |= NV_MSI_ENABLED;
2815                         if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2816                             (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
2817                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2818                                 pci_disable_msi(np->pci_dev);
2819                                 np->msi_flags &= ~NV_MSI_ENABLED;
2820                                 goto out_err;
2821                         }
2822
2823                         /* map interrupts to vector 0 */
2824                         writel(0, base + NvRegMSIMap0);
2825                         writel(0, base + NvRegMSIMap1);
2826                         /* enable msi vector 0 */
2827                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
2828                 }
2829         }
2830         if (ret != 0) {
2831                 if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2832                     (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0))
2833                         goto out_err;
2834
2835         }
2836
2837         return 0;
2838 out_free_tx:
2839         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
2840 out_free_rx:
2841         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
2842 out_err:
2843         return 1;
2844 }
2845
2846 static void nv_free_irq(struct net_device *dev)
2847 {
2848         struct fe_priv *np = get_nvpriv(dev);
2849         int i;
2850
2851         if (np->msi_flags & NV_MSI_X_ENABLED) {
2852                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2853                         free_irq(np->msi_x_entry[i].vector, dev);
2854                 }
2855                 pci_disable_msix(np->pci_dev);
2856                 np->msi_flags &= ~NV_MSI_X_ENABLED;
2857         } else {
2858                 free_irq(np->pci_dev->irq, dev);
2859                 if (np->msi_flags & NV_MSI_ENABLED) {
2860                         pci_disable_msi(np->pci_dev);
2861                         np->msi_flags &= ~NV_MSI_ENABLED;
2862                 }
2863         }
2864 }
2865
2866 static void nv_do_nic_poll(unsigned long data)
2867 {
2868         struct net_device *dev = (struct net_device *) data;
2869         struct fe_priv *np = netdev_priv(dev);
2870         u8 __iomem *base = get_hwbase(dev);
2871         u32 mask = 0;
2872
2873         /*
2874          * First disable irq(s) and then
2875          * reenable interrupts on the nic, we have to do this before calling
2876          * nv_nic_irq because that may decide to do otherwise
2877          */
2878
2879         if (!using_multi_irqs(dev)) {
2880                 if (np->msi_flags & NV_MSI_X_ENABLED)
2881                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2882                 else
2883                         disable_irq_lockdep(dev->irq);
2884                 mask = np->irqmask;
2885         } else {
2886                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
2887                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
2888                         mask |= NVREG_IRQ_RX_ALL;
2889                 }
2890                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
2891                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
2892                         mask |= NVREG_IRQ_TX_ALL;
2893                 }
2894                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
2895                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
2896                         mask |= NVREG_IRQ_OTHER;
2897                 }
2898         }
2899         np->nic_poll_irq = 0;
2900
2901         /* FIXME: Do we need synchronize_irq(dev->irq) here? */
2902
2903         writel(mask, base + NvRegIrqMask);
2904         pci_push(base);
2905
2906         if (!using_multi_irqs(dev)) {
2907                 nv_nic_irq(0, dev, NULL);
2908                 if (np->msi_flags & NV_MSI_X_ENABLED)
2909                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2910                 else
2911                         enable_irq_lockdep(dev->irq);
2912         } else {
2913                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
2914                         nv_nic_irq_rx(0, dev, NULL);
2915                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
2916                 }
2917                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
2918                         nv_nic_irq_tx(0, dev, NULL);
2919                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
2920                 }
2921                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
2922                         nv_nic_irq_other(0, dev, NULL);
2923                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
2924                 }
2925         }
2926 }
2927
2928 #ifdef CONFIG_NET_POLL_CONTROLLER
2929 static void nv_poll_controller(struct net_device *dev)
2930 {
2931         nv_do_nic_poll((unsigned long) dev);
2932 }
2933 #endif
2934
2935 static void nv_do_stats_poll(unsigned long data)
2936 {
2937         struct net_device *dev = (struct net_device *) data;
2938         struct fe_priv *np = netdev_priv(dev);
2939         u8 __iomem *base = get_hwbase(dev);
2940
2941         np->estats.tx_bytes += readl(base + NvRegTxCnt);
2942         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
2943         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
2944         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
2945         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
2946         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
2947         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
2948         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
2949         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
2950         np->estats.tx_deferral += readl(base + NvRegTxDef);
2951         np->estats.tx_packets += readl(base + NvRegTxFrame);
2952         np->estats.tx_pause += readl(base + NvRegTxPause);
2953         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
2954         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
2955         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
2956         np->estats.rx_runt += readl(base + NvRegRxRunt);
2957         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
2958         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
2959         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
2960         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
2961         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
2962         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
2963         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
2964         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
2965         np->estats.rx_bytes += readl(base + NvRegRxCnt);
2966         np->estats.rx_pause += readl(base + NvRegRxPause);
2967         np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
2968         np->estats.rx_packets =
2969                 np->estats.rx_unicast +
2970                 np->estats.rx_multicast +
2971                 np->estats.rx_broadcast;
2972         np->estats.rx_errors_total =
2973                 np->estats.rx_crc_errors +
2974                 np->estats.rx_over_errors +
2975                 np->estats.rx_frame_error +
2976                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
2977                 np->estats.rx_late_collision +
2978                 np->estats.rx_runt +
2979                 np->estats.rx_frame_too_long;
2980
2981         if (!np->in_shutdown)
2982                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
2983 }
2984
2985 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2986 {
2987         struct fe_priv *np = netdev_priv(dev);
2988         strcpy(info->driver, "forcedeth");
2989         strcpy(info->version, FORCEDETH_VERSION);
2990         strcpy(info->bus_info, pci_name(np->pci_dev));
2991 }
2992
2993 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
2994 {
2995         struct fe_priv *np = netdev_priv(dev);
2996         wolinfo->supported = WAKE_MAGIC;
2997
2998         spin_lock_irq(&np->lock);
2999         if (np->wolenabled)
3000                 wolinfo->wolopts = WAKE_MAGIC;
3001         spin_unlock_irq(&np->lock);
3002 }
3003
3004 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3005 {
3006         struct fe_priv *np = netdev_priv(dev);
3007         u8 __iomem *base = get_hwbase(dev);
3008         u32 flags = 0;
3009
3010         if (wolinfo->wolopts == 0) {
3011                 np->wolenabled = 0;
3012         } else if (wolinfo->wolopts & WAKE_MAGIC) {
3013                 np->wolenabled = 1;
3014                 flags = NVREG_WAKEUPFLAGS_ENABLE;
3015         }
3016         if (netif_running(dev)) {
3017                 spin_lock_irq(&np->lock);
3018                 writel(flags, base + NvRegWakeUpFlags);
3019                 spin_unlock_irq(&np->lock);
3020         }
3021         return 0;
3022 }
3023
3024 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3025 {
3026         struct fe_priv *np = netdev_priv(dev);
3027         int adv;
3028
3029         spin_lock_irq(&np->lock);
3030         ecmd->port = PORT_MII;
3031         if (!netif_running(dev)) {
3032                 /* We do not track link speed / duplex setting if the
3033                  * interface is disabled. Force a link check */
3034                 if (nv_update_linkspeed(dev)) {
3035                         if (!netif_carrier_ok(dev))
3036                                 netif_carrier_on(dev);
3037                 } else {
3038                         if (netif_carrier_ok(dev))
3039                                 netif_carrier_off(dev);
3040                 }
3041         }
3042
3043         if (netif_carrier_ok(dev)) {
3044                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
3045                 case NVREG_LINKSPEED_10:
3046                         ecmd->speed = SPEED_10;
3047                         break;
3048                 case NVREG_LINKSPEED_100:
3049                         ecmd->speed = SPEED_100;
3050                         break;
3051                 case NVREG_LINKSPEED_1000:
3052                         ecmd->speed = SPEED_1000;
3053                         break;
3054                 }
3055                 ecmd->duplex = DUPLEX_HALF;
3056                 if (np->duplex)
3057                         ecmd->duplex = DUPLEX_FULL;
3058         } else {
3059                 ecmd->speed = -1;
3060                 ecmd->duplex = -1;
3061         }
3062
3063         ecmd->autoneg = np->autoneg;
3064
3065         ecmd->advertising = ADVERTISED_MII;
3066         if (np->autoneg) {
3067                 ecmd->advertising |= ADVERTISED_Autoneg;
3068                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3069                 if (adv & ADVERTISE_10HALF)
3070                         ecmd->advertising |= ADVERTISED_10baseT_Half;
3071                 if (adv & ADVERTISE_10FULL)
3072                         ecmd->advertising |= ADVERTISED_10baseT_Full;
3073                 if (adv & ADVERTISE_100HALF)
3074                         ecmd->advertising |= ADVERTISED_100baseT_Half;
3075                 if (adv & ADVERTISE_100FULL)
3076                         ecmd->advertising |= ADVERTISED_100baseT_Full;
3077                 if (np->gigabit == PHY_GIGABIT) {
3078                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3079                         if (adv & ADVERTISE_1000FULL)
3080                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3081                 }
3082         }
3083         ecmd->supported = (SUPPORTED_Autoneg |
3084                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
3085                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
3086                 SUPPORTED_MII);
3087         if (np->gigabit == PHY_GIGABIT)
3088                 ecmd->supported |= SUPPORTED_1000baseT_Full;
3089
3090         ecmd->phy_address = np->phyaddr;
3091         ecmd->transceiver = XCVR_EXTERNAL;
3092
3093         /* ignore maxtxpkt, maxrxpkt for now */
3094         spin_unlock_irq(&np->lock);
3095         return 0;
3096 }
3097
3098 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3099 {
3100         struct fe_priv *np = netdev_priv(dev);
3101
3102         if (ecmd->port != PORT_MII)
3103                 return -EINVAL;
3104         if (ecmd->transceiver != XCVR_EXTERNAL)
3105                 return -EINVAL;
3106         if (ecmd->phy_address != np->phyaddr) {
3107                 /* TODO: support switching between multiple phys. Should be
3108                  * trivial, but not enabled due to lack of test hardware. */
3109                 return -EINVAL;
3110         }
3111         if (ecmd->autoneg == AUTONEG_ENABLE) {
3112                 u32 mask;
3113
3114                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3115                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3116                 if (np->gigabit == PHY_GIGABIT)
3117                         mask |= ADVERTISED_1000baseT_Full;
3118
3119                 if ((ecmd->advertising & mask) == 0)
3120                         return -EINVAL;
3121
3122         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
3123                 /* Note: autonegotiation disable, speed 1000 intentionally
3124                  * forbidden - noone should need that. */
3125
3126                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
3127                         return -EINVAL;
3128                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
3129                         return -EINVAL;
3130         } else {
3131                 return -EINVAL;
3132         }
3133
3134         netif_carrier_off(dev);
3135         if (netif_running(dev)) {
3136                 nv_disable_irq(dev);
3137                 netif_tx_lock_bh(dev);
3138                 spin_lock(&np->lock);
3139                 /* stop engines */
3140                 nv_stop_rx(dev);
3141                 nv_stop_tx(dev);
3142                 spin_unlock(&np->lock);
3143                 netif_tx_unlock_bh(dev);
3144         }
3145
3146         if (ecmd->autoneg == AUTONEG_ENABLE) {
3147                 int adv, bmcr;
3148
3149                 np->autoneg = 1;
3150
3151                 /* advertise only what has been requested */
3152                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3153                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3154                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
3155                         adv |= ADVERTISE_10HALF;
3156                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
3157                         adv |= ADVERTISE_10FULL;
3158                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
3159                         adv |= ADVERTISE_100HALF;
3160                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
3161                         adv |= ADVERTISE_100FULL;
3162                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
3163                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3164                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3165                         adv |=  ADVERTISE_PAUSE_ASYM;
3166                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3167
3168                 if (np->gigabit == PHY_GIGABIT) {
3169                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3170                         adv &= ~ADVERTISE_1000FULL;
3171                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
3172                                 adv |= ADVERTISE_1000FULL;
3173                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3174                 }
3175
3176                 if (netif_running(dev))
3177                         printk(KERN_INFO "%s: link down.\n", dev->name);
3178                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3179                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3180                         bmcr |= BMCR_ANENABLE;
3181                         /* reset the phy in order for settings to stick,
3182                          * and cause autoneg to start */
3183                         if (phy_reset(dev, bmcr)) {
3184                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3185                                 return -EINVAL;
3186                         }
3187                 } else {
3188                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3189                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3190                 }
3191         } else {
3192                 int adv, bmcr;
3193
3194                 np->autoneg = 0;
3195
3196                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3197                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3198                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
3199                         adv |= ADVERTISE_10HALF;
3200                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
3201                         adv |= ADVERTISE_10FULL;
3202                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
3203                         adv |= ADVERTISE_100HALF;
3204                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
3205                         adv |= ADVERTISE_100FULL;
3206                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3207                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
3208                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3209                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3210                 }
3211                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
3212                         adv |=  ADVERTISE_PAUSE_ASYM;
3213                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3214                 }
3215                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3216                 np->fixed_mode = adv;
3217
3218                 if (np->gigabit == PHY_GIGABIT) {
3219                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3220                         adv &= ~ADVERTISE_1000FULL;
3221                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3222                 }
3223
3224                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3225                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
3226                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
3227                         bmcr |= BMCR_FULLDPLX;
3228                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
3229                         bmcr |= BMCR_SPEED100;
3230                 if (np->phy_oui == PHY_OUI_MARVELL) {
3231                         /* reset the phy in order for forced mode settings to stick */
3232                         if (phy_reset(dev, bmcr)) {
3233                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3234                                 return -EINVAL;
3235                         }
3236                 } else {
3237                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3238                         if (netif_running(dev)) {
3239                                 /* Wait a bit and then reconfigure the nic. */
3240                                 udelay(10);
3241                                 nv_linkchange(dev);
3242                         }
3243                 }
3244         }
3245
3246         if (netif_running(dev)) {
3247                 nv_start_rx(dev);
3248                 nv_start_tx(dev);
3249                 nv_enable_irq(dev);
3250         }
3251
3252         return 0;
3253 }
3254
3255 #define FORCEDETH_REGS_VER      1
3256
3257 static int nv_get_regs_len(struct net_device *dev)
3258 {
3259         struct fe_priv *np = netdev_priv(dev);
3260         return np->register_size;
3261 }
3262
3263 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
3264 {
3265         struct fe_priv *np = netdev_priv(dev);
3266         u8 __iomem *base = get_hwbase(dev);
3267         u32 *rbuf = buf;
3268         int i;
3269
3270         regs->version = FORCEDETH_REGS_VER;
3271         spin_lock_irq(&np->lock);
3272         for (i = 0;i <= np->register_size/sizeof(u32); i++)
3273                 rbuf[i] = readl(base + i*sizeof(u32));
3274         spin_unlock_irq(&np->lock);
3275 }
3276
3277 static int nv_nway_reset(struct net_device *dev)
3278 {
3279         struct fe_priv *np = netdev_priv(dev);
3280         int ret;
3281
3282         if (np->autoneg) {
3283                 int bmcr;
3284
3285                 netif_carrier_off(dev);
3286                 if (netif_running(dev)) {
3287                         nv_disable_irq(dev);
3288                         netif_tx_lock_bh(dev);
3289                         spin_lock(&np->lock);
3290                         /* stop engines */
3291                         nv_stop_rx(dev);
3292                         nv_stop_tx(dev);
3293                         spin_unlock(&np->lock);
3294                         netif_tx_unlock_bh(dev);
3295                         printk(KERN_INFO "%s: link down.\n", dev->name);
3296                 }
3297
3298                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3299                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3300                         bmcr |= BMCR_ANENABLE;
3301                         /* reset the phy in order for settings to stick*/
3302                         if (phy_reset(dev, bmcr)) {
3303                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3304                                 return -EINVAL;
3305                         }
3306                 } else {
3307                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3308                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3309                 }
3310
3311                 if (netif_running(dev)) {
3312                         nv_start_rx(dev);
3313                         nv_start_tx(dev);
3314                         nv_enable_irq(dev);
3315                 }
3316                 ret = 0;
3317         } else {
3318                 ret = -EINVAL;
3319         }
3320
3321         return ret;
3322 }
3323
3324 static int nv_set_tso(struct net_device *dev, u32 value)
3325 {
3326         struct fe_priv *np = netdev_priv(dev);
3327
3328         if ((np->driver_data & DEV_HAS_CHECKSUM))
3329                 return ethtool_op_set_tso(dev, value);
3330         else
3331                 return -EOPNOTSUPP;
3332 }
3333
3334 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3335 {
3336         struct fe_priv *np = netdev_priv(dev);
3337
3338         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3339         ring->rx_mini_max_pending = 0;
3340         ring->rx_jumbo_max_pending = 0;
3341         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3342
3343         ring->rx_pending = np->rx_ring_size;
3344         ring->rx_mini_pending = 0;
3345         ring->rx_jumbo_pending = 0;
3346         ring->tx_pending = np->tx_ring_size;
3347 }
3348
3349 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3350 {
3351         struct fe_priv *np = netdev_priv(dev);
3352         u8 __iomem *base = get_hwbase(dev);
3353         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff, *rx_dma, *tx_dma, *tx_dma_len;
3354         dma_addr_t ring_addr;
3355
3356         if (ring->rx_pending < RX_RING_MIN ||
3357             ring->tx_pending < TX_RING_MIN ||
3358             ring->rx_mini_pending != 0 ||
3359             ring->rx_jumbo_pending != 0 ||
3360             (np->desc_ver == DESC_VER_1 &&
3361              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
3362               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
3363             (np->desc_ver != DESC_VER_1 &&
3364              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
3365               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
3366                 return -EINVAL;
3367         }
3368
3369         /* allocate new rings */
3370         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3371                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3372                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3373                                             &ring_addr);
3374         } else {
3375                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3376                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3377                                             &ring_addr);
3378         }
3379         rx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->rx_pending, GFP_KERNEL);
3380         rx_dma = kmalloc(sizeof(dma_addr_t) * ring->rx_pending, GFP_KERNEL);
3381         tx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->tx_pending, GFP_KERNEL);
3382         tx_dma = kmalloc(sizeof(dma_addr_t) * ring->tx_pending, GFP_KERNEL);
3383         tx_dma_len = kmalloc(sizeof(unsigned int) * ring->tx_pending, GFP_KERNEL);
3384         if (!rxtx_ring || !rx_skbuff || !rx_dma || !tx_skbuff || !tx_dma || !tx_dma_len) {
3385                 /* fall back to old rings */
3386                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3387                         if (rxtx_ring)
3388                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3389                                                     rxtx_ring, ring_addr);
3390                 } else {
3391                         if (rxtx_ring)
3392                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3393                                                     rxtx_ring, ring_addr);
3394                 }
3395                 if (rx_skbuff)
3396                         kfree(rx_skbuff);
3397                 if (rx_dma)
3398                         kfree(rx_dma);
3399                 if (tx_skbuff)
3400                         kfree(tx_skbuff);
3401                 if (tx_dma)
3402                         kfree(tx_dma);
3403                 if (tx_dma_len)
3404                         kfree(tx_dma_len);
3405                 goto exit;
3406         }
3407
3408         if (netif_running(dev)) {
3409                 nv_disable_irq(dev);
3410                 netif_tx_lock_bh(dev);
3411                 spin_lock(&np->lock);
3412                 /* stop engines */
3413                 nv_stop_rx(dev);
3414                 nv_stop_tx(dev);
3415                 nv_txrx_reset(dev);
3416                 /* drain queues */
3417                 nv_drain_rx(dev);
3418                 nv_drain_tx(dev);
3419                 /* delete queues */
3420                 free_rings(dev);
3421         }
3422
3423         /* set new values */
3424         np->rx_ring_size = ring->rx_pending;
3425         np->tx_ring_size = ring->tx_pending;
3426         np->tx_limit_stop = ring->tx_pending - TX_LIMIT_DIFFERENCE;
3427         np->tx_limit_start = ring->tx_pending - TX_LIMIT_DIFFERENCE - 1;
3428         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3429                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
3430                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
3431         } else {
3432                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
3433                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
3434         }
3435         np->rx_skbuff = (struct sk_buff**)rx_skbuff;
3436         np->rx_dma = (dma_addr_t*)rx_dma;
3437         np->tx_skbuff = (struct sk_buff**)tx_skbuff;
3438         np->tx_dma = (dma_addr_t*)tx_dma;
3439         np->tx_dma_len = (unsigned int*)tx_dma_len;
3440         np->ring_addr = ring_addr;
3441
3442         memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
3443         memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
3444         memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
3445         memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
3446         memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
3447
3448         if (netif_running(dev)) {
3449                 /* reinit driver view of the queues */
3450                 set_bufsize(dev);
3451                 if (nv_init_ring(dev)) {
3452                         if (!np->in_shutdown)
3453                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3454                 }
3455
3456                 /* reinit nic view of the queues */
3457                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3458                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3459                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3460                         base + NvRegRingSizes);
3461                 pci_push(base);
3462                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3463                 pci_push(base);
3464
3465                 /* restart engines */
3466                 nv_start_rx(dev);
3467                 nv_start_tx(dev);
3468                 spin_unlock(&np->lock);
3469                 netif_tx_unlock_bh(dev);
3470                 nv_enable_irq(dev);
3471         }
3472         return 0;
3473 exit:
3474         return -ENOMEM;
3475 }
3476
3477 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3478 {
3479         struct fe_priv *np = netdev_priv(dev);
3480
3481         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
3482         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
3483         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
3484 }
3485
3486 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3487 {
3488         struct fe_priv *np = netdev_priv(dev);
3489         int adv, bmcr;
3490
3491         if ((!np->autoneg && np->duplex == 0) ||
3492             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
3493                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
3494                        dev->name);
3495                 return -EINVAL;
3496         }
3497         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
3498                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
3499                 return -EINVAL;
3500         }
3501
3502         netif_carrier_off(dev);
3503         if (netif_running(dev)) {
3504                 nv_disable_irq(dev);
3505                 netif_tx_lock_bh(dev);
3506                 spin_lock(&np->lock);
3507                 /* stop engines */
3508                 nv_stop_rx(dev);
3509                 nv_stop_tx(dev);
3510                 spin_unlock(&np->lock);
3511                 netif_tx_unlock_bh(dev);
3512         }
3513
3514         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
3515         if (pause->rx_pause)
3516                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
3517         if (pause->tx_pause)
3518                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
3519
3520         if (np->autoneg && pause->autoneg) {
3521                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
3522
3523                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3524                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3525                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
3526                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3527                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3528                         adv |=  ADVERTISE_PAUSE_ASYM;
3529                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3530
3531                 if (netif_running(dev))
3532                         printk(KERN_INFO "%s: link down.\n", dev->name);
3533                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3534                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3535                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3536         } else {
3537                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3538                 if (pause->rx_pause)
3539                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3540                 if (pause->tx_pause)
3541                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3542
3543                 if (!netif_running(dev))
3544                         nv_update_linkspeed(dev);
3545                 else
3546                         nv_update_pause(dev, np->pause_flags);
3547         }
3548
3549         if (netif_running(dev)) {
3550                 nv_start_rx(dev);
3551                 nv_start_tx(dev);
3552                 nv_enable_irq(dev);
3553         }
3554         return 0;
3555 }
3556
3557 static u32 nv_get_rx_csum(struct net_device *dev)
3558 {
3559         struct fe_priv *np = netdev_priv(dev);
3560         return (np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) != 0;
3561 }
3562
3563 static int nv_set_rx_csum(struct net_device *dev, u32 data)
3564 {
3565         struct fe_priv *np = netdev_priv(dev);
3566         u8 __iomem *base = get_hwbase(dev);
3567         int retcode = 0;
3568
3569         if (np->driver_data & DEV_HAS_CHECKSUM) {
3570
3571                 if (((np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) && data) ||
3572                     (!(np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) && !data)) {
3573                         /* already set or unset */
3574                         return 0;
3575                 }
3576
3577                 if (data) {
3578                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
3579                 } else if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE)) {
3580                         np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
3581                 } else {
3582                         printk(KERN_INFO "Can not disable rx checksum if vlan is enabled\n");
3583                         return -EINVAL;
3584                 }
3585
3586                 if (netif_running(dev)) {
3587                         spin_lock_irq(&np->lock);
3588                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
3589                         spin_unlock_irq(&np->lock);
3590                 }
3591         } else {
3592                 return -EINVAL;
3593         }
3594
3595         return retcode;
3596 }
3597
3598 static int nv_set_tx_csum(struct net_device *dev, u32 data)
3599 {
3600         struct fe_priv *np = netdev_priv(dev);
3601
3602         if (np->driver_data & DEV_HAS_CHECKSUM)
3603                 return ethtool_op_set_tx_hw_csum(dev, data);
3604         else
3605                 return -EOPNOTSUPP;
3606 }
3607
3608 static int nv_set_sg(struct net_device *dev, u32 data)
3609 {
3610         struct fe_priv *np = netdev_priv(dev);
3611
3612         if (np->driver_data & DEV_HAS_CHECKSUM)
3613                 return ethtool_op_set_sg(dev, data);
3614         else
3615                 return -EOPNOTSUPP;
3616 }
3617
3618 static int nv_get_stats_count(struct net_device *dev)
3619 {
3620         struct fe_priv *np = netdev_priv(dev);
3621
3622         if (np->driver_data & DEV_HAS_STATISTICS)
3623                 return sizeof(struct nv_ethtool_stats)/sizeof(u64);
3624         else
3625                 return 0;
3626 }
3627
3628 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
3629 {
3630         struct fe_priv *np = netdev_priv(dev);
3631
3632         /* update stats */
3633         nv_do_stats_poll((unsigned long)dev);
3634
3635         memcpy(buffer, &np->estats, nv_get_stats_count(dev)*sizeof(u64));
3636 }
3637
3638 static int nv_self_test_count(struct net_device *dev)
3639 {
3640         struct fe_priv *np = netdev_priv(dev);
3641
3642         if (np->driver_data & DEV_HAS_TEST_EXTENDED)
3643                 return NV_TEST_COUNT_EXTENDED;
3644         else
3645                 return NV_TEST_COUNT_BASE;
3646 }
3647
3648 static int nv_link_test(struct net_device *dev)
3649 {
3650         struct fe_priv *np = netdev_priv(dev);
3651         int mii_status;
3652
3653         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3654         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3655
3656         /* check phy link status */
3657         if (!(mii_status & BMSR_LSTATUS))
3658                 return 0;
3659         else
3660                 return 1;
3661 }
3662
3663 static int nv_register_test(struct net_device *dev)
3664 {
3665         u8 __iomem *base = get_hwbase(dev);
3666         int i = 0;
3667         u32 orig_read, new_read;
3668
3669         do {
3670                 orig_read = readl(base + nv_registers_test[i].reg);
3671
3672                 /* xor with mask to toggle bits */
3673                 orig_read ^= nv_registers_test[i].mask;
3674
3675                 writel(orig_read, base + nv_registers_test[i].reg);
3676
3677                 new_read = readl(base + nv_registers_test[i].reg);
3678
3679                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
3680                         return 0;
3681
3682                 /* restore original value */
3683                 orig_read ^= nv_registers_test[i].mask;
3684                 writel(orig_read, base + nv_registers_test[i].reg);
3685
3686         } while (nv_registers_test[++i].reg != 0);
3687
3688         return 1;
3689 }
3690
3691 static int nv_interrupt_test(struct net_device *dev)
3692 {
3693         struct fe_priv *np = netdev_priv(dev);
3694         u8 __iomem *base = get_hwbase(dev);
3695         int ret = 1;
3696         int testcnt;
3697         u32 save_msi_flags, save_poll_interval = 0;
3698
3699         if (netif_running(dev)) {
3700                 /* free current irq */
3701                 nv_free_irq(dev);
3702                 save_poll_interval = readl(base+NvRegPollingInterval);
3703         }
3704
3705         /* flag to test interrupt handler */
3706         np->intr_test = 0;
3707
3708         /* setup test irq */
3709         save_msi_flags = np->msi_flags;
3710         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
3711         np->msi_flags |= 0x001; /* setup 1 vector */
3712         if (nv_request_irq(dev, 1))
3713                 return 0;
3714
3715         /* setup timer interrupt */
3716         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
3717         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3718
3719         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
3720
3721         /* wait for at least one interrupt */
3722         msleep(100);
3723
3724         spin_lock_irq(&np->lock);
3725
3726         /* flag should be set within ISR */
3727         testcnt = np->intr_test;
3728         if (!testcnt)
3729                 ret = 2;
3730
3731         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
3732         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3733                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3734         else
3735                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3736
3737         spin_unlock_irq(&np->lock);
3738
3739         nv_free_irq(dev);
3740
3741         np->msi_flags = save_msi_flags;
3742
3743         if (netif_running(dev)) {
3744                 writel(save_poll_interval, base + NvRegPollingInterval);
3745                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3746                 /* restore original irq */
3747                 if (nv_request_irq(dev, 0))
3748                         return 0;
3749         }
3750
3751         return ret;
3752 }
3753
3754 static int nv_loopback_test(struct net_device *dev)
3755 {
3756         struct fe_priv *np = netdev_priv(dev);
3757         u8 __iomem *base = get_hwbase(dev);
3758         struct sk_buff *tx_skb, *rx_skb;
3759         dma_addr_t test_dma_addr;
3760         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
3761         u32 flags;
3762         int len, i, pkt_len;
3763         u8 *pkt_data;
3764         u32 filter_flags = 0;
3765         u32 misc1_flags = 0;
3766         int ret = 1;
3767
3768         if (netif_running(dev)) {
3769                 nv_disable_irq(dev);
3770                 filter_flags = readl(base + NvRegPacketFilterFlags);
3771                 misc1_flags = readl(base + NvRegMisc1);
3772         } else {
3773                 nv_txrx_reset(dev);
3774         }
3775
3776         /* reinit driver view of the rx queue */
3777         set_bufsize(dev);
3778         nv_init_ring(dev);
3779
3780         /* setup hardware for loopback */
3781         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
3782         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
3783
3784         /* reinit nic view of the rx queue */
3785         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3786         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3787         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3788                 base + NvRegRingSizes);
3789         pci_push(base);
3790
3791         /* restart rx engine */
3792         nv_start_rx(dev);
3793         nv_start_tx(dev);
3794
3795         /* setup packet for tx */
3796         pkt_len = ETH_DATA_LEN;
3797         tx_skb = dev_alloc_skb(pkt_len);
3798         pkt_data = skb_put(tx_skb, pkt_len);
3799         for (i = 0; i < pkt_len; i++)
3800                 pkt_data[i] = (u8)(i & 0xff);
3801         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
3802                                        tx_skb->end-tx_skb->data, PCI_DMA_FROMDEVICE);
3803
3804         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3805                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
3806                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
3807         } else {
3808                 np->tx_ring.ex[0].bufhigh = cpu_to_le64(test_dma_addr) >> 32;
3809                 np->tx_ring.ex[0].buflow = cpu_to_le64(test_dma_addr) & 0x0FFFFFFFF;
3810                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
3811         }
3812         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3813         pci_push(get_hwbase(dev));
3814
3815         msleep(500);
3816
3817         /* check for rx of the packet */
3818         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3819                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
3820                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
3821
3822         } else {
3823                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
3824                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
3825         }
3826
3827         if (flags & NV_RX_AVAIL) {
3828                 ret = 0;
3829         } else if (np->desc_ver == DESC_VER_1) {
3830                 if (flags & NV_RX_ERROR)
3831                         ret = 0;
3832         } else {
3833                 if (flags & NV_RX2_ERROR) {
3834                         ret = 0;
3835                 }
3836         }
3837
3838         if (ret) {
3839                 if (len != pkt_len) {
3840                         ret = 0;
3841                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
3842                                 dev->name, len, pkt_len);
3843                 } else {
3844                         rx_skb = np->rx_skbuff[0];
3845                         for (i = 0; i < pkt_len; i++) {
3846                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
3847                                         ret = 0;
3848                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
3849                                                 dev->name, i);
3850                                         break;
3851                                 }
3852                         }
3853                 }
3854         } else {
3855                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
3856         }
3857
3858         pci_unmap_page(np->pci_dev, test_dma_addr,
3859                        tx_skb->end-tx_skb->data,
3860                        PCI_DMA_TODEVICE);
3861         dev_kfree_skb_any(tx_skb);
3862
3863         /* stop engines */
3864         nv_stop_rx(dev);
3865         nv_stop_tx(dev);
3866         nv_txrx_reset(dev);
3867         /* drain rx queue */
3868         nv_drain_rx(dev);
3869         nv_drain_tx(dev);
3870
3871         if (netif_running(dev)) {
3872                 writel(misc1_flags, base + NvRegMisc1);
3873                 writel(filter_flags, base + NvRegPacketFilterFlags);
3874                 nv_enable_irq(dev);
3875         }
3876
3877         return ret;
3878 }
3879
3880 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
3881 {
3882         struct fe_priv *np = netdev_priv(dev);
3883         u8 __iomem *base = get_hwbase(dev);
3884         int result;
3885         memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64));
3886
3887         if (!nv_link_test(dev)) {
3888                 test->flags |= ETH_TEST_FL_FAILED;
3889                 buffer[0] = 1;
3890         }
3891
3892         if (test->flags & ETH_TEST_FL_OFFLINE) {
3893                 if (netif_running(dev)) {
3894                         netif_stop_queue(dev);
3895                         netif_poll_disable(dev);
3896                         netif_tx_lock_bh(dev);
3897                         spin_lock_irq(&np->lock);
3898                         nv_disable_hw_interrupts(dev, np->irqmask);
3899                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3900                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3901                         } else {
3902                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3903                         }
3904                         /* stop engines */
3905                         nv_stop_rx(dev);
3906                         nv_stop_tx(dev);
3907                         nv_txrx_reset(dev);
3908                         /* drain rx queue */
3909                         nv_drain_rx(dev);
3910                         nv_drain_tx(dev);
3911                         spin_unlock_irq(&np->lock);
3912                         netif_tx_unlock_bh(dev);
3913                 }
3914
3915                 if (!nv_register_test(dev)) {
3916                         test->flags |= ETH_TEST_FL_FAILED;
3917                         buffer[1] = 1;
3918                 }
3919
3920                 result = nv_interrupt_test(dev);
3921                 if (result != 1) {
3922                         test->flags |= ETH_TEST_FL_FAILED;
3923                         buffer[2] = 1;
3924                 }
3925                 if (result == 0) {
3926                         /* bail out */
3927                         return;
3928                 }
3929
3930                 if (!nv_loopback_test(dev)) {
3931                         test->flags |= ETH_TEST_FL_FAILED;
3932                         buffer[3] = 1;
3933                 }
3934
3935                 if (netif_running(dev)) {
3936                         /* reinit driver view of the rx queue */
3937                         set_bufsize(dev);
3938                         if (nv_init_ring(dev)) {
3939                                 if (!np->in_shutdown)
3940                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3941                         }
3942                         /* reinit nic view of the rx queue */
3943                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3944                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3945                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3946                                 base + NvRegRingSizes);
3947                         pci_push(base);
3948                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3949                         pci_push(base);
3950                         /* restart rx engine */
3951                         nv_start_rx(dev);
3952                         nv_start_tx(dev);
3953                         netif_start_queue(dev);
3954                         netif_poll_enable(dev);
3955                         nv_enable_hw_interrupts(dev, np->irqmask);
3956                 }
3957         }
3958 }
3959
3960 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
3961 {
3962         switch (stringset) {
3963         case ETH_SS_STATS:
3964                 memcpy(buffer, &nv_estats_str, nv_get_stats_count(dev)*sizeof(struct nv_ethtool_str));
3965                 break;
3966         case ETH_SS_TEST:
3967                 memcpy(buffer, &nv_etests_str, nv_self_test_count(dev)*sizeof(struct nv_ethtool_str));
3968                 break;
3969         }
3970 }
3971
3972 static struct ethtool_ops ops = {
3973         .get_drvinfo = nv_get_drvinfo,
3974         .get_link = ethtool_op_get_link,
3975         .get_wol = nv_get_wol,
3976         .set_wol = nv_set_wol,
3977         .get_settings = nv_get_settings,
3978         .set_settings = nv_set_settings,
3979         .get_regs_len = nv_get_regs_len,
3980         .get_regs = nv_get_regs,
3981         .nway_reset = nv_nway_reset,
3982         .get_perm_addr = ethtool_op_get_perm_addr,
3983         .get_tso = ethtool_op_get_tso,
3984         .set_tso = nv_set_tso,
3985         .get_ringparam = nv_get_ringparam,
3986         .set_ringparam = nv_set_ringparam,
3987         .get_pauseparam = nv_get_pauseparam,
3988         .set_pauseparam = nv_set_pauseparam,
3989         .get_rx_csum = nv_get_rx_csum,
3990         .set_rx_csum = nv_set_rx_csum,
3991         .get_tx_csum = ethtool_op_get_tx_csum,
3992         .set_tx_csum = nv_set_tx_csum,
3993         .get_sg = ethtool_op_get_sg,
3994         .set_sg = nv_set_sg,
3995         .get_strings = nv_get_strings,
3996         .get_stats_count = nv_get_stats_count,
3997         .get_ethtool_stats = nv_get_ethtool_stats,
3998         .self_test_count = nv_self_test_count,
3999         .self_test = nv_self_test,
4000 };
4001
4002 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
4003 {
4004         struct fe_priv *np = get_nvpriv(dev);
4005
4006         spin_lock_irq(&np->lock);
4007
4008         /* save vlan group */
4009         np->vlangrp = grp;
4010
4011         if (grp) {
4012                 /* enable vlan on MAC */
4013                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
4014         } else {
4015                 /* disable vlan on MAC */
4016                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4017                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4018         }
4019
4020         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4021
4022         spin_unlock_irq(&np->lock);
4023 };
4024
4025 static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
4026 {
4027         /* nothing to do */
4028 };
4029
4030 static int nv_open(struct net_device *dev)
4031 {
4032         struct fe_priv *np = netdev_priv(dev);
4033         u8 __iomem *base = get_hwbase(dev);
4034         int ret = 1;
4035         int oom, i;
4036
4037         dprintk(KERN_DEBUG "nv_open: begin\n");
4038
4039         /* erase previous misconfiguration */
4040         if (np->driver_data & DEV_HAS_POWER_CNTRL)
4041                 nv_mac_reset(dev);
4042         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4043         writel(0, base + NvRegMulticastAddrB);
4044         writel(0, base + NvRegMulticastMaskA);
4045         writel(0, base + NvRegMulticastMaskB);
4046         writel(0, base + NvRegPacketFilterFlags);
4047
4048         writel(0, base + NvRegTransmitterControl);
4049         writel(0, base + NvRegReceiverControl);
4050
4051         writel(0, base + NvRegAdapterControl);
4052
4053         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
4054                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
4055
4056         /* initialize descriptor rings */
4057         set_bufsize(dev);
4058         oom = nv_init_ring(dev);
4059
4060         writel(0, base + NvRegLinkSpeed);
4061         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4062         nv_txrx_reset(dev);
4063         writel(0, base + NvRegUnknownSetupReg6);
4064
4065         np->in_shutdown = 0;
4066
4067         /* give hw rings */
4068         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4069         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4070                 base + NvRegRingSizes);
4071
4072         writel(np->linkspeed, base + NvRegLinkSpeed);
4073         if (np->desc_ver == DESC_VER_1)
4074                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
4075         else
4076                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
4077         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4078         writel(np->vlanctl_bits, base + NvRegVlanControl);
4079         pci_push(base);
4080         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
4081         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
4082                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
4083                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
4084
4085         writel(0, base + NvRegUnknownSetupReg4);
4086         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4087         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4088
4089         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
4090         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
4091         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
4092         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4093
4094         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
4095         get_random_bytes(&i, sizeof(i));
4096         writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
4097         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
4098         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
4099         if (poll_interval == -1) {
4100                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
4101                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
4102                 else
4103                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4104         }
4105         else
4106                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
4107         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4108         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
4109                         base + NvRegAdapterControl);
4110         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
4111         writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
4112         if (np->wolenabled)
4113                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
4114
4115         i = readl(base + NvRegPowerState);
4116         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
4117                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
4118
4119         pci_push(base);
4120         udelay(10);
4121         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
4122
4123         nv_disable_hw_interrupts(dev, np->irqmask);
4124         pci_push(base);
4125         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4126         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4127         pci_push(base);
4128
4129         if (nv_request_irq(dev, 0)) {
4130                 goto out_drain;
4131         }
4132
4133         /* ask for interrupts */
4134         nv_enable_hw_interrupts(dev, np->irqmask);
4135
4136         spin_lock_irq(&np->lock);
4137         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4138         writel(0, base + NvRegMulticastAddrB);
4139         writel(0, base + NvRegMulticastMaskA);
4140         writel(0, base + NvRegMulticastMaskB);
4141         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
4142         /* One manual link speed update: Interrupts are enabled, future link
4143          * speed changes cause interrupts and are handled by nv_link_irq().
4144          */
4145         {
4146                 u32 miistat;
4147                 miistat = readl(base + NvRegMIIStatus);
4148                 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
4149                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
4150         }
4151         /* set linkspeed to invalid value, thus force nv_update_linkspeed
4152          * to init hw */
4153         np->linkspeed = 0;
4154         ret = nv_update_linkspeed(dev);
4155         nv_start_rx(dev);
4156         nv_start_tx(dev);
4157         netif_start_queue(dev);
4158         netif_poll_enable(dev);
4159
4160         if (ret) {
4161                 netif_carrier_on(dev);
4162         } else {
4163                 printk("%s: no link during initialization.\n", dev->name);
4164                 netif_carrier_off(dev);
4165         }
4166         if (oom)
4167                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4168
4169         /* start statistics timer */
4170         if (np->driver_data & DEV_HAS_STATISTICS)
4171                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
4172
4173         spin_unlock_irq(&np->lock);
4174
4175         return 0;
4176 out_drain:
4177         drain_ring(dev);
4178         return ret;
4179 }
4180
4181 static int nv_close(struct net_device *dev)
4182 {
4183         struct fe_priv *np = netdev_priv(dev);
4184         u8 __iomem *base;
4185
4186         spin_lock_irq(&np->lock);
4187         np->in_shutdown = 1;
4188         spin_unlock_irq(&np->lock);
4189         netif_poll_disable(dev);
4190         synchronize_irq(dev->irq);
4191
4192         del_timer_sync(&np->oom_kick);
4193         del_timer_sync(&np->nic_poll);
4194         del_timer_sync(&np->stats_poll);
4195
4196         netif_stop_queue(dev);
4197         spin_lock_irq(&np->lock);
4198         nv_stop_tx(dev);
4199         nv_stop_rx(dev);
4200         nv_txrx_reset(dev);
4201
4202         /* disable interrupts on the nic or we will lock up */
4203         base = get_hwbase(dev);
4204         nv_disable_hw_interrupts(dev, np->irqmask);
4205         pci_push(base);
4206         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
4207
4208         spin_unlock_irq(&np->lock);
4209
4210         nv_free_irq(dev);
4211
4212         drain_ring(dev);
4213
4214         if (np->wolenabled)
4215                 nv_start_rx(dev);
4216
4217         /* FIXME: power down nic */
4218
4219         return 0;
4220 }
4221
4222 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
4223 {
4224         struct net_device *dev;
4225         struct fe_priv *np;
4226         unsigned long addr;
4227         u8 __iomem *base;
4228         int err, i;
4229         u32 powerstate, txreg;
4230
4231         dev = alloc_etherdev(sizeof(struct fe_priv));
4232         err = -ENOMEM;
4233         if (!dev)
4234                 goto out;
4235
4236         np = netdev_priv(dev);
4237         np->pci_dev = pci_dev;
4238         spin_lock_init(&np->lock);
4239         SET_MODULE_OWNER(dev);
4240         SET_NETDEV_DEV(dev, &pci_dev->dev);
4241
4242         init_timer(&np->oom_kick);
4243         np->oom_kick.data = (unsigned long) dev;
4244         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
4245         init_timer(&np->nic_poll);
4246         np->nic_poll.data = (unsigned long) dev;
4247         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
4248         init_timer(&np->stats_poll);
4249         np->stats_poll.data = (unsigned long) dev;
4250         np->stats_poll.function = &nv_do_stats_poll;    /* timer handler */
4251
4252         err = pci_enable_device(pci_dev);
4253         if (err) {
4254                 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
4255                                 err, pci_name(pci_dev));
4256                 goto out_free;
4257         }
4258
4259         pci_set_master(pci_dev);
4260
4261         err = pci_request_regions(pci_dev, DRV_NAME);
4262         if (err < 0)
4263                 goto out_disable;
4264
4265         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS))
4266                 np->register_size = NV_PCI_REGSZ_VER2;
4267         else
4268                 np->register_size = NV_PCI_REGSZ_VER1;
4269
4270         err = -EINVAL;
4271         addr = 0;
4272         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
4273                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
4274                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
4275                                 pci_resource_len(pci_dev, i),
4276                                 pci_resource_flags(pci_dev, i));
4277                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
4278                                 pci_resource_len(pci_dev, i) >= np->register_size) {
4279                         addr = pci_resource_start(pci_dev, i);
4280                         break;
4281                 }
4282         }
4283         if (i == DEVICE_COUNT_RESOURCE) {
4284                 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
4285                                         pci_name(pci_dev));
4286                 goto out_relreg;
4287         }
4288
4289         /* copy of driver data */
4290         np->driver_data = id->driver_data;
4291
4292         /* handle different descriptor versions */
4293         if (id->driver_data & DEV_HAS_HIGH_DMA) {
4294                 /* packet format 3: supports 40-bit addressing */
4295                 np->desc_ver = DESC_VER_3;
4296                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
4297                 if (dma_64bit) {
4298                         if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4299                                 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
4300                                        pci_name(pci_dev));
4301                         } else {
4302                                 dev->features |= NETIF_F_HIGHDMA;
4303                                 printk(KERN_INFO "forcedeth: using HIGHDMA\n");
4304                         }
4305                         if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4306                                 printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n",
4307                                        pci_name(pci_dev));
4308                         }
4309                 }
4310         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
4311                 /* packet format 2: supports jumbo frames */
4312                 np->desc_ver = DESC_VER_2;
4313                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
4314         } else {
4315                 /* original packet format */
4316                 np->desc_ver = DESC_VER_1;
4317                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
4318         }
4319
4320         np->pkt_limit = NV_PKTLIMIT_1;
4321         if (id->driver_data & DEV_HAS_LARGEDESC)
4322                 np->pkt_limit = NV_PKTLIMIT_2;
4323
4324         if (id->driver_data & DEV_HAS_CHECKSUM) {
4325                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4326                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
4327 #ifdef NETIF_F_TSO
4328                 dev->features |= NETIF_F_TSO;
4329 #endif
4330         }
4331
4332         np->vlanctl_bits = 0;
4333         if (id->driver_data & DEV_HAS_VLAN) {
4334                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
4335                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
4336                 dev->vlan_rx_register = nv_vlan_rx_register;
4337                 dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid;
4338         }
4339
4340         np->msi_flags = 0;
4341         if ((id->driver_data & DEV_HAS_MSI) && msi) {
4342                 np->msi_flags |= NV_MSI_CAPABLE;
4343         }
4344         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
4345                 np->msi_flags |= NV_MSI_X_CAPABLE;
4346         }
4347
4348         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
4349         if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {
4350                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
4351         }
4352
4353
4354         err = -ENOMEM;
4355         np->base = ioremap(addr, np->register_size);
4356         if (!np->base)
4357                 goto out_relreg;
4358         dev->base_addr = (unsigned long)np->base;
4359
4360         dev->irq = pci_dev->irq;
4361
4362         np->rx_ring_size = RX_RING_DEFAULT;
4363         np->tx_ring_size = TX_RING_DEFAULT;
4364         np->tx_limit_stop = np->tx_ring_size - TX_LIMIT_DIFFERENCE;
4365         np->tx_limit_start = np->tx_ring_size - TX_LIMIT_DIFFERENCE - 1;
4366
4367         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4368                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
4369                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
4370                                         &np->ring_addr);
4371                 if (!np->rx_ring.orig)
4372                         goto out_unmap;
4373                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4374         } else {
4375                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
4376                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
4377                                         &np->ring_addr);
4378                 if (!np->rx_ring.ex)
4379                         goto out_unmap;
4380                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4381         }
4382         np->rx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->rx_ring_size, GFP_KERNEL);
4383         np->rx_dma = kmalloc(sizeof(dma_addr_t) * np->rx_ring_size, GFP_KERNEL);
4384         np->tx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->tx_ring_size, GFP_KERNEL);
4385         np->tx_dma = kmalloc(sizeof(dma_addr_t) * np->tx_ring_size, GFP_KERNEL);
4386         np->tx_dma_len = kmalloc(sizeof(unsigned int) * np->tx_ring_size, GFP_KERNEL);
4387         if (!np->rx_skbuff || !np->rx_dma || !np->tx_skbuff || !np->tx_dma || !np->tx_dma_len)
4388                 goto out_freering;
4389         memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
4390         memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
4391         memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
4392         memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
4393         memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
4394
4395         dev->open = nv_open;
4396         dev->stop = nv_close;
4397         dev->hard_start_xmit = nv_start_xmit;
4398         dev->get_stats = nv_get_stats;
4399         dev->change_mtu = nv_change_mtu;
4400         dev->set_mac_address = nv_set_mac_address;
4401         dev->set_multicast_list = nv_set_multicast;
4402 #ifdef CONFIG_NET_POLL_CONTROLLER
4403         dev->poll_controller = nv_poll_controller;
4404 #endif
4405         dev->weight = 64;
4406 #ifdef CONFIG_FORCEDETH_NAPI
4407         dev->poll = nv_napi_poll;
4408 #endif
4409         SET_ETHTOOL_OPS(dev, &ops);
4410         dev->tx_timeout = nv_tx_timeout;
4411         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
4412
4413         pci_set_drvdata(pci_dev, dev);
4414
4415         /* read the mac address */
4416         base = get_hwbase(dev);
4417         np->orig_mac[0] = readl(base + NvRegMacAddrA);
4418         np->orig_mac[1] = readl(base + NvRegMacAddrB);
4419
4420         /* check the workaround bit for correct mac address order */
4421         txreg = readl(base + NvRegTransmitPoll);
4422         if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
4423                 /* mac address is already in correct order */
4424                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
4425                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
4426                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
4427                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
4428                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
4429                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
4430         } else {
4431                 /* need to reverse mac address to correct order */
4432                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
4433                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
4434                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
4435                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
4436                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
4437                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
4438                 /* set permanent address to be correct aswell */
4439                 np->orig_mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
4440                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
4441                 np->orig_mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
4442                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4443         }
4444         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4445
4446         if (!is_valid_ether_addr(dev->perm_addr)) {
4447                 /*
4448                  * Bad mac address. At least one bios sets the mac address
4449                  * to 01:23:45:67:89:ab
4450                  */
4451                 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
4452                         pci_name(pci_dev),
4453                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4454                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4455                 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
4456                 dev->dev_addr[0] = 0x00;
4457                 dev->dev_addr[1] = 0x00;
4458                 dev->dev_addr[2] = 0x6c;
4459                 get_random_bytes(&dev->dev_addr[3], 3);
4460         }
4461
4462         dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
4463                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4464                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4465
4466         /* set mac address */
4467         nv_copy_mac_to_hw(dev);
4468
4469         /* disable WOL */
4470         writel(0, base + NvRegWakeUpFlags);
4471         np->wolenabled = 0;
4472
4473         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
4474                 u8 revision_id;
4475                 pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id);
4476
4477                 /* take phy and nic out of low power mode */
4478                 powerstate = readl(base + NvRegPowerState2);
4479                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
4480                 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
4481                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
4482                     revision_id >= 0xA3)
4483                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
4484                 writel(powerstate, base + NvRegPowerState2);
4485         }
4486
4487         if (np->desc_ver == DESC_VER_1) {
4488                 np->tx_flags = NV_TX_VALID;
4489         } else {
4490                 np->tx_flags = NV_TX2_VALID;
4491         }
4492         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
4493                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
4494                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
4495                         np->msi_flags |= 0x0003;
4496         } else {
4497                 np->irqmask = NVREG_IRQMASK_CPU;
4498                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
4499                         np->msi_flags |= 0x0001;
4500         }
4501
4502         if (id->driver_data & DEV_NEED_TIMERIRQ)
4503                 np->irqmask |= NVREG_IRQ_TIMER;
4504         if (id->driver_data & DEV_NEED_LINKTIMER) {
4505                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
4506                 np->need_linktimer = 1;
4507                 np->link_timeout = jiffies + LINK_TIMEOUT;
4508         } else {
4509                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
4510                 np->need_linktimer = 0;
4511         }
4512
4513         /* find a suitable phy */
4514         for (i = 1; i <= 32; i++) {
4515                 int id1, id2;
4516                 int phyaddr = i & 0x1F;
4517
4518                 spin_lock_irq(&np->lock);
4519                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
4520                 spin_unlock_irq(&np->lock);
4521                 if (id1 < 0 || id1 == 0xffff)
4522                         continue;
4523                 spin_lock_irq(&np->lock);
4524                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
4525                 spin_unlock_irq(&np->lock);
4526                 if (id2 < 0 || id2 == 0xffff)
4527                         continue;
4528
4529                 np->phy_model = id2 & PHYID2_MODEL_MASK;
4530                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
4531                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
4532                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
4533                         pci_name(pci_dev), id1, id2, phyaddr);
4534                 np->phyaddr = phyaddr;
4535                 np->phy_oui = id1 | id2;
4536                 break;
4537         }
4538         if (i == 33) {
4539                 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
4540                        pci_name(pci_dev));
4541                 goto out_error;
4542         }
4543
4544         /* reset it */
4545         phy_init(dev);
4546
4547         /* set default link speed settings */
4548         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
4549         np->duplex = 0;
4550         np->autoneg = 1;
4551
4552         err = register_netdev(dev);
4553         if (err) {
4554                 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
4555                 goto out_error;
4556         }
4557         printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
4558                         dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
4559                         pci_name(pci_dev));
4560
4561         return 0;
4562
4563 out_error:
4564         pci_set_drvdata(pci_dev, NULL);
4565 out_freering:
4566         free_rings(dev);
4567 out_unmap:
4568         iounmap(get_hwbase(dev));
4569 out_relreg:
4570         pci_release_regions(pci_dev);
4571 out_disable:
4572         pci_disable_device(pci_dev);
4573 out_free:
4574         free_netdev(dev);
4575 out:
4576         return err;
4577 }
4578
4579 static void __devexit nv_remove(struct pci_dev *pci_dev)
4580 {
4581         struct net_device *dev = pci_get_drvdata(pci_dev);
4582         struct fe_priv *np = netdev_priv(dev);
4583         u8 __iomem *base = get_hwbase(dev);
4584
4585         unregister_netdev(dev);
4586
4587         /* special op: write back the misordered MAC address - otherwise
4588          * the next nv_probe would see a wrong address.
4589          */
4590         writel(np->orig_mac[0], base + NvRegMacAddrA);
4591         writel(np->orig_mac[1], base + NvRegMacAddrB);
4592
4593         /* free all structures */
4594         free_rings(dev);
4595         iounmap(get_hwbase(dev));
4596         pci_release_regions(pci_dev);
4597         pci_disable_device(pci_dev);
4598         free_netdev(dev);
4599         pci_set_drvdata(pci_dev, NULL);
4600 }
4601
4602 static struct pci_device_id pci_tbl[] = {
4603         {       /* nForce Ethernet Controller */
4604                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
4605                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4606         },
4607         {       /* nForce2 Ethernet Controller */
4608                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
4609                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4610         },
4611         {       /* nForce3 Ethernet Controller */
4612                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
4613                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4614         },
4615         {       /* nForce3 Ethernet Controller */
4616                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
4617                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4618         },
4619         {       /* nForce3 Ethernet Controller */
4620                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
4621                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4622         },
4623         {       /* nForce3 Ethernet Controller */
4624                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
4625                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4626         },
4627         {       /* nForce3 Ethernet Controller */
4628                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
4629                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4630         },
4631         {       /* CK804 Ethernet Controller */
4632                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
4633                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4634         },
4635         {       /* CK804 Ethernet Controller */
4636                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
4637                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4638         },
4639         {       /* MCP04 Ethernet Controller */
4640                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
4641                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4642         },
4643         {       /* MCP04 Ethernet Controller */
4644                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
4645                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4646         },
4647         {       /* MCP51 Ethernet Controller */
4648                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
4649                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4650         },
4651         {       /* MCP51 Ethernet Controller */
4652                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
4653                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4654         },
4655         {       /* MCP55 Ethernet Controller */
4656                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
4657                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4658         },
4659         {       /* MCP55 Ethernet Controller */
4660                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
4661                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4662         },
4663         {       /* MCP61 Ethernet Controller */
4664                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
4665                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4666         },
4667         {       /* MCP61 Ethernet Controller */
4668                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
4669                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4670         },
4671         {       /* MCP61 Ethernet Controller */
4672                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
4673                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4674         },
4675         {       /* MCP61 Ethernet Controller */
4676                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
4677                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4678         },
4679         {       /* MCP65 Ethernet Controller */
4680                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
4681                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4682         },
4683         {       /* MCP65 Ethernet Controller */
4684                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
4685                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4686         },
4687         {       /* MCP65 Ethernet Controller */
4688                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
4689                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4690         },
4691         {       /* MCP65 Ethernet Controller */
4692                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
4693                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4694         },
4695         {0,},
4696 };
4697
4698 static struct pci_driver driver = {
4699         .name = "forcedeth",
4700         .id_table = pci_tbl,
4701         .probe = nv_probe,
4702         .remove = __devexit_p(nv_remove),
4703 };
4704
4705
4706 static int __init init_nic(void)
4707 {
4708         printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
4709         return pci_register_driver(&driver);
4710 }
4711
4712 static void __exit exit_nic(void)
4713 {
4714         pci_unregister_driver(&driver);
4715 }
4716
4717 module_param(max_interrupt_work, int, 0);
4718 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
4719 module_param(optimization_mode, int, 0);
4720 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
4721 module_param(poll_interval, int, 0);
4722 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
4723 module_param(msi, int, 0);
4724 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
4725 module_param(msix, int, 0);
4726 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
4727 module_param(dma_64bit, int, 0);
4728 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
4729
4730 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
4731 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
4732 MODULE_LICENSE("GPL");
4733
4734 MODULE_DEVICE_TABLE(pci, pci_tbl);
4735
4736 module_init(init_nic);
4737 module_exit(exit_nic);