drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey.
   7  *
   8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
   9  * trademarks of NVIDIA Corporation in the United States and other
  10  * countries.
  11  *
  12  * Copyright (C) 2003,4,5 Manfred Spraul
  13  * Copyright (C) 2004 Andrew de Quincey (wol support)
  14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  16  * Copyright (c) 2004,2005,2006,2007,2008 NVIDIA Corporation
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License as published by
  20  * the Free Software Foundation; either version 2 of the License, or
  21  * (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  31  *
  32  * Known bugs:
  33  * We suspect that on some hardware no TX done interrupts are generated.
  34  * This means recovery from netif_stop_queue only happens if the hw timer
  35  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
  36  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
  37  * If your hardware reliably generates tx done interrupts, then you can remove
  38  * DEV_NEED_TIMERIRQ from the driver_data flags.
  39  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
  40  * superfluous timer interrupts from the nic.
  41  */
  42 #define FORCEDETH_VERSION               "0.61"
  43 #define DRV_NAME                        "forcedeth"
  44
  45 #include <linux/module.h>
  46 #include <linux/types.h>
  47 #include <linux/pci.h>
  48 #include <linux/interrupt.h>
  49 #include <linux/netdevice.h>
  50 #include <linux/etherdevice.h>
  51 #include <linux/delay.h>
  52 #include <linux/spinlock.h>
  53 #include <linux/ethtool.h>
  54 #include <linux/timer.h>
  55 #include <linux/skbuff.h>
  56 #include <linux/mii.h>
  57 #include <linux/random.h>
  58 #include <linux/init.h>
  59 #include <linux/if_vlan.h>
  60 #include <linux/dma-mapping.h>
  61
  62 #include <asm/irq.h>
  63 #include <asm/io.h>
  64 #include <asm/uaccess.h>
  65 #include <asm/system.h>
  66
  67 #if 0
  68 #define dprintk                 printk
  69 #else
  70 #define dprintk(x...)           do { } while (0)
  71 #endif
  72
  73 #define TX_WORK_PER_LOOP  64
  74 #define RX_WORK_PER_LOOP  64
  75
  76 /*
  77  * Hardware access:
  78  */
  79
  80 #define DEV_NEED_TIMERIRQ          0x00001  /* set the timer irq flag in the irq mask */
  81 #define DEV_NEED_LINKTIMER         0x00002  /* poll link settings. Relies on the timer irq */
  82 #define DEV_HAS_LARGEDESC          0x00004  /* device supports jumbo frames and needs packet format 2 */
  83 #define DEV_HAS_HIGH_DMA           0x00008  /* device supports 64bit dma */
  84 #define DEV_HAS_CHECKSUM           0x00010  /* device supports tx and rx checksum offloads */
  85 #define DEV_HAS_VLAN               0x00020  /* device supports vlan tagging and striping */
  86 #define DEV_HAS_MSI                0x00040  /* device supports MSI */
  87 #define DEV_HAS_MSI_X              0x00080  /* device supports MSI-X */
  88 #define DEV_HAS_POWER_CNTRL        0x00100  /* device supports power savings */
  89 #define DEV_HAS_STATISTICS_V1      0x00200  /* device supports hw statistics version 1 */
  90 #define DEV_HAS_STATISTICS_V2      0x00400  /* device supports hw statistics version 2 */
  91 #define DEV_HAS_TEST_EXTENDED      0x00800  /* device supports extended diagnostic test */
  92 #define DEV_HAS_MGMT_UNIT          0x01000  /* device supports management unit */
  93 #define DEV_HAS_CORRECT_MACADDR    0x02000  /* device supports correct mac address order */
  94 #define DEV_HAS_COLLISION_FIX      0x04000  /* device supports tx collision fix */
  95 #define DEV_HAS_PAUSEFRAME_TX_V1   0x08000  /* device supports tx pause frames version 1 */
  96 #define DEV_HAS_PAUSEFRAME_TX_V2   0x10000  /* device supports tx pause frames version 2 */
  97 #define DEV_HAS_PAUSEFRAME_TX_V3   0x20000  /* device supports tx pause frames version 3 */
  98 #define DEV_NEED_TX_LIMIT          0x40000  /* device needs to limit tx */
  99 #define DEV_HAS_GEAR_MODE          0x80000  /* device supports gear mode */
 100
 101 enum {
 102         NvRegIrqStatus = 0x000,
 103 #define NVREG_IRQSTAT_MIIEVENT  0x040
 104 #define NVREG_IRQSTAT_MASK              0x81ff
 105         NvRegIrqMask = 0x004,
 106 #define NVREG_IRQ_RX_ERROR              0x0001
 107 #define NVREG_IRQ_RX                    0x0002
 108 #define NVREG_IRQ_RX_NOBUF              0x0004
 109 #define NVREG_IRQ_TX_ERR                0x0008
 110 #define NVREG_IRQ_TX_OK                 0x0010
 111 #define NVREG_IRQ_TIMER                 0x0020
 112 #define NVREG_IRQ_LINK                  0x0040
 113 #define NVREG_IRQ_RX_FORCED             0x0080
 114 #define NVREG_IRQ_TX_FORCED             0x0100
 115 #define NVREG_IRQ_RECOVER_ERROR         0x8000
 116 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 117 #define NVREG_IRQMASK_CPU               0x0060
 118 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 119 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 120 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
 121
 122 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
 123                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
 124                                         NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
 125
 126         NvRegUnknownSetupReg6 = 0x008,
 127 #define NVREG_UNKSETUP6_VAL             3
 128
 129 /*
 130  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 131  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 132  */
 133         NvRegPollingInterval = 0x00c,
 134 #define NVREG_POLL_DEFAULT_THROUGHPUT   970 /* backup tx cleanup if loop max reached */
 135 #define NVREG_POLL_DEFAULT_CPU  13
 136         NvRegMSIMap0 = 0x020,
 137         NvRegMSIMap1 = 0x024,
 138         NvRegMSIIrqMask = 0x030,
 139 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 140         NvRegMisc1 = 0x080,
 141 #define NVREG_MISC1_PAUSE_TX    0x01
 142 #define NVREG_MISC1_HD          0x02
 143 #define NVREG_MISC1_FORCE       0x3b0f3c
 144
 145         NvRegMacReset = 0x34,
 146 #define NVREG_MAC_RESET_ASSERT  0x0F3
 147         NvRegTransmitterControl = 0x084,
 148 #define NVREG_XMITCTL_START     0x01
 149 #define NVREG_XMITCTL_MGMT_ST   0x40000000
 150 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
 151 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
 152 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
 153 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
 154 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
 155 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
 156 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
 157 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
 158 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
 159         NvRegTransmitterStatus = 0x088,
 160 #define NVREG_XMITSTAT_BUSY     0x01
 161
 162         NvRegPacketFilterFlags = 0x8c,
 163 #define NVREG_PFF_PAUSE_RX      0x08
 164 #define NVREG_PFF_ALWAYS        0x7F0000
 165 #define NVREG_PFF_PROMISC       0x80
 166 #define NVREG_PFF_MYADDR        0x20
 167 #define NVREG_PFF_LOOPBACK      0x10
 168
 169         NvRegOffloadConfig = 0x90,
 170 #define NVREG_OFFLOAD_HOMEPHY   0x601
 171 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 172         NvRegReceiverControl = 0x094,
 173 #define NVREG_RCVCTL_START      0x01
 174 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
 175         NvRegReceiverStatus = 0x98,
 176 #define NVREG_RCVSTAT_BUSY      0x01
 177
 178         NvRegSlotTime = 0x9c,
 179 #define NVREG_SLOTTIME_LEGBF_ENABLED    0x80000000
 180 #define NVREG_SLOTTIME_10_100_FULL      0x00007f00
 181 #define NVREG_SLOTTIME_1000_FULL        0x0003ff00
 182 #define NVREG_SLOTTIME_HALF             0x0000ff00
 183 #define NVREG_SLOTTIME_DEFAULT          0x00007f00
 184 #define NVREG_SLOTTIME_MASK             0x000000ff
 185
 186         NvRegTxDeferral = 0xA0,
 187 #define NVREG_TX_DEFERRAL_DEFAULT               0x15050f
 188 #define NVREG_TX_DEFERRAL_RGMII_10_100          0x16070f
 189 #define NVREG_TX_DEFERRAL_RGMII_1000            0x14050f
 190 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10      0x16190f
 191 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100     0x16300f
 192 #define NVREG_TX_DEFERRAL_MII_STRETCH           0x152000
 193         NvRegRxDeferral = 0xA4,
 194 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
 195         NvRegMacAddrA = 0xA8,
 196         NvRegMacAddrB = 0xAC,
 197         NvRegMulticastAddrA = 0xB0,
 198 #define NVREG_MCASTADDRA_FORCE  0x01
 199         NvRegMulticastAddrB = 0xB4,
 200         NvRegMulticastMaskA = 0xB8,
 201 #define NVREG_MCASTMASKA_NONE           0xffffffff
 202         NvRegMulticastMaskB = 0xBC,
 203 #define NVREG_MCASTMASKB_NONE           0xffff
 204
 205         NvRegPhyInterface = 0xC0,
 206 #define PHY_RGMII               0x10000000
 207         NvRegBackOffControl = 0xC4,
 208 #define NVREG_BKOFFCTRL_DEFAULT                 0x70000000
 209 #define NVREG_BKOFFCTRL_SEED_MASK               0x000003ff
 210 #define NVREG_BKOFFCTRL_SELECT                  24
 211 #define NVREG_BKOFFCTRL_GEAR                    12
 212
 213         NvRegTxRingPhysAddr = 0x100,
 214         NvRegRxRingPhysAddr = 0x104,
 215         NvRegRingSizes = 0x108,
 216 #define NVREG_RINGSZ_TXSHIFT 0
 217 #define NVREG_RINGSZ_RXSHIFT 16
 218         NvRegTransmitPoll = 0x10c,
 219 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
 220         NvRegLinkSpeed = 0x110,
 221 #define NVREG_LINKSPEED_FORCE 0x10000
 222 #define NVREG_LINKSPEED_10      1000
 223 #define NVREG_LINKSPEED_100     100
 224 #define NVREG_LINKSPEED_1000    50
 225 #define NVREG_LINKSPEED_MASK    (0xFFF)
 226         NvRegUnknownSetupReg5 = 0x130,
 227 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 228         NvRegTxWatermark = 0x13c,
 229 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
 230 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
 231 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
 232         NvRegTxRxControl = 0x144,
 233 #define NVREG_TXRXCTL_KICK      0x0001
 234 #define NVREG_TXRXCTL_BIT1      0x0002
 235 #define NVREG_TXRXCTL_BIT2      0x0004
 236 #define NVREG_TXRXCTL_IDLE      0x0008
 237 #define NVREG_TXRXCTL_RESET     0x0010
 238 #define NVREG_TXRXCTL_RXCHECK   0x0400
 239 #define NVREG_TXRXCTL_DESC_1    0
 240 #define NVREG_TXRXCTL_DESC_2    0x002100
 241 #define NVREG_TXRXCTL_DESC_3    0xc02200
 242 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 243 #define NVREG_TXRXCTL_VLANINS   0x00080
 244         NvRegTxRingPhysAddrHigh = 0x148,
 245         NvRegRxRingPhysAddrHigh = 0x14C,
 246         NvRegTxPauseFrame = 0x170,
 247 #define NVREG_TX_PAUSEFRAME_DISABLE     0x0fff0080
 248 #define NVREG_TX_PAUSEFRAME_ENABLE_V1   0x01800010
 249 #define NVREG_TX_PAUSEFRAME_ENABLE_V2   0x056003f0
 250 #define NVREG_TX_PAUSEFRAME_ENABLE_V3   0x09f00880
 251         NvRegMIIStatus = 0x180,
 252 #define NVREG_MIISTAT_ERROR             0x0001
 253 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 254 #define NVREG_MIISTAT_MASK_RW           0x0007
 255 #define NVREG_MIISTAT_MASK_ALL          0x000f
 256         NvRegMIIMask = 0x184,
 257 #define NVREG_MII_LINKCHANGE            0x0008
 258
 259         NvRegAdapterControl = 0x188,
 260 #define NVREG_ADAPTCTL_START    0x02
 261 #define NVREG_ADAPTCTL_LINKUP   0x04
 262 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 263 #define NVREG_ADAPTCTL_RUNNING  0x100000
 264 #define NVREG_ADAPTCTL_PHYSHIFT 24
 265         NvRegMIISpeed = 0x18c,
 266 #define NVREG_MIISPEED_BIT8     (1<<8)
 267 #define NVREG_MIIDELAY  5
 268         NvRegMIIControl = 0x190,
 269 #define NVREG_MIICTL_INUSE      0x08000
 270 #define NVREG_MIICTL_WRITE      0x00400
 271 #define NVREG_MIICTL_ADDRSHIFT  5
 272         NvRegMIIData = 0x194,
 273         NvRegWakeUpFlags = 0x200,
 274 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 275 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 276 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 277 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 278 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 279 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 280 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 281 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 282 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 283 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 284 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 285
 286         NvRegPatternCRC = 0x204,
 287         NvRegPatternMask = 0x208,
 288         NvRegPowerCap = 0x268,
 289 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 290 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 291 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 292         NvRegPowerState = 0x26c,
 293 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 294 #define NVREG_POWERSTATE_VALID          0x0100
 295 #define NVREG_POWERSTATE_MASK           0x0003
 296 #define NVREG_POWERSTATE_D0             0x0000
 297 #define NVREG_POWERSTATE_D1             0x0001
 298 #define NVREG_POWERSTATE_D2             0x0002
 299 #define NVREG_POWERSTATE_D3             0x0003
 300         NvRegTxCnt = 0x280,
 301         NvRegTxZeroReXmt = 0x284,
 302         NvRegTxOneReXmt = 0x288,
 303         NvRegTxManyReXmt = 0x28c,
 304         NvRegTxLateCol = 0x290,
 305         NvRegTxUnderflow = 0x294,
 306         NvRegTxLossCarrier = 0x298,
 307         NvRegTxExcessDef = 0x29c,
 308         NvRegTxRetryErr = 0x2a0,
 309         NvRegRxFrameErr = 0x2a4,
 310         NvRegRxExtraByte = 0x2a8,
 311         NvRegRxLateCol = 0x2ac,
 312         NvRegRxRunt = 0x2b0,
 313         NvRegRxFrameTooLong = 0x2b4,
 314         NvRegRxOverflow = 0x2b8,
 315         NvRegRxFCSErr = 0x2bc,
 316         NvRegRxFrameAlignErr = 0x2c0,
 317         NvRegRxLenErr = 0x2c4,
 318         NvRegRxUnicast = 0x2c8,
 319         NvRegRxMulticast = 0x2cc,
 320         NvRegRxBroadcast = 0x2d0,
 321         NvRegTxDef = 0x2d4,
 322         NvRegTxFrame = 0x2d8,
 323         NvRegRxCnt = 0x2dc,
 324         NvRegTxPause = 0x2e0,
 325         NvRegRxPause = 0x2e4,
 326         NvRegRxDropFrame = 0x2e8,
 327         NvRegVlanControl = 0x300,
 328 #define NVREG_VLANCONTROL_ENABLE        0x2000
 329         NvRegMSIXMap0 = 0x3e0,
 330         NvRegMSIXMap1 = 0x3e4,
 331         NvRegMSIXIrqStatus = 0x3f0,
 332
 333         NvRegPowerState2 = 0x600,
 334 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F11
 335 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 336 };
 337
 338 /* Big endian: should work, but is untested */
 339 struct ring_desc {
 340         __le32 buf;
 341         __le32 flaglen;
 342 };
 343
 344 struct ring_desc_ex {
 345         __le32 bufhigh;
 346         __le32 buflow;
 347         __le32 txvlan;
 348         __le32 flaglen;
 349 };
 350
 351 union ring_type {
 352         struct ring_desc* orig;
 353         struct ring_desc_ex* ex;
 354 };
 355
 356 #define FLAG_MASK_V1 0xffff0000
 357 #define FLAG_MASK_V2 0xffffc000
 358 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 359 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 360
 361 #define NV_TX_LASTPACKET        (1<<16)
 362 #define NV_TX_RETRYERROR        (1<<19)
 363 #define NV_TX_RETRYCOUNT_MASK   (0xF<<20)
 364 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 365 #define NV_TX_DEFERRED          (1<<26)
 366 #define NV_TX_CARRIERLOST       (1<<27)
 367 #define NV_TX_LATECOLLISION     (1<<28)
 368 #define NV_TX_UNDERFLOW         (1<<29)
 369 #define NV_TX_ERROR             (1<<30)
 370 #define NV_TX_VALID             (1<<31)
 371
 372 #define NV_TX2_LASTPACKET       (1<<29)
 373 #define NV_TX2_RETRYERROR       (1<<18)
 374 #define NV_TX2_RETRYCOUNT_MASK  (0xF<<19)
 375 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 376 #define NV_TX2_DEFERRED         (1<<25)
 377 #define NV_TX2_CARRIERLOST      (1<<26)
 378 #define NV_TX2_LATECOLLISION    (1<<27)
 379 #define NV_TX2_UNDERFLOW        (1<<28)
 380 /* error and valid are the same for both */
 381 #define NV_TX2_ERROR            (1<<30)
 382 #define NV_TX2_VALID            (1<<31)
 383 #define NV_TX2_TSO              (1<<28)
 384 #define NV_TX2_TSO_SHIFT        14
 385 #define NV_TX2_TSO_MAX_SHIFT    14
 386 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 387 #define NV_TX2_CHECKSUM_L3      (1<<27)
 388 #define NV_TX2_CHECKSUM_L4      (1<<26)
 389
 390 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 391
 392 #define NV_RX_DESCRIPTORVALID   (1<<16)
 393 #define NV_RX_MISSEDFRAME       (1<<17)
 394 #define NV_RX_SUBSTRACT1        (1<<18)
 395 #define NV_RX_ERROR1            (1<<23)
 396 #define NV_RX_ERROR2            (1<<24)
 397 #define NV_RX_ERROR3            (1<<25)
 398 #define NV_RX_ERROR4            (1<<26)
 399 #define NV_RX_CRCERR            (1<<27)
 400 #define NV_RX_OVERFLOW          (1<<28)
 401 #define NV_RX_FRAMINGERR        (1<<29)
 402 #define NV_RX_ERROR             (1<<30)
 403 #define NV_RX_AVAIL             (1<<31)
 404
 405 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 406 #define NV_RX2_CHECKSUM_IP      (0x10000000)
 407 #define NV_RX2_CHECKSUM_IP_TCP  (0x14000000)
 408 #define NV_RX2_CHECKSUM_IP_UDP  (0x18000000)
 409 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 410 #define NV_RX2_SUBSTRACT1       (1<<25)
 411 #define NV_RX2_ERROR1           (1<<18)
 412 #define NV_RX2_ERROR2           (1<<19)
 413 #define NV_RX2_ERROR3           (1<<20)
 414 #define NV_RX2_ERROR4           (1<<21)
 415 #define NV_RX2_CRCERR           (1<<22)
 416 #define NV_RX2_OVERFLOW         (1<<23)
 417 #define NV_RX2_FRAMINGERR       (1<<24)
 418 /* error and avail are the same for both */
 419 #define NV_RX2_ERROR            (1<<30)
 420 #define NV_RX2_AVAIL            (1<<31)
 421
 422 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 423 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 424
 425 /* Miscelaneous hardware related defines: */
 426 #define NV_PCI_REGSZ_VER1       0x270
 427 #define NV_PCI_REGSZ_VER2       0x2d4
 428 #define NV_PCI_REGSZ_VER3       0x604
 429 #define NV_PCI_REGSZ_MAX        0x604
 430
 431 /* various timeout delays: all in usec */
 432 #define NV_TXRX_RESET_DELAY     4
 433 #define NV_TXSTOP_DELAY1        10
 434 #define NV_TXSTOP_DELAY1MAX     500000
 435 #define NV_TXSTOP_DELAY2        100
 436 #define NV_RXSTOP_DELAY1        10
 437 #define NV_RXSTOP_DELAY1MAX     500000
 438 #define NV_RXSTOP_DELAY2        100
 439 #define NV_SETUP5_DELAY         5
 440 #define NV_SETUP5_DELAYMAX      50000
 441 #define NV_POWERUP_DELAY        5
 442 #define NV_POWERUP_DELAYMAX     5000
 443 #define NV_MIIBUSY_DELAY        50
 444 #define NV_MIIPHY_DELAY 10
 445 #define NV_MIIPHY_DELAYMAX      10000
 446 #define NV_MAC_RESET_DELAY      64
 447
 448 #define NV_WAKEUPPATTERNS       5
 449 #define NV_WAKEUPMASKENTRIES    4
 450
 451 /* General driver defaults */
 452 #define NV_WATCHDOG_TIMEO       (5*HZ)
 453
 454 #define RX_RING_DEFAULT         128
 455 #define TX_RING_DEFAULT         256
 456 #define RX_RING_MIN             128
 457 #define TX_RING_MIN             64
 458 #define RING_MAX_DESC_VER_1     1024
 459 #define RING_MAX_DESC_VER_2_3   16384
 460
 461 /* rx/tx mac addr + type + vlan + align + slack*/
 462 #define NV_RX_HEADERS           (64)
 463 /* even more slack. */
 464 #define NV_RX_ALLOC_PAD         (64)
 465
 466 /* maximum mtu size */
 467 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 468 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 469
 470 #define OOM_REFILL      (1+HZ/20)
 471 #define POLL_WAIT       (1+HZ/100)
 472 #define LINK_TIMEOUT    (3*HZ)
 473 #define STATS_INTERVAL  (10*HZ)
 474
 475 /*
 476  * desc_ver values:
 477  * The nic supports three different descriptor types:
 478  * - DESC_VER_1: Original
 479  * - DESC_VER_2: support for jumbo frames.
 480  * - DESC_VER_3: 64-bit format.
 481  */
 482 #define DESC_VER_1      1
 483 #define DESC_VER_2      2
 484 #define DESC_VER_3      3
 485
 486 /* PHY defines */
 487 #define PHY_OUI_MARVELL         0x5043
 488 #define PHY_OUI_CICADA          0x03f1
 489 #define PHY_OUI_VITESSE         0x01c1
 490 #define PHY_OUI_REALTEK         0x0732
 491 #define PHY_OUI_REALTEK2        0x0020
 492 #define PHYID1_OUI_MASK 0x03ff
 493 #define PHYID1_OUI_SHFT 6
 494 #define PHYID2_OUI_MASK 0xfc00
 495 #define PHYID2_OUI_SHFT 10
 496 #define PHYID2_MODEL_MASK               0x03f0
 497 #define PHY_MODEL_REALTEK_8211          0x0110
 498 #define PHY_REV_MASK                    0x0001
 499 #define PHY_REV_REALTEK_8211B           0x0000
 500 #define PHY_REV_REALTEK_8211C           0x0001
 501 #define PHY_MODEL_REALTEK_8201          0x0200
 502 #define PHY_MODEL_MARVELL_E3016         0x0220
 503 #define PHY_MARVELL_E3016_INITMASK      0x0300
 504 #define PHY_CICADA_INIT1        0x0f000
 505 #define PHY_CICADA_INIT2        0x0e00
 506 #define PHY_CICADA_INIT3        0x01000
 507 #define PHY_CICADA_INIT4        0x0200
 508 #define PHY_CICADA_INIT5        0x0004
 509 #define PHY_CICADA_INIT6        0x02000
 510 #define PHY_VITESSE_INIT_REG1   0x1f
 511 #define PHY_VITESSE_INIT_REG2   0x10
 512 #define PHY_VITESSE_INIT_REG3   0x11
 513 #define PHY_VITESSE_INIT_REG4   0x12
 514 #define PHY_VITESSE_INIT_MSK1   0xc
 515 #define PHY_VITESSE_INIT_MSK2   0x0180
 516 #define PHY_VITESSE_INIT1       0x52b5
 517 #define PHY_VITESSE_INIT2       0xaf8a
 518 #define PHY_VITESSE_INIT3       0x8
 519 #define PHY_VITESSE_INIT4       0x8f8a
 520 #define PHY_VITESSE_INIT5       0xaf86
 521 #define PHY_VITESSE_INIT6       0x8f86
 522 #define PHY_VITESSE_INIT7       0xaf82
 523 #define PHY_VITESSE_INIT8       0x0100
 524 #define PHY_VITESSE_INIT9       0x8f82
 525 #define PHY_VITESSE_INIT10      0x0
 526 #define PHY_REALTEK_INIT_REG1   0x1f
 527 #define PHY_REALTEK_INIT_REG2   0x19
 528 #define PHY_REALTEK_INIT_REG3   0x13
 529 #define PHY_REALTEK_INIT_REG4   0x14
 530 #define PHY_REALTEK_INIT_REG5   0x18
 531 #define PHY_REALTEK_INIT_REG6   0x11
 532 #define PHY_REALTEK_INIT1       0x0000
 533 #define PHY_REALTEK_INIT2       0x8e00
 534 #define PHY_REALTEK_INIT3       0x0001
 535 #define PHY_REALTEK_INIT4       0xad17
 536 #define PHY_REALTEK_INIT5       0xfb54
 537 #define PHY_REALTEK_INIT6       0xf5c7
 538 #define PHY_REALTEK_INIT7       0x1000
 539 #define PHY_REALTEK_INIT8       0x0003
 540 #define PHY_REALTEK_INIT_MSK1   0x0003
 541
 542 #define PHY_GIGABIT     0x0100
 543
 544 #define PHY_TIMEOUT     0x1
 545 #define PHY_ERROR       0x2
 546
 547 #define PHY_100 0x1
 548 #define PHY_1000        0x2
 549 #define PHY_HALF        0x100
 550
 551 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 552 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 553 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 554 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 555 #define NV_PAUSEFRAME_RX_REQ     0x0010
 556 #define NV_PAUSEFRAME_TX_REQ     0x0020
 557 #define NV_PAUSEFRAME_AUTONEG    0x0040
 558
 559 /* MSI/MSI-X defines */
 560 #define NV_MSI_X_MAX_VECTORS  8
 561 #define NV_MSI_X_VECTORS_MASK 0x000f
 562 #define NV_MSI_CAPABLE        0x0010
 563 #define NV_MSI_X_CAPABLE      0x0020
 564 #define NV_MSI_ENABLED        0x0040
 565 #define NV_MSI_X_ENABLED      0x0080
 566
 567 #define NV_MSI_X_VECTOR_ALL   0x0
 568 #define NV_MSI_X_VECTOR_RX    0x0
 569 #define NV_MSI_X_VECTOR_TX    0x1
 570 #define NV_MSI_X_VECTOR_OTHER 0x2
 571
 572 #define NV_RESTART_TX         0x1
 573 #define NV_RESTART_RX         0x2
 574
 575 #define NV_TX_LIMIT_COUNT     16
 576
 577 /* statistics */
 578 struct nv_ethtool_str {
 579         char name[ETH_GSTRING_LEN];
 580 };
 581
 582 static const struct nv_ethtool_str nv_estats_str[] = {
 583         { "tx_bytes" },
 584         { "tx_zero_rexmt" },
 585         { "tx_one_rexmt" },
 586         { "tx_many_rexmt" },
 587         { "tx_late_collision" },
 588         { "tx_fifo_errors" },
 589         { "tx_carrier_errors" },
 590         { "tx_excess_deferral" },
 591         { "tx_retry_error" },
 592         { "rx_frame_error" },
 593         { "rx_extra_byte" },
 594         { "rx_late_collision" },
 595         { "rx_runt" },
 596         { "rx_frame_too_long" },
 597         { "rx_over_errors" },
 598         { "rx_crc_errors" },
 599         { "rx_frame_align_error" },
 600         { "rx_length_error" },
 601         { "rx_unicast" },
 602         { "rx_multicast" },
 603         { "rx_broadcast" },
 604         { "rx_packets" },
 605         { "rx_errors_total" },
 606         { "tx_errors_total" },
 607
 608         /* version 2 stats */
 609         { "tx_deferral" },
 610         { "tx_packets" },
 611         { "rx_bytes" },
 612         { "tx_pause" },
 613         { "rx_pause" },
 614         { "rx_drop_frame" }
 615 };
 616
 617 struct nv_ethtool_stats {
 618         u64 tx_bytes;
 619         u64 tx_zero_rexmt;
 620         u64 tx_one_rexmt;
 621         u64 tx_many_rexmt;
 622         u64 tx_late_collision;
 623         u64 tx_fifo_errors;
 624         u64 tx_carrier_errors;
 625         u64 tx_excess_deferral;
 626         u64 tx_retry_error;
 627         u64 rx_frame_error;
 628         u64 rx_extra_byte;
 629         u64 rx_late_collision;
 630         u64 rx_runt;
 631         u64 rx_frame_too_long;
 632         u64 rx_over_errors;
 633         u64 rx_crc_errors;
 634         u64 rx_frame_align_error;
 635         u64 rx_length_error;
 636         u64 rx_unicast;
 637         u64 rx_multicast;
 638         u64 rx_broadcast;
 639         u64 rx_packets;
 640         u64 rx_errors_total;
 641         u64 tx_errors_total;
 642
 643         /* version 2 stats */
 644         u64 tx_deferral;
 645         u64 tx_packets;
 646         u64 rx_bytes;
 647         u64 tx_pause;
 648         u64 rx_pause;
 649         u64 rx_drop_frame;
 650 };
 651
 652 #define NV_DEV_STATISTICS_V2_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
 653 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
 654
 655 /* diagnostics */
 656 #define NV_TEST_COUNT_BASE 3
 657 #define NV_TEST_COUNT_EXTENDED 4
 658
 659 static const struct nv_ethtool_str nv_etests_str[] = {
 660         { "link      (online/offline)" },
 661         { "register  (offline)       " },
 662         { "interrupt (offline)       " },
 663         { "loopback  (offline)       " }
 664 };
 665
 666 struct register_test {
 667         __u32 reg;
 668         __u32 mask;
 669 };
 670
 671 static const struct register_test nv_registers_test[] = {
 672         { NvRegUnknownSetupReg6, 0x01 },
 673         { NvRegMisc1, 0x03c },
 674         { NvRegOffloadConfig, 0x03ff },
 675         { NvRegMulticastAddrA, 0xffffffff },
 676         { NvRegTxWatermark, 0x0ff },
 677         { NvRegWakeUpFlags, 0x07777 },
 678         { 0,0 }
 679 };
 680
 681 struct nv_skb_map {
 682         struct sk_buff *skb;
 683         dma_addr_t dma;
 684         unsigned int dma_len;
 685         struct ring_desc_ex *first_tx_desc;
 686         struct nv_skb_map *next_tx_ctx;
 687 };
 688
 689 /*
 690  * SMP locking:
 691  * All hardware access under dev->priv->lock, except the performance
 692  * critical parts:
 693  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 694  *      by the arch code for interrupts.
 695  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 696  *      needs dev->priv->lock :-(
 697  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 698  */
 699
 700 /* in dev: base, irq */
 701 struct fe_priv {
 702         spinlock_t lock;
 703
 704         struct net_device *dev;
 705         struct napi_struct napi;
 706
 707         /* General data:
 708          * Locking: spin_lock(&np->lock); */
 709         struct nv_ethtool_stats estats;
 710         int in_shutdown;
 711         u32 linkspeed;
 712         int duplex;
 713         int autoneg;
 714         int fixed_mode;
 715         int phyaddr;
 716         int wolenabled;
 717         unsigned int phy_oui;
 718         unsigned int phy_model;
 719         unsigned int phy_rev;
 720         u16 gigabit;
 721         int intr_test;
 722         int recover_error;
 723
 724         /* General data: RO fields */
 725         dma_addr_t ring_addr;
 726         struct pci_dev *pci_dev;
 727         u32 orig_mac[2];
 728         u32 irqmask;
 729         u32 desc_ver;
 730         u32 txrxctl_bits;
 731         u32 vlanctl_bits;
 732         u32 driver_data;
 733         u32 device_id;
 734         u32 register_size;
 735         int rx_csum;
 736         u32 mac_in_use;
 737
 738         void __iomem *base;
 739
 740         /* rx specific fields.
 741          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 742          */
 743         union ring_type get_rx, put_rx, first_rx, last_rx;
 744         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
 745         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
 746         struct nv_skb_map *rx_skb;
 747
 748         union ring_type rx_ring;
 749         unsigned int rx_buf_sz;
 750         unsigned int pkt_limit;
 751         struct timer_list oom_kick;
 752         struct timer_list nic_poll;
 753         struct timer_list stats_poll;
 754         u32 nic_poll_irq;
 755         int rx_ring_size;
 756
 757         /* media detection workaround.
 758          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 759          */
 760         int need_linktimer;
 761         unsigned long link_timeout;
 762         /*
 763          * tx specific fields.
 764          */
 765         union ring_type get_tx, put_tx, first_tx, last_tx;
 766         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
 767         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
 768         struct nv_skb_map *tx_skb;
 769
 770         union ring_type tx_ring;
 771         u32 tx_flags;
 772         int tx_ring_size;
 773         int tx_limit;
 774         u32 tx_pkts_in_progress;
 775         struct nv_skb_map *tx_change_owner;
 776         struct nv_skb_map *tx_end_flip;
 777         int tx_stop;
 778
 779         /* vlan fields */
 780         struct vlan_group *vlangrp;
 781
 782         /* msi/msi-x fields */
 783         u32 msi_flags;
 784         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 785
 786         /* flow control */
 787         u32 pause_flags;
 788
 789         /* power saved state */
 790         u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
 791 };
 792
 793 /*
 794  * Maximum number of loops until we assume that a bit in the irq mask
 795  * is stuck. Overridable with module param.
 796  */
 797 static int max_interrupt_work = 5;
 798
 799 /*
 800  * Optimization can be either throuput mode or cpu mode
 801  *
 802  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 803  * CPU Mode: Interrupts are controlled by a timer.
 804  */
 805 enum {
 806         NV_OPTIMIZATION_MODE_THROUGHPUT,
 807         NV_OPTIMIZATION_MODE_CPU
 808 };
 809 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
 810
 811 /*
 812  * Poll interval for timer irq
 813  *
 814  * This interval determines how frequent an interrupt is generated.
 815  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 816  * Min = 0, and Max = 65535
 817  */
 818 static int poll_interval = -1;
 819
 820 /*
 821  * MSI interrupts
 822  */
 823 enum {
 824         NV_MSI_INT_DISABLED,
 825         NV_MSI_INT_ENABLED
 826 };
 827 static int msi = NV_MSI_INT_ENABLED;
 828
 829 /*
 830  * MSIX interrupts
 831  */
 832 enum {
 833         NV_MSIX_INT_DISABLED,
 834         NV_MSIX_INT_ENABLED
 835 };
 836 static int msix = NV_MSIX_INT_DISABLED;
 837
 838 /*
 839  * DMA 64bit
 840  */
 841 enum {
 842         NV_DMA_64BIT_DISABLED,
 843         NV_DMA_64BIT_ENABLED
 844 };
 845 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 846
 847 /*
 848  * Crossover Detection
 849  * Realtek 8201 phy + some OEM boards do not work properly.
 850  */
 851 enum {
 852         NV_CROSSOVER_DETECTION_DISABLED,
 853         NV_CROSSOVER_DETECTION_ENABLED
 854 };
 855 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
 856
 857 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 858 {
 859         return netdev_priv(dev);
 860 }
 861
 862 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 863 {
 864         return ((struct fe_priv *)netdev_priv(dev))->base;
 865 }
 866
 867 static inline void pci_push(u8 __iomem *base)
 868 {
 869         /* force out pending posted writes */
 870         readl(base);
 871 }
 872
 873 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 874 {
 875         return le32_to_cpu(prd->flaglen)
 876                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 877 }
 878
 879 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 880 {
 881         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
 882 }
 883
 884 static bool nv_optimized(struct fe_priv *np)
 885 {
 886         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 887                 return false;
 888         return true;
 889 }
 890
 891 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 892                                 int delay, int delaymax, const char *msg)
 893 {
 894         u8 __iomem *base = get_hwbase(dev);
 895
 896         pci_push(base);
 897         do {
 898                 udelay(delay);
 899                 delaymax -= delay;
 900                 if (delaymax < 0) {
 901                         if (msg)
 902                                 printk(msg);
 903                         return 1;
 904                 }
 905         } while ((readl(base + offset) & mask) != target);
 906         return 0;
 907 }
 908
 909 #define NV_SETUP_RX_RING 0x01
 910 #define NV_SETUP_TX_RING 0x02
 911
 912 static inline u32 dma_low(dma_addr_t addr)
 913 {
 914         return addr;
 915 }
 916
 917 static inline u32 dma_high(dma_addr_t addr)
 918 {
 919         return addr>>31>>1;     /* 0 if 32bit, shift down by 32 if 64bit */
 920 }
 921
 922 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
 923 {
 924         struct fe_priv *np = get_nvpriv(dev);
 925         u8 __iomem *base = get_hwbase(dev);
 926
 927         if (!nv_optimized(np)) {
 928                 if (rxtx_flags & NV_SETUP_RX_RING) {
 929                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
 930                 }
 931                 if (rxtx_flags & NV_SETUP_TX_RING) {
 932                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
 933                 }
 934         } else {
 935                 if (rxtx_flags & NV_SETUP_RX_RING) {
 936                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
 937                         writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
 938                 }
 939                 if (rxtx_flags & NV_SETUP_TX_RING) {
 940                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
 941                         writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
 942                 }
 943         }
 944 }
 945
 946 static void free_rings(struct net_device *dev)
 947 {
 948         struct fe_priv *np = get_nvpriv(dev);
 949
 950         if (!nv_optimized(np)) {
 951                 if (np->rx_ring.orig)
 952                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
 953                                             np->rx_ring.orig, np->ring_addr);
 954         } else {
 955                 if (np->rx_ring.ex)
 956                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
 957                                             np->rx_ring.ex, np->ring_addr);
 958         }
 959         if (np->rx_skb)
 960                 kfree(np->rx_skb);
 961         if (np->tx_skb)
 962                 kfree(np->tx_skb);
 963 }
 964
 965 static int using_multi_irqs(struct net_device *dev)
 966 {
 967         struct fe_priv *np = get_nvpriv(dev);
 968
 969         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
 970             ((np->msi_flags & NV_MSI_X_ENABLED) &&
 971              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
 972                 return 0;
 973         else
 974                 return 1;
 975 }
 976
 977 static void nv_enable_irq(struct net_device *dev)
 978 {
 979         struct fe_priv *np = get_nvpriv(dev);
 980
 981         if (!using_multi_irqs(dev)) {
 982                 if (np->msi_flags & NV_MSI_X_ENABLED)
 983                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 984                 else
 985                         enable_irq(np->pci_dev->irq);
 986         } else {
 987                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 988                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 989                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
 990         }
 991 }
 992
 993 static void nv_disable_irq(struct net_device *dev)
 994 {
 995         struct fe_priv *np = get_nvpriv(dev);
 996
 997         if (!using_multi_irqs(dev)) {
 998                 if (np->msi_flags & NV_MSI_X_ENABLED)
 999                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1000                 else
1001                         disable_irq(np->pci_dev->irq);
1002         } else {
1003                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1004                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1005                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1006         }
1007 }
1008
1009 /* In MSIX mode, a write to irqmask behaves as XOR */
1010 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1011 {
1012         u8 __iomem *base = get_hwbase(dev);
1013
1014         writel(mask, base + NvRegIrqMask);
1015 }
1016
1017 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1018 {
1019         struct fe_priv *np = get_nvpriv(dev);
1020         u8 __iomem *base = get_hwbase(dev);
1021
1022         if (np->msi_flags & NV_MSI_X_ENABLED) {
1023                 writel(mask, base + NvRegIrqMask);
1024         } else {
1025                 if (np->msi_flags & NV_MSI_ENABLED)
1026                         writel(0, base + NvRegMSIIrqMask);
1027                 writel(0, base + NvRegIrqMask);
1028         }
1029 }
1030
1031 #define MII_READ        (-1)
1032 /* mii_rw: read/write a register on the PHY.
1033  *
1034  * Caller must guarantee serialization
1035  */
1036 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1037 {
1038         u8 __iomem *base = get_hwbase(dev);
1039         u32 reg;
1040         int retval;
1041
1042         writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1043
1044         reg = readl(base + NvRegMIIControl);
1045         if (reg & NVREG_MIICTL_INUSE) {
1046                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1047                 udelay(NV_MIIBUSY_DELAY);
1048         }
1049
1050         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1051         if (value != MII_READ) {
1052                 writel(value, base + NvRegMIIData);
1053                 reg |= NVREG_MIICTL_WRITE;
1054         }
1055         writel(reg, base + NvRegMIIControl);
1056
1057         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1058                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1059                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1060                                 dev->name, miireg, addr);
1061                 retval = -1;
1062         } else if (value != MII_READ) {
1063                 /* it was a write operation - fewer failures are detectable */
1064                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1065                                 dev->name, value, miireg, addr);
1066                 retval = 0;
1067         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1068                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1069                                 dev->name, miireg, addr);
1070                 retval = -1;
1071         } else {
1072                 retval = readl(base + NvRegMIIData);
1073                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1074                                 dev->name, miireg, addr, retval);
1075         }
1076
1077         return retval;
1078 }
1079
1080 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1081 {
1082         struct fe_priv *np = netdev_priv(dev);
1083         u32 miicontrol;
1084         unsigned int tries = 0;
1085
1086         miicontrol = BMCR_RESET | bmcr_setup;
1087         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1088                 return -1;
1089         }
1090
1091         /* wait for 500ms */
1092         msleep(500);
1093
1094         /* must wait till reset is deasserted */
1095         while (miicontrol & BMCR_RESET) {
1096                 msleep(10);
1097                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1098                 /* FIXME: 100 tries seem excessive */
1099                 if (tries++ > 100)
1100                         return -1;
1101         }
1102         return 0;
1103 }
1104
1105 static int phy_init(struct net_device *dev)
1106 {
1107         struct fe_priv *np = get_nvpriv(dev);
1108         u8 __iomem *base = get_hwbase(dev);
1109         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1110
1111         /* phy errata for E3016 phy */
1112         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1113                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1114                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1115                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1116                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1117                         return PHY_ERROR;
1118                 }
1119         }
1120         if (np->phy_oui == PHY_OUI_REALTEK) {
1121                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1122                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1123                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1124                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1125                                 return PHY_ERROR;
1126                         }
1127                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1128                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1129                                 return PHY_ERROR;
1130                         }
1131                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1132                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1133                                 return PHY_ERROR;
1134                         }
1135                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1136                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1137                                 return PHY_ERROR;
1138                         }
1139                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1140                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1141                                 return PHY_ERROR;
1142                         }
1143                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1144                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1145                                 return PHY_ERROR;
1146                         }
1147                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1148                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1149                                 return PHY_ERROR;
1150                         }
1151                 }
1152                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1153                         if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
1154                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1155                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1156                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1157                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1158                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1159                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1160                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1161                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1162                                 phy_reserved |= PHY_REALTEK_INIT7;
1163                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1164                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1165                                         return PHY_ERROR;
1166                                 }
1167                         }
1168                 }
1169         }
1170
1171         /* set advertise register */
1172         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1173         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1174         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1175                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1176                 return PHY_ERROR;
1177         }
1178
1179         /* get phy interface type */
1180         phyinterface = readl(base + NvRegPhyInterface);
1181
1182         /* see if gigabit phy */
1183         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1184         if (mii_status & PHY_GIGABIT) {
1185                 np->gigabit = PHY_GIGABIT;
1186                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1187                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1188                 if (phyinterface & PHY_RGMII)
1189                         mii_control_1000 |= ADVERTISE_1000FULL;
1190                 else
1191                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1192
1193                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1194                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1195                         return PHY_ERROR;
1196                 }
1197         }
1198         else
1199                 np->gigabit = 0;
1200
1201         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1202         mii_control |= BMCR_ANENABLE;
1203
1204         /* reset the phy
1205          * (certain phys need bmcr to be setup with reset)
1206          */
1207         if (phy_reset(dev, mii_control)) {
1208                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1209                 return PHY_ERROR;
1210         }
1211
1212         /* phy vendor specific configuration */
1213         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1214                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1215                 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1216                 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1217                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1218                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1219                         return PHY_ERROR;
1220                 }
1221                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1222                 phy_reserved |= PHY_CICADA_INIT5;
1223                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1224                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1225                         return PHY_ERROR;
1226                 }
1227         }
1228         if (np->phy_oui == PHY_OUI_CICADA) {
1229                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1230                 phy_reserved |= PHY_CICADA_INIT6;
1231                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1232                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1233                         return PHY_ERROR;
1234                 }
1235         }
1236         if (np->phy_oui == PHY_OUI_VITESSE) {
1237                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1238                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1239                         return PHY_ERROR;
1240                 }
1241                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1242                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1243                         return PHY_ERROR;
1244                 }
1245                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1246                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1247                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1248                         return PHY_ERROR;
1249                 }
1250                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1251                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1252                 phy_reserved |= PHY_VITESSE_INIT3;
1253                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1254                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1255                         return PHY_ERROR;
1256                 }
1257                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1258                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1259                         return PHY_ERROR;
1260                 }
1261                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1262                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1263                         return PHY_ERROR;
1264                 }
1265                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1266                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1267                 phy_reserved |= PHY_VITESSE_INIT3;
1268                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1269                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1270                         return PHY_ERROR;
1271                 }
1272                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1273                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1274                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1275                         return PHY_ERROR;
1276                 }
1277                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1278                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1279                         return PHY_ERROR;
1280                 }
1281                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1282                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1283                         return PHY_ERROR;
1284                 }
1285                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1286                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1287                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1288                         return PHY_ERROR;
1289                 }
1290                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1291                 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1292                 phy_reserved |= PHY_VITESSE_INIT8;
1293                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1294                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1295                         return PHY_ERROR;
1296                 }
1297                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1298                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1299                         return PHY_ERROR;
1300                 }
1301                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1302                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1303                         return PHY_ERROR;
1304                 }
1305         }
1306         if (np->phy_oui == PHY_OUI_REALTEK) {
1307                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1308                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1309                         /* reset could have cleared these out, set them back */
1310                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1311                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1312                                 return PHY_ERROR;
1313                         }
1314                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1315                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1316                                 return PHY_ERROR;
1317                         }
1318                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1319                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1320                                 return PHY_ERROR;
1321                         }
1322                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1323                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1324                                 return PHY_ERROR;
1325                         }
1326                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1327                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1328                                 return PHY_ERROR;
1329                         }
1330                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1331                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1332                                 return PHY_ERROR;
1333                         }
1334                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1335                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1336                                 return PHY_ERROR;
1337                         }
1338                 }
1339                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1340                         if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
1341                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1342                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1343                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1344                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1345                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1346                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1347                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1348                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1349                                 phy_reserved |= PHY_REALTEK_INIT7;
1350                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1351                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1352                                         return PHY_ERROR;
1353                                 }
1354                         }
1355                         if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1356                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1357                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1358                                         return PHY_ERROR;
1359                                 }
1360                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1361                                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1362                                 phy_reserved |= PHY_REALTEK_INIT3;
1363                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
1364                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1365                                         return PHY_ERROR;
1366                                 }
1367                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1368                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1369                                         return PHY_ERROR;
1370                                 }
1371                         }
1372                 }
1373         }
1374
1375         /* some phys clear out pause advertisment on reset, set it back */
1376         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1377
1378         /* restart auto negotiation */
1379         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1380         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1381         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1382                 return PHY_ERROR;
1383         }
1384
1385         return 0;
1386 }
1387
1388 static void nv_start_rx(struct net_device *dev)
1389 {
1390         struct fe_priv *np = netdev_priv(dev);
1391         u8 __iomem *base = get_hwbase(dev);
1392         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1393
1394         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1395         /* Already running? Stop it. */
1396         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1397                 rx_ctrl &= ~NVREG_RCVCTL_START;
1398                 writel(rx_ctrl, base + NvRegReceiverControl);
1399                 pci_push(base);
1400         }
1401         writel(np->linkspeed, base + NvRegLinkSpeed);
1402         pci_push(base);
1403         rx_ctrl |= NVREG_RCVCTL_START;
1404         if (np->mac_in_use)
1405                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1406         writel(rx_ctrl, base + NvRegReceiverControl);
1407         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1408                                 dev->name, np->duplex, np->linkspeed);
1409         pci_push(base);
1410 }
1411
1412 static void nv_stop_rx(struct net_device *dev)
1413 {
1414         struct fe_priv *np = netdev_priv(dev);
1415         u8 __iomem *base = get_hwbase(dev);
1416         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1417
1418         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1419         if (!np->mac_in_use)
1420                 rx_ctrl &= ~NVREG_RCVCTL_START;
1421         else
1422                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1423         writel(rx_ctrl, base + NvRegReceiverControl);
1424         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1425                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1426                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1427
1428         udelay(NV_RXSTOP_DELAY2);
1429         if (!np->mac_in_use)
1430                 writel(0, base + NvRegLinkSpeed);
1431 }
1432
1433 static void nv_start_tx(struct net_device *dev)
1434 {
1435         struct fe_priv *np = netdev_priv(dev);
1436         u8 __iomem *base = get_hwbase(dev);
1437         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1438
1439         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1440         tx_ctrl |= NVREG_XMITCTL_START;
1441         if (np->mac_in_use)
1442                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1443         writel(tx_ctrl, base + NvRegTransmitterControl);
1444         pci_push(base);
1445 }
1446
1447 static void nv_stop_tx(struct net_device *dev)
1448 {
1449         struct fe_priv *np = netdev_priv(dev);
1450         u8 __iomem *base = get_hwbase(dev);
1451         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1452
1453         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1454         if (!np->mac_in_use)
1455                 tx_ctrl &= ~NVREG_XMITCTL_START;
1456         else
1457                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1458         writel(tx_ctrl, base + NvRegTransmitterControl);
1459         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1460                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1461                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1462
1463         udelay(NV_TXSTOP_DELAY2);
1464         if (!np->mac_in_use)
1465                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1466                        base + NvRegTransmitPoll);
1467 }
1468
1469 static void nv_start_rxtx(struct net_device *dev)
1470 {
1471         nv_start_rx(dev);
1472         nv_start_tx(dev);
1473 }
1474
1475 static void nv_stop_rxtx(struct net_device *dev)
1476 {
1477         nv_stop_rx(dev);
1478         nv_stop_tx(dev);
1479 }
1480
1481 static void nv_txrx_reset(struct net_device *dev)
1482 {
1483         struct fe_priv *np = netdev_priv(dev);
1484         u8 __iomem *base = get_hwbase(dev);
1485
1486         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1487         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1488         pci_push(base);
1489         udelay(NV_TXRX_RESET_DELAY);
1490         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1491         pci_push(base);
1492 }
1493
1494 static void nv_mac_reset(struct net_device *dev)
1495 {
1496         struct fe_priv *np = netdev_priv(dev);
1497         u8 __iomem *base = get_hwbase(dev);
1498         u32 temp1, temp2, temp3;
1499
1500         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1501
1502         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1503         pci_push(base);
1504
1505         /* save registers since they will be cleared on reset */
1506         temp1 = readl(base + NvRegMacAddrA);
1507         temp2 = readl(base + NvRegMacAddrB);
1508         temp3 = readl(base + NvRegTransmitPoll);
1509
1510         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1511         pci_push(base);
1512         udelay(NV_MAC_RESET_DELAY);
1513         writel(0, base + NvRegMacReset);
1514         pci_push(base);
1515         udelay(NV_MAC_RESET_DELAY);
1516
1517         /* restore saved registers */
1518         writel(temp1, base + NvRegMacAddrA);
1519         writel(temp2, base + NvRegMacAddrB);
1520         writel(temp3, base + NvRegTransmitPoll);
1521
1522         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1523         pci_push(base);
1524 }
1525
1526 static void nv_get_hw_stats(struct net_device *dev)
1527 {
1528         struct fe_priv *np = netdev_priv(dev);
1529         u8 __iomem *base = get_hwbase(dev);
1530
1531         np->estats.tx_bytes += readl(base + NvRegTxCnt);
1532         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1533         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1534         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1535         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1536         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1537         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1538         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1539         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1540         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1541         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1542         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1543         np->estats.rx_runt += readl(base + NvRegRxRunt);
1544         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1545         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1546         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1547         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1548         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1549         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1550         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1551         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1552         np->estats.rx_packets =
1553                 np->estats.rx_unicast +
1554                 np->estats.rx_multicast +
1555                 np->estats.rx_broadcast;
1556         np->estats.rx_errors_total =
1557                 np->estats.rx_crc_errors +
1558                 np->estats.rx_over_errors +
1559                 np->estats.rx_frame_error +
1560                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1561                 np->estats.rx_late_collision +
1562                 np->estats.rx_runt +
1563                 np->estats.rx_frame_too_long;
1564         np->estats.tx_errors_total =
1565                 np->estats.tx_late_collision +
1566                 np->estats.tx_fifo_errors +
1567                 np->estats.tx_carrier_errors +
1568                 np->estats.tx_excess_deferral +
1569                 np->estats.tx_retry_error;
1570
1571         if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1572                 np->estats.tx_deferral += readl(base + NvRegTxDef);
1573                 np->estats.tx_packets += readl(base + NvRegTxFrame);
1574                 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1575                 np->estats.tx_pause += readl(base + NvRegTxPause);
1576                 np->estats.rx_pause += readl(base + NvRegRxPause);
1577                 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1578         }
1579 }
1580
1581 /*
1582  * nv_get_stats: dev->get_stats function
1583  * Get latest stats value from the nic.
1584  * Called with read_lock(&dev_base_lock) held for read -
1585  * only synchronized against unregister_netdevice.
1586  */
1587 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1588 {
1589         struct fe_priv *np = netdev_priv(dev);
1590
1591         /* If the nic supports hw counters then retrieve latest values */
1592         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2)) {
1593                 nv_get_hw_stats(dev);
1594
1595                 /* copy to net_device stats */
1596                 dev->stats.tx_bytes = np->estats.tx_bytes;
1597                 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1598                 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1599                 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1600                 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1601                 dev->stats.rx_errors = np->estats.rx_errors_total;
1602                 dev->stats.tx_errors = np->estats.tx_errors_total;
1603         }
1604
1605         return &dev->stats;
1606 }
1607
1608 /*
1609  * nv_alloc_rx: fill rx ring entries.
1610  * Return 1 if the allocations for the skbs failed and the
1611  * rx engine is without Available descriptors
1612  */
1613 static int nv_alloc_rx(struct net_device *dev)
1614 {
1615         struct fe_priv *np = netdev_priv(dev);
1616         struct ring_desc* less_rx;
1617
1618         less_rx = np->get_rx.orig;
1619         if (less_rx-- == np->first_rx.orig)
1620                 less_rx = np->last_rx.orig;
1621
1622         while (np->put_rx.orig != less_rx) {
1623                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1624                 if (skb) {
1625                         np->put_rx_ctx->skb = skb;
1626                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1627                                                              skb->data,
1628                                                              skb_tailroom(skb),
1629                                                              PCI_DMA_FROMDEVICE);
1630                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1631                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1632                         wmb();
1633                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1634                         if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1635                                 np->put_rx.orig = np->first_rx.orig;
1636                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1637                                 np->put_rx_ctx = np->first_rx_ctx;
1638                 } else {
1639                         return 1;
1640                 }
1641         }
1642         return 0;
1643 }
1644
1645 static int nv_alloc_rx_optimized(struct net_device *dev)
1646 {
1647         struct fe_priv *np = netdev_priv(dev);
1648         struct ring_desc_ex* less_rx;
1649
1650         less_rx = np->get_rx.ex;
1651         if (less_rx-- == np->first_rx.ex)
1652                 less_rx = np->last_rx.ex;
1653
1654         while (np->put_rx.ex != less_rx) {
1655                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1656                 if (skb) {
1657                         np->put_rx_ctx->skb = skb;
1658                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1659                                                              skb->data,
1660                                                              skb_tailroom(skb),
1661                                                              PCI_DMA_FROMDEVICE);
1662                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1663                         np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1664                         np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1665                         wmb();
1666                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1667                         if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1668                                 np->put_rx.ex = np->first_rx.ex;
1669                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1670                                 np->put_rx_ctx = np->first_rx_ctx;
1671                 } else {
1672                         return 1;
1673                 }
1674         }
1675         return 0;
1676 }
1677
1678 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1679 #ifdef CONFIG_FORCEDETH_NAPI
1680 static void nv_do_rx_refill(unsigned long data)
1681 {
1682         struct net_device *dev = (struct net_device *) data;
1683         struct fe_priv *np = netdev_priv(dev);
1684
1685         /* Just reschedule NAPI rx processing */
1686         netif_rx_schedule(dev, &np->napi);
1687 }
1688 #else
1689 static void nv_do_rx_refill(unsigned long data)
1690 {
1691         struct net_device *dev = (struct net_device *) data;
1692         struct fe_priv *np = netdev_priv(dev);
1693         int retcode;
1694
1695         if (!using_multi_irqs(dev)) {
1696                 if (np->msi_flags & NV_MSI_X_ENABLED)
1697                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1698                 else
1699                         disable_irq(np->pci_dev->irq);
1700         } else {
1701                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1702         }
1703         if (!nv_optimized(np))
1704                 retcode = nv_alloc_rx(dev);
1705         else
1706                 retcode = nv_alloc_rx_optimized(dev);
1707         if (retcode) {
1708                 spin_lock_irq(&np->lock);
1709                 if (!np->in_shutdown)
1710                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1711                 spin_unlock_irq(&np->lock);
1712         }
1713         if (!using_multi_irqs(dev)) {
1714                 if (np->msi_flags & NV_MSI_X_ENABLED)
1715                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1716                 else
1717                         enable_irq(np->pci_dev->irq);
1718         } else {
1719                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1720         }
1721 }
1722 #endif
1723
1724 static void nv_init_rx(struct net_device *dev)
1725 {
1726         struct fe_priv *np = netdev_priv(dev);
1727         int i;
1728
1729         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1730
1731         if (!nv_optimized(np))
1732                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1733         else
1734                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1735         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1736         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1737
1738         for (i = 0; i < np->rx_ring_size; i++) {
1739                 if (!nv_optimized(np)) {
1740                         np->rx_ring.orig[i].flaglen = 0;
1741                         np->rx_ring.orig[i].buf = 0;
1742                 } else {
1743                         np->rx_ring.ex[i].flaglen = 0;
1744                         np->rx_ring.ex[i].txvlan = 0;
1745                         np->rx_ring.ex[i].bufhigh = 0;
1746                         np->rx_ring.ex[i].buflow = 0;
1747                 }
1748                 np->rx_skb[i].skb = NULL;
1749                 np->rx_skb[i].dma = 0;
1750         }
1751 }
1752
1753 static void nv_init_tx(struct net_device *dev)
1754 {
1755         struct fe_priv *np = netdev_priv(dev);
1756         int i;
1757
1758         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1759
1760         if (!nv_optimized(np))
1761                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1762         else
1763                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1764         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1765         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1766         np->tx_pkts_in_progress = 0;
1767         np->tx_change_owner = NULL;
1768         np->tx_end_flip = NULL;
1769
1770         for (i = 0; i < np->tx_ring_size; i++) {
1771                 if (!nv_optimized(np)) {
1772                         np->tx_ring.orig[i].flaglen = 0;
1773                         np->tx_ring.orig[i].buf = 0;
1774                 } else {
1775                         np->tx_ring.ex[i].flaglen = 0;
1776                         np->tx_ring.ex[i].txvlan = 0;
1777                         np->tx_ring.ex[i].bufhigh = 0;
1778                         np->tx_ring.ex[i].buflow = 0;
1779                 }
1780                 np->tx_skb[i].skb = NULL;
1781                 np->tx_skb[i].dma = 0;
1782                 np->tx_skb[i].dma_len = 0;
1783                 np->tx_skb[i].first_tx_desc = NULL;
1784                 np->tx_skb[i].next_tx_ctx = NULL;
1785         }
1786 }
1787
1788 static int nv_init_ring(struct net_device *dev)
1789 {
1790         struct fe_priv *np = netdev_priv(dev);
1791
1792         nv_init_tx(dev);
1793         nv_init_rx(dev);
1794
1795         if (!nv_optimized(np))
1796                 return nv_alloc_rx(dev);
1797         else
1798                 return nv_alloc_rx_optimized(dev);
1799 }
1800
1801 static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
1802 {
1803         struct fe_priv *np = netdev_priv(dev);
1804
1805         if (tx_skb->dma) {
1806                 pci_unmap_page(np->pci_dev, tx_skb->dma,
1807                                tx_skb->dma_len,
1808                                PCI_DMA_TODEVICE);
1809                 tx_skb->dma = 0;
1810         }
1811         if (tx_skb->skb) {
1812                 dev_kfree_skb_any(tx_skb->skb);
1813                 tx_skb->skb = NULL;
1814                 return 1;
1815         } else {
1816                 return 0;
1817         }
1818 }
1819
1820 static void nv_drain_tx(struct net_device *dev)
1821 {
1822         struct fe_priv *np = netdev_priv(dev);
1823         unsigned int i;
1824
1825         for (i = 0; i < np->tx_ring_size; i++) {
1826                 if (!nv_optimized(np)) {
1827                         np->tx_ring.orig[i].flaglen = 0;
1828                         np->tx_ring.orig[i].buf = 0;
1829                 } else {
1830                         np->tx_ring.ex[i].flaglen = 0;
1831                         np->tx_ring.ex[i].txvlan = 0;
1832                         np->tx_ring.ex[i].bufhigh = 0;
1833                         np->tx_ring.ex[i].buflow = 0;
1834                 }
1835                 if (nv_release_txskb(dev, &np->tx_skb[i]))
1836                         dev->stats.tx_dropped++;
1837                 np->tx_skb[i].dma = 0;
1838                 np->tx_skb[i].dma_len = 0;
1839                 np->tx_skb[i].first_tx_desc = NULL;
1840                 np->tx_skb[i].next_tx_ctx = NULL;
1841         }
1842         np->tx_pkts_in_progress = 0;
1843         np->tx_change_owner = NULL;
1844         np->tx_end_flip = NULL;
1845 }
1846
1847 static void nv_drain_rx(struct net_device *dev)
1848 {
1849         struct fe_priv *np = netdev_priv(dev);
1850         int i;
1851
1852         for (i = 0; i < np->rx_ring_size; i++) {
1853                 if (!nv_optimized(np)) {
1854                         np->rx_ring.orig[i].flaglen = 0;
1855                         np->rx_ring.orig[i].buf = 0;
1856                 } else {
1857                         np->rx_ring.ex[i].flaglen = 0;
1858                         np->rx_ring.ex[i].txvlan = 0;
1859                         np->rx_ring.ex[i].bufhigh = 0;
1860                         np->rx_ring.ex[i].buflow = 0;
1861                 }
1862                 wmb();
1863                 if (np->rx_skb[i].skb) {
1864                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1865                                          (skb_end_pointer(np->rx_skb[i].skb) -
1866                                           np->rx_skb[i].skb->data),
1867                                          PCI_DMA_FROMDEVICE);
1868                         dev_kfree_skb(np->rx_skb[i].skb);
1869                         np->rx_skb[i].skb = NULL;
1870                 }
1871         }
1872 }
1873
1874 static void nv_drain_rxtx(struct net_device *dev)
1875 {
1876         nv_drain_tx(dev);
1877         nv_drain_rx(dev);
1878 }
1879
1880 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1881 {
1882         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1883 }
1884
1885 static void nv_legacybackoff_reseed(struct net_device *dev)
1886 {
1887         u8 __iomem *base = get_hwbase(dev);
1888         u32 reg;
1889         u32 low;
1890         int tx_status = 0;
1891
1892         reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
1893         get_random_bytes(&low, sizeof(low));
1894         reg |= low & NVREG_SLOTTIME_MASK;
1895
1896         /* Need to stop tx before change takes effect.
1897          * Caller has already gained np->lock.
1898          */
1899         tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
1900         if (tx_status)
1901                 nv_stop_tx(dev);
1902         nv_stop_rx(dev);
1903         writel(reg, base + NvRegSlotTime);
1904         if (tx_status)
1905                 nv_start_tx(dev);
1906         nv_start_rx(dev);
1907 }
1908
1909 /* Gear Backoff Seeds */
1910 #define BACKOFF_SEEDSET_ROWS    8
1911 #define BACKOFF_SEEDSET_LFSRS   15
1912
1913 /* Known Good seed sets */
1914 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
1915     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
1916     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
1917     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
1918     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
1919     {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
1920     {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
1921     {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800,  84},
1922     {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
1923
1924 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
1925     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
1926     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
1927     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
1928     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
1929     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
1930     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
1931     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
1932     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
1933
1934 static void nv_gear_backoff_reseed(struct net_device *dev)
1935 {
1936         u8 __iomem *base = get_hwbase(dev);
1937         u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
1938         u32 temp, seedset, combinedSeed;
1939         int i;
1940
1941         /* Setup seed for free running LFSR */
1942         /* We are going to read the time stamp counter 3 times
1943            and swizzle bits around to increase randomness */
1944         get_random_bytes(&miniseed1, sizeof(miniseed1));
1945         miniseed1 &= 0x0fff;
1946         if (miniseed1 == 0)
1947                 miniseed1 = 0xabc;
1948
1949         get_random_bytes(&miniseed2, sizeof(miniseed2));
1950         miniseed2 &= 0x0fff;
1951         if (miniseed2 == 0)
1952                 miniseed2 = 0xabc;
1953         miniseed2_reversed =
1954                 ((miniseed2 & 0xF00) >> 8) |
1955                  (miniseed2 & 0x0F0) |
1956                  ((miniseed2 & 0x00F) << 8);
1957
1958         get_random_bytes(&miniseed3, sizeof(miniseed3));
1959         miniseed3 &= 0x0fff;
1960         if (miniseed3 == 0)
1961                 miniseed3 = 0xabc;
1962         miniseed3_reversed =
1963                 ((miniseed3 & 0xF00) >> 8) |
1964                  (miniseed3 & 0x0F0) |
1965                  ((miniseed3 & 0x00F) << 8);
1966
1967         combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
1968                        (miniseed2 ^ miniseed3_reversed);
1969
1970         /* Seeds can not be zero */
1971         if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
1972                 combinedSeed |= 0x08;
1973         if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
1974                 combinedSeed |= 0x8000;
1975
1976         /* No need to disable tx here */
1977         temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
1978         temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
1979         temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
1980         writel(temp,base + NvRegBackOffControl);
1981
1982         /* Setup seeds for all gear LFSRs. */
1983         get_random_bytes(&seedset, sizeof(seedset));
1984         seedset = seedset % BACKOFF_SEEDSET_ROWS;
1985         for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++)
1986         {
1987                 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
1988                 temp |= main_seedset[seedset][i-1] & 0x3ff;
1989                 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
1990                 writel(temp, base + NvRegBackOffControl);
1991         }
1992 }
1993
1994 /*
1995  * nv_start_xmit: dev->hard_start_xmit function
1996  * Called with netif_tx_lock held.
1997  */
1998 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1999 {
2000         struct fe_priv *np = netdev_priv(dev);
2001         u32 tx_flags = 0;
2002         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2003         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2004         unsigned int i;
2005         u32 offset = 0;
2006         u32 bcnt;
2007         u32 size = skb->len-skb->data_len;
2008         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2009         u32 empty_slots;
2010         struct ring_desc* put_tx;
2011         struct ring_desc* start_tx;
2012         struct ring_desc* prev_tx;
2013         struct nv_skb_map* prev_tx_ctx;
2014         unsigned long flags;
2015
2016         /* add fragments to entries count */
2017         for (i = 0; i < fragments; i++) {
2018                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2019                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2020         }
2021
2022         empty_slots = nv_get_empty_tx_slots(np);
2023         if (unlikely(empty_slots <= entries)) {
2024                 spin_lock_irqsave(&np->lock, flags);
2025                 netif_stop_queue(dev);
2026                 np->tx_stop = 1;
2027                 spin_unlock_irqrestore(&np->lock, flags);
2028                 return NETDEV_TX_BUSY;
2029         }
2030
2031         start_tx = put_tx = np->put_tx.orig;
2032
2033         /* setup the header buffer */
2034         do {
2035                 prev_tx = put_tx;
2036                 prev_tx_ctx = np->put_tx_ctx;
2037                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2038                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2039                                                 PCI_DMA_TODEVICE);
2040                 np->put_tx_ctx->dma_len = bcnt;
2041                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2042                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2043
2044                 tx_flags = np->tx_flags;
2045                 offset += bcnt;
2046                 size -= bcnt;
2047                 if (unlikely(put_tx++ == np->last_tx.orig))
2048                         put_tx = np->first_tx.orig;
2049                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2050                         np->put_tx_ctx = np->first_tx_ctx;
2051         } while (size);
2052
2053         /* setup the fragments */
2054         for (i = 0; i < fragments; i++) {
2055                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2056                 u32 size = frag->size;
2057                 offset = 0;
2058
2059                 do {
2060                         prev_tx = put_tx;
2061                         prev_tx_ctx = np->put_tx_ctx;
2062                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2063                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2064                                                            PCI_DMA_TODEVICE);
2065                         np->put_tx_ctx->dma_len = bcnt;
2066                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2067                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2068
2069                         offset += bcnt;
2070                         size -= bcnt;
2071                         if (unlikely(put_tx++ == np->last_tx.orig))
2072                                 put_tx = np->first_tx.orig;
2073                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2074                                 np->put_tx_ctx = np->first_tx_ctx;
2075                 } while (size);
2076         }
2077
2078         /* set last fragment flag  */
2079         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2080
2081         /* save skb in this slot's context area */
2082         prev_tx_ctx->skb = skb;
2083
2084         if (skb_is_gso(skb))
2085                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2086         else
2087                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2088                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2089
2090         spin_lock_irqsave(&np->lock, flags);
2091
2092         /* set tx flags */
2093         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2094         np->put_tx.orig = put_tx;
2095
2096         spin_unlock_irqrestore(&np->lock, flags);
2097
2098         dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
2099                 dev->name, entries, tx_flags_extra);
2100         {
2101                 int j;
2102                 for (j=0; j<64; j++) {
2103                         if ((j%16) == 0)
2104                                 dprintk("\n%03x:", j);
2105                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2106                 }
2107                 dprintk("\n");
2108         }
2109
2110         dev->trans_start = jiffies;
2111         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2112         return NETDEV_TX_OK;
2113 }
2114
2115 static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
2116 {
2117         struct fe_priv *np = netdev_priv(dev);
2118         u32 tx_flags = 0;
2119         u32 tx_flags_extra;
2120         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2121         unsigned int i;
2122         u32 offset = 0;
2123         u32 bcnt;
2124         u32 size = skb->len-skb->data_len;
2125         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2126         u32 empty_slots;
2127         struct ring_desc_ex* put_tx;
2128         struct ring_desc_ex* start_tx;
2129         struct ring_desc_ex* prev_tx;
2130         struct nv_skb_map* prev_tx_ctx;
2131         struct nv_skb_map* start_tx_ctx;
2132         unsigned long flags;
2133
2134         /* add fragments to entries count */
2135         for (i = 0; i < fragments; i++) {
2136                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2137                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2138         }
2139
2140         empty_slots = nv_get_empty_tx_slots(np);
2141         if (unlikely(empty_slots <= entries)) {
2142                 spin_lock_irqsave(&np->lock, flags);
2143                 netif_stop_queue(dev);
2144                 np->tx_stop = 1;
2145                 spin_unlock_irqrestore(&np->lock, flags);
2146                 return NETDEV_TX_BUSY;
2147         }
2148
2149         start_tx = put_tx = np->put_tx.ex;
2150         start_tx_ctx = np->put_tx_ctx;
2151
2152         /* setup the header buffer */
2153         do {
2154                 prev_tx = put_tx;
2155                 prev_tx_ctx = np->put_tx_ctx;
2156                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2157                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2158                                                 PCI_DMA_TODEVICE);
2159                 np->put_tx_ctx->dma_len = bcnt;
2160                 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2161                 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2162                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2163
2164                 tx_flags = NV_TX2_VALID;
2165                 offset += bcnt;
2166                 size -= bcnt;
2167                 if (unlikely(put_tx++ == np->last_tx.ex))
2168                         put_tx = np->first_tx.ex;
2169                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2170                         np->put_tx_ctx = np->first_tx_ctx;
2171         } while (size);
2172
2173         /* setup the fragments */
2174         for (i = 0; i < fragments; i++) {
2175                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2176                 u32 size = frag->size;
2177                 offset = 0;
2178
2179                 do {
2180                         prev_tx = put_tx;
2181                         prev_tx_ctx = np->put_tx_ctx;
2182                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2183                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2184                                                            PCI_DMA_TODEVICE);
2185                         np->put_tx_ctx->dma_len = bcnt;
2186                         put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2187                         put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2188                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2189
2190                         offset += bcnt;
2191                         size -= bcnt;
2192                         if (unlikely(put_tx++ == np->last_tx.ex))
2193                                 put_tx = np->first_tx.ex;
2194                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2195                                 np->put_tx_ctx = np->first_tx_ctx;
2196                 } while (size);
2197         }
2198
2199         /* set last fragment flag  */
2200         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2201
2202         /* save skb in this slot's context area */
2203         prev_tx_ctx->skb = skb;
2204
2205         if (skb_is_gso(skb))
2206                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2207         else
2208                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2209                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2210
2211         /* vlan tag */
2212         if (likely(!np->vlangrp)) {
2213                 start_tx->txvlan = 0;
2214         } else {
2215                 if (vlan_tx_tag_present(skb))
2216                         start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
2217                 else
2218                         start_tx->txvlan = 0;
2219         }
2220
2221         spin_lock_irqsave(&np->lock, flags);
2222
2223         if (np->tx_limit) {
2224                 /* Limit the number of outstanding tx. Setup all fragments, but
2225                  * do not set the VALID bit on the first descriptor. Save a pointer
2226                  * to that descriptor and also for next skb_map element.
2227                  */
2228
2229                 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2230                         if (!np->tx_change_owner)
2231                                 np->tx_change_owner = start_tx_ctx;
2232
2233                         /* remove VALID bit */
2234                         tx_flags &= ~NV_TX2_VALID;
2235                         start_tx_ctx->first_tx_desc = start_tx;
2236                         start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2237                         np->tx_end_flip = np->put_tx_ctx;
2238                 } else {
2239                         np->tx_pkts_in_progress++;
2240                 }
2241         }
2242
2243         /* set tx flags */
2244         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2245         np->put_tx.ex = put_tx;
2246
2247         spin_unlock_irqrestore(&np->lock, flags);
2248
2249         dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2250                 dev->name, entries, tx_flags_extra);
2251         {
2252                 int j;
2253                 for (j=0; j<64; j++) {
2254                         if ((j%16) == 0)
2255                                 dprintk("\n%03x:", j);
2256                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2257                 }
2258                 dprintk("\n");
2259         }
2260
2261         dev->trans_start = jiffies;
2262         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2263         return NETDEV_TX_OK;
2264 }
2265
2266 static inline void nv_tx_flip_ownership(struct net_device *dev)
2267 {
2268         struct fe_priv *np = netdev_priv(dev);
2269
2270         np->tx_pkts_in_progress--;
2271         if (np->tx_change_owner) {
2272                 np->tx_change_owner->first_tx_desc->flaglen |=
2273                         cpu_to_le32(NV_TX2_VALID);
2274                 np->tx_pkts_in_progress++;
2275
2276                 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2277                 if (np->tx_change_owner == np->tx_end_flip)
2278                         np->tx_change_owner = NULL;
2279
2280                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2281         }
2282 }
2283
2284 /*
2285  * nv_tx_done: check for completed packets, release the skbs.
2286  *
2287  * Caller must own np->lock.
2288  */
2289 static void nv_tx_done(struct net_device *dev)
2290 {
2291         struct fe_priv *np = netdev_priv(dev);
2292         u32 flags;
2293         struct ring_desc* orig_get_tx = np->get_tx.orig;
2294
2295         while ((np->get_tx.orig != np->put_tx.orig) &&
2296                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID)) {
2297
2298                 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2299                                         dev->name, flags);
2300
2301                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2302                                np->get_tx_ctx->dma_len,
2303                                PCI_DMA_TODEVICE);
2304                 np->get_tx_ctx->dma = 0;
2305
2306                 if (np->desc_ver == DESC_VER_1) {
2307                         if (flags & NV_TX_LASTPACKET) {
2308                                 if (flags & NV_TX_ERROR) {
2309                                         if (flags & NV_TX_UNDERFLOW)
2310                                                 dev->stats.tx_fifo_errors++;
2311                                         if (flags & NV_TX_CARRIERLOST)
2312                                                 dev->stats.tx_carrier_errors++;
2313                                         if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2314                                                 nv_legacybackoff_reseed(dev);
2315                                         dev->stats.tx_errors++;
2316                                 } else {
2317                                         dev->stats.tx_packets++;
2318                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2319                                 }
2320                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2321                                 np->get_tx_ctx->skb = NULL;
2322                         }
2323                 } else {
2324                         if (flags & NV_TX2_LASTPACKET) {
2325                                 if (flags & NV_TX2_ERROR) {
2326                                         if (flags & NV_TX2_UNDERFLOW)
2327                                                 dev->stats.tx_fifo_errors++;
2328                                         if (flags & NV_TX2_CARRIERLOST)
2329                                                 dev->stats.tx_carrier_errors++;
2330                                         if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2331                                                 nv_legacybackoff_reseed(dev);
2332                                         dev->stats.tx_errors++;
2333                                 } else {
2334                                         dev->stats.tx_packets++;
2335                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2336                                 }
2337                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2338                                 np->get_tx_ctx->skb = NULL;
2339                         }
2340                 }
2341                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2342                         np->get_tx.orig = np->first_tx.orig;
2343                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2344                         np->get_tx_ctx = np->first_tx_ctx;
2345         }
2346         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2347                 np->tx_stop = 0;
2348                 netif_wake_queue(dev);
2349         }
2350 }
2351
2352 static void nv_tx_done_optimized(struct net_device *dev, int limit)
2353 {
2354         struct fe_priv *np = netdev_priv(dev);
2355         u32 flags;
2356         struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
2357
2358         while ((np->get_tx.ex != np->put_tx.ex) &&
2359                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
2360                (limit-- > 0)) {
2361
2362                 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2363                                         dev->name, flags);
2364
2365                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2366                                np->get_tx_ctx->dma_len,
2367                                PCI_DMA_TODEVICE);
2368                 np->get_tx_ctx->dma = 0;
2369
2370                 if (flags & NV_TX2_LASTPACKET) {
2371                         if (!(flags & NV_TX2_ERROR))
2372                                 dev->stats.tx_packets++;
2373                         else {
2374                                 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2375                                         if (np->driver_data & DEV_HAS_GEAR_MODE)
2376                                                 nv_gear_backoff_reseed(dev);
2377                                         else
2378                                                 nv_legacybackoff_reseed(dev);
2379                                 }
2380                         }
2381
2382                         dev_kfree_skb_any(np->get_tx_ctx->skb);
2383                         np->get_tx_ctx->skb = NULL;
2384
2385                         if (np->tx_limit) {
2386                                 nv_tx_flip_ownership(dev);
2387                         }
2388                 }
2389                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2390                         np->get_tx.ex = np->first_tx.ex;
2391                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2392                         np->get_tx_ctx = np->first_tx_ctx;
2393         }
2394         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2395                 np->tx_stop = 0;
2396                 netif_wake_queue(dev);
2397         }
2398 }
2399
2400 /*
2401  * nv_tx_timeout: dev->tx_timeout function
2402  * Called with netif_tx_lock held.
2403  */
2404 static void nv_tx_timeout(struct net_device *dev)
2405 {
2406         struct fe_priv *np = netdev_priv(dev);
2407         u8 __iomem *base = get_hwbase(dev);
2408         u32 status;
2409
2410         if (np->msi_flags & NV_MSI_X_ENABLED)
2411                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2412         else
2413                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2414
2415         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
2416
2417         {
2418                 int i;
2419
2420                 printk(KERN_INFO "%s: Ring at %lx\n",
2421                        dev->name, (unsigned long)np->ring_addr);
2422                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
2423                 for (i=0;i<=np->register_size;i+= 32) {
2424                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2425                                         i,
2426                                         readl(base + i + 0), readl(base + i + 4),
2427                                         readl(base + i + 8), readl(base + i + 12),
2428                                         readl(base + i + 16), readl(base + i + 20),
2429                                         readl(base + i + 24), readl(base + i + 28));
2430                 }
2431                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
2432                 for (i=0;i<np->tx_ring_size;i+= 4) {
2433                         if (!nv_optimized(np)) {
2434                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2435                                        i,
2436                                        le32_to_cpu(np->tx_ring.orig[i].buf),
2437                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
2438                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
2439                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2440                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
2441                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2442                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
2443                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2444                         } else {
2445                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2446                                        i,
2447                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2448                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
2449                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
2450                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2451                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2452                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2453                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2454                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2455                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2456                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2457                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2458                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2459                         }
2460                 }
2461         }
2462
2463         spin_lock_irq(&np->lock);
2464
2465         /* 1) stop tx engine */
2466         nv_stop_tx(dev);
2467
2468         /* 2) check that the packets were not sent already: */
2469         if (!nv_optimized(np))
2470                 nv_tx_done(dev);
2471         else
2472                 nv_tx_done_optimized(dev, np->tx_ring_size);
2473
2474         /* 3) if there are dead entries: clear everything */
2475         if (np->get_tx_ctx != np->put_tx_ctx) {
2476                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
2477                 nv_drain_tx(dev);
2478                 nv_init_tx(dev);
2479                 setup_hw_rings(dev, NV_SETUP_TX_RING);
2480         }
2481
2482         netif_wake_queue(dev);
2483
2484         /* 4) restart tx engine */
2485         nv_start_tx(dev);
2486         spin_unlock_irq(&np->lock);
2487 }
2488
2489 /*
2490  * Called when the nic notices a mismatch between the actual data len on the
2491  * wire and the len indicated in the 802 header
2492  */
2493 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2494 {
2495         int hdrlen;     /* length of the 802 header */
2496         int protolen;   /* length as stored in the proto field */
2497
2498         /* 1) calculate len according to header */
2499         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2500                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2501                 hdrlen = VLAN_HLEN;
2502         } else {
2503                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2504                 hdrlen = ETH_HLEN;
2505         }
2506         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2507                                 dev->name, datalen, protolen, hdrlen);
2508         if (protolen > ETH_DATA_LEN)
2509                 return datalen; /* Value in proto field not a len, no checks possible */
2510
2511         protolen += hdrlen;
2512         /* consistency checks: */
2513         if (datalen > ETH_ZLEN) {
2514                 if (datalen >= protolen) {
2515                         /* more data on wire than in 802 header, trim of
2516                          * additional data.
2517                          */
2518                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2519                                         dev->name, protolen);
2520                         return protolen;
2521                 } else {
2522                         /* less data on wire than mentioned in header.
2523                          * Discard the packet.
2524                          */
2525                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2526                                         dev->name);
2527                         return -1;
2528                 }
2529         } else {
2530                 /* short packet. Accept only if 802 values are also short */
2531                 if (protolen > ETH_ZLEN) {
2532                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2533                                         dev->name);
2534                         return -1;
2535                 }
2536                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2537                                 dev->name, datalen);
2538                 return datalen;
2539         }
2540 }
2541
2542 static int nv_rx_process(struct net_device *dev, int limit)
2543 {
2544         struct fe_priv *np = netdev_priv(dev);
2545         u32 flags;
2546         int rx_work = 0;
2547         struct sk_buff *skb;
2548         int len;
2549
2550         while((np->get_rx.orig != np->put_rx.orig) &&
2551               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2552                 (rx_work < limit)) {
2553
2554                 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2555                                         dev->name, flags);
2556
2557                 /*
2558                  * the packet is for us - immediately tear down the pci mapping.
2559                  * TODO: check if a prefetch of the first cacheline improves
2560                  * the performance.
2561                  */
2562                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2563                                 np->get_rx_ctx->dma_len,
2564                                 PCI_DMA_FROMDEVICE);
2565                 skb = np->get_rx_ctx->skb;
2566                 np->get_rx_ctx->skb = NULL;
2567
2568                 {
2569                         int j;
2570                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2571                         for (j=0; j<64; j++) {
2572                                 if ((j%16) == 0)
2573                                         dprintk("\n%03x:", j);
2574                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2575                         }
2576                         dprintk("\n");
2577                 }
2578                 /* look at what we actually got: */
2579                 if (np->desc_ver == DESC_VER_1) {
2580                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2581                                 len = flags & LEN_MASK_V1;
2582                                 if (unlikely(flags & NV_RX_ERROR)) {
2583                                         if (flags & NV_RX_ERROR4) {
2584                                                 len = nv_getlen(dev, skb->data, len);
2585                                                 if (len < 0) {
2586                                                         dev->stats.rx_errors++;
2587                                                         dev_kfree_skb(skb);
2588                                                         goto next_pkt;
2589                                                 }
2590                                         }
2591                                         /* framing errors are soft errors */
2592                                         else if (flags & NV_RX_FRAMINGERR) {
2593                                                 if (flags & NV_RX_SUBSTRACT1) {
2594                                                         len--;
2595                                                 }
2596                                         }
2597                                         /* the rest are hard errors */
2598                                         else {
2599                                                 if (flags & NV_RX_MISSEDFRAME)
2600                                                         dev->stats.rx_missed_errors++;
2601                                                 if (flags & NV_RX_CRCERR)
2602                                                         dev->stats.rx_crc_errors++;
2603                                                 if (flags & NV_RX_OVERFLOW)
2604                                                         dev->stats.rx_over_errors++;
2605                                                 dev->stats.rx_errors++;
2606                                                 dev_kfree_skb(skb);
2607                                                 goto next_pkt;
2608                                         }
2609                                 }
2610                         } else {
2611                                 dev_kfree_skb(skb);
2612                                 goto next_pkt;
2613                         }
2614                 } else {
2615                         if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2616                                 len = flags & LEN_MASK_V2;
2617                                 if (unlikely(flags & NV_RX2_ERROR)) {
2618                                         if (flags & NV_RX2_ERROR4) {
2619                                                 len = nv_getlen(dev, skb->data, len);
2620                                                 if (len < 0) {
2621                                                         dev->stats.rx_errors++;
2622                                                         dev_kfree_skb(skb);
2623                                                         goto next_pkt;
2624                                                 }
2625                                         }
2626                                         /* framing errors are soft errors */
2627                                         else if (flags & NV_RX2_FRAMINGERR) {
2628                                                 if (flags & NV_RX2_SUBSTRACT1) {
2629                                                         len--;
2630                                                 }
2631                                         }
2632                                         /* the rest are hard errors */
2633                                         else {
2634                                                 if (flags & NV_RX2_CRCERR)
2635                                                         dev->stats.rx_crc_errors++;
2636                                                 if (flags & NV_RX2_OVERFLOW)
2637                                                         dev->stats.rx_over_errors++;
2638                                                 dev->stats.rx_errors++;
2639                                                 dev_kfree_skb(skb);
2640                                                 goto next_pkt;
2641                                         }
2642                                 }
2643                                 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2644                                     ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2645                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2646                         } else {
2647                                 dev_kfree_skb(skb);
2648                                 goto next_pkt;
2649                         }
2650                 }
2651                 /* got a valid packet - forward it to the network core */
2652                 skb_put(skb, len);
2653                 skb->protocol = eth_type_trans(skb, dev);
2654                 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2655                                         dev->name, len, skb->protocol);
2656 #ifdef CONFIG_FORCEDETH_NAPI
2657                 netif_receive_skb(skb);
2658 #else
2659                 netif_rx(skb);
2660 #endif
2661                 dev->last_rx = jiffies;
2662                 dev->stats.rx_packets++;
2663                 dev->stats.rx_bytes += len;
2664 next_pkt:
2665                 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2666                         np->get_rx.orig = np->first_rx.orig;
2667                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2668                         np->get_rx_ctx = np->first_rx_ctx;
2669
2670                 rx_work++;
2671         }
2672
2673         return rx_work;
2674 }
2675
2676 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2677 {
2678         struct fe_priv *np = netdev_priv(dev);
2679         u32 flags;
2680         u32 vlanflags = 0;
2681         int rx_work = 0;
2682         struct sk_buff *skb;
2683         int len;
2684
2685         while((np->get_rx.ex != np->put_rx.ex) &&
2686               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2687               (rx_work < limit)) {
2688
2689                 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2690                                         dev->name, flags);
2691
2692                 /*
2693                  * the packet is for us - immediately tear down the pci mapping.
2694                  * TODO: check if a prefetch of the first cacheline improves
2695                  * the performance.
2696                  */
2697                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2698                                 np->get_rx_ctx->dma_len,
2699                                 PCI_DMA_FROMDEVICE);
2700                 skb = np->get_rx_ctx->skb;
2701                 np->get_rx_ctx->skb = NULL;
2702
2703                 {
2704                         int j;
2705                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2706                         for (j=0; j<64; j++) {
2707                                 if ((j%16) == 0)
2708                                         dprintk("\n%03x:", j);
2709                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2710                         }
2711                         dprintk("\n");
2712                 }
2713                 /* look at what we actually got: */
2714                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2715                         len = flags & LEN_MASK_V2;
2716                         if (unlikely(flags & NV_RX2_ERROR)) {
2717                                 if (flags & NV_RX2_ERROR4) {
2718                                         len = nv_getlen(dev, skb->data, len);
2719                                         if (len < 0) {
2720                                                 dev_kfree_skb(skb);
2721                                                 goto next_pkt;
2722                                         }
2723                                 }
2724                                 /* framing errors are soft errors */
2725                                 else if (flags & NV_RX2_FRAMINGERR) {
2726                                         if (flags & NV_RX2_SUBSTRACT1) {
2727                                                 len--;
2728                                         }
2729                                 }
2730                                 /* the rest are hard errors */
2731                                 else {
2732                                         dev_kfree_skb(skb);
2733                                         goto next_pkt;
2734                                 }
2735                         }
2736
2737                         if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2738                             ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2739                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2740
2741                         /* got a valid packet - forward it to the network core */
2742                         skb_put(skb, len);
2743                         skb->protocol = eth_type_trans(skb, dev);
2744                         prefetch(skb->data);
2745
2746                         dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2747                                 dev->name, len, skb->protocol);
2748
2749                         if (likely(!np->vlangrp)) {
2750 #ifdef CONFIG_FORCEDETH_NAPI
2751                                 netif_receive_skb(skb);
2752 #else
2753                                 netif_rx(skb);
2754 #endif
2755                         } else {
2756                                 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2757                                 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2758 #ifdef CONFIG_FORCEDETH_NAPI
2759                                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
2760                                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
2761 #else
2762                                         vlan_hwaccel_rx(skb, np->vlangrp,
2763                                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
2764 #endif
2765                                 } else {
2766 #ifdef CONFIG_FORCEDETH_NAPI
2767                                         netif_receive_skb(skb);
2768 #else
2769                                         netif_rx(skb);
2770 #endif
2771                                 }
2772                         }
2773
2774                         dev->last_rx = jiffies;
2775                         dev->stats.rx_packets++;
2776                         dev->stats.rx_bytes += len;
2777                 } else {
2778                         dev_kfree_skb(skb);
2779                 }
2780 next_pkt:
2781                 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2782                         np->get_rx.ex = np->first_rx.ex;
2783                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2784                         np->get_rx_ctx = np->first_rx_ctx;
2785
2786                 rx_work++;
2787         }
2788
2789         return rx_work;
2790 }
2791
2792 static void set_bufsize(struct net_device *dev)
2793 {
2794         struct fe_priv *np = netdev_priv(dev);
2795
2796         if (dev->mtu <= ETH_DATA_LEN)
2797                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2798         else
2799                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2800 }
2801
2802 /*
2803  * nv_change_mtu: dev->change_mtu function
2804  * Called with dev_base_lock held for read.
2805  */
2806 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2807 {
2808         struct fe_priv *np = netdev_priv(dev);
2809         int old_mtu;
2810
2811         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2812                 return -EINVAL;
2813
2814         old_mtu = dev->mtu;
2815         dev->mtu = new_mtu;
2816
2817         /* return early if the buffer sizes will not change */
2818         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2819                 return 0;
2820         if (old_mtu == new_mtu)
2821                 return 0;
2822
2823         /* synchronized against open : rtnl_lock() held by caller */
2824         if (netif_running(dev)) {
2825                 u8 __iomem *base = get_hwbase(dev);
2826                 /*
2827                  * It seems that the nic preloads valid ring entries into an
2828                  * internal buffer. The procedure for flushing everything is
2829                  * guessed, there is probably a simpler approach.
2830                  * Changing the MTU is a rare event, it shouldn't matter.
2831                  */
2832                 nv_disable_irq(dev);
2833                 netif_tx_lock_bh(dev);
2834                 netif_addr_lock(dev);
2835                 spin_lock(&np->lock);
2836                 /* stop engines */
2837                 nv_stop_rxtx(dev);
2838                 nv_txrx_reset(dev);
2839                 /* drain rx queue */
2840                 nv_drain_rxtx(dev);
2841                 /* reinit driver view of the rx queue */
2842                 set_bufsize(dev);
2843                 if (nv_init_ring(dev)) {
2844                         if (!np->in_shutdown)
2845                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2846                 }
2847                 /* reinit nic view of the rx queue */
2848                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2849                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2850                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2851                         base + NvRegRingSizes);
2852                 pci_push(base);
2853                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2854                 pci_push(base);
2855
2856                 /* restart rx engine */
2857                 nv_start_rxtx(dev);
2858                 spin_unlock(&np->lock);
2859                 netif_addr_unlock(dev);
2860                 netif_tx_unlock_bh(dev);
2861                 nv_enable_irq(dev);
2862         }
2863         return 0;
2864 }
2865
2866 static void nv_copy_mac_to_hw(struct net_device *dev)
2867 {
2868         u8 __iomem *base = get_hwbase(dev);
2869         u32 mac[2];
2870
2871         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2872                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2873         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2874
2875         writel(mac[0], base + NvRegMacAddrA);
2876         writel(mac[1], base + NvRegMacAddrB);
2877 }
2878
2879 /*
2880  * nv_set_mac_address: dev->set_mac_address function
2881  * Called with rtnl_lock() held.
2882  */
2883 static int nv_set_mac_address(struct net_device *dev, void *addr)
2884 {
2885         struct fe_priv *np = netdev_priv(dev);
2886         struct sockaddr *macaddr = (struct sockaddr*)addr;
2887
2888         if (!is_valid_ether_addr(macaddr->sa_data))
2889                 return -EADDRNOTAVAIL;
2890
2891         /* synchronized against open : rtnl_lock() held by caller */
2892         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2893
2894         if (netif_running(dev)) {
2895                 netif_tx_lock_bh(dev);
2896                 netif_addr_lock(dev);
2897                 spin_lock_irq(&np->lock);
2898
2899                 /* stop rx engine */
2900                 nv_stop_rx(dev);
2901
2902                 /* set mac address */
2903                 nv_copy_mac_to_hw(dev);
2904
2905                 /* restart rx engine */
2906                 nv_start_rx(dev);
2907                 spin_unlock_irq(&np->lock);
2908                 netif_addr_unlock(dev);
2909                 netif_tx_unlock_bh(dev);
2910         } else {
2911                 nv_copy_mac_to_hw(dev);
2912         }
2913         return 0;
2914 }
2915
2916 /*
2917  * nv_set_multicast: dev->set_multicast function
2918  * Called with netif_tx_lock held.
2919  */
2920 static void nv_set_multicast(struct net_device *dev)
2921 {
2922         struct fe_priv *np = netdev_priv(dev);
2923         u8 __iomem *base = get_hwbase(dev);
2924         u32 addr[2];
2925         u32 mask[2];
2926         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2927
2928         memset(addr, 0, sizeof(addr));
2929         memset(mask, 0, sizeof(mask));
2930
2931         if (dev->flags & IFF_PROMISC) {
2932                 pff |= NVREG_PFF_PROMISC;
2933         } else {
2934                 pff |= NVREG_PFF_MYADDR;
2935
2936                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2937                         u32 alwaysOff[2];
2938                         u32 alwaysOn[2];
2939
2940                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2941                         if (dev->flags & IFF_ALLMULTI) {
2942                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2943                         } else {
2944                                 struct dev_mc_list *walk;
2945
2946                                 walk = dev->mc_list;
2947                                 while (walk != NULL) {
2948                                         u32 a, b;
2949                                         a = le32_to_cpu(*(__le32 *) walk->dmi_addr);
2950                                         b = le16_to_cpu(*(__le16 *) (&walk->dmi_addr[4]));
2951                                         alwaysOn[0] &= a;
2952                                         alwaysOff[0] &= ~a;
2953                                         alwaysOn[1] &= b;
2954                                         alwaysOff[1] &= ~b;
2955                                         walk = walk->next;
2956                                 }
2957                         }
2958                         addr[0] = alwaysOn[0];
2959                         addr[1] = alwaysOn[1];
2960                         mask[0] = alwaysOn[0] | alwaysOff[0];
2961                         mask[1] = alwaysOn[1] | alwaysOff[1];
2962                 } else {
2963                         mask[0] = NVREG_MCASTMASKA_NONE;
2964                         mask[1] = NVREG_MCASTMASKB_NONE;
2965                 }
2966         }
2967         addr[0] |= NVREG_MCASTADDRA_FORCE;
2968         pff |= NVREG_PFF_ALWAYS;
2969         spin_lock_irq(&np->lock);
2970         nv_stop_rx(dev);
2971         writel(addr[0], base + NvRegMulticastAddrA);
2972         writel(addr[1], base + NvRegMulticastAddrB);
2973         writel(mask[0], base + NvRegMulticastMaskA);
2974         writel(mask[1], base + NvRegMulticastMaskB);
2975         writel(pff, base + NvRegPacketFilterFlags);
2976         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2977                 dev->name);
2978         nv_start_rx(dev);
2979         spin_unlock_irq(&np->lock);
2980 }
2981
2982 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2983 {
2984         struct fe_priv *np = netdev_priv(dev);
2985         u8 __iomem *base = get_hwbase(dev);
2986
2987         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2988
2989         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2990                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2991                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2992                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2993                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2994                 } else {
2995                         writel(pff, base + NvRegPacketFilterFlags);
2996                 }
2997         }
2998         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2999                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3000                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3001                         u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3002                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3003                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3004                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)
3005                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3006                         writel(pause_enable,  base + NvRegTxPauseFrame);
3007                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3008                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3009                 } else {
3010                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
3011                         writel(regmisc, base + NvRegMisc1);
3012                 }
3013         }
3014 }
3015
3016 /**
3017  * nv_update_linkspeed: Setup the MAC according to the link partner
3018  * @dev: Network device to be configured
3019  *
3020  * The function queries the PHY and checks if there is a link partner.
3021  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3022  * set to 10 MBit HD.
3023  *
3024  * The function returns 0 if there is no link partner and 1 if there is
3025  * a good link partner.
3026  */
3027 static int nv_update_linkspeed(struct net_device *dev)
3028 {
3029         struct fe_priv *np = netdev_priv(dev);
3030         u8 __iomem *base = get_hwbase(dev);
3031         int adv = 0;
3032         int lpa = 0;
3033         int adv_lpa, adv_pause, lpa_pause;
3034         int newls = np->linkspeed;
3035         int newdup = np->duplex;
3036         int mii_status;
3037         int retval = 0;
3038         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3039         u32 txrxFlags = 0;
3040         u32 phy_exp;
3041
3042         /* BMSR_LSTATUS is latched, read it twice:
3043          * we want the current value.
3044          */
3045         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3046         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3047
3048         if (!(mii_status & BMSR_LSTATUS)) {
3049                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
3050                                 dev->name);
3051                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3052                 newdup = 0;
3053                 retval = 0;
3054                 goto set_speed;
3055         }
3056
3057         if (np->autoneg == 0) {
3058                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
3059                                 dev->name, np->fixed_mode);
3060                 if (np->fixed_mode & LPA_100FULL) {
3061                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3062                         newdup = 1;
3063                 } else if (np->fixed_mode & LPA_100HALF) {
3064                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3065                         newdup = 0;
3066                 } else if (np->fixed_mode & LPA_10FULL) {
3067                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3068                         newdup = 1;
3069                 } else {
3070                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3071                         newdup = 0;
3072                 }
3073                 retval = 1;
3074                 goto set_speed;
3075         }
3076         /* check auto negotiation is complete */
3077         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3078                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3079                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3080                 newdup = 0;
3081                 retval = 0;
3082                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
3083                 goto set_speed;
3084         }
3085
3086         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3087         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3088         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
3089                                 dev->name, adv, lpa);
3090
3091         retval = 1;
3092         if (np->gigabit == PHY_GIGABIT) {
3093                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3094                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3095
3096                 if ((control_1000 & ADVERTISE_1000FULL) &&
3097                         (status_1000 & LPA_1000FULL)) {
3098                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
3099                                 dev->name);
3100                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3101                         newdup = 1;
3102                         goto set_speed;
3103                 }
3104         }
3105
3106         /* FIXME: handle parallel detection properly */
3107         adv_lpa = lpa & adv;
3108         if (adv_lpa & LPA_100FULL) {
3109                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3110                 newdup = 1;
3111         } else if (adv_lpa & LPA_100HALF) {
3112                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3113                 newdup = 0;
3114         } else if (adv_lpa & LPA_10FULL) {
3115                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3116                 newdup = 1;
3117         } else if (adv_lpa & LPA_10HALF) {
3118                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3119                 newdup = 0;
3120         } else {
3121                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
3122                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3123                 newdup = 0;
3124         }
3125
3126 set_speed:
3127         if (np->duplex == newdup && np->linkspeed == newls)
3128                 return retval;
3129
3130         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
3131                         dev->name, np->linkspeed, np->duplex, newls, newdup);
3132
3133         np->duplex = newdup;
3134         np->linkspeed = newls;
3135
3136         /* The transmitter and receiver must be restarted for safe update */
3137         if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3138                 txrxFlags |= NV_RESTART_TX;
3139                 nv_stop_tx(dev);
3140         }
3141         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3142                 txrxFlags |= NV_RESTART_RX;
3143                 nv_stop_rx(dev);
3144         }
3145
3146         if (np->gigabit == PHY_GIGABIT) {
3147                 phyreg = readl(base + NvRegSlotTime);
3148                 phyreg &= ~(0x3FF00);
3149                 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3150                     ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3151                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3152                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3153                         phyreg |= NVREG_SLOTTIME_1000_FULL;
3154                 writel(phyreg, base + NvRegSlotTime);
3155         }
3156
3157         phyreg = readl(base + NvRegPhyInterface);
3158         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3159         if (np->duplex == 0)
3160                 phyreg |= PHY_HALF;
3161         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3162                 phyreg |= PHY_100;
3163         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3164                 phyreg |= PHY_1000;
3165         writel(phyreg, base + NvRegPhyInterface);
3166
3167         phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3168         if (phyreg & PHY_RGMII) {
3169                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3170                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3171                 } else {
3172                         if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3173                                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3174                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3175                                 else
3176                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3177                         } else {
3178                                 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3179                         }
3180                 }
3181         } else {
3182                 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3183                         txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3184                 else
3185                         txreg = NVREG_TX_DEFERRAL_DEFAULT;
3186         }
3187         writel(txreg, base + NvRegTxDeferral);
3188
3189         if (np->desc_ver == DESC_VER_1) {
3190                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3191         } else {
3192                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3193                         txreg = NVREG_TX_WM_DESC2_3_1000;
3194                 else
3195                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3196         }
3197         writel(txreg, base + NvRegTxWatermark);
3198
3199         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
3200                 base + NvRegMisc1);
3201         pci_push(base);
3202         writel(np->linkspeed, base + NvRegLinkSpeed);
3203         pci_push(base);
3204
3205         pause_flags = 0;
3206         /* setup pause frame */
3207         if (np->duplex != 0) {
3208                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3209                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
3210                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
3211
3212                         switch (adv_pause) {
3213                         case ADVERTISE_PAUSE_CAP:
3214                                 if (lpa_pause & LPA_PAUSE_CAP) {
3215                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3216                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3217                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3218                                 }
3219                                 break;
3220                         case ADVERTISE_PAUSE_ASYM:
3221                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
3222                                 {
3223                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3224                                 }
3225                                 break;
3226                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
3227                                 if (lpa_pause & LPA_PAUSE_CAP)
3228                                 {
3229                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
3230                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3231                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3232                                 }
3233                                 if (lpa_pause == LPA_PAUSE_ASYM)
3234                                 {
3235                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3236                                 }
3237                                 break;
3238                         }
3239                 } else {
3240                         pause_flags = np->pause_flags;
3241                 }
3242         }
3243         nv_update_pause(dev, pause_flags);
3244
3245         if (txrxFlags & NV_RESTART_TX)
3246                 nv_start_tx(dev);
3247         if (txrxFlags & NV_RESTART_RX)
3248                 nv_start_rx(dev);
3249
3250         return retval;
3251 }
3252
3253 static void nv_linkchange(struct net_device *dev)
3254 {
3255         if (nv_update_linkspeed(dev)) {
3256                 if (!netif_carrier_ok(dev)) {
3257                         netif_carrier_on(dev);
3258                         printk(KERN_INFO "%s: link up.\n", dev->name);
3259                         nv_start_rx(dev);
3260                 }
3261         } else {
3262                 if (netif_carrier_ok(dev)) {
3263                         netif_carrier_off(dev);
3264                         printk(KERN_INFO "%s: link down.\n", dev->name);
3265                         nv_stop_rx(dev);
3266                 }
3267         }
3268 }
3269
3270 static void nv_link_irq(struct net_device *dev)
3271 {
3272         u8 __iomem *base = get_hwbase(dev);
3273         u32 miistat;
3274
3275         miistat = readl(base + NvRegMIIStatus);
3276         writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3277         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3278
3279         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3280                 nv_linkchange(dev);
3281         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
3282 }
3283
3284 static void nv_msi_workaround(struct fe_priv *np)
3285 {
3286
3287         /* Need to toggle the msi irq mask within the ethernet device,
3288          * otherwise, future interrupts will not be detected.
3289          */
3290         if (np->msi_flags & NV_MSI_ENABLED) {
3291                 u8 __iomem *base = np->base;
3292
3293                 writel(0, base + NvRegMSIIrqMask);
3294                 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3295         }
3296 }
3297
3298 static irqreturn_t nv_nic_irq(int foo, void *data)
3299 {
3300         struct net_device *dev = (struct net_device *) data;
3301         struct fe_priv *np = netdev_priv(dev);
3302         u8 __iomem *base = get_hwbase(dev);
3303         u32 events;
3304         int i;
3305
3306         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
3307
3308         for (i=0; ; i++) {
3309                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3310                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3311                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3312                 } else {
3313                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3314                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3315                 }
3316                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3317                 if (!(events & np->irqmask))
3318                         break;
3319
3320                 nv_msi_workaround(np);
3321
3322                 spin_lock(&np->lock);
3323                 nv_tx_done(dev);
3324                 spin_unlock(&np->lock);
3325
3326 #ifdef CONFIG_FORCEDETH_NAPI
3327                 if (events & NVREG_IRQ_RX_ALL) {
3328                         netif_rx_schedule(dev, &np->napi);
3329
3330                         /* Disable furthur receive irq's */
3331                         spin_lock(&np->lock);
3332                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
3333
3334                         if (np->msi_flags & NV_MSI_X_ENABLED)
3335                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3336                         else
3337                                 writel(np->irqmask, base + NvRegIrqMask);
3338                         spin_unlock(&np->lock);
3339                 }
3340 #else
3341                 if (nv_rx_process(dev, RX_WORK_PER_LOOP)) {
3342                         if (unlikely(nv_alloc_rx(dev))) {
3343                                 spin_lock(&np->lock);
3344                                 if (!np->in_shutdown)
3345                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3346                                 spin_unlock(&np->lock);
3347                         }
3348                 }
3349 #endif
3350                 if (unlikely(events & NVREG_IRQ_LINK)) {
3351                         spin_lock(&np->lock);
3352                         nv_link_irq(dev);
3353                         spin_unlock(&np->lock);
3354                 }
3355                 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3356                         spin_lock(&np->lock);
3357                         nv_linkchange(dev);
3358                         spin_unlock(&np->lock);
3359                         np->link_timeout = jiffies + LINK_TIMEOUT;
3360                 }
3361                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3362                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3363                                                 dev->name, events);
3364                 }
3365                 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3366                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3367                                                 dev->name, events);
3368                 }
3369                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3370                         spin_lock(&np->lock);
3371                         /* disable interrupts on the nic */
3372                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3373                                 writel(0, base + NvRegIrqMask);
3374                         else
3375                                 writel(np->irqmask, base + NvRegIrqMask);
3376                         pci_push(base);
3377
3378                         if (!np->in_shutdown) {
3379                                 np->nic_poll_irq = np->irqmask;
3380                                 np->recover_error = 1;
3381                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3382                         }
3383                         spin_unlock(&np->lock);
3384                         break;
3385                 }
3386                 if (unlikely(i > max_interrupt_work)) {
3387                         spin_lock(&np->lock);
3388                         /* disable interrupts on the nic */
3389                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3390                                 writel(0, base + NvRegIrqMask);
3391                         else
3392                                 writel(np->irqmask, base + NvRegIrqMask);
3393                         pci_push(base);
3394
3395                         if (!np->in_shutdown) {
3396                                 np->nic_poll_irq = np->irqmask;
3397                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3398                         }
3399                         spin_unlock(&np->lock);
3400                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3401                         break;
3402                 }
3403
3404         }
3405         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3406
3407         return IRQ_RETVAL(i);
3408 }
3409
3410 /**
3411  * All _optimized functions are used to help increase performance
3412  * (reduce CPU and increase throughput). They use descripter version 3,
3413  * compiler directives, and reduce memory accesses.
3414  */
3415 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3416 {
3417         struct net_device *dev = (struct net_device *) data;
3418         struct fe_priv *np = netdev_priv(dev);
3419         u8 __iomem *base = get_hwbase(dev);
3420         u32 events;
3421         int i;
3422
3423         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3424
3425         for (i=0; ; i++) {
3426                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3427                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3428                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3429                 } else {
3430                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3431                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3432                 }
3433                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3434                 if (!(events & np->irqmask))
3435                         break;
3436
3437                 nv_msi_workaround(np);
3438
3439                 spin_lock(&np->lock);
3440                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3441                 spin_unlock(&np->lock);
3442
3443 #ifdef CONFIG_FORCEDETH_NAPI
3444                 if (events & NVREG_IRQ_RX_ALL) {
3445                         netif_rx_schedule(dev, &np->napi);
3446
3447                         /* Disable furthur receive irq's */
3448                         spin_lock(&np->lock);
3449                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
3450
3451                         if (np->msi_flags & NV_MSI_X_ENABLED)
3452                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3453                         else
3454                                 writel(np->irqmask, base + NvRegIrqMask);
3455                         spin_unlock(&np->lock);
3456                 }
3457 #else
3458                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3459                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3460                                 spin_lock(&np->lock);
3461                                 if (!np->in_shutdown)
3462                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3463                                 spin_unlock(&np->lock);
3464                         }
3465                 }
3466 #endif
3467                 if (unlikely(events & NVREG_IRQ_LINK)) {
3468                         spin_lock(&np->lock);
3469                         nv_link_irq(dev);
3470                         spin_unlock(&np->lock);
3471                 }
3472                 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3473                         spin_lock(&np->lock);
3474                         nv_linkchange(dev);
3475                         spin_unlock(&np->lock);
3476                         np->link_timeout = jiffies + LINK_TIMEOUT;
3477                 }
3478                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3479                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3480                                                 dev->name, events);
3481                 }
3482                 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3483                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3484                                                 dev->name, events);
3485                 }
3486                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3487                         spin_lock(&np->lock);
3488                         /* disable interrupts on the nic */
3489                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3490                                 writel(0, base + NvRegIrqMask);
3491                         else
3492                                 writel(np->irqmask, base + NvRegIrqMask);
3493                         pci_push(base);
3494
3495                         if (!np->in_shutdown) {
3496                                 np->nic_poll_irq = np->irqmask;
3497                                 np->recover_error = 1;
3498                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3499                         }
3500                         spin_unlock(&np->lock);
3501                         break;
3502                 }
3503
3504                 if (unlikely(i > max_interrupt_work)) {
3505                         spin_lock(&np->lock);
3506                         /* disable interrupts on the nic */
3507                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3508                                 writel(0, base + NvRegIrqMask);
3509                         else
3510                                 writel(np->irqmask, base + NvRegIrqMask);
3511                         pci_push(base);
3512
3513                         if (!np->in_shutdown) {
3514                                 np->nic_poll_irq = np->irqmask;
3515                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3516                         }
3517                         spin_unlock(&np->lock);
3518                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3519                         break;
3520                 }
3521
3522         }
3523         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3524
3525         return IRQ_RETVAL(i);
3526 }
3527
3528 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3529 {
3530         struct net_device *dev = (struct net_device *) data;
3531         struct fe_priv *np = netdev_priv(dev);
3532         u8 __iomem *base = get_hwbase(dev);
3533         u32 events;
3534         int i;
3535         unsigned long flags;
3536
3537         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3538
3539         for (i=0; ; i++) {
3540                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3541                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3542                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3543                 if (!(events & np->irqmask))
3544                         break;
3545
3546                 spin_lock_irqsave(&np->lock, flags);
3547                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3548                 spin_unlock_irqrestore(&np->lock, flags);
3549
3550                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3551                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3552                                                 dev->name, events);
3553                 }
3554                 if (unlikely(i > max_interrupt_work)) {
3555                         spin_lock_irqsave(&np->lock, flags);
3556                         /* disable interrupts on the nic */
3557                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3558                         pci_push(base);
3559
3560                         if (!np->in_shutdown) {
3561                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3562                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3563                         }
3564                         spin_unlock_irqrestore(&np->lock, flags);
3565                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3566                         break;
3567                 }
3568
3569         }
3570         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3571
3572         return IRQ_RETVAL(i);
3573 }
3574
3575 #ifdef CONFIG_FORCEDETH_NAPI
3576 static int nv_napi_poll(struct napi_struct *napi, int budget)
3577 {
3578         struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3579         struct net_device *dev = np->dev;
3580         u8 __iomem *base = get_hwbase(dev);
3581         unsigned long flags;
3582         int pkts, retcode;
3583
3584         if (!nv_optimized(np)) {
3585                 pkts = nv_rx_process(dev, budget);
3586                 retcode = nv_alloc_rx(dev);
3587         } else {
3588                 pkts = nv_rx_process_optimized(dev, budget);
3589                 retcode = nv_alloc_rx_optimized(dev);
3590         }
3591
3592         if (retcode) {
3593                 spin_lock_irqsave(&np->lock, flags);
3594                 if (!np->in_shutdown)
3595                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3596                 spin_unlock_irqrestore(&np->lock, flags);
3597         }
3598
3599         if (pkts < budget) {
3600                 /* re-enable receive interrupts */
3601                 spin_lock_irqsave(&np->lock, flags);
3602
3603                 __netif_rx_complete(dev, napi);
3604
3605                 np->irqmask |= NVREG_IRQ_RX_ALL;
3606                 if (np->msi_flags & NV_MSI_X_ENABLED)
3607                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3608                 else
3609                         writel(np->irqmask, base + NvRegIrqMask);
3610
3611                 spin_unlock_irqrestore(&np->lock, flags);
3612         }
3613         return pkts;
3614 }
3615 #endif
3616
3617 #ifdef CONFIG_FORCEDETH_NAPI
3618 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3619 {
3620         struct net_device *dev = (struct net_device *) data;
3621         struct fe_priv *np = netdev_priv(dev);
3622         u8 __iomem *base = get_hwbase(dev);
3623         u32 events;
3624
3625         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3626         writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3627
3628         if (events) {
3629                 netif_rx_schedule(dev, &np->napi);
3630                 /* disable receive interrupts on the nic */
3631                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3632                 pci_push(base);
3633         }
3634         return IRQ_HANDLED;
3635 }
3636 #else
3637 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3638 {
3639         struct net_device *dev = (struct net_device *) data;
3640         struct fe_priv *np = netdev_priv(dev);
3641         u8 __iomem *base = get_hwbase(dev);
3642         u32 events;
3643         int i;
3644         unsigned long flags;
3645
3646         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3647
3648         for (i=0; ; i++) {
3649                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3650                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3651                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3652                 if (!(events & np->irqmask))
3653                         break;
3654
3655                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3656                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3657                                 spin_lock_irqsave(&np->lock, flags);
3658                                 if (!np->in_shutdown)
3659                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3660                                 spin_unlock_irqrestore(&np->lock, flags);
3661                         }
3662                 }
3663
3664                 if (unlikely(i > max_interrupt_work)) {
3665                         spin_lock_irqsave(&np->lock, flags);
3666                         /* disable interrupts on the nic */
3667                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3668                         pci_push(base);
3669
3670                         if (!np->in_shutdown) {
3671                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3672                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3673                         }
3674                         spin_unlock_irqrestore(&np->lock, flags);
3675                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3676                         break;
3677                 }
3678         }
3679         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3680
3681         return IRQ_RETVAL(i);
3682 }
3683 #endif
3684
3685 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3686 {
3687         struct net_device *dev = (struct net_device *) data;
3688         struct fe_priv *np = netdev_priv(dev);
3689         u8 __iomem *base = get_hwbase(dev);
3690         u32 events;
3691         int i;
3692         unsigned long flags;
3693
3694         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3695
3696         for (i=0; ; i++) {
3697                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3698                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3699                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3700                 if (!(events & np->irqmask))
3701                         break;
3702
3703                 /* check tx in case we reached max loop limit in tx isr */
3704                 spin_lock_irqsave(&np->lock, flags);
3705                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3706                 spin_unlock_irqrestore(&np->lock, flags);
3707
3708                 if (events & NVREG_IRQ_LINK) {
3709                         spin_lock_irqsave(&np->lock, flags);
3710                         nv_link_irq(dev);
3711                         spin_unlock_irqrestore(&np->lock, flags);
3712                 }
3713                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3714                         spin_lock_irqsave(&np->lock, flags);
3715                         nv_linkchange(dev);
3716                         spin_unlock_irqrestore(&np->lock, flags);
3717                         np->link_timeout = jiffies + LINK_TIMEOUT;
3718                 }
3719                 if (events & NVREG_IRQ_RECOVER_ERROR) {
3720                         spin_lock_irq(&np->lock);
3721                         /* disable interrupts on the nic */
3722                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3723                         pci_push(base);
3724
3725                         if (!np->in_shutdown) {
3726                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3727                                 np->recover_error = 1;
3728                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3729                         }
3730                         spin_unlock_irq(&np->lock);
3731                         break;
3732                 }
3733                 if (events & (NVREG_IRQ_UNKNOWN)) {
3734                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3735                                                 dev->name, events);
3736                 }
3737                 if (unlikely(i > max_interrupt_work)) {
3738                         spin_lock_irqsave(&np->lock, flags);
3739                         /* disable interrupts on the nic */
3740                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3741                         pci_push(base);
3742
3743                         if (!np->in_shutdown) {
3744                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3745                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3746                         }
3747                         spin_unlock_irqrestore(&np->lock, flags);
3748                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3749                         break;
3750                 }
3751
3752         }
3753         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3754
3755         return IRQ_RETVAL(i);
3756 }
3757
3758 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3759 {
3760         struct net_device *dev = (struct net_device *) data;
3761         struct fe_priv *np = netdev_priv(dev);
3762         u8 __iomem *base = get_hwbase(dev);
3763         u32 events;
3764
3765         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3766
3767         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3768                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3769                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3770         } else {
3771                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3772                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3773         }
3774         pci_push(base);
3775         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3776         if (!(events & NVREG_IRQ_TIMER))
3777                 return IRQ_RETVAL(0);
3778
3779         nv_msi_workaround(np);
3780
3781         spin_lock(&np->lock);
3782         np->intr_test = 1;
3783         spin_unlock(&np->lock);
3784
3785         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3786
3787         return IRQ_RETVAL(1);
3788 }
3789
3790 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3791 {
3792         u8 __iomem *base = get_hwbase(dev);
3793         int i;
3794         u32 msixmap = 0;
3795
3796         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3797          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3798          * the remaining 8 interrupts.
3799          */
3800         for (i = 0; i < 8; i++) {
3801                 if ((irqmask >> i) & 0x1) {
3802                         msixmap |= vector << (i << 2);
3803                 }
3804         }
3805         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3806
3807         msixmap = 0;
3808         for (i = 0; i < 8; i++) {
3809                 if ((irqmask >> (i + 8)) & 0x1) {
3810                         msixmap |= vector << (i << 2);
3811                 }
3812         }
3813         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3814 }
3815
3816 static int nv_request_irq(struct net_device *dev, int intr_test)
3817 {
3818         struct fe_priv *np = get_nvpriv(dev);
3819         u8 __iomem *base = get_hwbase(dev);
3820         int ret = 1;
3821         int i;
3822         irqreturn_t (*handler)(int foo, void *data);
3823
3824         if (intr_test) {
3825                 handler = nv_nic_irq_test;
3826         } else {
3827                 if (nv_optimized(np))
3828                         handler = nv_nic_irq_optimized;
3829                 else
3830                         handler = nv_nic_irq;
3831         }
3832
3833         if (np->msi_flags & NV_MSI_X_CAPABLE) {
3834                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3835                         np->msi_x_entry[i].entry = i;
3836                 }
3837                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3838                         np->msi_flags |= NV_MSI_X_ENABLED;
3839                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3840                                 /* Request irq for rx handling */
3841                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
3842                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3843                                         pci_disable_msix(np->pci_dev);
3844                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3845                                         goto out_err;
3846                                 }
3847                                 /* Request irq for tx handling */
3848                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
3849                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3850                                         pci_disable_msix(np->pci_dev);
3851                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3852                                         goto out_free_rx;
3853                                 }
3854                                 /* Request irq for link and timer handling */
3855                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
3856                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
3857                                         pci_disable_msix(np->pci_dev);
3858                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3859                                         goto out_free_tx;
3860                                 }
3861                                 /* map interrupts to their respective vector */
3862                                 writel(0, base + NvRegMSIXMap0);
3863                                 writel(0, base + NvRegMSIXMap1);
3864                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3865                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3866                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3867                         } else {
3868                                 /* Request irq for all interrupts */
3869                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3870                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3871                                         pci_disable_msix(np->pci_dev);
3872                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3873                                         goto out_err;
3874                                 }
3875
3876                                 /* map interrupts to vector 0 */
3877                                 writel(0, base + NvRegMSIXMap0);
3878                                 writel(0, base + NvRegMSIXMap1);
3879                         }
3880                 }
3881         }
3882         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3883                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
3884                         np->msi_flags |= NV_MSI_ENABLED;
3885                         dev->irq = np->pci_dev->irq;
3886                         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3887                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3888                                 pci_disable_msi(np->pci_dev);
3889                                 np->msi_flags &= ~NV_MSI_ENABLED;
3890                                 dev->irq = np->pci_dev->irq;
3891                                 goto out_err;
3892                         }
3893
3894                         /* map interrupts to vector 0 */
3895                         writel(0, base + NvRegMSIMap0);
3896                         writel(0, base + NvRegMSIMap1);
3897                         /* enable msi vector 0 */
3898                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3899                 }
3900         }
3901         if (ret != 0) {
3902                 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3903                         goto out_err;
3904
3905         }
3906
3907         return 0;
3908 out_free_tx:
3909         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3910 out_free_rx:
3911         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3912 out_err:
3913         return 1;
3914 }
3915
3916 static void nv_free_irq(struct net_device *dev)
3917 {
3918         struct fe_priv *np = get_nvpriv(dev);
3919         int i;
3920
3921         if (np->msi_flags & NV_MSI_X_ENABLED) {
3922                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3923                         free_irq(np->msi_x_entry[i].vector, dev);
3924                 }
3925                 pci_disable_msix(np->pci_dev);
3926                 np->msi_flags &= ~NV_MSI_X_ENABLED;
3927         } else {
3928                 free_irq(np->pci_dev->irq, dev);
3929                 if (np->msi_flags & NV_MSI_ENABLED) {
3930                         pci_disable_msi(np->pci_dev);
3931                         np->msi_flags &= ~NV_MSI_ENABLED;
3932                 }
3933         }
3934 }
3935
3936 static void nv_do_nic_poll(unsigned long data)
3937 {
3938         struct net_device *dev = (struct net_device *) data;
3939         struct fe_priv *np = netdev_priv(dev);
3940         u8 __iomem *base = get_hwbase(dev);
3941         u32 mask = 0;
3942
3943         /*
3944          * First disable irq(s) and then
3945          * reenable interrupts on the nic, we have to do this before calling
3946          * nv_nic_irq because that may decide to do otherwise
3947          */
3948
3949         if (!using_multi_irqs(dev)) {
3950                 if (np->msi_flags & NV_MSI_X_ENABLED)
3951                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3952                 else
3953                         disable_irq_lockdep(np->pci_dev->irq);
3954                 mask = np->irqmask;
3955         } else {
3956                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3957                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3958                         mask |= NVREG_IRQ_RX_ALL;
3959                 }
3960                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3961                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3962                         mask |= NVREG_IRQ_TX_ALL;
3963                 }
3964                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3965                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3966                         mask |= NVREG_IRQ_OTHER;
3967                 }
3968         }
3969         np->nic_poll_irq = 0;
3970
3971         /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
3972
3973         if (np->recover_error) {
3974                 np->recover_error = 0;
3975                 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
3976                 if (netif_running(dev)) {
3977                         netif_tx_lock_bh(dev);
3978                         netif_addr_lock(dev);
3979                         spin_lock(&np->lock);
3980                         /* stop engines */
3981                         nv_stop_rxtx(dev);
3982                         nv_txrx_reset(dev);
3983                         /* drain rx queue */
3984                         nv_drain_rxtx(dev);
3985                         /* reinit driver view of the rx queue */
3986                         set_bufsize(dev);
3987                         if (nv_init_ring(dev)) {
3988                                 if (!np->in_shutdown)
3989                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3990                         }
3991                         /* reinit nic view of the rx queue */
3992                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3993                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3994                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3995                                 base + NvRegRingSizes);
3996                         pci_push(base);
3997                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3998                         pci_push(base);
3999
4000                         /* restart rx engine */
4001                         nv_start_rxtx(dev);
4002                         spin_unlock(&np->lock);
4003                         netif_addr_unlock(dev);
4004                         netif_tx_unlock_bh(dev);
4005                 }
4006         }
4007
4008
4009         writel(mask, base + NvRegIrqMask);
4010         pci_push(base);
4011
4012         if (!using_multi_irqs(dev)) {
4013                 if (nv_optimized(np))
4014                         nv_nic_irq_optimized(0, dev);
4015                 else
4016                         nv_nic_irq(0, dev);
4017                 if (np->msi_flags & NV_MSI_X_ENABLED)
4018                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4019                 else
4020                         enable_irq_lockdep(np->pci_dev->irq);
4021         } else {
4022                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4023                         nv_nic_irq_rx(0, dev);
4024                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4025                 }
4026                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4027                         nv_nic_irq_tx(0, dev);
4028                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4029                 }
4030                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4031                         nv_nic_irq_other(0, dev);
4032                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4033                 }
4034         }
4035 }
4036
4037 #ifdef CONFIG_NET_POLL_CONTROLLER
4038 static void nv_poll_controller(struct net_device *dev)
4039 {
4040         nv_do_nic_poll((unsigned long) dev);
4041 }
4042 #endif
4043
4044 static void nv_do_stats_poll(unsigned long data)
4045 {
4046         struct net_device *dev = (struct net_device *) data;
4047         struct fe_priv *np = netdev_priv(dev);
4048
4049         nv_get_hw_stats(dev);
4050
4051         if (!np->in_shutdown)
4052                 mod_timer(&np->stats_poll,
4053                         round_jiffies(jiffies + STATS_INTERVAL));
4054 }
4055
4056 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4057 {
4058         struct fe_priv *np = netdev_priv(dev);
4059         strcpy(info->driver, DRV_NAME);
4060         strcpy(info->version, FORCEDETH_VERSION);
4061         strcpy(info->bus_info, pci_name(np->pci_dev));
4062 }
4063
4064 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4065 {
4066         struct fe_priv *np = netdev_priv(dev);
4067         wolinfo->supported = WAKE_MAGIC;
4068
4069         spin_lock_irq(&np->lock);
4070         if (np->wolenabled)
4071                 wolinfo->wolopts = WAKE_MAGIC;
4072         spin_unlock_irq(&np->lock);
4073 }
4074
4075 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4076 {
4077         struct fe_priv *np = netdev_priv(dev);
4078         u8 __iomem *base = get_hwbase(dev);
4079         u32 flags = 0;
4080
4081         if (wolinfo->wolopts == 0) {
4082                 np->wolenabled = 0;
4083         } else if (wolinfo->wolopts & WAKE_MAGIC) {
4084                 np->wolenabled = 1;
4085                 flags = NVREG_WAKEUPFLAGS_ENABLE;
4086         }
4087         if (netif_running(dev)) {
4088                 spin_lock_irq(&np->lock);
4089                 writel(flags, base + NvRegWakeUpFlags);
4090                 spin_unlock_irq(&np->lock);
4091         }
4092         return 0;
4093 }
4094
4095 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4096 {
4097         struct fe_priv *np = netdev_priv(dev);
4098         int adv;
4099
4100         spin_lock_irq(&np->lock);
4101         ecmd->port = PORT_MII;
4102         if (!netif_running(dev)) {
4103                 /* We do not track link speed / duplex setting if the
4104                  * interface is disabled. Force a link check */
4105                 if (nv_update_linkspeed(dev)) {
4106                         if (!netif_carrier_ok(dev))
4107                                 netif_carrier_on(dev);
4108                 } else {
4109                         if (netif_carrier_ok(dev))
4110                                 netif_carrier_off(dev);
4111                 }
4112         }
4113
4114         if (netif_carrier_ok(dev)) {
4115                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4116                 case NVREG_LINKSPEED_10:
4117                         ecmd->speed = SPEED_10;
4118                         break;
4119                 case NVREG_LINKSPEED_100:
4120                         ecmd->speed = SPEED_100;
4121                         break;
4122                 case NVREG_LINKSPEED_1000:
4123                         ecmd->speed = SPEED_1000;
4124                         break;
4125                 }
4126                 ecmd->duplex = DUPLEX_HALF;
4127                 if (np->duplex)
4128                         ecmd->duplex = DUPLEX_FULL;
4129         } else {
4130                 ecmd->speed = -1;
4131                 ecmd->duplex = -1;
4132         }
4133
4134         ecmd->autoneg = np->autoneg;
4135
4136         ecmd->advertising = ADVERTISED_MII;
4137         if (np->autoneg) {
4138                 ecmd->advertising |= ADVERTISED_Autoneg;
4139                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4140                 if (adv & ADVERTISE_10HALF)
4141                         ecmd->advertising |= ADVERTISED_10baseT_Half;
4142                 if (adv & ADVERTISE_10FULL)
4143                         ecmd->advertising |= ADVERTISED_10baseT_Full;
4144                 if (adv & ADVERTISE_100HALF)
4145                         ecmd->advertising |= ADVERTISED_100baseT_Half;
4146                 if (adv & ADVERTISE_100FULL)
4147                         ecmd->advertising |= ADVERTISED_100baseT_Full;
4148                 if (np->gigabit == PHY_GIGABIT) {
4149                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4150                         if (adv & ADVERTISE_1000FULL)
4151                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4152                 }
4153         }
4154         ecmd->supported = (SUPPORTED_Autoneg |
4155                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4156                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4157                 SUPPORTED_MII);
4158         if (np->gigabit == PHY_GIGABIT)
4159                 ecmd->supported |= SUPPORTED_1000baseT_Full;
4160
4161         ecmd->phy_address = np->phyaddr;
4162         ecmd->transceiver = XCVR_EXTERNAL;
4163
4164         /* ignore maxtxpkt, maxrxpkt for now */
4165         spin_unlock_irq(&np->lock);
4166         return 0;
4167 }
4168
4169 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4170 {
4171         struct fe_priv *np = netdev_priv(dev);
4172
4173         if (ecmd->port != PORT_MII)
4174                 return -EINVAL;
4175         if (ecmd->transceiver != XCVR_EXTERNAL)
4176                 return -EINVAL;
4177         if (ecmd->phy_address != np->phyaddr) {
4178                 /* TODO: support switching between multiple phys. Should be
4179                  * trivial, but not enabled due to lack of test hardware. */
4180                 return -EINVAL;
4181         }
4182         if (ecmd->autoneg == AUTONEG_ENABLE) {
4183                 u32 mask;
4184
4185                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4186                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4187                 if (np->gigabit == PHY_GIGABIT)
4188                         mask |= ADVERTISED_1000baseT_Full;
4189
4190                 if ((ecmd->advertising & mask) == 0)
4191                         return -EINVAL;
4192
4193         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4194                 /* Note: autonegotiation disable, speed 1000 intentionally
4195                  * forbidden - noone should need that. */
4196
4197                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4198                         return -EINVAL;
4199                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4200                         return -EINVAL;
4201         } else {
4202                 return -EINVAL;
4203         }
4204
4205         netif_carrier_off(dev);
4206         if (netif_running(dev)) {
4207                 unsigned long flags;
4208
4209                 nv_disable_irq(dev);
4210                 netif_tx_lock_bh(dev);
4211                 netif_addr_lock(dev);
4212                 /* with plain spinlock lockdep complains */
4213                 spin_lock_irqsave(&np->lock, flags);
4214                 /* stop engines */
4215                 /* FIXME:
4216                  * this can take some time, and interrupts are disabled
4217                  * due to spin_lock_irqsave, but let's hope no daemon
4218                  * is going to change the settings very often...
4219                  * Worst case:
4220                  * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4221                  * + some minor delays, which is up to a second approximately
4222                  */
4223                 nv_stop_rxtx(dev);
4224                 spin_unlock_irqrestore(&np->lock, flags);
4225                 netif_addr_unlock(dev);
4226                 netif_tx_unlock_bh(dev);
4227         }
4228
4229         if (ecmd->autoneg == AUTONEG_ENABLE) {
4230                 int adv, bmcr;
4231
4232                 np->autoneg = 1;
4233
4234                 /* advertise only what has been requested */
4235                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4236                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4237                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4238                         adv |= ADVERTISE_10HALF;
4239                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4240                         adv |= ADVERTISE_10FULL;
4241                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4242                         adv |= ADVERTISE_100HALF;
4243                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4244                         adv |= ADVERTISE_100FULL;
4245                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
4246                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4247                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4248                         adv |=  ADVERTISE_PAUSE_ASYM;
4249                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4250
4251                 if (np->gigabit == PHY_GIGABIT) {
4252                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4253                         adv &= ~ADVERTISE_1000FULL;
4254                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4255                                 adv |= ADVERTISE_1000FULL;
4256                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4257                 }
4258
4259                 if (netif_running(dev))
4260                         printk(KERN_INFO "%s: link down.\n", dev->name);
4261                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4262                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4263                         bmcr |= BMCR_ANENABLE;
4264                         /* reset the phy in order for settings to stick,
4265                          * and cause autoneg to start */
4266                         if (phy_reset(dev, bmcr)) {
4267                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4268                                 return -EINVAL;
4269                         }
4270                 } else {
4271                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4272                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4273                 }
4274         } else {
4275                 int adv, bmcr;
4276
4277                 np->autoneg = 0;
4278
4279                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4280                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4281                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4282                         adv |= ADVERTISE_10HALF;
4283                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4284                         adv |= ADVERTISE_10FULL;
4285                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4286                         adv |= ADVERTISE_100HALF;
4287                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4288                         adv |= ADVERTISE_100FULL;
4289                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4290                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4291                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4292                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4293                 }
4294                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4295                         adv |=  ADVERTISE_PAUSE_ASYM;
4296                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4297                 }
4298                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4299                 np->fixed_mode = adv;
4300
4301                 if (np->gigabit == PHY_GIGABIT) {
4302                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4303                         adv &= ~ADVERTISE_1000FULL;
4304                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4305                 }
4306
4307                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4308                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4309                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4310                         bmcr |= BMCR_FULLDPLX;
4311                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4312                         bmcr |= BMCR_SPEED100;
4313                 if (np->phy_oui == PHY_OUI_MARVELL) {
4314                         /* reset the phy in order for forced mode settings to stick */
4315                         if (phy_reset(dev, bmcr)) {
4316                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4317                                 return -EINVAL;
4318                         }
4319                 } else {
4320                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4321                         if (netif_running(dev)) {
4322                                 /* Wait a bit and then reconfigure the nic. */
4323                                 udelay(10);
4324                                 nv_linkchange(dev);
4325                         }
4326                 }
4327         }
4328
4329         if (netif_running(dev)) {
4330                 nv_start_rxtx(dev);
4331                 nv_enable_irq(dev);
4332         }
4333
4334         return 0;
4335 }
4336
4337 #define FORCEDETH_REGS_VER      1
4338
4339 static int nv_get_regs_len(struct net_device *dev)
4340 {
4341         struct fe_priv *np = netdev_priv(dev);
4342         return np->register_size;
4343 }
4344
4345 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4346 {
4347         struct fe_priv *np = netdev_priv(dev);
4348         u8 __iomem *base = get_hwbase(dev);
4349         u32 *rbuf = buf;
4350         int i;
4351
4352         regs->version = FORCEDETH_REGS_VER;
4353         spin_lock_irq(&np->lock);
4354         for (i = 0;i <= np->register_size/sizeof(u32); i++)
4355                 rbuf[i] = readl(base + i*sizeof(u32));
4356         spin_unlock_irq(&np->lock);
4357 }
4358
4359 static int nv_nway_reset(struct net_device *dev)
4360 {
4361         struct fe_priv *np = netdev_priv(dev);
4362         int ret;
4363
4364         if (np->autoneg) {
4365                 int bmcr;
4366
4367                 netif_carrier_off(dev);
4368                 if (netif_running(dev)) {
4369                         nv_disable_irq(dev);
4370                         netif_tx_lock_bh(dev);
4371                         netif_addr_lock(dev);
4372                         spin_lock(&np->lock);
4373                         /* stop engines */
4374                         nv_stop_rxtx(dev);
4375                         spin_unlock(&np->lock);
4376                         netif_addr_unlock(dev);
4377                         netif_tx_unlock_bh(dev);
4378                         printk(KERN_INFO "%s: link down.\n", dev->name);
4379                 }
4380
4381                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4382                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4383                         bmcr |= BMCR_ANENABLE;
4384                         /* reset the phy in order for settings to stick*/
4385                         if (phy_reset(dev, bmcr)) {
4386                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4387                                 return -EINVAL;
4388                         }
4389                 } else {
4390                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4391                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4392                 }
4393
4394                 if (netif_running(dev)) {
4395                         nv_start_rxtx(dev);
4396                         nv_enable_irq(dev);
4397                 }
4398                 ret = 0;
4399         } else {
4400                 ret = -EINVAL;
4401         }
4402
4403         return ret;
4404 }
4405
4406 static int nv_set_tso(struct net_device *dev, u32 value)
4407 {
4408         struct fe_priv *np = netdev_priv(dev);
4409
4410         if ((np->driver_data & DEV_HAS_CHECKSUM))
4411                 return ethtool_op_set_tso(dev, value);
4412         else
4413                 return -EOPNOTSUPP;
4414 }
4415
4416 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4417 {
4418         struct fe_priv *np = netdev_priv(dev);
4419
4420         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4421         ring->rx_mini_max_pending = 0;
4422         ring->rx_jumbo_max_pending = 0;
4423         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4424
4425         ring->rx_pending = np->rx_ring_size;
4426         ring->rx_mini_pending = 0;
4427         ring->rx_jumbo_pending = 0;
4428         ring->tx_pending = np->tx_ring_size;
4429 }
4430
4431 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4432 {
4433         struct fe_priv *np = netdev_priv(dev);
4434         u8 __iomem *base = get_hwbase(dev);
4435         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4436         dma_addr_t ring_addr;
4437
4438         if (ring->rx_pending < RX_RING_MIN ||
4439             ring->tx_pending < TX_RING_MIN ||
4440             ring->rx_mini_pending != 0 ||
4441             ring->rx_jumbo_pending != 0 ||
4442             (np->desc_ver == DESC_VER_1 &&
4443              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4444               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4445             (np->desc_ver != DESC_VER_1 &&
4446              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4447               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4448                 return -EINVAL;
4449         }
4450
4451         /* allocate new rings */
4452         if (!nv_optimized(np)) {
4453                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4454                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4455                                             &ring_addr);
4456         } else {
4457                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4458                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4459                                             &ring_addr);
4460         }
4461         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4462         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4463         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4464                 /* fall back to old rings */
4465                 if (!nv_optimized(np)) {
4466                         if (rxtx_ring)
4467                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4468                                                     rxtx_ring, ring_addr);
4469                 } else {
4470                         if (rxtx_ring)
4471                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4472                                                     rxtx_ring, ring_addr);
4473                 }
4474                 if (rx_skbuff)
4475                         kfree(rx_skbuff);
4476                 if (tx_skbuff)
4477                         kfree(tx_skbuff);
4478                 goto exit;
4479         }
4480
4481         if (netif_running(dev)) {
4482                 nv_disable_irq(dev);
4483                 netif_tx_lock_bh(dev);
4484                 netif_addr_lock(dev);
4485                 spin_lock(&np->lock);
4486                 /* stop engines */
4487                 nv_stop_rxtx(dev);
4488                 nv_txrx_reset(dev);
4489                 /* drain queues */
4490                 nv_drain_rxtx(dev);
4491                 /* delete queues */
4492                 free_rings(dev);
4493         }
4494
4495         /* set new values */
4496         np->rx_ring_size = ring->rx_pending;
4497         np->tx_ring_size = ring->tx_pending;
4498
4499         if (!nv_optimized(np)) {
4500                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4501                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4502         } else {
4503                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4504                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4505         }
4506         np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4507         np->tx_skb = (struct nv_skb_map*)tx_skbuff;
4508         np->ring_addr = ring_addr;
4509
4510         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4511         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4512
4513         if (netif_running(dev)) {
4514                 /* reinit driver view of the queues */
4515                 set_bufsize(dev);
4516                 if (nv_init_ring(dev)) {
4517                         if (!np->in_shutdown)
4518                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4519                 }
4520
4521                 /* reinit nic view of the queues */
4522                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4523                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4524                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4525                         base + NvRegRingSizes);
4526                 pci_push(base);
4527                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4528                 pci_push(base);
4529
4530                 /* restart engines */
4531                 nv_start_rxtx(dev);
4532                 spin_unlock(&np->lock);
4533                 netif_addr_unlock(dev);
4534                 netif_tx_unlock_bh(dev);
4535                 nv_enable_irq(dev);
4536         }
4537         return 0;
4538 exit:
4539         return -ENOMEM;
4540 }
4541
4542 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4543 {
4544         struct fe_priv *np = netdev_priv(dev);
4545
4546         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4547         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4548         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4549 }
4550
4551 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4552 {
4553         struct fe_priv *np = netdev_priv(dev);
4554         int adv, bmcr;
4555
4556         if ((!np->autoneg && np->duplex == 0) ||
4557             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4558                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4559                        dev->name);
4560                 return -EINVAL;
4561         }
4562         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4563                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4564                 return -EINVAL;
4565         }
4566
4567         netif_carrier_off(dev);
4568         if (netif_running(dev)) {
4569                 nv_disable_irq(dev);
4570                 netif_tx_lock_bh(dev);
4571                 netif_addr_lock(dev);
4572                 spin_lock(&np->lock);
4573                 /* stop engines */
4574                 nv_stop_rxtx(dev);
4575                 spin_unlock(&np->lock);
4576                 netif_addr_unlock(dev);
4577                 netif_tx_unlock_bh(dev);
4578         }
4579
4580         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4581         if (pause->rx_pause)
4582                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4583         if (pause->tx_pause)
4584                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4585
4586         if (np->autoneg && pause->autoneg) {
4587                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4588
4589                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4590                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4591                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4592                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4593                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4594                         adv |=  ADVERTISE_PAUSE_ASYM;
4595                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4596
4597                 if (netif_running(dev))
4598                         printk(KERN_INFO "%s: link down.\n", dev->name);
4599                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4600                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4601                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4602         } else {
4603                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4604                 if (pause->rx_pause)
4605                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4606                 if (pause->tx_pause)
4607                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4608
4609                 if (!netif_running(dev))
4610                         nv_update_linkspeed(dev);
4611                 else
4612                         nv_update_pause(dev, np->pause_flags);
4613         }
4614
4615         if (netif_running(dev)) {
4616                 nv_start_rxtx(dev);
4617                 nv_enable_irq(dev);
4618         }
4619         return 0;
4620 }
4621
4622 static u32 nv_get_rx_csum(struct net_device *dev)
4623 {
4624         struct fe_priv *np = netdev_priv(dev);
4625         return (np->rx_csum) != 0;
4626 }
4627
4628 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4629 {
4630         struct fe_priv *np = netdev_priv(dev);
4631         u8 __iomem *base = get_hwbase(dev);
4632         int retcode = 0;
4633
4634         if (np->driver_data & DEV_HAS_CHECKSUM) {
4635                 if (data) {
4636                         np->rx_csum = 1;
4637                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4638                 } else {
4639                         np->rx_csum = 0;
4640                         /* vlan is dependent on rx checksum offload */
4641                         if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4642                                 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4643                 }
4644                 if (netif_running(dev)) {
4645                         spin_lock_irq(&np->lock);
4646                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4647                         spin_unlock_irq(&np->lock);
4648                 }
4649         } else {
4650                 return -EINVAL;
4651         }
4652
4653         return retcode;
4654 }
4655
4656 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4657 {
4658         struct fe_priv *np = netdev_priv(dev);
4659
4660         if (np->driver_data & DEV_HAS_CHECKSUM)
4661                 return ethtool_op_set_tx_hw_csum(dev, data);
4662         else
4663                 return -EOPNOTSUPP;
4664 }
4665
4666 static int nv_set_sg(struct net_device *dev, u32 data)
4667 {
4668         struct fe_priv *np = netdev_priv(dev);
4669
4670         if (np->driver_data & DEV_HAS_CHECKSUM)
4671                 return ethtool_op_set_sg(dev, data);
4672         else
4673                 return -EOPNOTSUPP;
4674 }
4675
4676 static int nv_get_sset_count(struct net_device *dev, int sset)
4677 {
4678         struct fe_priv *np = netdev_priv(dev);
4679
4680         switch (sset) {
4681         case ETH_SS_TEST:
4682                 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4683                         return NV_TEST_COUNT_EXTENDED;
4684                 else
4685                         return NV_TEST_COUNT_BASE;
4686         case ETH_SS_STATS:
4687                 if (np->driver_data & DEV_HAS_STATISTICS_V1)
4688                         return NV_DEV_STATISTICS_V1_COUNT;
4689                 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4690                         return NV_DEV_STATISTICS_V2_COUNT;
4691                 else
4692                         return 0;
4693         default:
4694                 return -EOPNOTSUPP;
4695         }
4696 }
4697
4698 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4699 {
4700         struct fe_priv *np = netdev_priv(dev);
4701
4702         /* update stats */
4703         nv_do_stats_poll((unsigned long)dev);
4704
4705         memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4706 }
4707
4708 static int nv_link_test(struct net_device *dev)
4709 {
4710         struct fe_priv *np = netdev_priv(dev);
4711         int mii_status;
4712
4713         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4714         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4715
4716         /* check phy link status */
4717         if (!(mii_status & BMSR_LSTATUS))
4718                 return 0;
4719         else
4720                 return 1;
4721 }
4722
4723 static int nv_register_test(struct net_device *dev)
4724 {
4725         u8 __iomem *base = get_hwbase(dev);
4726         int i = 0;
4727         u32 orig_read, new_read;
4728
4729         do {
4730                 orig_read = readl(base + nv_registers_test[i].reg);
4731
4732                 /* xor with mask to toggle bits */
4733                 orig_read ^= nv_registers_test[i].mask;
4734
4735                 writel(orig_read, base + nv_registers_test[i].reg);
4736
4737                 new_read = readl(base + nv_registers_test[i].reg);
4738
4739                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4740                         return 0;
4741
4742                 /* restore original value */
4743                 orig_read ^= nv_registers_test[i].mask;
4744                 writel(orig_read, base + nv_registers_test[i].reg);
4745
4746         } while (nv_registers_test[++i].reg != 0);
4747
4748         return 1;
4749 }
4750
4751 static int nv_interrupt_test(struct net_device *dev)
4752 {
4753         struct fe_priv *np = netdev_priv(dev);
4754         u8 __iomem *base = get_hwbase(dev);
4755         int ret = 1;
4756         int testcnt;
4757         u32 save_msi_flags, save_poll_interval = 0;
4758
4759         if (netif_running(dev)) {
4760                 /* free current irq */
4761                 nv_free_irq(dev);
4762                 save_poll_interval = readl(base+NvRegPollingInterval);
4763         }
4764
4765         /* flag to test interrupt handler */
4766         np->intr_test = 0;
4767
4768         /* setup test irq */
4769         save_msi_flags = np->msi_flags;
4770         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4771         np->msi_flags |= 0x001; /* setup 1 vector */
4772         if (nv_request_irq(dev, 1))
4773                 return 0;
4774
4775         /* setup timer interrupt */
4776         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4777         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4778
4779         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4780
4781         /* wait for at least one interrupt */
4782         msleep(100);
4783
4784         spin_lock_irq(&np->lock);
4785
4786         /* flag should be set within ISR */
4787         testcnt = np->intr_test;
4788         if (!testcnt)
4789                 ret = 2;
4790
4791         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4792         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4793                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4794         else
4795                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4796
4797         spin_unlock_irq(&np->lock);
4798
4799         nv_free_irq(dev);
4800
4801         np->msi_flags = save_msi_flags;
4802
4803         if (netif_running(dev)) {
4804                 writel(save_poll_interval, base + NvRegPollingInterval);
4805                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4806                 /* restore original irq */
4807                 if (nv_request_irq(dev, 0))
4808                         return 0;
4809         }
4810
4811         return ret;
4812 }
4813
4814 static int nv_loopback_test(struct net_device *dev)
4815 {
4816         struct fe_priv *np = netdev_priv(dev);
4817         u8 __iomem *base = get_hwbase(dev);
4818         struct sk_buff *tx_skb, *rx_skb;
4819         dma_addr_t test_dma_addr;
4820         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4821         u32 flags;
4822         int len, i, pkt_len;
4823         u8 *pkt_data;
4824         u32 filter_flags = 0;
4825         u32 misc1_flags = 0;
4826         int ret = 1;
4827
4828         if (netif_running(dev)) {
4829                 nv_disable_irq(dev);
4830                 filter_flags = readl(base + NvRegPacketFilterFlags);
4831                 misc1_flags = readl(base + NvRegMisc1);
4832         } else {
4833                 nv_txrx_reset(dev);
4834         }
4835
4836         /* reinit driver view of the rx queue */
4837         set_bufsize(dev);
4838         nv_init_ring(dev);
4839
4840         /* setup hardware for loopback */
4841         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4842         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4843
4844         /* reinit nic view of the rx queue */
4845         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4846         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4847         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4848                 base + NvRegRingSizes);
4849         pci_push(base);
4850
4851         /* restart rx engine */
4852         nv_start_rxtx(dev);
4853
4854         /* setup packet for tx */
4855         pkt_len = ETH_DATA_LEN;
4856         tx_skb = dev_alloc_skb(pkt_len);
4857         if (!tx_skb) {
4858                 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
4859                          " of %s\n", dev->name);
4860                 ret = 0;
4861                 goto out;
4862         }
4863         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4864                                        skb_tailroom(tx_skb),
4865                                        PCI_DMA_FROMDEVICE);
4866         pkt_data = skb_put(tx_skb, pkt_len);
4867         for (i = 0; i < pkt_len; i++)
4868                 pkt_data[i] = (u8)(i & 0xff);
4869
4870         if (!nv_optimized(np)) {
4871                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4872                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4873         } else {
4874                 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4875                 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
4876                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4877         }
4878         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4879         pci_push(get_hwbase(dev));
4880
4881         msleep(500);
4882
4883         /* check for rx of the packet */
4884         if (!nv_optimized(np)) {
4885                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4886                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4887
4888         } else {
4889                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4890                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4891         }
4892
4893         if (flags & NV_RX_AVAIL) {
4894                 ret = 0;
4895         } else if (np->desc_ver == DESC_VER_1) {
4896                 if (flags & NV_RX_ERROR)
4897                         ret = 0;
4898         } else {
4899                 if (flags & NV_RX2_ERROR) {
4900                         ret = 0;
4901                 }
4902         }
4903
4904         if (ret) {
4905                 if (len != pkt_len) {
4906                         ret = 0;
4907                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
4908                                 dev->name, len, pkt_len);
4909                 } else {
4910                         rx_skb = np->rx_skb[0].skb;
4911                         for (i = 0; i < pkt_len; i++) {
4912                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4913                                         ret = 0;
4914                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
4915                                                 dev->name, i);
4916                                         break;
4917                                 }
4918                         }
4919                 }
4920         } else {
4921                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
4922         }
4923
4924         pci_unmap_page(np->pci_dev, test_dma_addr,
4925                        (skb_end_pointer(tx_skb) - tx_skb->data),
4926                        PCI_DMA_TODEVICE);
4927         dev_kfree_skb_any(tx_skb);
4928  out:
4929         /* stop engines */
4930         nv_stop_rxtx(dev);
4931         nv_txrx_reset(dev);
4932         /* drain rx queue */
4933         nv_drain_rxtx(dev);
4934
4935         if (netif_running(dev)) {
4936                 writel(misc1_flags, base + NvRegMisc1);
4937                 writel(filter_flags, base + NvRegPacketFilterFlags);
4938                 nv_enable_irq(dev);
4939         }
4940
4941         return ret;
4942 }
4943
4944 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4945 {
4946         struct fe_priv *np = netdev_priv(dev);
4947         u8 __iomem *base = get_hwbase(dev);
4948         int result;
4949         memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
4950
4951         if (!nv_link_test(dev)) {
4952                 test->flags |= ETH_TEST_FL_FAILED;
4953                 buffer[0] = 1;
4954         }
4955
4956         if (test->flags & ETH_TEST_FL_OFFLINE) {
4957                 if (netif_running(dev)) {
4958                         netif_stop_queue(dev);
4959 #ifdef CONFIG_FORCEDETH_NAPI
4960                         napi_disable(&np->napi);
4961 #endif
4962                         netif_tx_lock_bh(dev);
4963                         netif_addr_lock(dev);
4964                         spin_lock_irq(&np->lock);
4965                         nv_disable_hw_interrupts(dev, np->irqmask);
4966                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
4967                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4968                         } else {
4969                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4970                         }
4971                         /* stop engines */
4972                         nv_stop_rxtx(dev);
4973                         nv_txrx_reset(dev);
4974                         /* drain rx queue */
4975                         nv_drain_rxtx(dev);
4976                         spin_unlock_irq(&np->lock);
4977                         netif_addr_unlock(dev);
4978                         netif_tx_unlock_bh(dev);
4979                 }
4980
4981                 if (!nv_register_test(dev)) {
4982                         test->flags |= ETH_TEST_FL_FAILED;
4983                         buffer[1] = 1;
4984                 }
4985
4986                 result = nv_interrupt_test(dev);
4987                 if (result != 1) {
4988                         test->flags |= ETH_TEST_FL_FAILED;
4989                         buffer[2] = 1;
4990                 }
4991                 if (result == 0) {
4992                         /* bail out */
4993                         return;
4994                 }
4995
4996                 if (!nv_loopback_test(dev)) {
4997                         test->flags |= ETH_TEST_FL_FAILED;
4998                         buffer[3] = 1;
4999                 }
5000
5001                 if (netif_running(dev)) {
5002                         /* reinit driver view of the rx queue */
5003                         set_bufsize(dev);
5004                         if (nv_init_ring(dev)) {
5005                                 if (!np->in_shutdown)
5006                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5007                         }
5008                         /* reinit nic view of the rx queue */
5009                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5010                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5011                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5012                                 base + NvRegRingSizes);
5013                         pci_push(base);
5014                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5015                         pci_push(base);
5016                         /* restart rx engine */
5017                         nv_start_rxtx(dev);
5018                         netif_start_queue(dev);
5019 #ifdef CONFIG_FORCEDETH_NAPI
5020                         napi_enable(&np->napi);
5021 #endif
5022                         nv_enable_hw_interrupts(dev, np->irqmask);
5023                 }
5024         }
5025 }
5026
5027 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5028 {
5029         switch (stringset) {
5030         case ETH_SS_STATS:
5031                 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
5032                 break;
5033         case ETH_SS_TEST:
5034                 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
5035                 break;
5036         }
5037 }
5038
5039 static const struct ethtool_ops ops = {
5040         .get_drvinfo = nv_get_drvinfo,
5041         .get_link = ethtool_op_get_link,
5042         .get_wol = nv_get_wol,
5043         .set_wol = nv_set_wol,
5044         .get_settings = nv_get_settings,
5045         .set_settings = nv_set_settings,
5046         .get_regs_len = nv_get_regs_len,
5047         .get_regs = nv_get_regs,
5048         .nway_reset = nv_nway_reset,
5049         .set_tso = nv_set_tso,
5050         .get_ringparam = nv_get_ringparam,
5051         .set_ringparam = nv_set_ringparam,
5052         .get_pauseparam = nv_get_pauseparam,
5053         .set_pauseparam = nv_set_pauseparam,
5054         .get_rx_csum = nv_get_rx_csum,
5055         .set_rx_csum = nv_set_rx_csum,
5056         .set_tx_csum = nv_set_tx_csum,
5057         .set_sg = nv_set_sg,
5058         .get_strings = nv_get_strings,
5059         .get_ethtool_stats = nv_get_ethtool_stats,
5060         .get_sset_count = nv_get_sset_count,
5061         .self_test = nv_self_test,
5062 };
5063
5064 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
5065 {
5066         struct fe_priv *np = get_nvpriv(dev);
5067
5068         spin_lock_irq(&np->lock);
5069
5070         /* save vlan group */
5071         np->vlangrp = grp;
5072
5073         if (grp) {
5074                 /* enable vlan on MAC */
5075                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
5076         } else {
5077                 /* disable vlan on MAC */
5078                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
5079                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
5080         }
5081
5082         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5083
5084         spin_unlock_irq(&np->lock);
5085 }
5086
5087 /* The mgmt unit and driver use a semaphore to access the phy during init */
5088 static int nv_mgmt_acquire_sema(struct net_device *dev)
5089 {
5090         u8 __iomem *base = get_hwbase(dev);
5091         int i;
5092         u32 tx_ctrl, mgmt_sema;
5093
5094         for (i = 0; i < 10; i++) {
5095                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5096                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5097                         break;
5098                 msleep(500);
5099         }
5100
5101         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5102                 return 0;
5103
5104         for (i = 0; i < 2; i++) {
5105                 tx_ctrl = readl(base + NvRegTransmitterControl);
5106                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5107                 writel(tx_ctrl, base + NvRegTransmitterControl);
5108
5109                 /* verify that semaphore was acquired */
5110                 tx_ctrl = readl(base + NvRegTransmitterControl);
5111                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5112                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE))
5113                         return 1;
5114                 else
5115                         udelay(50);
5116         }
5117
5118         return 0;
5119 }
5120
5121 static int nv_open(struct net_device *dev)
5122 {
5123         struct fe_priv *np = netdev_priv(dev);
5124         u8 __iomem *base = get_hwbase(dev);
5125         int ret = 1;
5126         int oom, i;
5127         u32 low;
5128
5129         dprintk(KERN_DEBUG "nv_open: begin\n");
5130
5131         /* erase previous misconfiguration */
5132         if (np->driver_data & DEV_HAS_POWER_CNTRL)
5133                 nv_mac_reset(dev);
5134         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5135         writel(0, base + NvRegMulticastAddrB);
5136         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5137         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5138         writel(0, base + NvRegPacketFilterFlags);
5139
5140         writel(0, base + NvRegTransmitterControl);
5141         writel(0, base + NvRegReceiverControl);
5142
5143         writel(0, base + NvRegAdapterControl);
5144
5145         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5146                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
5147
5148         /* initialize descriptor rings */
5149         set_bufsize(dev);
5150         oom = nv_init_ring(dev);
5151
5152         writel(0, base + NvRegLinkSpeed);
5153         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5154         nv_txrx_reset(dev);
5155         writel(0, base + NvRegUnknownSetupReg6);
5156
5157         np->in_shutdown = 0;
5158
5159         /* give hw rings */
5160         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5161         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5162                 base + NvRegRingSizes);
5163
5164         writel(np->linkspeed, base + NvRegLinkSpeed);
5165         if (np->desc_ver == DESC_VER_1)
5166                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5167         else
5168                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5169         writel(np->txrxctl_bits, base + NvRegTxRxControl);
5170         writel(np->vlanctl_bits, base + NvRegVlanControl);
5171         pci_push(base);
5172         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5173         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5174                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
5175                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
5176
5177         writel(0, base + NvRegMIIMask);
5178         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5179         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5180
5181         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5182         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5183         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5184         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5185
5186         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5187
5188         get_random_bytes(&low, sizeof(low));
5189         low &= NVREG_SLOTTIME_MASK;
5190         if (np->desc_ver == DESC_VER_1) {
5191                 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5192         } else {
5193                 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5194                         /* setup legacy backoff */
5195                         writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5196                 } else {
5197                         writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5198                         nv_gear_backoff_reseed(dev);
5199                 }
5200         }
5201         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5202         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5203         if (poll_interval == -1) {
5204                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5205                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5206                 else
5207                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5208         }
5209         else
5210                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5211         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5212         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5213                         base + NvRegAdapterControl);
5214         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5215         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5216         if (np->wolenabled)
5217                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5218
5219         i = readl(base + NvRegPowerState);
5220         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
5221                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5222
5223         pci_push(base);
5224         udelay(10);
5225         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5226
5227         nv_disable_hw_interrupts(dev, np->irqmask);
5228         pci_push(base);
5229         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5230         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5231         pci_push(base);
5232
5233         if (nv_request_irq(dev, 0)) {
5234                 goto out_drain;
5235         }
5236
5237         /* ask for interrupts */
5238         nv_enable_hw_interrupts(dev, np->irqmask);
5239
5240         spin_lock_irq(&np->lock);
5241         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5242         writel(0, base + NvRegMulticastAddrB);
5243         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5244         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5245         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5246         /* One manual link speed update: Interrupts are enabled, future link
5247          * speed changes cause interrupts and are handled by nv_link_irq().
5248          */
5249         {
5250                 u32 miistat;
5251                 miistat = readl(base + NvRegMIIStatus);
5252                 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5253                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
5254         }
5255         /* set linkspeed to invalid value, thus force nv_update_linkspeed
5256          * to init hw */
5257         np->linkspeed = 0;
5258         ret = nv_update_linkspeed(dev);
5259         nv_start_rxtx(dev);
5260         netif_start_queue(dev);
5261 #ifdef CONFIG_FORCEDETH_NAPI
5262         napi_enable(&np->napi);
5263 #endif
5264
5265         if (ret) {
5266                 netif_carrier_on(dev);
5267         } else {
5268                 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
5269                 netif_carrier_off(dev);
5270         }
5271         if (oom)
5272                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5273
5274         /* start statistics timer */
5275         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2))
5276                 mod_timer(&np->stats_poll,
5277                         round_jiffies(jiffies + STATS_INTERVAL));
5278
5279         spin_unlock_irq(&np->lock);
5280
5281         return 0;
5282 out_drain:
5283         nv_drain_rxtx(dev);
5284         return ret;
5285 }
5286
5287 static int nv_close(struct net_device *dev)
5288 {
5289         struct fe_priv *np = netdev_priv(dev);
5290         u8 __iomem *base;
5291
5292         spin_lock_irq(&np->lock);
5293         np->in_shutdown = 1;
5294         spin_unlock_irq(&np->lock);
5295 #ifdef CONFIG_FORCEDETH_NAPI
5296         napi_disable(&np->napi);
5297 #endif
5298         synchronize_irq(np->pci_dev->irq);
5299
5300         del_timer_sync(&np->oom_kick);
5301         del_timer_sync(&np->nic_poll);
5302         del_timer_sync(&np->stats_poll);
5303
5304         netif_stop_queue(dev);
5305         spin_lock_irq(&np->lock);
5306         nv_stop_rxtx(dev);
5307         nv_txrx_reset(dev);
5308
5309         /* disable interrupts on the nic or we will lock up */
5310         base = get_hwbase(dev);
5311         nv_disable_hw_interrupts(dev, np->irqmask);
5312         pci_push(base);
5313         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5314
5315         spin_unlock_irq(&np->lock);
5316
5317         nv_free_irq(dev);
5318
5319         nv_drain_rxtx(dev);
5320
5321         if (np->wolenabled) {
5322                 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5323                 nv_start_rx(dev);
5324         }
5325
5326         /* FIXME: power down nic */
5327
5328         return 0;
5329 }
5330
5331 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5332 {
5333         struct net_device *dev;
5334         struct fe_priv *np;
5335         unsigned long addr;
5336         u8 __iomem *base;
5337         int err, i;
5338         u32 powerstate, txreg;
5339         u32 phystate_orig = 0, phystate;
5340         int phyinitialized = 0;
5341         DECLARE_MAC_BUF(mac);
5342         static int printed_version;
5343
5344         if (!printed_version++)
5345                 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
5346                        " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
5347
5348         dev = alloc_etherdev(sizeof(struct fe_priv));
5349         err = -ENOMEM;
5350         if (!dev)
5351                 goto out;
5352
5353         np = netdev_priv(dev);
5354         np->dev = dev;
5355         np->pci_dev = pci_dev;
5356         spin_lock_init(&np->lock);
5357         SET_NETDEV_DEV(dev, &pci_dev->dev);
5358
5359         init_timer(&np->oom_kick);
5360         np->oom_kick.data = (unsigned long) dev;
5361         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
5362         init_timer(&np->nic_poll);
5363         np->nic_poll.data = (unsigned long) dev;
5364         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
5365         init_timer(&np->stats_poll);
5366         np->stats_poll.data = (unsigned long) dev;
5367         np->stats_poll.function = &nv_do_stats_poll;    /* timer handler */
5368
5369         err = pci_enable_device(pci_dev);
5370         if (err)
5371                 goto out_free;
5372
5373         pci_set_master(pci_dev);
5374
5375         err = pci_request_regions(pci_dev, DRV_NAME);
5376         if (err < 0)
5377                 goto out_disable;
5378
5379         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2))
5380                 np->register_size = NV_PCI_REGSZ_VER3;
5381         else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5382                 np->register_size = NV_PCI_REGSZ_VER2;
5383         else
5384                 np->register_size = NV_PCI_REGSZ_VER1;
5385
5386         err = -EINVAL;
5387         addr = 0;
5388         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5389                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
5390                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
5391                                 pci_resource_len(pci_dev, i),
5392                                 pci_resource_flags(pci_dev, i));
5393                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5394                                 pci_resource_len(pci_dev, i) >= np->register_size) {
5395                         addr = pci_resource_start(pci_dev, i);
5396                         break;
5397                 }
5398         }
5399         if (i == DEVICE_COUNT_RESOURCE) {
5400                 dev_printk(KERN_INFO, &pci_dev->dev,
5401                            "Couldn't find register window\n");
5402                 goto out_relreg;
5403         }
5404
5405         /* copy of driver data */
5406         np->driver_data = id->driver_data;
5407         /* copy of device id */
5408         np->device_id = id->device;
5409
5410         /* handle different descriptor versions */
5411         if (id->driver_data & DEV_HAS_HIGH_DMA) {
5412                 /* packet format 3: supports 40-bit addressing */
5413                 np->desc_ver = DESC_VER_3;
5414                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5415                 if (dma_64bit) {
5416                         if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK))
5417                                 dev_printk(KERN_INFO, &pci_dev->dev,
5418                                         "64-bit DMA failed, using 32-bit addressing\n");
5419                         else
5420                                 dev->features |= NETIF_F_HIGHDMA;
5421                         if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
5422                                 dev_printk(KERN_INFO, &pci_dev->dev,
5423                                         "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5424                         }
5425                 }
5426         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5427                 /* packet format 2: supports jumbo frames */
5428                 np->desc_ver = DESC_VER_2;
5429                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5430         } else {
5431                 /* original packet format */
5432                 np->desc_ver = DESC_VER_1;
5433                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5434         }
5435
5436         np->pkt_limit = NV_PKTLIMIT_1;
5437         if (id->driver_data & DEV_HAS_LARGEDESC)
5438                 np->pkt_limit = NV_PKTLIMIT_2;
5439
5440         if (id->driver_data & DEV_HAS_CHECKSUM) {
5441                 np->rx_csum = 1;
5442                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5443                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
5444                 dev->features |= NETIF_F_TSO;
5445         }
5446
5447         np->vlanctl_bits = 0;
5448         if (id->driver_data & DEV_HAS_VLAN) {
5449                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5450                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5451                 dev->vlan_rx_register = nv_vlan_rx_register;
5452         }
5453
5454         np->msi_flags = 0;
5455         if ((id->driver_data & DEV_HAS_MSI) && msi) {
5456                 np->msi_flags |= NV_MSI_CAPABLE;
5457         }
5458         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5459                 np->msi_flags |= NV_MSI_X_CAPABLE;
5460         }
5461
5462         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5463         if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5464             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5465             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5466                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5467         }
5468
5469
5470         err = -ENOMEM;
5471         np->base = ioremap(addr, np->register_size);
5472         if (!np->base)
5473                 goto out_relreg;
5474         dev->base_addr = (unsigned long)np->base;
5475
5476         dev->irq = pci_dev->irq;
5477
5478         np->rx_ring_size = RX_RING_DEFAULT;
5479         np->tx_ring_size = TX_RING_DEFAULT;
5480
5481         if (!nv_optimized(np)) {
5482                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5483                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5484                                         &np->ring_addr);
5485                 if (!np->rx_ring.orig)
5486                         goto out_unmap;
5487                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5488         } else {
5489                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5490                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5491                                         &np->ring_addr);
5492                 if (!np->rx_ring.ex)
5493                         goto out_unmap;
5494                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5495         }
5496         np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5497         np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5498         if (!np->rx_skb || !np->tx_skb)
5499                 goto out_freering;
5500
5501         dev->open = nv_open;
5502         dev->stop = nv_close;
5503
5504         if (!nv_optimized(np))
5505                 dev->hard_start_xmit = nv_start_xmit;
5506         else
5507                 dev->hard_start_xmit = nv_start_xmit_optimized;
5508         dev->get_stats = nv_get_stats;
5509         dev->change_mtu = nv_change_mtu;
5510         dev->set_mac_address = nv_set_mac_address;
5511         dev->set_multicast_list = nv_set_multicast;
5512 #ifdef CONFIG_NET_POLL_CONTROLLER
5513         dev->poll_controller = nv_poll_controller;
5514 #endif
5515 #ifdef CONFIG_FORCEDETH_NAPI
5516         netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5517 #endif
5518         SET_ETHTOOL_OPS(dev, &ops);
5519         dev->tx_timeout = nv_tx_timeout;
5520         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5521
5522         pci_set_drvdata(pci_dev, dev);
5523
5524         /* read the mac address */
5525         base = get_hwbase(dev);
5526         np->orig_mac[0] = readl(base + NvRegMacAddrA);
5527         np->orig_mac[1] = readl(base + NvRegMacAddrB);
5528
5529         /* check the workaround bit for correct mac address order */
5530         txreg = readl(base + NvRegTransmitPoll);
5531         if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5532                 /* mac address is already in correct order */
5533                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5534                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5535                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5536                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5537                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5538                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5539         } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5540                 /* mac address is already in correct order */
5541                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5542                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5543                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5544                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5545                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5546                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5547                 /*
5548                  * Set orig mac address back to the reversed version.
5549                  * This flag will be cleared during low power transition.
5550                  * Therefore, we should always put back the reversed address.
5551                  */
5552                 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5553                         (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5554                 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5555         } else {
5556                 /* need to reverse mac address to correct order */
5557                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
5558                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
5559                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5560                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5561                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
5562                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
5563                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5564         }
5565         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5566
5567         if (!is_valid_ether_addr(dev->perm_addr)) {
5568                 /*
5569                  * Bad mac address. At least one bios sets the mac address
5570                  * to 01:23:45:67:89:ab
5571                  */
5572                 dev_printk(KERN_ERR, &pci_dev->dev,
5573                         "Invalid Mac address detected: %s\n",
5574                         print_mac(mac, dev->dev_addr));
5575                 dev_printk(KERN_ERR, &pci_dev->dev,
5576                         "Please complain to your hardware vendor. Switching to a random MAC.\n");
5577                 dev->dev_addr[0] = 0x00;
5578                 dev->dev_addr[1] = 0x00;
5579                 dev->dev_addr[2] = 0x6c;
5580                 get_random_bytes(&dev->dev_addr[3], 3);
5581         }
5582
5583         dprintk(KERN_DEBUG "%s: MAC Address %s\n",
5584                 pci_name(pci_dev), print_mac(mac, dev->dev_addr));
5585
5586         /* set mac address */
5587         nv_copy_mac_to_hw(dev);
5588
5589         /* Workaround current PCI init glitch:  wakeup bits aren't
5590          * being set from PCI PM capability.
5591          */
5592         device_init_wakeup(&pci_dev->dev, 1);
5593
5594         /* disable WOL */
5595         writel(0, base + NvRegWakeUpFlags);
5596         np->wolenabled = 0;
5597
5598         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5599
5600                 /* take phy and nic out of low power mode */
5601                 powerstate = readl(base + NvRegPowerState2);
5602                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5603                 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
5604                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
5605                     pci_dev->revision >= 0xA3)
5606                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5607                 writel(powerstate, base + NvRegPowerState2);
5608         }
5609
5610         if (np->desc_ver == DESC_VER_1) {
5611                 np->tx_flags = NV_TX_VALID;
5612         } else {
5613                 np->tx_flags = NV_TX2_VALID;
5614         }
5615         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
5616                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5617                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5618                         np->msi_flags |= 0x0003;
5619         } else {
5620                 np->irqmask = NVREG_IRQMASK_CPU;
5621                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5622                         np->msi_flags |= 0x0001;
5623         }
5624
5625         if (id->driver_data & DEV_NEED_TIMERIRQ)
5626                 np->irqmask |= NVREG_IRQ_TIMER;
5627         if (id->driver_data & DEV_NEED_LINKTIMER) {
5628                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5629                 np->need_linktimer = 1;
5630                 np->link_timeout = jiffies + LINK_TIMEOUT;
5631         } else {
5632                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5633                 np->need_linktimer = 0;
5634         }
5635
5636         /* Limit the number of tx's outstanding for hw bug */
5637         if (id->driver_data & DEV_NEED_TX_LIMIT) {
5638                 np->tx_limit = 1;
5639                 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
5640                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
5641                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
5642                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
5643                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
5644                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
5645                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
5646                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_39) &&
5647                     pci_dev->revision >= 0xA2)
5648                         np->tx_limit = 0;
5649         }
5650
5651         /* clear phy state and temporarily halt phy interrupts */
5652         writel(0, base + NvRegMIIMask);
5653         phystate = readl(base + NvRegAdapterControl);
5654         if (phystate & NVREG_ADAPTCTL_RUNNING) {
5655                 phystate_orig = 1;
5656                 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5657                 writel(phystate, base + NvRegAdapterControl);
5658         }
5659         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5660
5661         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5662                 /* management unit running on the mac? */
5663                 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) {
5664                         np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST;
5665                         dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev), np->mac_in_use);
5666                         if (nv_mgmt_acquire_sema(dev)) {
5667                                 /* management unit setup the phy already? */
5668                                 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5669                                     NVREG_XMITCTL_SYNC_PHY_INIT) {
5670                                         /* phy is inited by mgmt unit */
5671                                         phyinitialized = 1;
5672                                         dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev));
5673                                 } else {
5674                                         /* we need to init the phy */
5675                                 }
5676                         }
5677                 }
5678         }
5679
5680         /* find a suitable phy */
5681         for (i = 1; i <= 32; i++) {
5682                 int id1, id2;
5683                 int phyaddr = i & 0x1F;
5684
5685                 spin_lock_irq(&np->lock);
5686                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5687                 spin_unlock_irq(&np->lock);
5688                 if (id1 < 0 || id1 == 0xffff)
5689                         continue;
5690                 spin_lock_irq(&np->lock);
5691                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5692                 spin_unlock_irq(&np->lock);
5693                 if (id2 < 0 || id2 == 0xffff)
5694                         continue;
5695
5696                 np->phy_model = id2 & PHYID2_MODEL_MASK;
5697                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5698                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5699                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
5700                         pci_name(pci_dev), id1, id2, phyaddr);
5701                 np->phyaddr = phyaddr;
5702                 np->phy_oui = id1 | id2;
5703
5704                 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5705                 if (np->phy_oui == PHY_OUI_REALTEK2)
5706                         np->phy_oui = PHY_OUI_REALTEK;
5707                 /* Setup phy revision for Realtek */
5708                 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5709                         np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5710
5711                 break;
5712         }
5713         if (i == 33) {
5714                 dev_printk(KERN_INFO, &pci_dev->dev,
5715                         "open: Could not find a valid PHY.\n");
5716                 goto out_error;
5717         }
5718
5719         if (!phyinitialized) {
5720                 /* reset it */
5721                 phy_init(dev);
5722         } else {
5723                 /* see if it is a gigabit phy */
5724                 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5725                 if (mii_status & PHY_GIGABIT) {
5726                         np->gigabit = PHY_GIGABIT;
5727                 }
5728         }
5729
5730         /* set default link speed settings */
5731         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5732         np->duplex = 0;
5733         np->autoneg = 1;
5734
5735         err = register_netdev(dev);
5736         if (err) {
5737                 dev_printk(KERN_INFO, &pci_dev->dev,
5738                            "unable to register netdev: %d\n", err);
5739                 goto out_error;
5740         }
5741
5742         dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, "
5743                    "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
5744                    dev->name,
5745                    np->phy_oui,
5746                    np->phyaddr,
5747                    dev->dev_addr[0],
5748                    dev->dev_addr[1],
5749                    dev->dev_addr[2],
5750                    dev->dev_addr[3],
5751                    dev->dev_addr[4],
5752                    dev->dev_addr[5]);
5753
5754         dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5755                    dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5756                    dev->features & (NETIF_F_HW_CSUM | NETIF_F_SG) ?
5757                         "csum " : "",
5758                    dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5759                         "vlan " : "",
5760                    id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5761                    id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5762                    id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5763                    np->gigabit == PHY_GIGABIT ? "gbit " : "",
5764                    np->need_linktimer ? "lnktim " : "",
5765                    np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5766                    np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5767                    np->desc_ver);
5768
5769         return 0;
5770
5771 out_error:
5772         if (phystate_orig)
5773                 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5774         pci_set_drvdata(pci_dev, NULL);
5775 out_freering:
5776         free_rings(dev);
5777 out_unmap:
5778         iounmap(get_hwbase(dev));
5779 out_relreg:
5780         pci_release_regions(pci_dev);
5781 out_disable:
5782         pci_disable_device(pci_dev);
5783 out_free:
5784         free_netdev(dev);
5785 out:
5786         return err;
5787 }
5788
5789 static void nv_restore_phy(struct net_device *dev)
5790 {
5791         struct fe_priv *np = netdev_priv(dev);
5792         u16 phy_reserved, mii_control;
5793
5794         if (np->phy_oui == PHY_OUI_REALTEK &&
5795             np->phy_model == PHY_MODEL_REALTEK_8201 &&
5796             phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
5797                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
5798                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
5799                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
5800                 phy_reserved |= PHY_REALTEK_INIT8;
5801                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
5802                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
5803
5804                 /* restart auto negotiation */
5805                 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
5806                 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
5807                 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
5808         }
5809 }
5810
5811 static void __devexit nv_remove(struct pci_dev *pci_dev)
5812 {
5813         struct net_device *dev = pci_get_drvdata(pci_dev);
5814         struct fe_priv *np = netdev_priv(dev);
5815         u8 __iomem *base = get_hwbase(dev);
5816
5817         unregister_netdev(dev);
5818
5819         /* special op: write back the misordered MAC address - otherwise
5820          * the next nv_probe would see a wrong address.
5821          */
5822         writel(np->orig_mac[0], base + NvRegMacAddrA);
5823         writel(np->orig_mac[1], base + NvRegMacAddrB);
5824         writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5825                base + NvRegTransmitPoll);
5826
5827         /* restore any phy related changes */
5828         nv_restore_phy(dev);
5829
5830         /* free all structures */
5831         free_rings(dev);
5832         iounmap(get_hwbase(dev));
5833         pci_release_regions(pci_dev);
5834         pci_disable_device(pci_dev);
5835         free_netdev(dev);
5836         pci_set_drvdata(pci_dev, NULL);
5837 }
5838
5839 #ifdef CONFIG_PM
5840 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
5841 {
5842         struct net_device *dev = pci_get_drvdata(pdev);
5843         struct fe_priv *np = netdev_priv(dev);
5844         u8 __iomem *base = get_hwbase(dev);
5845         int i;
5846
5847         if (netif_running(dev)) {
5848                 // Gross.
5849                 nv_close(dev);
5850         }
5851         netif_device_detach(dev);
5852
5853         /* save non-pci configuration space */
5854         for (i = 0;i <= np->register_size/sizeof(u32); i++)
5855                 np->saved_config_space[i] = readl(base + i*sizeof(u32));
5856
5857         pci_save_state(pdev);
5858         pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
5859         pci_disable_device(pdev);
5860         pci_set_power_state(pdev, pci_choose_state(pdev, state));
5861         return 0;
5862 }
5863
5864 static int nv_resume(struct pci_dev *pdev)
5865 {
5866         struct net_device *dev = pci_get_drvdata(pdev);
5867         struct fe_priv *np = netdev_priv(dev);
5868         u8 __iomem *base = get_hwbase(dev);
5869         int i, rc = 0;
5870
5871         pci_set_power_state(pdev, PCI_D0);
5872         pci_restore_state(pdev);
5873         /* ack any pending wake events, disable PME */
5874         pci_enable_wake(pdev, PCI_D0, 0);
5875
5876         /* restore non-pci configuration space */
5877         for (i = 0;i <= np->register_size/sizeof(u32); i++)
5878                 writel(np->saved_config_space[i], base+i*sizeof(u32));
5879
5880         netif_device_attach(dev);
5881         if (netif_running(dev)) {
5882                 rc = nv_open(dev);
5883                 nv_set_multicast(dev);
5884         }
5885         return rc;
5886 }
5887
5888 static void nv_shutdown(struct pci_dev *pdev)
5889 {
5890         struct net_device *dev = pci_get_drvdata(pdev);
5891         struct fe_priv *np = netdev_priv(dev);
5892
5893         if (netif_running(dev))
5894                 nv_close(dev);
5895
5896         pci_enable_wake(pdev, PCI_D3hot, np->wolenabled);
5897         pci_enable_wake(pdev, PCI_D3cold, np->wolenabled);
5898         pci_disable_device(pdev);
5899         pci_set_power_state(pdev, PCI_D3hot);
5900 }
5901 #else
5902 #define nv_suspend NULL
5903 #define nv_shutdown NULL
5904 #define nv_resume NULL
5905 #endif /* CONFIG_PM */
5906
5907 static struct pci_device_id pci_tbl[] = {
5908         {       /* nForce Ethernet Controller */
5909                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
5910                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5911         },
5912         {       /* nForce2 Ethernet Controller */
5913                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
5914                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5915         },
5916         {       /* nForce3 Ethernet Controller */
5917                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
5918                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5919         },
5920         {       /* nForce3 Ethernet Controller */
5921                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
5922                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5923         },
5924         {       /* nForce3 Ethernet Controller */
5925                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
5926                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5927         },
5928         {       /* nForce3 Ethernet Controller */
5929                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
5930                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5931         },
5932         {       /* nForce3 Ethernet Controller */
5933                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
5934                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5935         },
5936         {       /* CK804 Ethernet Controller */
5937                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
5938                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5939         },
5940         {       /* CK804 Ethernet Controller */
5941                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
5942                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5943         },
5944         {       /* MCP04 Ethernet Controller */
5945                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
5946                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5947         },
5948         {       /* MCP04 Ethernet Controller */
5949                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
5950                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5951         },
5952         {       /* MCP51 Ethernet Controller */
5953                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
5954                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
5955         },
5956         {       /* MCP51 Ethernet Controller */
5957                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
5958                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
5959         },
5960         {       /* MCP55 Ethernet Controller */
5961                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
5962                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT,
5963         },
5964         {       /* MCP55 Ethernet Controller */
5965                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
5966                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT,
5967         },
5968         {       /* MCP61 Ethernet Controller */
5969                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
5970                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5971         },
5972         {       /* MCP61 Ethernet Controller */
5973                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
5974                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5975         },
5976         {       /* MCP61 Ethernet Controller */
5977                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
5978                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5979         },
5980         {       /* MCP61 Ethernet Controller */
5981                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
5982                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5983         },
5984         {       /* MCP65 Ethernet Controller */
5985                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
5986                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
5987         },
5988         {       /* MCP65 Ethernet Controller */
5989                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
5990                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
5991         },
5992         {       /* MCP65 Ethernet Controller */
5993                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
5994                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
5995         },
5996         {       /* MCP65 Ethernet Controller */
5997                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
5998                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
5999         },
6000         {       /* MCP67 Ethernet Controller */
6001                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
6002                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
6003         },
6004         {       /* MCP67 Ethernet Controller */
6005                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
6006                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
6007         },
6008         {       /* MCP67 Ethernet Controller */
6009                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
6010                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
6011         },
6012         {       /* MCP67 Ethernet Controller */
6013                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
6014                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
6015         },
6016         {       /* MCP73 Ethernet Controller */
6017                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_28),
6018                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
6019         },
6020         {       /* MCP73 Ethernet Controller */
6021                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_29),
6022                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
6023         },
6024         {       /* MCP73 Ethernet Controller */
6025                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_30),
6026                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
6027         },
6028         {       /* MCP73 Ethernet Controller */
6029                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_31),
6030                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
6031         },
6032         {       /* MCP77 Ethernet Controller */
6033                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32),
6034                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6035         },
6036         {       /* MCP77 Ethernet Controller */
6037                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33),
6038                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6039         },
6040         {       /* MCP77 Ethernet Controller */
6041                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34),
6042                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6043         },
6044         {       /* MCP77 Ethernet Controller */
6045                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35),
6046                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6047         },
6048         {       /* MCP79 Ethernet Controller */
6049                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36),
6050                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6051         },
6052         {       /* MCP79 Ethernet Controller */
6053                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37),
6054                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6055         },
6056         {       /* MCP79 Ethernet Controller */
6057                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38),
6058                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6059         },
6060         {       /* MCP79 Ethernet Controller */
6061                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39),
6062                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6063         },
6064         {0,},
6065 };
6066
6067 static struct pci_driver driver = {
6068         .name           = DRV_NAME,
6069         .id_table       = pci_tbl,
6070         .probe          = nv_probe,
6071         .remove         = __devexit_p(nv_remove),
6072         .suspend        = nv_suspend,
6073         .resume         = nv_resume,
6074         .shutdown       = nv_shutdown,
6075 };
6076
6077 static int __init init_nic(void)
6078 {
6079         return pci_register_driver(&driver);
6080 }
6081
6082 static void __exit exit_nic(void)
6083 {
6084         pci_unregister_driver(&driver);
6085 }
6086
6087 module_param(max_interrupt_work, int, 0);
6088 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
6089 module_param(optimization_mode, int, 0);
6090 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
6091 module_param(poll_interval, int, 0);
6092 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6093 module_param(msi, int, 0);
6094 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6095 module_param(msix, int, 0);
6096 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6097 module_param(dma_64bit, int, 0);
6098 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6099 module_param(phy_cross, int, 0);
6100 MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6101
6102 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6103 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6104 MODULE_LICENSE("GPL");
6105
6106 MODULE_DEVICE_TABLE(pci, pci_tbl);
6107
6108 module_init(init_nic);
6109 module_exit(exit_nic);