drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey.
   7  *
   8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
   9  * trademarks of NVIDIA Corporation in the United States and other
  10  * countries.
  11  *
  12  * Copyright (C) 2003,4,5 Manfred Spraul
  13  * Copyright (C) 2004 Andrew de Quincey (wol support)
  14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  16  * Copyright (c) 2004,5,6 NVIDIA Corporation
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License as published by
  20  * the Free Software Foundation; either version 2 of the License, or
  21  * (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  31  *
  32  * Changelog:
  33  *      0.01: 05 Oct 2003: First release that compiles without warnings.
  34  *      0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
  35  *                         Check all PCI BARs for the register window.
  36  *                         udelay added to mii_rw.
  37  *      0.03: 06 Oct 2003: Initialize dev->irq.
  38  *      0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
  39  *      0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
  40  *      0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
  41  *                         irq mask updated
  42  *      0.07: 14 Oct 2003: Further irq mask updates.
  43  *      0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
  44  *                         added into irq handler, NULL check for drain_ring.
  45  *      0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
  46  *                         requested interrupt sources.
  47  *      0.10: 20 Oct 2003: First cleanup for release.
  48  *      0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
  49  *                         MAC Address init fix, set_multicast cleanup.
  50  *      0.12: 23 Oct 2003: Cleanups for release.
  51  *      0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
  52  *                         Set link speed correctly. start rx before starting
  53  *                         tx (nv_start_rx sets the link speed).
  54  *      0.14: 25 Oct 2003: Nic dependant irq mask.
  55  *      0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
  56  *                         open.
  57  *      0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
  58  *                         increased to 1628 bytes.
  59  *      0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
  60  *                         the tx length.
  61  *      0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
  62  *      0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
  63  *                         addresses, really stop rx if already running
  64  *                         in nv_start_rx, clean up a bit.
  65  *      0.20: 07 Dec 2003: alloc fixes
  66  *      0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
  67  *      0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
  68  *                         on close.
  69  *      0.23: 26 Jan 2004: various small cleanups
  70  *      0.24: 27 Feb 2004: make driver even less anonymous in backtraces
  71  *      0.25: 09 Mar 2004: wol support
  72  *      0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
  73  *      0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
  74  *                         added CK804/MCP04 device IDs, code fixes
  75  *                         for registers, link status and other minor fixes.
  76  *      0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
  77  *      0.29: 31 Aug 2004: Add backup timer for link change notification.
  78  *      0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
  79  *                         into nv_close, otherwise reenabling for wol can
  80  *                         cause DMA to kfree'd memory.
  81  *      0.31: 14 Nov 2004: ethtool support for getting/setting link
  82  *                         capabilities.
  83  *      0.32: 16 Apr 2005: RX_ERROR4 handling added.
  84  *      0.33: 16 May 2005: Support for MCP51 added.
  85  *      0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
  86  *      0.35: 26 Jun 2005: Support for MCP55 added.
  87  *      0.36: 28 Jun 2005: Add jumbo frame support.
  88  *      0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
  89  *      0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
  90  *                         per-packet flags.
  91  *      0.39: 18 Jul 2005: Add 64bit descriptor support.
  92  *      0.40: 19 Jul 2005: Add support for mac address change.
  93  *      0.41: 30 Jul 2005: Write back original MAC in nv_close instead
  94  *                         of nv_remove
  95  *      0.42: 06 Aug 2005: Fix lack of link speed initialization
  96  *                         in the second (and later) nv_open call
  97  *      0.43: 10 Aug 2005: Add support for tx checksum.
  98  *      0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
  99  *      0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
 100  *      0.46: 20 Oct 2005: Add irq optimization modes.
 101  *      0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
 102  *      0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
 103  *      0.49: 10 Dec 2005: Fix tso for large buffers.
 104  *      0.50: 20 Jan 2006: Add 8021pq tagging support.
 105  *      0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
 106  *      0.52: 20 Jan 2006: Add MSI/MSIX support.
 107  *      0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
 108  *      0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
 109  *      0.55: 22 Mar 2006: Add flow control (pause frame).
 110  *      0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
 111  *      0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
 112  *      0.58: 30 Oct 2006: Added support for sideband management unit.
 113  *      0.59: 30 Oct 2006: Added support for recoverable error.
 114  *
 115  * Known bugs:
 116  * We suspect that on some hardware no TX done interrupts are generated.
 117  * This means recovery from netif_stop_queue only happens if the hw timer
 118  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
 119  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
 120  * If your hardware reliably generates tx done interrupts, then you can remove
 121  * DEV_NEED_TIMERIRQ from the driver_data flags.
 122  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
 123  * superfluous timer interrupts from the nic.
 124  */
 125 #ifdef CONFIG_FORCEDETH_NAPI
 126 #define DRIVERNAPI "-NAPI"
 127 #else
 128 #define DRIVERNAPI
 129 #endif
 130 #define FORCEDETH_VERSION               "0.59"
 131 #define DRV_NAME                        "forcedeth"
 132
 133 #include <linux/module.h>
 134 #include <linux/types.h>
 135 #include <linux/pci.h>
 136 #include <linux/interrupt.h>
 137 #include <linux/netdevice.h>
 138 #include <linux/etherdevice.h>
 139 #include <linux/delay.h>
 140 #include <linux/spinlock.h>
 141 #include <linux/ethtool.h>
 142 #include <linux/timer.h>
 143 #include <linux/skbuff.h>
 144 #include <linux/mii.h>
 145 #include <linux/random.h>
 146 #include <linux/init.h>
 147 #include <linux/if_vlan.h>
 148 #include <linux/dma-mapping.h>
 149
 150 #include <asm/irq.h>
 151 #include <asm/io.h>
 152 #include <asm/uaccess.h>
 153 #include <asm/system.h>
 154
 155 #if 0
 156 #define dprintk                 printk
 157 #else
 158 #define dprintk(x...)           do { } while (0)
 159 #endif
 160
 161
 162 /*
 163  * Hardware access:
 164  */
 165
 166 #define DEV_NEED_TIMERIRQ       0x0001  /* set the timer irq flag in the irq mask */
 167 #define DEV_NEED_LINKTIMER      0x0002  /* poll link settings. Relies on the timer irq */
 168 #define DEV_HAS_LARGEDESC       0x0004  /* device supports jumbo frames and needs packet format 2 */
 169 #define DEV_HAS_HIGH_DMA        0x0008  /* device supports 64bit dma */
 170 #define DEV_HAS_CHECKSUM        0x0010  /* device supports tx and rx checksum offloads */
 171 #define DEV_HAS_VLAN            0x0020  /* device supports vlan tagging and striping */
 172 #define DEV_HAS_MSI             0x0040  /* device supports MSI */
 173 #define DEV_HAS_MSI_X           0x0080  /* device supports MSI-X */
 174 #define DEV_HAS_POWER_CNTRL     0x0100  /* device supports power savings */
 175 #define DEV_HAS_PAUSEFRAME_TX   0x0200  /* device supports tx pause frames */
 176 #define DEV_HAS_STATISTICS      0x0400  /* device supports hw statistics */
 177 #define DEV_HAS_TEST_EXTENDED   0x0800  /* device supports extended diagnostic test */
 178 #define DEV_HAS_MGMT_UNIT       0x1000  /* device supports management unit */
 179
 180 enum {
 181         NvRegIrqStatus = 0x000,
 182 #define NVREG_IRQSTAT_MIIEVENT  0x040
 183 #define NVREG_IRQSTAT_MASK              0x81ff
 184         NvRegIrqMask = 0x004,
 185 #define NVREG_IRQ_RX_ERROR              0x0001
 186 #define NVREG_IRQ_RX                    0x0002
 187 #define NVREG_IRQ_RX_NOBUF              0x0004
 188 #define NVREG_IRQ_TX_ERR                0x0008
 189 #define NVREG_IRQ_TX_OK                 0x0010
 190 #define NVREG_IRQ_TIMER                 0x0020
 191 #define NVREG_IRQ_LINK                  0x0040
 192 #define NVREG_IRQ_RX_FORCED             0x0080
 193 #define NVREG_IRQ_TX_FORCED             0x0100
 194 #define NVREG_IRQ_RECOVER_ERROR         0x8000
 195 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 196 #define NVREG_IRQMASK_CPU               0x0040
 197 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 198 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 199 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
 200
 201 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
 202                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
 203                                         NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
 204
 205         NvRegUnknownSetupReg6 = 0x008,
 206 #define NVREG_UNKSETUP6_VAL             3
 207
 208 /*
 209  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 210  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 211  */
 212         NvRegPollingInterval = 0x00c,
 213 #define NVREG_POLL_DEFAULT_THROUGHPUT   970
 214 #define NVREG_POLL_DEFAULT_CPU  13
 215         NvRegMSIMap0 = 0x020,
 216         NvRegMSIMap1 = 0x024,
 217         NvRegMSIIrqMask = 0x030,
 218 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 219         NvRegMisc1 = 0x080,
 220 #define NVREG_MISC1_PAUSE_TX    0x01
 221 #define NVREG_MISC1_HD          0x02
 222 #define NVREG_MISC1_FORCE       0x3b0f3c
 223
 224         NvRegMacReset = 0x3c,
 225 #define NVREG_MAC_RESET_ASSERT  0x0F3
 226         NvRegTransmitterControl = 0x084,
 227 #define NVREG_XMITCTL_START     0x01
 228 #define NVREG_XMITCTL_MGMT_ST   0x40000000
 229 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
 230 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
 231 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
 232 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
 233 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
 234 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
 235 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
 236 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
 237         NvRegTransmitterStatus = 0x088,
 238 #define NVREG_XMITSTAT_BUSY     0x01
 239
 240         NvRegPacketFilterFlags = 0x8c,
 241 #define NVREG_PFF_PAUSE_RX      0x08
 242 #define NVREG_PFF_ALWAYS        0x7F0000
 243 #define NVREG_PFF_PROMISC       0x80
 244 #define NVREG_PFF_MYADDR        0x20
 245 #define NVREG_PFF_LOOPBACK      0x10
 246
 247         NvRegOffloadConfig = 0x90,
 248 #define NVREG_OFFLOAD_HOMEPHY   0x601
 249 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 250         NvRegReceiverControl = 0x094,
 251 #define NVREG_RCVCTL_START      0x01
 252         NvRegReceiverStatus = 0x98,
 253 #define NVREG_RCVSTAT_BUSY      0x01
 254
 255         NvRegRandomSeed = 0x9c,
 256 #define NVREG_RNDSEED_MASK      0x00ff
 257 #define NVREG_RNDSEED_FORCE     0x7f00
 258 #define NVREG_RNDSEED_FORCE2    0x2d00
 259 #define NVREG_RNDSEED_FORCE3    0x7400
 260
 261         NvRegTxDeferral = 0xA0,
 262 #define NVREG_TX_DEFERRAL_DEFAULT       0x15050f
 263 #define NVREG_TX_DEFERRAL_RGMII_10_100  0x16070f
 264 #define NVREG_TX_DEFERRAL_RGMII_1000    0x14050f
 265         NvRegRxDeferral = 0xA4,
 266 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
 267         NvRegMacAddrA = 0xA8,
 268         NvRegMacAddrB = 0xAC,
 269         NvRegMulticastAddrA = 0xB0,
 270 #define NVREG_MCASTADDRA_FORCE  0x01
 271         NvRegMulticastAddrB = 0xB4,
 272         NvRegMulticastMaskA = 0xB8,
 273         NvRegMulticastMaskB = 0xBC,
 274
 275         NvRegPhyInterface = 0xC0,
 276 #define PHY_RGMII               0x10000000
 277
 278         NvRegTxRingPhysAddr = 0x100,
 279         NvRegRxRingPhysAddr = 0x104,
 280         NvRegRingSizes = 0x108,
 281 #define NVREG_RINGSZ_TXSHIFT 0
 282 #define NVREG_RINGSZ_RXSHIFT 16
 283         NvRegTransmitPoll = 0x10c,
 284 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
 285         NvRegLinkSpeed = 0x110,
 286 #define NVREG_LINKSPEED_FORCE 0x10000
 287 #define NVREG_LINKSPEED_10      1000
 288 #define NVREG_LINKSPEED_100     100
 289 #define NVREG_LINKSPEED_1000    50
 290 #define NVREG_LINKSPEED_MASK    (0xFFF)
 291         NvRegUnknownSetupReg5 = 0x130,
 292 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 293         NvRegTxWatermark = 0x13c,
 294 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
 295 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
 296 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
 297         NvRegTxRxControl = 0x144,
 298 #define NVREG_TXRXCTL_KICK      0x0001
 299 #define NVREG_TXRXCTL_BIT1      0x0002
 300 #define NVREG_TXRXCTL_BIT2      0x0004
 301 #define NVREG_TXRXCTL_IDLE      0x0008
 302 #define NVREG_TXRXCTL_RESET     0x0010
 303 #define NVREG_TXRXCTL_RXCHECK   0x0400
 304 #define NVREG_TXRXCTL_DESC_1    0
 305 #define NVREG_TXRXCTL_DESC_2    0x02100
 306 #define NVREG_TXRXCTL_DESC_3    0x02200
 307 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 308 #define NVREG_TXRXCTL_VLANINS   0x00080
 309         NvRegTxRingPhysAddrHigh = 0x148,
 310         NvRegRxRingPhysAddrHigh = 0x14C,
 311         NvRegTxPauseFrame = 0x170,
 312 #define NVREG_TX_PAUSEFRAME_DISABLE     0x1ff0080
 313 #define NVREG_TX_PAUSEFRAME_ENABLE      0x0c00030
 314         NvRegMIIStatus = 0x180,
 315 #define NVREG_MIISTAT_ERROR             0x0001
 316 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 317 #define NVREG_MIISTAT_MASK              0x000f
 318 #define NVREG_MIISTAT_MASK2             0x000f
 319         NvRegMIIMask = 0x184,
 320 #define NVREG_MII_LINKCHANGE            0x0008
 321
 322         NvRegAdapterControl = 0x188,
 323 #define NVREG_ADAPTCTL_START    0x02
 324 #define NVREG_ADAPTCTL_LINKUP   0x04
 325 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 326 #define NVREG_ADAPTCTL_RUNNING  0x100000
 327 #define NVREG_ADAPTCTL_PHYSHIFT 24
 328         NvRegMIISpeed = 0x18c,
 329 #define NVREG_MIISPEED_BIT8     (1<<8)
 330 #define NVREG_MIIDELAY  5
 331         NvRegMIIControl = 0x190,
 332 #define NVREG_MIICTL_INUSE      0x08000
 333 #define NVREG_MIICTL_WRITE      0x00400
 334 #define NVREG_MIICTL_ADDRSHIFT  5
 335         NvRegMIIData = 0x194,
 336         NvRegWakeUpFlags = 0x200,
 337 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 338 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 339 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 340 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 341 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 342 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 343 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 344 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 345 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 346 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 347 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 348
 349         NvRegPatternCRC = 0x204,
 350         NvRegPatternMask = 0x208,
 351         NvRegPowerCap = 0x268,
 352 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 353 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 354 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 355         NvRegPowerState = 0x26c,
 356 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 357 #define NVREG_POWERSTATE_VALID          0x0100
 358 #define NVREG_POWERSTATE_MASK           0x0003
 359 #define NVREG_POWERSTATE_D0             0x0000
 360 #define NVREG_POWERSTATE_D1             0x0001
 361 #define NVREG_POWERSTATE_D2             0x0002
 362 #define NVREG_POWERSTATE_D3             0x0003
 363         NvRegTxCnt = 0x280,
 364         NvRegTxZeroReXmt = 0x284,
 365         NvRegTxOneReXmt = 0x288,
 366         NvRegTxManyReXmt = 0x28c,
 367         NvRegTxLateCol = 0x290,
 368         NvRegTxUnderflow = 0x294,
 369         NvRegTxLossCarrier = 0x298,
 370         NvRegTxExcessDef = 0x29c,
 371         NvRegTxRetryErr = 0x2a0,
 372         NvRegRxFrameErr = 0x2a4,
 373         NvRegRxExtraByte = 0x2a8,
 374         NvRegRxLateCol = 0x2ac,
 375         NvRegRxRunt = 0x2b0,
 376         NvRegRxFrameTooLong = 0x2b4,
 377         NvRegRxOverflow = 0x2b8,
 378         NvRegRxFCSErr = 0x2bc,
 379         NvRegRxFrameAlignErr = 0x2c0,
 380         NvRegRxLenErr = 0x2c4,
 381         NvRegRxUnicast = 0x2c8,
 382         NvRegRxMulticast = 0x2cc,
 383         NvRegRxBroadcast = 0x2d0,
 384         NvRegTxDef = 0x2d4,
 385         NvRegTxFrame = 0x2d8,
 386         NvRegRxCnt = 0x2dc,
 387         NvRegTxPause = 0x2e0,
 388         NvRegRxPause = 0x2e4,
 389         NvRegRxDropFrame = 0x2e8,
 390         NvRegVlanControl = 0x300,
 391 #define NVREG_VLANCONTROL_ENABLE        0x2000
 392         NvRegMSIXMap0 = 0x3e0,
 393         NvRegMSIXMap1 = 0x3e4,
 394         NvRegMSIXIrqStatus = 0x3f0,
 395
 396         NvRegPowerState2 = 0x600,
 397 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F11
 398 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 399 };
 400
 401 /* Big endian: should work, but is untested */
 402 struct ring_desc {
 403         __le32 buf;
 404         __le32 flaglen;
 405 };
 406
 407 struct ring_desc_ex {
 408         __le32 bufhigh;
 409         __le32 buflow;
 410         __le32 txvlan;
 411         __le32 flaglen;
 412 };
 413
 414 union ring_type {
 415         struct ring_desc* orig;
 416         struct ring_desc_ex* ex;
 417 };
 418
 419 #define FLAG_MASK_V1 0xffff0000
 420 #define FLAG_MASK_V2 0xffffc000
 421 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 422 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 423
 424 #define NV_TX_LASTPACKET        (1<<16)
 425 #define NV_TX_RETRYERROR        (1<<19)
 426 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 427 #define NV_TX_DEFERRED          (1<<26)
 428 #define NV_TX_CARRIERLOST       (1<<27)
 429 #define NV_TX_LATECOLLISION     (1<<28)
 430 #define NV_TX_UNDERFLOW         (1<<29)
 431 #define NV_TX_ERROR             (1<<30)
 432 #define NV_TX_VALID             (1<<31)
 433
 434 #define NV_TX2_LASTPACKET       (1<<29)
 435 #define NV_TX2_RETRYERROR       (1<<18)
 436 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 437 #define NV_TX2_DEFERRED         (1<<25)
 438 #define NV_TX2_CARRIERLOST      (1<<26)
 439 #define NV_TX2_LATECOLLISION    (1<<27)
 440 #define NV_TX2_UNDERFLOW        (1<<28)
 441 /* error and valid are the same for both */
 442 #define NV_TX2_ERROR            (1<<30)
 443 #define NV_TX2_VALID            (1<<31)
 444 #define NV_TX2_TSO              (1<<28)
 445 #define NV_TX2_TSO_SHIFT        14
 446 #define NV_TX2_TSO_MAX_SHIFT    14
 447 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 448 #define NV_TX2_CHECKSUM_L3      (1<<27)
 449 #define NV_TX2_CHECKSUM_L4      (1<<26)
 450
 451 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 452
 453 #define NV_RX_DESCRIPTORVALID   (1<<16)
 454 #define NV_RX_MISSEDFRAME       (1<<17)
 455 #define NV_RX_SUBSTRACT1        (1<<18)
 456 #define NV_RX_ERROR1            (1<<23)
 457 #define NV_RX_ERROR2            (1<<24)
 458 #define NV_RX_ERROR3            (1<<25)
 459 #define NV_RX_ERROR4            (1<<26)
 460 #define NV_RX_CRCERR            (1<<27)
 461 #define NV_RX_OVERFLOW          (1<<28)
 462 #define NV_RX_FRAMINGERR        (1<<29)
 463 #define NV_RX_ERROR             (1<<30)
 464 #define NV_RX_AVAIL             (1<<31)
 465
 466 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 467 #define NV_RX2_CHECKSUMOK1      (0x10000000)
 468 #define NV_RX2_CHECKSUMOK2      (0x14000000)
 469 #define NV_RX2_CHECKSUMOK3      (0x18000000)
 470 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 471 #define NV_RX2_SUBSTRACT1       (1<<25)
 472 #define NV_RX2_ERROR1           (1<<18)
 473 #define NV_RX2_ERROR2           (1<<19)
 474 #define NV_RX2_ERROR3           (1<<20)
 475 #define NV_RX2_ERROR4           (1<<21)
 476 #define NV_RX2_CRCERR           (1<<22)
 477 #define NV_RX2_OVERFLOW         (1<<23)
 478 #define NV_RX2_FRAMINGERR       (1<<24)
 479 /* error and avail are the same for both */
 480 #define NV_RX2_ERROR            (1<<30)
 481 #define NV_RX2_AVAIL            (1<<31)
 482
 483 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 484 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 485
 486 /* Miscelaneous hardware related defines: */
 487 #define NV_PCI_REGSZ_VER1       0x270
 488 #define NV_PCI_REGSZ_VER2       0x604
 489
 490 /* various timeout delays: all in usec */
 491 #define NV_TXRX_RESET_DELAY     4
 492 #define NV_TXSTOP_DELAY1        10
 493 #define NV_TXSTOP_DELAY1MAX     500000
 494 #define NV_TXSTOP_DELAY2        100
 495 #define NV_RXSTOP_DELAY1        10
 496 #define NV_RXSTOP_DELAY1MAX     500000
 497 #define NV_RXSTOP_DELAY2        100
 498 #define NV_SETUP5_DELAY         5
 499 #define NV_SETUP5_DELAYMAX      50000
 500 #define NV_POWERUP_DELAY        5
 501 #define NV_POWERUP_DELAYMAX     5000
 502 #define NV_MIIBUSY_DELAY        50
 503 #define NV_MIIPHY_DELAY 10
 504 #define NV_MIIPHY_DELAYMAX      10000
 505 #define NV_MAC_RESET_DELAY      64
 506
 507 #define NV_WAKEUPPATTERNS       5
 508 #define NV_WAKEUPMASKENTRIES    4
 509
 510 /* General driver defaults */
 511 #define NV_WATCHDOG_TIMEO       (5*HZ)
 512
 513 #define RX_RING_DEFAULT         128
 514 #define TX_RING_DEFAULT         256
 515 #define RX_RING_MIN             128
 516 #define TX_RING_MIN             64
 517 #define RING_MAX_DESC_VER_1     1024
 518 #define RING_MAX_DESC_VER_2_3   16384
 519 /*
 520  * Difference between the get and put pointers for the tx ring.
 521  * This is used to throttle the amount of data outstanding in the
 522  * tx ring.
 523  */
 524 #define TX_LIMIT_DIFFERENCE     1
 525
 526 /* rx/tx mac addr + type + vlan + align + slack*/
 527 #define NV_RX_HEADERS           (64)
 528 /* even more slack. */
 529 #define NV_RX_ALLOC_PAD         (64)
 530
 531 /* maximum mtu size */
 532 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 533 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 534
 535 #define OOM_REFILL      (1+HZ/20)
 536 #define POLL_WAIT       (1+HZ/100)
 537 #define LINK_TIMEOUT    (3*HZ)
 538 #define STATS_INTERVAL  (10*HZ)
 539
 540 /*
 541  * desc_ver values:
 542  * The nic supports three different descriptor types:
 543  * - DESC_VER_1: Original
 544  * - DESC_VER_2: support for jumbo frames.
 545  * - DESC_VER_3: 64-bit format.
 546  */
 547 #define DESC_VER_1      1
 548 #define DESC_VER_2      2
 549 #define DESC_VER_3      3
 550
 551 /* PHY defines */
 552 #define PHY_OUI_MARVELL 0x5043
 553 #define PHY_OUI_CICADA  0x03f1
 554 #define PHYID1_OUI_MASK 0x03ff
 555 #define PHYID1_OUI_SHFT 6
 556 #define PHYID2_OUI_MASK 0xfc00
 557 #define PHYID2_OUI_SHFT 10
 558 #define PHYID2_MODEL_MASK               0x03f0
 559 #define PHY_MODEL_MARVELL_E3016         0x220
 560 #define PHY_MARVELL_E3016_INITMASK      0x0300
 561 #define PHY_INIT1       0x0f000
 562 #define PHY_INIT2       0x0e00
 563 #define PHY_INIT3       0x01000
 564 #define PHY_INIT4       0x0200
 565 #define PHY_INIT5       0x0004
 566 #define PHY_INIT6       0x02000
 567 #define PHY_GIGABIT     0x0100
 568
 569 #define PHY_TIMEOUT     0x1
 570 #define PHY_ERROR       0x2
 571
 572 #define PHY_100 0x1
 573 #define PHY_1000        0x2
 574 #define PHY_HALF        0x100
 575
 576 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 577 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 578 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 579 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 580 #define NV_PAUSEFRAME_RX_REQ     0x0010
 581 #define NV_PAUSEFRAME_TX_REQ     0x0020
 582 #define NV_PAUSEFRAME_AUTONEG    0x0040
 583
 584 /* MSI/MSI-X defines */
 585 #define NV_MSI_X_MAX_VECTORS  8
 586 #define NV_MSI_X_VECTORS_MASK 0x000f
 587 #define NV_MSI_CAPABLE        0x0010
 588 #define NV_MSI_X_CAPABLE      0x0020
 589 #define NV_MSI_ENABLED        0x0040
 590 #define NV_MSI_X_ENABLED      0x0080
 591
 592 #define NV_MSI_X_VECTOR_ALL   0x0
 593 #define NV_MSI_X_VECTOR_RX    0x0
 594 #define NV_MSI_X_VECTOR_TX    0x1
 595 #define NV_MSI_X_VECTOR_OTHER 0x2
 596
 597 /* statistics */
 598 struct nv_ethtool_str {
 599         char name[ETH_GSTRING_LEN];
 600 };
 601
 602 static const struct nv_ethtool_str nv_estats_str[] = {
 603         { "tx_bytes" },
 604         { "tx_zero_rexmt" },
 605         { "tx_one_rexmt" },
 606         { "tx_many_rexmt" },
 607         { "tx_late_collision" },
 608         { "tx_fifo_errors" },
 609         { "tx_carrier_errors" },
 610         { "tx_excess_deferral" },
 611         { "tx_retry_error" },
 612         { "tx_deferral" },
 613         { "tx_packets" },
 614         { "tx_pause" },
 615         { "rx_frame_error" },
 616         { "rx_extra_byte" },
 617         { "rx_late_collision" },
 618         { "rx_runt" },
 619         { "rx_frame_too_long" },
 620         { "rx_over_errors" },
 621         { "rx_crc_errors" },
 622         { "rx_frame_align_error" },
 623         { "rx_length_error" },
 624         { "rx_unicast" },
 625         { "rx_multicast" },
 626         { "rx_broadcast" },
 627         { "rx_bytes" },
 628         { "rx_pause" },
 629         { "rx_drop_frame" },
 630         { "rx_packets" },
 631         { "rx_errors_total" }
 632 };
 633
 634 struct nv_ethtool_stats {
 635         u64 tx_bytes;
 636         u64 tx_zero_rexmt;
 637         u64 tx_one_rexmt;
 638         u64 tx_many_rexmt;
 639         u64 tx_late_collision;
 640         u64 tx_fifo_errors;
 641         u64 tx_carrier_errors;
 642         u64 tx_excess_deferral;
 643         u64 tx_retry_error;
 644         u64 tx_deferral;
 645         u64 tx_packets;
 646         u64 tx_pause;
 647         u64 rx_frame_error;
 648         u64 rx_extra_byte;
 649         u64 rx_late_collision;
 650         u64 rx_runt;
 651         u64 rx_frame_too_long;
 652         u64 rx_over_errors;
 653         u64 rx_crc_errors;
 654         u64 rx_frame_align_error;
 655         u64 rx_length_error;
 656         u64 rx_unicast;
 657         u64 rx_multicast;
 658         u64 rx_broadcast;
 659         u64 rx_bytes;
 660         u64 rx_pause;
 661         u64 rx_drop_frame;
 662         u64 rx_packets;
 663         u64 rx_errors_total;
 664 };
 665
 666 /* diagnostics */
 667 #define NV_TEST_COUNT_BASE 3
 668 #define NV_TEST_COUNT_EXTENDED 4
 669
 670 static const struct nv_ethtool_str nv_etests_str[] = {
 671         { "link      (online/offline)" },
 672         { "register  (offline)       " },
 673         { "interrupt (offline)       " },
 674         { "loopback  (offline)       " }
 675 };
 676
 677 struct register_test {
 678         __le32 reg;
 679         __le32 mask;
 680 };
 681
 682 static const struct register_test nv_registers_test[] = {
 683         { NvRegUnknownSetupReg6, 0x01 },
 684         { NvRegMisc1, 0x03c },
 685         { NvRegOffloadConfig, 0x03ff },
 686         { NvRegMulticastAddrA, 0xffffffff },
 687         { NvRegTxWatermark, 0x0ff },
 688         { NvRegWakeUpFlags, 0x07777 },
 689         { 0,0 }
 690 };
 691
 692 /*
 693  * SMP locking:
 694  * All hardware access under dev->priv->lock, except the performance
 695  * critical parts:
 696  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 697  *      by the arch code for interrupts.
 698  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 699  *      needs dev->priv->lock :-(
 700  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 701  */
 702
 703 /* in dev: base, irq */
 704 struct fe_priv {
 705         spinlock_t lock;
 706
 707         /* General data:
 708          * Locking: spin_lock(&np->lock); */
 709         struct net_device_stats stats;
 710         struct nv_ethtool_stats estats;
 711         int in_shutdown;
 712         u32 linkspeed;
 713         int duplex;
 714         int autoneg;
 715         int fixed_mode;
 716         int phyaddr;
 717         int wolenabled;
 718         unsigned int phy_oui;
 719         unsigned int phy_model;
 720         u16 gigabit;
 721         int intr_test;
 722         int recover_error;
 723
 724         /* General data: RO fields */
 725         dma_addr_t ring_addr;
 726         struct pci_dev *pci_dev;
 727         u32 orig_mac[2];
 728         u32 irqmask;
 729         u32 desc_ver;
 730         u32 txrxctl_bits;
 731         u32 vlanctl_bits;
 732         u32 driver_data;
 733         u32 register_size;
 734         int rx_csum;
 735         u32 mac_in_use;
 736
 737         void __iomem *base;
 738
 739         /* rx specific fields.
 740          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 741          */
 742         union ring_type rx_ring;
 743         unsigned int cur_rx, refill_rx;
 744         struct sk_buff **rx_skbuff;
 745         dma_addr_t *rx_dma;
 746         unsigned int rx_buf_sz;
 747         unsigned int pkt_limit;
 748         struct timer_list oom_kick;
 749         struct timer_list nic_poll;
 750         struct timer_list stats_poll;
 751         u32 nic_poll_irq;
 752         int rx_ring_size;
 753
 754         /* media detection workaround.
 755          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 756          */
 757         int need_linktimer;
 758         unsigned long link_timeout;
 759         /*
 760          * tx specific fields.
 761          */
 762         union ring_type tx_ring;
 763         unsigned int next_tx, nic_tx;
 764         struct sk_buff **tx_skbuff;
 765         dma_addr_t *tx_dma;
 766         unsigned int *tx_dma_len;
 767         u32 tx_flags;
 768         int tx_ring_size;
 769         int tx_limit_start;
 770         int tx_limit_stop;
 771
 772         /* vlan fields */
 773         struct vlan_group *vlangrp;
 774
 775         /* msi/msi-x fields */
 776         u32 msi_flags;
 777         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 778
 779         /* flow control */
 780         u32 pause_flags;
 781 };
 782
 783 /*
 784  * Maximum number of loops until we assume that a bit in the irq mask
 785  * is stuck. Overridable with module param.
 786  */
 787 static int max_interrupt_work = 5;
 788
 789 /*
 790  * Optimization can be either throuput mode or cpu mode
 791  *
 792  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 793  * CPU Mode: Interrupts are controlled by a timer.
 794  */
 795 enum {
 796         NV_OPTIMIZATION_MODE_THROUGHPUT,
 797         NV_OPTIMIZATION_MODE_CPU
 798 };
 799 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
 800
 801 /*
 802  * Poll interval for timer irq
 803  *
 804  * This interval determines how frequent an interrupt is generated.
 805  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 806  * Min = 0, and Max = 65535
 807  */
 808 static int poll_interval = -1;
 809
 810 /*
 811  * MSI interrupts
 812  */
 813 enum {
 814         NV_MSI_INT_DISABLED,
 815         NV_MSI_INT_ENABLED
 816 };
 817 static int msi = NV_MSI_INT_ENABLED;
 818
 819 /*
 820  * MSIX interrupts
 821  */
 822 enum {
 823         NV_MSIX_INT_DISABLED,
 824         NV_MSIX_INT_ENABLED
 825 };
 826 static int msix = NV_MSIX_INT_ENABLED;
 827
 828 /*
 829  * DMA 64bit
 830  */
 831 enum {
 832         NV_DMA_64BIT_DISABLED,
 833         NV_DMA_64BIT_ENABLED
 834 };
 835 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 836
 837 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 838 {
 839         return netdev_priv(dev);
 840 }
 841
 842 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 843 {
 844         return ((struct fe_priv *)netdev_priv(dev))->base;
 845 }
 846
 847 static inline void pci_push(u8 __iomem *base)
 848 {
 849         /* force out pending posted writes */
 850         readl(base);
 851 }
 852
 853 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 854 {
 855         return le32_to_cpu(prd->flaglen)
 856                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 857 }
 858
 859 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 860 {
 861         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
 862 }
 863
 864 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 865                                 int delay, int delaymax, const char *msg)
 866 {
 867         u8 __iomem *base = get_hwbase(dev);
 868
 869         pci_push(base);
 870         do {
 871                 udelay(delay);
 872                 delaymax -= delay;
 873                 if (delaymax < 0) {
 874                         if (msg)
 875                                 printk(msg);
 876                         return 1;
 877                 }
 878         } while ((readl(base + offset) & mask) != target);
 879         return 0;
 880 }
 881
 882 #define NV_SETUP_RX_RING 0x01
 883 #define NV_SETUP_TX_RING 0x02
 884
 885 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
 886 {
 887         struct fe_priv *np = get_nvpriv(dev);
 888         u8 __iomem *base = get_hwbase(dev);
 889
 890         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 891                 if (rxtx_flags & NV_SETUP_RX_RING) {
 892                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 893                 }
 894                 if (rxtx_flags & NV_SETUP_TX_RING) {
 895                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
 896                 }
 897         } else {
 898                 if (rxtx_flags & NV_SETUP_RX_RING) {
 899                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 900                         writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
 901                 }
 902                 if (rxtx_flags & NV_SETUP_TX_RING) {
 903                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
 904                         writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
 905                 }
 906         }
 907 }
 908
 909 static void free_rings(struct net_device *dev)
 910 {
 911         struct fe_priv *np = get_nvpriv(dev);
 912
 913         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 914                 if (np->rx_ring.orig)
 915                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
 916                                             np->rx_ring.orig, np->ring_addr);
 917         } else {
 918                 if (np->rx_ring.ex)
 919                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
 920                                             np->rx_ring.ex, np->ring_addr);
 921         }
 922         if (np->rx_skbuff)
 923                 kfree(np->rx_skbuff);
 924         if (np->rx_dma)
 925                 kfree(np->rx_dma);
 926         if (np->tx_skbuff)
 927                 kfree(np->tx_skbuff);
 928         if (np->tx_dma)
 929                 kfree(np->tx_dma);
 930         if (np->tx_dma_len)
 931                 kfree(np->tx_dma_len);
 932 }
 933
 934 static int using_multi_irqs(struct net_device *dev)
 935 {
 936         struct fe_priv *np = get_nvpriv(dev);
 937
 938         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
 939             ((np->msi_flags & NV_MSI_X_ENABLED) &&
 940              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
 941                 return 0;
 942         else
 943                 return 1;
 944 }
 945
 946 static void nv_enable_irq(struct net_device *dev)
 947 {
 948         struct fe_priv *np = get_nvpriv(dev);
 949
 950         if (!using_multi_irqs(dev)) {
 951                 if (np->msi_flags & NV_MSI_X_ENABLED)
 952                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 953                 else
 954                         enable_irq(dev->irq);
 955         } else {
 956                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 957                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 958                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
 959         }
 960 }
 961
 962 static void nv_disable_irq(struct net_device *dev)
 963 {
 964         struct fe_priv *np = get_nvpriv(dev);
 965
 966         if (!using_multi_irqs(dev)) {
 967                 if (np->msi_flags & NV_MSI_X_ENABLED)
 968                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 969                 else
 970                         disable_irq(dev->irq);
 971         } else {
 972                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 973                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 974                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
 975         }
 976 }
 977
 978 /* In MSIX mode, a write to irqmask behaves as XOR */
 979 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
 980 {
 981         u8 __iomem *base = get_hwbase(dev);
 982
 983         writel(mask, base + NvRegIrqMask);
 984 }
 985
 986 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
 987 {
 988         struct fe_priv *np = get_nvpriv(dev);
 989         u8 __iomem *base = get_hwbase(dev);
 990
 991         if (np->msi_flags & NV_MSI_X_ENABLED) {
 992                 writel(mask, base + NvRegIrqMask);
 993         } else {
 994                 if (np->msi_flags & NV_MSI_ENABLED)
 995                         writel(0, base + NvRegMSIIrqMask);
 996                 writel(0, base + NvRegIrqMask);
 997         }
 998 }
 999
1000 #define MII_READ        (-1)
1001 /* mii_rw: read/write a register on the PHY.
1002  *
1003  * Caller must guarantee serialization
1004  */
1005 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1006 {
1007         u8 __iomem *base = get_hwbase(dev);
1008         u32 reg;
1009         int retval;
1010
1011         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1012
1013         reg = readl(base + NvRegMIIControl);
1014         if (reg & NVREG_MIICTL_INUSE) {
1015                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1016                 udelay(NV_MIIBUSY_DELAY);
1017         }
1018
1019         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1020         if (value != MII_READ) {
1021                 writel(value, base + NvRegMIIData);
1022                 reg |= NVREG_MIICTL_WRITE;
1023         }
1024         writel(reg, base + NvRegMIIControl);
1025
1026         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1027                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1028                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1029                                 dev->name, miireg, addr);
1030                 retval = -1;
1031         } else if (value != MII_READ) {
1032                 /* it was a write operation - fewer failures are detectable */
1033                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1034                                 dev->name, value, miireg, addr);
1035                 retval = 0;
1036         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1037                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1038                                 dev->name, miireg, addr);
1039                 retval = -1;
1040         } else {
1041                 retval = readl(base + NvRegMIIData);
1042                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1043                                 dev->name, miireg, addr, retval);
1044         }
1045
1046         return retval;
1047 }
1048
1049 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1050 {
1051         struct fe_priv *np = netdev_priv(dev);
1052         u32 miicontrol;
1053         unsigned int tries = 0;
1054
1055         miicontrol = BMCR_RESET | bmcr_setup;
1056         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1057                 return -1;
1058         }
1059
1060         /* wait for 500ms */
1061         msleep(500);
1062
1063         /* must wait till reset is deasserted */
1064         while (miicontrol & BMCR_RESET) {
1065                 msleep(10);
1066                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1067                 /* FIXME: 100 tries seem excessive */
1068                 if (tries++ > 100)
1069                         return -1;
1070         }
1071         return 0;
1072 }
1073
1074 static int phy_init(struct net_device *dev)
1075 {
1076         struct fe_priv *np = get_nvpriv(dev);
1077         u8 __iomem *base = get_hwbase(dev);
1078         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1079
1080         /* phy errata for E3016 phy */
1081         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1082                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1083                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1084                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1085                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1086                         return PHY_ERROR;
1087                 }
1088         }
1089
1090         /* set advertise register */
1091         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1092         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1093         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1094                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1095                 return PHY_ERROR;
1096         }
1097
1098         /* get phy interface type */
1099         phyinterface = readl(base + NvRegPhyInterface);
1100
1101         /* see if gigabit phy */
1102         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1103         if (mii_status & PHY_GIGABIT) {
1104                 np->gigabit = PHY_GIGABIT;
1105                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1106                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1107                 if (phyinterface & PHY_RGMII)
1108                         mii_control_1000 |= ADVERTISE_1000FULL;
1109                 else
1110                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1111
1112                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1113                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1114                         return PHY_ERROR;
1115                 }
1116         }
1117         else
1118                 np->gigabit = 0;
1119
1120         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1121         mii_control |= BMCR_ANENABLE;
1122
1123         /* reset the phy
1124          * (certain phys need bmcr to be setup with reset)
1125          */
1126         if (phy_reset(dev, mii_control)) {
1127                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1128                 return PHY_ERROR;
1129         }
1130
1131         /* phy vendor specific configuration */
1132         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1133                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1134                 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
1135                 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
1136                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1137                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1138                         return PHY_ERROR;
1139                 }
1140                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1141                 phy_reserved |= PHY_INIT5;
1142                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1143                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1144                         return PHY_ERROR;
1145                 }
1146         }
1147         if (np->phy_oui == PHY_OUI_CICADA) {
1148                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1149                 phy_reserved |= PHY_INIT6;
1150                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1151                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1152                         return PHY_ERROR;
1153                 }
1154         }
1155         /* some phys clear out pause advertisment on reset, set it back */
1156         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1157
1158         /* restart auto negotiation */
1159         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1160         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1161         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1162                 return PHY_ERROR;
1163         }
1164
1165         return 0;
1166 }
1167
1168 static void nv_start_rx(struct net_device *dev)
1169 {
1170         struct fe_priv *np = netdev_priv(dev);
1171         u8 __iomem *base = get_hwbase(dev);
1172
1173         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1174         /* Already running? Stop it. */
1175         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
1176                 writel(0, base + NvRegReceiverControl);
1177                 pci_push(base);
1178         }
1179         writel(np->linkspeed, base + NvRegLinkSpeed);
1180         pci_push(base);
1181         writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
1182         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1183                                 dev->name, np->duplex, np->linkspeed);
1184         pci_push(base);
1185 }
1186
1187 static void nv_stop_rx(struct net_device *dev)
1188 {
1189         u8 __iomem *base = get_hwbase(dev);
1190
1191         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1192         writel(0, base + NvRegReceiverControl);
1193         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1194                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1195                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1196
1197         udelay(NV_RXSTOP_DELAY2);
1198         writel(0, base + NvRegLinkSpeed);
1199 }
1200
1201 static void nv_start_tx(struct net_device *dev)
1202 {
1203         u8 __iomem *base = get_hwbase(dev);
1204
1205         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1206         writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
1207         pci_push(base);
1208 }
1209
1210 static void nv_stop_tx(struct net_device *dev)
1211 {
1212         u8 __iomem *base = get_hwbase(dev);
1213
1214         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1215         writel(0, base + NvRegTransmitterControl);
1216         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1217                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1218                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1219
1220         udelay(NV_TXSTOP_DELAY2);
1221         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
1222 }
1223
1224 static void nv_txrx_reset(struct net_device *dev)
1225 {
1226         struct fe_priv *np = netdev_priv(dev);
1227         u8 __iomem *base = get_hwbase(dev);
1228
1229         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1230         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1231         pci_push(base);
1232         udelay(NV_TXRX_RESET_DELAY);
1233         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1234         pci_push(base);
1235 }
1236
1237 static void nv_mac_reset(struct net_device *dev)
1238 {
1239         struct fe_priv *np = netdev_priv(dev);
1240         u8 __iomem *base = get_hwbase(dev);
1241
1242         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1243         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1244         pci_push(base);
1245         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1246         pci_push(base);
1247         udelay(NV_MAC_RESET_DELAY);
1248         writel(0, base + NvRegMacReset);
1249         pci_push(base);
1250         udelay(NV_MAC_RESET_DELAY);
1251         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1252         pci_push(base);
1253 }
1254
1255 /*
1256  * nv_get_stats: dev->get_stats function
1257  * Get latest stats value from the nic.
1258  * Called with read_lock(&dev_base_lock) held for read -
1259  * only synchronized against unregister_netdevice.
1260  */
1261 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1262 {
1263         struct fe_priv *np = netdev_priv(dev);
1264
1265         /* It seems that the nic always generates interrupts and doesn't
1266          * accumulate errors internally. Thus the current values in np->stats
1267          * are already up to date.
1268          */
1269         return &np->stats;
1270 }
1271
1272 /*
1273  * nv_alloc_rx: fill rx ring entries.
1274  * Return 1 if the allocations for the skbs failed and the
1275  * rx engine is without Available descriptors
1276  */
1277 static int nv_alloc_rx(struct net_device *dev)
1278 {
1279         struct fe_priv *np = netdev_priv(dev);
1280         unsigned int refill_rx = np->refill_rx;
1281         int nr;
1282
1283         while (np->cur_rx != refill_rx) {
1284                 struct sk_buff *skb;
1285
1286                 nr = refill_rx % np->rx_ring_size;
1287                 if (np->rx_skbuff[nr] == NULL) {
1288
1289                         skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1290                         if (!skb)
1291                                 break;
1292
1293                         skb->dev = dev;
1294                         np->rx_skbuff[nr] = skb;
1295                 } else {
1296                         skb = np->rx_skbuff[nr];
1297                 }
1298                 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data,
1299                                         skb->end-skb->data, PCI_DMA_FROMDEVICE);
1300                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1301                         np->rx_ring.orig[nr].buf = cpu_to_le32(np->rx_dma[nr]);
1302                         wmb();
1303                         np->rx_ring.orig[nr].flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1304                 } else {
1305                         np->rx_ring.ex[nr].bufhigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
1306                         np->rx_ring.ex[nr].buflow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
1307                         wmb();
1308                         np->rx_ring.ex[nr].flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1309                 }
1310                 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
1311                                         dev->name, refill_rx);
1312                 refill_rx++;
1313         }
1314         np->refill_rx = refill_rx;
1315         if (np->cur_rx - refill_rx == np->rx_ring_size)
1316                 return 1;
1317         return 0;
1318 }
1319
1320 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1321 #ifdef CONFIG_FORCEDETH_NAPI
1322 static void nv_do_rx_refill(unsigned long data)
1323 {
1324         struct net_device *dev = (struct net_device *) data;
1325
1326         /* Just reschedule NAPI rx processing */
1327         netif_rx_schedule(dev);
1328 }
1329 #else
1330 static void nv_do_rx_refill(unsigned long data)
1331 {
1332         struct net_device *dev = (struct net_device *) data;
1333         struct fe_priv *np = netdev_priv(dev);
1334
1335         if (!using_multi_irqs(dev)) {
1336                 if (np->msi_flags & NV_MSI_X_ENABLED)
1337                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1338                 else
1339                         disable_irq(dev->irq);
1340         } else {
1341                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1342         }
1343         if (nv_alloc_rx(dev)) {
1344                 spin_lock_irq(&np->lock);
1345                 if (!np->in_shutdown)
1346                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1347                 spin_unlock_irq(&np->lock);
1348         }
1349         if (!using_multi_irqs(dev)) {
1350                 if (np->msi_flags & NV_MSI_X_ENABLED)
1351                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1352                 else
1353                         enable_irq(dev->irq);
1354         } else {
1355                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1356         }
1357 }
1358 #endif
1359
1360 static void nv_init_rx(struct net_device *dev)
1361 {
1362         struct fe_priv *np = netdev_priv(dev);
1363         int i;
1364
1365         np->cur_rx = np->rx_ring_size;
1366         np->refill_rx = 0;
1367         for (i = 0; i < np->rx_ring_size; i++)
1368                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1369                         np->rx_ring.orig[i].flaglen = 0;
1370                 else
1371                         np->rx_ring.ex[i].flaglen = 0;
1372 }
1373
1374 static void nv_init_tx(struct net_device *dev)
1375 {
1376         struct fe_priv *np = netdev_priv(dev);
1377         int i;
1378
1379         np->next_tx = np->nic_tx = 0;
1380         for (i = 0; i < np->tx_ring_size; i++) {
1381                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1382                         np->tx_ring.orig[i].flaglen = 0;
1383                 else
1384                         np->tx_ring.ex[i].flaglen = 0;
1385                 np->tx_skbuff[i] = NULL;
1386                 np->tx_dma[i] = 0;
1387         }
1388 }
1389
1390 static int nv_init_ring(struct net_device *dev)
1391 {
1392         nv_init_tx(dev);
1393         nv_init_rx(dev);
1394         return nv_alloc_rx(dev);
1395 }
1396
1397 static int nv_release_txskb(struct net_device *dev, unsigned int skbnr)
1398 {
1399         struct fe_priv *np = netdev_priv(dev);
1400
1401         dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d\n",
1402                 dev->name, skbnr);
1403
1404         if (np->tx_dma[skbnr]) {
1405                 pci_unmap_page(np->pci_dev, np->tx_dma[skbnr],
1406                                np->tx_dma_len[skbnr],
1407                                PCI_DMA_TODEVICE);
1408                 np->tx_dma[skbnr] = 0;
1409         }
1410
1411         if (np->tx_skbuff[skbnr]) {
1412                 dev_kfree_skb_any(np->tx_skbuff[skbnr]);
1413                 np->tx_skbuff[skbnr] = NULL;
1414                 return 1;
1415         } else {
1416                 return 0;
1417         }
1418 }
1419
1420 static void nv_drain_tx(struct net_device *dev)
1421 {
1422         struct fe_priv *np = netdev_priv(dev);
1423         unsigned int i;
1424
1425         for (i = 0; i < np->tx_ring_size; i++) {
1426                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1427                         np->tx_ring.orig[i].flaglen = 0;
1428                 else
1429                         np->tx_ring.ex[i].flaglen = 0;
1430                 if (nv_release_txskb(dev, i))
1431                         np->stats.tx_dropped++;
1432         }
1433 }
1434
1435 static void nv_drain_rx(struct net_device *dev)
1436 {
1437         struct fe_priv *np = netdev_priv(dev);
1438         int i;
1439         for (i = 0; i < np->rx_ring_size; i++) {
1440                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1441                         np->rx_ring.orig[i].flaglen = 0;
1442                 else
1443                         np->rx_ring.ex[i].flaglen = 0;
1444                 wmb();
1445                 if (np->rx_skbuff[i]) {
1446                         pci_unmap_single(np->pci_dev, np->rx_dma[i],
1447                                                 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1448                                                 PCI_DMA_FROMDEVICE);
1449                         dev_kfree_skb(np->rx_skbuff[i]);
1450                         np->rx_skbuff[i] = NULL;
1451                 }
1452         }
1453 }
1454
1455 static void drain_ring(struct net_device *dev)
1456 {
1457         nv_drain_tx(dev);
1458         nv_drain_rx(dev);
1459 }
1460
1461 /*
1462  * nv_start_xmit: dev->hard_start_xmit function
1463  * Called with netif_tx_lock held.
1464  */
1465 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1466 {
1467         struct fe_priv *np = netdev_priv(dev);
1468         u32 tx_flags = 0;
1469         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1470         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1471         unsigned int nr = (np->next_tx - 1) % np->tx_ring_size;
1472         unsigned int start_nr = np->next_tx % np->tx_ring_size;
1473         unsigned int i;
1474         u32 offset = 0;
1475         u32 bcnt;
1476         u32 size = skb->len-skb->data_len;
1477         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1478         u32 tx_flags_vlan = 0;
1479
1480         /* add fragments to entries count */
1481         for (i = 0; i < fragments; i++) {
1482                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1483                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1484         }
1485
1486         spin_lock_irq(&np->lock);
1487
1488         if ((np->next_tx - np->nic_tx + entries - 1) > np->tx_limit_stop) {
1489                 spin_unlock_irq(&np->lock);
1490                 netif_stop_queue(dev);
1491                 return NETDEV_TX_BUSY;
1492         }
1493
1494         /* setup the header buffer */
1495         do {
1496                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1497                 nr = (nr + 1) % np->tx_ring_size;
1498
1499                 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1500                                                 PCI_DMA_TODEVICE);
1501                 np->tx_dma_len[nr] = bcnt;
1502
1503                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1504                         np->tx_ring.orig[nr].buf = cpu_to_le32(np->tx_dma[nr]);
1505                         np->tx_ring.orig[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1506                 } else {
1507                         np->tx_ring.ex[nr].bufhigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1508                         np->tx_ring.ex[nr].buflow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1509                         np->tx_ring.ex[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1510                 }
1511                 tx_flags = np->tx_flags;
1512                 offset += bcnt;
1513                 size -= bcnt;
1514         } while (size);
1515
1516         /* setup the fragments */
1517         for (i = 0; i < fragments; i++) {
1518                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1519                 u32 size = frag->size;
1520                 offset = 0;
1521
1522                 do {
1523                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1524                         nr = (nr + 1) % np->tx_ring_size;
1525
1526                         np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1527                                                       PCI_DMA_TODEVICE);
1528                         np->tx_dma_len[nr] = bcnt;
1529
1530                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1531                                 np->tx_ring.orig[nr].buf = cpu_to_le32(np->tx_dma[nr]);
1532                                 np->tx_ring.orig[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1533                         } else {
1534                                 np->tx_ring.ex[nr].bufhigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1535                                 np->tx_ring.ex[nr].buflow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1536                                 np->tx_ring.ex[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1537                         }
1538                         offset += bcnt;
1539                         size -= bcnt;
1540                 } while (size);
1541         }
1542
1543         /* set last fragment flag  */
1544         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1545                 np->tx_ring.orig[nr].flaglen |= cpu_to_le32(tx_flags_extra);
1546         } else {
1547                 np->tx_ring.ex[nr].flaglen |= cpu_to_le32(tx_flags_extra);
1548         }
1549
1550         np->tx_skbuff[nr] = skb;
1551
1552 #ifdef NETIF_F_TSO
1553         if (skb_is_gso(skb))
1554                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1555         else
1556 #endif
1557         tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1558                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1559
1560         /* vlan tag */
1561         if (np->vlangrp && vlan_tx_tag_present(skb)) {
1562                 tx_flags_vlan = NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb);
1563         }
1564
1565         /* set tx flags */
1566         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1567                 np->tx_ring.orig[start_nr].flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1568         } else {
1569                 np->tx_ring.ex[start_nr].txvlan = cpu_to_le32(tx_flags_vlan);
1570                 np->tx_ring.ex[start_nr].flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1571         }
1572
1573         dprintk(KERN_DEBUG "%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n",
1574                 dev->name, np->next_tx, entries, tx_flags_extra);
1575         {
1576                 int j;
1577                 for (j=0; j<64; j++) {
1578                         if ((j%16) == 0)
1579                                 dprintk("\n%03x:", j);
1580                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1581                 }
1582                 dprintk("\n");
1583         }
1584
1585         np->next_tx += entries;
1586
1587         dev->trans_start = jiffies;
1588         spin_unlock_irq(&np->lock);
1589         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1590         pci_push(get_hwbase(dev));
1591         return NETDEV_TX_OK;
1592 }
1593
1594 /*
1595  * nv_tx_done: check for completed packets, release the skbs.
1596  *
1597  * Caller must own np->lock.
1598  */
1599 static void nv_tx_done(struct net_device *dev)
1600 {
1601         struct fe_priv *np = netdev_priv(dev);
1602         u32 flags;
1603         unsigned int i;
1604         struct sk_buff *skb;
1605
1606         while (np->nic_tx != np->next_tx) {
1607                 i = np->nic_tx % np->tx_ring_size;
1608
1609                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1610                         flags = le32_to_cpu(np->tx_ring.orig[i].flaglen);
1611                 else
1612                         flags = le32_to_cpu(np->tx_ring.ex[i].flaglen);
1613
1614                 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, flags 0x%x.\n",
1615                                         dev->name, np->nic_tx, flags);
1616                 if (flags & NV_TX_VALID)
1617                         break;
1618                 if (np->desc_ver == DESC_VER_1) {
1619                         if (flags & NV_TX_LASTPACKET) {
1620                                 skb = np->tx_skbuff[i];
1621                                 if (flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1622                                              NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1623                                         if (flags & NV_TX_UNDERFLOW)
1624                                                 np->stats.tx_fifo_errors++;
1625                                         if (flags & NV_TX_CARRIERLOST)
1626                                                 np->stats.tx_carrier_errors++;
1627                                         np->stats.tx_errors++;
1628                                 } else {
1629                                         np->stats.tx_packets++;
1630                                         np->stats.tx_bytes += skb->len;
1631                                 }
1632                         }
1633                 } else {
1634                         if (flags & NV_TX2_LASTPACKET) {
1635                                 skb = np->tx_skbuff[i];
1636                                 if (flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1637                                              NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1638                                         if (flags & NV_TX2_UNDERFLOW)
1639                                                 np->stats.tx_fifo_errors++;
1640                                         if (flags & NV_TX2_CARRIERLOST)
1641                                                 np->stats.tx_carrier_errors++;
1642                                         np->stats.tx_errors++;
1643                                 } else {
1644                                         np->stats.tx_packets++;
1645                                         np->stats.tx_bytes += skb->len;
1646                                 }
1647                         }
1648                 }
1649                 nv_release_txskb(dev, i);
1650                 np->nic_tx++;
1651         }
1652         if (np->next_tx - np->nic_tx < np->tx_limit_start)
1653                 netif_wake_queue(dev);
1654 }
1655
1656 /*
1657  * nv_tx_timeout: dev->tx_timeout function
1658  * Called with netif_tx_lock held.
1659  */
1660 static void nv_tx_timeout(struct net_device *dev)
1661 {
1662         struct fe_priv *np = netdev_priv(dev);
1663         u8 __iomem *base = get_hwbase(dev);
1664         u32 status;
1665
1666         if (np->msi_flags & NV_MSI_X_ENABLED)
1667                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
1668         else
1669                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1670
1671         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
1672
1673         {
1674                 int i;
1675
1676                 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
1677                                 dev->name, (unsigned long)np->ring_addr,
1678                                 np->next_tx, np->nic_tx);
1679                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1680                 for (i=0;i<=np->register_size;i+= 32) {
1681                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1682                                         i,
1683                                         readl(base + i + 0), readl(base + i + 4),
1684                                         readl(base + i + 8), readl(base + i + 12),
1685                                         readl(base + i + 16), readl(base + i + 20),
1686                                         readl(base + i + 24), readl(base + i + 28));
1687                 }
1688                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1689                 for (i=0;i<np->tx_ring_size;i+= 4) {
1690                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1691                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1692                                        i,
1693                                        le32_to_cpu(np->tx_ring.orig[i].buf),
1694                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
1695                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
1696                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
1697                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
1698                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
1699                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
1700                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
1701                         } else {
1702                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1703                                        i,
1704                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
1705                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
1706                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
1707                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
1708                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
1709                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
1710                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
1711                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
1712                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
1713                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
1714                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
1715                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
1716                         }
1717                 }
1718         }
1719
1720         spin_lock_irq(&np->lock);
1721
1722         /* 1) stop tx engine */
1723         nv_stop_tx(dev);
1724
1725         /* 2) check that the packets were not sent already: */
1726         nv_tx_done(dev);
1727
1728         /* 3) if there are dead entries: clear everything */
1729         if (np->next_tx != np->nic_tx) {
1730                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1731                 nv_drain_tx(dev);
1732                 np->next_tx = np->nic_tx = 0;
1733                 setup_hw_rings(dev, NV_SETUP_TX_RING);
1734                 netif_wake_queue(dev);
1735         }
1736
1737         /* 4) restart tx engine */
1738         nv_start_tx(dev);
1739         spin_unlock_irq(&np->lock);
1740 }
1741
1742 /*
1743  * Called when the nic notices a mismatch between the actual data len on the
1744  * wire and the len indicated in the 802 header
1745  */
1746 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1747 {
1748         int hdrlen;     /* length of the 802 header */
1749         int protolen;   /* length as stored in the proto field */
1750
1751         /* 1) calculate len according to header */
1752         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
1753                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1754                 hdrlen = VLAN_HLEN;
1755         } else {
1756                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1757                 hdrlen = ETH_HLEN;
1758         }
1759         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1760                                 dev->name, datalen, protolen, hdrlen);
1761         if (protolen > ETH_DATA_LEN)
1762                 return datalen; /* Value in proto field not a len, no checks possible */
1763
1764         protolen += hdrlen;
1765         /* consistency checks: */
1766         if (datalen > ETH_ZLEN) {
1767                 if (datalen >= protolen) {
1768                         /* more data on wire than in 802 header, trim of
1769                          * additional data.
1770                          */
1771                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1772                                         dev->name, protolen);
1773                         return protolen;
1774                 } else {
1775                         /* less data on wire than mentioned in header.
1776                          * Discard the packet.
1777                          */
1778                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1779                                         dev->name);
1780                         return -1;
1781                 }
1782         } else {
1783                 /* short packet. Accept only if 802 values are also short */
1784                 if (protolen > ETH_ZLEN) {
1785                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1786                                         dev->name);
1787                         return -1;
1788                 }
1789                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1790                                 dev->name, datalen);
1791                 return datalen;
1792         }
1793 }
1794
1795 static int nv_rx_process(struct net_device *dev, int limit)
1796 {
1797         struct fe_priv *np = netdev_priv(dev);
1798         u32 flags;
1799         u32 vlanflags = 0;
1800         int count;
1801
1802         for (count = 0; count < limit; ++count) {
1803                 struct sk_buff *skb;
1804                 int len;
1805                 int i;
1806                 if (np->cur_rx - np->refill_rx >= np->rx_ring_size)
1807                         break;  /* we scanned the whole ring - do not continue */
1808
1809                 i = np->cur_rx % np->rx_ring_size;
1810                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1811                         flags = le32_to_cpu(np->rx_ring.orig[i].flaglen);
1812                         len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
1813                 } else {
1814                         flags = le32_to_cpu(np->rx_ring.ex[i].flaglen);
1815                         len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
1816                         vlanflags = le32_to_cpu(np->rx_ring.ex[i].buflow);
1817                 }
1818
1819                 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, flags 0x%x.\n",
1820                                         dev->name, np->cur_rx, flags);
1821
1822                 if (flags & NV_RX_AVAIL)
1823                         break;  /* still owned by hardware, */
1824
1825                 /*
1826                  * the packet is for us - immediately tear down the pci mapping.
1827                  * TODO: check if a prefetch of the first cacheline improves
1828                  * the performance.
1829                  */
1830                 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1831                                 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1832                                 PCI_DMA_FROMDEVICE);
1833
1834                 {
1835                         int j;
1836                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
1837                         for (j=0; j<64; j++) {
1838                                 if ((j%16) == 0)
1839                                         dprintk("\n%03x:", j);
1840                                 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1841                         }
1842                         dprintk("\n");
1843                 }
1844                 /* look at what we actually got: */
1845                 if (np->desc_ver == DESC_VER_1) {
1846                         if (!(flags & NV_RX_DESCRIPTORVALID))
1847                                 goto next_pkt;
1848
1849                         if (flags & NV_RX_ERROR) {
1850                                 if (flags & NV_RX_MISSEDFRAME) {
1851                                         np->stats.rx_missed_errors++;
1852                                         np->stats.rx_errors++;
1853                                         goto next_pkt;
1854                                 }
1855                                 if (flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1856                                         np->stats.rx_errors++;
1857                                         goto next_pkt;
1858                                 }
1859                                 if (flags & NV_RX_CRCERR) {
1860                                         np->stats.rx_crc_errors++;
1861                                         np->stats.rx_errors++;
1862                                         goto next_pkt;
1863                                 }
1864                                 if (flags & NV_RX_OVERFLOW) {
1865                                         np->stats.rx_over_errors++;
1866                                         np->stats.rx_errors++;
1867                                         goto next_pkt;
1868                                 }
1869                                 if (flags & NV_RX_ERROR4) {
1870                                         len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1871                                         if (len < 0) {
1872                                                 np->stats.rx_errors++;
1873                                                 goto next_pkt;
1874                                         }
1875                                 }
1876                                 /* framing errors are soft errors. */
1877                                 if (flags & NV_RX_FRAMINGERR) {
1878                                         if (flags & NV_RX_SUBSTRACT1) {
1879                                                 len--;
1880                                         }
1881                                 }
1882                         }
1883                 } else {
1884                         if (!(flags & NV_RX2_DESCRIPTORVALID))
1885                                 goto next_pkt;
1886
1887                         if (flags & NV_RX2_ERROR) {
1888                                 if (flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
1889                                         np->stats.rx_errors++;
1890                                         goto next_pkt;
1891                                 }
1892                                 if (flags & NV_RX2_CRCERR) {
1893                                         np->stats.rx_crc_errors++;
1894                                         np->stats.rx_errors++;
1895                                         goto next_pkt;
1896                                 }
1897                                 if (flags & NV_RX2_OVERFLOW) {
1898                                         np->stats.rx_over_errors++;
1899                                         np->stats.rx_errors++;
1900                                         goto next_pkt;
1901                                 }
1902                                 if (flags & NV_RX2_ERROR4) {
1903                                         len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1904                                         if (len < 0) {
1905                                                 np->stats.rx_errors++;
1906                                                 goto next_pkt;
1907                                         }
1908                                 }
1909                                 /* framing errors are soft errors */
1910                                 if (flags & NV_RX2_FRAMINGERR) {
1911                                         if (flags & NV_RX2_SUBSTRACT1) {
1912                                                 len--;
1913                                         }
1914                                 }
1915                         }
1916                         if (np->rx_csum) {
1917                                 flags &= NV_RX2_CHECKSUMMASK;
1918                                 if (flags == NV_RX2_CHECKSUMOK1 ||
1919                                     flags == NV_RX2_CHECKSUMOK2 ||
1920                                     flags == NV_RX2_CHECKSUMOK3) {
1921                                         dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1922                                         np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1923                                 } else {
1924                                         dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1925                                 }
1926                         }
1927                 }
1928                 /* got a valid packet - forward it to the network core */
1929                 skb = np->rx_skbuff[i];
1930                 np->rx_skbuff[i] = NULL;
1931
1932                 skb_put(skb, len);
1933                 skb->protocol = eth_type_trans(skb, dev);
1934                 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1935                                         dev->name, np->cur_rx, len, skb->protocol);
1936 #ifdef CONFIG_FORCEDETH_NAPI
1937                 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
1938                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
1939                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
1940                 else
1941                         netif_receive_skb(skb);
1942 #else
1943                 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
1944                         vlan_hwaccel_rx(skb, np->vlangrp,
1945                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
1946                 else
1947                         netif_rx(skb);
1948 #endif
1949                 dev->last_rx = jiffies;
1950                 np->stats.rx_packets++;
1951                 np->stats.rx_bytes += len;
1952 next_pkt:
1953                 np->cur_rx++;
1954         }
1955
1956         return count;
1957 }
1958
1959 static void set_bufsize(struct net_device *dev)
1960 {
1961         struct fe_priv *np = netdev_priv(dev);
1962
1963         if (dev->mtu <= ETH_DATA_LEN)
1964                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
1965         else
1966                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
1967 }
1968
1969 /*
1970  * nv_change_mtu: dev->change_mtu function
1971  * Called with dev_base_lock held for read.
1972  */
1973 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1974 {
1975         struct fe_priv *np = netdev_priv(dev);
1976         int old_mtu;
1977
1978         if (new_mtu < 64 || new_mtu > np->pkt_limit)
1979                 return -EINVAL;
1980
1981         old_mtu = dev->mtu;
1982         dev->mtu = new_mtu;
1983
1984         /* return early if the buffer sizes will not change */
1985         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1986                 return 0;
1987         if (old_mtu == new_mtu)
1988                 return 0;
1989
1990         /* synchronized against open : rtnl_lock() held by caller */
1991         if (netif_running(dev)) {
1992                 u8 __iomem *base = get_hwbase(dev);
1993                 /*
1994                  * It seems that the nic preloads valid ring entries into an
1995                  * internal buffer. The procedure for flushing everything is
1996                  * guessed, there is probably a simpler approach.
1997                  * Changing the MTU is a rare event, it shouldn't matter.
1998                  */
1999                 nv_disable_irq(dev);
2000                 netif_tx_lock_bh(dev);
2001                 spin_lock(&np->lock);
2002                 /* stop engines */
2003                 nv_stop_rx(dev);
2004                 nv_stop_tx(dev);
2005                 nv_txrx_reset(dev);
2006                 /* drain rx queue */
2007                 nv_drain_rx(dev);
2008                 nv_drain_tx(dev);
2009                 /* reinit driver view of the rx queue */
2010                 set_bufsize(dev);
2011                 if (nv_init_ring(dev)) {
2012                         if (!np->in_shutdown)
2013                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2014                 }
2015                 /* reinit nic view of the rx queue */
2016                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2017                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2018                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2019                         base + NvRegRingSizes);
2020                 pci_push(base);
2021                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2022                 pci_push(base);
2023
2024                 /* restart rx engine */
2025                 nv_start_rx(dev);
2026                 nv_start_tx(dev);
2027                 spin_unlock(&np->lock);
2028                 netif_tx_unlock_bh(dev);
2029                 nv_enable_irq(dev);
2030         }
2031         return 0;
2032 }
2033
2034 static void nv_copy_mac_to_hw(struct net_device *dev)
2035 {
2036         u8 __iomem *base = get_hwbase(dev);
2037         u32 mac[2];
2038
2039         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2040                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2041         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2042
2043         writel(mac[0], base + NvRegMacAddrA);
2044         writel(mac[1], base + NvRegMacAddrB);
2045 }
2046
2047 /*
2048  * nv_set_mac_address: dev->set_mac_address function
2049  * Called with rtnl_lock() held.
2050  */
2051 static int nv_set_mac_address(struct net_device *dev, void *addr)
2052 {
2053         struct fe_priv *np = netdev_priv(dev);
2054         struct sockaddr *macaddr = (struct sockaddr*)addr;
2055
2056         if (!is_valid_ether_addr(macaddr->sa_data))
2057                 return -EADDRNOTAVAIL;
2058
2059         /* synchronized against open : rtnl_lock() held by caller */
2060         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2061
2062         if (netif_running(dev)) {
2063                 netif_tx_lock_bh(dev);
2064                 spin_lock_irq(&np->lock);
2065
2066                 /* stop rx engine */
2067                 nv_stop_rx(dev);
2068
2069                 /* set mac address */
2070                 nv_copy_mac_to_hw(dev);
2071
2072                 /* restart rx engine */
2073                 nv_start_rx(dev);
2074                 spin_unlock_irq(&np->lock);
2075                 netif_tx_unlock_bh(dev);
2076         } else {
2077                 nv_copy_mac_to_hw(dev);
2078         }
2079         return 0;
2080 }
2081
2082 /*
2083  * nv_set_multicast: dev->set_multicast function
2084  * Called with netif_tx_lock held.
2085  */
2086 static void nv_set_multicast(struct net_device *dev)
2087 {
2088         struct fe_priv *np = netdev_priv(dev);
2089         u8 __iomem *base = get_hwbase(dev);
2090         u32 addr[2];
2091         u32 mask[2];
2092         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2093
2094         memset(addr, 0, sizeof(addr));
2095         memset(mask, 0, sizeof(mask));
2096
2097         if (dev->flags & IFF_PROMISC) {
2098                 pff |= NVREG_PFF_PROMISC;
2099         } else {
2100                 pff |= NVREG_PFF_MYADDR;
2101
2102                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2103                         u32 alwaysOff[2];
2104                         u32 alwaysOn[2];
2105
2106                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2107                         if (dev->flags & IFF_ALLMULTI) {
2108                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2109                         } else {
2110                                 struct dev_mc_list *walk;
2111
2112                                 walk = dev->mc_list;
2113                                 while (walk != NULL) {
2114                                         u32 a, b;
2115                                         a = le32_to_cpu(*(u32 *) walk->dmi_addr);
2116                                         b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
2117                                         alwaysOn[0] &= a;
2118                                         alwaysOff[0] &= ~a;
2119                                         alwaysOn[1] &= b;
2120                                         alwaysOff[1] &= ~b;
2121                                         walk = walk->next;
2122                                 }
2123                         }
2124                         addr[0] = alwaysOn[0];
2125                         addr[1] = alwaysOn[1];
2126                         mask[0] = alwaysOn[0] | alwaysOff[0];
2127                         mask[1] = alwaysOn[1] | alwaysOff[1];
2128                 }
2129         }
2130         addr[0] |= NVREG_MCASTADDRA_FORCE;
2131         pff |= NVREG_PFF_ALWAYS;
2132         spin_lock_irq(&np->lock);
2133         nv_stop_rx(dev);
2134         writel(addr[0], base + NvRegMulticastAddrA);
2135         writel(addr[1], base + NvRegMulticastAddrB);
2136         writel(mask[0], base + NvRegMulticastMaskA);
2137         writel(mask[1], base + NvRegMulticastMaskB);
2138         writel(pff, base + NvRegPacketFilterFlags);
2139         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2140                 dev->name);
2141         nv_start_rx(dev);
2142         spin_unlock_irq(&np->lock);
2143 }
2144
2145 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2146 {
2147         struct fe_priv *np = netdev_priv(dev);
2148         u8 __iomem *base = get_hwbase(dev);
2149
2150         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2151
2152         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2153                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2154                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2155                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2156                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2157                 } else {
2158                         writel(pff, base + NvRegPacketFilterFlags);
2159                 }
2160         }
2161         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2162                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2163                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2164                         writel(NVREG_TX_PAUSEFRAME_ENABLE,  base + NvRegTxPauseFrame);
2165                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2166                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2167                 } else {
2168                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
2169                         writel(regmisc, base + NvRegMisc1);
2170                 }
2171         }
2172 }
2173
2174 /**
2175  * nv_update_linkspeed: Setup the MAC according to the link partner
2176  * @dev: Network device to be configured
2177  *
2178  * The function queries the PHY and checks if there is a link partner.
2179  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2180  * set to 10 MBit HD.
2181  *
2182  * The function returns 0 if there is no link partner and 1 if there is
2183  * a good link partner.
2184  */
2185 static int nv_update_linkspeed(struct net_device *dev)
2186 {
2187         struct fe_priv *np = netdev_priv(dev);
2188         u8 __iomem *base = get_hwbase(dev);
2189         int adv = 0;
2190         int lpa = 0;
2191         int adv_lpa, adv_pause, lpa_pause;
2192         int newls = np->linkspeed;
2193         int newdup = np->duplex;
2194         int mii_status;
2195         int retval = 0;
2196         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
2197
2198         /* BMSR_LSTATUS is latched, read it twice:
2199          * we want the current value.
2200          */
2201         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2202         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2203
2204         if (!(mii_status & BMSR_LSTATUS)) {
2205                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2206                                 dev->name);
2207                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2208                 newdup = 0;
2209                 retval = 0;
2210                 goto set_speed;
2211         }
2212
2213         if (np->autoneg == 0) {
2214                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2215                                 dev->name, np->fixed_mode);
2216                 if (np->fixed_mode & LPA_100FULL) {
2217                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2218                         newdup = 1;
2219                 } else if (np->fixed_mode & LPA_100HALF) {
2220                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2221                         newdup = 0;
2222                 } else if (np->fixed_mode & LPA_10FULL) {
2223                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2224                         newdup = 1;
2225                 } else {
2226                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2227                         newdup = 0;
2228                 }
2229                 retval = 1;
2230                 goto set_speed;
2231         }
2232         /* check auto negotiation is complete */
2233         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2234                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2235                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2236                 newdup = 0;
2237                 retval = 0;
2238                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2239                 goto set_speed;
2240         }
2241
2242         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2243         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2244         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2245                                 dev->name, adv, lpa);
2246
2247         retval = 1;
2248         if (np->gigabit == PHY_GIGABIT) {
2249                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2250                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2251
2252                 if ((control_1000 & ADVERTISE_1000FULL) &&
2253                         (status_1000 & LPA_1000FULL)) {
2254                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2255                                 dev->name);
2256                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2257                         newdup = 1;
2258                         goto set_speed;
2259                 }
2260         }
2261
2262         /* FIXME: handle parallel detection properly */
2263         adv_lpa = lpa & adv;
2264         if (adv_lpa & LPA_100FULL) {
2265                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2266                 newdup = 1;
2267         } else if (adv_lpa & LPA_100HALF) {
2268                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2269                 newdup = 0;
2270         } else if (adv_lpa & LPA_10FULL) {
2271                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2272                 newdup = 1;
2273         } else if (adv_lpa & LPA_10HALF) {
2274                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2275                 newdup = 0;
2276         } else {
2277                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2278                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2279                 newdup = 0;
2280         }
2281
2282 set_speed:
2283         if (np->duplex == newdup && np->linkspeed == newls)
2284                 return retval;
2285
2286         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2287                         dev->name, np->linkspeed, np->duplex, newls, newdup);
2288
2289         np->duplex = newdup;
2290         np->linkspeed = newls;
2291
2292         if (np->gigabit == PHY_GIGABIT) {
2293                 phyreg = readl(base + NvRegRandomSeed);
2294                 phyreg &= ~(0x3FF00);
2295                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2296                         phyreg |= NVREG_RNDSEED_FORCE3;
2297                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2298                         phyreg |= NVREG_RNDSEED_FORCE2;
2299                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2300                         phyreg |= NVREG_RNDSEED_FORCE;
2301                 writel(phyreg, base + NvRegRandomSeed);
2302         }
2303
2304         phyreg = readl(base + NvRegPhyInterface);
2305         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2306         if (np->duplex == 0)
2307                 phyreg |= PHY_HALF;
2308         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2309                 phyreg |= PHY_100;
2310         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2311                 phyreg |= PHY_1000;
2312         writel(phyreg, base + NvRegPhyInterface);
2313
2314         if (phyreg & PHY_RGMII) {
2315                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2316                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
2317                 else
2318                         txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
2319         } else {
2320                 txreg = NVREG_TX_DEFERRAL_DEFAULT;
2321         }
2322         writel(txreg, base + NvRegTxDeferral);
2323
2324         if (np->desc_ver == DESC_VER_1) {
2325                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
2326         } else {
2327                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2328                         txreg = NVREG_TX_WM_DESC2_3_1000;
2329                 else
2330                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
2331         }
2332         writel(txreg, base + NvRegTxWatermark);
2333
2334         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2335                 base + NvRegMisc1);
2336         pci_push(base);
2337         writel(np->linkspeed, base + NvRegLinkSpeed);
2338         pci_push(base);
2339
2340         pause_flags = 0;
2341         /* setup pause frame */
2342         if (np->duplex != 0) {
2343                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
2344                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
2345                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
2346
2347                         switch (adv_pause) {
2348                         case ADVERTISE_PAUSE_CAP:
2349                                 if (lpa_pause & LPA_PAUSE_CAP) {
2350                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2351                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2352                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2353                                 }
2354                                 break;
2355                         case ADVERTISE_PAUSE_ASYM:
2356                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
2357                                 {
2358                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2359                                 }
2360                                 break;
2361                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
2362                                 if (lpa_pause & LPA_PAUSE_CAP)
2363                                 {
2364                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
2365                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2366                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2367                                 }
2368                                 if (lpa_pause == LPA_PAUSE_ASYM)
2369                                 {
2370                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2371                                 }
2372                                 break;
2373                         }
2374                 } else {
2375                         pause_flags = np->pause_flags;
2376                 }
2377         }
2378         nv_update_pause(dev, pause_flags);
2379
2380         return retval;
2381 }
2382
2383 static void nv_linkchange(struct net_device *dev)
2384 {
2385         if (nv_update_linkspeed(dev)) {
2386                 if (!netif_carrier_ok(dev)) {
2387                         netif_carrier_on(dev);
2388                         printk(KERN_INFO "%s: link up.\n", dev->name);
2389                         nv_start_rx(dev);
2390                 }
2391         } else {
2392                 if (netif_carrier_ok(dev)) {
2393                         netif_carrier_off(dev);
2394                         printk(KERN_INFO "%s: link down.\n", dev->name);
2395                         nv_stop_rx(dev);
2396                 }
2397         }
2398 }
2399
2400 static void nv_link_irq(struct net_device *dev)
2401 {
2402         u8 __iomem *base = get_hwbase(dev);
2403         u32 miistat;
2404
2405         miistat = readl(base + NvRegMIIStatus);
2406         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2407         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
2408
2409         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
2410                 nv_linkchange(dev);
2411         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
2412 }
2413
2414 static irqreturn_t nv_nic_irq(int foo, void *data)
2415 {
2416         struct net_device *dev = (struct net_device *) data;
2417         struct fe_priv *np = netdev_priv(dev);
2418         u8 __iomem *base = get_hwbase(dev);
2419         u32 events;
2420         int i;
2421
2422         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
2423
2424         for (i=0; ; i++) {
2425                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2426                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2427                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2428                 } else {
2429                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2430                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2431                 }
2432                 pci_push(base);
2433                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2434                 if (!(events & np->irqmask))
2435                         break;
2436
2437                 spin_lock(&np->lock);
2438                 nv_tx_done(dev);
2439                 spin_unlock(&np->lock);
2440
2441                 if (events & NVREG_IRQ_LINK) {
2442                         spin_lock(&np->lock);
2443                         nv_link_irq(dev);
2444                         spin_unlock(&np->lock);
2445                 }
2446                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2447                         spin_lock(&np->lock);
2448                         nv_linkchange(dev);
2449                         spin_unlock(&np->lock);
2450                         np->link_timeout = jiffies + LINK_TIMEOUT;
2451                 }
2452                 if (events & (NVREG_IRQ_TX_ERR)) {
2453                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2454                                                 dev->name, events);
2455                 }
2456                 if (events & (NVREG_IRQ_UNKNOWN)) {
2457                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2458                                                 dev->name, events);
2459                 }
2460                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
2461                         spin_lock(&np->lock);
2462                         /* disable interrupts on the nic */
2463                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
2464                                 writel(0, base + NvRegIrqMask);
2465                         else
2466                                 writel(np->irqmask, base + NvRegIrqMask);
2467                         pci_push(base);
2468
2469                         if (!np->in_shutdown) {
2470                                 np->nic_poll_irq = np->irqmask;
2471                                 np->recover_error = 1;
2472                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2473                         }
2474                         spin_unlock(&np->lock);
2475                         break;
2476                 }
2477 #ifdef CONFIG_FORCEDETH_NAPI
2478                 if (events & NVREG_IRQ_RX_ALL) {
2479                         netif_rx_schedule(dev);
2480
2481                         /* Disable furthur receive irq's */
2482                         spin_lock(&np->lock);
2483                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
2484
2485                         if (np->msi_flags & NV_MSI_X_ENABLED)
2486                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2487                         else
2488                                 writel(np->irqmask, base + NvRegIrqMask);
2489                         spin_unlock(&np->lock);
2490                 }
2491 #else
2492                 nv_rx_process(dev, dev->weight);
2493                 if (nv_alloc_rx(dev)) {
2494                         spin_lock(&np->lock);
2495                         if (!np->in_shutdown)
2496                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2497                         spin_unlock(&np->lock);
2498                 }
2499 #endif
2500                 if (i > max_interrupt_work) {
2501                         spin_lock(&np->lock);
2502                         /* disable interrupts on the nic */
2503                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
2504                                 writel(0, base + NvRegIrqMask);
2505                         else
2506                                 writel(np->irqmask, base + NvRegIrqMask);
2507                         pci_push(base);
2508
2509                         if (!np->in_shutdown) {
2510                                 np->nic_poll_irq = np->irqmask;
2511                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2512                         }
2513                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
2514                         spin_unlock(&np->lock);
2515                         break;
2516                 }
2517
2518         }
2519         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
2520
2521         return IRQ_RETVAL(i);
2522 }
2523
2524 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
2525 {
2526         struct net_device *dev = (struct net_device *) data;
2527         struct fe_priv *np = netdev_priv(dev);
2528         u8 __iomem *base = get_hwbase(dev);
2529         u32 events;
2530         int i;
2531         unsigned long flags;
2532
2533         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
2534
2535         for (i=0; ; i++) {
2536                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
2537                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
2538                 pci_push(base);
2539                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
2540                 if (!(events & np->irqmask))
2541                         break;
2542
2543                 spin_lock_irqsave(&np->lock, flags);
2544                 nv_tx_done(dev);
2545                 spin_unlock_irqrestore(&np->lock, flags);
2546
2547                 if (events & (NVREG_IRQ_TX_ERR)) {
2548                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2549                                                 dev->name, events);
2550                 }
2551                 if (i > max_interrupt_work) {
2552                         spin_lock_irqsave(&np->lock, flags);
2553                         /* disable interrupts on the nic */
2554                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
2555                         pci_push(base);
2556
2557                         if (!np->in_shutdown) {
2558                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
2559                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2560                         }
2561                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
2562                         spin_unlock_irqrestore(&np->lock, flags);
2563                         break;
2564                 }
2565
2566         }
2567         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
2568
2569         return IRQ_RETVAL(i);
2570 }
2571
2572 #ifdef CONFIG_FORCEDETH_NAPI
2573 static int nv_napi_poll(struct net_device *dev, int *budget)
2574 {
2575         int pkts, limit = min(*budget, dev->quota);
2576         struct fe_priv *np = netdev_priv(dev);
2577         u8 __iomem *base = get_hwbase(dev);
2578         unsigned long flags;
2579
2580         pkts = nv_rx_process(dev, limit);
2581
2582         if (nv_alloc_rx(dev)) {
2583                 spin_lock_irqsave(&np->lock, flags);
2584                 if (!np->in_shutdown)
2585                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2586                 spin_unlock_irqrestore(&np->lock, flags);
2587         }
2588
2589         if (pkts < limit) {
2590                 /* all done, no more packets present */
2591                 netif_rx_complete(dev);
2592
2593                 /* re-enable receive interrupts */
2594                 spin_lock_irqsave(&np->lock, flags);
2595
2596                 np->irqmask |= NVREG_IRQ_RX_ALL;
2597                 if (np->msi_flags & NV_MSI_X_ENABLED)
2598                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2599                 else
2600                         writel(np->irqmask, base + NvRegIrqMask);
2601
2602                 spin_unlock_irqrestore(&np->lock, flags);
2603                 return 0;
2604         } else {
2605                 /* used up our quantum, so reschedule */
2606                 dev->quota -= pkts;
2607                 *budget -= pkts;
2608                 return 1;
2609         }
2610 }
2611 #endif
2612
2613 #ifdef CONFIG_FORCEDETH_NAPI
2614 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
2615 {
2616         struct net_device *dev = (struct net_device *) data;
2617         u8 __iomem *base = get_hwbase(dev);
2618         u32 events;
2619
2620         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
2621         writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
2622
2623         if (events) {
2624                 netif_rx_schedule(dev);
2625                 /* disable receive interrupts on the nic */
2626                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2627                 pci_push(base);
2628         }
2629         return IRQ_HANDLED;
2630 }
2631 #else
2632 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
2633 {
2634         struct net_device *dev = (struct net_device *) data;
2635         struct fe_priv *np = netdev_priv(dev);
2636         u8 __iomem *base = get_hwbase(dev);
2637         u32 events;
2638         int i;
2639         unsigned long flags;
2640
2641         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
2642
2643         for (i=0; ; i++) {
2644                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
2645                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
2646                 pci_push(base);
2647                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
2648                 if (!(events & np->irqmask))
2649                         break;
2650
2651                 nv_rx_process(dev, dev->weight);
2652                 if (nv_alloc_rx(dev)) {
2653                         spin_lock_irqsave(&np->lock, flags);
2654                         if (!np->in_shutdown)
2655                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2656                         spin_unlock_irqrestore(&np->lock, flags);
2657                 }
2658
2659                 if (i > max_interrupt_work) {
2660                         spin_lock_irqsave(&np->lock, flags);
2661                         /* disable interrupts on the nic */
2662                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2663                         pci_push(base);
2664
2665                         if (!np->in_shutdown) {
2666                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
2667                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2668                         }
2669                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
2670                         spin_unlock_irqrestore(&np->lock, flags);
2671                         break;
2672                 }
2673         }
2674         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
2675
2676         return IRQ_RETVAL(i);
2677 }
2678 #endif
2679
2680 static irqreturn_t nv_nic_irq_other(int foo, void *data)
2681 {
2682         struct net_device *dev = (struct net_device *) data;
2683         struct fe_priv *np = netdev_priv(dev);
2684         u8 __iomem *base = get_hwbase(dev);
2685         u32 events;
2686         int i;
2687         unsigned long flags;
2688
2689         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
2690
2691         for (i=0; ; i++) {
2692                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
2693                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
2694                 pci_push(base);
2695                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2696                 if (!(events & np->irqmask))
2697                         break;
2698
2699                 if (events & NVREG_IRQ_LINK) {
2700                         spin_lock_irqsave(&np->lock, flags);
2701                         nv_link_irq(dev);
2702                         spin_unlock_irqrestore(&np->lock, flags);
2703                 }
2704                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2705                         spin_lock_irqsave(&np->lock, flags);
2706                         nv_linkchange(dev);
2707                         spin_unlock_irqrestore(&np->lock, flags);
2708                         np->link_timeout = jiffies + LINK_TIMEOUT;
2709                 }
2710                 if (events & NVREG_IRQ_RECOVER_ERROR) {
2711                         spin_lock_irq(&np->lock);
2712                         /* disable interrupts on the nic */
2713                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
2714                         pci_push(base);
2715
2716                         if (!np->in_shutdown) {
2717                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
2718                                 np->recover_error = 1;
2719                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2720                         }
2721                         spin_unlock_irq(&np->lock);
2722                         break;
2723                 }
2724                 if (events & (NVREG_IRQ_UNKNOWN)) {
2725                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2726                                                 dev->name, events);
2727                 }
2728                 if (i > max_interrupt_work) {
2729                         spin_lock_irqsave(&np->lock, flags);
2730                         /* disable interrupts on the nic */
2731                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
2732                         pci_push(base);
2733
2734                         if (!np->in_shutdown) {
2735                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
2736                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2737                         }
2738                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
2739                         spin_unlock_irqrestore(&np->lock, flags);
2740                         break;
2741                 }
2742
2743         }
2744         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
2745
2746         return IRQ_RETVAL(i);
2747 }
2748
2749 static irqreturn_t nv_nic_irq_test(int foo, void *data)
2750 {
2751         struct net_device *dev = (struct net_device *) data;
2752         struct fe_priv *np = netdev_priv(dev);
2753         u8 __iomem *base = get_hwbase(dev);
2754         u32 events;
2755
2756         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
2757
2758         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2759                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2760                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
2761         } else {
2762                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2763                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
2764         }
2765         pci_push(base);
2766         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2767         if (!(events & NVREG_IRQ_TIMER))
2768                 return IRQ_RETVAL(0);
2769
2770         spin_lock(&np->lock);
2771         np->intr_test = 1;
2772         spin_unlock(&np->lock);
2773
2774         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
2775
2776         return IRQ_RETVAL(1);
2777 }
2778
2779 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
2780 {
2781         u8 __iomem *base = get_hwbase(dev);
2782         int i;
2783         u32 msixmap = 0;
2784
2785         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
2786          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
2787          * the remaining 8 interrupts.
2788          */
2789         for (i = 0; i < 8; i++) {
2790                 if ((irqmask >> i) & 0x1) {
2791                         msixmap |= vector << (i << 2);
2792                 }
2793         }
2794         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
2795
2796         msixmap = 0;
2797         for (i = 0; i < 8; i++) {
2798                 if ((irqmask >> (i + 8)) & 0x1) {
2799                         msixmap |= vector << (i << 2);
2800                 }
2801         }
2802         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
2803 }
2804
2805 static int nv_request_irq(struct net_device *dev, int intr_test)
2806 {
2807         struct fe_priv *np = get_nvpriv(dev);
2808         u8 __iomem *base = get_hwbase(dev);
2809         int ret = 1;
2810         int i;
2811
2812         if (np->msi_flags & NV_MSI_X_CAPABLE) {
2813                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2814                         np->msi_x_entry[i].entry = i;
2815                 }
2816                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
2817                         np->msi_flags |= NV_MSI_X_ENABLED;
2818                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
2819                                 /* Request irq for rx handling */
2820                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
2821                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
2822                                         pci_disable_msix(np->pci_dev);
2823                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2824                                         goto out_err;
2825                                 }
2826                                 /* Request irq for tx handling */
2827                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
2828                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
2829                                         pci_disable_msix(np->pci_dev);
2830                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2831                                         goto out_free_rx;
2832                                 }
2833                                 /* Request irq for link and timer handling */
2834                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
2835                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
2836                                         pci_disable_msix(np->pci_dev);
2837                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2838                                         goto out_free_tx;
2839                                 }
2840                                 /* map interrupts to their respective vector */
2841                                 writel(0, base + NvRegMSIXMap0);
2842                                 writel(0, base + NvRegMSIXMap1);
2843                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
2844                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
2845                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
2846                         } else {
2847                                 /* Request irq for all interrupts */
2848                                 if ((!intr_test &&
2849                                      request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2850                                     (intr_test &&
2851                                      request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
2852                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2853                                         pci_disable_msix(np->pci_dev);
2854                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2855                                         goto out_err;
2856                                 }
2857
2858                                 /* map interrupts to vector 0 */
2859                                 writel(0, base + NvRegMSIXMap0);
2860                                 writel(0, base + NvRegMSIXMap1);
2861                         }
2862                 }
2863         }
2864         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
2865                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
2866                         np->msi_flags |= NV_MSI_ENABLED;
2867                         if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2868                             (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
2869                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2870                                 pci_disable_msi(np->pci_dev);
2871                                 np->msi_flags &= ~NV_MSI_ENABLED;
2872                                 goto out_err;
2873                         }
2874
2875                         /* map interrupts to vector 0 */
2876                         writel(0, base + NvRegMSIMap0);
2877                         writel(0, base + NvRegMSIMap1);
2878                         /* enable msi vector 0 */
2879                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
2880                 }
2881         }
2882         if (ret != 0) {
2883                 if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2884                     (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0))
2885                         goto out_err;
2886
2887         }
2888
2889         return 0;
2890 out_free_tx:
2891         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
2892 out_free_rx:
2893         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
2894 out_err:
2895         return 1;
2896 }
2897
2898 static void nv_free_irq(struct net_device *dev)
2899 {
2900         struct fe_priv *np = get_nvpriv(dev);
2901         int i;
2902
2903         if (np->msi_flags & NV_MSI_X_ENABLED) {
2904                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2905                         free_irq(np->msi_x_entry[i].vector, dev);
2906                 }
2907                 pci_disable_msix(np->pci_dev);
2908                 np->msi_flags &= ~NV_MSI_X_ENABLED;
2909         } else {
2910                 free_irq(np->pci_dev->irq, dev);
2911                 if (np->msi_flags & NV_MSI_ENABLED) {
2912                         pci_disable_msi(np->pci_dev);
2913                         np->msi_flags &= ~NV_MSI_ENABLED;
2914                 }
2915         }
2916 }
2917
2918 static void nv_do_nic_poll(unsigned long data)
2919 {
2920         struct net_device *dev = (struct net_device *) data;
2921         struct fe_priv *np = netdev_priv(dev);
2922         u8 __iomem *base = get_hwbase(dev);
2923         u32 mask = 0;
2924
2925         /*
2926          * First disable irq(s) and then
2927          * reenable interrupts on the nic, we have to do this before calling
2928          * nv_nic_irq because that may decide to do otherwise
2929          */
2930
2931         if (!using_multi_irqs(dev)) {
2932                 if (np->msi_flags & NV_MSI_X_ENABLED)
2933                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2934                 else
2935                         disable_irq_lockdep(dev->irq);
2936                 mask = np->irqmask;
2937         } else {
2938                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
2939                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
2940                         mask |= NVREG_IRQ_RX_ALL;
2941                 }
2942                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
2943                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
2944                         mask |= NVREG_IRQ_TX_ALL;
2945                 }
2946                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
2947                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
2948                         mask |= NVREG_IRQ_OTHER;
2949                 }
2950         }
2951         np->nic_poll_irq = 0;
2952
2953         if (np->recover_error) {
2954                 np->recover_error = 0;
2955                 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
2956                 if (netif_running(dev)) {
2957                         netif_tx_lock_bh(dev);
2958                         spin_lock(&np->lock);
2959                         /* stop engines */
2960                         nv_stop_rx(dev);
2961                         nv_stop_tx(dev);
2962                         nv_txrx_reset(dev);
2963                         /* drain rx queue */
2964                         nv_drain_rx(dev);
2965                         nv_drain_tx(dev);
2966                         /* reinit driver view of the rx queue */
2967                         set_bufsize(dev);
2968                         if (nv_init_ring(dev)) {
2969                                 if (!np->in_shutdown)
2970                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2971                         }
2972                         /* reinit nic view of the rx queue */
2973                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2974                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2975                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2976                                 base + NvRegRingSizes);
2977                         pci_push(base);
2978                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2979                         pci_push(base);
2980
2981                         /* restart rx engine */
2982                         nv_start_rx(dev);
2983                         nv_start_tx(dev);
2984                         spin_unlock(&np->lock);
2985                         netif_tx_unlock_bh(dev);
2986                 }
2987         }
2988
2989         /* FIXME: Do we need synchronize_irq(dev->irq) here? */
2990
2991         writel(mask, base + NvRegIrqMask);
2992         pci_push(base);
2993
2994         if (!using_multi_irqs(dev)) {
2995                 nv_nic_irq(0, dev);
2996                 if (np->msi_flags & NV_MSI_X_ENABLED)
2997                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2998                 else
2999                         enable_irq_lockdep(dev->irq);
3000         } else {
3001                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3002                         nv_nic_irq_rx(0, dev);
3003                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3004                 }
3005                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3006                         nv_nic_irq_tx(0, dev);
3007                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3008                 }
3009                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3010                         nv_nic_irq_other(0, dev);
3011                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3012                 }
3013         }
3014 }
3015
3016 #ifdef CONFIG_NET_POLL_CONTROLLER
3017 static void nv_poll_controller(struct net_device *dev)
3018 {
3019         nv_do_nic_poll((unsigned long) dev);
3020 }
3021 #endif
3022
3023 static void nv_do_stats_poll(unsigned long data)
3024 {
3025         struct net_device *dev = (struct net_device *) data;
3026         struct fe_priv *np = netdev_priv(dev);
3027         u8 __iomem *base = get_hwbase(dev);
3028
3029         np->estats.tx_bytes += readl(base + NvRegTxCnt);
3030         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
3031         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
3032         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
3033         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
3034         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
3035         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
3036         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
3037         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
3038         np->estats.tx_deferral += readl(base + NvRegTxDef);
3039         np->estats.tx_packets += readl(base + NvRegTxFrame);
3040         np->estats.tx_pause += readl(base + NvRegTxPause);
3041         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
3042         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
3043         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
3044         np->estats.rx_runt += readl(base + NvRegRxRunt);
3045         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
3046         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
3047         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
3048         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
3049         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
3050         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
3051         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
3052         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
3053         np->estats.rx_bytes += readl(base + NvRegRxCnt);
3054         np->estats.rx_pause += readl(base + NvRegRxPause);
3055         np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
3056         np->estats.rx_packets =
3057                 np->estats.rx_unicast +
3058                 np->estats.rx_multicast +
3059                 np->estats.rx_broadcast;
3060         np->estats.rx_errors_total =
3061                 np->estats.rx_crc_errors +
3062                 np->estats.rx_over_errors +
3063                 np->estats.rx_frame_error +
3064                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
3065                 np->estats.rx_late_collision +
3066                 np->estats.rx_runt +
3067                 np->estats.rx_frame_too_long;
3068
3069         if (!np->in_shutdown)
3070                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
3071 }
3072
3073 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3074 {
3075         struct fe_priv *np = netdev_priv(dev);
3076         strcpy(info->driver, "forcedeth");
3077         strcpy(info->version, FORCEDETH_VERSION);
3078         strcpy(info->bus_info, pci_name(np->pci_dev));
3079 }
3080
3081 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3082 {
3083         struct fe_priv *np = netdev_priv(dev);
3084         wolinfo->supported = WAKE_MAGIC;
3085
3086         spin_lock_irq(&np->lock);
3087         if (np->wolenabled)
3088                 wolinfo->wolopts = WAKE_MAGIC;
3089         spin_unlock_irq(&np->lock);
3090 }
3091
3092 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3093 {
3094         struct fe_priv *np = netdev_priv(dev);
3095         u8 __iomem *base = get_hwbase(dev);
3096         u32 flags = 0;
3097
3098         if (wolinfo->wolopts == 0) {
3099                 np->wolenabled = 0;
3100         } else if (wolinfo->wolopts & WAKE_MAGIC) {
3101                 np->wolenabled = 1;
3102                 flags = NVREG_WAKEUPFLAGS_ENABLE;
3103         }
3104         if (netif_running(dev)) {
3105                 spin_lock_irq(&np->lock);
3106                 writel(flags, base + NvRegWakeUpFlags);
3107                 spin_unlock_irq(&np->lock);
3108         }
3109         return 0;
3110 }
3111
3112 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3113 {
3114         struct fe_priv *np = netdev_priv(dev);
3115         int adv;
3116
3117         spin_lock_irq(&np->lock);
3118         ecmd->port = PORT_MII;
3119         if (!netif_running(dev)) {
3120                 /* We do not track link speed / duplex setting if the
3121                  * interface is disabled. Force a link check */
3122                 if (nv_update_linkspeed(dev)) {
3123                         if (!netif_carrier_ok(dev))
3124                                 netif_carrier_on(dev);
3125                 } else {
3126                         if (netif_carrier_ok(dev))
3127                                 netif_carrier_off(dev);
3128                 }
3129         }
3130
3131         if (netif_carrier_ok(dev)) {
3132                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
3133                 case NVREG_LINKSPEED_10:
3134                         ecmd->speed = SPEED_10;
3135                         break;
3136                 case NVREG_LINKSPEED_100:
3137                         ecmd->speed = SPEED_100;
3138                         break;
3139                 case NVREG_LINKSPEED_1000:
3140                         ecmd->speed = SPEED_1000;
3141                         break;
3142                 }
3143                 ecmd->duplex = DUPLEX_HALF;
3144                 if (np->duplex)
3145                         ecmd->duplex = DUPLEX_FULL;
3146         } else {
3147                 ecmd->speed = -1;
3148                 ecmd->duplex = -1;
3149         }
3150
3151         ecmd->autoneg = np->autoneg;
3152
3153         ecmd->advertising = ADVERTISED_MII;
3154         if (np->autoneg) {
3155                 ecmd->advertising |= ADVERTISED_Autoneg;
3156                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3157                 if (adv & ADVERTISE_10HALF)
3158                         ecmd->advertising |= ADVERTISED_10baseT_Half;
3159                 if (adv & ADVERTISE_10FULL)
3160                         ecmd->advertising |= ADVERTISED_10baseT_Full;
3161                 if (adv & ADVERTISE_100HALF)
3162                         ecmd->advertising |= ADVERTISED_100baseT_Half;
3163                 if (adv & ADVERTISE_100FULL)
3164                         ecmd->advertising |= ADVERTISED_100baseT_Full;
3165                 if (np->gigabit == PHY_GIGABIT) {
3166                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3167                         if (adv & ADVERTISE_1000FULL)
3168                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3169                 }
3170         }
3171         ecmd->supported = (SUPPORTED_Autoneg |
3172                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
3173                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
3174                 SUPPORTED_MII);
3175         if (np->gigabit == PHY_GIGABIT)
3176                 ecmd->supported |= SUPPORTED_1000baseT_Full;
3177
3178         ecmd->phy_address = np->phyaddr;
3179         ecmd->transceiver = XCVR_EXTERNAL;
3180
3181         /* ignore maxtxpkt, maxrxpkt for now */
3182         spin_unlock_irq(&np->lock);
3183         return 0;
3184 }
3185
3186 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3187 {
3188         struct fe_priv *np = netdev_priv(dev);
3189
3190         if (ecmd->port != PORT_MII)
3191                 return -EINVAL;
3192         if (ecmd->transceiver != XCVR_EXTERNAL)
3193                 return -EINVAL;
3194         if (ecmd->phy_address != np->phyaddr) {
3195                 /* TODO: support switching between multiple phys. Should be
3196                  * trivial, but not enabled due to lack of test hardware. */
3197                 return -EINVAL;
3198         }
3199         if (ecmd->autoneg == AUTONEG_ENABLE) {
3200                 u32 mask;
3201
3202                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3203                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3204                 if (np->gigabit == PHY_GIGABIT)
3205                         mask |= ADVERTISED_1000baseT_Full;
3206
3207                 if ((ecmd->advertising & mask) == 0)
3208                         return -EINVAL;
3209
3210         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
3211                 /* Note: autonegotiation disable, speed 1000 intentionally
3212                  * forbidden - noone should need that. */
3213
3214                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
3215                         return -EINVAL;
3216                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
3217                         return -EINVAL;
3218         } else {
3219                 return -EINVAL;
3220         }
3221
3222         netif_carrier_off(dev);
3223         if (netif_running(dev)) {
3224                 nv_disable_irq(dev);
3225                 netif_tx_lock_bh(dev);
3226                 spin_lock(&np->lock);
3227                 /* stop engines */
3228                 nv_stop_rx(dev);
3229                 nv_stop_tx(dev);
3230                 spin_unlock(&np->lock);
3231                 netif_tx_unlock_bh(dev);
3232         }
3233
3234         if (ecmd->autoneg == AUTONEG_ENABLE) {
3235                 int adv, bmcr;
3236
3237                 np->autoneg = 1;
3238
3239                 /* advertise only what has been requested */
3240                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3241                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3242                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
3243                         adv |= ADVERTISE_10HALF;
3244                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
3245                         adv |= ADVERTISE_10FULL;
3246                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
3247                         adv |= ADVERTISE_100HALF;
3248                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
3249                         adv |= ADVERTISE_100FULL;
3250                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
3251                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3252                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3253                         adv |=  ADVERTISE_PAUSE_ASYM;
3254                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3255
3256                 if (np->gigabit == PHY_GIGABIT) {
3257                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3258                         adv &= ~ADVERTISE_1000FULL;
3259                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
3260                                 adv |= ADVERTISE_1000FULL;
3261                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3262                 }
3263
3264                 if (netif_running(dev))
3265                         printk(KERN_INFO "%s: link down.\n", dev->name);
3266                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3267                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3268                         bmcr |= BMCR_ANENABLE;
3269                         /* reset the phy in order for settings to stick,
3270                          * and cause autoneg to start */
3271                         if (phy_reset(dev, bmcr)) {
3272                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3273                                 return -EINVAL;
3274                         }
3275                 } else {
3276                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3277                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3278                 }
3279         } else {
3280                 int adv, bmcr;
3281
3282                 np->autoneg = 0;
3283
3284                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3285                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3286                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
3287                         adv |= ADVERTISE_10HALF;
3288                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
3289                         adv |= ADVERTISE_10FULL;
3290                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
3291                         adv |= ADVERTISE_100HALF;
3292                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
3293                         adv |= ADVERTISE_100FULL;
3294                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3295                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
3296                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3297                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3298                 }
3299                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
3300                         adv |=  ADVERTISE_PAUSE_ASYM;
3301                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3302                 }
3303                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3304                 np->fixed_mode = adv;
3305
3306                 if (np->gigabit == PHY_GIGABIT) {
3307                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3308                         adv &= ~ADVERTISE_1000FULL;
3309                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3310                 }
3311
3312                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3313                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
3314                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
3315                         bmcr |= BMCR_FULLDPLX;
3316                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
3317                         bmcr |= BMCR_SPEED100;
3318                 if (np->phy_oui == PHY_OUI_MARVELL) {
3319                         /* reset the phy in order for forced mode settings to stick */
3320                         if (phy_reset(dev, bmcr)) {
3321                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3322                                 return -EINVAL;
3323                         }
3324                 } else {
3325                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3326                         if (netif_running(dev)) {
3327                                 /* Wait a bit and then reconfigure the nic. */
3328                                 udelay(10);
3329                                 nv_linkchange(dev);
3330                         }
3331                 }
3332         }
3333
3334         if (netif_running(dev)) {
3335                 nv_start_rx(dev);
3336                 nv_start_tx(dev);
3337                 nv_enable_irq(dev);
3338         }
3339
3340         return 0;
3341 }
3342
3343 #define FORCEDETH_REGS_VER      1
3344
3345 static int nv_get_regs_len(struct net_device *dev)
3346 {
3347         struct fe_priv *np = netdev_priv(dev);
3348         return np->register_size;
3349 }
3350
3351 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
3352 {
3353         struct fe_priv *np = netdev_priv(dev);
3354         u8 __iomem *base = get_hwbase(dev);
3355         u32 *rbuf = buf;
3356         int i;
3357
3358         regs->version = FORCEDETH_REGS_VER;
3359         spin_lock_irq(&np->lock);
3360         for (i = 0;i <= np->register_size/sizeof(u32); i++)
3361                 rbuf[i] = readl(base + i*sizeof(u32));
3362         spin_unlock_irq(&np->lock);
3363 }
3364
3365 static int nv_nway_reset(struct net_device *dev)
3366 {
3367         struct fe_priv *np = netdev_priv(dev);
3368         int ret;
3369
3370         if (np->autoneg) {
3371                 int bmcr;
3372
3373                 netif_carrier_off(dev);
3374                 if (netif_running(dev)) {
3375                         nv_disable_irq(dev);
3376                         netif_tx_lock_bh(dev);
3377                         spin_lock(&np->lock);
3378                         /* stop engines */
3379                         nv_stop_rx(dev);
3380                         nv_stop_tx(dev);
3381                         spin_unlock(&np->lock);
3382                         netif_tx_unlock_bh(dev);
3383                         printk(KERN_INFO "%s: link down.\n", dev->name);
3384                 }
3385
3386                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3387                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3388                         bmcr |= BMCR_ANENABLE;
3389                         /* reset the phy in order for settings to stick*/
3390                         if (phy_reset(dev, bmcr)) {
3391                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3392                                 return -EINVAL;
3393                         }
3394                 } else {
3395                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3396                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3397                 }
3398
3399                 if (netif_running(dev)) {
3400                         nv_start_rx(dev);
3401                         nv_start_tx(dev);
3402                         nv_enable_irq(dev);
3403                 }
3404                 ret = 0;
3405         } else {
3406                 ret = -EINVAL;
3407         }
3408
3409         return ret;
3410 }
3411
3412 static int nv_set_tso(struct net_device *dev, u32 value)
3413 {
3414         struct fe_priv *np = netdev_priv(dev);
3415
3416         if ((np->driver_data & DEV_HAS_CHECKSUM))
3417                 return ethtool_op_set_tso(dev, value);
3418         else
3419                 return -EOPNOTSUPP;
3420 }
3421
3422 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3423 {
3424         struct fe_priv *np = netdev_priv(dev);
3425
3426         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3427         ring->rx_mini_max_pending = 0;
3428         ring->rx_jumbo_max_pending = 0;
3429         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3430
3431         ring->rx_pending = np->rx_ring_size;
3432         ring->rx_mini_pending = 0;
3433         ring->rx_jumbo_pending = 0;
3434         ring->tx_pending = np->tx_ring_size;
3435 }
3436
3437 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3438 {
3439         struct fe_priv *np = netdev_priv(dev);
3440         u8 __iomem *base = get_hwbase(dev);
3441         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff, *rx_dma, *tx_dma, *tx_dma_len;
3442         dma_addr_t ring_addr;
3443
3444         if (ring->rx_pending < RX_RING_MIN ||
3445             ring->tx_pending < TX_RING_MIN ||
3446             ring->rx_mini_pending != 0 ||
3447             ring->rx_jumbo_pending != 0 ||
3448             (np->desc_ver == DESC_VER_1 &&
3449              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
3450               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
3451             (np->desc_ver != DESC_VER_1 &&
3452              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
3453               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
3454                 return -EINVAL;
3455         }
3456
3457         /* allocate new rings */
3458         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3459                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3460                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3461                                             &ring_addr);
3462         } else {
3463                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3464                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3465                                             &ring_addr);
3466         }
3467         rx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->rx_pending, GFP_KERNEL);
3468         rx_dma = kmalloc(sizeof(dma_addr_t) * ring->rx_pending, GFP_KERNEL);
3469         tx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->tx_pending, GFP_KERNEL);
3470         tx_dma = kmalloc(sizeof(dma_addr_t) * ring->tx_pending, GFP_KERNEL);
3471         tx_dma_len = kmalloc(sizeof(unsigned int) * ring->tx_pending, GFP_KERNEL);
3472         if (!rxtx_ring || !rx_skbuff || !rx_dma || !tx_skbuff || !tx_dma || !tx_dma_len) {
3473                 /* fall back to old rings */
3474                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3475                         if (rxtx_ring)
3476                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3477                                                     rxtx_ring, ring_addr);
3478                 } else {
3479                         if (rxtx_ring)
3480                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3481                                                     rxtx_ring, ring_addr);
3482                 }
3483                 if (rx_skbuff)
3484                         kfree(rx_skbuff);
3485                 if (rx_dma)
3486                         kfree(rx_dma);
3487                 if (tx_skbuff)
3488                         kfree(tx_skbuff);
3489                 if (tx_dma)
3490                         kfree(tx_dma);
3491                 if (tx_dma_len)
3492                         kfree(tx_dma_len);
3493                 goto exit;
3494         }
3495
3496         if (netif_running(dev)) {
3497                 nv_disable_irq(dev);
3498                 netif_tx_lock_bh(dev);
3499                 spin_lock(&np->lock);
3500                 /* stop engines */
3501                 nv_stop_rx(dev);
3502                 nv_stop_tx(dev);
3503                 nv_txrx_reset(dev);
3504                 /* drain queues */
3505                 nv_drain_rx(dev);
3506                 nv_drain_tx(dev);
3507                 /* delete queues */
3508                 free_rings(dev);
3509         }
3510
3511         /* set new values */
3512         np->rx_ring_size = ring->rx_pending;
3513         np->tx_ring_size = ring->tx_pending;
3514         np->tx_limit_stop = ring->tx_pending - TX_LIMIT_DIFFERENCE;
3515         np->tx_limit_start = ring->tx_pending - TX_LIMIT_DIFFERENCE - 1;
3516         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3517                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
3518                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
3519         } else {
3520                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
3521                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
3522         }
3523         np->rx_skbuff = (struct sk_buff**)rx_skbuff;
3524         np->rx_dma = (dma_addr_t*)rx_dma;
3525         np->tx_skbuff = (struct sk_buff**)tx_skbuff;
3526         np->tx_dma = (dma_addr_t*)tx_dma;
3527         np->tx_dma_len = (unsigned int*)tx_dma_len;
3528         np->ring_addr = ring_addr;
3529
3530         memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
3531         memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
3532         memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
3533         memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
3534         memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
3535
3536         if (netif_running(dev)) {
3537                 /* reinit driver view of the queues */
3538                 set_bufsize(dev);
3539                 if (nv_init_ring(dev)) {
3540                         if (!np->in_shutdown)
3541                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3542                 }
3543
3544                 /* reinit nic view of the queues */
3545                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3546                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3547                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3548                         base + NvRegRingSizes);
3549                 pci_push(base);
3550                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3551                 pci_push(base);
3552
3553                 /* restart engines */
3554                 nv_start_rx(dev);
3555                 nv_start_tx(dev);
3556                 spin_unlock(&np->lock);
3557                 netif_tx_unlock_bh(dev);
3558                 nv_enable_irq(dev);
3559         }
3560         return 0;
3561 exit:
3562         return -ENOMEM;
3563 }
3564
3565 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3566 {
3567         struct fe_priv *np = netdev_priv(dev);
3568
3569         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
3570         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
3571         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
3572 }
3573
3574 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3575 {
3576         struct fe_priv *np = netdev_priv(dev);
3577         int adv, bmcr;
3578
3579         if ((!np->autoneg && np->duplex == 0) ||
3580             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
3581                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
3582                        dev->name);
3583                 return -EINVAL;
3584         }
3585         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
3586                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
3587                 return -EINVAL;
3588         }
3589
3590         netif_carrier_off(dev);
3591         if (netif_running(dev)) {
3592                 nv_disable_irq(dev);
3593                 netif_tx_lock_bh(dev);
3594                 spin_lock(&np->lock);
3595                 /* stop engines */
3596                 nv_stop_rx(dev);
3597                 nv_stop_tx(dev);
3598                 spin_unlock(&np->lock);
3599                 netif_tx_unlock_bh(dev);
3600         }
3601
3602         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
3603         if (pause->rx_pause)
3604                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
3605         if (pause->tx_pause)
3606                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
3607
3608         if (np->autoneg && pause->autoneg) {
3609                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
3610
3611                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3612                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3613                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
3614                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3615                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3616                         adv |=  ADVERTISE_PAUSE_ASYM;
3617                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3618
3619                 if (netif_running(dev))
3620                         printk(KERN_INFO "%s: link down.\n", dev->name);
3621                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3622                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3623                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3624         } else {
3625                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3626                 if (pause->rx_pause)
3627                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3628                 if (pause->tx_pause)
3629                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3630
3631                 if (!netif_running(dev))
3632                         nv_update_linkspeed(dev);
3633                 else
3634                         nv_update_pause(dev, np->pause_flags);
3635         }
3636
3637         if (netif_running(dev)) {
3638                 nv_start_rx(dev);
3639                 nv_start_tx(dev);
3640                 nv_enable_irq(dev);
3641         }
3642         return 0;
3643 }
3644
3645 static u32 nv_get_rx_csum(struct net_device *dev)
3646 {
3647         struct fe_priv *np = netdev_priv(dev);
3648         return (np->rx_csum) != 0;
3649 }
3650
3651 static int nv_set_rx_csum(struct net_device *dev, u32 data)
3652 {
3653         struct fe_priv *np = netdev_priv(dev);
3654         u8 __iomem *base = get_hwbase(dev);
3655         int retcode = 0;
3656
3657         if (np->driver_data & DEV_HAS_CHECKSUM) {
3658                 if (data) {
3659                         np->rx_csum = 1;
3660                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
3661                 } else {
3662                         np->rx_csum = 0;
3663                         /* vlan is dependent on rx checksum offload */
3664                         if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
3665                                 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
3666                 }
3667                 if (netif_running(dev)) {
3668                         spin_lock_irq(&np->lock);
3669                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
3670                         spin_unlock_irq(&np->lock);
3671                 }
3672         } else {
3673                 return -EINVAL;
3674         }
3675
3676         return retcode;
3677 }
3678
3679 static int nv_set_tx_csum(struct net_device *dev, u32 data)
3680 {
3681         struct fe_priv *np = netdev_priv(dev);
3682
3683         if (np->driver_data & DEV_HAS_CHECKSUM)
3684                 return ethtool_op_set_tx_hw_csum(dev, data);
3685         else
3686                 return -EOPNOTSUPP;
3687 }
3688
3689 static int nv_set_sg(struct net_device *dev, u32 data)
3690 {
3691         struct fe_priv *np = netdev_priv(dev);
3692
3693         if (np->driver_data & DEV_HAS_CHECKSUM)
3694                 return ethtool_op_set_sg(dev, data);
3695         else
3696                 return -EOPNOTSUPP;
3697 }
3698
3699 static int nv_get_stats_count(struct net_device *dev)
3700 {
3701         struct fe_priv *np = netdev_priv(dev);
3702
3703         if (np->driver_data & DEV_HAS_STATISTICS)
3704                 return sizeof(struct nv_ethtool_stats)/sizeof(u64);
3705         else
3706                 return 0;
3707 }
3708
3709 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
3710 {
3711         struct fe_priv *np = netdev_priv(dev);
3712
3713         /* update stats */
3714         nv_do_stats_poll((unsigned long)dev);
3715
3716         memcpy(buffer, &np->estats, nv_get_stats_count(dev)*sizeof(u64));
3717 }
3718
3719 static int nv_self_test_count(struct net_device *dev)
3720 {
3721         struct fe_priv *np = netdev_priv(dev);
3722
3723         if (np->driver_data & DEV_HAS_TEST_EXTENDED)
3724                 return NV_TEST_COUNT_EXTENDED;
3725         else
3726                 return NV_TEST_COUNT_BASE;
3727 }
3728
3729 static int nv_link_test(struct net_device *dev)
3730 {
3731         struct fe_priv *np = netdev_priv(dev);
3732         int mii_status;
3733
3734         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3735         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3736
3737         /* check phy link status */
3738         if (!(mii_status & BMSR_LSTATUS))
3739                 return 0;
3740         else
3741                 return 1;
3742 }
3743
3744 static int nv_register_test(struct net_device *dev)
3745 {
3746         u8 __iomem *base = get_hwbase(dev);
3747         int i = 0;
3748         u32 orig_read, new_read;
3749
3750         do {
3751                 orig_read = readl(base + nv_registers_test[i].reg);
3752
3753                 /* xor with mask to toggle bits */
3754                 orig_read ^= nv_registers_test[i].mask;
3755
3756                 writel(orig_read, base + nv_registers_test[i].reg);
3757
3758                 new_read = readl(base + nv_registers_test[i].reg);
3759
3760                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
3761                         return 0;
3762
3763                 /* restore original value */
3764                 orig_read ^= nv_registers_test[i].mask;
3765                 writel(orig_read, base + nv_registers_test[i].reg);
3766
3767         } while (nv_registers_test[++i].reg != 0);
3768
3769         return 1;
3770 }
3771
3772 static int nv_interrupt_test(struct net_device *dev)
3773 {
3774         struct fe_priv *np = netdev_priv(dev);
3775         u8 __iomem *base = get_hwbase(dev);
3776         int ret = 1;
3777         int testcnt;
3778         u32 save_msi_flags, save_poll_interval = 0;
3779
3780         if (netif_running(dev)) {
3781                 /* free current irq */
3782                 nv_free_irq(dev);
3783                 save_poll_interval = readl(base+NvRegPollingInterval);
3784         }
3785
3786         /* flag to test interrupt handler */
3787         np->intr_test = 0;
3788
3789         /* setup test irq */
3790         save_msi_flags = np->msi_flags;
3791         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
3792         np->msi_flags |= 0x001; /* setup 1 vector */
3793         if (nv_request_irq(dev, 1))
3794                 return 0;
3795
3796         /* setup timer interrupt */
3797         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
3798         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3799
3800         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
3801
3802         /* wait for at least one interrupt */
3803         msleep(100);
3804
3805         spin_lock_irq(&np->lock);
3806
3807         /* flag should be set within ISR */
3808         testcnt = np->intr_test;
3809         if (!testcnt)
3810                 ret = 2;
3811
3812         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
3813         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3814                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3815         else
3816                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3817
3818         spin_unlock_irq(&np->lock);
3819
3820         nv_free_irq(dev);
3821
3822         np->msi_flags = save_msi_flags;
3823
3824         if (netif_running(dev)) {
3825                 writel(save_poll_interval, base + NvRegPollingInterval);
3826                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3827                 /* restore original irq */
3828                 if (nv_request_irq(dev, 0))
3829                         return 0;
3830         }
3831
3832         return ret;
3833 }
3834
3835 static int nv_loopback_test(struct net_device *dev)
3836 {
3837         struct fe_priv *np = netdev_priv(dev);
3838         u8 __iomem *base = get_hwbase(dev);
3839         struct sk_buff *tx_skb, *rx_skb;
3840         dma_addr_t test_dma_addr;
3841         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
3842         u32 flags;
3843         int len, i, pkt_len;
3844         u8 *pkt_data;
3845         u32 filter_flags = 0;
3846         u32 misc1_flags = 0;
3847         int ret = 1;
3848
3849         if (netif_running(dev)) {
3850                 nv_disable_irq(dev);
3851                 filter_flags = readl(base + NvRegPacketFilterFlags);
3852                 misc1_flags = readl(base + NvRegMisc1);
3853         } else {
3854                 nv_txrx_reset(dev);
3855         }
3856
3857         /* reinit driver view of the rx queue */
3858         set_bufsize(dev);
3859         nv_init_ring(dev);
3860
3861         /* setup hardware for loopback */
3862         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
3863         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
3864
3865         /* reinit nic view of the rx queue */
3866         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3867         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3868         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3869                 base + NvRegRingSizes);
3870         pci_push(base);
3871
3872         /* restart rx engine */
3873         nv_start_rx(dev);
3874         nv_start_tx(dev);
3875
3876         /* setup packet for tx */
3877         pkt_len = ETH_DATA_LEN;
3878         tx_skb = dev_alloc_skb(pkt_len);
3879         if (!tx_skb) {
3880                 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
3881                          " of %s\n", dev->name);
3882                 ret = 0;
3883                 goto out;
3884         }
3885         pkt_data = skb_put(tx_skb, pkt_len);
3886         for (i = 0; i < pkt_len; i++)
3887                 pkt_data[i] = (u8)(i & 0xff);
3888         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
3889                                        tx_skb->end-tx_skb->data, PCI_DMA_FROMDEVICE);
3890
3891         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3892                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
3893                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
3894         } else {
3895                 np->tx_ring.ex[0].bufhigh = cpu_to_le64(test_dma_addr) >> 32;
3896                 np->tx_ring.ex[0].buflow = cpu_to_le64(test_dma_addr) & 0x0FFFFFFFF;
3897                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
3898         }
3899         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3900         pci_push(get_hwbase(dev));
3901
3902         msleep(500);
3903
3904         /* check for rx of the packet */
3905         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3906                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
3907                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
3908
3909         } else {
3910                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
3911                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
3912         }
3913
3914         if (flags & NV_RX_AVAIL) {
3915                 ret = 0;
3916         } else if (np->desc_ver == DESC_VER_1) {
3917                 if (flags & NV_RX_ERROR)
3918                         ret = 0;
3919         } else {
3920                 if (flags & NV_RX2_ERROR) {
3921                         ret = 0;
3922                 }
3923         }
3924
3925         if (ret) {
3926                 if (len != pkt_len) {
3927                         ret = 0;
3928                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
3929                                 dev->name, len, pkt_len);
3930                 } else {
3931                         rx_skb = np->rx_skbuff[0];
3932                         for (i = 0; i < pkt_len; i++) {
3933                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
3934                                         ret = 0;
3935                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
3936                                                 dev->name, i);
3937                                         break;
3938                                 }
3939                         }
3940                 }
3941         } else {
3942                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
3943         }
3944
3945         pci_unmap_page(np->pci_dev, test_dma_addr,
3946                        tx_skb->end-tx_skb->data,
3947                        PCI_DMA_TODEVICE);
3948         dev_kfree_skb_any(tx_skb);
3949  out:
3950         /* stop engines */
3951         nv_stop_rx(dev);
3952         nv_stop_tx(dev);
3953         nv_txrx_reset(dev);
3954         /* drain rx queue */
3955         nv_drain_rx(dev);
3956         nv_drain_tx(dev);
3957
3958         if (netif_running(dev)) {
3959                 writel(misc1_flags, base + NvRegMisc1);
3960                 writel(filter_flags, base + NvRegPacketFilterFlags);
3961                 nv_enable_irq(dev);
3962         }
3963
3964         return ret;
3965 }
3966
3967 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
3968 {
3969         struct fe_priv *np = netdev_priv(dev);
3970         u8 __iomem *base = get_hwbase(dev);
3971         int result;
3972         memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64));
3973
3974         if (!nv_link_test(dev)) {
3975                 test->flags |= ETH_TEST_FL_FAILED;
3976                 buffer[0] = 1;
3977         }
3978
3979         if (test->flags & ETH_TEST_FL_OFFLINE) {
3980                 if (netif_running(dev)) {
3981                         netif_stop_queue(dev);
3982                         netif_poll_disable(dev);
3983                         netif_tx_lock_bh(dev);
3984                         spin_lock_irq(&np->lock);
3985                         nv_disable_hw_interrupts(dev, np->irqmask);
3986                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3987                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3988                         } else {
3989                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3990                         }
3991                         /* stop engines */
3992                         nv_stop_rx(dev);
3993                         nv_stop_tx(dev);
3994                         nv_txrx_reset(dev);
3995                         /* drain rx queue */
3996                         nv_drain_rx(dev);
3997                         nv_drain_tx(dev);
3998                         spin_unlock_irq(&np->lock);
3999                         netif_tx_unlock_bh(dev);
4000                 }
4001
4002                 if (!nv_register_test(dev)) {
4003                         test->flags |= ETH_TEST_FL_FAILED;
4004                         buffer[1] = 1;
4005                 }
4006
4007                 result = nv_interrupt_test(dev);
4008                 if (result != 1) {
4009                         test->flags |= ETH_TEST_FL_FAILED;
4010                         buffer[2] = 1;
4011                 }
4012                 if (result == 0) {
4013                         /* bail out */
4014                         return;
4015                 }
4016
4017                 if (!nv_loopback_test(dev)) {
4018                         test->flags |= ETH_TEST_FL_FAILED;
4019                         buffer[3] = 1;
4020                 }
4021
4022                 if (netif_running(dev)) {
4023                         /* reinit driver view of the rx queue */
4024                         set_bufsize(dev);
4025                         if (nv_init_ring(dev)) {
4026                                 if (!np->in_shutdown)
4027                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4028                         }
4029                         /* reinit nic view of the rx queue */
4030                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4031                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4032                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4033                                 base + NvRegRingSizes);
4034                         pci_push(base);
4035                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4036                         pci_push(base);
4037                         /* restart rx engine */
4038                         nv_start_rx(dev);
4039                         nv_start_tx(dev);
4040                         netif_start_queue(dev);
4041                         netif_poll_enable(dev);
4042                         nv_enable_hw_interrupts(dev, np->irqmask);
4043                 }
4044         }
4045 }
4046
4047 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4048 {
4049         switch (stringset) {
4050         case ETH_SS_STATS:
4051                 memcpy(buffer, &nv_estats_str, nv_get_stats_count(dev)*sizeof(struct nv_ethtool_str));
4052                 break;
4053         case ETH_SS_TEST:
4054                 memcpy(buffer, &nv_etests_str, nv_self_test_count(dev)*sizeof(struct nv_ethtool_str));
4055                 break;
4056         }
4057 }
4058
4059 static const struct ethtool_ops ops = {
4060         .get_drvinfo = nv_get_drvinfo,
4061         .get_link = ethtool_op_get_link,
4062         .get_wol = nv_get_wol,
4063         .set_wol = nv_set_wol,
4064         .get_settings = nv_get_settings,
4065         .set_settings = nv_set_settings,
4066         .get_regs_len = nv_get_regs_len,
4067         .get_regs = nv_get_regs,
4068         .nway_reset = nv_nway_reset,
4069         .get_perm_addr = ethtool_op_get_perm_addr,
4070         .get_tso = ethtool_op_get_tso,
4071         .set_tso = nv_set_tso,
4072         .get_ringparam = nv_get_ringparam,
4073         .set_ringparam = nv_set_ringparam,
4074         .get_pauseparam = nv_get_pauseparam,
4075         .set_pauseparam = nv_set_pauseparam,
4076         .get_rx_csum = nv_get_rx_csum,
4077         .set_rx_csum = nv_set_rx_csum,
4078         .get_tx_csum = ethtool_op_get_tx_csum,
4079         .set_tx_csum = nv_set_tx_csum,
4080         .get_sg = ethtool_op_get_sg,
4081         .set_sg = nv_set_sg,
4082         .get_strings = nv_get_strings,
4083         .get_stats_count = nv_get_stats_count,
4084         .get_ethtool_stats = nv_get_ethtool_stats,
4085         .self_test_count = nv_self_test_count,
4086         .self_test = nv_self_test,
4087 };
4088
4089 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
4090 {
4091         struct fe_priv *np = get_nvpriv(dev);
4092
4093         spin_lock_irq(&np->lock);
4094
4095         /* save vlan group */
4096         np->vlangrp = grp;
4097
4098         if (grp) {
4099                 /* enable vlan on MAC */
4100                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
4101         } else {
4102                 /* disable vlan on MAC */
4103                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4104                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4105         }
4106
4107         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4108
4109         spin_unlock_irq(&np->lock);
4110 };
4111
4112 static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
4113 {
4114         /* nothing to do */
4115 };
4116
4117 /* The mgmt unit and driver use a semaphore to access the phy during init */
4118 static int nv_mgmt_acquire_sema(struct net_device *dev)
4119 {
4120         u8 __iomem *base = get_hwbase(dev);
4121         int i;
4122         u32 tx_ctrl, mgmt_sema;
4123
4124         for (i = 0; i < 10; i++) {
4125                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
4126                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
4127                         break;
4128                 msleep(500);
4129         }
4130
4131         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
4132                 return 0;
4133
4134         for (i = 0; i < 2; i++) {
4135                 tx_ctrl = readl(base + NvRegTransmitterControl);
4136                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
4137                 writel(tx_ctrl, base + NvRegTransmitterControl);
4138
4139                 /* verify that semaphore was acquired */
4140                 tx_ctrl = readl(base + NvRegTransmitterControl);
4141                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
4142                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE))
4143                         return 1;
4144                 else
4145                         udelay(50);
4146         }
4147
4148         return 0;
4149 }
4150
4151 /* Indicate to mgmt unit whether driver is loaded or not */
4152 static void nv_mgmt_driver_loaded(struct net_device *dev, int loaded)
4153 {
4154         u8 __iomem *base = get_hwbase(dev);
4155         u32 tx_ctrl;
4156
4157         tx_ctrl = readl(base + NvRegTransmitterControl);
4158         if (loaded)
4159                 tx_ctrl |= NVREG_XMITCTL_HOST_LOADED;
4160         else
4161                 tx_ctrl &= ~NVREG_XMITCTL_HOST_LOADED;
4162         writel(tx_ctrl, base + NvRegTransmitterControl);
4163 }
4164
4165 static int nv_open(struct net_device *dev)
4166 {
4167         struct fe_priv *np = netdev_priv(dev);
4168         u8 __iomem *base = get_hwbase(dev);
4169         int ret = 1;
4170         int oom, i;
4171
4172         dprintk(KERN_DEBUG "nv_open: begin\n");
4173
4174         /* erase previous misconfiguration */
4175         if (np->driver_data & DEV_HAS_POWER_CNTRL)
4176                 nv_mac_reset(dev);
4177         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4178         writel(0, base + NvRegMulticastAddrB);
4179         writel(0, base + NvRegMulticastMaskA);
4180         writel(0, base + NvRegMulticastMaskB);
4181         writel(0, base + NvRegPacketFilterFlags);
4182
4183         writel(0, base + NvRegTransmitterControl);
4184         writel(0, base + NvRegReceiverControl);
4185
4186         writel(0, base + NvRegAdapterControl);
4187
4188         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
4189                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
4190
4191         /* initialize descriptor rings */
4192         set_bufsize(dev);
4193         oom = nv_init_ring(dev);
4194
4195         writel(0, base + NvRegLinkSpeed);
4196         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4197         nv_txrx_reset(dev);
4198         writel(0, base + NvRegUnknownSetupReg6);
4199
4200         np->in_shutdown = 0;
4201
4202         /* give hw rings */
4203         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4204         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4205                 base + NvRegRingSizes);
4206
4207         writel(np->linkspeed, base + NvRegLinkSpeed);
4208         if (np->desc_ver == DESC_VER_1)
4209                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
4210         else
4211                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
4212         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4213         writel(np->vlanctl_bits, base + NvRegVlanControl);
4214         pci_push(base);
4215         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
4216         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
4217                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
4218                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
4219
4220         writel(0, base + NvRegMIIMask);
4221         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4222         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4223
4224         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
4225         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
4226         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
4227         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4228
4229         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
4230         get_random_bytes(&i, sizeof(i));
4231         writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
4232         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
4233         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
4234         if (poll_interval == -1) {
4235                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
4236                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
4237                 else
4238                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4239         }
4240         else
4241                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
4242         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4243         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
4244                         base + NvRegAdapterControl);
4245         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
4246         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
4247         if (np->wolenabled)
4248                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
4249
4250         i = readl(base + NvRegPowerState);
4251         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
4252                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
4253
4254         pci_push(base);
4255         udelay(10);
4256         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
4257
4258         nv_disable_hw_interrupts(dev, np->irqmask);
4259         pci_push(base);
4260         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4261         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4262         pci_push(base);
4263
4264         if (nv_request_irq(dev, 0)) {
4265                 goto out_drain;
4266         }
4267
4268         /* ask for interrupts */
4269         nv_enable_hw_interrupts(dev, np->irqmask);
4270
4271         spin_lock_irq(&np->lock);
4272         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4273         writel(0, base + NvRegMulticastAddrB);
4274         writel(0, base + NvRegMulticastMaskA);
4275         writel(0, base + NvRegMulticastMaskB);
4276         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
4277         /* One manual link speed update: Interrupts are enabled, future link
4278          * speed changes cause interrupts and are handled by nv_link_irq().
4279          */
4280         {
4281                 u32 miistat;
4282                 miistat = readl(base + NvRegMIIStatus);
4283                 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
4284                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
4285         }
4286         /* set linkspeed to invalid value, thus force nv_update_linkspeed
4287          * to init hw */
4288         np->linkspeed = 0;
4289         ret = nv_update_linkspeed(dev);
4290         nv_start_rx(dev);
4291         nv_start_tx(dev);
4292         netif_start_queue(dev);
4293         netif_poll_enable(dev);
4294
4295         if (ret) {
4296                 netif_carrier_on(dev);
4297         } else {
4298                 printk("%s: no link during initialization.\n", dev->name);
4299                 netif_carrier_off(dev);
4300         }
4301         if (oom)
4302                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4303
4304         /* start statistics timer */
4305         if (np->driver_data & DEV_HAS_STATISTICS)
4306                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
4307
4308         spin_unlock_irq(&np->lock);
4309
4310         return 0;
4311 out_drain:
4312         drain_ring(dev);
4313         return ret;
4314 }
4315
4316 static int nv_close(struct net_device *dev)
4317 {
4318         struct fe_priv *np = netdev_priv(dev);
4319         u8 __iomem *base;
4320
4321         spin_lock_irq(&np->lock);
4322         np->in_shutdown = 1;
4323         spin_unlock_irq(&np->lock);
4324         netif_poll_disable(dev);
4325         synchronize_irq(dev->irq);
4326
4327         del_timer_sync(&np->oom_kick);
4328         del_timer_sync(&np->nic_poll);
4329         del_timer_sync(&np->stats_poll);
4330
4331         netif_stop_queue(dev);
4332         spin_lock_irq(&np->lock);
4333         nv_stop_tx(dev);
4334         nv_stop_rx(dev);
4335         nv_txrx_reset(dev);
4336
4337         /* disable interrupts on the nic or we will lock up */
4338         base = get_hwbase(dev);
4339         nv_disable_hw_interrupts(dev, np->irqmask);
4340         pci_push(base);
4341         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
4342
4343         spin_unlock_irq(&np->lock);
4344
4345         nv_free_irq(dev);
4346
4347         drain_ring(dev);
4348
4349         if (np->wolenabled)
4350                 nv_start_rx(dev);
4351
4352         /* FIXME: power down nic */
4353
4354         return 0;
4355 }
4356
4357 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
4358 {
4359         struct net_device *dev;
4360         struct fe_priv *np;
4361         unsigned long addr;
4362         u8 __iomem *base;
4363         int err, i;
4364         u32 powerstate, txreg;
4365         u32 phystate_orig = 0, phystate;
4366         int phyinitialized = 0;
4367
4368         dev = alloc_etherdev(sizeof(struct fe_priv));
4369         err = -ENOMEM;
4370         if (!dev)
4371                 goto out;
4372
4373         np = netdev_priv(dev);
4374         np->pci_dev = pci_dev;
4375         spin_lock_init(&np->lock);
4376         SET_MODULE_OWNER(dev);
4377         SET_NETDEV_DEV(dev, &pci_dev->dev);
4378
4379         init_timer(&np->oom_kick);
4380         np->oom_kick.data = (unsigned long) dev;
4381         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
4382         init_timer(&np->nic_poll);
4383         np->nic_poll.data = (unsigned long) dev;
4384         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
4385         init_timer(&np->stats_poll);
4386         np->stats_poll.data = (unsigned long) dev;
4387         np->stats_poll.function = &nv_do_stats_poll;    /* timer handler */
4388
4389         err = pci_enable_device(pci_dev);
4390         if (err) {
4391                 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
4392                                 err, pci_name(pci_dev));
4393                 goto out_free;
4394         }
4395
4396         pci_set_master(pci_dev);
4397
4398         err = pci_request_regions(pci_dev, DRV_NAME);
4399         if (err < 0)
4400                 goto out_disable;
4401
4402         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS))
4403                 np->register_size = NV_PCI_REGSZ_VER2;
4404         else
4405                 np->register_size = NV_PCI_REGSZ_VER1;
4406
4407         err = -EINVAL;
4408         addr = 0;
4409         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
4410                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
4411                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
4412                                 pci_resource_len(pci_dev, i),
4413                                 pci_resource_flags(pci_dev, i));
4414                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
4415                                 pci_resource_len(pci_dev, i) >= np->register_size) {
4416                         addr = pci_resource_start(pci_dev, i);
4417                         break;
4418                 }
4419         }
4420         if (i == DEVICE_COUNT_RESOURCE) {
4421                 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
4422                                         pci_name(pci_dev));
4423                 goto out_relreg;
4424         }
4425
4426         /* copy of driver data */
4427         np->driver_data = id->driver_data;
4428
4429         /* handle different descriptor versions */
4430         if (id->driver_data & DEV_HAS_HIGH_DMA) {
4431                 /* packet format 3: supports 40-bit addressing */
4432                 np->desc_ver = DESC_VER_3;
4433                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
4434                 if (dma_64bit) {
4435                         if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4436                                 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
4437                                        pci_name(pci_dev));
4438                         } else {
4439                                 dev->features |= NETIF_F_HIGHDMA;
4440                                 printk(KERN_INFO "forcedeth: using HIGHDMA\n");
4441                         }
4442                         if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4443                                 printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n",
4444                                        pci_name(pci_dev));
4445                         }
4446                 }
4447         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
4448                 /* packet format 2: supports jumbo frames */
4449                 np->desc_ver = DESC_VER_2;
4450                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
4451         } else {
4452                 /* original packet format */
4453                 np->desc_ver = DESC_VER_1;
4454                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
4455         }
4456
4457         np->pkt_limit = NV_PKTLIMIT_1;
4458         if (id->driver_data & DEV_HAS_LARGEDESC)
4459                 np->pkt_limit = NV_PKTLIMIT_2;
4460
4461         if (id->driver_data & DEV_HAS_CHECKSUM) {
4462                 np->rx_csum = 1;
4463                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4464                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
4465 #ifdef NETIF_F_TSO
4466                 dev->features |= NETIF_F_TSO;
4467 #endif
4468         }
4469
4470         np->vlanctl_bits = 0;
4471         if (id->driver_data & DEV_HAS_VLAN) {
4472                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
4473                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
4474                 dev->vlan_rx_register = nv_vlan_rx_register;
4475                 dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid;
4476         }
4477
4478         np->msi_flags = 0;
4479         if ((id->driver_data & DEV_HAS_MSI) && msi) {
4480                 np->msi_flags |= NV_MSI_CAPABLE;
4481         }
4482         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
4483                 np->msi_flags |= NV_MSI_X_CAPABLE;
4484         }
4485
4486         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
4487         if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {
4488                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
4489         }
4490
4491
4492         err = -ENOMEM;
4493         np->base = ioremap(addr, np->register_size);
4494         if (!np->base)
4495                 goto out_relreg;
4496         dev->base_addr = (unsigned long)np->base;
4497
4498         dev->irq = pci_dev->irq;
4499
4500         np->rx_ring_size = RX_RING_DEFAULT;
4501         np->tx_ring_size = TX_RING_DEFAULT;
4502         np->tx_limit_stop = np->tx_ring_size - TX_LIMIT_DIFFERENCE;
4503         np->tx_limit_start = np->tx_ring_size - TX_LIMIT_DIFFERENCE - 1;
4504
4505         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4506                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
4507                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
4508                                         &np->ring_addr);
4509                 if (!np->rx_ring.orig)
4510                         goto out_unmap;
4511                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4512         } else {
4513                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
4514                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
4515                                         &np->ring_addr);
4516                 if (!np->rx_ring.ex)
4517                         goto out_unmap;
4518                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4519         }
4520         np->rx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->rx_ring_size, GFP_KERNEL);
4521         np->rx_dma = kmalloc(sizeof(dma_addr_t) * np->rx_ring_size, GFP_KERNEL);
4522         np->tx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->tx_ring_size, GFP_KERNEL);
4523         np->tx_dma = kmalloc(sizeof(dma_addr_t) * np->tx_ring_size, GFP_KERNEL);
4524         np->tx_dma_len = kmalloc(sizeof(unsigned int) * np->tx_ring_size, GFP_KERNEL);
4525         if (!np->rx_skbuff || !np->rx_dma || !np->tx_skbuff || !np->tx_dma || !np->tx_dma_len)
4526                 goto out_freering;
4527         memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
4528         memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
4529         memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
4530         memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
4531         memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
4532
4533         dev->open = nv_open;
4534         dev->stop = nv_close;
4535         dev->hard_start_xmit = nv_start_xmit;
4536         dev->get_stats = nv_get_stats;
4537         dev->change_mtu = nv_change_mtu;
4538         dev->set_mac_address = nv_set_mac_address;
4539         dev->set_multicast_list = nv_set_multicast;
4540 #ifdef CONFIG_NET_POLL_CONTROLLER
4541         dev->poll_controller = nv_poll_controller;
4542 #endif
4543         dev->weight = 64;
4544 #ifdef CONFIG_FORCEDETH_NAPI
4545         dev->poll = nv_napi_poll;
4546 #endif
4547         SET_ETHTOOL_OPS(dev, &ops);
4548         dev->tx_timeout = nv_tx_timeout;
4549         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
4550
4551         pci_set_drvdata(pci_dev, dev);
4552
4553         /* read the mac address */
4554         base = get_hwbase(dev);
4555         np->orig_mac[0] = readl(base + NvRegMacAddrA);
4556         np->orig_mac[1] = readl(base + NvRegMacAddrB);
4557
4558         /* check the workaround bit for correct mac address order */
4559         txreg = readl(base + NvRegTransmitPoll);
4560         if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
4561                 /* mac address is already in correct order */
4562                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
4563                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
4564                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
4565                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
4566                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
4567                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
4568         } else {
4569                 /* need to reverse mac address to correct order */
4570                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
4571                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
4572                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
4573                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
4574                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
4575                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
4576                 /* set permanent address to be correct aswell */
4577                 np->orig_mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
4578                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
4579                 np->orig_mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
4580                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4581         }
4582         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4583
4584         if (!is_valid_ether_addr(dev->perm_addr)) {
4585                 /*
4586                  * Bad mac address. At least one bios sets the mac address
4587                  * to 01:23:45:67:89:ab
4588                  */
4589                 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
4590                         pci_name(pci_dev),
4591                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4592                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4593                 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
4594                 dev->dev_addr[0] = 0x00;
4595                 dev->dev_addr[1] = 0x00;
4596                 dev->dev_addr[2] = 0x6c;
4597                 get_random_bytes(&dev->dev_addr[3], 3);
4598         }
4599
4600         dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
4601                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4602                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4603
4604         /* set mac address */
4605         nv_copy_mac_to_hw(dev);
4606
4607         /* disable WOL */
4608         writel(0, base + NvRegWakeUpFlags);
4609         np->wolenabled = 0;
4610
4611         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
4612                 u8 revision_id;
4613                 pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id);
4614
4615                 /* take phy and nic out of low power mode */
4616                 powerstate = readl(base + NvRegPowerState2);
4617                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
4618                 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
4619                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
4620                     revision_id >= 0xA3)
4621                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
4622                 writel(powerstate, base + NvRegPowerState2);
4623         }
4624
4625         if (np->desc_ver == DESC_VER_1) {
4626                 np->tx_flags = NV_TX_VALID;
4627         } else {
4628                 np->tx_flags = NV_TX2_VALID;
4629         }
4630         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
4631                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
4632                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
4633                         np->msi_flags |= 0x0003;
4634         } else {
4635                 np->irqmask = NVREG_IRQMASK_CPU;
4636                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
4637                         np->msi_flags |= 0x0001;
4638         }
4639
4640         if (id->driver_data & DEV_NEED_TIMERIRQ)
4641                 np->irqmask |= NVREG_IRQ_TIMER;
4642         if (id->driver_data & DEV_NEED_LINKTIMER) {
4643                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
4644                 np->need_linktimer = 1;
4645                 np->link_timeout = jiffies + LINK_TIMEOUT;
4646         } else {
4647                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
4648                 np->need_linktimer = 0;
4649         }
4650
4651         /* clear phy state and temporarily halt phy interrupts */
4652         writel(0, base + NvRegMIIMask);
4653         phystate = readl(base + NvRegAdapterControl);
4654         if (phystate & NVREG_ADAPTCTL_RUNNING) {
4655                 phystate_orig = 1;
4656                 phystate &= ~NVREG_ADAPTCTL_RUNNING;
4657                 writel(phystate, base + NvRegAdapterControl);
4658         }
4659         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
4660
4661         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
4662                 writel(0x1, base + 0x204); pci_push(base);
4663                 msleep(500);
4664                 /* management unit running on the mac? */
4665                 np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST;
4666                 if (np->mac_in_use) {
4667                         u32 mgmt_sync;
4668                         /* management unit setup the phy already? */
4669                         mgmt_sync = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK;
4670                         if (mgmt_sync == NVREG_XMITCTL_SYNC_NOT_READY) {
4671                                 if (!nv_mgmt_acquire_sema(dev)) {
4672                                         for (i = 0; i < 5000; i++) {
4673                                                 msleep(1);
4674                                                 mgmt_sync = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK;
4675                                                 if (mgmt_sync == NVREG_XMITCTL_SYNC_NOT_READY)
4676                                                         continue;
4677                                                 if (mgmt_sync == NVREG_XMITCTL_SYNC_PHY_INIT)
4678                                                         phyinitialized = 1;
4679                                                 break;
4680                                         }
4681                                 } else {
4682                                         /* we need to init the phy */
4683                                 }
4684                         } else if (mgmt_sync == NVREG_XMITCTL_SYNC_PHY_INIT) {
4685                                 /* phy is inited by SMU */
4686                                 phyinitialized = 1;
4687                         } else {
4688                                 /* we need to init the phy */
4689                         }
4690                 }
4691         }
4692
4693         /* find a suitable phy */
4694         for (i = 1; i <= 32; i++) {
4695                 int id1, id2;
4696                 int phyaddr = i & 0x1F;
4697
4698                 spin_lock_irq(&np->lock);
4699                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
4700                 spin_unlock_irq(&np->lock);
4701                 if (id1 < 0 || id1 == 0xffff)
4702                         continue;
4703                 spin_lock_irq(&np->lock);
4704                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
4705                 spin_unlock_irq(&np->lock);
4706                 if (id2 < 0 || id2 == 0xffff)
4707                         continue;
4708
4709                 np->phy_model = id2 & PHYID2_MODEL_MASK;
4710                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
4711                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
4712                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
4713                         pci_name(pci_dev), id1, id2, phyaddr);
4714                 np->phyaddr = phyaddr;
4715                 np->phy_oui = id1 | id2;
4716                 break;
4717         }
4718         if (i == 33) {
4719                 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
4720                        pci_name(pci_dev));
4721                 goto out_error;
4722         }
4723
4724         if (!phyinitialized) {
4725                 /* reset it */
4726                 phy_init(dev);
4727         }
4728
4729         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
4730                 nv_mgmt_driver_loaded(dev, 1);
4731         }
4732
4733         /* set default link speed settings */
4734         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
4735         np->duplex = 0;
4736         np->autoneg = 1;
4737
4738         err = register_netdev(dev);
4739         if (err) {
4740                 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
4741                 goto out_error;
4742         }
4743         printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
4744                         dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
4745                         pci_name(pci_dev));
4746
4747         return 0;
4748
4749 out_error:
4750         if (phystate_orig)
4751                 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
4752         if (np->mac_in_use)
4753                 nv_mgmt_driver_loaded(dev, 0);
4754         pci_set_drvdata(pci_dev, NULL);
4755 out_freering:
4756         free_rings(dev);
4757 out_unmap:
4758         iounmap(get_hwbase(dev));
4759 out_relreg:
4760         pci_release_regions(pci_dev);
4761 out_disable:
4762         pci_disable_device(pci_dev);
4763 out_free:
4764         free_netdev(dev);
4765 out:
4766         return err;
4767 }
4768
4769 static void __devexit nv_remove(struct pci_dev *pci_dev)
4770 {
4771         struct net_device *dev = pci_get_drvdata(pci_dev);
4772         struct fe_priv *np = netdev_priv(dev);
4773         u8 __iomem *base = get_hwbase(dev);
4774
4775         unregister_netdev(dev);
4776
4777         /* special op: write back the misordered MAC address - otherwise
4778          * the next nv_probe would see a wrong address.
4779          */
4780         writel(np->orig_mac[0], base + NvRegMacAddrA);
4781         writel(np->orig_mac[1], base + NvRegMacAddrB);
4782
4783         if (np->mac_in_use)
4784                 nv_mgmt_driver_loaded(dev, 0);
4785
4786         /* free all structures */
4787         free_rings(dev);
4788         iounmap(get_hwbase(dev));
4789         pci_release_regions(pci_dev);
4790         pci_disable_device(pci_dev);
4791         free_netdev(dev);
4792         pci_set_drvdata(pci_dev, NULL);
4793 }
4794
4795 #ifdef CONFIG_PM
4796 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
4797 {
4798         struct net_device *dev = pci_get_drvdata(pdev);
4799         struct fe_priv *np = netdev_priv(dev);
4800
4801         if (!netif_running(dev))
4802                 goto out;
4803
4804         netif_device_detach(dev);
4805
4806         // Gross.
4807         nv_close(dev);
4808
4809         pci_save_state(pdev);
4810         pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
4811         pci_set_power_state(pdev, pci_choose_state(pdev, state));
4812 out:
4813         return 0;
4814 }
4815
4816 static int nv_resume(struct pci_dev *pdev)
4817 {
4818         struct net_device *dev = pci_get_drvdata(pdev);
4819         int rc = 0;
4820
4821         if (!netif_running(dev))
4822                 goto out;
4823
4824         netif_device_attach(dev);
4825
4826         pci_set_power_state(pdev, PCI_D0);
4827         pci_restore_state(pdev);
4828         pci_enable_wake(pdev, PCI_D0, 0);
4829
4830         rc = nv_open(dev);
4831 out:
4832         return rc;
4833 }
4834 #else
4835 #define nv_suspend NULL
4836 #define nv_resume NULL
4837 #endif /* CONFIG_PM */
4838
4839 static struct pci_device_id pci_tbl[] = {
4840         {       /* nForce Ethernet Controller */
4841                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
4842                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4843         },
4844         {       /* nForce2 Ethernet Controller */
4845                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
4846                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4847         },
4848         {       /* nForce3 Ethernet Controller */
4849                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
4850                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4851         },
4852         {       /* nForce3 Ethernet Controller */
4853                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
4854                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4855         },
4856         {       /* nForce3 Ethernet Controller */
4857                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
4858                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4859         },
4860         {       /* nForce3 Ethernet Controller */
4861                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
4862                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4863         },
4864         {       /* nForce3 Ethernet Controller */
4865                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
4866                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4867         },
4868         {       /* CK804 Ethernet Controller */
4869                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
4870                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4871         },
4872         {       /* CK804 Ethernet Controller */
4873                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
4874                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4875         },
4876         {       /* MCP04 Ethernet Controller */
4877                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
4878                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4879         },
4880         {       /* MCP04 Ethernet Controller */
4881                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
4882                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4883         },
4884         {       /* MCP51 Ethernet Controller */
4885                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
4886                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4887         },
4888         {       /* MCP51 Ethernet Controller */
4889                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
4890                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4891         },
4892         {       /* MCP55 Ethernet Controller */
4893                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
4894                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4895         },
4896         {       /* MCP55 Ethernet Controller */
4897                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
4898                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4899         },
4900         {       /* MCP61 Ethernet Controller */
4901                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
4902                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4903         },
4904         {       /* MCP61 Ethernet Controller */
4905                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
4906                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4907         },
4908         {       /* MCP61 Ethernet Controller */
4909                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
4910                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4911         },
4912         {       /* MCP61 Ethernet Controller */
4913                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
4914                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4915         },
4916         {       /* MCP65 Ethernet Controller */
4917                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
4918                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4919         },
4920         {       /* MCP65 Ethernet Controller */
4921                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
4922                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4923         },
4924         {       /* MCP65 Ethernet Controller */
4925                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
4926                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4927         },
4928         {       /* MCP65 Ethernet Controller */
4929                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
4930                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4931         },
4932         {       /* MCP67 Ethernet Controller */
4933                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
4934                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4935         },
4936         {       /* MCP67 Ethernet Controller */
4937                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
4938                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4939         },
4940         {       /* MCP67 Ethernet Controller */
4941                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
4942                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4943         },
4944         {       /* MCP67 Ethernet Controller */
4945                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
4946                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4947         },
4948         {0,},
4949 };
4950
4951 static struct pci_driver driver = {
4952         .name = "forcedeth",
4953         .id_table = pci_tbl,
4954         .probe = nv_probe,
4955         .remove = __devexit_p(nv_remove),
4956         .suspend = nv_suspend,
4957         .resume = nv_resume,
4958 };
4959
4960 static int __init init_nic(void)
4961 {
4962         printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
4963         return pci_register_driver(&driver);
4964 }
4965
4966 static void __exit exit_nic(void)
4967 {
4968         pci_unregister_driver(&driver);
4969 }
4970
4971 module_param(max_interrupt_work, int, 0);
4972 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
4973 module_param(optimization_mode, int, 0);
4974 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
4975 module_param(poll_interval, int, 0);
4976 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
4977 module_param(msi, int, 0);
4978 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
4979 module_param(msix, int, 0);
4980 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
4981 module_param(dma_64bit, int, 0);
4982 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
4983
4984 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
4985 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
4986 MODULE_LICENSE("GPL");
4987
4988 MODULE_DEVICE_TABLE(pci, pci_tbl);
4989
4990 module_init(init_nic);
4991 module_exit(exit_nic);