drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey. It's neither supported nor endorsed
   7  *      by NVIDIA Corp. Use at your own risk.
   8  *
   9  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
  10  * trademarks of NVIDIA Corporation in the United States and other
  11  * countries.
  12  *
  13  * Copyright (C) 2003,4,5 Manfred Spraul
  14  * Copyright (C) 2004 Andrew de Quincey (wol support)
  15  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  16  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  17  * Copyright (c) 2004 NVIDIA Corporation
  18  *
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License as published by
  21  * the Free Software Foundation; either version 2 of the License, or
  22  * (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  32  *
  33  * Changelog:
  34  *      0.01: 05 Oct 2003: First release that compiles without warnings.
  35  *      0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
  36  *                         Check all PCI BARs for the register window.
  37  *                         udelay added to mii_rw.
  38  *      0.03: 06 Oct 2003: Initialize dev->irq.
  39  *      0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
  40  *      0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
  41  *      0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
  42  *                         irq mask updated
  43  *      0.07: 14 Oct 2003: Further irq mask updates.
  44  *      0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
  45  *                         added into irq handler, NULL check for drain_ring.
  46  *      0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
  47  *                         requested interrupt sources.
  48  *      0.10: 20 Oct 2003: First cleanup for release.
  49  *      0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
  50  *                         MAC Address init fix, set_multicast cleanup.
  51  *      0.12: 23 Oct 2003: Cleanups for release.
  52  *      0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
  53  *                         Set link speed correctly. start rx before starting
  54  *                         tx (nv_start_rx sets the link speed).
  55  *      0.14: 25 Oct 2003: Nic dependant irq mask.
  56  *      0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
  57  *                         open.
  58  *      0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
  59  *                         increased to 1628 bytes.
  60  *      0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
  61  *                         the tx length.
  62  *      0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
  63  *      0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
  64  *                         addresses, really stop rx if already running
  65  *                         in nv_start_rx, clean up a bit.
  66  *      0.20: 07 Dec 2003: alloc fixes
  67  *      0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
  68  *      0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
  69  *                         on close.
  70  *      0.23: 26 Jan 2004: various small cleanups
  71  *      0.24: 27 Feb 2004: make driver even less anonymous in backtraces
  72  *      0.25: 09 Mar 2004: wol support
  73  *      0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
  74  *      0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
  75  *                         added CK804/MCP04 device IDs, code fixes
  76  *                         for registers, link status and other minor fixes.
  77  *      0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
  78  *      0.29: 31 Aug 2004: Add backup timer for link change notification.
  79  *      0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
  80  *                         into nv_close, otherwise reenabling for wol can
  81  *                         cause DMA to kfree'd memory.
  82  *      0.31: 14 Nov 2004: ethtool support for getting/setting link
  83  *                         capabilities.
  84  *      0.32: 16 Apr 2005: RX_ERROR4 handling added.
  85  *      0.33: 16 May 2005: Support for MCP51 added.
  86  *      0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
  87  *      0.35: 26 Jun 2005: Support for MCP55 added.
  88  *      0.36: 28 Jun 2005: Add jumbo frame support.
  89  *      0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
  90  *      0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
  91  *                         per-packet flags.
  92  *      0.39: 18 Jul 2005: Add 64bit descriptor support.
  93  *      0.40: 19 Jul 2005: Add support for mac address change.
  94  *      0.41: 30 Jul 2005: Write back original MAC in nv_close instead
  95  *                         of nv_remove
  96  *      0.42: 06 Aug 2005: Fix lack of link speed initialization
  97  *                         in the second (and later) nv_open call
  98  *      0.43: 10 Aug 2005: Add support for tx checksum.
  99  *      0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
 100  *      0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
 101  *      0.46: 20 Oct 2005: Add irq optimization modes.
 102  *      0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
 103  *      0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
 104  *      0.49: 10 Dec 2005: Fix tso for large buffers.
 105  *      0.50: 20 Jan 2006: Add 8021pq tagging support.
 106  *      0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
 107  *      0.52: 20 Jan 2006: Add MSI/MSIX support.
 108  *      0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
 109  *      0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
 110  *      0.55: 22 Mar 2006: Add flow control (pause frame).
 111  *
 112  * Known bugs:
 113  * We suspect that on some hardware no TX done interrupts are generated.
 114  * This means recovery from netif_stop_queue only happens if the hw timer
 115  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
 116  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
 117  * If your hardware reliably generates tx done interrupts, then you can remove
 118  * DEV_NEED_TIMERIRQ from the driver_data flags.
 119  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
 120  * superfluous timer interrupts from the nic.
 121  */
 122 #define FORCEDETH_VERSION               "0.55"
 123 #define DRV_NAME                        "forcedeth"
 124
 125 #include <linux/module.h>
 126 #include <linux/types.h>
 127 #include <linux/pci.h>
 128 #include <linux/interrupt.h>
 129 #include <linux/netdevice.h>
 130 #include <linux/etherdevice.h>
 131 #include <linux/delay.h>
 132 #include <linux/spinlock.h>
 133 #include <linux/ethtool.h>
 134 #include <linux/timer.h>
 135 #include <linux/skbuff.h>
 136 #include <linux/mii.h>
 137 #include <linux/random.h>
 138 #include <linux/init.h>
 139 #include <linux/if_vlan.h>
 140 #include <linux/dma-mapping.h>
 141
 142 #include <asm/irq.h>
 143 #include <asm/io.h>
 144 #include <asm/uaccess.h>
 145 #include <asm/system.h>
 146
 147 #if 0
 148 #define dprintk                 printk
 149 #else
 150 #define dprintk(x...)           do { } while (0)
 151 #endif
 152
 153
 154 /*
 155  * Hardware access:
 156  */
 157
 158 #define DEV_NEED_TIMERIRQ       0x0001  /* set the timer irq flag in the irq mask */
 159 #define DEV_NEED_LINKTIMER      0x0002  /* poll link settings. Relies on the timer irq */
 160 #define DEV_HAS_LARGEDESC       0x0004  /* device supports jumbo frames and needs packet format 2 */
 161 #define DEV_HAS_HIGH_DMA        0x0008  /* device supports 64bit dma */
 162 #define DEV_HAS_CHECKSUM        0x0010  /* device supports tx and rx checksum offloads */
 163 #define DEV_HAS_VLAN            0x0020  /* device supports vlan tagging and striping */
 164 #define DEV_HAS_MSI             0x0040  /* device supports MSI */
 165 #define DEV_HAS_MSI_X           0x0080  /* device supports MSI-X */
 166 #define DEV_HAS_POWER_CNTRL     0x0100  /* device supports power savings */
 167 #define DEV_HAS_PAUSEFRAME_TX   0x0200  /* device supports tx pause frames */
 168 #define DEV_HAS_STATISTICS      0x0400  /* device supports hw statistics */
 169 #define DEV_HAS_TEST_EXTENDED   0x0800  /* device supports extended diagnostic test */
 170
 171 enum {
 172         NvRegIrqStatus = 0x000,
 173 #define NVREG_IRQSTAT_MIIEVENT  0x040
 174 #define NVREG_IRQSTAT_MASK              0x1ff
 175         NvRegIrqMask = 0x004,
 176 #define NVREG_IRQ_RX_ERROR              0x0001
 177 #define NVREG_IRQ_RX                    0x0002
 178 #define NVREG_IRQ_RX_NOBUF              0x0004
 179 #define NVREG_IRQ_TX_ERR                0x0008
 180 #define NVREG_IRQ_TX_OK                 0x0010
 181 #define NVREG_IRQ_TIMER                 0x0020
 182 #define NVREG_IRQ_LINK                  0x0040
 183 #define NVREG_IRQ_RX_FORCED             0x0080
 184 #define NVREG_IRQ_TX_FORCED             0x0100
 185 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 186 #define NVREG_IRQMASK_CPU               0x0040
 187 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 188 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 189 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK)
 190
 191 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
 192                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
 193                                         NVREG_IRQ_TX_FORCED))
 194
 195         NvRegUnknownSetupReg6 = 0x008,
 196 #define NVREG_UNKSETUP6_VAL             3
 197
 198 /*
 199  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 200  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 201  */
 202         NvRegPollingInterval = 0x00c,
 203 #define NVREG_POLL_DEFAULT_THROUGHPUT   970
 204 #define NVREG_POLL_DEFAULT_CPU  13
 205         NvRegMSIMap0 = 0x020,
 206         NvRegMSIMap1 = 0x024,
 207         NvRegMSIIrqMask = 0x030,
 208 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 209         NvRegMisc1 = 0x080,
 210 #define NVREG_MISC1_PAUSE_TX    0x01
 211 #define NVREG_MISC1_HD          0x02
 212 #define NVREG_MISC1_FORCE       0x3b0f3c
 213
 214         NvRegMacReset = 0x3c,
 215 #define NVREG_MAC_RESET_ASSERT  0x0F3
 216         NvRegTransmitterControl = 0x084,
 217 #define NVREG_XMITCTL_START     0x01
 218         NvRegTransmitterStatus = 0x088,
 219 #define NVREG_XMITSTAT_BUSY     0x01
 220
 221         NvRegPacketFilterFlags = 0x8c,
 222 #define NVREG_PFF_PAUSE_RX      0x08
 223 #define NVREG_PFF_ALWAYS        0x7F0000
 224 #define NVREG_PFF_PROMISC       0x80
 225 #define NVREG_PFF_MYADDR        0x20
 226 #define NVREG_PFF_LOOPBACK      0x10
 227
 228         NvRegOffloadConfig = 0x90,
 229 #define NVREG_OFFLOAD_HOMEPHY   0x601
 230 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 231         NvRegReceiverControl = 0x094,
 232 #define NVREG_RCVCTL_START      0x01
 233         NvRegReceiverStatus = 0x98,
 234 #define NVREG_RCVSTAT_BUSY      0x01
 235
 236         NvRegRandomSeed = 0x9c,
 237 #define NVREG_RNDSEED_MASK      0x00ff
 238 #define NVREG_RNDSEED_FORCE     0x7f00
 239 #define NVREG_RNDSEED_FORCE2    0x2d00
 240 #define NVREG_RNDSEED_FORCE3    0x7400
 241
 242         NvRegUnknownSetupReg1 = 0xA0,
 243 #define NVREG_UNKSETUP1_VAL     0x16070f
 244         NvRegUnknownSetupReg2 = 0xA4,
 245 #define NVREG_UNKSETUP2_VAL     0x16
 246         NvRegMacAddrA = 0xA8,
 247         NvRegMacAddrB = 0xAC,
 248         NvRegMulticastAddrA = 0xB0,
 249 #define NVREG_MCASTADDRA_FORCE  0x01
 250         NvRegMulticastAddrB = 0xB4,
 251         NvRegMulticastMaskA = 0xB8,
 252         NvRegMulticastMaskB = 0xBC,
 253
 254         NvRegPhyInterface = 0xC0,
 255 #define PHY_RGMII               0x10000000
 256
 257         NvRegTxRingPhysAddr = 0x100,
 258         NvRegRxRingPhysAddr = 0x104,
 259         NvRegRingSizes = 0x108,
 260 #define NVREG_RINGSZ_TXSHIFT 0
 261 #define NVREG_RINGSZ_RXSHIFT 16
 262         NvRegUnknownTransmitterReg = 0x10c,
 263         NvRegLinkSpeed = 0x110,
 264 #define NVREG_LINKSPEED_FORCE 0x10000
 265 #define NVREG_LINKSPEED_10      1000
 266 #define NVREG_LINKSPEED_100     100
 267 #define NVREG_LINKSPEED_1000    50
 268 #define NVREG_LINKSPEED_MASK    (0xFFF)
 269         NvRegUnknownSetupReg5 = 0x130,
 270 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 271         NvRegUnknownSetupReg3 = 0x13c,
 272 #define NVREG_UNKSETUP3_VAL1    0x200010
 273         NvRegTxRxControl = 0x144,
 274 #define NVREG_TXRXCTL_KICK      0x0001
 275 #define NVREG_TXRXCTL_BIT1      0x0002
 276 #define NVREG_TXRXCTL_BIT2      0x0004
 277 #define NVREG_TXRXCTL_IDLE      0x0008
 278 #define NVREG_TXRXCTL_RESET     0x0010
 279 #define NVREG_TXRXCTL_RXCHECK   0x0400
 280 #define NVREG_TXRXCTL_DESC_1    0
 281 #define NVREG_TXRXCTL_DESC_2    0x02100
 282 #define NVREG_TXRXCTL_DESC_3    0x02200
 283 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 284 #define NVREG_TXRXCTL_VLANINS   0x00080
 285         NvRegTxRingPhysAddrHigh = 0x148,
 286         NvRegRxRingPhysAddrHigh = 0x14C,
 287         NvRegTxPauseFrame = 0x170,
 288 #define NVREG_TX_PAUSEFRAME_DISABLE     0x1ff0080
 289 #define NVREG_TX_PAUSEFRAME_ENABLE      0x0c00030
 290         NvRegMIIStatus = 0x180,
 291 #define NVREG_MIISTAT_ERROR             0x0001
 292 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 293 #define NVREG_MIISTAT_MASK              0x000f
 294 #define NVREG_MIISTAT_MASK2             0x000f
 295         NvRegUnknownSetupReg4 = 0x184,
 296 #define NVREG_UNKSETUP4_VAL     8
 297
 298         NvRegAdapterControl = 0x188,
 299 #define NVREG_ADAPTCTL_START    0x02
 300 #define NVREG_ADAPTCTL_LINKUP   0x04
 301 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 302 #define NVREG_ADAPTCTL_RUNNING  0x100000
 303 #define NVREG_ADAPTCTL_PHYSHIFT 24
 304         NvRegMIISpeed = 0x18c,
 305 #define NVREG_MIISPEED_BIT8     (1<<8)
 306 #define NVREG_MIIDELAY  5
 307         NvRegMIIControl = 0x190,
 308 #define NVREG_MIICTL_INUSE      0x08000
 309 #define NVREG_MIICTL_WRITE      0x00400
 310 #define NVREG_MIICTL_ADDRSHIFT  5
 311         NvRegMIIData = 0x194,
 312         NvRegWakeUpFlags = 0x200,
 313 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 314 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 315 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 316 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 317 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 318 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 319 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 320 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 321 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 322 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 323 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 324
 325         NvRegPatternCRC = 0x204,
 326         NvRegPatternMask = 0x208,
 327         NvRegPowerCap = 0x268,
 328 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 329 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 330 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 331         NvRegPowerState = 0x26c,
 332 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 333 #define NVREG_POWERSTATE_VALID          0x0100
 334 #define NVREG_POWERSTATE_MASK           0x0003
 335 #define NVREG_POWERSTATE_D0             0x0000
 336 #define NVREG_POWERSTATE_D1             0x0001
 337 #define NVREG_POWERSTATE_D2             0x0002
 338 #define NVREG_POWERSTATE_D3             0x0003
 339         NvRegTxCnt = 0x280,
 340         NvRegTxZeroReXmt = 0x284,
 341         NvRegTxOneReXmt = 0x288,
 342         NvRegTxManyReXmt = 0x28c,
 343         NvRegTxLateCol = 0x290,
 344         NvRegTxUnderflow = 0x294,
 345         NvRegTxLossCarrier = 0x298,
 346         NvRegTxExcessDef = 0x29c,
 347         NvRegTxRetryErr = 0x2a0,
 348         NvRegRxFrameErr = 0x2a4,
 349         NvRegRxExtraByte = 0x2a8,
 350         NvRegRxLateCol = 0x2ac,
 351         NvRegRxRunt = 0x2b0,
 352         NvRegRxFrameTooLong = 0x2b4,
 353         NvRegRxOverflow = 0x2b8,
 354         NvRegRxFCSErr = 0x2bc,
 355         NvRegRxFrameAlignErr = 0x2c0,
 356         NvRegRxLenErr = 0x2c4,
 357         NvRegRxUnicast = 0x2c8,
 358         NvRegRxMulticast = 0x2cc,
 359         NvRegRxBroadcast = 0x2d0,
 360         NvRegTxDef = 0x2d4,
 361         NvRegTxFrame = 0x2d8,
 362         NvRegRxCnt = 0x2dc,
 363         NvRegTxPause = 0x2e0,
 364         NvRegRxPause = 0x2e4,
 365         NvRegRxDropFrame = 0x2e8,
 366         NvRegVlanControl = 0x300,
 367 #define NVREG_VLANCONTROL_ENABLE        0x2000
 368         NvRegMSIXMap0 = 0x3e0,
 369         NvRegMSIXMap1 = 0x3e4,
 370         NvRegMSIXIrqStatus = 0x3f0,
 371
 372         NvRegPowerState2 = 0x600,
 373 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F11
 374 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 375 };
 376
 377 /* Big endian: should work, but is untested */
 378 struct ring_desc {
 379         u32 PacketBuffer;
 380         u32 FlagLen;
 381 };
 382
 383 struct ring_desc_ex {
 384         u32 PacketBufferHigh;
 385         u32 PacketBufferLow;
 386         u32 TxVlan;
 387         u32 FlagLen;
 388 };
 389
 390 typedef union _ring_type {
 391         struct ring_desc* orig;
 392         struct ring_desc_ex* ex;
 393 } ring_type;
 394
 395 #define FLAG_MASK_V1 0xffff0000
 396 #define FLAG_MASK_V2 0xffffc000
 397 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 398 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 399
 400 #define NV_TX_LASTPACKET        (1<<16)
 401 #define NV_TX_RETRYERROR        (1<<19)
 402 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 403 #define NV_TX_DEFERRED          (1<<26)
 404 #define NV_TX_CARRIERLOST       (1<<27)
 405 #define NV_TX_LATECOLLISION     (1<<28)
 406 #define NV_TX_UNDERFLOW         (1<<29)
 407 #define NV_TX_ERROR             (1<<30)
 408 #define NV_TX_VALID             (1<<31)
 409
 410 #define NV_TX2_LASTPACKET       (1<<29)
 411 #define NV_TX2_RETRYERROR       (1<<18)
 412 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 413 #define NV_TX2_DEFERRED         (1<<25)
 414 #define NV_TX2_CARRIERLOST      (1<<26)
 415 #define NV_TX2_LATECOLLISION    (1<<27)
 416 #define NV_TX2_UNDERFLOW        (1<<28)
 417 /* error and valid are the same for both */
 418 #define NV_TX2_ERROR            (1<<30)
 419 #define NV_TX2_VALID            (1<<31)
 420 #define NV_TX2_TSO              (1<<28)
 421 #define NV_TX2_TSO_SHIFT        14
 422 #define NV_TX2_TSO_MAX_SHIFT    14
 423 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 424 #define NV_TX2_CHECKSUM_L3      (1<<27)
 425 #define NV_TX2_CHECKSUM_L4      (1<<26)
 426
 427 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 428
 429 #define NV_RX_DESCRIPTORVALID   (1<<16)
 430 #define NV_RX_MISSEDFRAME       (1<<17)
 431 #define NV_RX_SUBSTRACT1        (1<<18)
 432 #define NV_RX_ERROR1            (1<<23)
 433 #define NV_RX_ERROR2            (1<<24)
 434 #define NV_RX_ERROR3            (1<<25)
 435 #define NV_RX_ERROR4            (1<<26)
 436 #define NV_RX_CRCERR            (1<<27)
 437 #define NV_RX_OVERFLOW          (1<<28)
 438 #define NV_RX_FRAMINGERR        (1<<29)
 439 #define NV_RX_ERROR             (1<<30)
 440 #define NV_RX_AVAIL             (1<<31)
 441
 442 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 443 #define NV_RX2_CHECKSUMOK1      (0x10000000)
 444 #define NV_RX2_CHECKSUMOK2      (0x14000000)
 445 #define NV_RX2_CHECKSUMOK3      (0x18000000)
 446 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 447 #define NV_RX2_SUBSTRACT1       (1<<25)
 448 #define NV_RX2_ERROR1           (1<<18)
 449 #define NV_RX2_ERROR2           (1<<19)
 450 #define NV_RX2_ERROR3           (1<<20)
 451 #define NV_RX2_ERROR4           (1<<21)
 452 #define NV_RX2_CRCERR           (1<<22)
 453 #define NV_RX2_OVERFLOW         (1<<23)
 454 #define NV_RX2_FRAMINGERR       (1<<24)
 455 /* error and avail are the same for both */
 456 #define NV_RX2_ERROR            (1<<30)
 457 #define NV_RX2_AVAIL            (1<<31)
 458
 459 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 460 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 461
 462 /* Miscelaneous hardware related defines: */
 463 #define NV_PCI_REGSZ_VER1       0x270
 464 #define NV_PCI_REGSZ_VER2       0x604
 465
 466 /* various timeout delays: all in usec */
 467 #define NV_TXRX_RESET_DELAY     4
 468 #define NV_TXSTOP_DELAY1        10
 469 #define NV_TXSTOP_DELAY1MAX     500000
 470 #define NV_TXSTOP_DELAY2        100
 471 #define NV_RXSTOP_DELAY1        10
 472 #define NV_RXSTOP_DELAY1MAX     500000
 473 #define NV_RXSTOP_DELAY2        100
 474 #define NV_SETUP5_DELAY         5
 475 #define NV_SETUP5_DELAYMAX      50000
 476 #define NV_POWERUP_DELAY        5
 477 #define NV_POWERUP_DELAYMAX     5000
 478 #define NV_MIIBUSY_DELAY        50
 479 #define NV_MIIPHY_DELAY 10
 480 #define NV_MIIPHY_DELAYMAX      10000
 481 #define NV_MAC_RESET_DELAY      64
 482
 483 #define NV_WAKEUPPATTERNS       5
 484 #define NV_WAKEUPMASKENTRIES    4
 485
 486 /* General driver defaults */
 487 #define NV_WATCHDOG_TIMEO       (5*HZ)
 488
 489 #define RX_RING_DEFAULT         128
 490 #define TX_RING_DEFAULT         256
 491 #define RX_RING_MIN             128
 492 #define TX_RING_MIN             64
 493 #define RING_MAX_DESC_VER_1     1024
 494 #define RING_MAX_DESC_VER_2_3   16384
 495 /*
 496  * Difference between the get and put pointers for the tx ring.
 497  * This is used to throttle the amount of data outstanding in the
 498  * tx ring.
 499  */
 500 #define TX_LIMIT_DIFFERENCE     1
 501
 502 /* rx/tx mac addr + type + vlan + align + slack*/
 503 #define NV_RX_HEADERS           (64)
 504 /* even more slack. */
 505 #define NV_RX_ALLOC_PAD         (64)
 506
 507 /* maximum mtu size */
 508 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 509 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 510
 511 #define OOM_REFILL      (1+HZ/20)
 512 #define POLL_WAIT       (1+HZ/100)
 513 #define LINK_TIMEOUT    (3*HZ)
 514 #define STATS_INTERVAL  (10*HZ)
 515
 516 /*
 517  * desc_ver values:
 518  * The nic supports three different descriptor types:
 519  * - DESC_VER_1: Original
 520  * - DESC_VER_2: support for jumbo frames.
 521  * - DESC_VER_3: 64-bit format.
 522  */
 523 #define DESC_VER_1      1
 524 #define DESC_VER_2      2
 525 #define DESC_VER_3      3
 526
 527 /* PHY defines */
 528 #define PHY_OUI_MARVELL 0x5043
 529 #define PHY_OUI_CICADA  0x03f1
 530 #define PHYID1_OUI_MASK 0x03ff
 531 #define PHYID1_OUI_SHFT 6
 532 #define PHYID2_OUI_MASK 0xfc00
 533 #define PHYID2_OUI_SHFT 10
 534 #define PHY_INIT1       0x0f000
 535 #define PHY_INIT2       0x0e00
 536 #define PHY_INIT3       0x01000
 537 #define PHY_INIT4       0x0200
 538 #define PHY_INIT5       0x0004
 539 #define PHY_INIT6       0x02000
 540 #define PHY_GIGABIT     0x0100
 541
 542 #define PHY_TIMEOUT     0x1
 543 #define PHY_ERROR       0x2
 544
 545 #define PHY_100 0x1
 546 #define PHY_1000        0x2
 547 #define PHY_HALF        0x100
 548
 549 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 550 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 551 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 552 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 553 #define NV_PAUSEFRAME_RX_REQ     0x0010
 554 #define NV_PAUSEFRAME_TX_REQ     0x0020
 555 #define NV_PAUSEFRAME_AUTONEG    0x0040
 556
 557 /* MSI/MSI-X defines */
 558 #define NV_MSI_X_MAX_VECTORS  8
 559 #define NV_MSI_X_VECTORS_MASK 0x000f
 560 #define NV_MSI_CAPABLE        0x0010
 561 #define NV_MSI_X_CAPABLE      0x0020
 562 #define NV_MSI_ENABLED        0x0040
 563 #define NV_MSI_X_ENABLED      0x0080
 564
 565 #define NV_MSI_X_VECTOR_ALL   0x0
 566 #define NV_MSI_X_VECTOR_RX    0x0
 567 #define NV_MSI_X_VECTOR_TX    0x1
 568 #define NV_MSI_X_VECTOR_OTHER 0x2
 569
 570 /* statistics */
 571 struct nv_ethtool_str {
 572         char name[ETH_GSTRING_LEN];
 573 };
 574
 575 static const struct nv_ethtool_str nv_estats_str[] = {
 576         { "tx_bytes" },
 577         { "tx_zero_rexmt" },
 578         { "tx_one_rexmt" },
 579         { "tx_many_rexmt" },
 580         { "tx_late_collision" },
 581         { "tx_fifo_errors" },
 582         { "tx_carrier_errors" },
 583         { "tx_excess_deferral" },
 584         { "tx_retry_error" },
 585         { "tx_deferral" },
 586         { "tx_packets" },
 587         { "tx_pause" },
 588         { "rx_frame_error" },
 589         { "rx_extra_byte" },
 590         { "rx_late_collision" },
 591         { "rx_runt" },
 592         { "rx_frame_too_long" },
 593         { "rx_over_errors" },
 594         { "rx_crc_errors" },
 595         { "rx_frame_align_error" },
 596         { "rx_length_error" },
 597         { "rx_unicast" },
 598         { "rx_multicast" },
 599         { "rx_broadcast" },
 600         { "rx_bytes" },
 601         { "rx_pause" },
 602         { "rx_drop_frame" },
 603         { "rx_packets" },
 604         { "rx_errors_total" }
 605 };
 606
 607 struct nv_ethtool_stats {
 608         u64 tx_bytes;
 609         u64 tx_zero_rexmt;
 610         u64 tx_one_rexmt;
 611         u64 tx_many_rexmt;
 612         u64 tx_late_collision;
 613         u64 tx_fifo_errors;
 614         u64 tx_carrier_errors;
 615         u64 tx_excess_deferral;
 616         u64 tx_retry_error;
 617         u64 tx_deferral;
 618         u64 tx_packets;
 619         u64 tx_pause;
 620         u64 rx_frame_error;
 621         u64 rx_extra_byte;
 622         u64 rx_late_collision;
 623         u64 rx_runt;
 624         u64 rx_frame_too_long;
 625         u64 rx_over_errors;
 626         u64 rx_crc_errors;
 627         u64 rx_frame_align_error;
 628         u64 rx_length_error;
 629         u64 rx_unicast;
 630         u64 rx_multicast;
 631         u64 rx_broadcast;
 632         u64 rx_bytes;
 633         u64 rx_pause;
 634         u64 rx_drop_frame;
 635         u64 rx_packets;
 636         u64 rx_errors_total;
 637 };
 638
 639 /* diagnostics */
 640 #define NV_TEST_COUNT_BASE 3
 641 #define NV_TEST_COUNT_EXTENDED 4
 642
 643 static const struct nv_ethtool_str nv_etests_str[] = {
 644         { "link      (online/offline)" },
 645         { "register  (offline)       " },
 646         { "interrupt (offline)       " },
 647         { "loopback  (offline)       " }
 648 };
 649
 650 struct register_test {
 651         u32 reg;
 652         u32 mask;
 653 };
 654
 655 static const struct register_test nv_registers_test[] = {
 656         { NvRegUnknownSetupReg6, 0x01 },
 657         { NvRegMisc1, 0x03c },
 658         { NvRegOffloadConfig, 0x03ff },
 659         { NvRegMulticastAddrA, 0xffffffff },
 660         { NvRegUnknownSetupReg3, 0x0ff },
 661         { NvRegWakeUpFlags, 0x07777 },
 662         { 0,0 }
 663 };
 664
 665 /*
 666  * SMP locking:
 667  * All hardware access under dev->priv->lock, except the performance
 668  * critical parts:
 669  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 670  *      by the arch code for interrupts.
 671  * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
 672  *      needs dev->priv->lock :-(
 673  * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
 674  */
 675
 676 /* in dev: base, irq */
 677 struct fe_priv {
 678         spinlock_t lock;
 679
 680         /* General data:
 681          * Locking: spin_lock(&np->lock); */
 682         struct net_device_stats stats;
 683         struct nv_ethtool_stats estats;
 684         int in_shutdown;
 685         u32 linkspeed;
 686         int duplex;
 687         int autoneg;
 688         int fixed_mode;
 689         int phyaddr;
 690         int wolenabled;
 691         unsigned int phy_oui;
 692         u16 gigabit;
 693         int intr_test;
 694
 695         /* General data: RO fields */
 696         dma_addr_t ring_addr;
 697         struct pci_dev *pci_dev;
 698         u32 orig_mac[2];
 699         u32 irqmask;
 700         u32 desc_ver;
 701         u32 txrxctl_bits;
 702         u32 vlanctl_bits;
 703         u32 driver_data;
 704         u32 register_size;
 705
 706         void __iomem *base;
 707
 708         /* rx specific fields.
 709          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 710          */
 711         ring_type rx_ring;
 712         unsigned int cur_rx, refill_rx;
 713         struct sk_buff **rx_skbuff;
 714         dma_addr_t *rx_dma;
 715         unsigned int rx_buf_sz;
 716         unsigned int pkt_limit;
 717         struct timer_list oom_kick;
 718         struct timer_list nic_poll;
 719         struct timer_list stats_poll;
 720         u32 nic_poll_irq;
 721         int rx_ring_size;
 722
 723         /* media detection workaround.
 724          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 725          */
 726         int need_linktimer;
 727         unsigned long link_timeout;
 728         /*
 729          * tx specific fields.
 730          */
 731         ring_type tx_ring;
 732         unsigned int next_tx, nic_tx;
 733         struct sk_buff **tx_skbuff;
 734         dma_addr_t *tx_dma;
 735         unsigned int *tx_dma_len;
 736         u32 tx_flags;
 737         int tx_ring_size;
 738         int tx_limit_start;
 739         int tx_limit_stop;
 740
 741         /* vlan fields */
 742         struct vlan_group *vlangrp;
 743
 744         /* msi/msi-x fields */
 745         u32 msi_flags;
 746         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 747
 748         /* flow control */
 749         u32 pause_flags;
 750 };
 751
 752 /*
 753  * Maximum number of loops until we assume that a bit in the irq mask
 754  * is stuck. Overridable with module param.
 755  */
 756 static int max_interrupt_work = 5;
 757
 758 /*
 759  * Optimization can be either throuput mode or cpu mode
 760  *
 761  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 762  * CPU Mode: Interrupts are controlled by a timer.
 763  */
 764 enum {
 765         NV_OPTIMIZATION_MODE_THROUGHPUT,
 766         NV_OPTIMIZATION_MODE_CPU
 767 };
 768 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
 769
 770 /*
 771  * Poll interval for timer irq
 772  *
 773  * This interval determines how frequent an interrupt is generated.
 774  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 775  * Min = 0, and Max = 65535
 776  */
 777 static int poll_interval = -1;
 778
 779 /*
 780  * MSI interrupts
 781  */
 782 enum {
 783         NV_MSI_INT_DISABLED,
 784         NV_MSI_INT_ENABLED
 785 };
 786 static int msi = NV_MSI_INT_ENABLED;
 787
 788 /*
 789  * MSIX interrupts
 790  */
 791 enum {
 792         NV_MSIX_INT_DISABLED,
 793         NV_MSIX_INT_ENABLED
 794 };
 795 static int msix = NV_MSIX_INT_ENABLED;
 796
 797 /*
 798  * DMA 64bit
 799  */
 800 enum {
 801         NV_DMA_64BIT_DISABLED,
 802         NV_DMA_64BIT_ENABLED
 803 };
 804 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 805
 806 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 807 {
 808         return netdev_priv(dev);
 809 }
 810
 811 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 812 {
 813         return ((struct fe_priv *)netdev_priv(dev))->base;
 814 }
 815
 816 static inline void pci_push(u8 __iomem *base)
 817 {
 818         /* force out pending posted writes */
 819         readl(base);
 820 }
 821
 822 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 823 {
 824         return le32_to_cpu(prd->FlagLen)
 825                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 826 }
 827
 828 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 829 {
 830         return le32_to_cpu(prd->FlagLen) & LEN_MASK_V2;
 831 }
 832
 833 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 834                                 int delay, int delaymax, const char *msg)
 835 {
 836         u8 __iomem *base = get_hwbase(dev);
 837
 838         pci_push(base);
 839         do {
 840                 udelay(delay);
 841                 delaymax -= delay;
 842                 if (delaymax < 0) {
 843                         if (msg)
 844                                 printk(msg);
 845                         return 1;
 846                 }
 847         } while ((readl(base + offset) & mask) != target);
 848         return 0;
 849 }
 850
 851 #define NV_SETUP_RX_RING 0x01
 852 #define NV_SETUP_TX_RING 0x02
 853
 854 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
 855 {
 856         struct fe_priv *np = get_nvpriv(dev);
 857         u8 __iomem *base = get_hwbase(dev);
 858
 859         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 860                 if (rxtx_flags & NV_SETUP_RX_RING) {
 861                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 862                 }
 863                 if (rxtx_flags & NV_SETUP_TX_RING) {
 864                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
 865                 }
 866         } else {
 867                 if (rxtx_flags & NV_SETUP_RX_RING) {
 868                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 869                         writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
 870                 }
 871                 if (rxtx_flags & NV_SETUP_TX_RING) {
 872                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
 873                         writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
 874                 }
 875         }
 876 }
 877
 878 static void free_rings(struct net_device *dev)
 879 {
 880         struct fe_priv *np = get_nvpriv(dev);
 881
 882         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 883                 if(np->rx_ring.orig)
 884                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
 885                                             np->rx_ring.orig, np->ring_addr);
 886         } else {
 887                 if (np->rx_ring.ex)
 888                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
 889                                             np->rx_ring.ex, np->ring_addr);
 890         }
 891         if (np->rx_skbuff)
 892                 kfree(np->rx_skbuff);
 893         if (np->rx_dma)
 894                 kfree(np->rx_dma);
 895         if (np->tx_skbuff)
 896                 kfree(np->tx_skbuff);
 897         if (np->tx_dma)
 898                 kfree(np->tx_dma);
 899         if (np->tx_dma_len)
 900                 kfree(np->tx_dma_len);
 901 }
 902
 903 static int using_multi_irqs(struct net_device *dev)
 904 {
 905         struct fe_priv *np = get_nvpriv(dev);
 906
 907         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
 908             ((np->msi_flags & NV_MSI_X_ENABLED) &&
 909              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
 910                 return 0;
 911         else
 912                 return 1;
 913 }
 914
 915 static void nv_enable_irq(struct net_device *dev)
 916 {
 917         struct fe_priv *np = get_nvpriv(dev);
 918
 919         if (!using_multi_irqs(dev)) {
 920                 if (np->msi_flags & NV_MSI_X_ENABLED)
 921                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 922                 else
 923                         enable_irq(dev->irq);
 924         } else {
 925                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 926                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 927                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
 928         }
 929 }
 930
 931 static void nv_disable_irq(struct net_device *dev)
 932 {
 933         struct fe_priv *np = get_nvpriv(dev);
 934
 935         if (!using_multi_irqs(dev)) {
 936                 if (np->msi_flags & NV_MSI_X_ENABLED)
 937                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 938                 else
 939                         disable_irq(dev->irq);
 940         } else {
 941                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 942                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 943                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
 944         }
 945 }
 946
 947 /* In MSIX mode, a write to irqmask behaves as XOR */
 948 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
 949 {
 950         u8 __iomem *base = get_hwbase(dev);
 951
 952         writel(mask, base + NvRegIrqMask);
 953 }
 954
 955 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
 956 {
 957         struct fe_priv *np = get_nvpriv(dev);
 958         u8 __iomem *base = get_hwbase(dev);
 959
 960         if (np->msi_flags & NV_MSI_X_ENABLED) {
 961                 writel(mask, base + NvRegIrqMask);
 962         } else {
 963                 if (np->msi_flags & NV_MSI_ENABLED)
 964                         writel(0, base + NvRegMSIIrqMask);
 965                 writel(0, base + NvRegIrqMask);
 966         }
 967 }
 968
 969 #define MII_READ        (-1)
 970 /* mii_rw: read/write a register on the PHY.
 971  *
 972  * Caller must guarantee serialization
 973  */
 974 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
 975 {
 976         u8 __iomem *base = get_hwbase(dev);
 977         u32 reg;
 978         int retval;
 979
 980         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
 981
 982         reg = readl(base + NvRegMIIControl);
 983         if (reg & NVREG_MIICTL_INUSE) {
 984                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
 985                 udelay(NV_MIIBUSY_DELAY);
 986         }
 987
 988         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
 989         if (value != MII_READ) {
 990                 writel(value, base + NvRegMIIData);
 991                 reg |= NVREG_MIICTL_WRITE;
 992         }
 993         writel(reg, base + NvRegMIIControl);
 994
 995         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
 996                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
 997                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
 998                                 dev->name, miireg, addr);
 999                 retval = -1;
1000         } else if (value != MII_READ) {
1001                 /* it was a write operation - fewer failures are detectable */
1002                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1003                                 dev->name, value, miireg, addr);
1004                 retval = 0;
1005         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1006                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1007                                 dev->name, miireg, addr);
1008                 retval = -1;
1009         } else {
1010                 retval = readl(base + NvRegMIIData);
1011                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1012                                 dev->name, miireg, addr, retval);
1013         }
1014
1015         return retval;
1016 }
1017
1018 static int phy_reset(struct net_device *dev)
1019 {
1020         struct fe_priv *np = netdev_priv(dev);
1021         u32 miicontrol;
1022         unsigned int tries = 0;
1023
1024         miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1025         miicontrol |= BMCR_RESET;
1026         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1027                 return -1;
1028         }
1029
1030         /* wait for 500ms */
1031         msleep(500);
1032
1033         /* must wait till reset is deasserted */
1034         while (miicontrol & BMCR_RESET) {
1035                 msleep(10);
1036                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1037                 /* FIXME: 100 tries seem excessive */
1038                 if (tries++ > 100)
1039                         return -1;
1040         }
1041         return 0;
1042 }
1043
1044 static int phy_init(struct net_device *dev)
1045 {
1046         struct fe_priv *np = get_nvpriv(dev);
1047         u8 __iomem *base = get_hwbase(dev);
1048         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1049
1050         /* set advertise register */
1051         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1052         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1053         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1054                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1055                 return PHY_ERROR;
1056         }
1057
1058         /* get phy interface type */
1059         phyinterface = readl(base + NvRegPhyInterface);
1060
1061         /* see if gigabit phy */
1062         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1063         if (mii_status & PHY_GIGABIT) {
1064                 np->gigabit = PHY_GIGABIT;
1065                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1066                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1067                 if (phyinterface & PHY_RGMII)
1068                         mii_control_1000 |= ADVERTISE_1000FULL;
1069                 else
1070                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1071
1072                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1073                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1074                         return PHY_ERROR;
1075                 }
1076         }
1077         else
1078                 np->gigabit = 0;
1079
1080         /* reset the phy */
1081         if (phy_reset(dev)) {
1082                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1083                 return PHY_ERROR;
1084         }
1085
1086         /* phy vendor specific configuration */
1087         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1088                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1089                 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
1090                 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
1091                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1092                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1093                         return PHY_ERROR;
1094                 }
1095                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1096                 phy_reserved |= PHY_INIT5;
1097                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1098                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1099                         return PHY_ERROR;
1100                 }
1101         }
1102         if (np->phy_oui == PHY_OUI_CICADA) {
1103                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1104                 phy_reserved |= PHY_INIT6;
1105                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1106                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1107                         return PHY_ERROR;
1108                 }
1109         }
1110         /* some phys clear out pause advertisment on reset, set it back */
1111         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1112
1113         /* restart auto negotiation */
1114         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1115         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1116         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1117                 return PHY_ERROR;
1118         }
1119
1120         return 0;
1121 }
1122
1123 static void nv_start_rx(struct net_device *dev)
1124 {
1125         struct fe_priv *np = netdev_priv(dev);
1126         u8 __iomem *base = get_hwbase(dev);
1127
1128         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1129         /* Already running? Stop it. */
1130         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
1131                 writel(0, base + NvRegReceiverControl);
1132                 pci_push(base);
1133         }
1134         writel(np->linkspeed, base + NvRegLinkSpeed);
1135         pci_push(base);
1136         writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
1137         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1138                                 dev->name, np->duplex, np->linkspeed);
1139         pci_push(base);
1140 }
1141
1142 static void nv_stop_rx(struct net_device *dev)
1143 {
1144         u8 __iomem *base = get_hwbase(dev);
1145
1146         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1147         writel(0, base + NvRegReceiverControl);
1148         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1149                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1150                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1151
1152         udelay(NV_RXSTOP_DELAY2);
1153         writel(0, base + NvRegLinkSpeed);
1154 }
1155
1156 static void nv_start_tx(struct net_device *dev)
1157 {
1158         u8 __iomem *base = get_hwbase(dev);
1159
1160         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1161         writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
1162         pci_push(base);
1163 }
1164
1165 static void nv_stop_tx(struct net_device *dev)
1166 {
1167         u8 __iomem *base = get_hwbase(dev);
1168
1169         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1170         writel(0, base + NvRegTransmitterControl);
1171         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1172                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1173                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1174
1175         udelay(NV_TXSTOP_DELAY2);
1176         writel(0, base + NvRegUnknownTransmitterReg);
1177 }
1178
1179 static void nv_txrx_reset(struct net_device *dev)
1180 {
1181         struct fe_priv *np = netdev_priv(dev);
1182         u8 __iomem *base = get_hwbase(dev);
1183
1184         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1185         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1186         pci_push(base);
1187         udelay(NV_TXRX_RESET_DELAY);
1188         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1189         pci_push(base);
1190 }
1191
1192 static void nv_mac_reset(struct net_device *dev)
1193 {
1194         struct fe_priv *np = netdev_priv(dev);
1195         u8 __iomem *base = get_hwbase(dev);
1196
1197         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1198         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1199         pci_push(base);
1200         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1201         pci_push(base);
1202         udelay(NV_MAC_RESET_DELAY);
1203         writel(0, base + NvRegMacReset);
1204         pci_push(base);
1205         udelay(NV_MAC_RESET_DELAY);
1206         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1207         pci_push(base);
1208 }
1209
1210 /*
1211  * nv_get_stats: dev->get_stats function
1212  * Get latest stats value from the nic.
1213  * Called with read_lock(&dev_base_lock) held for read -
1214  * only synchronized against unregister_netdevice.
1215  */
1216 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1217 {
1218         struct fe_priv *np = netdev_priv(dev);
1219
1220         /* It seems that the nic always generates interrupts and doesn't
1221          * accumulate errors internally. Thus the current values in np->stats
1222          * are already up to date.
1223          */
1224         return &np->stats;
1225 }
1226
1227 /*
1228  * nv_alloc_rx: fill rx ring entries.
1229  * Return 1 if the allocations for the skbs failed and the
1230  * rx engine is without Available descriptors
1231  */
1232 static int nv_alloc_rx(struct net_device *dev)
1233 {
1234         struct fe_priv *np = netdev_priv(dev);
1235         unsigned int refill_rx = np->refill_rx;
1236         int nr;
1237
1238         while (np->cur_rx != refill_rx) {
1239                 struct sk_buff *skb;
1240
1241                 nr = refill_rx % np->rx_ring_size;
1242                 if (np->rx_skbuff[nr] == NULL) {
1243
1244                         skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1245                         if (!skb)
1246                                 break;
1247
1248                         skb->dev = dev;
1249                         np->rx_skbuff[nr] = skb;
1250                 } else {
1251                         skb = np->rx_skbuff[nr];
1252                 }
1253                 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data,
1254                                         skb->end-skb->data, PCI_DMA_FROMDEVICE);
1255                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1256                         np->rx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
1257                         wmb();
1258                         np->rx_ring.orig[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1259                 } else {
1260                         np->rx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
1261                         np->rx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
1262                         wmb();
1263                         np->rx_ring.ex[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1264                 }
1265                 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
1266                                         dev->name, refill_rx);
1267                 refill_rx++;
1268         }
1269         np->refill_rx = refill_rx;
1270         if (np->cur_rx - refill_rx == np->rx_ring_size)
1271                 return 1;
1272         return 0;
1273 }
1274
1275 static void nv_do_rx_refill(unsigned long data)
1276 {
1277         struct net_device *dev = (struct net_device *) data;
1278         struct fe_priv *np = netdev_priv(dev);
1279
1280         if (!using_multi_irqs(dev)) {
1281                 if (np->msi_flags & NV_MSI_X_ENABLED)
1282                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1283                 else
1284                         disable_irq(dev->irq);
1285         } else {
1286                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1287         }
1288         if (nv_alloc_rx(dev)) {
1289                 spin_lock_irq(&np->lock);
1290                 if (!np->in_shutdown)
1291                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1292                 spin_unlock_irq(&np->lock);
1293         }
1294         if (!using_multi_irqs(dev)) {
1295                 if (np->msi_flags & NV_MSI_X_ENABLED)
1296                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1297                 else
1298                         enable_irq(dev->irq);
1299         } else {
1300                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1301         }
1302 }
1303
1304 static void nv_init_rx(struct net_device *dev)
1305 {
1306         struct fe_priv *np = netdev_priv(dev);
1307         int i;
1308
1309         np->cur_rx = np->rx_ring_size;
1310         np->refill_rx = 0;
1311         for (i = 0; i < np->rx_ring_size; i++)
1312                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1313                         np->rx_ring.orig[i].FlagLen = 0;
1314                 else
1315                         np->rx_ring.ex[i].FlagLen = 0;
1316 }
1317
1318 static void nv_init_tx(struct net_device *dev)
1319 {
1320         struct fe_priv *np = netdev_priv(dev);
1321         int i;
1322
1323         np->next_tx = np->nic_tx = 0;
1324         for (i = 0; i < np->tx_ring_size; i++) {
1325                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1326                         np->tx_ring.orig[i].FlagLen = 0;
1327                 else
1328                         np->tx_ring.ex[i].FlagLen = 0;
1329                 np->tx_skbuff[i] = NULL;
1330                 np->tx_dma[i] = 0;
1331         }
1332 }
1333
1334 static int nv_init_ring(struct net_device *dev)
1335 {
1336         nv_init_tx(dev);
1337         nv_init_rx(dev);
1338         return nv_alloc_rx(dev);
1339 }
1340
1341 static int nv_release_txskb(struct net_device *dev, unsigned int skbnr)
1342 {
1343         struct fe_priv *np = netdev_priv(dev);
1344
1345         dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d\n",
1346                 dev->name, skbnr);
1347
1348         if (np->tx_dma[skbnr]) {
1349                 pci_unmap_page(np->pci_dev, np->tx_dma[skbnr],
1350                                np->tx_dma_len[skbnr],
1351                                PCI_DMA_TODEVICE);
1352                 np->tx_dma[skbnr] = 0;
1353         }
1354
1355         if (np->tx_skbuff[skbnr]) {
1356                 dev_kfree_skb_any(np->tx_skbuff[skbnr]);
1357                 np->tx_skbuff[skbnr] = NULL;
1358                 return 1;
1359         } else {
1360                 return 0;
1361         }
1362 }
1363
1364 static void nv_drain_tx(struct net_device *dev)
1365 {
1366         struct fe_priv *np = netdev_priv(dev);
1367         unsigned int i;
1368
1369         for (i = 0; i < np->tx_ring_size; i++) {
1370                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1371                         np->tx_ring.orig[i].FlagLen = 0;
1372                 else
1373                         np->tx_ring.ex[i].FlagLen = 0;
1374                 if (nv_release_txskb(dev, i))
1375                         np->stats.tx_dropped++;
1376         }
1377 }
1378
1379 static void nv_drain_rx(struct net_device *dev)
1380 {
1381         struct fe_priv *np = netdev_priv(dev);
1382         int i;
1383         for (i = 0; i < np->rx_ring_size; i++) {
1384                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1385                         np->rx_ring.orig[i].FlagLen = 0;
1386                 else
1387                         np->rx_ring.ex[i].FlagLen = 0;
1388                 wmb();
1389                 if (np->rx_skbuff[i]) {
1390                         pci_unmap_single(np->pci_dev, np->rx_dma[i],
1391                                                 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1392                                                 PCI_DMA_FROMDEVICE);
1393                         dev_kfree_skb(np->rx_skbuff[i]);
1394                         np->rx_skbuff[i] = NULL;
1395                 }
1396         }
1397 }
1398
1399 static void drain_ring(struct net_device *dev)
1400 {
1401         nv_drain_tx(dev);
1402         nv_drain_rx(dev);
1403 }
1404
1405 /*
1406  * nv_start_xmit: dev->hard_start_xmit function
1407  * Called with dev->xmit_lock held.
1408  */
1409 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1410 {
1411         struct fe_priv *np = netdev_priv(dev);
1412         u32 tx_flags = 0;
1413         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1414         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1415         unsigned int nr = (np->next_tx - 1) % np->tx_ring_size;
1416         unsigned int start_nr = np->next_tx % np->tx_ring_size;
1417         unsigned int i;
1418         u32 offset = 0;
1419         u32 bcnt;
1420         u32 size = skb->len-skb->data_len;
1421         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1422         u32 tx_flags_vlan = 0;
1423
1424         /* add fragments to entries count */
1425         for (i = 0; i < fragments; i++) {
1426                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1427                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1428         }
1429
1430         spin_lock_irq(&np->lock);
1431
1432         if ((np->next_tx - np->nic_tx + entries - 1) > np->tx_limit_stop) {
1433                 spin_unlock_irq(&np->lock);
1434                 netif_stop_queue(dev);
1435                 return NETDEV_TX_BUSY;
1436         }
1437
1438         /* setup the header buffer */
1439         do {
1440                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1441                 nr = (nr + 1) % np->tx_ring_size;
1442
1443                 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1444                                                 PCI_DMA_TODEVICE);
1445                 np->tx_dma_len[nr] = bcnt;
1446
1447                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1448                         np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1449                         np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1450                 } else {
1451                         np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1452                         np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1453                         np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1454                 }
1455                 tx_flags = np->tx_flags;
1456                 offset += bcnt;
1457                 size -= bcnt;
1458         } while(size);
1459
1460         /* setup the fragments */
1461         for (i = 0; i < fragments; i++) {
1462                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1463                 u32 size = frag->size;
1464                 offset = 0;
1465
1466                 do {
1467                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1468                         nr = (nr + 1) % np->tx_ring_size;
1469
1470                         np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1471                                                       PCI_DMA_TODEVICE);
1472                         np->tx_dma_len[nr] = bcnt;
1473
1474                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1475                                 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1476                                 np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1477                         } else {
1478                                 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1479                                 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1480                                 np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1481                         }
1482                         offset += bcnt;
1483                         size -= bcnt;
1484                 } while (size);
1485         }
1486
1487         /* set last fragment flag  */
1488         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1489                 np->tx_ring.orig[nr].FlagLen |= cpu_to_le32(tx_flags_extra);
1490         } else {
1491                 np->tx_ring.ex[nr].FlagLen |= cpu_to_le32(tx_flags_extra);
1492         }
1493
1494         np->tx_skbuff[nr] = skb;
1495
1496 #ifdef NETIF_F_TSO
1497         if (skb_shinfo(skb)->tso_size)
1498                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->tso_size << NV_TX2_TSO_SHIFT);
1499         else
1500 #endif
1501         tx_flags_extra = (skb->ip_summed == CHECKSUM_HW ? (NV_TX2_CHECKSUM_L3|NV_TX2_CHECKSUM_L4) : 0);
1502
1503         /* vlan tag */
1504         if (np->vlangrp && vlan_tx_tag_present(skb)) {
1505                 tx_flags_vlan = NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb);
1506         }
1507
1508         /* set tx flags */
1509         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1510                 np->tx_ring.orig[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra);
1511         } else {
1512                 np->tx_ring.ex[start_nr].TxVlan = cpu_to_le32(tx_flags_vlan);
1513                 np->tx_ring.ex[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra);
1514         }
1515
1516         dprintk(KERN_DEBUG "%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n",
1517                 dev->name, np->next_tx, entries, tx_flags_extra);
1518         {
1519                 int j;
1520                 for (j=0; j<64; j++) {
1521                         if ((j%16) == 0)
1522                                 dprintk("\n%03x:", j);
1523                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1524                 }
1525                 dprintk("\n");
1526         }
1527
1528         np->next_tx += entries;
1529
1530         dev->trans_start = jiffies;
1531         spin_unlock_irq(&np->lock);
1532         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1533         pci_push(get_hwbase(dev));
1534         return NETDEV_TX_OK;
1535 }
1536
1537 /*
1538  * nv_tx_done: check for completed packets, release the skbs.
1539  *
1540  * Caller must own np->lock.
1541  */
1542 static void nv_tx_done(struct net_device *dev)
1543 {
1544         struct fe_priv *np = netdev_priv(dev);
1545         u32 Flags;
1546         unsigned int i;
1547         struct sk_buff *skb;
1548
1549         while (np->nic_tx != np->next_tx) {
1550                 i = np->nic_tx % np->tx_ring_size;
1551
1552                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1553                         Flags = le32_to_cpu(np->tx_ring.orig[i].FlagLen);
1554                 else
1555                         Flags = le32_to_cpu(np->tx_ring.ex[i].FlagLen);
1556
1557                 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
1558                                         dev->name, np->nic_tx, Flags);
1559                 if (Flags & NV_TX_VALID)
1560                         break;
1561                 if (np->desc_ver == DESC_VER_1) {
1562                         if (Flags & NV_TX_LASTPACKET) {
1563                                 skb = np->tx_skbuff[i];
1564                                 if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1565                                              NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1566                                         if (Flags & NV_TX_UNDERFLOW)
1567                                                 np->stats.tx_fifo_errors++;
1568                                         if (Flags & NV_TX_CARRIERLOST)
1569                                                 np->stats.tx_carrier_errors++;
1570                                         np->stats.tx_errors++;
1571                                 } else {
1572                                         np->stats.tx_packets++;
1573                                         np->stats.tx_bytes += skb->len;
1574                                 }
1575                         }
1576                 } else {
1577                         if (Flags & NV_TX2_LASTPACKET) {
1578                                 skb = np->tx_skbuff[i];
1579                                 if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1580                                              NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1581                                         if (Flags & NV_TX2_UNDERFLOW)
1582                                                 np->stats.tx_fifo_errors++;
1583                                         if (Flags & NV_TX2_CARRIERLOST)
1584                                                 np->stats.tx_carrier_errors++;
1585                                         np->stats.tx_errors++;
1586                                 } else {
1587                                         np->stats.tx_packets++;
1588                                         np->stats.tx_bytes += skb->len;
1589                                 }
1590                         }
1591                 }
1592                 nv_release_txskb(dev, i);
1593                 np->nic_tx++;
1594         }
1595         if (np->next_tx - np->nic_tx < np->tx_limit_start)
1596                 netif_wake_queue(dev);
1597 }
1598
1599 /*
1600  * nv_tx_timeout: dev->tx_timeout function
1601  * Called with dev->xmit_lock held.
1602  */
1603 static void nv_tx_timeout(struct net_device *dev)
1604 {
1605         struct fe_priv *np = netdev_priv(dev);
1606         u8 __iomem *base = get_hwbase(dev);
1607         u32 status;
1608
1609         if (np->msi_flags & NV_MSI_X_ENABLED)
1610                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
1611         else
1612                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1613
1614         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
1615
1616         {
1617                 int i;
1618
1619                 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
1620                                 dev->name, (unsigned long)np->ring_addr,
1621                                 np->next_tx, np->nic_tx);
1622                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1623                 for (i=0;i<=np->register_size;i+= 32) {
1624                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1625                                         i,
1626                                         readl(base + i + 0), readl(base + i + 4),
1627                                         readl(base + i + 8), readl(base + i + 12),
1628                                         readl(base + i + 16), readl(base + i + 20),
1629                                         readl(base + i + 24), readl(base + i + 28));
1630                 }
1631                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1632                 for (i=0;i<np->tx_ring_size;i+= 4) {
1633                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1634                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1635                                        i,
1636                                        le32_to_cpu(np->tx_ring.orig[i].PacketBuffer),
1637                                        le32_to_cpu(np->tx_ring.orig[i].FlagLen),
1638                                        le32_to_cpu(np->tx_ring.orig[i+1].PacketBuffer),
1639                                        le32_to_cpu(np->tx_ring.orig[i+1].FlagLen),
1640                                        le32_to_cpu(np->tx_ring.orig[i+2].PacketBuffer),
1641                                        le32_to_cpu(np->tx_ring.orig[i+2].FlagLen),
1642                                        le32_to_cpu(np->tx_ring.orig[i+3].PacketBuffer),
1643                                        le32_to_cpu(np->tx_ring.orig[i+3].FlagLen));
1644                         } else {
1645                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1646                                        i,
1647                                        le32_to_cpu(np->tx_ring.ex[i].PacketBufferHigh),
1648                                        le32_to_cpu(np->tx_ring.ex[i].PacketBufferLow),
1649                                        le32_to_cpu(np->tx_ring.ex[i].FlagLen),
1650                                        le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferHigh),
1651                                        le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferLow),
1652                                        le32_to_cpu(np->tx_ring.ex[i+1].FlagLen),
1653                                        le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferHigh),
1654                                        le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferLow),
1655                                        le32_to_cpu(np->tx_ring.ex[i+2].FlagLen),
1656                                        le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferHigh),
1657                                        le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferLow),
1658                                        le32_to_cpu(np->tx_ring.ex[i+3].FlagLen));
1659                         }
1660                 }
1661         }
1662
1663         spin_lock_irq(&np->lock);
1664
1665         /* 1) stop tx engine */
1666         nv_stop_tx(dev);
1667
1668         /* 2) check that the packets were not sent already: */
1669         nv_tx_done(dev);
1670
1671         /* 3) if there are dead entries: clear everything */
1672         if (np->next_tx != np->nic_tx) {
1673                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1674                 nv_drain_tx(dev);
1675                 np->next_tx = np->nic_tx = 0;
1676                 setup_hw_rings(dev, NV_SETUP_TX_RING);
1677                 netif_wake_queue(dev);
1678         }
1679
1680         /* 4) restart tx engine */
1681         nv_start_tx(dev);
1682         spin_unlock_irq(&np->lock);
1683 }
1684
1685 /*
1686  * Called when the nic notices a mismatch between the actual data len on the
1687  * wire and the len indicated in the 802 header
1688  */
1689 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1690 {
1691         int hdrlen;     /* length of the 802 header */
1692         int protolen;   /* length as stored in the proto field */
1693
1694         /* 1) calculate len according to header */
1695         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) {
1696                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1697                 hdrlen = VLAN_HLEN;
1698         } else {
1699                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1700                 hdrlen = ETH_HLEN;
1701         }
1702         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1703                                 dev->name, datalen, protolen, hdrlen);
1704         if (protolen > ETH_DATA_LEN)
1705                 return datalen; /* Value in proto field not a len, no checks possible */
1706
1707         protolen += hdrlen;
1708         /* consistency checks: */
1709         if (datalen > ETH_ZLEN) {
1710                 if (datalen >= protolen) {
1711                         /* more data on wire than in 802 header, trim of
1712                          * additional data.
1713                          */
1714                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1715                                         dev->name, protolen);
1716                         return protolen;
1717                 } else {
1718                         /* less data on wire than mentioned in header.
1719                          * Discard the packet.
1720                          */
1721                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1722                                         dev->name);
1723                         return -1;
1724                 }
1725         } else {
1726                 /* short packet. Accept only if 802 values are also short */
1727                 if (protolen > ETH_ZLEN) {
1728                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1729                                         dev->name);
1730                         return -1;
1731                 }
1732                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1733                                 dev->name, datalen);
1734                 return datalen;
1735         }
1736 }
1737
1738 static void nv_rx_process(struct net_device *dev)
1739 {
1740         struct fe_priv *np = netdev_priv(dev);
1741         u32 Flags;
1742         u32 vlanflags = 0;
1743
1744         for (;;) {
1745                 struct sk_buff *skb;
1746                 int len;
1747                 int i;
1748                 if (np->cur_rx - np->refill_rx >= np->rx_ring_size)
1749                         break;  /* we scanned the whole ring - do not continue */
1750
1751                 i = np->cur_rx % np->rx_ring_size;
1752                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1753                         Flags = le32_to_cpu(np->rx_ring.orig[i].FlagLen);
1754                         len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
1755                 } else {
1756                         Flags = le32_to_cpu(np->rx_ring.ex[i].FlagLen);
1757                         len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
1758                         vlanflags = le32_to_cpu(np->rx_ring.ex[i].PacketBufferLow);
1759                 }
1760
1761                 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1762                                         dev->name, np->cur_rx, Flags);
1763
1764                 if (Flags & NV_RX_AVAIL)
1765                         break;  /* still owned by hardware, */
1766
1767                 /*
1768                  * the packet is for us - immediately tear down the pci mapping.
1769                  * TODO: check if a prefetch of the first cacheline improves
1770                  * the performance.
1771                  */
1772                 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1773                                 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1774                                 PCI_DMA_FROMDEVICE);
1775
1776                 {
1777                         int j;
1778                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags);
1779                         for (j=0; j<64; j++) {
1780                                 if ((j%16) == 0)
1781                                         dprintk("\n%03x:", j);
1782                                 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1783                         }
1784                         dprintk("\n");
1785                 }
1786                 /* look at what we actually got: */
1787                 if (np->desc_ver == DESC_VER_1) {
1788                         if (!(Flags & NV_RX_DESCRIPTORVALID))
1789                                 goto next_pkt;
1790
1791                         if (Flags & NV_RX_ERROR) {
1792                                 if (Flags & NV_RX_MISSEDFRAME) {
1793                                         np->stats.rx_missed_errors++;
1794                                         np->stats.rx_errors++;
1795                                         goto next_pkt;
1796                                 }
1797                                 if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1798                                         np->stats.rx_errors++;
1799                                         goto next_pkt;
1800                                 }
1801                                 if (Flags & NV_RX_CRCERR) {
1802                                         np->stats.rx_crc_errors++;
1803                                         np->stats.rx_errors++;
1804                                         goto next_pkt;
1805                                 }
1806                                 if (Flags & NV_RX_OVERFLOW) {
1807                                         np->stats.rx_over_errors++;
1808                                         np->stats.rx_errors++;
1809                                         goto next_pkt;
1810                                 }
1811                                 if (Flags & NV_RX_ERROR4) {
1812                                         len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1813                                         if (len < 0) {
1814                                                 np->stats.rx_errors++;
1815                                                 goto next_pkt;
1816                                         }
1817                                 }
1818                                 /* framing errors are soft errors. */
1819                                 if (Flags & NV_RX_FRAMINGERR) {
1820                                         if (Flags & NV_RX_SUBSTRACT1) {
1821                                                 len--;
1822                                         }
1823                                 }
1824                         }
1825                 } else {
1826                         if (!(Flags & NV_RX2_DESCRIPTORVALID))
1827                                 goto next_pkt;
1828
1829                         if (Flags & NV_RX2_ERROR) {
1830                                 if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
1831                                         np->stats.rx_errors++;
1832                                         goto next_pkt;
1833                                 }
1834                                 if (Flags & NV_RX2_CRCERR) {
1835                                         np->stats.rx_crc_errors++;
1836                                         np->stats.rx_errors++;
1837                                         goto next_pkt;
1838                                 }
1839                                 if (Flags & NV_RX2_OVERFLOW) {
1840                                         np->stats.rx_over_errors++;
1841                                         np->stats.rx_errors++;
1842                                         goto next_pkt;
1843                                 }
1844                                 if (Flags & NV_RX2_ERROR4) {
1845                                         len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1846                                         if (len < 0) {
1847                                                 np->stats.rx_errors++;
1848                                                 goto next_pkt;
1849                                         }
1850                                 }
1851                                 /* framing errors are soft errors */
1852                                 if (Flags & NV_RX2_FRAMINGERR) {
1853                                         if (Flags & NV_RX2_SUBSTRACT1) {
1854                                                 len--;
1855                                         }
1856                                 }
1857                         }
1858                         if (np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) {
1859                                 Flags &= NV_RX2_CHECKSUMMASK;
1860                                 if (Flags == NV_RX2_CHECKSUMOK1 ||
1861                                     Flags == NV_RX2_CHECKSUMOK2 ||
1862                                     Flags == NV_RX2_CHECKSUMOK3) {
1863                                         dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1864                                         np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1865                                 } else {
1866                                         dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1867                                 }
1868                         }
1869                 }
1870                 /* got a valid packet - forward it to the network core */
1871                 skb = np->rx_skbuff[i];
1872                 np->rx_skbuff[i] = NULL;
1873
1874                 skb_put(skb, len);
1875                 skb->protocol = eth_type_trans(skb, dev);
1876                 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1877                                         dev->name, np->cur_rx, len, skb->protocol);
1878                 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT)) {
1879                         vlan_hwaccel_rx(skb, np->vlangrp, vlanflags & NV_RX3_VLAN_TAG_MASK);
1880                 } else {
1881                         netif_rx(skb);
1882                 }
1883                 dev->last_rx = jiffies;
1884                 np->stats.rx_packets++;
1885                 np->stats.rx_bytes += len;
1886 next_pkt:
1887                 np->cur_rx++;
1888         }
1889 }
1890
1891 static void set_bufsize(struct net_device *dev)
1892 {
1893         struct fe_priv *np = netdev_priv(dev);
1894
1895         if (dev->mtu <= ETH_DATA_LEN)
1896                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
1897         else
1898                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
1899 }
1900
1901 /*
1902  * nv_change_mtu: dev->change_mtu function
1903  * Called with dev_base_lock held for read.
1904  */
1905 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1906 {
1907         struct fe_priv *np = netdev_priv(dev);
1908         int old_mtu;
1909
1910         if (new_mtu < 64 || new_mtu > np->pkt_limit)
1911                 return -EINVAL;
1912
1913         old_mtu = dev->mtu;
1914         dev->mtu = new_mtu;
1915
1916         /* return early if the buffer sizes will not change */
1917         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1918                 return 0;
1919         if (old_mtu == new_mtu)
1920                 return 0;
1921
1922         /* synchronized against open : rtnl_lock() held by caller */
1923         if (netif_running(dev)) {
1924                 u8 __iomem *base = get_hwbase(dev);
1925                 /*
1926                  * It seems that the nic preloads valid ring entries into an
1927                  * internal buffer. The procedure for flushing everything is
1928                  * guessed, there is probably a simpler approach.
1929                  * Changing the MTU is a rare event, it shouldn't matter.
1930                  */
1931                 nv_disable_irq(dev);
1932                 spin_lock_bh(&dev->xmit_lock);
1933                 spin_lock(&np->lock);
1934                 /* stop engines */
1935                 nv_stop_rx(dev);
1936                 nv_stop_tx(dev);
1937                 nv_txrx_reset(dev);
1938                 /* drain rx queue */
1939                 nv_drain_rx(dev);
1940                 nv_drain_tx(dev);
1941                 /* reinit driver view of the rx queue */
1942                 set_bufsize(dev);
1943                 if (nv_init_ring(dev)) {
1944                         if (!np->in_shutdown)
1945                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1946                 }
1947                 /* reinit nic view of the rx queue */
1948                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
1949                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
1950                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
1951                         base + NvRegRingSizes);
1952                 pci_push(base);
1953                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1954                 pci_push(base);
1955
1956                 /* restart rx engine */
1957                 nv_start_rx(dev);
1958                 nv_start_tx(dev);
1959                 spin_unlock(&np->lock);
1960                 spin_unlock_bh(&dev->xmit_lock);
1961                 nv_enable_irq(dev);
1962         }
1963         return 0;
1964 }
1965
1966 static void nv_copy_mac_to_hw(struct net_device *dev)
1967 {
1968         u8 __iomem *base = get_hwbase(dev);
1969         u32 mac[2];
1970
1971         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
1972                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
1973         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
1974
1975         writel(mac[0], base + NvRegMacAddrA);
1976         writel(mac[1], base + NvRegMacAddrB);
1977 }
1978
1979 /*
1980  * nv_set_mac_address: dev->set_mac_address function
1981  * Called with rtnl_lock() held.
1982  */
1983 static int nv_set_mac_address(struct net_device *dev, void *addr)
1984 {
1985         struct fe_priv *np = netdev_priv(dev);
1986         struct sockaddr *macaddr = (struct sockaddr*)addr;
1987
1988         if(!is_valid_ether_addr(macaddr->sa_data))
1989                 return -EADDRNOTAVAIL;
1990
1991         /* synchronized against open : rtnl_lock() held by caller */
1992         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
1993
1994         if (netif_running(dev)) {
1995                 spin_lock_bh(&dev->xmit_lock);
1996                 spin_lock_irq(&np->lock);
1997
1998                 /* stop rx engine */
1999                 nv_stop_rx(dev);
2000
2001                 /* set mac address */
2002                 nv_copy_mac_to_hw(dev);
2003
2004                 /* restart rx engine */
2005                 nv_start_rx(dev);
2006                 spin_unlock_irq(&np->lock);
2007                 spin_unlock_bh(&dev->xmit_lock);
2008         } else {
2009                 nv_copy_mac_to_hw(dev);
2010         }
2011         return 0;
2012 }
2013
2014 /*
2015  * nv_set_multicast: dev->set_multicast function
2016  * Called with dev->xmit_lock held.
2017  */
2018 static void nv_set_multicast(struct net_device *dev)
2019 {
2020         struct fe_priv *np = netdev_priv(dev);
2021         u8 __iomem *base = get_hwbase(dev);
2022         u32 addr[2];
2023         u32 mask[2];
2024         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2025
2026         memset(addr, 0, sizeof(addr));
2027         memset(mask, 0, sizeof(mask));
2028
2029         if (dev->flags & IFF_PROMISC) {
2030                 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
2031                 pff |= NVREG_PFF_PROMISC;
2032         } else {
2033                 pff |= NVREG_PFF_MYADDR;
2034
2035                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2036                         u32 alwaysOff[2];
2037                         u32 alwaysOn[2];
2038
2039                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2040                         if (dev->flags & IFF_ALLMULTI) {
2041                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2042                         } else {
2043                                 struct dev_mc_list *walk;
2044
2045                                 walk = dev->mc_list;
2046                                 while (walk != NULL) {
2047                                         u32 a, b;
2048                                         a = le32_to_cpu(*(u32 *) walk->dmi_addr);
2049                                         b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
2050                                         alwaysOn[0] &= a;
2051                                         alwaysOff[0] &= ~a;
2052                                         alwaysOn[1] &= b;
2053                                         alwaysOff[1] &= ~b;
2054                                         walk = walk->next;
2055                                 }
2056                         }
2057                         addr[0] = alwaysOn[0];
2058                         addr[1] = alwaysOn[1];
2059                         mask[0] = alwaysOn[0] | alwaysOff[0];
2060                         mask[1] = alwaysOn[1] | alwaysOff[1];
2061                 }
2062         }
2063         addr[0] |= NVREG_MCASTADDRA_FORCE;
2064         pff |= NVREG_PFF_ALWAYS;
2065         spin_lock_irq(&np->lock);
2066         nv_stop_rx(dev);
2067         writel(addr[0], base + NvRegMulticastAddrA);
2068         writel(addr[1], base + NvRegMulticastAddrB);
2069         writel(mask[0], base + NvRegMulticastMaskA);
2070         writel(mask[1], base + NvRegMulticastMaskB);
2071         writel(pff, base + NvRegPacketFilterFlags);
2072         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2073                 dev->name);
2074         nv_start_rx(dev);
2075         spin_unlock_irq(&np->lock);
2076 }
2077
2078 void nv_update_pause(struct net_device *dev, u32 pause_flags)
2079 {
2080         struct fe_priv *np = netdev_priv(dev);
2081         u8 __iomem *base = get_hwbase(dev);
2082
2083         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2084
2085         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2086                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2087                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2088                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2089                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2090                 } else {
2091                         writel(pff, base + NvRegPacketFilterFlags);
2092                 }
2093         }
2094         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2095                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2096                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2097                         writel(NVREG_TX_PAUSEFRAME_ENABLE,  base + NvRegTxPauseFrame);
2098                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2099                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2100                 } else {
2101                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
2102                         writel(regmisc, base + NvRegMisc1);
2103                 }
2104         }
2105 }
2106
2107 /**
2108  * nv_update_linkspeed: Setup the MAC according to the link partner
2109  * @dev: Network device to be configured
2110  *
2111  * The function queries the PHY and checks if there is a link partner.
2112  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2113  * set to 10 MBit HD.
2114  *
2115  * The function returns 0 if there is no link partner and 1 if there is
2116  * a good link partner.
2117  */
2118 static int nv_update_linkspeed(struct net_device *dev)
2119 {
2120         struct fe_priv *np = netdev_priv(dev);
2121         u8 __iomem *base = get_hwbase(dev);
2122         int adv = 0;
2123         int lpa = 0;
2124         int adv_lpa, adv_pause, lpa_pause;
2125         int newls = np->linkspeed;
2126         int newdup = np->duplex;
2127         int mii_status;
2128         int retval = 0;
2129         u32 control_1000, status_1000, phyreg, pause_flags;
2130
2131         /* BMSR_LSTATUS is latched, read it twice:
2132          * we want the current value.
2133          */
2134         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2135         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2136
2137         if (!(mii_status & BMSR_LSTATUS)) {
2138                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2139                                 dev->name);
2140                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2141                 newdup = 0;
2142                 retval = 0;
2143                 goto set_speed;
2144         }
2145
2146         if (np->autoneg == 0) {
2147                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2148                                 dev->name, np->fixed_mode);
2149                 if (np->fixed_mode & LPA_100FULL) {
2150                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2151                         newdup = 1;
2152                 } else if (np->fixed_mode & LPA_100HALF) {
2153                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2154                         newdup = 0;
2155                 } else if (np->fixed_mode & LPA_10FULL) {
2156                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2157                         newdup = 1;
2158                 } else {
2159                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2160                         newdup = 0;
2161                 }
2162                 retval = 1;
2163                 goto set_speed;
2164         }
2165         /* check auto negotiation is complete */
2166         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2167                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2168                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2169                 newdup = 0;
2170                 retval = 0;
2171                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2172                 goto set_speed;
2173         }
2174
2175         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2176         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2177         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2178                                 dev->name, adv, lpa);
2179
2180         retval = 1;
2181         if (np->gigabit == PHY_GIGABIT) {
2182                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2183                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2184
2185                 if ((control_1000 & ADVERTISE_1000FULL) &&
2186                         (status_1000 & LPA_1000FULL)) {
2187                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2188                                 dev->name);
2189                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2190                         newdup = 1;
2191                         goto set_speed;
2192                 }
2193         }
2194
2195         /* FIXME: handle parallel detection properly */
2196         adv_lpa = lpa & adv;
2197         if (adv_lpa & LPA_100FULL) {
2198                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2199                 newdup = 1;
2200         } else if (adv_lpa & LPA_100HALF) {
2201                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2202                 newdup = 0;
2203         } else if (adv_lpa & LPA_10FULL) {
2204                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2205                 newdup = 1;
2206         } else if (adv_lpa & LPA_10HALF) {
2207                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2208                 newdup = 0;
2209         } else {
2210                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2211                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2212                 newdup = 0;
2213         }
2214
2215 set_speed:
2216         if (np->duplex == newdup && np->linkspeed == newls)
2217                 return retval;
2218
2219         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2220                         dev->name, np->linkspeed, np->duplex, newls, newdup);
2221
2222         np->duplex = newdup;
2223         np->linkspeed = newls;
2224
2225         if (np->gigabit == PHY_GIGABIT) {
2226                 phyreg = readl(base + NvRegRandomSeed);
2227                 phyreg &= ~(0x3FF00);
2228                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2229                         phyreg |= NVREG_RNDSEED_FORCE3;
2230                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2231                         phyreg |= NVREG_RNDSEED_FORCE2;
2232                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2233                         phyreg |= NVREG_RNDSEED_FORCE;
2234                 writel(phyreg, base + NvRegRandomSeed);
2235         }
2236
2237         phyreg = readl(base + NvRegPhyInterface);
2238         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2239         if (np->duplex == 0)
2240                 phyreg |= PHY_HALF;
2241         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2242                 phyreg |= PHY_100;
2243         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2244                 phyreg |= PHY_1000;
2245         writel(phyreg, base + NvRegPhyInterface);
2246
2247         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2248                 base + NvRegMisc1);
2249         pci_push(base);
2250         writel(np->linkspeed, base + NvRegLinkSpeed);
2251         pci_push(base);
2252
2253         pause_flags = 0;
2254         /* setup pause frame */
2255         if (np->duplex != 0) {
2256                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
2257                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
2258                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
2259
2260                         switch (adv_pause) {
2261                         case (ADVERTISE_PAUSE_CAP):
2262                                 if (lpa_pause & LPA_PAUSE_CAP) {
2263                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2264                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2265                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2266                                 }
2267                                 break;
2268                         case (ADVERTISE_PAUSE_ASYM):
2269                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
2270                                 {
2271                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2272                                 }
2273                                 break;
2274                         case (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM):
2275                                 if (lpa_pause & LPA_PAUSE_CAP)
2276                                 {
2277                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
2278                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2279                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2280                                 }
2281                                 if (lpa_pause == LPA_PAUSE_ASYM)
2282                                 {
2283                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2284                                 }
2285                                 break;
2286                         }
2287                 } else {
2288                         pause_flags = np->pause_flags;
2289                 }
2290         }
2291         nv_update_pause(dev, pause_flags);
2292
2293         return retval;
2294 }
2295
2296 static void nv_linkchange(struct net_device *dev)
2297 {
2298         if (nv_update_linkspeed(dev)) {
2299                 if (!netif_carrier_ok(dev)) {
2300                         netif_carrier_on(dev);
2301                         printk(KERN_INFO "%s: link up.\n", dev->name);
2302                         nv_start_rx(dev);
2303                 }
2304         } else {
2305                 if (netif_carrier_ok(dev)) {
2306                         netif_carrier_off(dev);
2307                         printk(KERN_INFO "%s: link down.\n", dev->name);
2308                         nv_stop_rx(dev);
2309                 }
2310         }
2311 }
2312
2313 static void nv_link_irq(struct net_device *dev)
2314 {
2315         u8 __iomem *base = get_hwbase(dev);
2316         u32 miistat;
2317
2318         miistat = readl(base + NvRegMIIStatus);
2319         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2320         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
2321
2322         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
2323                 nv_linkchange(dev);
2324         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
2325 }
2326
2327 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
2328 {
2329         struct net_device *dev = (struct net_device *) data;
2330         struct fe_priv *np = netdev_priv(dev);
2331         u8 __iomem *base = get_hwbase(dev);
2332         u32 events;
2333         int i;
2334
2335         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
2336
2337         for (i=0; ; i++) {
2338                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2339                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2340                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2341                 } else {
2342                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2343                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2344                 }
2345                 pci_push(base);
2346                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2347                 if (!(events & np->irqmask))
2348                         break;
2349
2350                 spin_lock(&np->lock);
2351                 nv_tx_done(dev);
2352                 spin_unlock(&np->lock);
2353
2354                 nv_rx_process(dev);
2355                 if (nv_alloc_rx(dev)) {
2356                         spin_lock(&np->lock);
2357                         if (!np->in_shutdown)
2358                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2359                         spin_unlock(&np->lock);
2360                 }
2361
2362                 if (events & NVREG_IRQ_LINK) {
2363                         spin_lock(&np->lock);
2364                         nv_link_irq(dev);
2365                         spin_unlock(&np->lock);
2366                 }
2367                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2368                         spin_lock(&np->lock);
2369                         nv_linkchange(dev);
2370                         spin_unlock(&np->lock);
2371                         np->link_timeout = jiffies + LINK_TIMEOUT;
2372                 }
2373                 if (events & (NVREG_IRQ_TX_ERR)) {
2374                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2375                                                 dev->name, events);
2376                 }
2377                 if (events & (NVREG_IRQ_UNKNOWN)) {
2378                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2379                                                 dev->name, events);
2380                 }
2381                 if (i > max_interrupt_work) {
2382                         spin_lock(&np->lock);
2383                         /* disable interrupts on the nic */
2384                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
2385                                 writel(0, base + NvRegIrqMask);
2386                         else
2387                                 writel(np->irqmask, base + NvRegIrqMask);
2388                         pci_push(base);
2389
2390                         if (!np->in_shutdown) {
2391                                 np->nic_poll_irq = np->irqmask;
2392                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2393                         }
2394                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
2395                         spin_unlock(&np->lock);
2396                         break;
2397                 }
2398
2399         }
2400         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
2401
2402         return IRQ_RETVAL(i);
2403 }
2404
2405 static irqreturn_t nv_nic_irq_tx(int foo, void *data, struct pt_regs *regs)
2406 {
2407         struct net_device *dev = (struct net_device *) data;
2408         struct fe_priv *np = netdev_priv(dev);
2409         u8 __iomem *base = get_hwbase(dev);
2410         u32 events;
2411         int i;
2412
2413         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
2414
2415         for (i=0; ; i++) {
2416                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
2417                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
2418                 pci_push(base);
2419                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
2420                 if (!(events & np->irqmask))
2421                         break;
2422
2423                 spin_lock_irq(&np->lock);
2424                 nv_tx_done(dev);
2425                 spin_unlock_irq(&np->lock);
2426
2427                 if (events & (NVREG_IRQ_TX_ERR)) {
2428                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2429                                                 dev->name, events);
2430                 }
2431                 if (i > max_interrupt_work) {
2432                         spin_lock_irq(&np->lock);
2433                         /* disable interrupts on the nic */
2434                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
2435                         pci_push(base);
2436
2437                         if (!np->in_shutdown) {
2438                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
2439                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2440                         }
2441                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
2442                         spin_unlock_irq(&np->lock);
2443                         break;
2444                 }
2445
2446         }
2447         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
2448
2449         return IRQ_RETVAL(i);
2450 }
2451
2452 static irqreturn_t nv_nic_irq_rx(int foo, void *data, struct pt_regs *regs)
2453 {
2454         struct net_device *dev = (struct net_device *) data;
2455         struct fe_priv *np = netdev_priv(dev);
2456         u8 __iomem *base = get_hwbase(dev);
2457         u32 events;
2458         int i;
2459
2460         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
2461
2462         for (i=0; ; i++) {
2463                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
2464                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
2465                 pci_push(base);
2466                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
2467                 if (!(events & np->irqmask))
2468                         break;
2469
2470                 nv_rx_process(dev);
2471                 if (nv_alloc_rx(dev)) {
2472                         spin_lock_irq(&np->lock);
2473                         if (!np->in_shutdown)
2474                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2475                         spin_unlock_irq(&np->lock);
2476                 }
2477
2478                 if (i > max_interrupt_work) {
2479                         spin_lock_irq(&np->lock);
2480                         /* disable interrupts on the nic */
2481                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2482                         pci_push(base);
2483
2484                         if (!np->in_shutdown) {
2485                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
2486                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2487                         }
2488                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
2489                         spin_unlock_irq(&np->lock);
2490                         break;
2491                 }
2492
2493         }
2494         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
2495
2496         return IRQ_RETVAL(i);
2497 }
2498
2499 static irqreturn_t nv_nic_irq_other(int foo, void *data, struct pt_regs *regs)
2500 {
2501         struct net_device *dev = (struct net_device *) data;
2502         struct fe_priv *np = netdev_priv(dev);
2503         u8 __iomem *base = get_hwbase(dev);
2504         u32 events;
2505         int i;
2506
2507         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
2508
2509         for (i=0; ; i++) {
2510                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
2511                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
2512                 pci_push(base);
2513                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2514                 if (!(events & np->irqmask))
2515                         break;
2516
2517                 if (events & NVREG_IRQ_LINK) {
2518                         spin_lock_irq(&np->lock);
2519                         nv_link_irq(dev);
2520                         spin_unlock_irq(&np->lock);
2521                 }
2522                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2523                         spin_lock_irq(&np->lock);
2524                         nv_linkchange(dev);
2525                         spin_unlock_irq(&np->lock);
2526                         np->link_timeout = jiffies + LINK_TIMEOUT;
2527                 }
2528                 if (events & (NVREG_IRQ_UNKNOWN)) {
2529                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2530                                                 dev->name, events);
2531                 }
2532                 if (i > max_interrupt_work) {
2533                         spin_lock_irq(&np->lock);
2534                         /* disable interrupts on the nic */
2535                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
2536                         pci_push(base);
2537
2538                         if (!np->in_shutdown) {
2539                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
2540                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2541                         }
2542                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
2543                         spin_unlock_irq(&np->lock);
2544                         break;
2545                 }
2546
2547         }
2548         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
2549
2550         return IRQ_RETVAL(i);
2551 }
2552
2553 static irqreturn_t nv_nic_irq_test(int foo, void *data, struct pt_regs *regs)
2554 {
2555         struct net_device *dev = (struct net_device *) data;
2556         struct fe_priv *np = netdev_priv(dev);
2557         u8 __iomem *base = get_hwbase(dev);
2558         u32 events;
2559
2560         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
2561
2562         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2563                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2564                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
2565         } else {
2566                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2567                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
2568         }
2569         pci_push(base);
2570         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2571         if (!(events & NVREG_IRQ_TIMER))
2572                 return IRQ_RETVAL(0);
2573
2574         spin_lock(&np->lock);
2575         np->intr_test = 1;
2576         spin_unlock(&np->lock);
2577
2578         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
2579
2580         return IRQ_RETVAL(1);
2581 }
2582
2583 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
2584 {
2585         u8 __iomem *base = get_hwbase(dev);
2586         int i;
2587         u32 msixmap = 0;
2588
2589         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
2590          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
2591          * the remaining 8 interrupts.
2592          */
2593         for (i = 0; i < 8; i++) {
2594                 if ((irqmask >> i) & 0x1) {
2595                         msixmap |= vector << (i << 2);
2596                 }
2597         }
2598         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
2599
2600         msixmap = 0;
2601         for (i = 0; i < 8; i++) {
2602                 if ((irqmask >> (i + 8)) & 0x1) {
2603                         msixmap |= vector << (i << 2);
2604                 }
2605         }
2606         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
2607 }
2608
2609 static int nv_request_irq(struct net_device *dev, int intr_test)
2610 {
2611         struct fe_priv *np = get_nvpriv(dev);
2612         u8 __iomem *base = get_hwbase(dev);
2613         int ret = 1;
2614         int i;
2615
2616         if (np->msi_flags & NV_MSI_X_CAPABLE) {
2617                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2618                         np->msi_x_entry[i].entry = i;
2619                 }
2620                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
2621                         np->msi_flags |= NV_MSI_X_ENABLED;
2622                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
2623                                 /* Request irq for rx handling */
2624                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, SA_SHIRQ, dev->name, dev) != 0) {
2625                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
2626                                         pci_disable_msix(np->pci_dev);
2627                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2628                                         goto out_err;
2629                                 }
2630                                 /* Request irq for tx handling */
2631                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, SA_SHIRQ, dev->name, dev) != 0) {
2632                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
2633                                         pci_disable_msix(np->pci_dev);
2634                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2635                                         goto out_free_rx;
2636                                 }
2637                                 /* Request irq for link and timer handling */
2638                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, SA_SHIRQ, dev->name, dev) != 0) {
2639                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
2640                                         pci_disable_msix(np->pci_dev);
2641                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2642                                         goto out_free_tx;
2643                                 }
2644                                 /* map interrupts to their respective vector */
2645                                 writel(0, base + NvRegMSIXMap0);
2646                                 writel(0, base + NvRegMSIXMap1);
2647                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
2648                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
2649                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
2650                         } else {
2651                                 /* Request irq for all interrupts */
2652                                 if ((!intr_test &&
2653                                      request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) ||
2654                                     (intr_test &&
2655                                      request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq_test, SA_SHIRQ, dev->name, dev) != 0)) {
2656                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2657                                         pci_disable_msix(np->pci_dev);
2658                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2659                                         goto out_err;
2660                                 }
2661
2662                                 /* map interrupts to vector 0 */
2663                                 writel(0, base + NvRegMSIXMap0);
2664                                 writel(0, base + NvRegMSIXMap1);
2665                         }
2666                 }
2667         }
2668         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
2669                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
2670                         np->msi_flags |= NV_MSI_ENABLED;
2671                         if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) ||
2672                             (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, SA_SHIRQ, dev->name, dev) != 0)) {
2673                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2674                                 pci_disable_msi(np->pci_dev);
2675                                 np->msi_flags &= ~NV_MSI_ENABLED;
2676                                 goto out_err;
2677                         }
2678
2679                         /* map interrupts to vector 0 */
2680                         writel(0, base + NvRegMSIMap0);
2681                         writel(0, base + NvRegMSIMap1);
2682                         /* enable msi vector 0 */
2683                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
2684                 }
2685         }
2686         if (ret != 0) {
2687                 if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) ||
2688                     (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, SA_SHIRQ, dev->name, dev) != 0))
2689                         goto out_err;
2690
2691         }
2692
2693         return 0;
2694 out_free_tx:
2695         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
2696 out_free_rx:
2697         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
2698 out_err:
2699         return 1;
2700 }
2701
2702 static void nv_free_irq(struct net_device *dev)
2703 {
2704         struct fe_priv *np = get_nvpriv(dev);
2705         int i;
2706
2707         if (np->msi_flags & NV_MSI_X_ENABLED) {
2708                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2709                         free_irq(np->msi_x_entry[i].vector, dev);
2710                 }
2711                 pci_disable_msix(np->pci_dev);
2712                 np->msi_flags &= ~NV_MSI_X_ENABLED;
2713         } else {
2714                 free_irq(np->pci_dev->irq, dev);
2715                 if (np->msi_flags & NV_MSI_ENABLED) {
2716                         pci_disable_msi(np->pci_dev);
2717                         np->msi_flags &= ~NV_MSI_ENABLED;
2718                 }
2719         }
2720 }
2721
2722 static void nv_do_nic_poll(unsigned long data)
2723 {
2724         struct net_device *dev = (struct net_device *) data;
2725         struct fe_priv *np = netdev_priv(dev);
2726         u8 __iomem *base = get_hwbase(dev);
2727         u32 mask = 0;
2728
2729         /*
2730          * First disable irq(s) and then
2731          * reenable interrupts on the nic, we have to do this before calling
2732          * nv_nic_irq because that may decide to do otherwise
2733          */
2734
2735         if (!using_multi_irqs(dev)) {
2736                 if (np->msi_flags & NV_MSI_X_ENABLED)
2737                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2738                 else
2739                         disable_irq(dev->irq);
2740                 mask = np->irqmask;
2741         } else {
2742                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
2743                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
2744                         mask |= NVREG_IRQ_RX_ALL;
2745                 }
2746                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
2747                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
2748                         mask |= NVREG_IRQ_TX_ALL;
2749                 }
2750                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
2751                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
2752                         mask |= NVREG_IRQ_OTHER;
2753                 }
2754         }
2755         np->nic_poll_irq = 0;
2756
2757         /* FIXME: Do we need synchronize_irq(dev->irq) here? */
2758
2759         writel(mask, base + NvRegIrqMask);
2760         pci_push(base);
2761
2762         if (!using_multi_irqs(dev)) {
2763                 nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL);
2764                 if (np->msi_flags & NV_MSI_X_ENABLED)
2765                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2766                 else
2767                         enable_irq(dev->irq);
2768         } else {
2769                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
2770                         nv_nic_irq_rx((int) 0, (void *) data, (struct pt_regs *) NULL);
2771                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
2772                 }
2773                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
2774                         nv_nic_irq_tx((int) 0, (void *) data, (struct pt_regs *) NULL);
2775                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
2776                 }
2777                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
2778                         nv_nic_irq_other((int) 0, (void *) data, (struct pt_regs *) NULL);
2779                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
2780                 }
2781         }
2782 }
2783
2784 #ifdef CONFIG_NET_POLL_CONTROLLER
2785 static void nv_poll_controller(struct net_device *dev)
2786 {
2787         nv_do_nic_poll((unsigned long) dev);
2788 }
2789 #endif
2790
2791 static void nv_do_stats_poll(unsigned long data)
2792 {
2793         struct net_device *dev = (struct net_device *) data;
2794         struct fe_priv *np = netdev_priv(dev);
2795         u8 __iomem *base = get_hwbase(dev);
2796
2797         np->estats.tx_bytes += readl(base + NvRegTxCnt);
2798         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
2799         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
2800         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
2801         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
2802         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
2803         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
2804         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
2805         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
2806         np->estats.tx_deferral += readl(base + NvRegTxDef);
2807         np->estats.tx_packets += readl(base + NvRegTxFrame);
2808         np->estats.tx_pause += readl(base + NvRegTxPause);
2809         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
2810         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
2811         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
2812         np->estats.rx_runt += readl(base + NvRegRxRunt);
2813         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
2814         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
2815         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
2816         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
2817         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
2818         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
2819         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
2820         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
2821         np->estats.rx_bytes += readl(base + NvRegRxCnt);
2822         np->estats.rx_pause += readl(base + NvRegRxPause);
2823         np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
2824         np->estats.rx_packets =
2825                 np->estats.rx_unicast +
2826                 np->estats.rx_multicast +
2827                 np->estats.rx_broadcast;
2828         np->estats.rx_errors_total =
2829                 np->estats.rx_crc_errors +
2830                 np->estats.rx_over_errors +
2831                 np->estats.rx_frame_error +
2832                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
2833                 np->estats.rx_late_collision +
2834                 np->estats.rx_runt +
2835                 np->estats.rx_frame_too_long;
2836
2837         if (!np->in_shutdown)
2838                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
2839 }
2840
2841 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2842 {
2843         struct fe_priv *np = netdev_priv(dev);
2844         strcpy(info->driver, "forcedeth");
2845         strcpy(info->version, FORCEDETH_VERSION);
2846         strcpy(info->bus_info, pci_name(np->pci_dev));
2847 }
2848
2849 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
2850 {
2851         struct fe_priv *np = netdev_priv(dev);
2852         wolinfo->supported = WAKE_MAGIC;
2853
2854         spin_lock_irq(&np->lock);
2855         if (np->wolenabled)
2856                 wolinfo->wolopts = WAKE_MAGIC;
2857         spin_unlock_irq(&np->lock);
2858 }
2859
2860 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
2861 {
2862         struct fe_priv *np = netdev_priv(dev);
2863         u8 __iomem *base = get_hwbase(dev);
2864         u32 flags = 0;
2865
2866         if (wolinfo->wolopts == 0) {
2867                 np->wolenabled = 0;
2868         } else if (wolinfo->wolopts & WAKE_MAGIC) {
2869                 np->wolenabled = 1;
2870                 flags = NVREG_WAKEUPFLAGS_ENABLE;
2871         }
2872         if (netif_running(dev)) {
2873                 spin_lock_irq(&np->lock);
2874                 writel(flags, base + NvRegWakeUpFlags);
2875                 spin_unlock_irq(&np->lock);
2876         }
2877         return 0;
2878 }
2879
2880 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2881 {
2882         struct fe_priv *np = netdev_priv(dev);
2883         int adv;
2884
2885         spin_lock_irq(&np->lock);
2886         ecmd->port = PORT_MII;
2887         if (!netif_running(dev)) {
2888                 /* We do not track link speed / duplex setting if the
2889                  * interface is disabled. Force a link check */
2890                 if (nv_update_linkspeed(dev)) {
2891                         if (!netif_carrier_ok(dev))
2892                                 netif_carrier_on(dev);
2893                 } else {
2894                         if (netif_carrier_ok(dev))
2895                                 netif_carrier_off(dev);
2896                 }
2897         }
2898
2899         if (netif_carrier_ok(dev)) {
2900                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
2901                 case NVREG_LINKSPEED_10:
2902                         ecmd->speed = SPEED_10;
2903                         break;
2904                 case NVREG_LINKSPEED_100:
2905                         ecmd->speed = SPEED_100;
2906                         break;
2907                 case NVREG_LINKSPEED_1000:
2908                         ecmd->speed = SPEED_1000;
2909                         break;
2910                 }
2911                 ecmd->duplex = DUPLEX_HALF;
2912                 if (np->duplex)
2913                         ecmd->duplex = DUPLEX_FULL;
2914         } else {
2915                 ecmd->speed = -1;
2916                 ecmd->duplex = -1;
2917         }
2918
2919         ecmd->autoneg = np->autoneg;
2920
2921         ecmd->advertising = ADVERTISED_MII;
2922         if (np->autoneg) {
2923                 ecmd->advertising |= ADVERTISED_Autoneg;
2924                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2925                 if (adv & ADVERTISE_10HALF)
2926                         ecmd->advertising |= ADVERTISED_10baseT_Half;
2927                 if (adv & ADVERTISE_10FULL)
2928                         ecmd->advertising |= ADVERTISED_10baseT_Full;
2929                 if (adv & ADVERTISE_100HALF)
2930                         ecmd->advertising |= ADVERTISED_100baseT_Half;
2931                 if (adv & ADVERTISE_100FULL)
2932                         ecmd->advertising |= ADVERTISED_100baseT_Full;
2933                 if (np->gigabit == PHY_GIGABIT) {
2934                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2935                         if (adv & ADVERTISE_1000FULL)
2936                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
2937                 }
2938         }
2939         ecmd->supported = (SUPPORTED_Autoneg |
2940                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2941                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2942                 SUPPORTED_MII);
2943         if (np->gigabit == PHY_GIGABIT)
2944                 ecmd->supported |= SUPPORTED_1000baseT_Full;
2945
2946         ecmd->phy_address = np->phyaddr;
2947         ecmd->transceiver = XCVR_EXTERNAL;
2948
2949         /* ignore maxtxpkt, maxrxpkt for now */
2950         spin_unlock_irq(&np->lock);
2951         return 0;
2952 }
2953
2954 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2955 {
2956         struct fe_priv *np = netdev_priv(dev);
2957
2958         if (ecmd->port != PORT_MII)
2959                 return -EINVAL;
2960         if (ecmd->transceiver != XCVR_EXTERNAL)
2961                 return -EINVAL;
2962         if (ecmd->phy_address != np->phyaddr) {
2963                 /* TODO: support switching between multiple phys. Should be
2964                  * trivial, but not enabled due to lack of test hardware. */
2965                 return -EINVAL;
2966         }
2967         if (ecmd->autoneg == AUTONEG_ENABLE) {
2968                 u32 mask;
2969
2970                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2971                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
2972                 if (np->gigabit == PHY_GIGABIT)
2973                         mask |= ADVERTISED_1000baseT_Full;
2974
2975                 if ((ecmd->advertising & mask) == 0)
2976                         return -EINVAL;
2977
2978         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2979                 /* Note: autonegotiation disable, speed 1000 intentionally
2980                  * forbidden - noone should need that. */
2981
2982                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
2983                         return -EINVAL;
2984                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2985                         return -EINVAL;
2986         } else {
2987                 return -EINVAL;
2988         }
2989
2990         netif_carrier_off(dev);
2991         if (netif_running(dev)) {
2992                 nv_disable_irq(dev);
2993                 spin_lock_bh(&dev->xmit_lock);
2994                 spin_lock(&np->lock);
2995                 /* stop engines */
2996                 nv_stop_rx(dev);
2997                 nv_stop_tx(dev);
2998                 spin_unlock(&np->lock);
2999                 spin_unlock_bh(&dev->xmit_lock);
3000         }
3001
3002         if (ecmd->autoneg == AUTONEG_ENABLE) {
3003                 int adv, bmcr;
3004
3005                 np->autoneg = 1;
3006
3007                 /* advertise only what has been requested */
3008                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3009                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3010                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
3011                         adv |= ADVERTISE_10HALF;
3012                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
3013                         adv |= ADVERTISE_10FULL;
3014                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
3015                         adv |= ADVERTISE_100HALF;
3016                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
3017                         adv |= ADVERTISE_100FULL;
3018                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
3019                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3020                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3021                         adv |=  ADVERTISE_PAUSE_ASYM;
3022                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3023
3024                 if (np->gigabit == PHY_GIGABIT) {
3025                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3026                         adv &= ~ADVERTISE_1000FULL;
3027                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
3028                                 adv |= ADVERTISE_1000FULL;
3029                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3030                 }
3031
3032                 if (netif_running(dev))
3033                         printk(KERN_INFO "%s: link down.\n", dev->name);
3034                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3035                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3036                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3037
3038         } else {
3039                 int adv, bmcr;
3040
3041                 np->autoneg = 0;
3042
3043                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3044                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3045                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
3046                         adv |= ADVERTISE_10HALF;
3047                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
3048                         adv |= ADVERTISE_10FULL;
3049                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
3050                         adv |= ADVERTISE_100HALF;
3051                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
3052                         adv |= ADVERTISE_100FULL;
3053                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3054                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
3055                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3056                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3057                 }
3058                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
3059                         adv |=  ADVERTISE_PAUSE_ASYM;
3060                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3061                 }
3062                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3063                 np->fixed_mode = adv;
3064
3065                 if (np->gigabit == PHY_GIGABIT) {
3066                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3067                         adv &= ~ADVERTISE_1000FULL;
3068                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3069                 }
3070
3071                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3072                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
3073                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
3074                         bmcr |= BMCR_FULLDPLX;
3075                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
3076                         bmcr |= BMCR_SPEED100;
3077                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3078                 if (np->phy_oui == PHY_OUI_MARVELL) {
3079                         /* reset the phy */
3080                         if (phy_reset(dev)) {
3081                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3082                                 return -EINVAL;
3083                         }
3084                 } else if (netif_running(dev)) {
3085                         /* Wait a bit and then reconfigure the nic. */
3086                         udelay(10);
3087                         nv_linkchange(dev);
3088                 }
3089         }
3090
3091         if (netif_running(dev)) {
3092                 nv_start_rx(dev);
3093                 nv_start_tx(dev);
3094                 nv_enable_irq(dev);
3095         }
3096
3097         return 0;
3098 }
3099
3100 #define FORCEDETH_REGS_VER      1
3101
3102 static int nv_get_regs_len(struct net_device *dev)
3103 {
3104         struct fe_priv *np = netdev_priv(dev);
3105         return np->register_size;
3106 }
3107
3108 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
3109 {
3110         struct fe_priv *np = netdev_priv(dev);
3111         u8 __iomem *base = get_hwbase(dev);
3112         u32 *rbuf = buf;
3113         int i;
3114
3115         regs->version = FORCEDETH_REGS_VER;
3116         spin_lock_irq(&np->lock);
3117         for (i = 0;i <= np->register_size/sizeof(u32); i++)
3118                 rbuf[i] = readl(base + i*sizeof(u32));
3119         spin_unlock_irq(&np->lock);
3120 }
3121
3122 static int nv_nway_reset(struct net_device *dev)
3123 {
3124         struct fe_priv *np = netdev_priv(dev);
3125         int ret;
3126
3127         if (np->autoneg) {
3128                 int bmcr;
3129
3130                 netif_carrier_off(dev);
3131                 if (netif_running(dev)) {
3132                         nv_disable_irq(dev);
3133                         spin_lock_bh(&dev->xmit_lock);
3134                         spin_lock(&np->lock);
3135                         /* stop engines */
3136                         nv_stop_rx(dev);
3137                         nv_stop_tx(dev);
3138                         spin_unlock(&np->lock);
3139                         spin_unlock_bh(&dev->xmit_lock);
3140                         printk(KERN_INFO "%s: link down.\n", dev->name);
3141                 }
3142
3143                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3144                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3145                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3146
3147                 if (netif_running(dev)) {
3148                         nv_start_rx(dev);
3149                         nv_start_tx(dev);
3150                         nv_enable_irq(dev);
3151                 }
3152                 ret = 0;
3153         } else {
3154                 ret = -EINVAL;
3155         }
3156
3157         return ret;
3158 }
3159
3160 static int nv_set_tso(struct net_device *dev, u32 value)
3161 {
3162         struct fe_priv *np = netdev_priv(dev);
3163
3164         if ((np->driver_data & DEV_HAS_CHECKSUM))
3165                 return ethtool_op_set_tso(dev, value);
3166         else
3167                 return -EOPNOTSUPP;
3168 }
3169
3170 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3171 {
3172         struct fe_priv *np = netdev_priv(dev);
3173
3174         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3175         ring->rx_mini_max_pending = 0;
3176         ring->rx_jumbo_max_pending = 0;
3177         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3178
3179         ring->rx_pending = np->rx_ring_size;
3180         ring->rx_mini_pending = 0;
3181         ring->rx_jumbo_pending = 0;
3182         ring->tx_pending = np->tx_ring_size;
3183 }
3184
3185 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3186 {
3187         struct fe_priv *np = netdev_priv(dev);
3188         u8 __iomem *base = get_hwbase(dev);
3189         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff, *rx_dma, *tx_dma, *tx_dma_len;
3190         dma_addr_t ring_addr;
3191
3192         if (ring->rx_pending < RX_RING_MIN ||
3193             ring->tx_pending < TX_RING_MIN ||
3194             ring->rx_mini_pending != 0 ||
3195             ring->rx_jumbo_pending != 0 ||
3196             (np->desc_ver == DESC_VER_1 &&
3197              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
3198               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
3199             (np->desc_ver != DESC_VER_1 &&
3200              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
3201               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
3202                 return -EINVAL;
3203         }
3204
3205         /* allocate new rings */
3206         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3207                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3208                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3209                                             &ring_addr);
3210         } else {
3211                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3212                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3213                                             &ring_addr);
3214         }
3215         rx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->rx_pending, GFP_KERNEL);
3216         rx_dma = kmalloc(sizeof(dma_addr_t) * ring->rx_pending, GFP_KERNEL);
3217         tx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->tx_pending, GFP_KERNEL);
3218         tx_dma = kmalloc(sizeof(dma_addr_t) * ring->tx_pending, GFP_KERNEL);
3219         tx_dma_len = kmalloc(sizeof(unsigned int) * ring->tx_pending, GFP_KERNEL);
3220         if (!rxtx_ring || !rx_skbuff || !rx_dma || !tx_skbuff || !tx_dma || !tx_dma_len) {
3221                 /* fall back to old rings */
3222                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3223                         if(rxtx_ring)
3224                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3225                                                     rxtx_ring, ring_addr);
3226                 } else {
3227                         if (rxtx_ring)
3228                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3229                                                     rxtx_ring, ring_addr);
3230                 }
3231                 if (rx_skbuff)
3232                         kfree(rx_skbuff);
3233                 if (rx_dma)
3234                         kfree(rx_dma);
3235                 if (tx_skbuff)
3236                         kfree(tx_skbuff);
3237                 if (tx_dma)
3238                         kfree(tx_dma);
3239                 if (tx_dma_len)
3240                         kfree(tx_dma_len);
3241                 goto exit;
3242         }
3243
3244         if (netif_running(dev)) {
3245                 nv_disable_irq(dev);
3246                 spin_lock_bh(&dev->xmit_lock);
3247                 spin_lock(&np->lock);
3248                 /* stop engines */
3249                 nv_stop_rx(dev);
3250                 nv_stop_tx(dev);
3251                 nv_txrx_reset(dev);
3252                 /* drain queues */
3253                 nv_drain_rx(dev);
3254                 nv_drain_tx(dev);
3255                 /* delete queues */
3256                 free_rings(dev);
3257         }
3258
3259         /* set new values */
3260         np->rx_ring_size = ring->rx_pending;
3261         np->tx_ring_size = ring->tx_pending;
3262         np->tx_limit_stop = ring->tx_pending - TX_LIMIT_DIFFERENCE;
3263         np->tx_limit_start = ring->tx_pending - TX_LIMIT_DIFFERENCE - 1;
3264         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3265                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
3266                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
3267         } else {
3268                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
3269                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
3270         }
3271         np->rx_skbuff = (struct sk_buff**)rx_skbuff;
3272         np->rx_dma = (dma_addr_t*)rx_dma;
3273         np->tx_skbuff = (struct sk_buff**)tx_skbuff;
3274         np->tx_dma = (dma_addr_t*)tx_dma;
3275         np->tx_dma_len = (unsigned int*)tx_dma_len;
3276         np->ring_addr = ring_addr;
3277
3278         memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
3279         memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
3280         memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
3281         memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
3282         memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
3283
3284         if (netif_running(dev)) {
3285                 /* reinit driver view of the queues */
3286                 set_bufsize(dev);
3287                 if (nv_init_ring(dev)) {
3288                         if (!np->in_shutdown)
3289                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3290                 }
3291
3292                 /* reinit nic view of the queues */
3293                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3294                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3295                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3296                         base + NvRegRingSizes);
3297                 pci_push(base);
3298                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3299                 pci_push(base);
3300
3301                 /* restart engines */
3302                 nv_start_rx(dev);
3303                 nv_start_tx(dev);
3304                 spin_unlock(&np->lock);
3305                 spin_unlock_bh(&dev->xmit_lock);
3306                 nv_enable_irq(dev);
3307         }
3308         return 0;
3309 exit:
3310         return -ENOMEM;
3311 }
3312
3313 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3314 {
3315         struct fe_priv *np = netdev_priv(dev);
3316
3317         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
3318         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
3319         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
3320 }
3321
3322 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3323 {
3324         struct fe_priv *np = netdev_priv(dev);
3325         int adv, bmcr;
3326
3327         if ((!np->autoneg && np->duplex == 0) ||
3328             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
3329                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
3330                        dev->name);
3331                 return -EINVAL;
3332         }
3333         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
3334                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
3335                 return -EINVAL;
3336         }
3337
3338         netif_carrier_off(dev);
3339         if (netif_running(dev)) {
3340                 nv_disable_irq(dev);
3341                 spin_lock_bh(&dev->xmit_lock);
3342                 spin_lock(&np->lock);
3343                 /* stop engines */
3344                 nv_stop_rx(dev);
3345                 nv_stop_tx(dev);
3346                 spin_unlock(&np->lock);
3347                 spin_unlock_bh(&dev->xmit_lock);
3348         }
3349
3350         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
3351         if (pause->rx_pause)
3352                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
3353         if (pause->tx_pause)
3354                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
3355
3356         if (np->autoneg && pause->autoneg) {
3357                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
3358
3359                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3360                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3361                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
3362                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3363                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3364                         adv |=  ADVERTISE_PAUSE_ASYM;
3365                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3366
3367                 if (netif_running(dev))
3368                         printk(KERN_INFO "%s: link down.\n", dev->name);
3369                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3370                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3371                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3372         } else {
3373                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3374                 if (pause->rx_pause)
3375                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3376                 if (pause->tx_pause)
3377                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3378
3379                 if (!netif_running(dev))
3380                         nv_update_linkspeed(dev);
3381                 else
3382                         nv_update_pause(dev, np->pause_flags);
3383         }
3384
3385         if (netif_running(dev)) {
3386                 nv_start_rx(dev);
3387                 nv_start_tx(dev);
3388                 nv_enable_irq(dev);
3389         }
3390         return 0;
3391 }
3392
3393 static u32 nv_get_rx_csum(struct net_device *dev)
3394 {
3395         struct fe_priv *np = netdev_priv(dev);
3396         return (np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) != 0;
3397 }
3398
3399 static int nv_set_rx_csum(struct net_device *dev, u32 data)
3400 {
3401         struct fe_priv *np = netdev_priv(dev);
3402         u8 __iomem *base = get_hwbase(dev);
3403         int retcode = 0;
3404
3405         if (np->driver_data & DEV_HAS_CHECKSUM) {
3406
3407                 if (((np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) && data) ||
3408                     (!(np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) && !data)) {
3409                         /* already set or unset */
3410                         return 0;
3411                 }
3412
3413                 if (data) {
3414                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
3415                 } else if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE)) {
3416                         np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
3417                 } else {
3418                         printk(KERN_INFO "Can not disable rx checksum if vlan is enabled\n");
3419                         return -EINVAL;
3420                 }
3421
3422                 if (netif_running(dev)) {
3423                         spin_lock_irq(&np->lock);
3424                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
3425                         spin_unlock_irq(&np->lock);
3426                 }
3427         } else {
3428                 return -EINVAL;
3429         }
3430
3431         return retcode;
3432 }
3433
3434 static int nv_set_tx_csum(struct net_device *dev, u32 data)
3435 {
3436         struct fe_priv *np = netdev_priv(dev);
3437
3438         if (np->driver_data & DEV_HAS_CHECKSUM)
3439                 return ethtool_op_set_tx_hw_csum(dev, data);
3440         else
3441                 return -EOPNOTSUPP;
3442 }
3443
3444 static int nv_set_sg(struct net_device *dev, u32 data)
3445 {
3446         struct fe_priv *np = netdev_priv(dev);
3447
3448         if (np->driver_data & DEV_HAS_CHECKSUM)
3449                 return ethtool_op_set_sg(dev, data);
3450         else
3451                 return -EOPNOTSUPP;
3452 }
3453
3454 static int nv_get_stats_count(struct net_device *dev)
3455 {
3456         struct fe_priv *np = netdev_priv(dev);
3457
3458         if (np->driver_data & DEV_HAS_STATISTICS)
3459                 return (sizeof(struct nv_ethtool_stats)/sizeof(u64));
3460         else
3461                 return 0;
3462 }
3463
3464 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
3465 {
3466         struct fe_priv *np = netdev_priv(dev);
3467
3468         /* update stats */
3469         nv_do_stats_poll((unsigned long)dev);
3470
3471         memcpy(buffer, &np->estats, nv_get_stats_count(dev)*sizeof(u64));
3472 }
3473
3474 static int nv_self_test_count(struct net_device *dev)
3475 {
3476         struct fe_priv *np = netdev_priv(dev);
3477
3478         if (np->driver_data & DEV_HAS_TEST_EXTENDED)
3479                 return NV_TEST_COUNT_EXTENDED;
3480         else
3481                 return NV_TEST_COUNT_BASE;
3482 }
3483
3484 static int nv_link_test(struct net_device *dev)
3485 {
3486         struct fe_priv *np = netdev_priv(dev);
3487         int mii_status;
3488
3489         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3490         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3491
3492         /* check phy link status */
3493         if (!(mii_status & BMSR_LSTATUS))
3494                 return 0;
3495         else
3496                 return 1;
3497 }
3498
3499 static int nv_register_test(struct net_device *dev)
3500 {
3501         u8 __iomem *base = get_hwbase(dev);
3502         int i = 0;
3503         u32 orig_read, new_read;
3504
3505         do {
3506                 orig_read = readl(base + nv_registers_test[i].reg);
3507
3508                 /* xor with mask to toggle bits */
3509                 orig_read ^= nv_registers_test[i].mask;
3510
3511                 writel(orig_read, base + nv_registers_test[i].reg);
3512
3513                 new_read = readl(base + nv_registers_test[i].reg);
3514
3515                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
3516                         return 0;
3517
3518                 /* restore original value */
3519                 orig_read ^= nv_registers_test[i].mask;
3520                 writel(orig_read, base + nv_registers_test[i].reg);
3521
3522         } while (nv_registers_test[++i].reg != 0);
3523
3524         return 1;
3525 }
3526
3527 static int nv_interrupt_test(struct net_device *dev)
3528 {
3529         struct fe_priv *np = netdev_priv(dev);
3530         u8 __iomem *base = get_hwbase(dev);
3531         int ret = 1;
3532         int testcnt;
3533         u32 save_msi_flags, save_poll_interval = 0;
3534
3535         if (netif_running(dev)) {
3536                 /* free current irq */
3537                 nv_free_irq(dev);
3538                 save_poll_interval = readl(base+NvRegPollingInterval);
3539         }
3540
3541         /* flag to test interrupt handler */
3542         np->intr_test = 0;
3543
3544         /* setup test irq */
3545         save_msi_flags = np->msi_flags;
3546         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
3547         np->msi_flags |= 0x001; /* setup 1 vector */
3548         if (nv_request_irq(dev, 1))
3549                 return 0;
3550
3551         /* setup timer interrupt */
3552         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
3553         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3554
3555         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
3556
3557         /* wait for at least one interrupt */
3558         msleep(100);
3559
3560         spin_lock_irq(&np->lock);
3561
3562         /* flag should be set within ISR */
3563         testcnt = np->intr_test;
3564         if (!testcnt)
3565                 ret = 2;
3566
3567         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
3568         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3569                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3570         else
3571                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3572
3573         spin_unlock_irq(&np->lock);
3574
3575         nv_free_irq(dev);
3576
3577         np->msi_flags = save_msi_flags;
3578
3579         if (netif_running(dev)) {
3580                 writel(save_poll_interval, base + NvRegPollingInterval);
3581                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3582                 /* restore original irq */
3583                 if (nv_request_irq(dev, 0))
3584                         return 0;
3585         }
3586
3587         return ret;
3588 }
3589
3590 static int nv_loopback_test(struct net_device *dev)
3591 {
3592         struct fe_priv *np = netdev_priv(dev);
3593         u8 __iomem *base = get_hwbase(dev);
3594         struct sk_buff *tx_skb, *rx_skb;
3595         dma_addr_t test_dma_addr;
3596         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
3597         u32 Flags;
3598         int len, i, pkt_len;
3599         u8 *pkt_data;
3600         u32 filter_flags = 0;
3601         u32 misc1_flags = 0;
3602         int ret = 1;
3603
3604         if (netif_running(dev)) {
3605                 nv_disable_irq(dev);
3606                 filter_flags = readl(base + NvRegPacketFilterFlags);
3607                 misc1_flags = readl(base + NvRegMisc1);
3608         } else {
3609                 nv_txrx_reset(dev);
3610         }
3611
3612         /* reinit driver view of the rx queue */
3613         set_bufsize(dev);
3614         nv_init_ring(dev);
3615
3616         /* setup hardware for loopback */
3617         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
3618         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
3619
3620         /* reinit nic view of the rx queue */
3621         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3622         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3623         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3624                 base + NvRegRingSizes);
3625         pci_push(base);
3626
3627         /* restart rx engine */
3628         nv_start_rx(dev);
3629         nv_start_tx(dev);
3630
3631         /* setup packet for tx */
3632         pkt_len = ETH_DATA_LEN;
3633         tx_skb = dev_alloc_skb(pkt_len);
3634         pkt_data = skb_put(tx_skb, pkt_len);
3635         for (i = 0; i < pkt_len; i++)
3636                 pkt_data[i] = (u8)(i & 0xff);
3637         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
3638                                        tx_skb->end-tx_skb->data, PCI_DMA_FROMDEVICE);
3639
3640         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3641                 np->tx_ring.orig[0].PacketBuffer = cpu_to_le32(test_dma_addr);
3642                 np->tx_ring.orig[0].FlagLen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
3643         } else {
3644                 np->tx_ring.ex[0].PacketBufferHigh = cpu_to_le64(test_dma_addr) >> 32;
3645                 np->tx_ring.ex[0].PacketBufferLow = cpu_to_le64(test_dma_addr) & 0x0FFFFFFFF;
3646                 np->tx_ring.ex[0].FlagLen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
3647         }
3648         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3649         pci_push(get_hwbase(dev));
3650
3651         msleep(500);
3652
3653         /* check for rx of the packet */
3654         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3655                 Flags = le32_to_cpu(np->rx_ring.orig[0].FlagLen);
3656                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
3657
3658         } else {
3659                 Flags = le32_to_cpu(np->rx_ring.ex[0].FlagLen);
3660                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
3661         }
3662
3663         if (Flags & NV_RX_AVAIL) {
3664                 ret = 0;
3665         } else if (np->desc_ver == DESC_VER_1) {
3666                 if (Flags & NV_RX_ERROR)
3667                         ret = 0;
3668         } else {
3669                 if (Flags & NV_RX2_ERROR) {
3670                         ret = 0;
3671                 }
3672         }
3673
3674         if (ret) {
3675                 if (len != pkt_len) {
3676                         ret = 0;
3677                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
3678                                 dev->name, len, pkt_len);
3679                 } else {
3680                         rx_skb = np->rx_skbuff[0];
3681                         for (i = 0; i < pkt_len; i++) {
3682                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
3683                                         ret = 0;
3684                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
3685                                                 dev->name, i);
3686                                         break;
3687                                 }
3688                         }
3689                 }
3690         } else {
3691                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
3692         }
3693
3694         pci_unmap_page(np->pci_dev, test_dma_addr,
3695                        tx_skb->end-tx_skb->data,
3696                        PCI_DMA_TODEVICE);
3697         dev_kfree_skb_any(tx_skb);
3698
3699         /* stop engines */
3700         nv_stop_rx(dev);
3701         nv_stop_tx(dev);
3702         nv_txrx_reset(dev);
3703         /* drain rx queue */
3704         nv_drain_rx(dev);
3705         nv_drain_tx(dev);
3706
3707         if (netif_running(dev)) {
3708                 writel(misc1_flags, base + NvRegMisc1);
3709                 writel(filter_flags, base + NvRegPacketFilterFlags);
3710                 nv_enable_irq(dev);
3711         }
3712
3713         return ret;
3714 }
3715
3716 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
3717 {
3718         struct fe_priv *np = netdev_priv(dev);
3719         u8 __iomem *base = get_hwbase(dev);
3720         int result;
3721         memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64));
3722
3723         if (!nv_link_test(dev)) {
3724                 test->flags |= ETH_TEST_FL_FAILED;
3725                 buffer[0] = 1;
3726         }
3727
3728         if (test->flags & ETH_TEST_FL_OFFLINE) {
3729                 if (netif_running(dev)) {
3730                         netif_stop_queue(dev);
3731                         spin_lock_bh(&dev->xmit_lock);
3732                         spin_lock_irq(&np->lock);
3733                         nv_disable_hw_interrupts(dev, np->irqmask);
3734                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3735                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3736                         } else {
3737                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3738                         }
3739                         /* stop engines */
3740                         nv_stop_rx(dev);
3741                         nv_stop_tx(dev);
3742                         nv_txrx_reset(dev);
3743                         /* drain rx queue */
3744                         nv_drain_rx(dev);
3745                         nv_drain_tx(dev);
3746                         spin_unlock_irq(&np->lock);
3747                         spin_unlock_bh(&dev->xmit_lock);
3748                 }
3749
3750                 if (!nv_register_test(dev)) {
3751                         test->flags |= ETH_TEST_FL_FAILED;
3752                         buffer[1] = 1;
3753                 }
3754
3755                 result = nv_interrupt_test(dev);
3756                 if (result != 1) {
3757                         test->flags |= ETH_TEST_FL_FAILED;
3758                         buffer[2] = 1;
3759                 }
3760                 if (result == 0) {
3761                         /* bail out */
3762                         return;
3763                 }
3764
3765                 if (!nv_loopback_test(dev)) {
3766                         test->flags |= ETH_TEST_FL_FAILED;
3767                         buffer[3] = 1;
3768                 }
3769
3770                 if (netif_running(dev)) {
3771                         /* reinit driver view of the rx queue */
3772                         set_bufsize(dev);
3773                         if (nv_init_ring(dev)) {
3774                                 if (!np->in_shutdown)
3775                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3776                         }
3777                         /* reinit nic view of the rx queue */
3778                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3779                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3780                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3781                                 base + NvRegRingSizes);
3782                         pci_push(base);
3783                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3784                         pci_push(base);
3785                         /* restart rx engine */
3786                         nv_start_rx(dev);
3787                         nv_start_tx(dev);
3788                         netif_start_queue(dev);
3789                         nv_enable_hw_interrupts(dev, np->irqmask);
3790                 }
3791         }
3792 }
3793
3794 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
3795 {
3796         switch (stringset) {
3797         case ETH_SS_STATS:
3798                 memcpy(buffer, &nv_estats_str, nv_get_stats_count(dev)*sizeof(struct nv_ethtool_str));
3799                 break;
3800         case ETH_SS_TEST:
3801                 memcpy(buffer, &nv_etests_str, nv_self_test_count(dev)*sizeof(struct nv_ethtool_str));
3802                 break;
3803         }
3804 }
3805
3806 static struct ethtool_ops ops = {
3807         .get_drvinfo = nv_get_drvinfo,
3808         .get_link = ethtool_op_get_link,
3809         .get_wol = nv_get_wol,
3810         .set_wol = nv_set_wol,
3811         .get_settings = nv_get_settings,
3812         .set_settings = nv_set_settings,
3813         .get_regs_len = nv_get_regs_len,
3814         .get_regs = nv_get_regs,
3815         .nway_reset = nv_nway_reset,
3816         .get_perm_addr = ethtool_op_get_perm_addr,
3817         .get_tso = ethtool_op_get_tso,
3818         .set_tso = nv_set_tso,
3819         .get_ringparam = nv_get_ringparam,
3820         .set_ringparam = nv_set_ringparam,
3821         .get_pauseparam = nv_get_pauseparam,
3822         .set_pauseparam = nv_set_pauseparam,
3823         .get_rx_csum = nv_get_rx_csum,
3824         .set_rx_csum = nv_set_rx_csum,
3825         .get_tx_csum = ethtool_op_get_tx_csum,
3826         .set_tx_csum = nv_set_tx_csum,
3827         .get_sg = ethtool_op_get_sg,
3828         .set_sg = nv_set_sg,
3829         .get_strings = nv_get_strings,
3830         .get_stats_count = nv_get_stats_count,
3831         .get_ethtool_stats = nv_get_ethtool_stats,
3832         .self_test_count = nv_self_test_count,
3833         .self_test = nv_self_test,
3834 };
3835
3836 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
3837 {
3838         struct fe_priv *np = get_nvpriv(dev);
3839
3840         spin_lock_irq(&np->lock);
3841
3842         /* save vlan group */
3843         np->vlangrp = grp;
3844
3845         if (grp) {
3846                 /* enable vlan on MAC */
3847                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
3848         } else {
3849                 /* disable vlan on MAC */
3850                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
3851                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
3852         }
3853
3854         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3855
3856         spin_unlock_irq(&np->lock);
3857 };
3858
3859 static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
3860 {
3861         /* nothing to do */
3862 };
3863
3864 static int nv_open(struct net_device *dev)
3865 {
3866         struct fe_priv *np = netdev_priv(dev);
3867         u8 __iomem *base = get_hwbase(dev);
3868         int ret = 1;
3869         int oom, i;
3870
3871         dprintk(KERN_DEBUG "nv_open: begin\n");
3872
3873         /* 1) erase previous misconfiguration */
3874         if (np->driver_data & DEV_HAS_POWER_CNTRL)
3875                 nv_mac_reset(dev);
3876         /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
3877         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
3878         writel(0, base + NvRegMulticastAddrB);
3879         writel(0, base + NvRegMulticastMaskA);
3880         writel(0, base + NvRegMulticastMaskB);
3881         writel(0, base + NvRegPacketFilterFlags);
3882
3883         writel(0, base + NvRegTransmitterControl);
3884         writel(0, base + NvRegReceiverControl);
3885
3886         writel(0, base + NvRegAdapterControl);
3887
3888         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
3889                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
3890
3891         /* 2) initialize descriptor rings */
3892         set_bufsize(dev);
3893         oom = nv_init_ring(dev);
3894
3895         writel(0, base + NvRegLinkSpeed);
3896         writel(0, base + NvRegUnknownTransmitterReg);
3897         nv_txrx_reset(dev);
3898         writel(0, base + NvRegUnknownSetupReg6);
3899
3900         np->in_shutdown = 0;
3901
3902         /* 3) set mac address */
3903         nv_copy_mac_to_hw(dev);
3904
3905         /* 4) give hw rings */
3906         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3907         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3908                 base + NvRegRingSizes);
3909
3910         /* 5) continue setup */
3911         writel(np->linkspeed, base + NvRegLinkSpeed);
3912         writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
3913         writel(np->txrxctl_bits, base + NvRegTxRxControl);
3914         writel(np->vlanctl_bits, base + NvRegVlanControl);
3915         pci_push(base);
3916         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
3917         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
3918                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
3919                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
3920
3921         writel(0, base + NvRegUnknownSetupReg4);
3922         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3923         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
3924
3925         /* 6) continue setup */
3926         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
3927         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
3928         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
3929         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3930
3931         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
3932         get_random_bytes(&i, sizeof(i));
3933         writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
3934         writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
3935         writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
3936         if (poll_interval == -1) {
3937                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
3938                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
3939                 else
3940                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
3941         }
3942         else
3943                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
3944         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3945         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
3946                         base + NvRegAdapterControl);
3947         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
3948         writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
3949         if (np->wolenabled)
3950                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
3951
3952         i = readl(base + NvRegPowerState);
3953         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
3954                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
3955
3956         pci_push(base);
3957         udelay(10);
3958         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
3959
3960         nv_disable_hw_interrupts(dev, np->irqmask);
3961         pci_push(base);
3962         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
3963         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3964         pci_push(base);
3965
3966         if (nv_request_irq(dev, 0)) {
3967                 goto out_drain;
3968         }
3969
3970         /* ask for interrupts */
3971         nv_enable_hw_interrupts(dev, np->irqmask);
3972
3973         spin_lock_irq(&np->lock);
3974         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
3975         writel(0, base + NvRegMulticastAddrB);
3976         writel(0, base + NvRegMulticastMaskA);
3977         writel(0, base + NvRegMulticastMaskB);
3978         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
3979         /* One manual link speed update: Interrupts are enabled, future link
3980          * speed changes cause interrupts and are handled by nv_link_irq().
3981          */
3982         {
3983                 u32 miistat;
3984                 miistat = readl(base + NvRegMIIStatus);
3985                 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
3986                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
3987         }
3988         /* set linkspeed to invalid value, thus force nv_update_linkspeed
3989          * to init hw */
3990         np->linkspeed = 0;
3991         ret = nv_update_linkspeed(dev);
3992         nv_start_rx(dev);
3993         nv_start_tx(dev);
3994         netif_start_queue(dev);
3995         if (ret) {
3996                 netif_carrier_on(dev);
3997         } else {
3998                 printk("%s: no link during initialization.\n", dev->name);
3999                 netif_carrier_off(dev);
4000         }
4001         if (oom)
4002                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4003
4004         /* start statistics timer */
4005         if (np->driver_data & DEV_HAS_STATISTICS)
4006                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
4007
4008         spin_unlock_irq(&np->lock);
4009
4010         return 0;
4011 out_drain:
4012         drain_ring(dev);
4013         return ret;
4014 }
4015
4016 static int nv_close(struct net_device *dev)
4017 {
4018         struct fe_priv *np = netdev_priv(dev);
4019         u8 __iomem *base;
4020
4021         spin_lock_irq(&np->lock);
4022         np->in_shutdown = 1;
4023         spin_unlock_irq(&np->lock);
4024         synchronize_irq(dev->irq);
4025
4026         del_timer_sync(&np->oom_kick);
4027         del_timer_sync(&np->nic_poll);
4028         del_timer_sync(&np->stats_poll);
4029
4030         netif_stop_queue(dev);
4031         spin_lock_irq(&np->lock);
4032         nv_stop_tx(dev);
4033         nv_stop_rx(dev);
4034         nv_txrx_reset(dev);
4035
4036         /* disable interrupts on the nic or we will lock up */
4037         base = get_hwbase(dev);
4038         nv_disable_hw_interrupts(dev, np->irqmask);
4039         pci_push(base);
4040         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
4041
4042         spin_unlock_irq(&np->lock);
4043
4044         nv_free_irq(dev);
4045
4046         drain_ring(dev);
4047
4048         if (np->wolenabled)
4049                 nv_start_rx(dev);
4050
4051         /* special op: write back the misordered MAC address - otherwise
4052          * the next nv_probe would see a wrong address.
4053          */
4054         writel(np->orig_mac[0], base + NvRegMacAddrA);
4055         writel(np->orig_mac[1], base + NvRegMacAddrB);
4056
4057         /* FIXME: power down nic */
4058
4059         return 0;
4060 }
4061
4062 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
4063 {
4064         struct net_device *dev;
4065         struct fe_priv *np;
4066         unsigned long addr;
4067         u8 __iomem *base;
4068         int err, i;
4069         u32 powerstate;
4070
4071         dev = alloc_etherdev(sizeof(struct fe_priv));
4072         err = -ENOMEM;
4073         if (!dev)
4074                 goto out;
4075
4076         np = netdev_priv(dev);
4077         np->pci_dev = pci_dev;
4078         spin_lock_init(&np->lock);
4079         SET_MODULE_OWNER(dev);
4080         SET_NETDEV_DEV(dev, &pci_dev->dev);
4081
4082         init_timer(&np->oom_kick);
4083         np->oom_kick.data = (unsigned long) dev;
4084         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
4085         init_timer(&np->nic_poll);
4086         np->nic_poll.data = (unsigned long) dev;
4087         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
4088         init_timer(&np->stats_poll);
4089         np->stats_poll.data = (unsigned long) dev;
4090         np->stats_poll.function = &nv_do_stats_poll;    /* timer handler */
4091
4092         err = pci_enable_device(pci_dev);
4093         if (err) {
4094                 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
4095                                 err, pci_name(pci_dev));
4096                 goto out_free;
4097         }
4098
4099         pci_set_master(pci_dev);
4100
4101         err = pci_request_regions(pci_dev, DRV_NAME);
4102         if (err < 0)
4103                 goto out_disable;
4104
4105         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS))
4106                 np->register_size = NV_PCI_REGSZ_VER2;
4107         else
4108                 np->register_size = NV_PCI_REGSZ_VER1;
4109
4110         err = -EINVAL;
4111         addr = 0;
4112         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
4113                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
4114                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
4115                                 pci_resource_len(pci_dev, i),
4116                                 pci_resource_flags(pci_dev, i));
4117                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
4118                                 pci_resource_len(pci_dev, i) >= np->register_size) {
4119                         addr = pci_resource_start(pci_dev, i);
4120                         break;
4121                 }
4122         }
4123         if (i == DEVICE_COUNT_RESOURCE) {
4124                 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
4125                                         pci_name(pci_dev));
4126                 goto out_relreg;
4127         }
4128
4129         /* copy of driver data */
4130         np->driver_data = id->driver_data;
4131
4132         /* handle different descriptor versions */
4133         if (id->driver_data & DEV_HAS_HIGH_DMA) {
4134                 /* packet format 3: supports 40-bit addressing */
4135                 np->desc_ver = DESC_VER_3;
4136                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
4137                 if (dma_64bit) {
4138                         if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4139                                 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
4140                                        pci_name(pci_dev));
4141                         } else {
4142                                 dev->features |= NETIF_F_HIGHDMA;
4143                                 printk(KERN_INFO "forcedeth: using HIGHDMA\n");
4144                         }
4145                         if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4146                                 printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n",
4147                                        pci_name(pci_dev));
4148                         }
4149                 }
4150         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
4151                 /* packet format 2: supports jumbo frames */
4152                 np->desc_ver = DESC_VER_2;
4153                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
4154         } else {
4155                 /* original packet format */
4156                 np->desc_ver = DESC_VER_1;
4157                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
4158         }
4159
4160         np->pkt_limit = NV_PKTLIMIT_1;
4161         if (id->driver_data & DEV_HAS_LARGEDESC)
4162                 np->pkt_limit = NV_PKTLIMIT_2;
4163
4164         if (id->driver_data & DEV_HAS_CHECKSUM) {
4165                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4166                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
4167 #ifdef NETIF_F_TSO
4168                 dev->features |= NETIF_F_TSO;
4169 #endif
4170         }
4171
4172         np->vlanctl_bits = 0;
4173         if (id->driver_data & DEV_HAS_VLAN) {
4174                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
4175                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
4176                 dev->vlan_rx_register = nv_vlan_rx_register;
4177                 dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid;
4178         }
4179
4180         np->msi_flags = 0;
4181         if ((id->driver_data & DEV_HAS_MSI) && msi) {
4182                 np->msi_flags |= NV_MSI_CAPABLE;
4183         }
4184         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
4185                 np->msi_flags |= NV_MSI_X_CAPABLE;
4186         }
4187
4188         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
4189         if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {
4190                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
4191         }
4192
4193
4194         err = -ENOMEM;
4195         np->base = ioremap(addr, np->register_size);
4196         if (!np->base)
4197                 goto out_relreg;
4198         dev->base_addr = (unsigned long)np->base;
4199
4200         dev->irq = pci_dev->irq;
4201
4202         np->rx_ring_size = RX_RING_DEFAULT;
4203         np->tx_ring_size = TX_RING_DEFAULT;
4204         np->tx_limit_stop = np->tx_ring_size - TX_LIMIT_DIFFERENCE;
4205         np->tx_limit_start = np->tx_ring_size - TX_LIMIT_DIFFERENCE - 1;
4206
4207         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4208                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
4209                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
4210                                         &np->ring_addr);
4211                 if (!np->rx_ring.orig)
4212                         goto out_unmap;
4213                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4214         } else {
4215                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
4216                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
4217                                         &np->ring_addr);
4218                 if (!np->rx_ring.ex)
4219                         goto out_unmap;
4220                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4221         }
4222         np->rx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->rx_ring_size, GFP_KERNEL);
4223         np->rx_dma = kmalloc(sizeof(dma_addr_t) * np->rx_ring_size, GFP_KERNEL);
4224         np->tx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->tx_ring_size, GFP_KERNEL);
4225         np->tx_dma = kmalloc(sizeof(dma_addr_t) * np->tx_ring_size, GFP_KERNEL);
4226         np->tx_dma_len = kmalloc(sizeof(unsigned int) * np->tx_ring_size, GFP_KERNEL);
4227         if (!np->rx_skbuff || !np->rx_dma || !np->tx_skbuff || !np->tx_dma || !np->tx_dma_len)
4228                 goto out_freering;
4229         memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
4230         memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
4231         memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
4232         memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
4233         memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
4234
4235         dev->open = nv_open;
4236         dev->stop = nv_close;
4237         dev->hard_start_xmit = nv_start_xmit;
4238         dev->get_stats = nv_get_stats;
4239         dev->change_mtu = nv_change_mtu;
4240         dev->set_mac_address = nv_set_mac_address;
4241         dev->set_multicast_list = nv_set_multicast;
4242 #ifdef CONFIG_NET_POLL_CONTROLLER
4243         dev->poll_controller = nv_poll_controller;
4244 #endif
4245         SET_ETHTOOL_OPS(dev, &ops);
4246         dev->tx_timeout = nv_tx_timeout;
4247         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
4248
4249         pci_set_drvdata(pci_dev, dev);
4250
4251         /* read the mac address */
4252         base = get_hwbase(dev);
4253         np->orig_mac[0] = readl(base + NvRegMacAddrA);
4254         np->orig_mac[1] = readl(base + NvRegMacAddrB);
4255
4256         dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
4257         dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
4258         dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
4259         dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
4260         dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
4261         dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
4262         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4263
4264         if (!is_valid_ether_addr(dev->perm_addr)) {
4265                 /*
4266                  * Bad mac address. At least one bios sets the mac address
4267                  * to 01:23:45:67:89:ab
4268                  */
4269                 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
4270                         pci_name(pci_dev),
4271                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4272                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4273                 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
4274                 dev->dev_addr[0] = 0x00;
4275                 dev->dev_addr[1] = 0x00;
4276                 dev->dev_addr[2] = 0x6c;
4277                 get_random_bytes(&dev->dev_addr[3], 3);
4278         }
4279
4280         dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
4281                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4282                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4283
4284         /* disable WOL */
4285         writel(0, base + NvRegWakeUpFlags);
4286         np->wolenabled = 0;
4287
4288         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
4289                 u8 revision_id;
4290                 pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id);
4291
4292                 /* take phy and nic out of low power mode */
4293                 powerstate = readl(base + NvRegPowerState2);
4294                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
4295                 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
4296                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
4297                     revision_id >= 0xA3)
4298                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
4299                 writel(powerstate, base + NvRegPowerState2);
4300         }
4301
4302         if (np->desc_ver == DESC_VER_1) {
4303                 np->tx_flags = NV_TX_VALID;
4304         } else {
4305                 np->tx_flags = NV_TX2_VALID;
4306         }
4307         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
4308                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
4309                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
4310                         np->msi_flags |= 0x0003;
4311         } else {
4312                 np->irqmask = NVREG_IRQMASK_CPU;
4313                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
4314                         np->msi_flags |= 0x0001;
4315         }
4316
4317         if (id->driver_data & DEV_NEED_TIMERIRQ)
4318                 np->irqmask |= NVREG_IRQ_TIMER;
4319         if (id->driver_data & DEV_NEED_LINKTIMER) {
4320                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
4321                 np->need_linktimer = 1;
4322                 np->link_timeout = jiffies + LINK_TIMEOUT;
4323         } else {
4324                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
4325                 np->need_linktimer = 0;
4326         }
4327
4328         /* find a suitable phy */
4329         for (i = 1; i <= 32; i++) {
4330                 int id1, id2;
4331                 int phyaddr = i & 0x1F;
4332
4333                 spin_lock_irq(&np->lock);
4334                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
4335                 spin_unlock_irq(&np->lock);
4336                 if (id1 < 0 || id1 == 0xffff)
4337                         continue;
4338                 spin_lock_irq(&np->lock);
4339                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
4340                 spin_unlock_irq(&np->lock);
4341                 if (id2 < 0 || id2 == 0xffff)
4342                         continue;
4343
4344                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
4345                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
4346                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
4347                         pci_name(pci_dev), id1, id2, phyaddr);
4348                 np->phyaddr = phyaddr;
4349                 np->phy_oui = id1 | id2;
4350                 break;
4351         }
4352         if (i == 33) {
4353                 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
4354                        pci_name(pci_dev));
4355                 goto out_error;
4356         }
4357
4358         /* reset it */
4359         phy_init(dev);
4360
4361         /* set default link speed settings */
4362         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
4363         np->duplex = 0;
4364         np->autoneg = 1;
4365
4366         err = register_netdev(dev);
4367         if (err) {
4368                 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
4369                 goto out_error;
4370         }
4371         printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
4372                         dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
4373                         pci_name(pci_dev));
4374
4375         return 0;
4376
4377 out_error:
4378         pci_set_drvdata(pci_dev, NULL);
4379 out_freering:
4380         free_rings(dev);
4381 out_unmap:
4382         iounmap(get_hwbase(dev));
4383 out_relreg:
4384         pci_release_regions(pci_dev);
4385 out_disable:
4386         pci_disable_device(pci_dev);
4387 out_free:
4388         free_netdev(dev);
4389 out:
4390         return err;
4391 }
4392
4393 static void __devexit nv_remove(struct pci_dev *pci_dev)
4394 {
4395         struct net_device *dev = pci_get_drvdata(pci_dev);
4396
4397         unregister_netdev(dev);
4398
4399         /* free all structures */
4400         free_rings(dev);
4401         iounmap(get_hwbase(dev));
4402         pci_release_regions(pci_dev);
4403         pci_disable_device(pci_dev);
4404         free_netdev(dev);
4405         pci_set_drvdata(pci_dev, NULL);
4406 }
4407
4408 static struct pci_device_id pci_tbl[] = {
4409         {       /* nForce Ethernet Controller */
4410                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
4411                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4412         },
4413         {       /* nForce2 Ethernet Controller */
4414                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
4415                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4416         },
4417         {       /* nForce3 Ethernet Controller */
4418                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
4419                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4420         },
4421         {       /* nForce3 Ethernet Controller */
4422                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
4423                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4424         },
4425         {       /* nForce3 Ethernet Controller */
4426                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
4427                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4428         },
4429         {       /* nForce3 Ethernet Controller */
4430                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
4431                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4432         },
4433         {       /* nForce3 Ethernet Controller */
4434                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
4435                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4436         },
4437         {       /* CK804 Ethernet Controller */
4438                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
4439                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4440         },
4441         {       /* CK804 Ethernet Controller */
4442                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
4443                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4444         },
4445         {       /* MCP04 Ethernet Controller */
4446                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
4447                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4448         },
4449         {       /* MCP04 Ethernet Controller */
4450                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
4451                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4452         },
4453         {       /* MCP51 Ethernet Controller */
4454                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
4455                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4456         },
4457         {       /* MCP51 Ethernet Controller */
4458                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
4459                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4460         },
4461         {       /* MCP55 Ethernet Controller */
4462                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
4463                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4464         },
4465         {       /* MCP55 Ethernet Controller */
4466                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
4467                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4468         },
4469         {0,},
4470 };
4471
4472 static struct pci_driver driver = {
4473         .name = "forcedeth",
4474         .id_table = pci_tbl,
4475         .probe = nv_probe,
4476         .remove = __devexit_p(nv_remove),
4477 };
4478
4479
4480 static int __init init_nic(void)
4481 {
4482         printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
4483         return pci_module_init(&driver);
4484 }
4485
4486 static void __exit exit_nic(void)
4487 {
4488         pci_unregister_driver(&driver);
4489 }
4490
4491 module_param(max_interrupt_work, int, 0);
4492 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
4493 module_param(optimization_mode, int, 0);
4494 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
4495 module_param(poll_interval, int, 0);
4496 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
4497 module_param(msi, int, 0);
4498 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
4499 module_param(msix, int, 0);
4500 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
4501 module_param(dma_64bit, int, 0);
4502 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
4503
4504 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
4505 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
4506 MODULE_LICENSE("GPL");
4507
4508 MODULE_DEVICE_TABLE(pci, pci_tbl);
4509
4510 module_init(init_nic);
4511 module_exit(exit_nic);