drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey.
   7  *
   8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
   9  * trademarks of NVIDIA Corporation in the United States and other
  10  * countries.
  11  *
  12  * Copyright (C) 2003,4,5 Manfred Spraul
  13  * Copyright (C) 2004 Andrew de Quincey (wol support)
  14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  16  * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License as published by
  20  * the Free Software Foundation; either version 2 of the License, or
  21  * (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  31  *
  32  * Known bugs:
  33  * We suspect that on some hardware no TX done interrupts are generated.
  34  * This means recovery from netif_stop_queue only happens if the hw timer
  35  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
  36  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
  37  * If your hardware reliably generates tx done interrupts, then you can remove
  38  * DEV_NEED_TIMERIRQ from the driver_data flags.
  39  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
  40  * superfluous timer interrupts from the nic.
  41  */
  42 #define FORCEDETH_VERSION               "0.64"
  43 #define DRV_NAME                        "forcedeth"
  44
  45 #include <linux/module.h>
  46 #include <linux/types.h>
  47 #include <linux/pci.h>
  48 #include <linux/interrupt.h>
  49 #include <linux/netdevice.h>
  50 #include <linux/etherdevice.h>
  51 #include <linux/delay.h>
  52 #include <linux/spinlock.h>
  53 #include <linux/ethtool.h>
  54 #include <linux/timer.h>
  55 #include <linux/skbuff.h>
  56 #include <linux/mii.h>
  57 #include <linux/random.h>
  58 #include <linux/init.h>
  59 #include <linux/if_vlan.h>
  60 #include <linux/dma-mapping.h>
  61
  62 #include <asm/irq.h>
  63 #include <asm/io.h>
  64 #include <asm/uaccess.h>
  65 #include <asm/system.h>
  66
  67 #if 0
  68 #define dprintk                 printk
  69 #else
  70 #define dprintk(x...)           do { } while (0)
  71 #endif
  72
  73 #define TX_WORK_PER_LOOP  64
  74 #define RX_WORK_PER_LOOP  64
  75
  76 /*
  77  * Hardware access:
  78  */
  79
  80 #define DEV_NEED_TIMERIRQ          0x0000001  /* set the timer irq flag in the irq mask */
  81 #define DEV_NEED_LINKTIMER         0x0000002  /* poll link settings. Relies on the timer irq */
  82 #define DEV_HAS_LARGEDESC          0x0000004  /* device supports jumbo frames and needs packet format 2 */
  83 #define DEV_HAS_HIGH_DMA           0x0000008  /* device supports 64bit dma */
  84 #define DEV_HAS_CHECKSUM           0x0000010  /* device supports tx and rx checksum offloads */
  85 #define DEV_HAS_VLAN               0x0000020  /* device supports vlan tagging and striping */
  86 #define DEV_HAS_MSI                0x0000040  /* device supports MSI */
  87 #define DEV_HAS_MSI_X              0x0000080  /* device supports MSI-X */
  88 #define DEV_HAS_POWER_CNTRL        0x0000100  /* device supports power savings */
  89 #define DEV_HAS_STATISTICS_V1      0x0000200  /* device supports hw statistics version 1 */
  90 #define DEV_HAS_STATISTICS_V2      0x0000600  /* device supports hw statistics version 2 */
  91 #define DEV_HAS_STATISTICS_V3      0x0000e00  /* device supports hw statistics version 3 */
  92 #define DEV_HAS_TEST_EXTENDED      0x0001000  /* device supports extended diagnostic test */
  93 #define DEV_HAS_MGMT_UNIT          0x0002000  /* device supports management unit */
  94 #define DEV_HAS_CORRECT_MACADDR    0x0004000  /* device supports correct mac address order */
  95 #define DEV_HAS_COLLISION_FIX      0x0008000  /* device supports tx collision fix */
  96 #define DEV_HAS_PAUSEFRAME_TX_V1   0x0010000  /* device supports tx pause frames version 1 */
  97 #define DEV_HAS_PAUSEFRAME_TX_V2   0x0020000  /* device supports tx pause frames version 2 */
  98 #define DEV_HAS_PAUSEFRAME_TX_V3   0x0040000  /* device supports tx pause frames version 3 */
  99 #define DEV_NEED_TX_LIMIT          0x0080000  /* device needs to limit tx */
 100 #define DEV_NEED_TX_LIMIT2         0x0180000  /* device needs to limit tx, expect for some revs */
 101 #define DEV_HAS_GEAR_MODE          0x0200000  /* device supports gear mode */
 102 #define DEV_NEED_PHY_INIT_FIX      0x0400000  /* device needs specific phy workaround */
 103 #define DEV_NEED_LOW_POWER_FIX     0x0800000  /* device needs special power up workaround */
 104 #define DEV_NEED_MSI_FIX           0x1000000  /* device needs msi workaround */
 105
 106 enum {
 107         NvRegIrqStatus = 0x000,
 108 #define NVREG_IRQSTAT_MIIEVENT  0x040
 109 #define NVREG_IRQSTAT_MASK              0x83ff
 110         NvRegIrqMask = 0x004,
 111 #define NVREG_IRQ_RX_ERROR              0x0001
 112 #define NVREG_IRQ_RX                    0x0002
 113 #define NVREG_IRQ_RX_NOBUF              0x0004
 114 #define NVREG_IRQ_TX_ERR                0x0008
 115 #define NVREG_IRQ_TX_OK                 0x0010
 116 #define NVREG_IRQ_TIMER                 0x0020
 117 #define NVREG_IRQ_LINK                  0x0040
 118 #define NVREG_IRQ_RX_FORCED             0x0080
 119 #define NVREG_IRQ_TX_FORCED             0x0100
 120 #define NVREG_IRQ_RECOVER_ERROR         0x8200
 121 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 122 #define NVREG_IRQMASK_CPU               0x0060
 123 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 124 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 125 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
 126
 127         NvRegUnknownSetupReg6 = 0x008,
 128 #define NVREG_UNKSETUP6_VAL             3
 129
 130 /*
 131  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 132  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 133  */
 134         NvRegPollingInterval = 0x00c,
 135 #define NVREG_POLL_DEFAULT_THROUGHPUT   65535 /* backup tx cleanup if loop max reached */
 136 #define NVREG_POLL_DEFAULT_CPU  13
 137         NvRegMSIMap0 = 0x020,
 138         NvRegMSIMap1 = 0x024,
 139         NvRegMSIIrqMask = 0x030,
 140 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 141         NvRegMisc1 = 0x080,
 142 #define NVREG_MISC1_PAUSE_TX    0x01
 143 #define NVREG_MISC1_HD          0x02
 144 #define NVREG_MISC1_FORCE       0x3b0f3c
 145
 146         NvRegMacReset = 0x34,
 147 #define NVREG_MAC_RESET_ASSERT  0x0F3
 148         NvRegTransmitterControl = 0x084,
 149 #define NVREG_XMITCTL_START     0x01
 150 #define NVREG_XMITCTL_MGMT_ST   0x40000000
 151 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
 152 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
 153 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
 154 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
 155 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
 156 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
 157 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
 158 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
 159 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
 160 #define NVREG_XMITCTL_DATA_START        0x00100000
 161 #define NVREG_XMITCTL_DATA_READY        0x00010000
 162 #define NVREG_XMITCTL_DATA_ERROR        0x00020000
 163         NvRegTransmitterStatus = 0x088,
 164 #define NVREG_XMITSTAT_BUSY     0x01
 165
 166         NvRegPacketFilterFlags = 0x8c,
 167 #define NVREG_PFF_PAUSE_RX      0x08
 168 #define NVREG_PFF_ALWAYS        0x7F0000
 169 #define NVREG_PFF_PROMISC       0x80
 170 #define NVREG_PFF_MYADDR        0x20
 171 #define NVREG_PFF_LOOPBACK      0x10
 172
 173         NvRegOffloadConfig = 0x90,
 174 #define NVREG_OFFLOAD_HOMEPHY   0x601
 175 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 176         NvRegReceiverControl = 0x094,
 177 #define NVREG_RCVCTL_START      0x01
 178 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
 179         NvRegReceiverStatus = 0x98,
 180 #define NVREG_RCVSTAT_BUSY      0x01
 181
 182         NvRegSlotTime = 0x9c,
 183 #define NVREG_SLOTTIME_LEGBF_ENABLED    0x80000000
 184 #define NVREG_SLOTTIME_10_100_FULL      0x00007f00
 185 #define NVREG_SLOTTIME_1000_FULL        0x0003ff00
 186 #define NVREG_SLOTTIME_HALF             0x0000ff00
 187 #define NVREG_SLOTTIME_DEFAULT          0x00007f00
 188 #define NVREG_SLOTTIME_MASK             0x000000ff
 189
 190         NvRegTxDeferral = 0xA0,
 191 #define NVREG_TX_DEFERRAL_DEFAULT               0x15050f
 192 #define NVREG_TX_DEFERRAL_RGMII_10_100          0x16070f
 193 #define NVREG_TX_DEFERRAL_RGMII_1000            0x14050f
 194 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10      0x16190f
 195 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100     0x16300f
 196 #define NVREG_TX_DEFERRAL_MII_STRETCH           0x152000
 197         NvRegRxDeferral = 0xA4,
 198 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
 199         NvRegMacAddrA = 0xA8,
 200         NvRegMacAddrB = 0xAC,
 201         NvRegMulticastAddrA = 0xB0,
 202 #define NVREG_MCASTADDRA_FORCE  0x01
 203         NvRegMulticastAddrB = 0xB4,
 204         NvRegMulticastMaskA = 0xB8,
 205 #define NVREG_MCASTMASKA_NONE           0xffffffff
 206         NvRegMulticastMaskB = 0xBC,
 207 #define NVREG_MCASTMASKB_NONE           0xffff
 208
 209         NvRegPhyInterface = 0xC0,
 210 #define PHY_RGMII               0x10000000
 211         NvRegBackOffControl = 0xC4,
 212 #define NVREG_BKOFFCTRL_DEFAULT                 0x70000000
 213 #define NVREG_BKOFFCTRL_SEED_MASK               0x000003ff
 214 #define NVREG_BKOFFCTRL_SELECT                  24
 215 #define NVREG_BKOFFCTRL_GEAR                    12
 216
 217         NvRegTxRingPhysAddr = 0x100,
 218         NvRegRxRingPhysAddr = 0x104,
 219         NvRegRingSizes = 0x108,
 220 #define NVREG_RINGSZ_TXSHIFT 0
 221 #define NVREG_RINGSZ_RXSHIFT 16
 222         NvRegTransmitPoll = 0x10c,
 223 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
 224         NvRegLinkSpeed = 0x110,
 225 #define NVREG_LINKSPEED_FORCE 0x10000
 226 #define NVREG_LINKSPEED_10      1000
 227 #define NVREG_LINKSPEED_100     100
 228 #define NVREG_LINKSPEED_1000    50
 229 #define NVREG_LINKSPEED_MASK    (0xFFF)
 230         NvRegUnknownSetupReg5 = 0x130,
 231 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 232         NvRegTxWatermark = 0x13c,
 233 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
 234 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
 235 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
 236         NvRegTxRxControl = 0x144,
 237 #define NVREG_TXRXCTL_KICK      0x0001
 238 #define NVREG_TXRXCTL_BIT1      0x0002
 239 #define NVREG_TXRXCTL_BIT2      0x0004
 240 #define NVREG_TXRXCTL_IDLE      0x0008
 241 #define NVREG_TXRXCTL_RESET     0x0010
 242 #define NVREG_TXRXCTL_RXCHECK   0x0400
 243 #define NVREG_TXRXCTL_DESC_1    0
 244 #define NVREG_TXRXCTL_DESC_2    0x002100
 245 #define NVREG_TXRXCTL_DESC_3    0xc02200
 246 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 247 #define NVREG_TXRXCTL_VLANINS   0x00080
 248         NvRegTxRingPhysAddrHigh = 0x148,
 249         NvRegRxRingPhysAddrHigh = 0x14C,
 250         NvRegTxPauseFrame = 0x170,
 251 #define NVREG_TX_PAUSEFRAME_DISABLE     0x0fff0080
 252 #define NVREG_TX_PAUSEFRAME_ENABLE_V1   0x01800010
 253 #define NVREG_TX_PAUSEFRAME_ENABLE_V2   0x056003f0
 254 #define NVREG_TX_PAUSEFRAME_ENABLE_V3   0x09f00880
 255         NvRegTxPauseFrameLimit = 0x174,
 256 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
 257         NvRegMIIStatus = 0x180,
 258 #define NVREG_MIISTAT_ERROR             0x0001
 259 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 260 #define NVREG_MIISTAT_MASK_RW           0x0007
 261 #define NVREG_MIISTAT_MASK_ALL          0x000f
 262         NvRegMIIMask = 0x184,
 263 #define NVREG_MII_LINKCHANGE            0x0008
 264
 265         NvRegAdapterControl = 0x188,
 266 #define NVREG_ADAPTCTL_START    0x02
 267 #define NVREG_ADAPTCTL_LINKUP   0x04
 268 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 269 #define NVREG_ADAPTCTL_RUNNING  0x100000
 270 #define NVREG_ADAPTCTL_PHYSHIFT 24
 271         NvRegMIISpeed = 0x18c,
 272 #define NVREG_MIISPEED_BIT8     (1<<8)
 273 #define NVREG_MIIDELAY  5
 274         NvRegMIIControl = 0x190,
 275 #define NVREG_MIICTL_INUSE      0x08000
 276 #define NVREG_MIICTL_WRITE      0x00400
 277 #define NVREG_MIICTL_ADDRSHIFT  5
 278         NvRegMIIData = 0x194,
 279         NvRegTxUnicast = 0x1a0,
 280         NvRegTxMulticast = 0x1a4,
 281         NvRegTxBroadcast = 0x1a8,
 282         NvRegWakeUpFlags = 0x200,
 283 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 284 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 285 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 286 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 287 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 288 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 289 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 290 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 291 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 292 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 293 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 294
 295         NvRegMgmtUnitGetVersion = 0x204,
 296 #define NVREG_MGMTUNITGETVERSION        0x01
 297         NvRegMgmtUnitVersion = 0x208,
 298 #define NVREG_MGMTUNITVERSION           0x08
 299         NvRegPowerCap = 0x268,
 300 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 301 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 302 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 303         NvRegPowerState = 0x26c,
 304 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 305 #define NVREG_POWERSTATE_VALID          0x0100
 306 #define NVREG_POWERSTATE_MASK           0x0003
 307 #define NVREG_POWERSTATE_D0             0x0000
 308 #define NVREG_POWERSTATE_D1             0x0001
 309 #define NVREG_POWERSTATE_D2             0x0002
 310 #define NVREG_POWERSTATE_D3             0x0003
 311         NvRegMgmtUnitControl = 0x278,
 312 #define NVREG_MGMTUNITCONTROL_INUSE     0x20000
 313         NvRegTxCnt = 0x280,
 314         NvRegTxZeroReXmt = 0x284,
 315         NvRegTxOneReXmt = 0x288,
 316         NvRegTxManyReXmt = 0x28c,
 317         NvRegTxLateCol = 0x290,
 318         NvRegTxUnderflow = 0x294,
 319         NvRegTxLossCarrier = 0x298,
 320         NvRegTxExcessDef = 0x29c,
 321         NvRegTxRetryErr = 0x2a0,
 322         NvRegRxFrameErr = 0x2a4,
 323         NvRegRxExtraByte = 0x2a8,
 324         NvRegRxLateCol = 0x2ac,
 325         NvRegRxRunt = 0x2b0,
 326         NvRegRxFrameTooLong = 0x2b4,
 327         NvRegRxOverflow = 0x2b8,
 328         NvRegRxFCSErr = 0x2bc,
 329         NvRegRxFrameAlignErr = 0x2c0,
 330         NvRegRxLenErr = 0x2c4,
 331         NvRegRxUnicast = 0x2c8,
 332         NvRegRxMulticast = 0x2cc,
 333         NvRegRxBroadcast = 0x2d0,
 334         NvRegTxDef = 0x2d4,
 335         NvRegTxFrame = 0x2d8,
 336         NvRegRxCnt = 0x2dc,
 337         NvRegTxPause = 0x2e0,
 338         NvRegRxPause = 0x2e4,
 339         NvRegRxDropFrame = 0x2e8,
 340         NvRegVlanControl = 0x300,
 341 #define NVREG_VLANCONTROL_ENABLE        0x2000
 342         NvRegMSIXMap0 = 0x3e0,
 343         NvRegMSIXMap1 = 0x3e4,
 344         NvRegMSIXIrqStatus = 0x3f0,
 345
 346         NvRegPowerState2 = 0x600,
 347 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F15
 348 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 349 #define NVREG_POWERSTATE2_PHY_RESET             0x0004
 350 #define NVREG_POWERSTATE2_GATE_CLOCKS           0x0F00
 351 };
 352
 353 /* Big endian: should work, but is untested */
 354 struct ring_desc {
 355         __le32 buf;
 356         __le32 flaglen;
 357 };
 358
 359 struct ring_desc_ex {
 360         __le32 bufhigh;
 361         __le32 buflow;
 362         __le32 txvlan;
 363         __le32 flaglen;
 364 };
 365
 366 union ring_type {
 367         struct ring_desc* orig;
 368         struct ring_desc_ex* ex;
 369 };
 370
 371 #define FLAG_MASK_V1 0xffff0000
 372 #define FLAG_MASK_V2 0xffffc000
 373 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 374 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 375
 376 #define NV_TX_LASTPACKET        (1<<16)
 377 #define NV_TX_RETRYERROR        (1<<19)
 378 #define NV_TX_RETRYCOUNT_MASK   (0xF<<20)
 379 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 380 #define NV_TX_DEFERRED          (1<<26)
 381 #define NV_TX_CARRIERLOST       (1<<27)
 382 #define NV_TX_LATECOLLISION     (1<<28)
 383 #define NV_TX_UNDERFLOW         (1<<29)
 384 #define NV_TX_ERROR             (1<<30)
 385 #define NV_TX_VALID             (1<<31)
 386
 387 #define NV_TX2_LASTPACKET       (1<<29)
 388 #define NV_TX2_RETRYERROR       (1<<18)
 389 #define NV_TX2_RETRYCOUNT_MASK  (0xF<<19)
 390 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 391 #define NV_TX2_DEFERRED         (1<<25)
 392 #define NV_TX2_CARRIERLOST      (1<<26)
 393 #define NV_TX2_LATECOLLISION    (1<<27)
 394 #define NV_TX2_UNDERFLOW        (1<<28)
 395 /* error and valid are the same for both */
 396 #define NV_TX2_ERROR            (1<<30)
 397 #define NV_TX2_VALID            (1<<31)
 398 #define NV_TX2_TSO              (1<<28)
 399 #define NV_TX2_TSO_SHIFT        14
 400 #define NV_TX2_TSO_MAX_SHIFT    14
 401 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 402 #define NV_TX2_CHECKSUM_L3      (1<<27)
 403 #define NV_TX2_CHECKSUM_L4      (1<<26)
 404
 405 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 406
 407 #define NV_RX_DESCRIPTORVALID   (1<<16)
 408 #define NV_RX_MISSEDFRAME       (1<<17)
 409 #define NV_RX_SUBSTRACT1        (1<<18)
 410 #define NV_RX_ERROR1            (1<<23)
 411 #define NV_RX_ERROR2            (1<<24)
 412 #define NV_RX_ERROR3            (1<<25)
 413 #define NV_RX_ERROR4            (1<<26)
 414 #define NV_RX_CRCERR            (1<<27)
 415 #define NV_RX_OVERFLOW          (1<<28)
 416 #define NV_RX_FRAMINGERR        (1<<29)
 417 #define NV_RX_ERROR             (1<<30)
 418 #define NV_RX_AVAIL             (1<<31)
 419 #define NV_RX_ERROR_MASK        (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
 420
 421 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 422 #define NV_RX2_CHECKSUM_IP      (0x10000000)
 423 #define NV_RX2_CHECKSUM_IP_TCP  (0x14000000)
 424 #define NV_RX2_CHECKSUM_IP_UDP  (0x18000000)
 425 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 426 #define NV_RX2_SUBSTRACT1       (1<<25)
 427 #define NV_RX2_ERROR1           (1<<18)
 428 #define NV_RX2_ERROR2           (1<<19)
 429 #define NV_RX2_ERROR3           (1<<20)
 430 #define NV_RX2_ERROR4           (1<<21)
 431 #define NV_RX2_CRCERR           (1<<22)
 432 #define NV_RX2_OVERFLOW         (1<<23)
 433 #define NV_RX2_FRAMINGERR       (1<<24)
 434 /* error and avail are the same for both */
 435 #define NV_RX2_ERROR            (1<<30)
 436 #define NV_RX2_AVAIL            (1<<31)
 437 #define NV_RX2_ERROR_MASK       (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
 438
 439 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 440 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 441
 442 /* Miscelaneous hardware related defines: */
 443 #define NV_PCI_REGSZ_VER1       0x270
 444 #define NV_PCI_REGSZ_VER2       0x2d4
 445 #define NV_PCI_REGSZ_VER3       0x604
 446 #define NV_PCI_REGSZ_MAX        0x604
 447
 448 /* various timeout delays: all in usec */
 449 #define NV_TXRX_RESET_DELAY     4
 450 #define NV_TXSTOP_DELAY1        10
 451 #define NV_TXSTOP_DELAY1MAX     500000
 452 #define NV_TXSTOP_DELAY2        100
 453 #define NV_RXSTOP_DELAY1        10
 454 #define NV_RXSTOP_DELAY1MAX     500000
 455 #define NV_RXSTOP_DELAY2        100
 456 #define NV_SETUP5_DELAY         5
 457 #define NV_SETUP5_DELAYMAX      50000
 458 #define NV_POWERUP_DELAY        5
 459 #define NV_POWERUP_DELAYMAX     5000
 460 #define NV_MIIBUSY_DELAY        50
 461 #define NV_MIIPHY_DELAY 10
 462 #define NV_MIIPHY_DELAYMAX      10000
 463 #define NV_MAC_RESET_DELAY      64
 464
 465 #define NV_WAKEUPPATTERNS       5
 466 #define NV_WAKEUPMASKENTRIES    4
 467
 468 /* General driver defaults */
 469 #define NV_WATCHDOG_TIMEO       (5*HZ)
 470
 471 #define RX_RING_DEFAULT         512
 472 #define TX_RING_DEFAULT         256
 473 #define RX_RING_MIN             128
 474 #define TX_RING_MIN             64
 475 #define RING_MAX_DESC_VER_1     1024
 476 #define RING_MAX_DESC_VER_2_3   16384
 477
 478 /* rx/tx mac addr + type + vlan + align + slack*/
 479 #define NV_RX_HEADERS           (64)
 480 /* even more slack. */
 481 #define NV_RX_ALLOC_PAD         (64)
 482
 483 /* maximum mtu size */
 484 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 485 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 486
 487 #define OOM_REFILL      (1+HZ/20)
 488 #define POLL_WAIT       (1+HZ/100)
 489 #define LINK_TIMEOUT    (3*HZ)
 490 #define STATS_INTERVAL  (10*HZ)
 491
 492 /*
 493  * desc_ver values:
 494  * The nic supports three different descriptor types:
 495  * - DESC_VER_1: Original
 496  * - DESC_VER_2: support for jumbo frames.
 497  * - DESC_VER_3: 64-bit format.
 498  */
 499 #define DESC_VER_1      1
 500 #define DESC_VER_2      2
 501 #define DESC_VER_3      3
 502
 503 /* PHY defines */
 504 #define PHY_OUI_MARVELL         0x5043
 505 #define PHY_OUI_CICADA          0x03f1
 506 #define PHY_OUI_VITESSE         0x01c1
 507 #define PHY_OUI_REALTEK         0x0732
 508 #define PHY_OUI_REALTEK2        0x0020
 509 #define PHYID1_OUI_MASK 0x03ff
 510 #define PHYID1_OUI_SHFT 6
 511 #define PHYID2_OUI_MASK 0xfc00
 512 #define PHYID2_OUI_SHFT 10
 513 #define PHYID2_MODEL_MASK               0x03f0
 514 #define PHY_MODEL_REALTEK_8211          0x0110
 515 #define PHY_REV_MASK                    0x0001
 516 #define PHY_REV_REALTEK_8211B           0x0000
 517 #define PHY_REV_REALTEK_8211C           0x0001
 518 #define PHY_MODEL_REALTEK_8201          0x0200
 519 #define PHY_MODEL_MARVELL_E3016         0x0220
 520 #define PHY_MARVELL_E3016_INITMASK      0x0300
 521 #define PHY_CICADA_INIT1        0x0f000
 522 #define PHY_CICADA_INIT2        0x0e00
 523 #define PHY_CICADA_INIT3        0x01000
 524 #define PHY_CICADA_INIT4        0x0200
 525 #define PHY_CICADA_INIT5        0x0004
 526 #define PHY_CICADA_INIT6        0x02000
 527 #define PHY_VITESSE_INIT_REG1   0x1f
 528 #define PHY_VITESSE_INIT_REG2   0x10
 529 #define PHY_VITESSE_INIT_REG3   0x11
 530 #define PHY_VITESSE_INIT_REG4   0x12
 531 #define PHY_VITESSE_INIT_MSK1   0xc
 532 #define PHY_VITESSE_INIT_MSK2   0x0180
 533 #define PHY_VITESSE_INIT1       0x52b5
 534 #define PHY_VITESSE_INIT2       0xaf8a
 535 #define PHY_VITESSE_INIT3       0x8
 536 #define PHY_VITESSE_INIT4       0x8f8a
 537 #define PHY_VITESSE_INIT5       0xaf86
 538 #define PHY_VITESSE_INIT6       0x8f86
 539 #define PHY_VITESSE_INIT7       0xaf82
 540 #define PHY_VITESSE_INIT8       0x0100
 541 #define PHY_VITESSE_INIT9       0x8f82
 542 #define PHY_VITESSE_INIT10      0x0
 543 #define PHY_REALTEK_INIT_REG1   0x1f
 544 #define PHY_REALTEK_INIT_REG2   0x19
 545 #define PHY_REALTEK_INIT_REG3   0x13
 546 #define PHY_REALTEK_INIT_REG4   0x14
 547 #define PHY_REALTEK_INIT_REG5   0x18
 548 #define PHY_REALTEK_INIT_REG6   0x11
 549 #define PHY_REALTEK_INIT_REG7   0x01
 550 #define PHY_REALTEK_INIT1       0x0000
 551 #define PHY_REALTEK_INIT2       0x8e00
 552 #define PHY_REALTEK_INIT3       0x0001
 553 #define PHY_REALTEK_INIT4       0xad17
 554 #define PHY_REALTEK_INIT5       0xfb54
 555 #define PHY_REALTEK_INIT6       0xf5c7
 556 #define PHY_REALTEK_INIT7       0x1000
 557 #define PHY_REALTEK_INIT8       0x0003
 558 #define PHY_REALTEK_INIT9       0x0008
 559 #define PHY_REALTEK_INIT10      0x0005
 560 #define PHY_REALTEK_INIT11      0x0200
 561 #define PHY_REALTEK_INIT_MSK1   0x0003
 562
 563 #define PHY_GIGABIT     0x0100
 564
 565 #define PHY_TIMEOUT     0x1
 566 #define PHY_ERROR       0x2
 567
 568 #define PHY_100 0x1
 569 #define PHY_1000        0x2
 570 #define PHY_HALF        0x100
 571
 572 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 573 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 574 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 575 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 576 #define NV_PAUSEFRAME_RX_REQ     0x0010
 577 #define NV_PAUSEFRAME_TX_REQ     0x0020
 578 #define NV_PAUSEFRAME_AUTONEG    0x0040
 579
 580 /* MSI/MSI-X defines */
 581 #define NV_MSI_X_MAX_VECTORS  8
 582 #define NV_MSI_X_VECTORS_MASK 0x000f
 583 #define NV_MSI_CAPABLE        0x0010
 584 #define NV_MSI_X_CAPABLE      0x0020
 585 #define NV_MSI_ENABLED        0x0040
 586 #define NV_MSI_X_ENABLED      0x0080
 587
 588 #define NV_MSI_X_VECTOR_ALL   0x0
 589 #define NV_MSI_X_VECTOR_RX    0x0
 590 #define NV_MSI_X_VECTOR_TX    0x1
 591 #define NV_MSI_X_VECTOR_OTHER 0x2
 592
 593 #define NV_MSI_PRIV_OFFSET 0x68
 594 #define NV_MSI_PRIV_VALUE  0xffffffff
 595
 596 #define NV_RESTART_TX         0x1
 597 #define NV_RESTART_RX         0x2
 598
 599 #define NV_TX_LIMIT_COUNT     16
 600
 601 #define NV_DYNAMIC_THRESHOLD        4
 602 #define NV_DYNAMIC_MAX_QUIET_COUNT  2048
 603
 604 /* statistics */
 605 struct nv_ethtool_str {
 606         char name[ETH_GSTRING_LEN];
 607 };
 608
 609 static const struct nv_ethtool_str nv_estats_str[] = {
 610         { "tx_bytes" },
 611         { "tx_zero_rexmt" },
 612         { "tx_one_rexmt" },
 613         { "tx_many_rexmt" },
 614         { "tx_late_collision" },
 615         { "tx_fifo_errors" },
 616         { "tx_carrier_errors" },
 617         { "tx_excess_deferral" },
 618         { "tx_retry_error" },
 619         { "rx_frame_error" },
 620         { "rx_extra_byte" },
 621         { "rx_late_collision" },
 622         { "rx_runt" },
 623         { "rx_frame_too_long" },
 624         { "rx_over_errors" },
 625         { "rx_crc_errors" },
 626         { "rx_frame_align_error" },
 627         { "rx_length_error" },
 628         { "rx_unicast" },
 629         { "rx_multicast" },
 630         { "rx_broadcast" },
 631         { "rx_packets" },
 632         { "rx_errors_total" },
 633         { "tx_errors_total" },
 634
 635         /* version 2 stats */
 636         { "tx_deferral" },
 637         { "tx_packets" },
 638         { "rx_bytes" },
 639         { "tx_pause" },
 640         { "rx_pause" },
 641         { "rx_drop_frame" },
 642
 643         /* version 3 stats */
 644         { "tx_unicast" },
 645         { "tx_multicast" },
 646         { "tx_broadcast" }
 647 };
 648
 649 struct nv_ethtool_stats {
 650         u64 tx_bytes;
 651         u64 tx_zero_rexmt;
 652         u64 tx_one_rexmt;
 653         u64 tx_many_rexmt;
 654         u64 tx_late_collision;
 655         u64 tx_fifo_errors;
 656         u64 tx_carrier_errors;
 657         u64 tx_excess_deferral;
 658         u64 tx_retry_error;
 659         u64 rx_frame_error;
 660         u64 rx_extra_byte;
 661         u64 rx_late_collision;
 662         u64 rx_runt;
 663         u64 rx_frame_too_long;
 664         u64 rx_over_errors;
 665         u64 rx_crc_errors;
 666         u64 rx_frame_align_error;
 667         u64 rx_length_error;
 668         u64 rx_unicast;
 669         u64 rx_multicast;
 670         u64 rx_broadcast;
 671         u64 rx_packets;
 672         u64 rx_errors_total;
 673         u64 tx_errors_total;
 674
 675         /* version 2 stats */
 676         u64 tx_deferral;
 677         u64 tx_packets;
 678         u64 rx_bytes;
 679         u64 tx_pause;
 680         u64 rx_pause;
 681         u64 rx_drop_frame;
 682
 683         /* version 3 stats */
 684         u64 tx_unicast;
 685         u64 tx_multicast;
 686         u64 tx_broadcast;
 687 };
 688
 689 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
 690 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
 691 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
 692
 693 /* diagnostics */
 694 #define NV_TEST_COUNT_BASE 3
 695 #define NV_TEST_COUNT_EXTENDED 4
 696
 697 static const struct nv_ethtool_str nv_etests_str[] = {
 698         { "link      (online/offline)" },
 699         { "register  (offline)       " },
 700         { "interrupt (offline)       " },
 701         { "loopback  (offline)       " }
 702 };
 703
 704 struct register_test {
 705         __u32 reg;
 706         __u32 mask;
 707 };
 708
 709 static const struct register_test nv_registers_test[] = {
 710         { NvRegUnknownSetupReg6, 0x01 },
 711         { NvRegMisc1, 0x03c },
 712         { NvRegOffloadConfig, 0x03ff },
 713         { NvRegMulticastAddrA, 0xffffffff },
 714         { NvRegTxWatermark, 0x0ff },
 715         { NvRegWakeUpFlags, 0x07777 },
 716         { 0,0 }
 717 };
 718
 719 struct nv_skb_map {
 720         struct sk_buff *skb;
 721         dma_addr_t dma;
 722         unsigned int dma_len;
 723         struct ring_desc_ex *first_tx_desc;
 724         struct nv_skb_map *next_tx_ctx;
 725 };
 726
 727 /*
 728  * SMP locking:
 729  * All hardware access under netdev_priv(dev)->lock, except the performance
 730  * critical parts:
 731  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 732  *      by the arch code for interrupts.
 733  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 734  *      needs netdev_priv(dev)->lock :-(
 735  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 736  */
 737
 738 /* in dev: base, irq */
 739 struct fe_priv {
 740         spinlock_t lock;
 741
 742         struct net_device *dev;
 743         struct napi_struct napi;
 744
 745         /* General data:
 746          * Locking: spin_lock(&np->lock); */
 747         struct nv_ethtool_stats estats;
 748         int in_shutdown;
 749         u32 linkspeed;
 750         int duplex;
 751         int autoneg;
 752         int fixed_mode;
 753         int phyaddr;
 754         int wolenabled;
 755         unsigned int phy_oui;
 756         unsigned int phy_model;
 757         unsigned int phy_rev;
 758         u16 gigabit;
 759         int intr_test;
 760         int recover_error;
 761         int quiet_count;
 762
 763         /* General data: RO fields */
 764         dma_addr_t ring_addr;
 765         struct pci_dev *pci_dev;
 766         u32 orig_mac[2];
 767         u32 events;
 768         u32 irqmask;
 769         u32 desc_ver;
 770         u32 txrxctl_bits;
 771         u32 vlanctl_bits;
 772         u32 driver_data;
 773         u32 device_id;
 774         u32 register_size;
 775         int rx_csum;
 776         u32 mac_in_use;
 777         int mgmt_version;
 778         int mgmt_sema;
 779
 780         void __iomem *base;
 781
 782         /* rx specific fields.
 783          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 784          */
 785         union ring_type get_rx, put_rx, first_rx, last_rx;
 786         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
 787         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
 788         struct nv_skb_map *rx_skb;
 789
 790         union ring_type rx_ring;
 791         unsigned int rx_buf_sz;
 792         unsigned int pkt_limit;
 793         struct timer_list oom_kick;
 794         struct timer_list nic_poll;
 795         struct timer_list stats_poll;
 796         u32 nic_poll_irq;
 797         int rx_ring_size;
 798
 799         /* media detection workaround.
 800          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 801          */
 802         int need_linktimer;
 803         unsigned long link_timeout;
 804         /*
 805          * tx specific fields.
 806          */
 807         union ring_type get_tx, put_tx, first_tx, last_tx;
 808         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
 809         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
 810         struct nv_skb_map *tx_skb;
 811
 812         union ring_type tx_ring;
 813         u32 tx_flags;
 814         int tx_ring_size;
 815         int tx_limit;
 816         u32 tx_pkts_in_progress;
 817         struct nv_skb_map *tx_change_owner;
 818         struct nv_skb_map *tx_end_flip;
 819         int tx_stop;
 820
 821         /* vlan fields */
 822         struct vlan_group *vlangrp;
 823
 824         /* msi/msi-x fields */
 825         u32 msi_flags;
 826         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 827
 828         /* flow control */
 829         u32 pause_flags;
 830
 831         /* power saved state */
 832         u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
 833
 834         /* for different msi-x irq type */
 835         char name_rx[IFNAMSIZ + 3];       /* -rx    */
 836         char name_tx[IFNAMSIZ + 3];       /* -tx    */
 837         char name_other[IFNAMSIZ + 6];    /* -other */
 838 };
 839
 840 /*
 841  * Maximum number of loops until we assume that a bit in the irq mask
 842  * is stuck. Overridable with module param.
 843  */
 844 static int max_interrupt_work = 4;
 845
 846 /*
 847  * Optimization can be either throuput mode or cpu mode
 848  *
 849  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 850  * CPU Mode: Interrupts are controlled by a timer.
 851  */
 852 enum {
 853         NV_OPTIMIZATION_MODE_THROUGHPUT,
 854         NV_OPTIMIZATION_MODE_CPU,
 855         NV_OPTIMIZATION_MODE_DYNAMIC
 856 };
 857 static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
 858
 859 /*
 860  * Poll interval for timer irq
 861  *
 862  * This interval determines how frequent an interrupt is generated.
 863  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 864  * Min = 0, and Max = 65535
 865  */
 866 static int poll_interval = -1;
 867
 868 /*
 869  * MSI interrupts
 870  */
 871 enum {
 872         NV_MSI_INT_DISABLED,
 873         NV_MSI_INT_ENABLED
 874 };
 875 static int msi = NV_MSI_INT_ENABLED;
 876
 877 /*
 878  * MSIX interrupts
 879  */
 880 enum {
 881         NV_MSIX_INT_DISABLED,
 882         NV_MSIX_INT_ENABLED
 883 };
 884 static int msix = NV_MSIX_INT_ENABLED;
 885
 886 /*
 887  * DMA 64bit
 888  */
 889 enum {
 890         NV_DMA_64BIT_DISABLED,
 891         NV_DMA_64BIT_ENABLED
 892 };
 893 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 894
 895 /*
 896  * Crossover Detection
 897  * Realtek 8201 phy + some OEM boards do not work properly.
 898  */
 899 enum {
 900         NV_CROSSOVER_DETECTION_DISABLED,
 901         NV_CROSSOVER_DETECTION_ENABLED
 902 };
 903 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
 904
 905 /*
 906  * Power down phy when interface is down (persists through reboot;
 907  * older Linux and other OSes may not power it up again)
 908  */
 909 static int phy_power_down = 0;
 910
 911 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 912 {
 913         return netdev_priv(dev);
 914 }
 915
 916 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 917 {
 918         return ((struct fe_priv *)netdev_priv(dev))->base;
 919 }
 920
 921 static inline void pci_push(u8 __iomem *base)
 922 {
 923         /* force out pending posted writes */
 924         readl(base);
 925 }
 926
 927 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 928 {
 929         return le32_to_cpu(prd->flaglen)
 930                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 931 }
 932
 933 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 934 {
 935         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
 936 }
 937
 938 static bool nv_optimized(struct fe_priv *np)
 939 {
 940         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 941                 return false;
 942         return true;
 943 }
 944
 945 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 946                                 int delay, int delaymax, const char *msg)
 947 {
 948         u8 __iomem *base = get_hwbase(dev);
 949
 950         pci_push(base);
 951         do {
 952                 udelay(delay);
 953                 delaymax -= delay;
 954                 if (delaymax < 0) {
 955                         if (msg)
 956                                 printk("%s", msg);
 957                         return 1;
 958                 }
 959         } while ((readl(base + offset) & mask) != target);
 960         return 0;
 961 }
 962
 963 #define NV_SETUP_RX_RING 0x01
 964 #define NV_SETUP_TX_RING 0x02
 965
 966 static inline u32 dma_low(dma_addr_t addr)
 967 {
 968         return addr;
 969 }
 970
 971 static inline u32 dma_high(dma_addr_t addr)
 972 {
 973         return addr>>31>>1;     /* 0 if 32bit, shift down by 32 if 64bit */
 974 }
 975
 976 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
 977 {
 978         struct fe_priv *np = get_nvpriv(dev);
 979         u8 __iomem *base = get_hwbase(dev);
 980
 981         if (!nv_optimized(np)) {
 982                 if (rxtx_flags & NV_SETUP_RX_RING) {
 983                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
 984                 }
 985                 if (rxtx_flags & NV_SETUP_TX_RING) {
 986                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
 987                 }
 988         } else {
 989                 if (rxtx_flags & NV_SETUP_RX_RING) {
 990                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
 991                         writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
 992                 }
 993                 if (rxtx_flags & NV_SETUP_TX_RING) {
 994                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
 995                         writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
 996                 }
 997         }
 998 }
 999
1000 static void free_rings(struct net_device *dev)
1001 {
1002         struct fe_priv *np = get_nvpriv(dev);
1003
1004         if (!nv_optimized(np)) {
1005                 if (np->rx_ring.orig)
1006                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
1007                                             np->rx_ring.orig, np->ring_addr);
1008         } else {
1009                 if (np->rx_ring.ex)
1010                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1011                                             np->rx_ring.ex, np->ring_addr);
1012         }
1013         if (np->rx_skb)
1014                 kfree(np->rx_skb);
1015         if (np->tx_skb)
1016                 kfree(np->tx_skb);
1017 }
1018
1019 static int using_multi_irqs(struct net_device *dev)
1020 {
1021         struct fe_priv *np = get_nvpriv(dev);
1022
1023         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1024             ((np->msi_flags & NV_MSI_X_ENABLED) &&
1025              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1026                 return 0;
1027         else
1028                 return 1;
1029 }
1030
1031 static void nv_txrx_gate(struct net_device *dev, bool gate)
1032 {
1033         struct fe_priv *np = get_nvpriv(dev);
1034         u8 __iomem *base = get_hwbase(dev);
1035         u32 powerstate;
1036
1037         if (!np->mac_in_use &&
1038             (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1039                 powerstate = readl(base + NvRegPowerState2);
1040                 if (gate)
1041                         powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1042                 else
1043                         powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1044                 writel(powerstate, base + NvRegPowerState2);
1045         }
1046 }
1047
1048 static void nv_enable_irq(struct net_device *dev)
1049 {
1050         struct fe_priv *np = get_nvpriv(dev);
1051
1052         if (!using_multi_irqs(dev)) {
1053                 if (np->msi_flags & NV_MSI_X_ENABLED)
1054                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1055                 else
1056                         enable_irq(np->pci_dev->irq);
1057         } else {
1058                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1059                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1060                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1061         }
1062 }
1063
1064 static void nv_disable_irq(struct net_device *dev)
1065 {
1066         struct fe_priv *np = get_nvpriv(dev);
1067
1068         if (!using_multi_irqs(dev)) {
1069                 if (np->msi_flags & NV_MSI_X_ENABLED)
1070                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1071                 else
1072                         disable_irq(np->pci_dev->irq);
1073         } else {
1074                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1075                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1076                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1077         }
1078 }
1079
1080 /* In MSIX mode, a write to irqmask behaves as XOR */
1081 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1082 {
1083         u8 __iomem *base = get_hwbase(dev);
1084
1085         writel(mask, base + NvRegIrqMask);
1086 }
1087
1088 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1089 {
1090         struct fe_priv *np = get_nvpriv(dev);
1091         u8 __iomem *base = get_hwbase(dev);
1092
1093         if (np->msi_flags & NV_MSI_X_ENABLED) {
1094                 writel(mask, base + NvRegIrqMask);
1095         } else {
1096                 if (np->msi_flags & NV_MSI_ENABLED)
1097                         writel(0, base + NvRegMSIIrqMask);
1098                 writel(0, base + NvRegIrqMask);
1099         }
1100 }
1101
1102 static void nv_napi_enable(struct net_device *dev)
1103 {
1104 #ifdef CONFIG_FORCEDETH_NAPI
1105         struct fe_priv *np = get_nvpriv(dev);
1106
1107         napi_enable(&np->napi);
1108 #endif
1109 }
1110
1111 static void nv_napi_disable(struct net_device *dev)
1112 {
1113 #ifdef CONFIG_FORCEDETH_NAPI
1114         struct fe_priv *np = get_nvpriv(dev);
1115
1116         napi_disable(&np->napi);
1117 #endif
1118 }
1119
1120 #define MII_READ        (-1)
1121 /* mii_rw: read/write a register on the PHY.
1122  *
1123  * Caller must guarantee serialization
1124  */
1125 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1126 {
1127         u8 __iomem *base = get_hwbase(dev);
1128         u32 reg;
1129         int retval;
1130
1131         writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1132
1133         reg = readl(base + NvRegMIIControl);
1134         if (reg & NVREG_MIICTL_INUSE) {
1135                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1136                 udelay(NV_MIIBUSY_DELAY);
1137         }
1138
1139         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1140         if (value != MII_READ) {
1141                 writel(value, base + NvRegMIIData);
1142                 reg |= NVREG_MIICTL_WRITE;
1143         }
1144         writel(reg, base + NvRegMIIControl);
1145
1146         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1147                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1148                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1149                                 dev->name, miireg, addr);
1150                 retval = -1;
1151         } else if (value != MII_READ) {
1152                 /* it was a write operation - fewer failures are detectable */
1153                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1154                                 dev->name, value, miireg, addr);
1155                 retval = 0;
1156         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1157                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1158                                 dev->name, miireg, addr);
1159                 retval = -1;
1160         } else {
1161                 retval = readl(base + NvRegMIIData);
1162                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1163                                 dev->name, miireg, addr, retval);
1164         }
1165
1166         return retval;
1167 }
1168
1169 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1170 {
1171         struct fe_priv *np = netdev_priv(dev);
1172         u32 miicontrol;
1173         unsigned int tries = 0;
1174
1175         miicontrol = BMCR_RESET | bmcr_setup;
1176         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1177                 return -1;
1178         }
1179
1180         /* wait for 500ms */
1181         msleep(500);
1182
1183         /* must wait till reset is deasserted */
1184         while (miicontrol & BMCR_RESET) {
1185                 msleep(10);
1186                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1187                 /* FIXME: 100 tries seem excessive */
1188                 if (tries++ > 100)
1189                         return -1;
1190         }
1191         return 0;
1192 }
1193
1194 static int phy_init(struct net_device *dev)
1195 {
1196         struct fe_priv *np = get_nvpriv(dev);
1197         u8 __iomem *base = get_hwbase(dev);
1198         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1199
1200         /* phy errata for E3016 phy */
1201         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1202                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1203                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1204                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1205                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1206                         return PHY_ERROR;
1207                 }
1208         }
1209         if (np->phy_oui == PHY_OUI_REALTEK) {
1210                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1211                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1212                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1213                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1214                                 return PHY_ERROR;
1215                         }
1216                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1217                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1218                                 return PHY_ERROR;
1219                         }
1220                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1221                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1222                                 return PHY_ERROR;
1223                         }
1224                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1225                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1226                                 return PHY_ERROR;
1227                         }
1228                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1229                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1230                                 return PHY_ERROR;
1231                         }
1232                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1233                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1234                                 return PHY_ERROR;
1235                         }
1236                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1237                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1238                                 return PHY_ERROR;
1239                         }
1240                 }
1241                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1242                     np->phy_rev == PHY_REV_REALTEK_8211C) {
1243                         u32 powerstate = readl(base + NvRegPowerState2);
1244
1245                         /* need to perform hw phy reset */
1246                         powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1247                         writel(powerstate, base + NvRegPowerState2);
1248                         msleep(25);
1249
1250                         powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1251                         writel(powerstate, base + NvRegPowerState2);
1252                         msleep(25);
1253
1254                         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1255                         reg |= PHY_REALTEK_INIT9;
1256                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) {
1257                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1258                                 return PHY_ERROR;
1259                         }
1260                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) {
1261                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1262                                 return PHY_ERROR;
1263                         }
1264                         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1265                         if (!(reg & PHY_REALTEK_INIT11)) {
1266                                 reg |= PHY_REALTEK_INIT11;
1267                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) {
1268                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1269                                         return PHY_ERROR;
1270                                 }
1271                         }
1272                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1273                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1274                                 return PHY_ERROR;
1275                         }
1276                 }
1277                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1278                         if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1279                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1280                                 phy_reserved |= PHY_REALTEK_INIT7;
1281                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1282                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1283                                         return PHY_ERROR;
1284                                 }
1285                         }
1286                 }
1287         }
1288
1289         /* set advertise register */
1290         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1291         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1292         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1293                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1294                 return PHY_ERROR;
1295         }
1296
1297         /* get phy interface type */
1298         phyinterface = readl(base + NvRegPhyInterface);
1299
1300         /* see if gigabit phy */
1301         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1302         if (mii_status & PHY_GIGABIT) {
1303                 np->gigabit = PHY_GIGABIT;
1304                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1305                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1306                 if (phyinterface & PHY_RGMII)
1307                         mii_control_1000 |= ADVERTISE_1000FULL;
1308                 else
1309                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1310
1311                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1312                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1313                         return PHY_ERROR;
1314                 }
1315         }
1316         else
1317                 np->gigabit = 0;
1318
1319         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1320         mii_control |= BMCR_ANENABLE;
1321
1322         if (np->phy_oui == PHY_OUI_REALTEK &&
1323             np->phy_model == PHY_MODEL_REALTEK_8211 &&
1324             np->phy_rev == PHY_REV_REALTEK_8211C) {
1325                 /* start autoneg since we already performed hw reset above */
1326                 mii_control |= BMCR_ANRESTART;
1327                 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1328                         printk(KERN_INFO "%s: phy init failed\n", pci_name(np->pci_dev));
1329                         return PHY_ERROR;
1330                 }
1331         } else {
1332                 /* reset the phy
1333                  * (certain phys need bmcr to be setup with reset)
1334                  */
1335                 if (phy_reset(dev, mii_control)) {
1336                         printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1337                         return PHY_ERROR;
1338                 }
1339         }
1340
1341         /* phy vendor specific configuration */
1342         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1343                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1344                 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1345                 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1346                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1347                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1348                         return PHY_ERROR;
1349                 }
1350                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1351                 phy_reserved |= PHY_CICADA_INIT5;
1352                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1353                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1354                         return PHY_ERROR;
1355                 }
1356         }
1357         if (np->phy_oui == PHY_OUI_CICADA) {
1358                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1359                 phy_reserved |= PHY_CICADA_INIT6;
1360                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1361                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1362                         return PHY_ERROR;
1363                 }
1364         }
1365         if (np->phy_oui == PHY_OUI_VITESSE) {
1366                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1367                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1368                         return PHY_ERROR;
1369                 }
1370                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1371                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1372                         return PHY_ERROR;
1373                 }
1374                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1375                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1376                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1377                         return PHY_ERROR;
1378                 }
1379                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1380                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1381                 phy_reserved |= PHY_VITESSE_INIT3;
1382                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1383                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1384                         return PHY_ERROR;
1385                 }
1386                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1387                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1388                         return PHY_ERROR;
1389                 }
1390                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1391                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1392                         return PHY_ERROR;
1393                 }
1394                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1395                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1396                 phy_reserved |= PHY_VITESSE_INIT3;
1397                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1398                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1399                         return PHY_ERROR;
1400                 }
1401                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1402                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1403                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1404                         return PHY_ERROR;
1405                 }
1406                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1407                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1408                         return PHY_ERROR;
1409                 }
1410                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1411                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1412                         return PHY_ERROR;
1413                 }
1414                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1415                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1416                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1417                         return PHY_ERROR;
1418                 }
1419                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1420                 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1421                 phy_reserved |= PHY_VITESSE_INIT8;
1422                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1423                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1424                         return PHY_ERROR;
1425                 }
1426                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1427                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1428                         return PHY_ERROR;
1429                 }
1430                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1431                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1432                         return PHY_ERROR;
1433                 }
1434         }
1435         if (np->phy_oui == PHY_OUI_REALTEK) {
1436                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1437                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1438                         /* reset could have cleared these out, set them back */
1439                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1440                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1441                                 return PHY_ERROR;
1442                         }
1443                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1444                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1445                                 return PHY_ERROR;
1446                         }
1447                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1448                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1449                                 return PHY_ERROR;
1450                         }
1451                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1452                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1453                                 return PHY_ERROR;
1454                         }
1455                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1456                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1457                                 return PHY_ERROR;
1458                         }
1459                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1460                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1461                                 return PHY_ERROR;
1462                         }
1463                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1464                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1465                                 return PHY_ERROR;
1466                         }
1467                 }
1468                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1469                         if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1470                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1471                                 phy_reserved |= PHY_REALTEK_INIT7;
1472                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1473                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1474                                         return PHY_ERROR;
1475                                 }
1476                         }
1477                         if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1478                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1479                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1480                                         return PHY_ERROR;
1481                                 }
1482                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1483                                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1484                                 phy_reserved |= PHY_REALTEK_INIT3;
1485                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
1486                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1487                                         return PHY_ERROR;
1488                                 }
1489                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1490                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1491                                         return PHY_ERROR;
1492                                 }
1493                         }
1494                 }
1495         }
1496
1497         /* some phys clear out pause advertisment on reset, set it back */
1498         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1499
1500         /* restart auto negotiation, power down phy */
1501         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1502         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1503         if (phy_power_down) {
1504                 mii_control |= BMCR_PDOWN;
1505         }
1506         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1507                 return PHY_ERROR;
1508         }
1509
1510         return 0;
1511 }
1512
1513 static void nv_start_rx(struct net_device *dev)
1514 {
1515         struct fe_priv *np = netdev_priv(dev);
1516         u8 __iomem *base = get_hwbase(dev);
1517         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1518
1519         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1520         /* Already running? Stop it. */
1521         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1522                 rx_ctrl &= ~NVREG_RCVCTL_START;
1523                 writel(rx_ctrl, base + NvRegReceiverControl);
1524                 pci_push(base);
1525         }
1526         writel(np->linkspeed, base + NvRegLinkSpeed);
1527         pci_push(base);
1528         rx_ctrl |= NVREG_RCVCTL_START;
1529         if (np->mac_in_use)
1530                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1531         writel(rx_ctrl, base + NvRegReceiverControl);
1532         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1533                                 dev->name, np->duplex, np->linkspeed);
1534         pci_push(base);
1535 }
1536
1537 static void nv_stop_rx(struct net_device *dev)
1538 {
1539         struct fe_priv *np = netdev_priv(dev);
1540         u8 __iomem *base = get_hwbase(dev);
1541         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1542
1543         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1544         if (!np->mac_in_use)
1545                 rx_ctrl &= ~NVREG_RCVCTL_START;
1546         else
1547                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1548         writel(rx_ctrl, base + NvRegReceiverControl);
1549         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1550                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1551                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1552
1553         udelay(NV_RXSTOP_DELAY2);
1554         if (!np->mac_in_use)
1555                 writel(0, base + NvRegLinkSpeed);
1556 }
1557
1558 static void nv_start_tx(struct net_device *dev)
1559 {
1560         struct fe_priv *np = netdev_priv(dev);
1561         u8 __iomem *base = get_hwbase(dev);
1562         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1563
1564         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1565         tx_ctrl |= NVREG_XMITCTL_START;
1566         if (np->mac_in_use)
1567                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1568         writel(tx_ctrl, base + NvRegTransmitterControl);
1569         pci_push(base);
1570 }
1571
1572 static void nv_stop_tx(struct net_device *dev)
1573 {
1574         struct fe_priv *np = netdev_priv(dev);
1575         u8 __iomem *base = get_hwbase(dev);
1576         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1577
1578         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1579         if (!np->mac_in_use)
1580                 tx_ctrl &= ~NVREG_XMITCTL_START;
1581         else
1582                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1583         writel(tx_ctrl, base + NvRegTransmitterControl);
1584         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1585                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1586                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1587
1588         udelay(NV_TXSTOP_DELAY2);
1589         if (!np->mac_in_use)
1590                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1591                        base + NvRegTransmitPoll);
1592 }
1593
1594 static void nv_start_rxtx(struct net_device *dev)
1595 {
1596         nv_start_rx(dev);
1597         nv_start_tx(dev);
1598 }
1599
1600 static void nv_stop_rxtx(struct net_device *dev)
1601 {
1602         nv_stop_rx(dev);
1603         nv_stop_tx(dev);
1604 }
1605
1606 static void nv_txrx_reset(struct net_device *dev)
1607 {
1608         struct fe_priv *np = netdev_priv(dev);
1609         u8 __iomem *base = get_hwbase(dev);
1610
1611         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1612         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1613         pci_push(base);
1614         udelay(NV_TXRX_RESET_DELAY);
1615         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1616         pci_push(base);
1617 }
1618
1619 static void nv_mac_reset(struct net_device *dev)
1620 {
1621         struct fe_priv *np = netdev_priv(dev);
1622         u8 __iomem *base = get_hwbase(dev);
1623         u32 temp1, temp2, temp3;
1624
1625         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1626
1627         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1628         pci_push(base);
1629
1630         /* save registers since they will be cleared on reset */
1631         temp1 = readl(base + NvRegMacAddrA);
1632         temp2 = readl(base + NvRegMacAddrB);
1633         temp3 = readl(base + NvRegTransmitPoll);
1634
1635         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1636         pci_push(base);
1637         udelay(NV_MAC_RESET_DELAY);
1638         writel(0, base + NvRegMacReset);
1639         pci_push(base);
1640         udelay(NV_MAC_RESET_DELAY);
1641
1642         /* restore saved registers */
1643         writel(temp1, base + NvRegMacAddrA);
1644         writel(temp2, base + NvRegMacAddrB);
1645         writel(temp3, base + NvRegTransmitPoll);
1646
1647         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1648         pci_push(base);
1649 }
1650
1651 static void nv_get_hw_stats(struct net_device *dev)
1652 {
1653         struct fe_priv *np = netdev_priv(dev);
1654         u8 __iomem *base = get_hwbase(dev);
1655
1656         np->estats.tx_bytes += readl(base + NvRegTxCnt);
1657         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1658         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1659         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1660         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1661         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1662         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1663         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1664         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1665         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1666         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1667         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1668         np->estats.rx_runt += readl(base + NvRegRxRunt);
1669         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1670         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1671         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1672         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1673         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1674         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1675         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1676         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1677         np->estats.rx_packets =
1678                 np->estats.rx_unicast +
1679                 np->estats.rx_multicast +
1680                 np->estats.rx_broadcast;
1681         np->estats.rx_errors_total =
1682                 np->estats.rx_crc_errors +
1683                 np->estats.rx_over_errors +
1684                 np->estats.rx_frame_error +
1685                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1686                 np->estats.rx_late_collision +
1687                 np->estats.rx_runt +
1688                 np->estats.rx_frame_too_long;
1689         np->estats.tx_errors_total =
1690                 np->estats.tx_late_collision +
1691                 np->estats.tx_fifo_errors +
1692                 np->estats.tx_carrier_errors +
1693                 np->estats.tx_excess_deferral +
1694                 np->estats.tx_retry_error;
1695
1696         if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1697                 np->estats.tx_deferral += readl(base + NvRegTxDef);
1698                 np->estats.tx_packets += readl(base + NvRegTxFrame);
1699                 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1700                 np->estats.tx_pause += readl(base + NvRegTxPause);
1701                 np->estats.rx_pause += readl(base + NvRegRxPause);
1702                 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1703         }
1704
1705         if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1706                 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1707                 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1708                 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1709         }
1710 }
1711
1712 /*
1713  * nv_get_stats: dev->get_stats function
1714  * Get latest stats value from the nic.
1715  * Called with read_lock(&dev_base_lock) held for read -
1716  * only synchronized against unregister_netdevice.
1717  */
1718 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1719 {
1720         struct fe_priv *np = netdev_priv(dev);
1721
1722         /* If the nic supports hw counters then retrieve latest values */
1723         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
1724                 nv_get_hw_stats(dev);
1725
1726                 /* copy to net_device stats */
1727                 dev->stats.tx_bytes = np->estats.tx_bytes;
1728                 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1729                 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1730                 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1731                 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1732                 dev->stats.rx_errors = np->estats.rx_errors_total;
1733                 dev->stats.tx_errors = np->estats.tx_errors_total;
1734         }
1735
1736         return &dev->stats;
1737 }
1738
1739 /*
1740  * nv_alloc_rx: fill rx ring entries.
1741  * Return 1 if the allocations for the skbs failed and the
1742  * rx engine is without Available descriptors
1743  */
1744 static int nv_alloc_rx(struct net_device *dev)
1745 {
1746         struct fe_priv *np = netdev_priv(dev);
1747         struct ring_desc* less_rx;
1748
1749         less_rx = np->get_rx.orig;
1750         if (less_rx-- == np->first_rx.orig)
1751                 less_rx = np->last_rx.orig;
1752
1753         while (np->put_rx.orig != less_rx) {
1754                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1755                 if (skb) {
1756                         np->put_rx_ctx->skb = skb;
1757                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1758                                                              skb->data,
1759                                                              skb_tailroom(skb),
1760                                                              PCI_DMA_FROMDEVICE);
1761                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1762                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1763                         wmb();
1764                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1765                         if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1766                                 np->put_rx.orig = np->first_rx.orig;
1767                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1768                                 np->put_rx_ctx = np->first_rx_ctx;
1769                 } else {
1770                         return 1;
1771                 }
1772         }
1773         return 0;
1774 }
1775
1776 static int nv_alloc_rx_optimized(struct net_device *dev)
1777 {
1778         struct fe_priv *np = netdev_priv(dev);
1779         struct ring_desc_ex* less_rx;
1780
1781         less_rx = np->get_rx.ex;
1782         if (less_rx-- == np->first_rx.ex)
1783                 less_rx = np->last_rx.ex;
1784
1785         while (np->put_rx.ex != less_rx) {
1786                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1787                 if (skb) {
1788                         np->put_rx_ctx->skb = skb;
1789                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1790                                                              skb->data,
1791                                                              skb_tailroom(skb),
1792                                                              PCI_DMA_FROMDEVICE);
1793                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1794                         np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1795                         np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1796                         wmb();
1797                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1798                         if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1799                                 np->put_rx.ex = np->first_rx.ex;
1800                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1801                                 np->put_rx_ctx = np->first_rx_ctx;
1802                 } else {
1803                         return 1;
1804                 }
1805         }
1806         return 0;
1807 }
1808
1809 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1810 #ifdef CONFIG_FORCEDETH_NAPI
1811 static void nv_do_rx_refill(unsigned long data)
1812 {
1813         struct net_device *dev = (struct net_device *) data;
1814         struct fe_priv *np = netdev_priv(dev);
1815
1816         /* Just reschedule NAPI rx processing */
1817         napi_schedule(&np->napi);
1818 }
1819 #else
1820 static void nv_do_rx_refill(unsigned long data)
1821 {
1822         struct net_device *dev = (struct net_device *) data;
1823         struct fe_priv *np = netdev_priv(dev);
1824         int retcode;
1825
1826         if (!using_multi_irqs(dev)) {
1827                 if (np->msi_flags & NV_MSI_X_ENABLED)
1828                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1829                 else
1830                         disable_irq(np->pci_dev->irq);
1831         } else {
1832                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1833         }
1834         if (!nv_optimized(np))
1835                 retcode = nv_alloc_rx(dev);
1836         else
1837                 retcode = nv_alloc_rx_optimized(dev);
1838         if (retcode) {
1839                 spin_lock_irq(&np->lock);
1840                 if (!np->in_shutdown)
1841                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1842                 spin_unlock_irq(&np->lock);
1843         }
1844         if (!using_multi_irqs(dev)) {
1845                 if (np->msi_flags & NV_MSI_X_ENABLED)
1846                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1847                 else
1848                         enable_irq(np->pci_dev->irq);
1849         } else {
1850                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1851         }
1852 }
1853 #endif
1854
1855 static void nv_init_rx(struct net_device *dev)
1856 {
1857         struct fe_priv *np = netdev_priv(dev);
1858         int i;
1859
1860         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1861
1862         if (!nv_optimized(np))
1863                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1864         else
1865                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1866         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1867         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1868
1869         for (i = 0; i < np->rx_ring_size; i++) {
1870                 if (!nv_optimized(np)) {
1871                         np->rx_ring.orig[i].flaglen = 0;
1872                         np->rx_ring.orig[i].buf = 0;
1873                 } else {
1874                         np->rx_ring.ex[i].flaglen = 0;
1875                         np->rx_ring.ex[i].txvlan = 0;
1876                         np->rx_ring.ex[i].bufhigh = 0;
1877                         np->rx_ring.ex[i].buflow = 0;
1878                 }
1879                 np->rx_skb[i].skb = NULL;
1880                 np->rx_skb[i].dma = 0;
1881         }
1882 }
1883
1884 static void nv_init_tx(struct net_device *dev)
1885 {
1886         struct fe_priv *np = netdev_priv(dev);
1887         int i;
1888
1889         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1890
1891         if (!nv_optimized(np))
1892                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1893         else
1894                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1895         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1896         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1897         np->tx_pkts_in_progress = 0;
1898         np->tx_change_owner = NULL;
1899         np->tx_end_flip = NULL;
1900         np->tx_stop = 0;
1901
1902         for (i = 0; i < np->tx_ring_size; i++) {
1903                 if (!nv_optimized(np)) {
1904                         np->tx_ring.orig[i].flaglen = 0;
1905                         np->tx_ring.orig[i].buf = 0;
1906                 } else {
1907                         np->tx_ring.ex[i].flaglen = 0;
1908                         np->tx_ring.ex[i].txvlan = 0;
1909                         np->tx_ring.ex[i].bufhigh = 0;
1910                         np->tx_ring.ex[i].buflow = 0;
1911                 }
1912                 np->tx_skb[i].skb = NULL;
1913                 np->tx_skb[i].dma = 0;
1914                 np->tx_skb[i].dma_len = 0;
1915                 np->tx_skb[i].first_tx_desc = NULL;
1916                 np->tx_skb[i].next_tx_ctx = NULL;
1917         }
1918 }
1919
1920 static int nv_init_ring(struct net_device *dev)
1921 {
1922         struct fe_priv *np = netdev_priv(dev);
1923
1924         nv_init_tx(dev);
1925         nv_init_rx(dev);
1926
1927         if (!nv_optimized(np))
1928                 return nv_alloc_rx(dev);
1929         else
1930                 return nv_alloc_rx_optimized(dev);
1931 }
1932
1933 static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
1934 {
1935         struct fe_priv *np = netdev_priv(dev);
1936
1937         if (tx_skb->dma) {
1938                 pci_unmap_page(np->pci_dev, tx_skb->dma,
1939                                tx_skb->dma_len,
1940                                PCI_DMA_TODEVICE);
1941                 tx_skb->dma = 0;
1942         }
1943         if (tx_skb->skb) {
1944                 dev_kfree_skb_any(tx_skb->skb);
1945                 tx_skb->skb = NULL;
1946                 return 1;
1947         } else {
1948                 return 0;
1949         }
1950 }
1951
1952 static void nv_drain_tx(struct net_device *dev)
1953 {
1954         struct fe_priv *np = netdev_priv(dev);
1955         unsigned int i;
1956
1957         for (i = 0; i < np->tx_ring_size; i++) {
1958                 if (!nv_optimized(np)) {
1959                         np->tx_ring.orig[i].flaglen = 0;
1960                         np->tx_ring.orig[i].buf = 0;
1961                 } else {
1962                         np->tx_ring.ex[i].flaglen = 0;
1963                         np->tx_ring.ex[i].txvlan = 0;
1964                         np->tx_ring.ex[i].bufhigh = 0;
1965                         np->tx_ring.ex[i].buflow = 0;
1966                 }
1967                 if (nv_release_txskb(dev, &np->tx_skb[i]))
1968                         dev->stats.tx_dropped++;
1969                 np->tx_skb[i].dma = 0;
1970                 np->tx_skb[i].dma_len = 0;
1971                 np->tx_skb[i].first_tx_desc = NULL;
1972                 np->tx_skb[i].next_tx_ctx = NULL;
1973         }
1974         np->tx_pkts_in_progress = 0;
1975         np->tx_change_owner = NULL;
1976         np->tx_end_flip = NULL;
1977 }
1978
1979 static void nv_drain_rx(struct net_device *dev)
1980 {
1981         struct fe_priv *np = netdev_priv(dev);
1982         int i;
1983
1984         for (i = 0; i < np->rx_ring_size; i++) {
1985                 if (!nv_optimized(np)) {
1986                         np->rx_ring.orig[i].flaglen = 0;
1987                         np->rx_ring.orig[i].buf = 0;
1988                 } else {
1989                         np->rx_ring.ex[i].flaglen = 0;
1990                         np->rx_ring.ex[i].txvlan = 0;
1991                         np->rx_ring.ex[i].bufhigh = 0;
1992                         np->rx_ring.ex[i].buflow = 0;
1993                 }
1994                 wmb();
1995                 if (np->rx_skb[i].skb) {
1996                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1997                                          (skb_end_pointer(np->rx_skb[i].skb) -
1998                                           np->rx_skb[i].skb->data),
1999                                          PCI_DMA_FROMDEVICE);
2000                         dev_kfree_skb(np->rx_skb[i].skb);
2001                         np->rx_skb[i].skb = NULL;
2002                 }
2003         }
2004 }
2005
2006 static void nv_drain_rxtx(struct net_device *dev)
2007 {
2008         nv_drain_tx(dev);
2009         nv_drain_rx(dev);
2010 }
2011
2012 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
2013 {
2014         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
2015 }
2016
2017 static void nv_legacybackoff_reseed(struct net_device *dev)
2018 {
2019         u8 __iomem *base = get_hwbase(dev);
2020         u32 reg;
2021         u32 low;
2022         int tx_status = 0;
2023
2024         reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
2025         get_random_bytes(&low, sizeof(low));
2026         reg |= low & NVREG_SLOTTIME_MASK;
2027
2028         /* Need to stop tx before change takes effect.
2029          * Caller has already gained np->lock.
2030          */
2031         tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
2032         if (tx_status)
2033                 nv_stop_tx(dev);
2034         nv_stop_rx(dev);
2035         writel(reg, base + NvRegSlotTime);
2036         if (tx_status)
2037                 nv_start_tx(dev);
2038         nv_start_rx(dev);
2039 }
2040
2041 /* Gear Backoff Seeds */
2042 #define BACKOFF_SEEDSET_ROWS    8
2043 #define BACKOFF_SEEDSET_LFSRS   15
2044
2045 /* Known Good seed sets */
2046 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2047     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2048     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2049     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2050     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2051     {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2052     {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2053     {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800,  84},
2054     {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
2055
2056 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2057     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2058     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2059     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2060     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2061     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2062     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2063     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2064     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
2065
2066 static void nv_gear_backoff_reseed(struct net_device *dev)
2067 {
2068         u8 __iomem *base = get_hwbase(dev);
2069         u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2070         u32 temp, seedset, combinedSeed;
2071         int i;
2072
2073         /* Setup seed for free running LFSR */
2074         /* We are going to read the time stamp counter 3 times
2075            and swizzle bits around to increase randomness */
2076         get_random_bytes(&miniseed1, sizeof(miniseed1));
2077         miniseed1 &= 0x0fff;
2078         if (miniseed1 == 0)
2079                 miniseed1 = 0xabc;
2080
2081         get_random_bytes(&miniseed2, sizeof(miniseed2));
2082         miniseed2 &= 0x0fff;
2083         if (miniseed2 == 0)
2084                 miniseed2 = 0xabc;
2085         miniseed2_reversed =
2086                 ((miniseed2 & 0xF00) >> 8) |
2087                  (miniseed2 & 0x0F0) |
2088                  ((miniseed2 & 0x00F) << 8);
2089
2090         get_random_bytes(&miniseed3, sizeof(miniseed3));
2091         miniseed3 &= 0x0fff;
2092         if (miniseed3 == 0)
2093                 miniseed3 = 0xabc;
2094         miniseed3_reversed =
2095                 ((miniseed3 & 0xF00) >> 8) |
2096                  (miniseed3 & 0x0F0) |
2097                  ((miniseed3 & 0x00F) << 8);
2098
2099         combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2100                        (miniseed2 ^ miniseed3_reversed);
2101
2102         /* Seeds can not be zero */
2103         if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2104                 combinedSeed |= 0x08;
2105         if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2106                 combinedSeed |= 0x8000;
2107
2108         /* No need to disable tx here */
2109         temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2110         temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2111         temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2112         writel(temp,base + NvRegBackOffControl);
2113
2114         /* Setup seeds for all gear LFSRs. */
2115         get_random_bytes(&seedset, sizeof(seedset));
2116         seedset = seedset % BACKOFF_SEEDSET_ROWS;
2117         for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++)
2118         {
2119                 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2120                 temp |= main_seedset[seedset][i-1] & 0x3ff;
2121                 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2122                 writel(temp, base + NvRegBackOffControl);
2123         }
2124 }
2125
2126 /*
2127  * nv_start_xmit: dev->hard_start_xmit function
2128  * Called with netif_tx_lock held.
2129  */
2130 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2131 {
2132         struct fe_priv *np = netdev_priv(dev);
2133         u32 tx_flags = 0;
2134         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2135         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2136         unsigned int i;
2137         u32 offset = 0;
2138         u32 bcnt;
2139         u32 size = skb->len-skb->data_len;
2140         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2141         u32 empty_slots;
2142         struct ring_desc* put_tx;
2143         struct ring_desc* start_tx;
2144         struct ring_desc* prev_tx;
2145         struct nv_skb_map* prev_tx_ctx;
2146         unsigned long flags;
2147
2148         /* add fragments to entries count */
2149         for (i = 0; i < fragments; i++) {
2150                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2151                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2152         }
2153
2154         spin_lock_irqsave(&np->lock, flags);
2155         empty_slots = nv_get_empty_tx_slots(np);
2156         if (unlikely(empty_slots <= entries)) {
2157                 netif_stop_queue(dev);
2158                 np->tx_stop = 1;
2159                 spin_unlock_irqrestore(&np->lock, flags);
2160                 return NETDEV_TX_BUSY;
2161         }
2162         spin_unlock_irqrestore(&np->lock, flags);
2163
2164         start_tx = put_tx = np->put_tx.orig;
2165
2166         /* setup the header buffer */
2167         do {
2168                 prev_tx = put_tx;
2169                 prev_tx_ctx = np->put_tx_ctx;
2170                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2171                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2172                                                 PCI_DMA_TODEVICE);
2173                 np->put_tx_ctx->dma_len = bcnt;
2174                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2175                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2176
2177                 tx_flags = np->tx_flags;
2178                 offset += bcnt;
2179                 size -= bcnt;
2180                 if (unlikely(put_tx++ == np->last_tx.orig))
2181                         put_tx = np->first_tx.orig;
2182                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2183                         np->put_tx_ctx = np->first_tx_ctx;
2184         } while (size);
2185
2186         /* setup the fragments */
2187         for (i = 0; i < fragments; i++) {
2188                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2189                 u32 size = frag->size;
2190                 offset = 0;
2191
2192                 do {
2193                         prev_tx = put_tx;
2194                         prev_tx_ctx = np->put_tx_ctx;
2195                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2196                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2197                                                            PCI_DMA_TODEVICE);
2198                         np->put_tx_ctx->dma_len = bcnt;
2199                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2200                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2201
2202                         offset += bcnt;
2203                         size -= bcnt;
2204                         if (unlikely(put_tx++ == np->last_tx.orig))
2205                                 put_tx = np->first_tx.orig;
2206                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2207                                 np->put_tx_ctx = np->first_tx_ctx;
2208                 } while (size);
2209         }
2210
2211         /* set last fragment flag  */
2212         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2213
2214         /* save skb in this slot's context area */
2215         prev_tx_ctx->skb = skb;
2216
2217         if (skb_is_gso(skb))
2218                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2219         else
2220                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2221                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2222
2223         spin_lock_irqsave(&np->lock, flags);
2224
2225         /* set tx flags */
2226         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2227         np->put_tx.orig = put_tx;
2228
2229         spin_unlock_irqrestore(&np->lock, flags);
2230
2231         dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
2232                 dev->name, entries, tx_flags_extra);
2233         {
2234                 int j;
2235                 for (j=0; j<64; j++) {
2236                         if ((j%16) == 0)
2237                                 dprintk("\n%03x:", j);
2238                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2239                 }
2240                 dprintk("\n");
2241         }
2242
2243         dev->trans_start = jiffies;
2244         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2245         return NETDEV_TX_OK;
2246 }
2247
2248 static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
2249 {
2250         struct fe_priv *np = netdev_priv(dev);
2251         u32 tx_flags = 0;
2252         u32 tx_flags_extra;
2253         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2254         unsigned int i;
2255         u32 offset = 0;
2256         u32 bcnt;
2257         u32 size = skb->len-skb->data_len;
2258         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2259         u32 empty_slots;
2260         struct ring_desc_ex* put_tx;
2261         struct ring_desc_ex* start_tx;
2262         struct ring_desc_ex* prev_tx;
2263         struct nv_skb_map* prev_tx_ctx;
2264         struct nv_skb_map* start_tx_ctx;
2265         unsigned long flags;
2266
2267         /* add fragments to entries count */
2268         for (i = 0; i < fragments; i++) {
2269                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2270                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2271         }
2272
2273         spin_lock_irqsave(&np->lock, flags);
2274         empty_slots = nv_get_empty_tx_slots(np);
2275         if (unlikely(empty_slots <= entries)) {
2276                 netif_stop_queue(dev);
2277                 np->tx_stop = 1;
2278                 spin_unlock_irqrestore(&np->lock, flags);
2279                 return NETDEV_TX_BUSY;
2280         }
2281         spin_unlock_irqrestore(&np->lock, flags);
2282
2283         start_tx = put_tx = np->put_tx.ex;
2284         start_tx_ctx = np->put_tx_ctx;
2285
2286         /* setup the header buffer */
2287         do {
2288                 prev_tx = put_tx;
2289                 prev_tx_ctx = np->put_tx_ctx;
2290                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2291                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2292                                                 PCI_DMA_TODEVICE);
2293                 np->put_tx_ctx->dma_len = bcnt;
2294                 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2295                 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2296                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2297
2298                 tx_flags = NV_TX2_VALID;
2299                 offset += bcnt;
2300                 size -= bcnt;
2301                 if (unlikely(put_tx++ == np->last_tx.ex))
2302                         put_tx = np->first_tx.ex;
2303                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2304                         np->put_tx_ctx = np->first_tx_ctx;
2305         } while (size);
2306
2307         /* setup the fragments */
2308         for (i = 0; i < fragments; i++) {
2309                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2310                 u32 size = frag->size;
2311                 offset = 0;
2312
2313                 do {
2314                         prev_tx = put_tx;
2315                         prev_tx_ctx = np->put_tx_ctx;
2316                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2317                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2318                                                            PCI_DMA_TODEVICE);
2319                         np->put_tx_ctx->dma_len = bcnt;
2320                         put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2321                         put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2322                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2323
2324                         offset += bcnt;
2325                         size -= bcnt;
2326                         if (unlikely(put_tx++ == np->last_tx.ex))
2327                                 put_tx = np->first_tx.ex;
2328                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2329                                 np->put_tx_ctx = np->first_tx_ctx;
2330                 } while (size);
2331         }
2332
2333         /* set last fragment flag  */
2334         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2335
2336         /* save skb in this slot's context area */
2337         prev_tx_ctx->skb = skb;
2338
2339         if (skb_is_gso(skb))
2340                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2341         else
2342                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2343                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2344
2345         /* vlan tag */
2346         if (likely(!np->vlangrp)) {
2347                 start_tx->txvlan = 0;
2348         } else {
2349                 if (vlan_tx_tag_present(skb))
2350                         start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
2351                 else
2352                         start_tx->txvlan = 0;
2353         }
2354
2355         spin_lock_irqsave(&np->lock, flags);
2356
2357         if (np->tx_limit) {
2358                 /* Limit the number of outstanding tx. Setup all fragments, but
2359                  * do not set the VALID bit on the first descriptor. Save a pointer
2360                  * to that descriptor and also for next skb_map element.
2361                  */
2362
2363                 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2364                         if (!np->tx_change_owner)
2365                                 np->tx_change_owner = start_tx_ctx;
2366
2367                         /* remove VALID bit */
2368                         tx_flags &= ~NV_TX2_VALID;
2369                         start_tx_ctx->first_tx_desc = start_tx;
2370                         start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2371                         np->tx_end_flip = np->put_tx_ctx;
2372                 } else {
2373                         np->tx_pkts_in_progress++;
2374                 }
2375         }
2376
2377         /* set tx flags */
2378         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2379         np->put_tx.ex = put_tx;
2380
2381         spin_unlock_irqrestore(&np->lock, flags);
2382
2383         dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2384                 dev->name, entries, tx_flags_extra);
2385         {
2386                 int j;
2387                 for (j=0; j<64; j++) {
2388                         if ((j%16) == 0)
2389                                 dprintk("\n%03x:", j);
2390                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2391                 }
2392                 dprintk("\n");
2393         }
2394
2395         dev->trans_start = jiffies;
2396         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2397         return NETDEV_TX_OK;
2398 }
2399
2400 static inline void nv_tx_flip_ownership(struct net_device *dev)
2401 {
2402         struct fe_priv *np = netdev_priv(dev);
2403
2404         np->tx_pkts_in_progress--;
2405         if (np->tx_change_owner) {
2406                 np->tx_change_owner->first_tx_desc->flaglen |=
2407                         cpu_to_le32(NV_TX2_VALID);
2408                 np->tx_pkts_in_progress++;
2409
2410                 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2411                 if (np->tx_change_owner == np->tx_end_flip)
2412                         np->tx_change_owner = NULL;
2413
2414                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2415         }
2416 }
2417
2418 /*
2419  * nv_tx_done: check for completed packets, release the skbs.
2420  *
2421  * Caller must own np->lock.
2422  */
2423 static int nv_tx_done(struct net_device *dev, int limit)
2424 {
2425         struct fe_priv *np = netdev_priv(dev);
2426         u32 flags;
2427         int tx_work = 0;
2428         struct ring_desc* orig_get_tx = np->get_tx.orig;
2429
2430         while ((np->get_tx.orig != np->put_tx.orig) &&
2431                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2432                (tx_work < limit)) {
2433
2434                 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2435                                         dev->name, flags);
2436
2437                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2438                                np->get_tx_ctx->dma_len,
2439                                PCI_DMA_TODEVICE);
2440                 np->get_tx_ctx->dma = 0;
2441
2442                 if (np->desc_ver == DESC_VER_1) {
2443                         if (flags & NV_TX_LASTPACKET) {
2444                                 if (flags & NV_TX_ERROR) {
2445                                         if (flags & NV_TX_UNDERFLOW)
2446                                                 dev->stats.tx_fifo_errors++;
2447                                         if (flags & NV_TX_CARRIERLOST)
2448                                                 dev->stats.tx_carrier_errors++;
2449                                         if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2450                                                 nv_legacybackoff_reseed(dev);
2451                                         dev->stats.tx_errors++;
2452                                 } else {
2453                                         dev->stats.tx_packets++;
2454                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2455                                 }
2456                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2457                                 np->get_tx_ctx->skb = NULL;
2458                                 tx_work++;
2459                         }
2460                 } else {
2461                         if (flags & NV_TX2_LASTPACKET) {
2462                                 if (flags & NV_TX2_ERROR) {
2463                                         if (flags & NV_TX2_UNDERFLOW)
2464                                                 dev->stats.tx_fifo_errors++;
2465                                         if (flags & NV_TX2_CARRIERLOST)
2466                                                 dev->stats.tx_carrier_errors++;
2467                                         if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2468                                                 nv_legacybackoff_reseed(dev);
2469                                         dev->stats.tx_errors++;
2470                                 } else {
2471                                         dev->stats.tx_packets++;
2472                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2473                                 }
2474                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2475                                 np->get_tx_ctx->skb = NULL;
2476                                 tx_work++;
2477                         }
2478                 }
2479                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2480                         np->get_tx.orig = np->first_tx.orig;
2481                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2482                         np->get_tx_ctx = np->first_tx_ctx;
2483         }
2484         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2485                 np->tx_stop = 0;
2486                 netif_wake_queue(dev);
2487         }
2488         return tx_work;
2489 }
2490
2491 static int nv_tx_done_optimized(struct net_device *dev, int limit)
2492 {
2493         struct fe_priv *np = netdev_priv(dev);
2494         u32 flags;
2495         int tx_work = 0;
2496         struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
2497
2498         while ((np->get_tx.ex != np->put_tx.ex) &&
2499                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
2500                (tx_work < limit)) {
2501
2502                 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2503                                         dev->name, flags);
2504
2505                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2506                                np->get_tx_ctx->dma_len,
2507                                PCI_DMA_TODEVICE);
2508                 np->get_tx_ctx->dma = 0;
2509
2510                 if (flags & NV_TX2_LASTPACKET) {
2511                         if (!(flags & NV_TX2_ERROR))
2512                                 dev->stats.tx_packets++;
2513                         else {
2514                                 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2515                                         if (np->driver_data & DEV_HAS_GEAR_MODE)
2516                                                 nv_gear_backoff_reseed(dev);
2517                                         else
2518                                                 nv_legacybackoff_reseed(dev);
2519                                 }
2520                         }
2521
2522                         dev_kfree_skb_any(np->get_tx_ctx->skb);
2523                         np->get_tx_ctx->skb = NULL;
2524                         tx_work++;
2525
2526                         if (np->tx_limit) {
2527                                 nv_tx_flip_ownership(dev);
2528                         }
2529                 }
2530                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2531                         np->get_tx.ex = np->first_tx.ex;
2532                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2533                         np->get_tx_ctx = np->first_tx_ctx;
2534         }
2535         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2536                 np->tx_stop = 0;
2537                 netif_wake_queue(dev);
2538         }
2539         return tx_work;
2540 }
2541
2542 /*
2543  * nv_tx_timeout: dev->tx_timeout function
2544  * Called with netif_tx_lock held.
2545  */
2546 static void nv_tx_timeout(struct net_device *dev)
2547 {
2548         struct fe_priv *np = netdev_priv(dev);
2549         u8 __iomem *base = get_hwbase(dev);
2550         u32 status;
2551         union ring_type put_tx;
2552         int saved_tx_limit;
2553
2554         if (np->msi_flags & NV_MSI_X_ENABLED)
2555                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2556         else
2557                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2558
2559         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
2560
2561         {
2562                 int i;
2563
2564                 printk(KERN_INFO "%s: Ring at %lx\n",
2565                        dev->name, (unsigned long)np->ring_addr);
2566                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
2567                 for (i=0;i<=np->register_size;i+= 32) {
2568                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2569                                         i,
2570                                         readl(base + i + 0), readl(base + i + 4),
2571                                         readl(base + i + 8), readl(base + i + 12),
2572                                         readl(base + i + 16), readl(base + i + 20),
2573                                         readl(base + i + 24), readl(base + i + 28));
2574                 }
2575                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
2576                 for (i=0;i<np->tx_ring_size;i+= 4) {
2577                         if (!nv_optimized(np)) {
2578                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2579                                        i,
2580                                        le32_to_cpu(np->tx_ring.orig[i].buf),
2581                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
2582                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
2583                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2584                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
2585                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2586                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
2587                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2588                         } else {
2589                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2590                                        i,
2591                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2592                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
2593                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
2594                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2595                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2596                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2597                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2598                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2599                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2600                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2601                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2602                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2603                         }
2604                 }
2605         }
2606
2607         spin_lock_irq(&np->lock);
2608
2609         /* 1) stop tx engine */
2610         nv_stop_tx(dev);
2611
2612         /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2613         saved_tx_limit = np->tx_limit;
2614         np->tx_limit = 0; /* prevent giving HW any limited pkts */
2615         np->tx_stop = 0;  /* prevent waking tx queue */
2616         if (!nv_optimized(np))
2617                 nv_tx_done(dev, np->tx_ring_size);
2618         else
2619                 nv_tx_done_optimized(dev, np->tx_ring_size);
2620
2621         /* save current HW postion */
2622         if (np->tx_change_owner)
2623                 put_tx.ex = np->tx_change_owner->first_tx_desc;
2624         else
2625                 put_tx = np->put_tx;
2626
2627         /* 3) clear all tx state */
2628         nv_drain_tx(dev);
2629         nv_init_tx(dev);
2630
2631         /* 4) restore state to current HW position */
2632         np->get_tx = np->put_tx = put_tx;
2633         np->tx_limit = saved_tx_limit;
2634
2635         /* 5) restart tx engine */
2636         nv_start_tx(dev);
2637         netif_wake_queue(dev);
2638         spin_unlock_irq(&np->lock);
2639 }
2640
2641 /*
2642  * Called when the nic notices a mismatch between the actual data len on the
2643  * wire and the len indicated in the 802 header
2644  */
2645 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2646 {
2647         int hdrlen;     /* length of the 802 header */
2648         int protolen;   /* length as stored in the proto field */
2649
2650         /* 1) calculate len according to header */
2651         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2652                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2653                 hdrlen = VLAN_HLEN;
2654         } else {
2655                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2656                 hdrlen = ETH_HLEN;
2657         }
2658         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2659                                 dev->name, datalen, protolen, hdrlen);
2660         if (protolen > ETH_DATA_LEN)
2661                 return datalen; /* Value in proto field not a len, no checks possible */
2662
2663         protolen += hdrlen;
2664         /* consistency checks: */
2665         if (datalen > ETH_ZLEN) {
2666                 if (datalen >= protolen) {
2667                         /* more data on wire than in 802 header, trim of
2668                          * additional data.
2669                          */
2670                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2671                                         dev->name, protolen);
2672                         return protolen;
2673                 } else {
2674                         /* less data on wire than mentioned in header.
2675                          * Discard the packet.
2676                          */
2677                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2678                                         dev->name);
2679                         return -1;
2680                 }
2681         } else {
2682                 /* short packet. Accept only if 802 values are also short */
2683                 if (protolen > ETH_ZLEN) {
2684                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2685                                         dev->name);
2686                         return -1;
2687                 }
2688                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2689                                 dev->name, datalen);
2690                 return datalen;
2691         }
2692 }
2693
2694 static int nv_rx_process(struct net_device *dev, int limit)
2695 {
2696         struct fe_priv *np = netdev_priv(dev);
2697         u32 flags;
2698         int rx_work = 0;
2699         struct sk_buff *skb;
2700         int len;
2701
2702         while((np->get_rx.orig != np->put_rx.orig) &&
2703               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2704                 (rx_work < limit)) {
2705
2706                 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2707                                         dev->name, flags);
2708
2709                 /*
2710                  * the packet is for us - immediately tear down the pci mapping.
2711                  * TODO: check if a prefetch of the first cacheline improves
2712                  * the performance.
2713                  */
2714                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2715                                 np->get_rx_ctx->dma_len,
2716                                 PCI_DMA_FROMDEVICE);
2717                 skb = np->get_rx_ctx->skb;
2718                 np->get_rx_ctx->skb = NULL;
2719
2720                 {
2721                         int j;
2722                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2723                         for (j=0; j<64; j++) {
2724                                 if ((j%16) == 0)
2725                                         dprintk("\n%03x:", j);
2726                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2727                         }
2728                         dprintk("\n");
2729                 }
2730                 /* look at what we actually got: */
2731                 if (np->desc_ver == DESC_VER_1) {
2732                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2733                                 len = flags & LEN_MASK_V1;
2734                                 if (unlikely(flags & NV_RX_ERROR)) {
2735                                         if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2736                                                 len = nv_getlen(dev, skb->data, len);
2737                                                 if (len < 0) {
2738                                                         dev->stats.rx_errors++;
2739                                                         dev_kfree_skb(skb);
2740                                                         goto next_pkt;
2741                                                 }
2742                                         }
2743                                         /* framing errors are soft errors */
2744                                         else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2745                                                 if (flags & NV_RX_SUBSTRACT1) {
2746                                                         len--;
2747                                                 }
2748                                         }
2749                                         /* the rest are hard errors */
2750                                         else {
2751                                                 if (flags & NV_RX_MISSEDFRAME)
2752                                                         dev->stats.rx_missed_errors++;
2753                                                 if (flags & NV_RX_CRCERR)
2754                                                         dev->stats.rx_crc_errors++;
2755                                                 if (flags & NV_RX_OVERFLOW)
2756                                                         dev->stats.rx_over_errors++;
2757                                                 dev->stats.rx_errors++;
2758                                                 dev_kfree_skb(skb);
2759                                                 goto next_pkt;
2760                                         }
2761                                 }
2762                         } else {
2763                                 dev_kfree_skb(skb);
2764                                 goto next_pkt;
2765                         }
2766                 } else {
2767                         if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2768                                 len = flags & LEN_MASK_V2;
2769                                 if (unlikely(flags & NV_RX2_ERROR)) {
2770                                         if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2771                                                 len = nv_getlen(dev, skb->data, len);
2772                                                 if (len < 0) {
2773                                                         dev->stats.rx_errors++;
2774                                                         dev_kfree_skb(skb);
2775                                                         goto next_pkt;
2776                                                 }
2777                                         }
2778                                         /* framing errors are soft errors */
2779                                         else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2780                                                 if (flags & NV_RX2_SUBSTRACT1) {
2781                                                         len--;
2782                                                 }
2783                                         }
2784                                         /* the rest are hard errors */
2785                                         else {
2786                                                 if (flags & NV_RX2_CRCERR)
2787                                                         dev->stats.rx_crc_errors++;
2788                                                 if (flags & NV_RX2_OVERFLOW)
2789                                                         dev->stats.rx_over_errors++;
2790                                                 dev->stats.rx_errors++;
2791                                                 dev_kfree_skb(skb);
2792                                                 goto next_pkt;
2793                                         }
2794                                 }
2795                                 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2796                                     ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2797                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2798                         } else {
2799                                 dev_kfree_skb(skb);
2800                                 goto next_pkt;
2801                         }
2802                 }
2803                 /* got a valid packet - forward it to the network core */
2804                 skb_put(skb, len);
2805                 skb->protocol = eth_type_trans(skb, dev);
2806                 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2807                                         dev->name, len, skb->protocol);
2808 #ifdef CONFIG_FORCEDETH_NAPI
2809                 netif_receive_skb(skb);
2810 #else
2811                 netif_rx(skb);
2812 #endif
2813                 dev->stats.rx_packets++;
2814                 dev->stats.rx_bytes += len;
2815 next_pkt:
2816                 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2817                         np->get_rx.orig = np->first_rx.orig;
2818                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2819                         np->get_rx_ctx = np->first_rx_ctx;
2820
2821                 rx_work++;
2822         }
2823
2824         return rx_work;
2825 }
2826
2827 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2828 {
2829         struct fe_priv *np = netdev_priv(dev);
2830         u32 flags;
2831         u32 vlanflags = 0;
2832         int rx_work = 0;
2833         struct sk_buff *skb;
2834         int len;
2835
2836         while((np->get_rx.ex != np->put_rx.ex) &&
2837               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2838               (rx_work < limit)) {
2839
2840                 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2841                                         dev->name, flags);
2842
2843                 /*
2844                  * the packet is for us - immediately tear down the pci mapping.
2845                  * TODO: check if a prefetch of the first cacheline improves
2846                  * the performance.
2847                  */
2848                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2849                                 np->get_rx_ctx->dma_len,
2850                                 PCI_DMA_FROMDEVICE);
2851                 skb = np->get_rx_ctx->skb;
2852                 np->get_rx_ctx->skb = NULL;
2853
2854                 {
2855                         int j;
2856                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2857                         for (j=0; j<64; j++) {
2858                                 if ((j%16) == 0)
2859                                         dprintk("\n%03x:", j);
2860                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2861                         }
2862                         dprintk("\n");
2863                 }
2864                 /* look at what we actually got: */
2865                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2866                         len = flags & LEN_MASK_V2;
2867                         if (unlikely(flags & NV_RX2_ERROR)) {
2868                                 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2869                                         len = nv_getlen(dev, skb->data, len);
2870                                         if (len < 0) {
2871                                                 dev_kfree_skb(skb);
2872                                                 goto next_pkt;
2873                                         }
2874                                 }
2875                                 /* framing errors are soft errors */
2876                                 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2877                                         if (flags & NV_RX2_SUBSTRACT1) {
2878                                                 len--;
2879                                         }
2880                                 }
2881                                 /* the rest are hard errors */
2882                                 else {
2883                                         dev_kfree_skb(skb);
2884                                         goto next_pkt;
2885                                 }
2886                         }
2887
2888                         if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2889                             ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2890                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2891
2892                         /* got a valid packet - forward it to the network core */
2893                         skb_put(skb, len);
2894                         skb->protocol = eth_type_trans(skb, dev);
2895                         prefetch(skb->data);
2896
2897                         dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2898                                 dev->name, len, skb->protocol);
2899
2900                         if (likely(!np->vlangrp)) {
2901 #ifdef CONFIG_FORCEDETH_NAPI
2902                                 netif_receive_skb(skb);
2903 #else
2904                                 netif_rx(skb);
2905 #endif
2906                         } else {
2907                                 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2908                                 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2909 #ifdef CONFIG_FORCEDETH_NAPI
2910                                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
2911                                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
2912 #else
2913                                         vlan_hwaccel_rx(skb, np->vlangrp,
2914                                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
2915 #endif
2916                                 } else {
2917 #ifdef CONFIG_FORCEDETH_NAPI
2918                                         netif_receive_skb(skb);
2919 #else
2920                                         netif_rx(skb);
2921 #endif
2922                                 }
2923                         }
2924
2925                         dev->stats.rx_packets++;
2926                         dev->stats.rx_bytes += len;
2927                 } else {
2928                         dev_kfree_skb(skb);
2929                 }
2930 next_pkt:
2931                 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2932                         np->get_rx.ex = np->first_rx.ex;
2933                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2934                         np->get_rx_ctx = np->first_rx_ctx;
2935
2936                 rx_work++;
2937         }
2938
2939         return rx_work;
2940 }
2941
2942 static void set_bufsize(struct net_device *dev)
2943 {
2944         struct fe_priv *np = netdev_priv(dev);
2945
2946         if (dev->mtu <= ETH_DATA_LEN)
2947                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2948         else
2949                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2950 }
2951
2952 /*
2953  * nv_change_mtu: dev->change_mtu function
2954  * Called with dev_base_lock held for read.
2955  */
2956 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2957 {
2958         struct fe_priv *np = netdev_priv(dev);
2959         int old_mtu;
2960
2961         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2962                 return -EINVAL;
2963
2964         old_mtu = dev->mtu;
2965         dev->mtu = new_mtu;
2966
2967         /* return early if the buffer sizes will not change */
2968         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2969                 return 0;
2970         if (old_mtu == new_mtu)
2971                 return 0;
2972
2973         /* synchronized against open : rtnl_lock() held by caller */
2974         if (netif_running(dev)) {
2975                 u8 __iomem *base = get_hwbase(dev);
2976                 /*
2977                  * It seems that the nic preloads valid ring entries into an
2978                  * internal buffer. The procedure for flushing everything is
2979                  * guessed, there is probably a simpler approach.
2980                  * Changing the MTU is a rare event, it shouldn't matter.
2981                  */
2982                 nv_disable_irq(dev);
2983                 nv_napi_disable(dev);
2984                 netif_tx_lock_bh(dev);
2985                 netif_addr_lock(dev);
2986                 spin_lock(&np->lock);
2987                 /* stop engines */
2988                 nv_stop_rxtx(dev);
2989                 nv_txrx_reset(dev);
2990                 /* drain rx queue */
2991                 nv_drain_rxtx(dev);
2992                 /* reinit driver view of the rx queue */
2993                 set_bufsize(dev);
2994                 if (nv_init_ring(dev)) {
2995                         if (!np->in_shutdown)
2996                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2997                 }
2998                 /* reinit nic view of the rx queue */
2999                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3000                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3001                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3002                         base + NvRegRingSizes);
3003                 pci_push(base);
3004                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3005                 pci_push(base);
3006
3007                 /* restart rx engine */
3008                 nv_start_rxtx(dev);
3009                 spin_unlock(&np->lock);
3010                 netif_addr_unlock(dev);
3011                 netif_tx_unlock_bh(dev);
3012                 nv_napi_enable(dev);
3013                 nv_enable_irq(dev);
3014         }
3015         return 0;
3016 }
3017
3018 static void nv_copy_mac_to_hw(struct net_device *dev)
3019 {
3020         u8 __iomem *base = get_hwbase(dev);
3021         u32 mac[2];
3022
3023         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
3024                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
3025         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
3026
3027         writel(mac[0], base + NvRegMacAddrA);
3028         writel(mac[1], base + NvRegMacAddrB);
3029 }
3030
3031 /*
3032  * nv_set_mac_address: dev->set_mac_address function
3033  * Called with rtnl_lock() held.
3034  */
3035 static int nv_set_mac_address(struct net_device *dev, void *addr)
3036 {
3037         struct fe_priv *np = netdev_priv(dev);
3038         struct sockaddr *macaddr = (struct sockaddr*)addr;
3039
3040         if (!is_valid_ether_addr(macaddr->sa_data))
3041                 return -EADDRNOTAVAIL;
3042
3043         /* synchronized against open : rtnl_lock() held by caller */
3044         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
3045
3046         if (netif_running(dev)) {
3047                 netif_tx_lock_bh(dev);
3048                 netif_addr_lock(dev);
3049                 spin_lock_irq(&np->lock);
3050
3051                 /* stop rx engine */
3052                 nv_stop_rx(dev);
3053
3054                 /* set mac address */
3055                 nv_copy_mac_to_hw(dev);
3056
3057                 /* restart rx engine */
3058                 nv_start_rx(dev);
3059                 spin_unlock_irq(&np->lock);
3060                 netif_addr_unlock(dev);
3061                 netif_tx_unlock_bh(dev);
3062         } else {
3063                 nv_copy_mac_to_hw(dev);
3064         }
3065         return 0;
3066 }
3067
3068 /*
3069  * nv_set_multicast: dev->set_multicast function
3070  * Called with netif_tx_lock held.
3071  */
3072 static void nv_set_multicast(struct net_device *dev)
3073 {
3074         struct fe_priv *np = netdev_priv(dev);
3075         u8 __iomem *base = get_hwbase(dev);
3076         u32 addr[2];
3077         u32 mask[2];
3078         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
3079
3080         memset(addr, 0, sizeof(addr));
3081         memset(mask, 0, sizeof(mask));
3082
3083         if (dev->flags & IFF_PROMISC) {
3084                 pff |= NVREG_PFF_PROMISC;
3085         } else {
3086                 pff |= NVREG_PFF_MYADDR;
3087
3088                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
3089                         u32 alwaysOff[2];
3090                         u32 alwaysOn[2];
3091
3092                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3093                         if (dev->flags & IFF_ALLMULTI) {
3094                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3095                         } else {
3096                                 struct dev_mc_list *walk;
3097
3098                                 walk = dev->mc_list;
3099                                 while (walk != NULL) {
3100                                         u32 a, b;
3101                                         a = le32_to_cpu(*(__le32 *) walk->dmi_addr);
3102                                         b = le16_to_cpu(*(__le16 *) (&walk->dmi_addr[4]));
3103                                         alwaysOn[0] &= a;
3104                                         alwaysOff[0] &= ~a;
3105                                         alwaysOn[1] &= b;
3106                                         alwaysOff[1] &= ~b;
3107                                         walk = walk->next;
3108                                 }
3109                         }
3110                         addr[0] = alwaysOn[0];
3111                         addr[1] = alwaysOn[1];
3112                         mask[0] = alwaysOn[0] | alwaysOff[0];
3113                         mask[1] = alwaysOn[1] | alwaysOff[1];
3114                 } else {
3115                         mask[0] = NVREG_MCASTMASKA_NONE;
3116                         mask[1] = NVREG_MCASTMASKB_NONE;
3117                 }
3118         }
3119         addr[0] |= NVREG_MCASTADDRA_FORCE;
3120         pff |= NVREG_PFF_ALWAYS;
3121         spin_lock_irq(&np->lock);
3122         nv_stop_rx(dev);
3123         writel(addr[0], base + NvRegMulticastAddrA);
3124         writel(addr[1], base + NvRegMulticastAddrB);
3125         writel(mask[0], base + NvRegMulticastMaskA);
3126         writel(mask[1], base + NvRegMulticastMaskB);
3127         writel(pff, base + NvRegPacketFilterFlags);
3128         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
3129                 dev->name);
3130         nv_start_rx(dev);
3131         spin_unlock_irq(&np->lock);
3132 }
3133
3134 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
3135 {
3136         struct fe_priv *np = netdev_priv(dev);
3137         u8 __iomem *base = get_hwbase(dev);
3138
3139         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3140
3141         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3142                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3143                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3144                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3145                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3146                 } else {
3147                         writel(pff, base + NvRegPacketFilterFlags);
3148                 }
3149         }
3150         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3151                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3152                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3153                         u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3154                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3155                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3156                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3157                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3158                                 /* limit the number of tx pause frames to a default of 8 */
3159                                 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3160                         }
3161                         writel(pause_enable,  base + NvRegTxPauseFrame);
3162                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3163                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3164                 } else {
3165                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
3166                         writel(regmisc, base + NvRegMisc1);
3167                 }
3168         }
3169 }
3170
3171 /**
3172  * nv_update_linkspeed: Setup the MAC according to the link partner
3173  * @dev: Network device to be configured
3174  *
3175  * The function queries the PHY and checks if there is a link partner.
3176  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3177  * set to 10 MBit HD.
3178  *
3179  * The function returns 0 if there is no link partner and 1 if there is
3180  * a good link partner.
3181  */
3182 static int nv_update_linkspeed(struct net_device *dev)
3183 {
3184         struct fe_priv *np = netdev_priv(dev);
3185         u8 __iomem *base = get_hwbase(dev);
3186         int adv = 0;
3187         int lpa = 0;
3188         int adv_lpa, adv_pause, lpa_pause;
3189         int newls = np->linkspeed;
3190         int newdup = np->duplex;
3191         int mii_status;
3192         int retval = 0;
3193         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3194         u32 txrxFlags = 0;
3195         u32 phy_exp;
3196
3197         /* BMSR_LSTATUS is latched, read it twice:
3198          * we want the current value.
3199          */
3200         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3201         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3202
3203         if (!(mii_status & BMSR_LSTATUS)) {
3204                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
3205                                 dev->name);
3206                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3207                 newdup = 0;
3208                 retval = 0;
3209                 goto set_speed;
3210         }
3211
3212         if (np->autoneg == 0) {
3213                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
3214                                 dev->name, np->fixed_mode);
3215                 if (np->fixed_mode & LPA_100FULL) {
3216                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3217                         newdup = 1;
3218                 } else if (np->fixed_mode & LPA_100HALF) {
3219                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3220                         newdup = 0;
3221                 } else if (np->fixed_mode & LPA_10FULL) {
3222                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3223                         newdup = 1;
3224                 } else {
3225                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3226                         newdup = 0;
3227                 }
3228                 retval = 1;
3229                 goto set_speed;
3230         }
3231         /* check auto negotiation is complete */
3232         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3233                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3234                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3235                 newdup = 0;
3236                 retval = 0;
3237                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
3238                 goto set_speed;
3239         }
3240
3241         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3242         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3243         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
3244                                 dev->name, adv, lpa);
3245
3246         retval = 1;
3247         if (np->gigabit == PHY_GIGABIT) {
3248                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3249                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3250
3251                 if ((control_1000 & ADVERTISE_1000FULL) &&
3252                         (status_1000 & LPA_1000FULL)) {
3253                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
3254                                 dev->name);
3255                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3256                         newdup = 1;
3257                         goto set_speed;
3258                 }
3259         }
3260
3261         /* FIXME: handle parallel detection properly */
3262         adv_lpa = lpa & adv;
3263         if (adv_lpa & LPA_100FULL) {
3264                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3265                 newdup = 1;
3266         } else if (adv_lpa & LPA_100HALF) {
3267                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3268                 newdup = 0;
3269         } else if (adv_lpa & LPA_10FULL) {
3270                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3271                 newdup = 1;
3272         } else if (adv_lpa & LPA_10HALF) {
3273                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3274                 newdup = 0;
3275         } else {
3276                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
3277                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3278                 newdup = 0;
3279         }
3280
3281 set_speed:
3282         if (np->duplex == newdup && np->linkspeed == newls)
3283                 return retval;
3284
3285         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
3286                         dev->name, np->linkspeed, np->duplex, newls, newdup);
3287
3288         np->duplex = newdup;
3289         np->linkspeed = newls;
3290
3291         /* The transmitter and receiver must be restarted for safe update */
3292         if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3293                 txrxFlags |= NV_RESTART_TX;
3294                 nv_stop_tx(dev);
3295         }
3296         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3297                 txrxFlags |= NV_RESTART_RX;
3298                 nv_stop_rx(dev);
3299         }
3300
3301         if (np->gigabit == PHY_GIGABIT) {
3302                 phyreg = readl(base + NvRegSlotTime);
3303                 phyreg &= ~(0x3FF00);
3304                 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3305                     ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3306                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3307                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3308                         phyreg |= NVREG_SLOTTIME_1000_FULL;
3309                 writel(phyreg, base + NvRegSlotTime);
3310         }
3311
3312         phyreg = readl(base + NvRegPhyInterface);
3313         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3314         if (np->duplex == 0)
3315                 phyreg |= PHY_HALF;
3316         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3317                 phyreg |= PHY_100;
3318         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3319                 phyreg |= PHY_1000;
3320         writel(phyreg, base + NvRegPhyInterface);
3321
3322         phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3323         if (phyreg & PHY_RGMII) {
3324                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3325                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3326                 } else {
3327                         if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3328                                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3329                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3330                                 else
3331                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3332                         } else {
3333                                 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3334                         }
3335                 }
3336         } else {
3337                 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3338                         txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3339                 else
3340                         txreg = NVREG_TX_DEFERRAL_DEFAULT;
3341         }
3342         writel(txreg, base + NvRegTxDeferral);
3343
3344         if (np->desc_ver == DESC_VER_1) {
3345                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3346         } else {
3347                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3348                         txreg = NVREG_TX_WM_DESC2_3_1000;
3349                 else
3350                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3351         }
3352         writel(txreg, base + NvRegTxWatermark);
3353
3354         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
3355                 base + NvRegMisc1);
3356         pci_push(base);
3357         writel(np->linkspeed, base + NvRegLinkSpeed);
3358         pci_push(base);
3359
3360         pause_flags = 0;
3361         /* setup pause frame */
3362         if (np->duplex != 0) {
3363                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3364                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
3365                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
3366
3367                         switch (adv_pause) {
3368                         case ADVERTISE_PAUSE_CAP:
3369                                 if (lpa_pause & LPA_PAUSE_CAP) {
3370                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3371                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3372                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3373                                 }
3374                                 break;
3375                         case ADVERTISE_PAUSE_ASYM:
3376                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
3377                                 {
3378                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3379                                 }
3380                                 break;
3381                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
3382                                 if (lpa_pause & LPA_PAUSE_CAP)
3383                                 {
3384                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
3385                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3386                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3387                                 }
3388                                 if (lpa_pause == LPA_PAUSE_ASYM)
3389                                 {
3390                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3391                                 }
3392                                 break;
3393                         }
3394                 } else {
3395                         pause_flags = np->pause_flags;
3396                 }
3397         }
3398         nv_update_pause(dev, pause_flags);
3399
3400         if (txrxFlags & NV_RESTART_TX)
3401                 nv_start_tx(dev);
3402         if (txrxFlags & NV_RESTART_RX)
3403                 nv_start_rx(dev);
3404
3405         return retval;
3406 }
3407
3408 static void nv_linkchange(struct net_device *dev)
3409 {
3410         if (nv_update_linkspeed(dev)) {
3411                 if (!netif_carrier_ok(dev)) {
3412                         netif_carrier_on(dev);
3413                         printk(KERN_INFO "%s: link up.\n", dev->name);
3414                         nv_txrx_gate(dev, false);
3415                         nv_start_rx(dev);
3416                 }
3417         } else {
3418                 if (netif_carrier_ok(dev)) {
3419                         netif_carrier_off(dev);
3420                         printk(KERN_INFO "%s: link down.\n", dev->name);
3421                         nv_txrx_gate(dev, true);
3422                         nv_stop_rx(dev);
3423                 }
3424         }
3425 }
3426
3427 static void nv_link_irq(struct net_device *dev)
3428 {
3429         u8 __iomem *base = get_hwbase(dev);
3430         u32 miistat;
3431
3432         miistat = readl(base + NvRegMIIStatus);
3433         writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3434         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3435
3436         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3437                 nv_linkchange(dev);
3438         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
3439 }
3440
3441 static void nv_msi_workaround(struct fe_priv *np)
3442 {
3443
3444         /* Need to toggle the msi irq mask within the ethernet device,
3445          * otherwise, future interrupts will not be detected.
3446          */
3447         if (np->msi_flags & NV_MSI_ENABLED) {
3448                 u8 __iomem *base = np->base;
3449
3450                 writel(0, base + NvRegMSIIrqMask);
3451                 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3452         }
3453 }
3454
3455 static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3456 {
3457         struct fe_priv *np = netdev_priv(dev);
3458
3459         if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3460                 if (total_work > NV_DYNAMIC_THRESHOLD) {
3461                         /* transition to poll based interrupts */
3462                         np->quiet_count = 0;
3463                         if (np->irqmask != NVREG_IRQMASK_CPU) {
3464                                 np->irqmask = NVREG_IRQMASK_CPU;
3465                                 return 1;
3466                         }
3467                 } else {
3468                         if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3469                                 np->quiet_count++;
3470                         } else {
3471                                 /* reached a period of low activity, switch
3472                                    to per tx/rx packet interrupts */
3473                                 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3474                                         np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3475                                         return 1;
3476                                 }
3477                         }
3478                 }
3479         }
3480         return 0;
3481 }
3482
3483 static irqreturn_t nv_nic_irq(int foo, void *data)
3484 {
3485         struct net_device *dev = (struct net_device *) data;
3486         struct fe_priv *np = netdev_priv(dev);
3487         u8 __iomem *base = get_hwbase(dev);
3488 #ifndef CONFIG_FORCEDETH_NAPI
3489         int total_work = 0;
3490         int loop_count = 0;
3491 #endif
3492
3493         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
3494
3495         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3496                 np->events = readl(base + NvRegIrqStatus);
3497                 writel(np->events, base + NvRegIrqStatus);
3498         } else {
3499                 np->events = readl(base + NvRegMSIXIrqStatus);
3500                 writel(np->events, base + NvRegMSIXIrqStatus);
3501         }
3502         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
3503         if (!(np->events & np->irqmask))
3504                 return IRQ_NONE;
3505
3506         nv_msi_workaround(np);
3507
3508 #ifdef CONFIG_FORCEDETH_NAPI
3509         napi_schedule(&np->napi);
3510
3511         /* Disable furthur irq's
3512            (msix not enabled with napi) */
3513         writel(0, base + NvRegIrqMask);
3514
3515 #else
3516         do
3517         {
3518                 int work = 0;
3519                 if ((work = nv_rx_process(dev, RX_WORK_PER_LOOP))) {
3520                         if (unlikely(nv_alloc_rx(dev))) {
3521                                 spin_lock(&np->lock);
3522                                 if (!np->in_shutdown)
3523                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3524                                 spin_unlock(&np->lock);
3525                         }
3526                 }
3527
3528                 spin_lock(&np->lock);
3529                 work += nv_tx_done(dev, TX_WORK_PER_LOOP);
3530                 spin_unlock(&np->lock);
3531
3532                 if (!work)
3533                         break;
3534
3535                 total_work += work;
3536
3537                 loop_count++;
3538         }
3539         while (loop_count < max_interrupt_work);
3540
3541         if (nv_change_interrupt_mode(dev, total_work)) {
3542                 /* setup new irq mask */
3543                 writel(np->irqmask, base + NvRegIrqMask);
3544         }
3545
3546         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3547                 spin_lock(&np->lock);
3548                 nv_link_irq(dev);
3549                 spin_unlock(&np->lock);
3550         }
3551         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3552                 spin_lock(&np->lock);
3553                 nv_linkchange(dev);
3554                 spin_unlock(&np->lock);
3555                 np->link_timeout = jiffies + LINK_TIMEOUT;
3556         }
3557         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3558                 spin_lock(&np->lock);
3559                 /* disable interrupts on the nic */
3560                 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3561                         writel(0, base + NvRegIrqMask);
3562                 else
3563                         writel(np->irqmask, base + NvRegIrqMask);
3564                 pci_push(base);
3565
3566                 if (!np->in_shutdown) {
3567                         np->nic_poll_irq = np->irqmask;
3568                         np->recover_error = 1;
3569                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3570                 }
3571                 spin_unlock(&np->lock);
3572         }
3573 #endif
3574         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3575
3576         return IRQ_HANDLED;
3577 }
3578
3579 /**
3580  * All _optimized functions are used to help increase performance
3581  * (reduce CPU and increase throughput). They use descripter version 3,
3582  * compiler directives, and reduce memory accesses.
3583  */
3584 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3585 {
3586         struct net_device *dev = (struct net_device *) data;
3587         struct fe_priv *np = netdev_priv(dev);
3588         u8 __iomem *base = get_hwbase(dev);
3589 #ifndef CONFIG_FORCEDETH_NAPI
3590         int total_work = 0;
3591         int loop_count = 0;
3592 #endif
3593
3594         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3595
3596         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3597                 np->events = readl(base + NvRegIrqStatus);
3598                 writel(np->events, base + NvRegIrqStatus);
3599         } else {
3600                 np->events = readl(base + NvRegMSIXIrqStatus);
3601                 writel(np->events, base + NvRegMSIXIrqStatus);
3602         }
3603         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
3604         if (!(np->events & np->irqmask))
3605                 return IRQ_NONE;
3606
3607         nv_msi_workaround(np);
3608
3609 #ifdef CONFIG_FORCEDETH_NAPI
3610         napi_schedule(&np->napi);
3611
3612         /* Disable furthur irq's
3613            (msix not enabled with napi) */
3614         writel(0, base + NvRegIrqMask);
3615
3616 #else
3617         do
3618         {
3619                 int work = 0;
3620                 if ((work = nv_rx_process_optimized(dev, RX_WORK_PER_LOOP))) {
3621                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3622                                 spin_lock(&np->lock);
3623                                 if (!np->in_shutdown)
3624                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3625                                 spin_unlock(&np->lock);
3626                         }
3627                 }
3628
3629                 spin_lock(&np->lock);
3630                 work += nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3631                 spin_unlock(&np->lock);
3632
3633                 if (!work)
3634                         break;
3635
3636                 total_work += work;
3637
3638                 loop_count++;
3639         }
3640         while (loop_count < max_interrupt_work);
3641
3642         if (nv_change_interrupt_mode(dev, total_work)) {
3643                 /* setup new irq mask */
3644                 writel(np->irqmask, base + NvRegIrqMask);
3645         }
3646
3647         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3648                 spin_lock(&np->lock);
3649                 nv_link_irq(dev);
3650                 spin_unlock(&np->lock);
3651         }
3652         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3653                 spin_lock(&np->lock);
3654                 nv_linkchange(dev);
3655                 spin_unlock(&np->lock);
3656                 np->link_timeout = jiffies + LINK_TIMEOUT;
3657         }
3658         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3659                 spin_lock(&np->lock);
3660                 /* disable interrupts on the nic */
3661                 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3662                         writel(0, base + NvRegIrqMask);
3663                 else
3664                         writel(np->irqmask, base + NvRegIrqMask);
3665                 pci_push(base);
3666
3667                 if (!np->in_shutdown) {
3668                         np->nic_poll_irq = np->irqmask;
3669                         np->recover_error = 1;
3670                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3671                 }
3672                 spin_unlock(&np->lock);
3673         }
3674
3675 #endif
3676         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3677
3678         return IRQ_HANDLED;
3679 }
3680
3681 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3682 {
3683         struct net_device *dev = (struct net_device *) data;
3684         struct fe_priv *np = netdev_priv(dev);
3685         u8 __iomem *base = get_hwbase(dev);
3686         u32 events;
3687         int i;
3688         unsigned long flags;
3689
3690         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3691
3692         for (i=0; ; i++) {
3693                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3694                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3695                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3696                 if (!(events & np->irqmask))
3697                         break;
3698
3699                 spin_lock_irqsave(&np->lock, flags);
3700                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3701                 spin_unlock_irqrestore(&np->lock, flags);
3702
3703                 if (unlikely(i > max_interrupt_work)) {
3704                         spin_lock_irqsave(&np->lock, flags);
3705                         /* disable interrupts on the nic */
3706                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3707                         pci_push(base);
3708
3709                         if (!np->in_shutdown) {
3710                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3711                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3712                         }
3713                         spin_unlock_irqrestore(&np->lock, flags);
3714                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3715                         break;
3716                 }
3717
3718         }
3719         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3720
3721         return IRQ_RETVAL(i);
3722 }
3723
3724 #ifdef CONFIG_FORCEDETH_NAPI
3725 static int nv_napi_poll(struct napi_struct *napi, int budget)
3726 {
3727         struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3728         struct net_device *dev = np->dev;
3729         u8 __iomem *base = get_hwbase(dev);
3730         unsigned long flags;
3731         int retcode;
3732         int tx_work, rx_work;
3733
3734         if (!nv_optimized(np)) {
3735                 spin_lock_irqsave(&np->lock, flags);
3736                 tx_work = nv_tx_done(dev, np->tx_ring_size);
3737                 spin_unlock_irqrestore(&np->lock, flags);
3738
3739                 rx_work = nv_rx_process(dev, budget);
3740                 retcode = nv_alloc_rx(dev);
3741         } else {
3742                 spin_lock_irqsave(&np->lock, flags);
3743                 tx_work = nv_tx_done_optimized(dev, np->tx_ring_size);
3744                 spin_unlock_irqrestore(&np->lock, flags);
3745
3746                 rx_work = nv_rx_process_optimized(dev, budget);
3747                 retcode = nv_alloc_rx_optimized(dev);
3748         }
3749
3750         if (retcode) {
3751                 spin_lock_irqsave(&np->lock, flags);
3752                 if (!np->in_shutdown)
3753                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3754                 spin_unlock_irqrestore(&np->lock, flags);
3755         }
3756
3757         nv_change_interrupt_mode(dev, tx_work + rx_work);
3758
3759         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3760                 spin_lock_irqsave(&np->lock, flags);
3761                 nv_link_irq(dev);
3762                 spin_unlock_irqrestore(&np->lock, flags);
3763         }
3764         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3765                 spin_lock_irqsave(&np->lock, flags);
3766                 nv_linkchange(dev);
3767                 spin_unlock_irqrestore(&np->lock, flags);
3768                 np->link_timeout = jiffies + LINK_TIMEOUT;
3769         }
3770         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3771                 spin_lock_irqsave(&np->lock, flags);
3772                 if (!np->in_shutdown) {
3773                         np->nic_poll_irq = np->irqmask;
3774                         np->recover_error = 1;
3775                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3776                 }
3777                 spin_unlock_irqrestore(&np->lock, flags);
3778                 napi_complete(napi);
3779                 return rx_work;
3780         }
3781
3782         if (rx_work < budget) {
3783                 /* re-enable interrupts
3784                    (msix not enabled in napi) */
3785                 napi_complete(napi);
3786
3787                 writel(np->irqmask, base + NvRegIrqMask);
3788         }
3789         return rx_work;
3790 }
3791 #endif
3792
3793 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3794 {
3795         struct net_device *dev = (struct net_device *) data;
3796         struct fe_priv *np = netdev_priv(dev);
3797         u8 __iomem *base = get_hwbase(dev);
3798         u32 events;
3799         int i;
3800         unsigned long flags;
3801
3802         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3803
3804         for (i=0; ; i++) {
3805                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3806                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3807                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3808                 if (!(events & np->irqmask))
3809                         break;
3810
3811                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3812                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3813                                 spin_lock_irqsave(&np->lock, flags);
3814                                 if (!np->in_shutdown)
3815                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3816                                 spin_unlock_irqrestore(&np->lock, flags);
3817                         }
3818                 }
3819
3820                 if (unlikely(i > max_interrupt_work)) {
3821                         spin_lock_irqsave(&np->lock, flags);
3822                         /* disable interrupts on the nic */
3823                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3824                         pci_push(base);
3825
3826                         if (!np->in_shutdown) {
3827                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3828                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3829                         }
3830                         spin_unlock_irqrestore(&np->lock, flags);
3831                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3832                         break;
3833                 }
3834         }
3835         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3836
3837         return IRQ_RETVAL(i);
3838 }
3839
3840 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3841 {
3842         struct net_device *dev = (struct net_device *) data;
3843         struct fe_priv *np = netdev_priv(dev);
3844         u8 __iomem *base = get_hwbase(dev);
3845         u32 events;
3846         int i;
3847         unsigned long flags;
3848
3849         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3850
3851         for (i=0; ; i++) {
3852                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3853                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3854                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3855                 if (!(events & np->irqmask))
3856                         break;
3857
3858                 /* check tx in case we reached max loop limit in tx isr */
3859                 spin_lock_irqsave(&np->lock, flags);
3860                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3861                 spin_unlock_irqrestore(&np->lock, flags);
3862
3863                 if (events & NVREG_IRQ_LINK) {
3864                         spin_lock_irqsave(&np->lock, flags);
3865                         nv_link_irq(dev);
3866                         spin_unlock_irqrestore(&np->lock, flags);
3867                 }
3868                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3869                         spin_lock_irqsave(&np->lock, flags);
3870                         nv_linkchange(dev);
3871                         spin_unlock_irqrestore(&np->lock, flags);
3872                         np->link_timeout = jiffies + LINK_TIMEOUT;
3873                 }
3874                 if (events & NVREG_IRQ_RECOVER_ERROR) {
3875                         spin_lock_irq(&np->lock);
3876                         /* disable interrupts on the nic */
3877                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3878                         pci_push(base);
3879
3880                         if (!np->in_shutdown) {
3881                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3882                                 np->recover_error = 1;
3883                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3884                         }
3885                         spin_unlock_irq(&np->lock);
3886                         break;
3887                 }
3888                 if (unlikely(i > max_interrupt_work)) {
3889                         spin_lock_irqsave(&np->lock, flags);
3890                         /* disable interrupts on the nic */
3891                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3892                         pci_push(base);
3893
3894                         if (!np->in_shutdown) {
3895                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3896                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3897                         }
3898                         spin_unlock_irqrestore(&np->lock, flags);
3899                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3900                         break;
3901                 }
3902
3903         }
3904         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3905
3906         return IRQ_RETVAL(i);
3907 }
3908
3909 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3910 {
3911         struct net_device *dev = (struct net_device *) data;
3912         struct fe_priv *np = netdev_priv(dev);
3913         u8 __iomem *base = get_hwbase(dev);
3914         u32 events;
3915
3916         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3917
3918         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3919                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3920                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3921         } else {
3922                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3923                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3924         }
3925         pci_push(base);
3926         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3927         if (!(events & NVREG_IRQ_TIMER))
3928                 return IRQ_RETVAL(0);
3929
3930         nv_msi_workaround(np);
3931
3932         spin_lock(&np->lock);
3933         np->intr_test = 1;
3934         spin_unlock(&np->lock);
3935
3936         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3937
3938         return IRQ_RETVAL(1);
3939 }
3940
3941 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3942 {
3943         u8 __iomem *base = get_hwbase(dev);
3944         int i;
3945         u32 msixmap = 0;
3946
3947         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3948          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3949          * the remaining 8 interrupts.
3950          */
3951         for (i = 0; i < 8; i++) {
3952                 if ((irqmask >> i) & 0x1) {
3953                         msixmap |= vector << (i << 2);
3954                 }
3955         }
3956         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3957
3958         msixmap = 0;
3959         for (i = 0; i < 8; i++) {
3960                 if ((irqmask >> (i + 8)) & 0x1) {
3961                         msixmap |= vector << (i << 2);
3962                 }
3963         }
3964         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3965 }
3966
3967 static int nv_request_irq(struct net_device *dev, int intr_test)
3968 {
3969         struct fe_priv *np = get_nvpriv(dev);
3970         u8 __iomem *base = get_hwbase(dev);
3971         int ret = 1;
3972         int i;
3973         irqreturn_t (*handler)(int foo, void *data);
3974
3975         if (intr_test) {
3976                 handler = nv_nic_irq_test;
3977         } else {
3978                 if (nv_optimized(np))
3979                         handler = nv_nic_irq_optimized;
3980                 else
3981                         handler = nv_nic_irq;
3982         }
3983
3984         if (np->msi_flags & NV_MSI_X_CAPABLE) {
3985                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3986                         np->msi_x_entry[i].entry = i;
3987                 }
3988                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3989                         np->msi_flags |= NV_MSI_X_ENABLED;
3990                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3991                                 /* Request irq for rx handling */
3992                                 sprintf(np->name_rx, "%s-rx", dev->name);
3993                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3994                                                 &nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
3995                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3996                                         pci_disable_msix(np->pci_dev);
3997                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3998                                         goto out_err;
3999                                 }
4000                                 /* Request irq for tx handling */
4001                                 sprintf(np->name_tx, "%s-tx", dev->name);
4002                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
4003                                                 &nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
4004                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
4005                                         pci_disable_msix(np->pci_dev);
4006                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
4007                                         goto out_free_rx;
4008                                 }
4009                                 /* Request irq for link and timer handling */
4010                                 sprintf(np->name_other, "%s-other", dev->name);
4011                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
4012                                                 &nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
4013                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
4014                                         pci_disable_msix(np->pci_dev);
4015                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
4016                                         goto out_free_tx;
4017                                 }
4018                                 /* map interrupts to their respective vector */
4019                                 writel(0, base + NvRegMSIXMap0);
4020                                 writel(0, base + NvRegMSIXMap1);
4021                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
4022                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
4023                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
4024                         } else {
4025                                 /* Request irq for all interrupts */
4026                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
4027                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
4028                                         pci_disable_msix(np->pci_dev);
4029                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
4030                                         goto out_err;
4031                                 }
4032
4033                                 /* map interrupts to vector 0 */
4034                                 writel(0, base + NvRegMSIXMap0);
4035                                 writel(0, base + NvRegMSIXMap1);
4036                         }
4037                 }
4038         }
4039         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
4040                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
4041                         np->msi_flags |= NV_MSI_ENABLED;
4042                         dev->irq = np->pci_dev->irq;
4043                         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
4044                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
4045                                 pci_disable_msi(np->pci_dev);
4046                                 np->msi_flags &= ~NV_MSI_ENABLED;
4047                                 dev->irq = np->pci_dev->irq;
4048                                 goto out_err;
4049                         }
4050
4051                         /* map interrupts to vector 0 */
4052                         writel(0, base + NvRegMSIMap0);
4053                         writel(0, base + NvRegMSIMap1);
4054                         /* enable msi vector 0 */
4055                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
4056                 }
4057         }
4058         if (ret != 0) {
4059                 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
4060                         goto out_err;
4061
4062         }
4063
4064         return 0;
4065 out_free_tx:
4066         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
4067 out_free_rx:
4068         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
4069 out_err:
4070         return 1;
4071 }
4072
4073 static void nv_free_irq(struct net_device *dev)
4074 {
4075         struct fe_priv *np = get_nvpriv(dev);
4076         int i;
4077
4078         if (np->msi_flags & NV_MSI_X_ENABLED) {
4079                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
4080                         free_irq(np->msi_x_entry[i].vector, dev);
4081                 }
4082                 pci_disable_msix(np->pci_dev);
4083                 np->msi_flags &= ~NV_MSI_X_ENABLED;
4084         } else {
4085                 free_irq(np->pci_dev->irq, dev);
4086                 if (np->msi_flags & NV_MSI_ENABLED) {
4087                         pci_disable_msi(np->pci_dev);
4088                         np->msi_flags &= ~NV_MSI_ENABLED;
4089                 }
4090         }
4091 }
4092
4093 static void nv_do_nic_poll(unsigned long data)
4094 {
4095         struct net_device *dev = (struct net_device *) data;
4096         struct fe_priv *np = netdev_priv(dev);
4097         u8 __iomem *base = get_hwbase(dev);
4098         u32 mask = 0;
4099
4100         /*
4101          * First disable irq(s) and then
4102          * reenable interrupts on the nic, we have to do this before calling
4103          * nv_nic_irq because that may decide to do otherwise
4104          */
4105
4106         if (!using_multi_irqs(dev)) {
4107                 if (np->msi_flags & NV_MSI_X_ENABLED)
4108                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4109                 else
4110                         disable_irq_lockdep(np->pci_dev->irq);
4111                 mask = np->irqmask;
4112         } else {
4113                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4114                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4115                         mask |= NVREG_IRQ_RX_ALL;
4116                 }
4117                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4118                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4119                         mask |= NVREG_IRQ_TX_ALL;
4120                 }
4121                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4122                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4123                         mask |= NVREG_IRQ_OTHER;
4124                 }
4125         }
4126         /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
4127
4128         if (np->recover_error) {
4129                 np->recover_error = 0;
4130                 printk(KERN_INFO "%s: MAC in recoverable error state\n", dev->name);
4131                 if (netif_running(dev)) {
4132                         netif_tx_lock_bh(dev);
4133                         netif_addr_lock(dev);
4134                         spin_lock(&np->lock);
4135                         /* stop engines */
4136                         nv_stop_rxtx(dev);
4137                         if (np->driver_data & DEV_HAS_POWER_CNTRL)
4138                                 nv_mac_reset(dev);
4139                         nv_txrx_reset(dev);
4140                         /* drain rx queue */
4141                         nv_drain_rxtx(dev);
4142                         /* reinit driver view of the rx queue */
4143                         set_bufsize(dev);
4144                         if (nv_init_ring(dev)) {
4145                                 if (!np->in_shutdown)
4146                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4147                         }
4148                         /* reinit nic view of the rx queue */
4149                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4150                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4151                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4152                                 base + NvRegRingSizes);
4153                         pci_push(base);
4154                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4155                         pci_push(base);
4156                         /* clear interrupts */
4157                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4158                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4159                         else
4160                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4161
4162                         /* restart rx engine */
4163                         nv_start_rxtx(dev);
4164                         spin_unlock(&np->lock);
4165                         netif_addr_unlock(dev);
4166                         netif_tx_unlock_bh(dev);
4167                 }
4168         }
4169
4170         writel(mask, base + NvRegIrqMask);
4171         pci_push(base);
4172
4173         if (!using_multi_irqs(dev)) {
4174                 np->nic_poll_irq = 0;
4175                 if (nv_optimized(np))
4176                         nv_nic_irq_optimized(0, dev);
4177                 else
4178                         nv_nic_irq(0, dev);
4179                 if (np->msi_flags & NV_MSI_X_ENABLED)
4180                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4181                 else
4182                         enable_irq_lockdep(np->pci_dev->irq);
4183         } else {
4184                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4185                         np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
4186                         nv_nic_irq_rx(0, dev);
4187                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4188                 }
4189                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4190                         np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
4191                         nv_nic_irq_tx(0, dev);
4192                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4193                 }
4194                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4195                         np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
4196                         nv_nic_irq_other(0, dev);
4197                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4198                 }
4199         }
4200
4201 }
4202
4203 #ifdef CONFIG_NET_POLL_CONTROLLER
4204 static void nv_poll_controller(struct net_device *dev)
4205 {
4206         nv_do_nic_poll((unsigned long) dev);
4207 }
4208 #endif
4209
4210 static void nv_do_stats_poll(unsigned long data)
4211 {
4212         struct net_device *dev = (struct net_device *) data;
4213         struct fe_priv *np = netdev_priv(dev);
4214
4215         nv_get_hw_stats(dev);
4216
4217         if (!np->in_shutdown)
4218                 mod_timer(&np->stats_poll,
4219                         round_jiffies(jiffies + STATS_INTERVAL));
4220 }
4221
4222 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4223 {
4224         struct fe_priv *np = netdev_priv(dev);
4225         strcpy(info->driver, DRV_NAME);
4226         strcpy(info->version, FORCEDETH_VERSION);
4227         strcpy(info->bus_info, pci_name(np->pci_dev));
4228 }
4229
4230 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4231 {
4232         struct fe_priv *np = netdev_priv(dev);
4233         wolinfo->supported = WAKE_MAGIC;
4234
4235         spin_lock_irq(&np->lock);
4236         if (np->wolenabled)
4237                 wolinfo->wolopts = WAKE_MAGIC;
4238         spin_unlock_irq(&np->lock);
4239 }
4240
4241 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4242 {
4243         struct fe_priv *np = netdev_priv(dev);
4244         u8 __iomem *base = get_hwbase(dev);
4245         u32 flags = 0;
4246
4247         if (wolinfo->wolopts == 0) {
4248                 np->wolenabled = 0;
4249         } else if (wolinfo->wolopts & WAKE_MAGIC) {
4250                 np->wolenabled = 1;
4251                 flags = NVREG_WAKEUPFLAGS_ENABLE;
4252         }
4253         if (netif_running(dev)) {
4254                 spin_lock_irq(&np->lock);
4255                 writel(flags, base + NvRegWakeUpFlags);
4256                 spin_unlock_irq(&np->lock);
4257         }
4258         return 0;
4259 }
4260
4261 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4262 {
4263         struct fe_priv *np = netdev_priv(dev);
4264         int adv;
4265
4266         spin_lock_irq(&np->lock);
4267         ecmd->port = PORT_MII;
4268         if (!netif_running(dev)) {
4269                 /* We do not track link speed / duplex setting if the
4270                  * interface is disabled. Force a link check */
4271                 if (nv_update_linkspeed(dev)) {
4272                         if (!netif_carrier_ok(dev))
4273                                 netif_carrier_on(dev);
4274                 } else {
4275                         if (netif_carrier_ok(dev))
4276                                 netif_carrier_off(dev);
4277                 }
4278         }
4279
4280         if (netif_carrier_ok(dev)) {
4281                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4282                 case NVREG_LINKSPEED_10:
4283                         ecmd->speed = SPEED_10;
4284                         break;
4285                 case NVREG_LINKSPEED_100:
4286                         ecmd->speed = SPEED_100;
4287                         break;
4288                 case NVREG_LINKSPEED_1000:
4289                         ecmd->speed = SPEED_1000;
4290                         break;
4291                 }
4292                 ecmd->duplex = DUPLEX_HALF;
4293                 if (np->duplex)
4294                         ecmd->duplex = DUPLEX_FULL;
4295         } else {
4296                 ecmd->speed = -1;
4297                 ecmd->duplex = -1;
4298         }
4299
4300         ecmd->autoneg = np->autoneg;
4301
4302         ecmd->advertising = ADVERTISED_MII;
4303         if (np->autoneg) {
4304                 ecmd->advertising |= ADVERTISED_Autoneg;
4305                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4306                 if (adv & ADVERTISE_10HALF)
4307                         ecmd->advertising |= ADVERTISED_10baseT_Half;
4308                 if (adv & ADVERTISE_10FULL)
4309                         ecmd->advertising |= ADVERTISED_10baseT_Full;
4310                 if (adv & ADVERTISE_100HALF)
4311                         ecmd->advertising |= ADVERTISED_100baseT_Half;
4312                 if (adv & ADVERTISE_100FULL)
4313                         ecmd->advertising |= ADVERTISED_100baseT_Full;
4314                 if (np->gigabit == PHY_GIGABIT) {
4315                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4316                         if (adv & ADVERTISE_1000FULL)
4317                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4318                 }
4319         }
4320         ecmd->supported = (SUPPORTED_Autoneg |
4321                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4322                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4323                 SUPPORTED_MII);
4324         if (np->gigabit == PHY_GIGABIT)
4325                 ecmd->supported |= SUPPORTED_1000baseT_Full;
4326
4327         ecmd->phy_address = np->phyaddr;
4328         ecmd->transceiver = XCVR_EXTERNAL;
4329
4330         /* ignore maxtxpkt, maxrxpkt for now */
4331         spin_unlock_irq(&np->lock);
4332         return 0;
4333 }
4334
4335 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4336 {
4337         struct fe_priv *np = netdev_priv(dev);
4338
4339         if (ecmd->port != PORT_MII)
4340                 return -EINVAL;
4341         if (ecmd->transceiver != XCVR_EXTERNAL)
4342                 return -EINVAL;
4343         if (ecmd->phy_address != np->phyaddr) {
4344                 /* TODO: support switching between multiple phys. Should be
4345                  * trivial, but not enabled due to lack of test hardware. */
4346                 return -EINVAL;
4347         }
4348         if (ecmd->autoneg == AUTONEG_ENABLE) {
4349                 u32 mask;
4350
4351                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4352                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4353                 if (np->gigabit == PHY_GIGABIT)
4354                         mask |= ADVERTISED_1000baseT_Full;
4355
4356                 if ((ecmd->advertising & mask) == 0)
4357                         return -EINVAL;
4358
4359         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4360                 /* Note: autonegotiation disable, speed 1000 intentionally
4361                  * forbidden - noone should need that. */
4362
4363                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4364                         return -EINVAL;
4365                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4366                         return -EINVAL;
4367         } else {
4368                 return -EINVAL;
4369         }
4370
4371         netif_carrier_off(dev);
4372         if (netif_running(dev)) {
4373                 unsigned long flags;
4374
4375                 nv_disable_irq(dev);
4376                 netif_tx_lock_bh(dev);
4377                 netif_addr_lock(dev);
4378                 /* with plain spinlock lockdep complains */
4379                 spin_lock_irqsave(&np->lock, flags);
4380                 /* stop engines */
4381                 /* FIXME:
4382                  * this can take some time, and interrupts are disabled
4383                  * due to spin_lock_irqsave, but let's hope no daemon
4384                  * is going to change the settings very often...
4385                  * Worst case:
4386                  * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4387                  * + some minor delays, which is up to a second approximately
4388                  */
4389                 nv_stop_rxtx(dev);
4390                 spin_unlock_irqrestore(&np->lock, flags);
4391                 netif_addr_unlock(dev);
4392                 netif_tx_unlock_bh(dev);
4393         }
4394
4395         if (ecmd->autoneg == AUTONEG_ENABLE) {
4396                 int adv, bmcr;
4397
4398                 np->autoneg = 1;
4399
4400                 /* advertise only what has been requested */
4401                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4402                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4403                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4404                         adv |= ADVERTISE_10HALF;
4405                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4406                         adv |= ADVERTISE_10FULL;
4407                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4408                         adv |= ADVERTISE_100HALF;
4409                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4410                         adv |= ADVERTISE_100FULL;
4411                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
4412                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4413                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4414                         adv |=  ADVERTISE_PAUSE_ASYM;
4415                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4416
4417                 if (np->gigabit == PHY_GIGABIT) {
4418                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4419                         adv &= ~ADVERTISE_1000FULL;
4420                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4421                                 adv |= ADVERTISE_1000FULL;
4422                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4423                 }
4424
4425                 if (netif_running(dev))
4426                         printk(KERN_INFO "%s: link down.\n", dev->name);
4427                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4428                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4429                         bmcr |= BMCR_ANENABLE;
4430                         /* reset the phy in order for settings to stick,
4431                          * and cause autoneg to start */
4432                         if (phy_reset(dev, bmcr)) {
4433                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4434                                 return -EINVAL;
4435                         }
4436                 } else {
4437                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4438                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4439                 }
4440         } else {
4441                 int adv, bmcr;
4442
4443                 np->autoneg = 0;
4444
4445                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4446                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4447                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4448                         adv |= ADVERTISE_10HALF;
4449                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4450                         adv |= ADVERTISE_10FULL;
4451                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4452                         adv |= ADVERTISE_100HALF;
4453                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4454                         adv |= ADVERTISE_100FULL;
4455                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4456                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4457                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4458                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4459                 }
4460                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4461                         adv |=  ADVERTISE_PAUSE_ASYM;
4462                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4463                 }
4464                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4465                 np->fixed_mode = adv;
4466
4467                 if (np->gigabit == PHY_GIGABIT) {
4468                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4469                         adv &= ~ADVERTISE_1000FULL;
4470                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4471                 }
4472
4473                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4474                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4475                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4476                         bmcr |= BMCR_FULLDPLX;
4477                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4478                         bmcr |= BMCR_SPEED100;
4479                 if (np->phy_oui == PHY_OUI_MARVELL) {
4480                         /* reset the phy in order for forced mode settings to stick */
4481                         if (phy_reset(dev, bmcr)) {
4482                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4483                                 return -EINVAL;
4484                         }
4485                 } else {
4486                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4487                         if (netif_running(dev)) {
4488                                 /* Wait a bit and then reconfigure the nic. */
4489                                 udelay(10);
4490                                 nv_linkchange(dev);
4491                         }
4492                 }
4493         }
4494
4495         if (netif_running(dev)) {
4496                 nv_start_rxtx(dev);
4497                 nv_enable_irq(dev);
4498         }
4499
4500         return 0;
4501 }
4502
4503 #define FORCEDETH_REGS_VER      1
4504
4505 static int nv_get_regs_len(struct net_device *dev)
4506 {
4507         struct fe_priv *np = netdev_priv(dev);
4508         return np->register_size;
4509 }
4510
4511 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4512 {
4513         struct fe_priv *np = netdev_priv(dev);
4514         u8 __iomem *base = get_hwbase(dev);
4515         u32 *rbuf = buf;
4516         int i;
4517
4518         regs->version = FORCEDETH_REGS_VER;
4519         spin_lock_irq(&np->lock);
4520         for (i = 0;i <= np->register_size/sizeof(u32); i++)
4521                 rbuf[i] = readl(base + i*sizeof(u32));
4522         spin_unlock_irq(&np->lock);
4523 }
4524
4525 static int nv_nway_reset(struct net_device *dev)
4526 {
4527         struct fe_priv *np = netdev_priv(dev);
4528         int ret;
4529
4530         if (np->autoneg) {
4531                 int bmcr;
4532
4533                 netif_carrier_off(dev);
4534                 if (netif_running(dev)) {
4535                         nv_disable_irq(dev);
4536                         netif_tx_lock_bh(dev);
4537                         netif_addr_lock(dev);
4538                         spin_lock(&np->lock);
4539                         /* stop engines */
4540                         nv_stop_rxtx(dev);
4541                         spin_unlock(&np->lock);
4542                         netif_addr_unlock(dev);
4543                         netif_tx_unlock_bh(dev);
4544                         printk(KERN_INFO "%s: link down.\n", dev->name);
4545                 }
4546
4547                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4548                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4549                         bmcr |= BMCR_ANENABLE;
4550                         /* reset the phy in order for settings to stick*/
4551                         if (phy_reset(dev, bmcr)) {
4552                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4553                                 return -EINVAL;
4554                         }
4555                 } else {
4556                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4557                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4558                 }
4559
4560                 if (netif_running(dev)) {
4561                         nv_start_rxtx(dev);
4562                         nv_enable_irq(dev);
4563                 }
4564                 ret = 0;
4565         } else {
4566                 ret = -EINVAL;
4567         }
4568
4569         return ret;
4570 }
4571
4572 static int nv_set_tso(struct net_device *dev, u32 value)
4573 {
4574         struct fe_priv *np = netdev_priv(dev);
4575
4576         if ((np->driver_data & DEV_HAS_CHECKSUM))
4577                 return ethtool_op_set_tso(dev, value);
4578         else
4579                 return -EOPNOTSUPP;
4580 }
4581
4582 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4583 {
4584         struct fe_priv *np = netdev_priv(dev);
4585
4586         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4587         ring->rx_mini_max_pending = 0;
4588         ring->rx_jumbo_max_pending = 0;
4589         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4590
4591         ring->rx_pending = np->rx_ring_size;
4592         ring->rx_mini_pending = 0;
4593         ring->rx_jumbo_pending = 0;
4594         ring->tx_pending = np->tx_ring_size;
4595 }
4596
4597 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4598 {
4599         struct fe_priv *np = netdev_priv(dev);
4600         u8 __iomem *base = get_hwbase(dev);
4601         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4602         dma_addr_t ring_addr;
4603
4604         if (ring->rx_pending < RX_RING_MIN ||
4605             ring->tx_pending < TX_RING_MIN ||
4606             ring->rx_mini_pending != 0 ||
4607             ring->rx_jumbo_pending != 0 ||
4608             (np->desc_ver == DESC_VER_1 &&
4609              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4610               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4611             (np->desc_ver != DESC_VER_1 &&
4612              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4613               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4614                 return -EINVAL;
4615         }
4616
4617         /* allocate new rings */
4618         if (!nv_optimized(np)) {
4619                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4620                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4621                                             &ring_addr);
4622         } else {
4623                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4624                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4625                                             &ring_addr);
4626         }
4627         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4628         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4629         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4630                 /* fall back to old rings */
4631                 if (!nv_optimized(np)) {
4632                         if (rxtx_ring)
4633                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4634                                                     rxtx_ring, ring_addr);
4635                 } else {
4636                         if (rxtx_ring)
4637                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4638                                                     rxtx_ring, ring_addr);
4639                 }
4640                 if (rx_skbuff)
4641                         kfree(rx_skbuff);
4642                 if (tx_skbuff)
4643                         kfree(tx_skbuff);
4644                 goto exit;
4645         }
4646
4647         if (netif_running(dev)) {
4648                 nv_disable_irq(dev);
4649                 nv_napi_disable(dev);
4650                 netif_tx_lock_bh(dev);
4651                 netif_addr_lock(dev);
4652                 spin_lock(&np->lock);
4653                 /* stop engines */
4654                 nv_stop_rxtx(dev);
4655                 nv_txrx_reset(dev);
4656                 /* drain queues */
4657                 nv_drain_rxtx(dev);
4658                 /* delete queues */
4659                 free_rings(dev);
4660         }
4661
4662         /* set new values */
4663         np->rx_ring_size = ring->rx_pending;
4664         np->tx_ring_size = ring->tx_pending;
4665
4666         if (!nv_optimized(np)) {
4667                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4668                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4669         } else {
4670                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4671                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4672         }
4673         np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4674         np->tx_skb = (struct nv_skb_map*)tx_skbuff;
4675         np->ring_addr = ring_addr;
4676
4677         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4678         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4679
4680         if (netif_running(dev)) {
4681                 /* reinit driver view of the queues */
4682                 set_bufsize(dev);
4683                 if (nv_init_ring(dev)) {
4684                         if (!np->in_shutdown)
4685                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4686                 }
4687
4688                 /* reinit nic view of the queues */
4689                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4690                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4691                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4692                         base + NvRegRingSizes);
4693                 pci_push(base);
4694                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4695                 pci_push(base);
4696
4697                 /* restart engines */
4698                 nv_start_rxtx(dev);
4699                 spin_unlock(&np->lock);
4700                 netif_addr_unlock(dev);
4701                 netif_tx_unlock_bh(dev);
4702                 nv_napi_enable(dev);
4703                 nv_enable_irq(dev);
4704         }
4705         return 0;
4706 exit:
4707         return -ENOMEM;
4708 }
4709
4710 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4711 {
4712         struct fe_priv *np = netdev_priv(dev);
4713
4714         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4715         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4716         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4717 }
4718
4719 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4720 {
4721         struct fe_priv *np = netdev_priv(dev);
4722         int adv, bmcr;
4723
4724         if ((!np->autoneg && np->duplex == 0) ||
4725             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4726                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4727                        dev->name);
4728                 return -EINVAL;
4729         }
4730         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4731                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4732                 return -EINVAL;
4733         }
4734
4735         netif_carrier_off(dev);
4736         if (netif_running(dev)) {
4737                 nv_disable_irq(dev);
4738                 netif_tx_lock_bh(dev);
4739                 netif_addr_lock(dev);
4740                 spin_lock(&np->lock);
4741                 /* stop engines */
4742                 nv_stop_rxtx(dev);
4743                 spin_unlock(&np->lock);
4744                 netif_addr_unlock(dev);
4745                 netif_tx_unlock_bh(dev);
4746         }
4747
4748         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4749         if (pause->rx_pause)
4750                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4751         if (pause->tx_pause)
4752                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4753
4754         if (np->autoneg && pause->autoneg) {
4755                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4756
4757                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4758                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4759                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4760                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4761                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4762                         adv |=  ADVERTISE_PAUSE_ASYM;
4763                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4764
4765                 if (netif_running(dev))
4766                         printk(KERN_INFO "%s: link down.\n", dev->name);
4767                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4768                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4769                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4770         } else {
4771                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4772                 if (pause->rx_pause)
4773                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4774                 if (pause->tx_pause)
4775                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4776
4777                 if (!netif_running(dev))
4778                         nv_update_linkspeed(dev);
4779                 else
4780                         nv_update_pause(dev, np->pause_flags);
4781         }
4782
4783         if (netif_running(dev)) {
4784                 nv_start_rxtx(dev);
4785                 nv_enable_irq(dev);
4786         }
4787         return 0;
4788 }
4789
4790 static u32 nv_get_rx_csum(struct net_device *dev)
4791 {
4792         struct fe_priv *np = netdev_priv(dev);
4793         return (np->rx_csum) != 0;
4794 }
4795
4796 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4797 {
4798         struct fe_priv *np = netdev_priv(dev);
4799         u8 __iomem *base = get_hwbase(dev);
4800         int retcode = 0;
4801
4802         if (np->driver_data & DEV_HAS_CHECKSUM) {
4803                 if (data) {
4804                         np->rx_csum = 1;
4805                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4806                 } else {
4807                         np->rx_csum = 0;
4808                         /* vlan is dependent on rx checksum offload */
4809                         if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4810                                 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4811                 }
4812                 if (netif_running(dev)) {
4813                         spin_lock_irq(&np->lock);
4814                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4815                         spin_unlock_irq(&np->lock);
4816                 }
4817         } else {
4818                 return -EINVAL;
4819         }
4820
4821         return retcode;
4822 }
4823
4824 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4825 {
4826         struct fe_priv *np = netdev_priv(dev);
4827
4828         if (np->driver_data & DEV_HAS_CHECKSUM)
4829                 return ethtool_op_set_tx_csum(dev, data);
4830         else
4831                 return -EOPNOTSUPP;
4832 }
4833
4834 static int nv_set_sg(struct net_device *dev, u32 data)
4835 {
4836         struct fe_priv *np = netdev_priv(dev);
4837
4838         if (np->driver_data & DEV_HAS_CHECKSUM)
4839                 return ethtool_op_set_sg(dev, data);
4840         else
4841                 return -EOPNOTSUPP;
4842 }
4843
4844 static int nv_get_sset_count(struct net_device *dev, int sset)
4845 {
4846         struct fe_priv *np = netdev_priv(dev);
4847
4848         switch (sset) {
4849         case ETH_SS_TEST:
4850                 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4851                         return NV_TEST_COUNT_EXTENDED;
4852                 else
4853                         return NV_TEST_COUNT_BASE;
4854         case ETH_SS_STATS:
4855                 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4856                         return NV_DEV_STATISTICS_V3_COUNT;
4857                 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4858                         return NV_DEV_STATISTICS_V2_COUNT;
4859                 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4860                         return NV_DEV_STATISTICS_V1_COUNT;
4861                 else
4862                         return 0;
4863         default:
4864                 return -EOPNOTSUPP;
4865         }
4866 }
4867
4868 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4869 {
4870         struct fe_priv *np = netdev_priv(dev);
4871
4872         /* update stats */
4873         nv_do_stats_poll((unsigned long)dev);
4874
4875         memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4876 }
4877
4878 static int nv_link_test(struct net_device *dev)
4879 {
4880         struct fe_priv *np = netdev_priv(dev);
4881         int mii_status;
4882
4883         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4884         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4885
4886         /* check phy link status */
4887         if (!(mii_status & BMSR_LSTATUS))
4888                 return 0;
4889         else
4890                 return 1;
4891 }
4892
4893 static int nv_register_test(struct net_device *dev)
4894 {
4895         u8 __iomem *base = get_hwbase(dev);
4896         int i = 0;
4897         u32 orig_read, new_read;
4898
4899         do {
4900                 orig_read = readl(base + nv_registers_test[i].reg);
4901
4902                 /* xor with mask to toggle bits */
4903                 orig_read ^= nv_registers_test[i].mask;
4904
4905                 writel(orig_read, base + nv_registers_test[i].reg);
4906
4907                 new_read = readl(base + nv_registers_test[i].reg);
4908
4909                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4910                         return 0;
4911
4912                 /* restore original value */
4913                 orig_read ^= nv_registers_test[i].mask;
4914                 writel(orig_read, base + nv_registers_test[i].reg);
4915
4916         } while (nv_registers_test[++i].reg != 0);
4917
4918         return 1;
4919 }
4920
4921 static int nv_interrupt_test(struct net_device *dev)
4922 {
4923         struct fe_priv *np = netdev_priv(dev);
4924         u8 __iomem *base = get_hwbase(dev);
4925         int ret = 1;
4926         int testcnt;
4927         u32 save_msi_flags, save_poll_interval = 0;
4928
4929         if (netif_running(dev)) {
4930                 /* free current irq */
4931                 nv_free_irq(dev);
4932                 save_poll_interval = readl(base+NvRegPollingInterval);
4933         }
4934
4935         /* flag to test interrupt handler */
4936         np->intr_test = 0;
4937
4938         /* setup test irq */
4939         save_msi_flags = np->msi_flags;
4940         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4941         np->msi_flags |= 0x001; /* setup 1 vector */
4942         if (nv_request_irq(dev, 1))
4943                 return 0;
4944
4945         /* setup timer interrupt */
4946         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4947         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4948
4949         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4950
4951         /* wait for at least one interrupt */
4952         msleep(100);
4953
4954         spin_lock_irq(&np->lock);
4955
4956         /* flag should be set within ISR */
4957         testcnt = np->intr_test;
4958         if (!testcnt)
4959                 ret = 2;
4960
4961         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4962         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4963                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4964         else
4965                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4966
4967         spin_unlock_irq(&np->lock);
4968
4969         nv_free_irq(dev);
4970
4971         np->msi_flags = save_msi_flags;
4972
4973         if (netif_running(dev)) {
4974                 writel(save_poll_interval, base + NvRegPollingInterval);
4975                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4976                 /* restore original irq */
4977                 if (nv_request_irq(dev, 0))
4978                         return 0;
4979         }
4980
4981         return ret;
4982 }
4983
4984 static int nv_loopback_test(struct net_device *dev)
4985 {
4986         struct fe_priv *np = netdev_priv(dev);
4987         u8 __iomem *base = get_hwbase(dev);
4988         struct sk_buff *tx_skb, *rx_skb;
4989         dma_addr_t test_dma_addr;
4990         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4991         u32 flags;
4992         int len, i, pkt_len;
4993         u8 *pkt_data;
4994         u32 filter_flags = 0;
4995         u32 misc1_flags = 0;
4996         int ret = 1;
4997
4998         if (netif_running(dev)) {
4999                 nv_disable_irq(dev);
5000                 filter_flags = readl(base + NvRegPacketFilterFlags);
5001                 misc1_flags = readl(base + NvRegMisc1);
5002         } else {
5003                 nv_txrx_reset(dev);
5004         }
5005
5006         /* reinit driver view of the rx queue */
5007         set_bufsize(dev);
5008         nv_init_ring(dev);
5009
5010         /* setup hardware for loopback */
5011         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
5012         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
5013
5014         /* reinit nic view of the rx queue */
5015         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5016         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5017         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5018                 base + NvRegRingSizes);
5019         pci_push(base);
5020
5021         /* restart rx engine */
5022         nv_start_rxtx(dev);
5023
5024         /* setup packet for tx */
5025         pkt_len = ETH_DATA_LEN;
5026         tx_skb = dev_alloc_skb(pkt_len);
5027         if (!tx_skb) {
5028                 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
5029                          " of %s\n", dev->name);
5030                 ret = 0;
5031                 goto out;
5032         }
5033         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
5034                                        skb_tailroom(tx_skb),
5035                                        PCI_DMA_FROMDEVICE);
5036         pkt_data = skb_put(tx_skb, pkt_len);
5037         for (i = 0; i < pkt_len; i++)
5038                 pkt_data[i] = (u8)(i & 0xff);
5039
5040         if (!nv_optimized(np)) {
5041                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
5042                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5043         } else {
5044                 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
5045                 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
5046                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5047         }
5048         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5049         pci_push(get_hwbase(dev));
5050
5051         msleep(500);
5052
5053         /* check for rx of the packet */
5054         if (!nv_optimized(np)) {
5055                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
5056                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
5057
5058         } else {
5059                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
5060                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
5061         }
5062
5063         if (flags & NV_RX_AVAIL) {
5064                 ret = 0;
5065         } else if (np->desc_ver == DESC_VER_1) {
5066                 if (flags & NV_RX_ERROR)
5067                         ret = 0;
5068         } else {
5069                 if (flags & NV_RX2_ERROR) {
5070                         ret = 0;
5071                 }
5072         }
5073
5074         if (ret) {
5075                 if (len != pkt_len) {
5076                         ret = 0;
5077                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
5078                                 dev->name, len, pkt_len);
5079                 } else {
5080                         rx_skb = np->rx_skb[0].skb;
5081                         for (i = 0; i < pkt_len; i++) {
5082                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
5083                                         ret = 0;
5084                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
5085                                                 dev->name, i);
5086                                         break;
5087                                 }
5088                         }
5089                 }
5090         } else {
5091                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
5092         }
5093
5094         pci_unmap_page(np->pci_dev, test_dma_addr,
5095                        (skb_end_pointer(tx_skb) - tx_skb->data),
5096                        PCI_DMA_TODEVICE);
5097         dev_kfree_skb_any(tx_skb);
5098  out:
5099         /* stop engines */
5100         nv_stop_rxtx(dev);
5101         nv_txrx_reset(dev);
5102         /* drain rx queue */
5103         nv_drain_rxtx(dev);
5104
5105         if (netif_running(dev)) {
5106                 writel(misc1_flags, base + NvRegMisc1);
5107                 writel(filter_flags, base + NvRegPacketFilterFlags);
5108                 nv_enable_irq(dev);
5109         }
5110
5111         return ret;
5112 }
5113
5114 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
5115 {
5116         struct fe_priv *np = netdev_priv(dev);
5117         u8 __iomem *base = get_hwbase(dev);
5118         int result;
5119         memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
5120
5121         if (!nv_link_test(dev)) {
5122                 test->flags |= ETH_TEST_FL_FAILED;
5123                 buffer[0] = 1;
5124         }
5125
5126         if (test->flags & ETH_TEST_FL_OFFLINE) {
5127                 if (netif_running(dev)) {
5128                         netif_stop_queue(dev);
5129                         nv_napi_disable(dev);
5130                         netif_tx_lock_bh(dev);
5131                         netif_addr_lock(dev);
5132                         spin_lock_irq(&np->lock);
5133                         nv_disable_hw_interrupts(dev, np->irqmask);
5134                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
5135                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5136                         } else {
5137                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5138                         }
5139                         /* stop engines */
5140                         nv_stop_rxtx(dev);
5141                         nv_txrx_reset(dev);
5142                         /* drain rx queue */
5143                         nv_drain_rxtx(dev);
5144                         spin_unlock_irq(&np->lock);
5145                         netif_addr_unlock(dev);
5146                         netif_tx_unlock_bh(dev);
5147                 }
5148
5149                 if (!nv_register_test(dev)) {
5150                         test->flags |= ETH_TEST_FL_FAILED;
5151                         buffer[1] = 1;
5152                 }
5153
5154                 result = nv_interrupt_test(dev);
5155                 if (result != 1) {
5156                         test->flags |= ETH_TEST_FL_FAILED;
5157                         buffer[2] = 1;
5158                 }
5159                 if (result == 0) {
5160                         /* bail out */
5161                         return;
5162                 }
5163
5164                 if (!nv_loopback_test(dev)) {
5165                         test->flags |= ETH_TEST_FL_FAILED;
5166                         buffer[3] = 1;
5167                 }
5168
5169                 if (netif_running(dev)) {
5170                         /* reinit driver view of the rx queue */
5171                         set_bufsize(dev);
5172                         if (nv_init_ring(dev)) {
5173                                 if (!np->in_shutdown)
5174                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5175                         }
5176                         /* reinit nic view of the rx queue */
5177                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5178                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5179                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5180                                 base + NvRegRingSizes);
5181                         pci_push(base);
5182                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5183                         pci_push(base);
5184                         /* restart rx engine */
5185                         nv_start_rxtx(dev);
5186                         netif_start_queue(dev);
5187                         nv_napi_enable(dev);
5188                         nv_enable_hw_interrupts(dev, np->irqmask);
5189                 }
5190         }
5191 }
5192
5193 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5194 {
5195         switch (stringset) {
5196         case ETH_SS_STATS:
5197                 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
5198                 break;
5199         case ETH_SS_TEST:
5200                 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
5201                 break;
5202         }
5203 }
5204
5205 static const struct ethtool_ops ops = {
5206         .get_drvinfo = nv_get_drvinfo,
5207         .get_link = ethtool_op_get_link,
5208         .get_wol = nv_get_wol,
5209         .set_wol = nv_set_wol,
5210         .get_settings = nv_get_settings,
5211         .set_settings = nv_set_settings,
5212         .get_regs_len = nv_get_regs_len,
5213         .get_regs = nv_get_regs,
5214         .nway_reset = nv_nway_reset,
5215         .set_tso = nv_set_tso,
5216         .get_ringparam = nv_get_ringparam,
5217         .set_ringparam = nv_set_ringparam,
5218         .get_pauseparam = nv_get_pauseparam,
5219         .set_pauseparam = nv_set_pauseparam,
5220         .get_rx_csum = nv_get_rx_csum,
5221         .set_rx_csum = nv_set_rx_csum,
5222         .set_tx_csum = nv_set_tx_csum,
5223         .set_sg = nv_set_sg,
5224         .get_strings = nv_get_strings,
5225         .get_ethtool_stats = nv_get_ethtool_stats,
5226         .get_sset_count = nv_get_sset_count,
5227         .self_test = nv_self_test,
5228 };
5229
5230 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
5231 {
5232         struct fe_priv *np = get_nvpriv(dev);
5233
5234         spin_lock_irq(&np->lock);
5235
5236         /* save vlan group */
5237         np->vlangrp = grp;
5238
5239         if (grp) {
5240                 /* enable vlan on MAC */
5241                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
5242         } else {
5243                 /* disable vlan on MAC */
5244                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
5245                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
5246         }
5247
5248         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5249
5250         spin_unlock_irq(&np->lock);
5251 }
5252
5253 /* The mgmt unit and driver use a semaphore to access the phy during init */
5254 static int nv_mgmt_acquire_sema(struct net_device *dev)
5255 {
5256         struct fe_priv *np = netdev_priv(dev);
5257         u8 __iomem *base = get_hwbase(dev);
5258         int i;
5259         u32 tx_ctrl, mgmt_sema;
5260
5261         for (i = 0; i < 10; i++) {
5262                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5263                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5264                         break;
5265                 msleep(500);
5266         }
5267
5268         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5269                 return 0;
5270
5271         for (i = 0; i < 2; i++) {
5272                 tx_ctrl = readl(base + NvRegTransmitterControl);
5273                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5274                 writel(tx_ctrl, base + NvRegTransmitterControl);
5275
5276                 /* verify that semaphore was acquired */
5277                 tx_ctrl = readl(base + NvRegTransmitterControl);
5278                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5279                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5280                         np->mgmt_sema = 1;
5281                         return 1;
5282                 }
5283                 else
5284                         udelay(50);
5285         }
5286
5287         return 0;
5288 }
5289
5290 static void nv_mgmt_release_sema(struct net_device *dev)
5291 {
5292         struct fe_priv *np = netdev_priv(dev);
5293         u8 __iomem *base = get_hwbase(dev);
5294         u32 tx_ctrl;
5295
5296         if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5297                 if (np->mgmt_sema) {
5298                         tx_ctrl = readl(base + NvRegTransmitterControl);
5299                         tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5300                         writel(tx_ctrl, base + NvRegTransmitterControl);
5301                 }
5302         }
5303 }
5304
5305
5306 static int nv_mgmt_get_version(struct net_device *dev)
5307 {
5308         struct fe_priv *np = netdev_priv(dev);
5309         u8 __iomem *base = get_hwbase(dev);
5310         u32 data_ready = readl(base + NvRegTransmitterControl);
5311         u32 data_ready2 = 0;
5312         unsigned long start;
5313         int ready = 0;
5314
5315         writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5316         writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5317         start = jiffies;
5318         while (time_before(jiffies, start + 5*HZ)) {
5319                 data_ready2 = readl(base + NvRegTransmitterControl);
5320                 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5321                         ready = 1;
5322                         break;
5323                 }
5324                 schedule_timeout_uninterruptible(1);
5325         }
5326
5327         if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5328                 return 0;
5329
5330         np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5331
5332         return 1;
5333 }
5334
5335 static int nv_open(struct net_device *dev)
5336 {
5337         struct fe_priv *np = netdev_priv(dev);
5338         u8 __iomem *base = get_hwbase(dev);
5339         int ret = 1;
5340         int oom, i;
5341         u32 low;
5342
5343         dprintk(KERN_DEBUG "nv_open: begin\n");
5344
5345         /* power up phy */
5346         mii_rw(dev, np->phyaddr, MII_BMCR,
5347                mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5348
5349         nv_txrx_gate(dev, false);
5350         /* erase previous misconfiguration */
5351         if (np->driver_data & DEV_HAS_POWER_CNTRL)
5352                 nv_mac_reset(dev);
5353         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5354         writel(0, base + NvRegMulticastAddrB);
5355         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5356         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5357         writel(0, base + NvRegPacketFilterFlags);
5358
5359         writel(0, base + NvRegTransmitterControl);
5360         writel(0, base + NvRegReceiverControl);
5361
5362         writel(0, base + NvRegAdapterControl);
5363
5364         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5365                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
5366
5367         /* initialize descriptor rings */
5368         set_bufsize(dev);
5369         oom = nv_init_ring(dev);
5370
5371         writel(0, base + NvRegLinkSpeed);
5372         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5373         nv_txrx_reset(dev);
5374         writel(0, base + NvRegUnknownSetupReg6);
5375
5376         np->in_shutdown = 0;
5377
5378         /* give hw rings */
5379         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5380         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5381                 base + NvRegRingSizes);
5382
5383         writel(np->linkspeed, base + NvRegLinkSpeed);
5384         if (np->desc_ver == DESC_VER_1)
5385                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5386         else
5387                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5388         writel(np->txrxctl_bits, base + NvRegTxRxControl);
5389         writel(np->vlanctl_bits, base + NvRegVlanControl);
5390         pci_push(base);
5391         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5392         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5393                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
5394                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
5395
5396         writel(0, base + NvRegMIIMask);
5397         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5398         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5399
5400         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5401         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5402         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5403         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5404
5405         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5406
5407         get_random_bytes(&low, sizeof(low));
5408         low &= NVREG_SLOTTIME_MASK;
5409         if (np->desc_ver == DESC_VER_1) {
5410                 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5411         } else {
5412                 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5413                         /* setup legacy backoff */
5414                         writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5415                 } else {
5416                         writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5417                         nv_gear_backoff_reseed(dev);
5418                 }
5419         }
5420         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5421         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5422         if (poll_interval == -1) {
5423                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5424                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5425                 else
5426                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5427         }
5428         else
5429                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5430         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5431         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5432                         base + NvRegAdapterControl);
5433         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5434         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5435         if (np->wolenabled)
5436                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5437
5438         i = readl(base + NvRegPowerState);
5439         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
5440                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5441
5442         pci_push(base);
5443         udelay(10);
5444         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5445
5446         nv_disable_hw_interrupts(dev, np->irqmask);
5447         pci_push(base);
5448         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5449         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5450         pci_push(base);
5451
5452         if (nv_request_irq(dev, 0)) {
5453                 goto out_drain;
5454         }
5455
5456         /* ask for interrupts */
5457         nv_enable_hw_interrupts(dev, np->irqmask);
5458
5459         spin_lock_irq(&np->lock);
5460         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5461         writel(0, base + NvRegMulticastAddrB);
5462         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5463         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5464         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5465         /* One manual link speed update: Interrupts are enabled, future link
5466          * speed changes cause interrupts and are handled by nv_link_irq().
5467          */
5468         {
5469                 u32 miistat;
5470                 miistat = readl(base + NvRegMIIStatus);
5471                 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5472                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
5473         }
5474         /* set linkspeed to invalid value, thus force nv_update_linkspeed
5475          * to init hw */
5476         np->linkspeed = 0;
5477         ret = nv_update_linkspeed(dev);
5478         nv_start_rxtx(dev);
5479         netif_start_queue(dev);
5480         nv_napi_enable(dev);
5481
5482         if (ret) {
5483                 netif_carrier_on(dev);
5484         } else {
5485                 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
5486                 netif_carrier_off(dev);
5487         }
5488         if (oom)
5489                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5490
5491         /* start statistics timer */
5492         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5493                 mod_timer(&np->stats_poll,
5494                         round_jiffies(jiffies + STATS_INTERVAL));
5495
5496         spin_unlock_irq(&np->lock);
5497
5498         return 0;
5499 out_drain:
5500         nv_drain_rxtx(dev);
5501         return ret;
5502 }
5503
5504 static int nv_close(struct net_device *dev)
5505 {
5506         struct fe_priv *np = netdev_priv(dev);
5507         u8 __iomem *base;
5508
5509         spin_lock_irq(&np->lock);
5510         np->in_shutdown = 1;
5511         spin_unlock_irq(&np->lock);
5512         nv_napi_disable(dev);
5513         synchronize_irq(np->pci_dev->irq);
5514
5515         del_timer_sync(&np->oom_kick);
5516         del_timer_sync(&np->nic_poll);
5517         del_timer_sync(&np->stats_poll);
5518
5519         netif_stop_queue(dev);
5520         spin_lock_irq(&np->lock);
5521         nv_stop_rxtx(dev);
5522         nv_txrx_reset(dev);
5523
5524         /* disable interrupts on the nic or we will lock up */
5525         base = get_hwbase(dev);
5526         nv_disable_hw_interrupts(dev, np->irqmask);
5527         pci_push(base);
5528         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5529
5530         spin_unlock_irq(&np->lock);
5531
5532         nv_free_irq(dev);
5533
5534         nv_drain_rxtx(dev);
5535
5536         if (np->wolenabled || !phy_power_down) {
5537                 nv_txrx_gate(dev, false);
5538                 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5539                 nv_start_rx(dev);
5540         } else {
5541                 /* power down phy */
5542                 mii_rw(dev, np->phyaddr, MII_BMCR,
5543                        mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5544                 nv_txrx_gate(dev, true);
5545         }
5546
5547         /* FIXME: power down nic */
5548
5549         return 0;
5550 }
5551
5552 static const struct net_device_ops nv_netdev_ops = {
5553         .ndo_open               = nv_open,
5554         .ndo_stop               = nv_close,
5555         .ndo_get_stats          = nv_get_stats,
5556         .ndo_start_xmit         = nv_start_xmit,
5557         .ndo_tx_timeout         = nv_tx_timeout,
5558         .ndo_change_mtu         = nv_change_mtu,
5559         .ndo_validate_addr      = eth_validate_addr,
5560         .ndo_set_mac_address    = nv_set_mac_address,
5561         .ndo_set_multicast_list = nv_set_multicast,
5562         .ndo_vlan_rx_register   = nv_vlan_rx_register,
5563 #ifdef CONFIG_NET_POLL_CONTROLLER
5564         .ndo_poll_controller    = nv_poll_controller,
5565 #endif
5566 };
5567
5568 static const struct net_device_ops nv_netdev_ops_optimized = {
5569         .ndo_open               = nv_open,
5570         .ndo_stop               = nv_close,
5571         .ndo_get_stats          = nv_get_stats,
5572         .ndo_start_xmit         = nv_start_xmit_optimized,
5573         .ndo_tx_timeout         = nv_tx_timeout,
5574         .ndo_change_mtu         = nv_change_mtu,
5575         .ndo_validate_addr      = eth_validate_addr,
5576         .ndo_set_mac_address    = nv_set_mac_address,
5577         .ndo_set_multicast_list = nv_set_multicast,
5578         .ndo_vlan_rx_register   = nv_vlan_rx_register,
5579 #ifdef CONFIG_NET_POLL_CONTROLLER
5580         .ndo_poll_controller    = nv_poll_controller,
5581 #endif
5582 };
5583
5584 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5585 {
5586         struct net_device *dev;
5587         struct fe_priv *np;
5588         unsigned long addr;
5589         u8 __iomem *base;
5590         int err, i;
5591         u32 powerstate, txreg;
5592         u32 phystate_orig = 0, phystate;
5593         int phyinitialized = 0;
5594         static int printed_version;
5595
5596         if (!printed_version++)
5597                 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
5598                        " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
5599
5600         dev = alloc_etherdev(sizeof(struct fe_priv));
5601         err = -ENOMEM;
5602         if (!dev)
5603                 goto out;
5604
5605         np = netdev_priv(dev);
5606         np->dev = dev;
5607         np->pci_dev = pci_dev;
5608         spin_lock_init(&np->lock);
5609         SET_NETDEV_DEV(dev, &pci_dev->dev);
5610
5611         init_timer(&np->oom_kick);
5612         np->oom_kick.data = (unsigned long) dev;
5613         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
5614         init_timer(&np->nic_poll);
5615         np->nic_poll.data = (unsigned long) dev;
5616         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
5617         init_timer(&np->stats_poll);
5618         np->stats_poll.data = (unsigned long) dev;
5619         np->stats_poll.function = &nv_do_stats_poll;    /* timer handler */
5620
5621         err = pci_enable_device(pci_dev);
5622         if (err)
5623                 goto out_free;
5624
5625         pci_set_master(pci_dev);
5626
5627         err = pci_request_regions(pci_dev, DRV_NAME);
5628         if (err < 0)
5629                 goto out_disable;
5630
5631         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5632                 np->register_size = NV_PCI_REGSZ_VER3;
5633         else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5634                 np->register_size = NV_PCI_REGSZ_VER2;
5635         else
5636                 np->register_size = NV_PCI_REGSZ_VER1;
5637
5638         err = -EINVAL;
5639         addr = 0;
5640         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5641                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
5642                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
5643                                 pci_resource_len(pci_dev, i),
5644                                 pci_resource_flags(pci_dev, i));
5645                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5646                                 pci_resource_len(pci_dev, i) >= np->register_size) {
5647                         addr = pci_resource_start(pci_dev, i);
5648                         break;
5649                 }
5650         }
5651         if (i == DEVICE_COUNT_RESOURCE) {
5652                 dev_printk(KERN_INFO, &pci_dev->dev,
5653                            "Couldn't find register window\n");
5654                 goto out_relreg;
5655         }
5656
5657         /* copy of driver data */
5658         np->driver_data = id->driver_data;
5659         /* copy of device id */
5660         np->device_id = id->device;
5661
5662         /* handle different descriptor versions */
5663         if (id->driver_data & DEV_HAS_HIGH_DMA) {
5664                 /* packet format 3: supports 40-bit addressing */
5665                 np->desc_ver = DESC_VER_3;
5666                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5667                 if (dma_64bit) {
5668                         if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
5669                                 dev_printk(KERN_INFO, &pci_dev->dev,
5670                                         "64-bit DMA failed, using 32-bit addressing\n");
5671                         else
5672                                 dev->features |= NETIF_F_HIGHDMA;
5673                         if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
5674                                 dev_printk(KERN_INFO, &pci_dev->dev,
5675                                         "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5676                         }
5677                 }
5678         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5679                 /* packet format 2: supports jumbo frames */
5680                 np->desc_ver = DESC_VER_2;
5681                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5682         } else {
5683                 /* original packet format */
5684                 np->desc_ver = DESC_VER_1;
5685                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5686         }
5687
5688         np->pkt_limit = NV_PKTLIMIT_1;
5689         if (id->driver_data & DEV_HAS_LARGEDESC)
5690                 np->pkt_limit = NV_PKTLIMIT_2;
5691
5692         if (id->driver_data & DEV_HAS_CHECKSUM) {
5693                 np->rx_csum = 1;
5694                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5695                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
5696                 dev->features |= NETIF_F_TSO;
5697         }
5698
5699         np->vlanctl_bits = 0;
5700         if (id->driver_data & DEV_HAS_VLAN) {
5701                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5702                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5703         }
5704
5705         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5706         if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5707             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5708             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5709                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5710         }
5711
5712
5713         err = -ENOMEM;
5714         np->base = ioremap(addr, np->register_size);
5715         if (!np->base)
5716                 goto out_relreg;
5717         dev->base_addr = (unsigned long)np->base;
5718
5719         dev->irq = pci_dev->irq;
5720
5721         np->rx_ring_size = RX_RING_DEFAULT;
5722         np->tx_ring_size = TX_RING_DEFAULT;
5723
5724         if (!nv_optimized(np)) {
5725                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5726                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5727                                         &np->ring_addr);
5728                 if (!np->rx_ring.orig)
5729                         goto out_unmap;
5730                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5731         } else {
5732                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5733                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5734                                         &np->ring_addr);
5735                 if (!np->rx_ring.ex)
5736                         goto out_unmap;
5737                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5738         }
5739         np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5740         np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5741         if (!np->rx_skb || !np->tx_skb)
5742                 goto out_freering;
5743
5744         if (!nv_optimized(np))
5745                 dev->netdev_ops = &nv_netdev_ops;
5746         else
5747                 dev->netdev_ops = &nv_netdev_ops_optimized;
5748
5749 #ifdef CONFIG_FORCEDETH_NAPI
5750         netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5751 #endif
5752         SET_ETHTOOL_OPS(dev, &ops);
5753         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5754
5755         pci_set_drvdata(pci_dev, dev);
5756
5757         /* read the mac address */
5758         base = get_hwbase(dev);
5759         np->orig_mac[0] = readl(base + NvRegMacAddrA);
5760         np->orig_mac[1] = readl(base + NvRegMacAddrB);
5761
5762         /* check the workaround bit for correct mac address order */
5763         txreg = readl(base + NvRegTransmitPoll);
5764         if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5765                 /* mac address is already in correct order */
5766                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5767                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5768                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5769                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5770                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5771                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5772         } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5773                 /* mac address is already in correct order */
5774                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5775                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5776                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5777                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5778                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5779                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5780                 /*
5781                  * Set orig mac address back to the reversed version.
5782                  * This flag will be cleared during low power transition.
5783                  * Therefore, we should always put back the reversed address.
5784                  */
5785                 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5786                         (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5787                 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5788         } else {
5789                 /* need to reverse mac address to correct order */
5790                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
5791                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
5792                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5793                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5794                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
5795                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
5796                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5797                 printk(KERN_DEBUG "nv_probe: set workaround bit for reversed mac addr\n");
5798         }
5799         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5800
5801         if (!is_valid_ether_addr(dev->perm_addr)) {
5802                 /*
5803                  * Bad mac address. At least one bios sets the mac address
5804                  * to 01:23:45:67:89:ab
5805                  */
5806                 dev_printk(KERN_ERR, &pci_dev->dev,
5807                         "Invalid Mac address detected: %pM\n",
5808                         dev->dev_addr);
5809                 dev_printk(KERN_ERR, &pci_dev->dev,
5810                         "Please complain to your hardware vendor. Switching to a random MAC.\n");
5811                 dev->dev_addr[0] = 0x00;
5812                 dev->dev_addr[1] = 0x00;
5813                 dev->dev_addr[2] = 0x6c;
5814                 get_random_bytes(&dev->dev_addr[3], 3);
5815         }
5816
5817         dprintk(KERN_DEBUG "%s: MAC Address %pM\n",
5818                 pci_name(pci_dev), dev->dev_addr);
5819
5820         /* set mac address */
5821         nv_copy_mac_to_hw(dev);
5822
5823         /* Workaround current PCI init glitch:  wakeup bits aren't
5824          * being set from PCI PM capability.
5825          */
5826         device_init_wakeup(&pci_dev->dev, 1);
5827
5828         /* disable WOL */
5829         writel(0, base + NvRegWakeUpFlags);
5830         np->wolenabled = 0;
5831
5832         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5833
5834                 /* take phy and nic out of low power mode */
5835                 powerstate = readl(base + NvRegPowerState2);
5836                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5837                 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
5838                     pci_dev->revision >= 0xA3)
5839                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5840                 writel(powerstate, base + NvRegPowerState2);
5841         }
5842
5843         if (np->desc_ver == DESC_VER_1) {
5844                 np->tx_flags = NV_TX_VALID;
5845         } else {
5846                 np->tx_flags = NV_TX2_VALID;
5847         }
5848
5849         np->msi_flags = 0;
5850         if ((id->driver_data & DEV_HAS_MSI) && msi) {
5851                 np->msi_flags |= NV_MSI_CAPABLE;
5852         }
5853         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5854                 /* msix has had reported issues when modifying irqmask
5855                    as in the case of napi, therefore, disable for now
5856                 */
5857 #ifndef CONFIG_FORCEDETH_NAPI
5858                 np->msi_flags |= NV_MSI_X_CAPABLE;
5859 #endif
5860         }
5861
5862         if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
5863                 np->irqmask = NVREG_IRQMASK_CPU;
5864                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5865                         np->msi_flags |= 0x0001;
5866         } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5867                    !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5868                 /* start off in throughput mode */
5869                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5870                 /* remove support for msix mode */
5871                 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5872         } else {
5873                 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5874                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5875                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5876                         np->msi_flags |= 0x0003;
5877         }
5878
5879         if (id->driver_data & DEV_NEED_TIMERIRQ)
5880                 np->irqmask |= NVREG_IRQ_TIMER;
5881         if (id->driver_data & DEV_NEED_LINKTIMER) {
5882                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5883                 np->need_linktimer = 1;
5884                 np->link_timeout = jiffies + LINK_TIMEOUT;
5885         } else {
5886                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5887                 np->need_linktimer = 0;
5888         }
5889
5890         /* Limit the number of tx's outstanding for hw bug */
5891         if (id->driver_data & DEV_NEED_TX_LIMIT) {
5892                 np->tx_limit = 1;
5893                 if ((id->driver_data & DEV_NEED_TX_LIMIT2) &&
5894                     pci_dev->revision >= 0xA2)
5895                         np->tx_limit = 0;
5896         }
5897
5898         /* clear phy state and temporarily halt phy interrupts */
5899         writel(0, base + NvRegMIIMask);
5900         phystate = readl(base + NvRegAdapterControl);
5901         if (phystate & NVREG_ADAPTCTL_RUNNING) {
5902                 phystate_orig = 1;
5903                 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5904                 writel(phystate, base + NvRegAdapterControl);
5905         }
5906         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5907
5908         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5909                 /* management unit running on the mac? */
5910                 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5911                     (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5912                     nv_mgmt_acquire_sema(dev) &&
5913                     nv_mgmt_get_version(dev)) {
5914                         np->mac_in_use = 1;
5915                         if (np->mgmt_version > 0) {
5916                                 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
5917                         }
5918                         dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n",
5919                                 pci_name(pci_dev), np->mac_in_use);
5920                         /* management unit setup the phy already? */
5921                         if (np->mac_in_use &&
5922                             ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5923                              NVREG_XMITCTL_SYNC_PHY_INIT)) {
5924                                 /* phy is inited by mgmt unit */
5925                                 phyinitialized = 1;
5926                                 dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n",
5927                                         pci_name(pci_dev));
5928                         } else {
5929                                 /* we need to init the phy */
5930                         }
5931                 }
5932         }
5933
5934         /* find a suitable phy */
5935         for (i = 1; i <= 32; i++) {
5936                 int id1, id2;
5937                 int phyaddr = i & 0x1F;
5938
5939                 spin_lock_irq(&np->lock);
5940                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5941                 spin_unlock_irq(&np->lock);
5942                 if (id1 < 0 || id1 == 0xffff)
5943                         continue;
5944                 spin_lock_irq(&np->lock);
5945                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5946                 spin_unlock_irq(&np->lock);
5947                 if (id2 < 0 || id2 == 0xffff)
5948                         continue;
5949
5950                 np->phy_model = id2 & PHYID2_MODEL_MASK;
5951                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5952                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5953                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
5954                         pci_name(pci_dev), id1, id2, phyaddr);
5955                 np->phyaddr = phyaddr;
5956                 np->phy_oui = id1 | id2;
5957
5958                 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5959                 if (np->phy_oui == PHY_OUI_REALTEK2)
5960                         np->phy_oui = PHY_OUI_REALTEK;
5961                 /* Setup phy revision for Realtek */
5962                 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5963                         np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5964
5965                 break;
5966         }
5967         if (i == 33) {
5968                 dev_printk(KERN_INFO, &pci_dev->dev,
5969                         "open: Could not find a valid PHY.\n");
5970                 goto out_error;
5971         }
5972
5973         if (!phyinitialized) {
5974                 /* reset it */
5975                 phy_init(dev);
5976         } else {
5977                 /* see if it is a gigabit phy */
5978                 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5979                 if (mii_status & PHY_GIGABIT) {
5980                         np->gigabit = PHY_GIGABIT;
5981                 }
5982         }
5983
5984         /* set default link speed settings */
5985         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5986         np->duplex = 0;
5987         np->autoneg = 1;
5988
5989         err = register_netdev(dev);
5990         if (err) {
5991                 dev_printk(KERN_INFO, &pci_dev->dev,
5992                            "unable to register netdev: %d\n", err);
5993                 goto out_error;
5994         }
5995
5996         dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, "
5997                    "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
5998                    dev->name,
5999                    np->phy_oui,
6000                    np->phyaddr,
6001                    dev->dev_addr[0],
6002                    dev->dev_addr[1],
6003                    dev->dev_addr[2],
6004                    dev->dev_addr[3],
6005                    dev->dev_addr[4],
6006                    dev->dev_addr[5]);
6007
6008         dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
6009                    dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
6010                    dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
6011                         "csum " : "",
6012                    dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
6013                         "vlan " : "",
6014                    id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
6015                    id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
6016                    id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
6017                    np->gigabit == PHY_GIGABIT ? "gbit " : "",
6018                    np->need_linktimer ? "lnktim " : "",
6019                    np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
6020                    np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
6021                    np->desc_ver);
6022
6023         return 0;
6024
6025 out_error:
6026         if (phystate_orig)
6027                 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
6028         pci_set_drvdata(pci_dev, NULL);
6029 out_freering:
6030         free_rings(dev);
6031 out_unmap:
6032         iounmap(get_hwbase(dev));
6033 out_relreg:
6034         pci_release_regions(pci_dev);
6035 out_disable:
6036         pci_disable_device(pci_dev);
6037 out_free:
6038         free_netdev(dev);
6039 out:
6040         return err;
6041 }
6042
6043 static void nv_restore_phy(struct net_device *dev)
6044 {
6045         struct fe_priv *np = netdev_priv(dev);
6046         u16 phy_reserved, mii_control;
6047
6048         if (np->phy_oui == PHY_OUI_REALTEK &&
6049             np->phy_model == PHY_MODEL_REALTEK_8201 &&
6050             phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
6051                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
6052                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
6053                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
6054                 phy_reserved |= PHY_REALTEK_INIT8;
6055                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
6056                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
6057
6058                 /* restart auto negotiation */
6059                 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
6060                 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
6061                 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
6062         }
6063 }
6064
6065 static void nv_restore_mac_addr(struct pci_dev *pci_dev)
6066 {
6067         struct net_device *dev = pci_get_drvdata(pci_dev);
6068         struct fe_priv *np = netdev_priv(dev);
6069         u8 __iomem *base = get_hwbase(dev);
6070
6071         /* special op: write back the misordered MAC address - otherwise
6072          * the next nv_probe would see a wrong address.
6073          */
6074         writel(np->orig_mac[0], base + NvRegMacAddrA);
6075         writel(np->orig_mac[1], base + NvRegMacAddrB);
6076         writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
6077                base + NvRegTransmitPoll);
6078 }
6079
6080 static void __devexit nv_remove(struct pci_dev *pci_dev)
6081 {
6082         struct net_device *dev = pci_get_drvdata(pci_dev);
6083
6084         unregister_netdev(dev);
6085
6086         nv_restore_mac_addr(pci_dev);
6087
6088         /* restore any phy related changes */
6089         nv_restore_phy(dev);
6090
6091         nv_mgmt_release_sema(dev);
6092
6093         /* free all structures */
6094         free_rings(dev);
6095         iounmap(get_hwbase(dev));
6096         pci_release_regions(pci_dev);
6097         pci_disable_device(pci_dev);
6098         free_netdev(dev);
6099         pci_set_drvdata(pci_dev, NULL);
6100 }
6101
6102 #ifdef CONFIG_PM
6103 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
6104 {
6105         struct net_device *dev = pci_get_drvdata(pdev);
6106         struct fe_priv *np = netdev_priv(dev);
6107         u8 __iomem *base = get_hwbase(dev);
6108         int i;
6109
6110         if (netif_running(dev)) {
6111                 // Gross.
6112                 nv_close(dev);
6113         }
6114         netif_device_detach(dev);
6115
6116         /* save non-pci configuration space */
6117         for (i = 0;i <= np->register_size/sizeof(u32); i++)
6118                 np->saved_config_space[i] = readl(base + i*sizeof(u32));
6119
6120         pci_save_state(pdev);
6121         pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
6122         pci_disable_device(pdev);
6123         pci_set_power_state(pdev, pci_choose_state(pdev, state));
6124         return 0;
6125 }
6126
6127 static int nv_resume(struct pci_dev *pdev)
6128 {
6129         struct net_device *dev = pci_get_drvdata(pdev);
6130         struct fe_priv *np = netdev_priv(dev);
6131         u8 __iomem *base = get_hwbase(dev);
6132         int i, rc = 0;
6133
6134         pci_set_power_state(pdev, PCI_D0);
6135         pci_restore_state(pdev);
6136         /* ack any pending wake events, disable PME */
6137         pci_enable_wake(pdev, PCI_D0, 0);
6138
6139         /* restore non-pci configuration space */
6140         for (i = 0;i <= np->register_size/sizeof(u32); i++)
6141                 writel(np->saved_config_space[i], base+i*sizeof(u32));
6142
6143         if (np->driver_data & DEV_NEED_MSI_FIX)
6144                 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
6145
6146         /* restore phy state, including autoneg */
6147         phy_init(dev);
6148
6149         netif_device_attach(dev);
6150         if (netif_running(dev)) {
6151                 rc = nv_open(dev);
6152                 nv_set_multicast(dev);
6153         }
6154         return rc;
6155 }
6156
6157 static void nv_shutdown(struct pci_dev *pdev)
6158 {
6159         struct net_device *dev = pci_get_drvdata(pdev);
6160         struct fe_priv *np = netdev_priv(dev);
6161
6162         if (netif_running(dev))
6163                 nv_close(dev);
6164
6165         /*
6166          * Restore the MAC so a kernel started by kexec won't get confused.
6167          * If we really go for poweroff, we must not restore the MAC,
6168          * otherwise the MAC for WOL will be reversed at least on some boards.
6169          */
6170         if (system_state != SYSTEM_POWER_OFF) {
6171                 nv_restore_mac_addr(pdev);
6172         }
6173
6174         pci_disable_device(pdev);
6175         /*
6176          * Apparently it is not possible to reinitialise from D3 hot,
6177          * only put the device into D3 if we really go for poweroff.
6178          */
6179         if (system_state == SYSTEM_POWER_OFF) {
6180                 if (pci_enable_wake(pdev, PCI_D3cold, np->wolenabled))
6181                         pci_enable_wake(pdev, PCI_D3hot, np->wolenabled);
6182                 pci_set_power_state(pdev, PCI_D3hot);
6183         }
6184 }
6185 #else
6186 #define nv_suspend NULL
6187 #define nv_shutdown NULL
6188 #define nv_resume NULL
6189 #endif /* CONFIG_PM */
6190
6191 static struct pci_device_id pci_tbl[] = {
6192         {       /* nForce Ethernet Controller */
6193                 PCI_DEVICE(0x10DE, 0x01C3),
6194                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6195         },
6196         {       /* nForce2 Ethernet Controller */
6197                 PCI_DEVICE(0x10DE, 0x0066),
6198                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6199         },
6200         {       /* nForce3 Ethernet Controller */
6201                 PCI_DEVICE(0x10DE, 0x00D6),
6202                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6203         },
6204         {       /* nForce3 Ethernet Controller */
6205                 PCI_DEVICE(0x10DE, 0x0086),
6206                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6207         },
6208         {       /* nForce3 Ethernet Controller */
6209                 PCI_DEVICE(0x10DE, 0x008C),
6210                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6211         },
6212         {       /* nForce3 Ethernet Controller */
6213                 PCI_DEVICE(0x10DE, 0x00E6),
6214                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6215         },
6216         {       /* nForce3 Ethernet Controller */
6217                 PCI_DEVICE(0x10DE, 0x00DF),
6218                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6219         },
6220         {       /* CK804 Ethernet Controller */
6221                 PCI_DEVICE(0x10DE, 0x0056),
6222                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6223         },
6224         {       /* CK804 Ethernet Controller */
6225                 PCI_DEVICE(0x10DE, 0x0057),
6226                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6227         },
6228         {       /* MCP04 Ethernet Controller */
6229                 PCI_DEVICE(0x10DE, 0x0037),
6230                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6231         },
6232         {       /* MCP04 Ethernet Controller */
6233                 PCI_DEVICE(0x10DE, 0x0038),
6234                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6235         },
6236         {       /* MCP51 Ethernet Controller */
6237                 PCI_DEVICE(0x10DE, 0x0268),
6238                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6239         },
6240         {       /* MCP51 Ethernet Controller */
6241                 PCI_DEVICE(0x10DE, 0x0269),
6242                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6243         },
6244         {       /* MCP55 Ethernet Controller */
6245                 PCI_DEVICE(0x10DE, 0x0372),
6246                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6247         },
6248         {       /* MCP55 Ethernet Controller */
6249                 PCI_DEVICE(0x10DE, 0x0373),
6250                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6251         },
6252         {       /* MCP61 Ethernet Controller */
6253                 PCI_DEVICE(0x10DE, 0x03E5),
6254                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6255         },
6256         {       /* MCP61 Ethernet Controller */
6257                 PCI_DEVICE(0x10DE, 0x03E6),
6258                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6259         },
6260         {       /* MCP61 Ethernet Controller */
6261                 PCI_DEVICE(0x10DE, 0x03EE),
6262                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6263         },
6264         {       /* MCP61 Ethernet Controller */
6265                 PCI_DEVICE(0x10DE, 0x03EF),
6266                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6267         },
6268         {       /* MCP65 Ethernet Controller */
6269                 PCI_DEVICE(0x10DE, 0x0450),
6270                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6271         },
6272         {       /* MCP65 Ethernet Controller */
6273                 PCI_DEVICE(0x10DE, 0x0451),
6274                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6275         },
6276         {       /* MCP65 Ethernet Controller */
6277                 PCI_DEVICE(0x10DE, 0x0452),
6278                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6279         },
6280         {       /* MCP65 Ethernet Controller */
6281                 PCI_DEVICE(0x10DE, 0x0453),
6282                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6283         },
6284         {       /* MCP67 Ethernet Controller */
6285                 PCI_DEVICE(0x10DE, 0x054C),
6286                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6287         },
6288         {       /* MCP67 Ethernet Controller */
6289                 PCI_DEVICE(0x10DE, 0x054D),
6290                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6291         },
6292         {       /* MCP67 Ethernet Controller */
6293                 PCI_DEVICE(0x10DE, 0x054E),
6294                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6295         },
6296         {       /* MCP67 Ethernet Controller */
6297                 PCI_DEVICE(0x10DE, 0x054F),
6298                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6299         },
6300         {       /* MCP73 Ethernet Controller */
6301                 PCI_DEVICE(0x10DE, 0x07DC),
6302                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6303         },
6304         {       /* MCP73 Ethernet Controller */
6305                 PCI_DEVICE(0x10DE, 0x07DD),
6306                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6307         },
6308         {       /* MCP73 Ethernet Controller */
6309                 PCI_DEVICE(0x10DE, 0x07DE),
6310                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6311         },
6312         {       /* MCP73 Ethernet Controller */
6313                 PCI_DEVICE(0x10DE, 0x07DF),
6314                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6315         },
6316         {       /* MCP77 Ethernet Controller */
6317                 PCI_DEVICE(0x10DE, 0x0760),
6318                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6319         },
6320         {       /* MCP77 Ethernet Controller */
6321                 PCI_DEVICE(0x10DE, 0x0761),
6322                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6323         },
6324         {       /* MCP77 Ethernet Controller */
6325                 PCI_DEVICE(0x10DE, 0x0762),
6326                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6327         },
6328         {       /* MCP77 Ethernet Controller */
6329                 PCI_DEVICE(0x10DE, 0x0763),
6330                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6331         },
6332         {       /* MCP79 Ethernet Controller */
6333                 PCI_DEVICE(0x10DE, 0x0AB0),
6334                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6335         },
6336         {       /* MCP79 Ethernet Controller */
6337                 PCI_DEVICE(0x10DE, 0x0AB1),
6338                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6339         },
6340         {       /* MCP79 Ethernet Controller */
6341                 PCI_DEVICE(0x10DE, 0x0AB2),
6342                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6343         },
6344         {       /* MCP79 Ethernet Controller */
6345                 PCI_DEVICE(0x10DE, 0x0AB3),
6346                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6347         },
6348         {       /* MCP89 Ethernet Controller */
6349                 PCI_DEVICE(0x10DE, 0x0D7D),
6350                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
6351         },
6352         {0,},
6353 };
6354
6355 static struct pci_driver driver = {
6356         .name           = DRV_NAME,
6357         .id_table       = pci_tbl,
6358         .probe          = nv_probe,
6359         .remove         = __devexit_p(nv_remove),
6360         .suspend        = nv_suspend,
6361         .resume         = nv_resume,
6362         .shutdown       = nv_shutdown,
6363 };
6364
6365 static int __init init_nic(void)
6366 {
6367         return pci_register_driver(&driver);
6368 }
6369
6370 static void __exit exit_nic(void)
6371 {
6372         pci_unregister_driver(&driver);
6373 }
6374
6375 module_param(max_interrupt_work, int, 0);
6376 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
6377 module_param(optimization_mode, int, 0);
6378 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
6379 module_param(poll_interval, int, 0);
6380 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6381 module_param(msi, int, 0);
6382 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6383 module_param(msix, int, 0);
6384 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6385 module_param(dma_64bit, int, 0);
6386 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6387 module_param(phy_cross, int, 0);
6388 MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6389 module_param(phy_power_down, int, 0);
6390 MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6391
6392 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6393 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6394 MODULE_LICENSE("GPL");
6395
6396 MODULE_DEVICE_TABLE(pci, pci_tbl);
6397
6398 module_init(init_nic);
6399 module_exit(exit_nic);