drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey.
   7  *
   8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
   9  * trademarks of NVIDIA Corporation in the United States and other
  10  * countries.
  11  *
  12  * Copyright (C) 2003,4,5 Manfred Spraul
  13  * Copyright (C) 2004 Andrew de Quincey (wol support)
  14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  16  * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License as published by
  20  * the Free Software Foundation; either version 2 of the License, or
  21  * (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  31  *
  32  * Known bugs:
  33  * We suspect that on some hardware no TX done interrupts are generated.
  34  * This means recovery from netif_stop_queue only happens if the hw timer
  35  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
  36  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
  37  * If your hardware reliably generates tx done interrupts, then you can remove
  38  * DEV_NEED_TIMERIRQ from the driver_data flags.
  39  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
  40  * superfluous timer interrupts from the nic.
  41  */
  42 #define FORCEDETH_VERSION               "0.63"
  43 #define DRV_NAME                        "forcedeth"
  44
  45 #include <linux/module.h>
  46 #include <linux/types.h>
  47 #include <linux/pci.h>
  48 #include <linux/interrupt.h>
  49 #include <linux/netdevice.h>
  50 #include <linux/etherdevice.h>
  51 #include <linux/delay.h>
  52 #include <linux/spinlock.h>
  53 #include <linux/ethtool.h>
  54 #include <linux/timer.h>
  55 #include <linux/skbuff.h>
  56 #include <linux/mii.h>
  57 #include <linux/random.h>
  58 #include <linux/init.h>
  59 #include <linux/if_vlan.h>
  60 #include <linux/dma-mapping.h>
  61
  62 #include <asm/irq.h>
  63 #include <asm/io.h>
  64 #include <asm/uaccess.h>
  65 #include <asm/system.h>
  66
  67 #if 0
  68 #define dprintk                 printk
  69 #else
  70 #define dprintk(x...)           do { } while (0)
  71 #endif
  72
  73 #define TX_WORK_PER_LOOP  64
  74 #define RX_WORK_PER_LOOP  64
  75
  76 /*
  77  * Hardware access:
  78  */
  79
  80 #define DEV_NEED_TIMERIRQ          0x000001  /* set the timer irq flag in the irq mask */
  81 #define DEV_NEED_LINKTIMER         0x000002  /* poll link settings. Relies on the timer irq */
  82 #define DEV_HAS_LARGEDESC          0x000004  /* device supports jumbo frames and needs packet format 2 */
  83 #define DEV_HAS_HIGH_DMA           0x000008  /* device supports 64bit dma */
  84 #define DEV_HAS_CHECKSUM           0x000010  /* device supports tx and rx checksum offloads */
  85 #define DEV_HAS_VLAN               0x000020  /* device supports vlan tagging and striping */
  86 #define DEV_HAS_MSI                0x000040  /* device supports MSI */
  87 #define DEV_HAS_MSI_X              0x000080  /* device supports MSI-X */
  88 #define DEV_HAS_POWER_CNTRL        0x000100  /* device supports power savings */
  89 #define DEV_HAS_STATISTICS_V1      0x000200  /* device supports hw statistics version 1 */
  90 #define DEV_HAS_STATISTICS_V2      0x000600  /* device supports hw statistics version 2 */
  91 #define DEV_HAS_STATISTICS_V3      0x000e00  /* device supports hw statistics version 3 */
  92 #define DEV_HAS_TEST_EXTENDED      0x001000  /* device supports extended diagnostic test */
  93 #define DEV_HAS_MGMT_UNIT          0x002000  /* device supports management unit */
  94 #define DEV_HAS_CORRECT_MACADDR    0x004000  /* device supports correct mac address order */
  95 #define DEV_HAS_COLLISION_FIX      0x008000  /* device supports tx collision fix */
  96 #define DEV_HAS_PAUSEFRAME_TX_V1   0x010000  /* device supports tx pause frames version 1 */
  97 #define DEV_HAS_PAUSEFRAME_TX_V2   0x020000  /* device supports tx pause frames version 2 */
  98 #define DEV_HAS_PAUSEFRAME_TX_V3   0x040000  /* device supports tx pause frames version 3 */
  99 #define DEV_NEED_TX_LIMIT          0x080000  /* device needs to limit tx */
 100 #define DEV_HAS_GEAR_MODE          0x100000  /* device supports gear mode */
 101
 102 enum {
 103         NvRegIrqStatus = 0x000,
 104 #define NVREG_IRQSTAT_MIIEVENT  0x040
 105 #define NVREG_IRQSTAT_MASK              0x83ff
 106         NvRegIrqMask = 0x004,
 107 #define NVREG_IRQ_RX_ERROR              0x0001
 108 #define NVREG_IRQ_RX                    0x0002
 109 #define NVREG_IRQ_RX_NOBUF              0x0004
 110 #define NVREG_IRQ_TX_ERR                0x0008
 111 #define NVREG_IRQ_TX_OK                 0x0010
 112 #define NVREG_IRQ_TIMER                 0x0020
 113 #define NVREG_IRQ_LINK                  0x0040
 114 #define NVREG_IRQ_RX_FORCED             0x0080
 115 #define NVREG_IRQ_TX_FORCED             0x0100
 116 #define NVREG_IRQ_RECOVER_ERROR         0x8200
 117 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 118 #define NVREG_IRQMASK_CPU               0x0060
 119 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 120 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 121 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
 122
 123 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
 124                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
 125                                         NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
 126
 127         NvRegUnknownSetupReg6 = 0x008,
 128 #define NVREG_UNKSETUP6_VAL             3
 129
 130 /*
 131  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 132  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 133  */
 134         NvRegPollingInterval = 0x00c,
 135 #define NVREG_POLL_DEFAULT_THROUGHPUT   970 /* backup tx cleanup if loop max reached */
 136 #define NVREG_POLL_DEFAULT_CPU  13
 137         NvRegMSIMap0 = 0x020,
 138         NvRegMSIMap1 = 0x024,
 139         NvRegMSIIrqMask = 0x030,
 140 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 141         NvRegMisc1 = 0x080,
 142 #define NVREG_MISC1_PAUSE_TX    0x01
 143 #define NVREG_MISC1_HD          0x02
 144 #define NVREG_MISC1_FORCE       0x3b0f3c
 145
 146         NvRegMacReset = 0x34,
 147 #define NVREG_MAC_RESET_ASSERT  0x0F3
 148         NvRegTransmitterControl = 0x084,
 149 #define NVREG_XMITCTL_START     0x01
 150 #define NVREG_XMITCTL_MGMT_ST   0x40000000
 151 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
 152 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
 153 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
 154 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
 155 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
 156 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
 157 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
 158 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
 159 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
 160 #define NVREG_XMITCTL_DATA_START        0x00100000
 161 #define NVREG_XMITCTL_DATA_READY        0x00010000
 162 #define NVREG_XMITCTL_DATA_ERROR        0x00020000
 163         NvRegTransmitterStatus = 0x088,
 164 #define NVREG_XMITSTAT_BUSY     0x01
 165
 166         NvRegPacketFilterFlags = 0x8c,
 167 #define NVREG_PFF_PAUSE_RX      0x08
 168 #define NVREG_PFF_ALWAYS        0x7F0000
 169 #define NVREG_PFF_PROMISC       0x80
 170 #define NVREG_PFF_MYADDR        0x20
 171 #define NVREG_PFF_LOOPBACK      0x10
 172
 173         NvRegOffloadConfig = 0x90,
 174 #define NVREG_OFFLOAD_HOMEPHY   0x601
 175 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 176         NvRegReceiverControl = 0x094,
 177 #define NVREG_RCVCTL_START      0x01
 178 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
 179         NvRegReceiverStatus = 0x98,
 180 #define NVREG_RCVSTAT_BUSY      0x01
 181
 182         NvRegSlotTime = 0x9c,
 183 #define NVREG_SLOTTIME_LEGBF_ENABLED    0x80000000
 184 #define NVREG_SLOTTIME_10_100_FULL      0x00007f00
 185 #define NVREG_SLOTTIME_1000_FULL        0x0003ff00
 186 #define NVREG_SLOTTIME_HALF             0x0000ff00
 187 #define NVREG_SLOTTIME_DEFAULT          0x00007f00
 188 #define NVREG_SLOTTIME_MASK             0x000000ff
 189
 190         NvRegTxDeferral = 0xA0,
 191 #define NVREG_TX_DEFERRAL_DEFAULT               0x15050f
 192 #define NVREG_TX_DEFERRAL_RGMII_10_100          0x16070f
 193 #define NVREG_TX_DEFERRAL_RGMII_1000            0x14050f
 194 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10      0x16190f
 195 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100     0x16300f
 196 #define NVREG_TX_DEFERRAL_MII_STRETCH           0x152000
 197         NvRegRxDeferral = 0xA4,
 198 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
 199         NvRegMacAddrA = 0xA8,
 200         NvRegMacAddrB = 0xAC,
 201         NvRegMulticastAddrA = 0xB0,
 202 #define NVREG_MCASTADDRA_FORCE  0x01
 203         NvRegMulticastAddrB = 0xB4,
 204         NvRegMulticastMaskA = 0xB8,
 205 #define NVREG_MCASTMASKA_NONE           0xffffffff
 206         NvRegMulticastMaskB = 0xBC,
 207 #define NVREG_MCASTMASKB_NONE           0xffff
 208
 209         NvRegPhyInterface = 0xC0,
 210 #define PHY_RGMII               0x10000000
 211         NvRegBackOffControl = 0xC4,
 212 #define NVREG_BKOFFCTRL_DEFAULT                 0x70000000
 213 #define NVREG_BKOFFCTRL_SEED_MASK               0x000003ff
 214 #define NVREG_BKOFFCTRL_SELECT                  24
 215 #define NVREG_BKOFFCTRL_GEAR                    12
 216
 217         NvRegTxRingPhysAddr = 0x100,
 218         NvRegRxRingPhysAddr = 0x104,
 219         NvRegRingSizes = 0x108,
 220 #define NVREG_RINGSZ_TXSHIFT 0
 221 #define NVREG_RINGSZ_RXSHIFT 16
 222         NvRegTransmitPoll = 0x10c,
 223 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
 224         NvRegLinkSpeed = 0x110,
 225 #define NVREG_LINKSPEED_FORCE 0x10000
 226 #define NVREG_LINKSPEED_10      1000
 227 #define NVREG_LINKSPEED_100     100
 228 #define NVREG_LINKSPEED_1000    50
 229 #define NVREG_LINKSPEED_MASK    (0xFFF)
 230         NvRegUnknownSetupReg5 = 0x130,
 231 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 232         NvRegTxWatermark = 0x13c,
 233 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
 234 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
 235 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
 236         NvRegTxRxControl = 0x144,
 237 #define NVREG_TXRXCTL_KICK      0x0001
 238 #define NVREG_TXRXCTL_BIT1      0x0002
 239 #define NVREG_TXRXCTL_BIT2      0x0004
 240 #define NVREG_TXRXCTL_IDLE      0x0008
 241 #define NVREG_TXRXCTL_RESET     0x0010
 242 #define NVREG_TXRXCTL_RXCHECK   0x0400
 243 #define NVREG_TXRXCTL_DESC_1    0
 244 #define NVREG_TXRXCTL_DESC_2    0x002100
 245 #define NVREG_TXRXCTL_DESC_3    0xc02200
 246 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 247 #define NVREG_TXRXCTL_VLANINS   0x00080
 248         NvRegTxRingPhysAddrHigh = 0x148,
 249         NvRegRxRingPhysAddrHigh = 0x14C,
 250         NvRegTxPauseFrame = 0x170,
 251 #define NVREG_TX_PAUSEFRAME_DISABLE     0x0fff0080
 252 #define NVREG_TX_PAUSEFRAME_ENABLE_V1   0x01800010
 253 #define NVREG_TX_PAUSEFRAME_ENABLE_V2   0x056003f0
 254 #define NVREG_TX_PAUSEFRAME_ENABLE_V3   0x09f00880
 255         NvRegTxPauseFrameLimit = 0x174,
 256 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
 257         NvRegMIIStatus = 0x180,
 258 #define NVREG_MIISTAT_ERROR             0x0001
 259 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 260 #define NVREG_MIISTAT_MASK_RW           0x0007
 261 #define NVREG_MIISTAT_MASK_ALL          0x000f
 262         NvRegMIIMask = 0x184,
 263 #define NVREG_MII_LINKCHANGE            0x0008
 264
 265         NvRegAdapterControl = 0x188,
 266 #define NVREG_ADAPTCTL_START    0x02
 267 #define NVREG_ADAPTCTL_LINKUP   0x04
 268 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 269 #define NVREG_ADAPTCTL_RUNNING  0x100000
 270 #define NVREG_ADAPTCTL_PHYSHIFT 24
 271         NvRegMIISpeed = 0x18c,
 272 #define NVREG_MIISPEED_BIT8     (1<<8)
 273 #define NVREG_MIIDELAY  5
 274         NvRegMIIControl = 0x190,
 275 #define NVREG_MIICTL_INUSE      0x08000
 276 #define NVREG_MIICTL_WRITE      0x00400
 277 #define NVREG_MIICTL_ADDRSHIFT  5
 278         NvRegMIIData = 0x194,
 279         NvRegTxUnicast = 0x1a0,
 280         NvRegTxMulticast = 0x1a4,
 281         NvRegTxBroadcast = 0x1a8,
 282         NvRegWakeUpFlags = 0x200,
 283 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 284 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 285 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 286 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 287 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 288 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 289 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 290 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 291 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 292 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 293 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 294
 295         NvRegMgmtUnitGetVersion = 0x204,
 296 #define NVREG_MGMTUNITGETVERSION        0x01
 297         NvRegMgmtUnitVersion = 0x208,
 298 #define NVREG_MGMTUNITVERSION           0x08
 299         NvRegPowerCap = 0x268,
 300 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 301 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 302 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 303         NvRegPowerState = 0x26c,
 304 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 305 #define NVREG_POWERSTATE_VALID          0x0100
 306 #define NVREG_POWERSTATE_MASK           0x0003
 307 #define NVREG_POWERSTATE_D0             0x0000
 308 #define NVREG_POWERSTATE_D1             0x0001
 309 #define NVREG_POWERSTATE_D2             0x0002
 310 #define NVREG_POWERSTATE_D3             0x0003
 311         NvRegMgmtUnitControl = 0x278,
 312 #define NVREG_MGMTUNITCONTROL_INUSE     0x20000
 313         NvRegTxCnt = 0x280,
 314         NvRegTxZeroReXmt = 0x284,
 315         NvRegTxOneReXmt = 0x288,
 316         NvRegTxManyReXmt = 0x28c,
 317         NvRegTxLateCol = 0x290,
 318         NvRegTxUnderflow = 0x294,
 319         NvRegTxLossCarrier = 0x298,
 320         NvRegTxExcessDef = 0x29c,
 321         NvRegTxRetryErr = 0x2a0,
 322         NvRegRxFrameErr = 0x2a4,
 323         NvRegRxExtraByte = 0x2a8,
 324         NvRegRxLateCol = 0x2ac,
 325         NvRegRxRunt = 0x2b0,
 326         NvRegRxFrameTooLong = 0x2b4,
 327         NvRegRxOverflow = 0x2b8,
 328         NvRegRxFCSErr = 0x2bc,
 329         NvRegRxFrameAlignErr = 0x2c0,
 330         NvRegRxLenErr = 0x2c4,
 331         NvRegRxUnicast = 0x2c8,
 332         NvRegRxMulticast = 0x2cc,
 333         NvRegRxBroadcast = 0x2d0,
 334         NvRegTxDef = 0x2d4,
 335         NvRegTxFrame = 0x2d8,
 336         NvRegRxCnt = 0x2dc,
 337         NvRegTxPause = 0x2e0,
 338         NvRegRxPause = 0x2e4,
 339         NvRegRxDropFrame = 0x2e8,
 340         NvRegVlanControl = 0x300,
 341 #define NVREG_VLANCONTROL_ENABLE        0x2000
 342         NvRegMSIXMap0 = 0x3e0,
 343         NvRegMSIXMap1 = 0x3e4,
 344         NvRegMSIXIrqStatus = 0x3f0,
 345
 346         NvRegPowerState2 = 0x600,
 347 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F15
 348 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 349 #define NVREG_POWERSTATE2_PHY_RESET             0x0004
 350 };
 351
 352 /* Big endian: should work, but is untested */
 353 struct ring_desc {
 354         __le32 buf;
 355         __le32 flaglen;
 356 };
 357
 358 struct ring_desc_ex {
 359         __le32 bufhigh;
 360         __le32 buflow;
 361         __le32 txvlan;
 362         __le32 flaglen;
 363 };
 364
 365 union ring_type {
 366         struct ring_desc* orig;
 367         struct ring_desc_ex* ex;
 368 };
 369
 370 #define FLAG_MASK_V1 0xffff0000
 371 #define FLAG_MASK_V2 0xffffc000
 372 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 373 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 374
 375 #define NV_TX_LASTPACKET        (1<<16)
 376 #define NV_TX_RETRYERROR        (1<<19)
 377 #define NV_TX_RETRYCOUNT_MASK   (0xF<<20)
 378 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 379 #define NV_TX_DEFERRED          (1<<26)
 380 #define NV_TX_CARRIERLOST       (1<<27)
 381 #define NV_TX_LATECOLLISION     (1<<28)
 382 #define NV_TX_UNDERFLOW         (1<<29)
 383 #define NV_TX_ERROR             (1<<30)
 384 #define NV_TX_VALID             (1<<31)
 385
 386 #define NV_TX2_LASTPACKET       (1<<29)
 387 #define NV_TX2_RETRYERROR       (1<<18)
 388 #define NV_TX2_RETRYCOUNT_MASK  (0xF<<19)
 389 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 390 #define NV_TX2_DEFERRED         (1<<25)
 391 #define NV_TX2_CARRIERLOST      (1<<26)
 392 #define NV_TX2_LATECOLLISION    (1<<27)
 393 #define NV_TX2_UNDERFLOW        (1<<28)
 394 /* error and valid are the same for both */
 395 #define NV_TX2_ERROR            (1<<30)
 396 #define NV_TX2_VALID            (1<<31)
 397 #define NV_TX2_TSO              (1<<28)
 398 #define NV_TX2_TSO_SHIFT        14
 399 #define NV_TX2_TSO_MAX_SHIFT    14
 400 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 401 #define NV_TX2_CHECKSUM_L3      (1<<27)
 402 #define NV_TX2_CHECKSUM_L4      (1<<26)
 403
 404 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 405
 406 #define NV_RX_DESCRIPTORVALID   (1<<16)
 407 #define NV_RX_MISSEDFRAME       (1<<17)
 408 #define NV_RX_SUBSTRACT1        (1<<18)
 409 #define NV_RX_ERROR1            (1<<23)
 410 #define NV_RX_ERROR2            (1<<24)
 411 #define NV_RX_ERROR3            (1<<25)
 412 #define NV_RX_ERROR4            (1<<26)
 413 #define NV_RX_CRCERR            (1<<27)
 414 #define NV_RX_OVERFLOW          (1<<28)
 415 #define NV_RX_FRAMINGERR        (1<<29)
 416 #define NV_RX_ERROR             (1<<30)
 417 #define NV_RX_AVAIL             (1<<31)
 418 #define NV_RX_ERROR_MASK        (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
 419
 420 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 421 #define NV_RX2_CHECKSUM_IP      (0x10000000)
 422 #define NV_RX2_CHECKSUM_IP_TCP  (0x14000000)
 423 #define NV_RX2_CHECKSUM_IP_UDP  (0x18000000)
 424 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 425 #define NV_RX2_SUBSTRACT1       (1<<25)
 426 #define NV_RX2_ERROR1           (1<<18)
 427 #define NV_RX2_ERROR2           (1<<19)
 428 #define NV_RX2_ERROR3           (1<<20)
 429 #define NV_RX2_ERROR4           (1<<21)
 430 #define NV_RX2_CRCERR           (1<<22)
 431 #define NV_RX2_OVERFLOW         (1<<23)
 432 #define NV_RX2_FRAMINGERR       (1<<24)
 433 /* error and avail are the same for both */
 434 #define NV_RX2_ERROR            (1<<30)
 435 #define NV_RX2_AVAIL            (1<<31)
 436 #define NV_RX2_ERROR_MASK       (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
 437
 438 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 439 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 440
 441 /* Miscelaneous hardware related defines: */
 442 #define NV_PCI_REGSZ_VER1       0x270
 443 #define NV_PCI_REGSZ_VER2       0x2d4
 444 #define NV_PCI_REGSZ_VER3       0x604
 445 #define NV_PCI_REGSZ_MAX        0x604
 446
 447 /* various timeout delays: all in usec */
 448 #define NV_TXRX_RESET_DELAY     4
 449 #define NV_TXSTOP_DELAY1        10
 450 #define NV_TXSTOP_DELAY1MAX     500000
 451 #define NV_TXSTOP_DELAY2        100
 452 #define NV_RXSTOP_DELAY1        10
 453 #define NV_RXSTOP_DELAY1MAX     500000
 454 #define NV_RXSTOP_DELAY2        100
 455 #define NV_SETUP5_DELAY         5
 456 #define NV_SETUP5_DELAYMAX      50000
 457 #define NV_POWERUP_DELAY        5
 458 #define NV_POWERUP_DELAYMAX     5000
 459 #define NV_MIIBUSY_DELAY        50
 460 #define NV_MIIPHY_DELAY 10
 461 #define NV_MIIPHY_DELAYMAX      10000
 462 #define NV_MAC_RESET_DELAY      64
 463
 464 #define NV_WAKEUPPATTERNS       5
 465 #define NV_WAKEUPMASKENTRIES    4
 466
 467 /* General driver defaults */
 468 #define NV_WATCHDOG_TIMEO       (5*HZ)
 469
 470 #define RX_RING_DEFAULT         128
 471 #define TX_RING_DEFAULT         256
 472 #define RX_RING_MIN             128
 473 #define TX_RING_MIN             64
 474 #define RING_MAX_DESC_VER_1     1024
 475 #define RING_MAX_DESC_VER_2_3   16384
 476
 477 /* rx/tx mac addr + type + vlan + align + slack*/
 478 #define NV_RX_HEADERS           (64)
 479 /* even more slack. */
 480 #define NV_RX_ALLOC_PAD         (64)
 481
 482 /* maximum mtu size */
 483 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 484 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 485
 486 #define OOM_REFILL      (1+HZ/20)
 487 #define POLL_WAIT       (1+HZ/100)
 488 #define LINK_TIMEOUT    (3*HZ)
 489 #define STATS_INTERVAL  (10*HZ)
 490
 491 /*
 492  * desc_ver values:
 493  * The nic supports three different descriptor types:
 494  * - DESC_VER_1: Original
 495  * - DESC_VER_2: support for jumbo frames.
 496  * - DESC_VER_3: 64-bit format.
 497  */
 498 #define DESC_VER_1      1
 499 #define DESC_VER_2      2
 500 #define DESC_VER_3      3
 501
 502 /* PHY defines */
 503 #define PHY_OUI_MARVELL         0x5043
 504 #define PHY_OUI_CICADA          0x03f1
 505 #define PHY_OUI_VITESSE         0x01c1
 506 #define PHY_OUI_REALTEK         0x0732
 507 #define PHY_OUI_REALTEK2        0x0020
 508 #define PHYID1_OUI_MASK 0x03ff
 509 #define PHYID1_OUI_SHFT 6
 510 #define PHYID2_OUI_MASK 0xfc00
 511 #define PHYID2_OUI_SHFT 10
 512 #define PHYID2_MODEL_MASK               0x03f0
 513 #define PHY_MODEL_REALTEK_8211          0x0110
 514 #define PHY_REV_MASK                    0x0001
 515 #define PHY_REV_REALTEK_8211B           0x0000
 516 #define PHY_REV_REALTEK_8211C           0x0001
 517 #define PHY_MODEL_REALTEK_8201          0x0200
 518 #define PHY_MODEL_MARVELL_E3016         0x0220
 519 #define PHY_MARVELL_E3016_INITMASK      0x0300
 520 #define PHY_CICADA_INIT1        0x0f000
 521 #define PHY_CICADA_INIT2        0x0e00
 522 #define PHY_CICADA_INIT3        0x01000
 523 #define PHY_CICADA_INIT4        0x0200
 524 #define PHY_CICADA_INIT5        0x0004
 525 #define PHY_CICADA_INIT6        0x02000
 526 #define PHY_VITESSE_INIT_REG1   0x1f
 527 #define PHY_VITESSE_INIT_REG2   0x10
 528 #define PHY_VITESSE_INIT_REG3   0x11
 529 #define PHY_VITESSE_INIT_REG4   0x12
 530 #define PHY_VITESSE_INIT_MSK1   0xc
 531 #define PHY_VITESSE_INIT_MSK2   0x0180
 532 #define PHY_VITESSE_INIT1       0x52b5
 533 #define PHY_VITESSE_INIT2       0xaf8a
 534 #define PHY_VITESSE_INIT3       0x8
 535 #define PHY_VITESSE_INIT4       0x8f8a
 536 #define PHY_VITESSE_INIT5       0xaf86
 537 #define PHY_VITESSE_INIT6       0x8f86
 538 #define PHY_VITESSE_INIT7       0xaf82
 539 #define PHY_VITESSE_INIT8       0x0100
 540 #define PHY_VITESSE_INIT9       0x8f82
 541 #define PHY_VITESSE_INIT10      0x0
 542 #define PHY_REALTEK_INIT_REG1   0x1f
 543 #define PHY_REALTEK_INIT_REG2   0x19
 544 #define PHY_REALTEK_INIT_REG3   0x13
 545 #define PHY_REALTEK_INIT_REG4   0x14
 546 #define PHY_REALTEK_INIT_REG5   0x18
 547 #define PHY_REALTEK_INIT_REG6   0x11
 548 #define PHY_REALTEK_INIT_REG7   0x01
 549 #define PHY_REALTEK_INIT1       0x0000
 550 #define PHY_REALTEK_INIT2       0x8e00
 551 #define PHY_REALTEK_INIT3       0x0001
 552 #define PHY_REALTEK_INIT4       0xad17
 553 #define PHY_REALTEK_INIT5       0xfb54
 554 #define PHY_REALTEK_INIT6       0xf5c7
 555 #define PHY_REALTEK_INIT7       0x1000
 556 #define PHY_REALTEK_INIT8       0x0003
 557 #define PHY_REALTEK_INIT9       0x0008
 558 #define PHY_REALTEK_INIT10      0x0005
 559 #define PHY_REALTEK_INIT11      0x0200
 560 #define PHY_REALTEK_INIT_MSK1   0x0003
 561
 562 #define PHY_GIGABIT     0x0100
 563
 564 #define PHY_TIMEOUT     0x1
 565 #define PHY_ERROR       0x2
 566
 567 #define PHY_100 0x1
 568 #define PHY_1000        0x2
 569 #define PHY_HALF        0x100
 570
 571 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 572 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 573 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 574 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 575 #define NV_PAUSEFRAME_RX_REQ     0x0010
 576 #define NV_PAUSEFRAME_TX_REQ     0x0020
 577 #define NV_PAUSEFRAME_AUTONEG    0x0040
 578
 579 /* MSI/MSI-X defines */
 580 #define NV_MSI_X_MAX_VECTORS  8
 581 #define NV_MSI_X_VECTORS_MASK 0x000f
 582 #define NV_MSI_CAPABLE        0x0010
 583 #define NV_MSI_X_CAPABLE      0x0020
 584 #define NV_MSI_ENABLED        0x0040
 585 #define NV_MSI_X_ENABLED      0x0080
 586
 587 #define NV_MSI_X_VECTOR_ALL   0x0
 588 #define NV_MSI_X_VECTOR_RX    0x0
 589 #define NV_MSI_X_VECTOR_TX    0x1
 590 #define NV_MSI_X_VECTOR_OTHER 0x2
 591
 592 #define NV_MSI_PRIV_OFFSET 0x68
 593 #define NV_MSI_PRIV_VALUE  0xffffffff
 594
 595 #define NV_RESTART_TX         0x1
 596 #define NV_RESTART_RX         0x2
 597
 598 #define NV_TX_LIMIT_COUNT     16
 599
 600 /* statistics */
 601 struct nv_ethtool_str {
 602         char name[ETH_GSTRING_LEN];
 603 };
 604
 605 static const struct nv_ethtool_str nv_estats_str[] = {
 606         { "tx_bytes" },
 607         { "tx_zero_rexmt" },
 608         { "tx_one_rexmt" },
 609         { "tx_many_rexmt" },
 610         { "tx_late_collision" },
 611         { "tx_fifo_errors" },
 612         { "tx_carrier_errors" },
 613         { "tx_excess_deferral" },
 614         { "tx_retry_error" },
 615         { "rx_frame_error" },
 616         { "rx_extra_byte" },
 617         { "rx_late_collision" },
 618         { "rx_runt" },
 619         { "rx_frame_too_long" },
 620         { "rx_over_errors" },
 621         { "rx_crc_errors" },
 622         { "rx_frame_align_error" },
 623         { "rx_length_error" },
 624         { "rx_unicast" },
 625         { "rx_multicast" },
 626         { "rx_broadcast" },
 627         { "rx_packets" },
 628         { "rx_errors_total" },
 629         { "tx_errors_total" },
 630
 631         /* version 2 stats */
 632         { "tx_deferral" },
 633         { "tx_packets" },
 634         { "rx_bytes" },
 635         { "tx_pause" },
 636         { "rx_pause" },
 637         { "rx_drop_frame" },
 638
 639         /* version 3 stats */
 640         { "tx_unicast" },
 641         { "tx_multicast" },
 642         { "tx_broadcast" }
 643 };
 644
 645 struct nv_ethtool_stats {
 646         u64 tx_bytes;
 647         u64 tx_zero_rexmt;
 648         u64 tx_one_rexmt;
 649         u64 tx_many_rexmt;
 650         u64 tx_late_collision;
 651         u64 tx_fifo_errors;
 652         u64 tx_carrier_errors;
 653         u64 tx_excess_deferral;
 654         u64 tx_retry_error;
 655         u64 rx_frame_error;
 656         u64 rx_extra_byte;
 657         u64 rx_late_collision;
 658         u64 rx_runt;
 659         u64 rx_frame_too_long;
 660         u64 rx_over_errors;
 661         u64 rx_crc_errors;
 662         u64 rx_frame_align_error;
 663         u64 rx_length_error;
 664         u64 rx_unicast;
 665         u64 rx_multicast;
 666         u64 rx_broadcast;
 667         u64 rx_packets;
 668         u64 rx_errors_total;
 669         u64 tx_errors_total;
 670
 671         /* version 2 stats */
 672         u64 tx_deferral;
 673         u64 tx_packets;
 674         u64 rx_bytes;
 675         u64 tx_pause;
 676         u64 rx_pause;
 677         u64 rx_drop_frame;
 678
 679         /* version 3 stats */
 680         u64 tx_unicast;
 681         u64 tx_multicast;
 682         u64 tx_broadcast;
 683 };
 684
 685 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
 686 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
 687 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
 688
 689 /* diagnostics */
 690 #define NV_TEST_COUNT_BASE 3
 691 #define NV_TEST_COUNT_EXTENDED 4
 692
 693 static const struct nv_ethtool_str nv_etests_str[] = {
 694         { "link      (online/offline)" },
 695         { "register  (offline)       " },
 696         { "interrupt (offline)       " },
 697         { "loopback  (offline)       " }
 698 };
 699
 700 struct register_test {
 701         __u32 reg;
 702         __u32 mask;
 703 };
 704
 705 static const struct register_test nv_registers_test[] = {
 706         { NvRegUnknownSetupReg6, 0x01 },
 707         { NvRegMisc1, 0x03c },
 708         { NvRegOffloadConfig, 0x03ff },
 709         { NvRegMulticastAddrA, 0xffffffff },
 710         { NvRegTxWatermark, 0x0ff },
 711         { NvRegWakeUpFlags, 0x07777 },
 712         { 0,0 }
 713 };
 714
 715 struct nv_skb_map {
 716         struct sk_buff *skb;
 717         dma_addr_t dma;
 718         unsigned int dma_len;
 719         struct ring_desc_ex *first_tx_desc;
 720         struct nv_skb_map *next_tx_ctx;
 721 };
 722
 723 /*
 724  * SMP locking:
 725  * All hardware access under netdev_priv(dev)->lock, except the performance
 726  * critical parts:
 727  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 728  *      by the arch code for interrupts.
 729  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 730  *      needs netdev_priv(dev)->lock :-(
 731  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 732  */
 733
 734 /* in dev: base, irq */
 735 struct fe_priv {
 736         spinlock_t lock;
 737
 738         struct net_device *dev;
 739         struct napi_struct napi;
 740
 741         /* General data:
 742          * Locking: spin_lock(&np->lock); */
 743         struct nv_ethtool_stats estats;
 744         int in_shutdown;
 745         u32 linkspeed;
 746         int duplex;
 747         int autoneg;
 748         int fixed_mode;
 749         int phyaddr;
 750         int wolenabled;
 751         unsigned int phy_oui;
 752         unsigned int phy_model;
 753         unsigned int phy_rev;
 754         u16 gigabit;
 755         int intr_test;
 756         int recover_error;
 757
 758         /* General data: RO fields */
 759         dma_addr_t ring_addr;
 760         struct pci_dev *pci_dev;
 761         u32 orig_mac[2];
 762         u32 irqmask;
 763         u32 desc_ver;
 764         u32 txrxctl_bits;
 765         u32 vlanctl_bits;
 766         u32 driver_data;
 767         u32 device_id;
 768         u32 register_size;
 769         int rx_csum;
 770         u32 mac_in_use;
 771         int mgmt_version;
 772         int mgmt_sema;
 773
 774         void __iomem *base;
 775
 776         /* rx specific fields.
 777          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 778          */
 779         union ring_type get_rx, put_rx, first_rx, last_rx;
 780         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
 781         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
 782         struct nv_skb_map *rx_skb;
 783
 784         union ring_type rx_ring;
 785         unsigned int rx_buf_sz;
 786         unsigned int pkt_limit;
 787         struct timer_list oom_kick;
 788         struct timer_list nic_poll;
 789         struct timer_list stats_poll;
 790         u32 nic_poll_irq;
 791         int rx_ring_size;
 792
 793         /* media detection workaround.
 794          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 795          */
 796         int need_linktimer;
 797         unsigned long link_timeout;
 798         /*
 799          * tx specific fields.
 800          */
 801         union ring_type get_tx, put_tx, first_tx, last_tx;
 802         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
 803         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
 804         struct nv_skb_map *tx_skb;
 805
 806         union ring_type tx_ring;
 807         u32 tx_flags;
 808         int tx_ring_size;
 809         int tx_limit;
 810         u32 tx_pkts_in_progress;
 811         struct nv_skb_map *tx_change_owner;
 812         struct nv_skb_map *tx_end_flip;
 813         int tx_stop;
 814
 815         /* vlan fields */
 816         struct vlan_group *vlangrp;
 817
 818         /* msi/msi-x fields */
 819         u32 msi_flags;
 820         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 821
 822         /* flow control */
 823         u32 pause_flags;
 824
 825         /* power saved state */
 826         u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
 827
 828         /* for different msi-x irq type */
 829         char name_rx[IFNAMSIZ + 3];       /* -rx    */
 830         char name_tx[IFNAMSIZ + 3];       /* -tx    */
 831         char name_other[IFNAMSIZ + 6];    /* -other */
 832 };
 833
 834 /*
 835  * Maximum number of loops until we assume that a bit in the irq mask
 836  * is stuck. Overridable with module param.
 837  */
 838 static int max_interrupt_work = 15;
 839
 840 /*
 841  * Optimization can be either throuput mode or cpu mode
 842  *
 843  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 844  * CPU Mode: Interrupts are controlled by a timer.
 845  */
 846 enum {
 847         NV_OPTIMIZATION_MODE_THROUGHPUT,
 848         NV_OPTIMIZATION_MODE_CPU
 849 };
 850 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
 851
 852 /*
 853  * Poll interval for timer irq
 854  *
 855  * This interval determines how frequent an interrupt is generated.
 856  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 857  * Min = 0, and Max = 65535
 858  */
 859 static int poll_interval = -1;
 860
 861 /*
 862  * MSI interrupts
 863  */
 864 enum {
 865         NV_MSI_INT_DISABLED,
 866         NV_MSI_INT_ENABLED
 867 };
 868 static int msi = NV_MSI_INT_ENABLED;
 869
 870 /*
 871  * MSIX interrupts
 872  */
 873 enum {
 874         NV_MSIX_INT_DISABLED,
 875         NV_MSIX_INT_ENABLED
 876 };
 877 static int msix = NV_MSIX_INT_ENABLED;
 878
 879 /*
 880  * DMA 64bit
 881  */
 882 enum {
 883         NV_DMA_64BIT_DISABLED,
 884         NV_DMA_64BIT_ENABLED
 885 };
 886 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 887
 888 /*
 889  * Crossover Detection
 890  * Realtek 8201 phy + some OEM boards do not work properly.
 891  */
 892 enum {
 893         NV_CROSSOVER_DETECTION_DISABLED,
 894         NV_CROSSOVER_DETECTION_ENABLED
 895 };
 896 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
 897
 898 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 899 {
 900         return netdev_priv(dev);
 901 }
 902
 903 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 904 {
 905         return ((struct fe_priv *)netdev_priv(dev))->base;
 906 }
 907
 908 static inline void pci_push(u8 __iomem *base)
 909 {
 910         /* force out pending posted writes */
 911         readl(base);
 912 }
 913
 914 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 915 {
 916         return le32_to_cpu(prd->flaglen)
 917                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 918 }
 919
 920 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 921 {
 922         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
 923 }
 924
 925 static bool nv_optimized(struct fe_priv *np)
 926 {
 927         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 928                 return false;
 929         return true;
 930 }
 931
 932 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 933                                 int delay, int delaymax, const char *msg)
 934 {
 935         u8 __iomem *base = get_hwbase(dev);
 936
 937         pci_push(base);
 938         do {
 939                 udelay(delay);
 940                 delaymax -= delay;
 941                 if (delaymax < 0) {
 942                         if (msg)
 943                                 printk("%s", msg);
 944                         return 1;
 945                 }
 946         } while ((readl(base + offset) & mask) != target);
 947         return 0;
 948 }
 949
 950 #define NV_SETUP_RX_RING 0x01
 951 #define NV_SETUP_TX_RING 0x02
 952
 953 static inline u32 dma_low(dma_addr_t addr)
 954 {
 955         return addr;
 956 }
 957
 958 static inline u32 dma_high(dma_addr_t addr)
 959 {
 960         return addr>>31>>1;     /* 0 if 32bit, shift down by 32 if 64bit */
 961 }
 962
 963 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
 964 {
 965         struct fe_priv *np = get_nvpriv(dev);
 966         u8 __iomem *base = get_hwbase(dev);
 967
 968         if (!nv_optimized(np)) {
 969                 if (rxtx_flags & NV_SETUP_RX_RING) {
 970                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
 971                 }
 972                 if (rxtx_flags & NV_SETUP_TX_RING) {
 973                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
 974                 }
 975         } else {
 976                 if (rxtx_flags & NV_SETUP_RX_RING) {
 977                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
 978                         writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
 979                 }
 980                 if (rxtx_flags & NV_SETUP_TX_RING) {
 981                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
 982                         writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
 983                 }
 984         }
 985 }
 986
 987 static void free_rings(struct net_device *dev)
 988 {
 989         struct fe_priv *np = get_nvpriv(dev);
 990
 991         if (!nv_optimized(np)) {
 992                 if (np->rx_ring.orig)
 993                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
 994                                             np->rx_ring.orig, np->ring_addr);
 995         } else {
 996                 if (np->rx_ring.ex)
 997                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
 998                                             np->rx_ring.ex, np->ring_addr);
 999         }
1000         if (np->rx_skb)
1001                 kfree(np->rx_skb);
1002         if (np->tx_skb)
1003                 kfree(np->tx_skb);
1004 }
1005
1006 static int using_multi_irqs(struct net_device *dev)
1007 {
1008         struct fe_priv *np = get_nvpriv(dev);
1009
1010         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1011             ((np->msi_flags & NV_MSI_X_ENABLED) &&
1012              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1013                 return 0;
1014         else
1015                 return 1;
1016 }
1017
1018 static void nv_enable_irq(struct net_device *dev)
1019 {
1020         struct fe_priv *np = get_nvpriv(dev);
1021
1022         if (!using_multi_irqs(dev)) {
1023                 if (np->msi_flags & NV_MSI_X_ENABLED)
1024                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1025                 else
1026                         enable_irq(np->pci_dev->irq);
1027         } else {
1028                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1029                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1030                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1031         }
1032 }
1033
1034 static void nv_disable_irq(struct net_device *dev)
1035 {
1036         struct fe_priv *np = get_nvpriv(dev);
1037
1038         if (!using_multi_irqs(dev)) {
1039                 if (np->msi_flags & NV_MSI_X_ENABLED)
1040                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1041                 else
1042                         disable_irq(np->pci_dev->irq);
1043         } else {
1044                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1045                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1046                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1047         }
1048 }
1049
1050 /* In MSIX mode, a write to irqmask behaves as XOR */
1051 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1052 {
1053         u8 __iomem *base = get_hwbase(dev);
1054
1055         writel(mask, base + NvRegIrqMask);
1056 }
1057
1058 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1059 {
1060         struct fe_priv *np = get_nvpriv(dev);
1061         u8 __iomem *base = get_hwbase(dev);
1062
1063         if (np->msi_flags & NV_MSI_X_ENABLED) {
1064                 writel(mask, base + NvRegIrqMask);
1065         } else {
1066                 if (np->msi_flags & NV_MSI_ENABLED)
1067                         writel(0, base + NvRegMSIIrqMask);
1068                 writel(0, base + NvRegIrqMask);
1069         }
1070 }
1071
1072 #define MII_READ        (-1)
1073 /* mii_rw: read/write a register on the PHY.
1074  *
1075  * Caller must guarantee serialization
1076  */
1077 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1078 {
1079         u8 __iomem *base = get_hwbase(dev);
1080         u32 reg;
1081         int retval;
1082
1083         writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1084
1085         reg = readl(base + NvRegMIIControl);
1086         if (reg & NVREG_MIICTL_INUSE) {
1087                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1088                 udelay(NV_MIIBUSY_DELAY);
1089         }
1090
1091         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1092         if (value != MII_READ) {
1093                 writel(value, base + NvRegMIIData);
1094                 reg |= NVREG_MIICTL_WRITE;
1095         }
1096         writel(reg, base + NvRegMIIControl);
1097
1098         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1099                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1100                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1101                                 dev->name, miireg, addr);
1102                 retval = -1;
1103         } else if (value != MII_READ) {
1104                 /* it was a write operation - fewer failures are detectable */
1105                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1106                                 dev->name, value, miireg, addr);
1107                 retval = 0;
1108         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1109                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1110                                 dev->name, miireg, addr);
1111                 retval = -1;
1112         } else {
1113                 retval = readl(base + NvRegMIIData);
1114                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1115                                 dev->name, miireg, addr, retval);
1116         }
1117
1118         return retval;
1119 }
1120
1121 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1122 {
1123         struct fe_priv *np = netdev_priv(dev);
1124         u32 miicontrol;
1125         unsigned int tries = 0;
1126
1127         miicontrol = BMCR_RESET | bmcr_setup;
1128         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1129                 return -1;
1130         }
1131
1132         /* wait for 500ms */
1133         msleep(500);
1134
1135         /* must wait till reset is deasserted */
1136         while (miicontrol & BMCR_RESET) {
1137                 msleep(10);
1138                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1139                 /* FIXME: 100 tries seem excessive */
1140                 if (tries++ > 100)
1141                         return -1;
1142         }
1143         return 0;
1144 }
1145
1146 static int phy_init(struct net_device *dev)
1147 {
1148         struct fe_priv *np = get_nvpriv(dev);
1149         u8 __iomem *base = get_hwbase(dev);
1150         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1151
1152         /* phy errata for E3016 phy */
1153         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1154                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1155                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1156                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1157                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1158                         return PHY_ERROR;
1159                 }
1160         }
1161         if (np->phy_oui == PHY_OUI_REALTEK) {
1162                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1163                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1164                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1165                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1166                                 return PHY_ERROR;
1167                         }
1168                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1169                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1170                                 return PHY_ERROR;
1171                         }
1172                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1173                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1174                                 return PHY_ERROR;
1175                         }
1176                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1177                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1178                                 return PHY_ERROR;
1179                         }
1180                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1181                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1182                                 return PHY_ERROR;
1183                         }
1184                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1185                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1186                                 return PHY_ERROR;
1187                         }
1188                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1189                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1190                                 return PHY_ERROR;
1191                         }
1192                 }
1193                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1194                     np->phy_rev == PHY_REV_REALTEK_8211C) {
1195                         u32 powerstate = readl(base + NvRegPowerState2);
1196
1197                         /* need to perform hw phy reset */
1198                         powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1199                         writel(powerstate, base + NvRegPowerState2);
1200                         msleep(25);
1201
1202                         powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1203                         writel(powerstate, base + NvRegPowerState2);
1204                         msleep(25);
1205
1206                         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1207                         reg |= PHY_REALTEK_INIT9;
1208                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) {
1209                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1210                                 return PHY_ERROR;
1211                         }
1212                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) {
1213                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1214                                 return PHY_ERROR;
1215                         }
1216                         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1217                         if (!(reg & PHY_REALTEK_INIT11)) {
1218                                 reg |= PHY_REALTEK_INIT11;
1219                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) {
1220                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1221                                         return PHY_ERROR;
1222                                 }
1223                         }
1224                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1225                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1226                                 return PHY_ERROR;
1227                         }
1228                 }
1229                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1230                         if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
1231                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1232                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1233                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1234                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1235                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1236                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1237                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1238                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1239                                 phy_reserved |= PHY_REALTEK_INIT7;
1240                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1241                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1242                                         return PHY_ERROR;
1243                                 }
1244                         }
1245                 }
1246         }
1247
1248         /* set advertise register */
1249         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1250         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1251         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1252                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1253                 return PHY_ERROR;
1254         }
1255
1256         /* get phy interface type */
1257         phyinterface = readl(base + NvRegPhyInterface);
1258
1259         /* see if gigabit phy */
1260         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1261         if (mii_status & PHY_GIGABIT) {
1262                 np->gigabit = PHY_GIGABIT;
1263                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1264                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1265                 if (phyinterface & PHY_RGMII)
1266                         mii_control_1000 |= ADVERTISE_1000FULL;
1267                 else
1268                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1269
1270                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1271                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1272                         return PHY_ERROR;
1273                 }
1274         }
1275         else
1276                 np->gigabit = 0;
1277
1278         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1279         mii_control |= BMCR_ANENABLE;
1280
1281         if (np->phy_oui == PHY_OUI_REALTEK &&
1282             np->phy_model == PHY_MODEL_REALTEK_8211 &&
1283             np->phy_rev == PHY_REV_REALTEK_8211C) {
1284                 /* start autoneg since we already performed hw reset above */
1285                 mii_control |= BMCR_ANRESTART;
1286                 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1287                         printk(KERN_INFO "%s: phy init failed\n", pci_name(np->pci_dev));
1288                         return PHY_ERROR;
1289                 }
1290         } else {
1291                 /* reset the phy
1292                  * (certain phys need bmcr to be setup with reset)
1293                  */
1294                 if (phy_reset(dev, mii_control)) {
1295                         printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1296                         return PHY_ERROR;
1297                 }
1298         }
1299
1300         /* phy vendor specific configuration */
1301         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1302                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1303                 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1304                 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1305                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1306                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1307                         return PHY_ERROR;
1308                 }
1309                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1310                 phy_reserved |= PHY_CICADA_INIT5;
1311                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1312                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1313                         return PHY_ERROR;
1314                 }
1315         }
1316         if (np->phy_oui == PHY_OUI_CICADA) {
1317                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1318                 phy_reserved |= PHY_CICADA_INIT6;
1319                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1320                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1321                         return PHY_ERROR;
1322                 }
1323         }
1324         if (np->phy_oui == PHY_OUI_VITESSE) {
1325                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1326                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1327                         return PHY_ERROR;
1328                 }
1329                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1330                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1331                         return PHY_ERROR;
1332                 }
1333                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1334                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1335                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1336                         return PHY_ERROR;
1337                 }
1338                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1339                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1340                 phy_reserved |= PHY_VITESSE_INIT3;
1341                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1342                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1343                         return PHY_ERROR;
1344                 }
1345                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1346                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1347                         return PHY_ERROR;
1348                 }
1349                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1350                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1351                         return PHY_ERROR;
1352                 }
1353                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1354                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1355                 phy_reserved |= PHY_VITESSE_INIT3;
1356                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1357                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1358                         return PHY_ERROR;
1359                 }
1360                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1361                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1362                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1363                         return PHY_ERROR;
1364                 }
1365                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1366                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1367                         return PHY_ERROR;
1368                 }
1369                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1370                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1371                         return PHY_ERROR;
1372                 }
1373                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1374                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1375                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1376                         return PHY_ERROR;
1377                 }
1378                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1379                 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1380                 phy_reserved |= PHY_VITESSE_INIT8;
1381                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1382                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1383                         return PHY_ERROR;
1384                 }
1385                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1386                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1387                         return PHY_ERROR;
1388                 }
1389                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1390                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1391                         return PHY_ERROR;
1392                 }
1393         }
1394         if (np->phy_oui == PHY_OUI_REALTEK) {
1395                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1396                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1397                         /* reset could have cleared these out, set them back */
1398                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1399                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1400                                 return PHY_ERROR;
1401                         }
1402                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1403                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1404                                 return PHY_ERROR;
1405                         }
1406                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1407                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1408                                 return PHY_ERROR;
1409                         }
1410                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1411                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1412                                 return PHY_ERROR;
1413                         }
1414                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1415                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1416                                 return PHY_ERROR;
1417                         }
1418                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1419                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1420                                 return PHY_ERROR;
1421                         }
1422                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1423                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1424                                 return PHY_ERROR;
1425                         }
1426                 }
1427                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1428                         if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
1429                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1430                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1431                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1432                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1433                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1434                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1435                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1436                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1437                                 phy_reserved |= PHY_REALTEK_INIT7;
1438                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1439                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1440                                         return PHY_ERROR;
1441                                 }
1442                         }
1443                         if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1444                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1445                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1446                                         return PHY_ERROR;
1447                                 }
1448                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1449                                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1450                                 phy_reserved |= PHY_REALTEK_INIT3;
1451                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
1452                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1453                                         return PHY_ERROR;
1454                                 }
1455                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1456                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1457                                         return PHY_ERROR;
1458                                 }
1459                         }
1460                 }
1461         }
1462
1463         /* some phys clear out pause advertisment on reset, set it back */
1464         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1465
1466         /* restart auto negotiation, power down phy */
1467         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1468         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE | BMCR_PDOWN);
1469         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1470                 return PHY_ERROR;
1471         }
1472
1473         return 0;
1474 }
1475
1476 static void nv_start_rx(struct net_device *dev)
1477 {
1478         struct fe_priv *np = netdev_priv(dev);
1479         u8 __iomem *base = get_hwbase(dev);
1480         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1481
1482         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1483         /* Already running? Stop it. */
1484         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1485                 rx_ctrl &= ~NVREG_RCVCTL_START;
1486                 writel(rx_ctrl, base + NvRegReceiverControl);
1487                 pci_push(base);
1488         }
1489         writel(np->linkspeed, base + NvRegLinkSpeed);
1490         pci_push(base);
1491         rx_ctrl |= NVREG_RCVCTL_START;
1492         if (np->mac_in_use)
1493                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1494         writel(rx_ctrl, base + NvRegReceiverControl);
1495         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1496                                 dev->name, np->duplex, np->linkspeed);
1497         pci_push(base);
1498 }
1499
1500 static void nv_stop_rx(struct net_device *dev)
1501 {
1502         struct fe_priv *np = netdev_priv(dev);
1503         u8 __iomem *base = get_hwbase(dev);
1504         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1505
1506         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1507         if (!np->mac_in_use)
1508                 rx_ctrl &= ~NVREG_RCVCTL_START;
1509         else
1510                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1511         writel(rx_ctrl, base + NvRegReceiverControl);
1512         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1513                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1514                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1515
1516         udelay(NV_RXSTOP_DELAY2);
1517         if (!np->mac_in_use)
1518                 writel(0, base + NvRegLinkSpeed);
1519 }
1520
1521 static void nv_start_tx(struct net_device *dev)
1522 {
1523         struct fe_priv *np = netdev_priv(dev);
1524         u8 __iomem *base = get_hwbase(dev);
1525         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1526
1527         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1528         tx_ctrl |= NVREG_XMITCTL_START;
1529         if (np->mac_in_use)
1530                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1531         writel(tx_ctrl, base + NvRegTransmitterControl);
1532         pci_push(base);
1533 }
1534
1535 static void nv_stop_tx(struct net_device *dev)
1536 {
1537         struct fe_priv *np = netdev_priv(dev);
1538         u8 __iomem *base = get_hwbase(dev);
1539         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1540
1541         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1542         if (!np->mac_in_use)
1543                 tx_ctrl &= ~NVREG_XMITCTL_START;
1544         else
1545                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1546         writel(tx_ctrl, base + NvRegTransmitterControl);
1547         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1548                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1549                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1550
1551         udelay(NV_TXSTOP_DELAY2);
1552         if (!np->mac_in_use)
1553                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1554                        base + NvRegTransmitPoll);
1555 }
1556
1557 static void nv_start_rxtx(struct net_device *dev)
1558 {
1559         nv_start_rx(dev);
1560         nv_start_tx(dev);
1561 }
1562
1563 static void nv_stop_rxtx(struct net_device *dev)
1564 {
1565         nv_stop_rx(dev);
1566         nv_stop_tx(dev);
1567 }
1568
1569 static void nv_txrx_reset(struct net_device *dev)
1570 {
1571         struct fe_priv *np = netdev_priv(dev);
1572         u8 __iomem *base = get_hwbase(dev);
1573
1574         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1575         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1576         pci_push(base);
1577         udelay(NV_TXRX_RESET_DELAY);
1578         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1579         pci_push(base);
1580 }
1581
1582 static void nv_mac_reset(struct net_device *dev)
1583 {
1584         struct fe_priv *np = netdev_priv(dev);
1585         u8 __iomem *base = get_hwbase(dev);
1586         u32 temp1, temp2, temp3;
1587
1588         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1589
1590         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1591         pci_push(base);
1592
1593         /* save registers since they will be cleared on reset */
1594         temp1 = readl(base + NvRegMacAddrA);
1595         temp2 = readl(base + NvRegMacAddrB);
1596         temp3 = readl(base + NvRegTransmitPoll);
1597
1598         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1599         pci_push(base);
1600         udelay(NV_MAC_RESET_DELAY);
1601         writel(0, base + NvRegMacReset);
1602         pci_push(base);
1603         udelay(NV_MAC_RESET_DELAY);
1604
1605         /* restore saved registers */
1606         writel(temp1, base + NvRegMacAddrA);
1607         writel(temp2, base + NvRegMacAddrB);
1608         writel(temp3, base + NvRegTransmitPoll);
1609
1610         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1611         pci_push(base);
1612 }
1613
1614 static void nv_get_hw_stats(struct net_device *dev)
1615 {
1616         struct fe_priv *np = netdev_priv(dev);
1617         u8 __iomem *base = get_hwbase(dev);
1618
1619         np->estats.tx_bytes += readl(base + NvRegTxCnt);
1620         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1621         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1622         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1623         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1624         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1625         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1626         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1627         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1628         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1629         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1630         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1631         np->estats.rx_runt += readl(base + NvRegRxRunt);
1632         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1633         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1634         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1635         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1636         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1637         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1638         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1639         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1640         np->estats.rx_packets =
1641                 np->estats.rx_unicast +
1642                 np->estats.rx_multicast +
1643                 np->estats.rx_broadcast;
1644         np->estats.rx_errors_total =
1645                 np->estats.rx_crc_errors +
1646                 np->estats.rx_over_errors +
1647                 np->estats.rx_frame_error +
1648                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1649                 np->estats.rx_late_collision +
1650                 np->estats.rx_runt +
1651                 np->estats.rx_frame_too_long;
1652         np->estats.tx_errors_total =
1653                 np->estats.tx_late_collision +
1654                 np->estats.tx_fifo_errors +
1655                 np->estats.tx_carrier_errors +
1656                 np->estats.tx_excess_deferral +
1657                 np->estats.tx_retry_error;
1658
1659         if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1660                 np->estats.tx_deferral += readl(base + NvRegTxDef);
1661                 np->estats.tx_packets += readl(base + NvRegTxFrame);
1662                 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1663                 np->estats.tx_pause += readl(base + NvRegTxPause);
1664                 np->estats.rx_pause += readl(base + NvRegRxPause);
1665                 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1666         }
1667
1668         if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1669                 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1670                 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1671                 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1672         }
1673 }
1674
1675 /*
1676  * nv_get_stats: dev->get_stats function
1677  * Get latest stats value from the nic.
1678  * Called with read_lock(&dev_base_lock) held for read -
1679  * only synchronized against unregister_netdevice.
1680  */
1681 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1682 {
1683         struct fe_priv *np = netdev_priv(dev);
1684
1685         /* If the nic supports hw counters then retrieve latest values */
1686         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
1687                 nv_get_hw_stats(dev);
1688
1689                 /* copy to net_device stats */
1690                 dev->stats.tx_bytes = np->estats.tx_bytes;
1691                 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1692                 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1693                 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1694                 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1695                 dev->stats.rx_errors = np->estats.rx_errors_total;
1696                 dev->stats.tx_errors = np->estats.tx_errors_total;
1697         }
1698
1699         return &dev->stats;
1700 }
1701
1702 /*
1703  * nv_alloc_rx: fill rx ring entries.
1704  * Return 1 if the allocations for the skbs failed and the
1705  * rx engine is without Available descriptors
1706  */
1707 static int nv_alloc_rx(struct net_device *dev)
1708 {
1709         struct fe_priv *np = netdev_priv(dev);
1710         struct ring_desc* less_rx;
1711
1712         less_rx = np->get_rx.orig;
1713         if (less_rx-- == np->first_rx.orig)
1714                 less_rx = np->last_rx.orig;
1715
1716         while (np->put_rx.orig != less_rx) {
1717                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1718                 if (skb) {
1719                         np->put_rx_ctx->skb = skb;
1720                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1721                                                              skb->data,
1722                                                              skb_tailroom(skb),
1723                                                              PCI_DMA_FROMDEVICE);
1724                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1725                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1726                         wmb();
1727                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1728                         if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1729                                 np->put_rx.orig = np->first_rx.orig;
1730                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1731                                 np->put_rx_ctx = np->first_rx_ctx;
1732                 } else {
1733                         return 1;
1734                 }
1735         }
1736         return 0;
1737 }
1738
1739 static int nv_alloc_rx_optimized(struct net_device *dev)
1740 {
1741         struct fe_priv *np = netdev_priv(dev);
1742         struct ring_desc_ex* less_rx;
1743
1744         less_rx = np->get_rx.ex;
1745         if (less_rx-- == np->first_rx.ex)
1746                 less_rx = np->last_rx.ex;
1747
1748         while (np->put_rx.ex != less_rx) {
1749                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1750                 if (skb) {
1751                         np->put_rx_ctx->skb = skb;
1752                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1753                                                              skb->data,
1754                                                              skb_tailroom(skb),
1755                                                              PCI_DMA_FROMDEVICE);
1756                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1757                         np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1758                         np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1759                         wmb();
1760                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1761                         if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1762                                 np->put_rx.ex = np->first_rx.ex;
1763                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1764                                 np->put_rx_ctx = np->first_rx_ctx;
1765                 } else {
1766                         return 1;
1767                 }
1768         }
1769         return 0;
1770 }
1771
1772 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1773 #ifdef CONFIG_FORCEDETH_NAPI
1774 static void nv_do_rx_refill(unsigned long data)
1775 {
1776         struct net_device *dev = (struct net_device *) data;
1777         struct fe_priv *np = netdev_priv(dev);
1778
1779         /* Just reschedule NAPI rx processing */
1780         napi_schedule(&np->napi);
1781 }
1782 #else
1783 static void nv_do_rx_refill(unsigned long data)
1784 {
1785         struct net_device *dev = (struct net_device *) data;
1786         struct fe_priv *np = netdev_priv(dev);
1787         int retcode;
1788
1789         if (!using_multi_irqs(dev)) {
1790                 if (np->msi_flags & NV_MSI_X_ENABLED)
1791                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1792                 else
1793                         disable_irq(np->pci_dev->irq);
1794         } else {
1795                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1796         }
1797         if (!nv_optimized(np))
1798                 retcode = nv_alloc_rx(dev);
1799         else
1800                 retcode = nv_alloc_rx_optimized(dev);
1801         if (retcode) {
1802                 spin_lock_irq(&np->lock);
1803                 if (!np->in_shutdown)
1804                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1805                 spin_unlock_irq(&np->lock);
1806         }
1807         if (!using_multi_irqs(dev)) {
1808                 if (np->msi_flags & NV_MSI_X_ENABLED)
1809                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1810                 else
1811                         enable_irq(np->pci_dev->irq);
1812         } else {
1813                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1814         }
1815 }
1816 #endif
1817
1818 static void nv_init_rx(struct net_device *dev)
1819 {
1820         struct fe_priv *np = netdev_priv(dev);
1821         int i;
1822
1823         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1824
1825         if (!nv_optimized(np))
1826                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1827         else
1828                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1829         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1830         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1831
1832         for (i = 0; i < np->rx_ring_size; i++) {
1833                 if (!nv_optimized(np)) {
1834                         np->rx_ring.orig[i].flaglen = 0;
1835                         np->rx_ring.orig[i].buf = 0;
1836                 } else {
1837                         np->rx_ring.ex[i].flaglen = 0;
1838                         np->rx_ring.ex[i].txvlan = 0;
1839                         np->rx_ring.ex[i].bufhigh = 0;
1840                         np->rx_ring.ex[i].buflow = 0;
1841                 }
1842                 np->rx_skb[i].skb = NULL;
1843                 np->rx_skb[i].dma = 0;
1844         }
1845 }
1846
1847 static void nv_init_tx(struct net_device *dev)
1848 {
1849         struct fe_priv *np = netdev_priv(dev);
1850         int i;
1851
1852         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1853
1854         if (!nv_optimized(np))
1855                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1856         else
1857                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1858         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1859         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1860         np->tx_pkts_in_progress = 0;
1861         np->tx_change_owner = NULL;
1862         np->tx_end_flip = NULL;
1863
1864         for (i = 0; i < np->tx_ring_size; i++) {
1865                 if (!nv_optimized(np)) {
1866                         np->tx_ring.orig[i].flaglen = 0;
1867                         np->tx_ring.orig[i].buf = 0;
1868                 } else {
1869                         np->tx_ring.ex[i].flaglen = 0;
1870                         np->tx_ring.ex[i].txvlan = 0;
1871                         np->tx_ring.ex[i].bufhigh = 0;
1872                         np->tx_ring.ex[i].buflow = 0;
1873                 }
1874                 np->tx_skb[i].skb = NULL;
1875                 np->tx_skb[i].dma = 0;
1876                 np->tx_skb[i].dma_len = 0;
1877                 np->tx_skb[i].first_tx_desc = NULL;
1878                 np->tx_skb[i].next_tx_ctx = NULL;
1879         }
1880 }
1881
1882 static int nv_init_ring(struct net_device *dev)
1883 {
1884         struct fe_priv *np = netdev_priv(dev);
1885
1886         nv_init_tx(dev);
1887         nv_init_rx(dev);
1888
1889         if (!nv_optimized(np))
1890                 return nv_alloc_rx(dev);
1891         else
1892                 return nv_alloc_rx_optimized(dev);
1893 }
1894
1895 static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
1896 {
1897         struct fe_priv *np = netdev_priv(dev);
1898
1899         if (tx_skb->dma) {
1900                 pci_unmap_page(np->pci_dev, tx_skb->dma,
1901                                tx_skb->dma_len,
1902                                PCI_DMA_TODEVICE);
1903                 tx_skb->dma = 0;
1904         }
1905         if (tx_skb->skb) {
1906                 dev_kfree_skb_any(tx_skb->skb);
1907                 tx_skb->skb = NULL;
1908                 return 1;
1909         } else {
1910                 return 0;
1911         }
1912 }
1913
1914 static void nv_drain_tx(struct net_device *dev)
1915 {
1916         struct fe_priv *np = netdev_priv(dev);
1917         unsigned int i;
1918
1919         for (i = 0; i < np->tx_ring_size; i++) {
1920                 if (!nv_optimized(np)) {
1921                         np->tx_ring.orig[i].flaglen = 0;
1922                         np->tx_ring.orig[i].buf = 0;
1923                 } else {
1924                         np->tx_ring.ex[i].flaglen = 0;
1925                         np->tx_ring.ex[i].txvlan = 0;
1926                         np->tx_ring.ex[i].bufhigh = 0;
1927                         np->tx_ring.ex[i].buflow = 0;
1928                 }
1929                 if (nv_release_txskb(dev, &np->tx_skb[i]))
1930                         dev->stats.tx_dropped++;
1931                 np->tx_skb[i].dma = 0;
1932                 np->tx_skb[i].dma_len = 0;
1933                 np->tx_skb[i].first_tx_desc = NULL;
1934                 np->tx_skb[i].next_tx_ctx = NULL;
1935         }
1936         np->tx_pkts_in_progress = 0;
1937         np->tx_change_owner = NULL;
1938         np->tx_end_flip = NULL;
1939 }
1940
1941 static void nv_drain_rx(struct net_device *dev)
1942 {
1943         struct fe_priv *np = netdev_priv(dev);
1944         int i;
1945
1946         for (i = 0; i < np->rx_ring_size; i++) {
1947                 if (!nv_optimized(np)) {
1948                         np->rx_ring.orig[i].flaglen = 0;
1949                         np->rx_ring.orig[i].buf = 0;
1950                 } else {
1951                         np->rx_ring.ex[i].flaglen = 0;
1952                         np->rx_ring.ex[i].txvlan = 0;
1953                         np->rx_ring.ex[i].bufhigh = 0;
1954                         np->rx_ring.ex[i].buflow = 0;
1955                 }
1956                 wmb();
1957                 if (np->rx_skb[i].skb) {
1958                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1959                                          (skb_end_pointer(np->rx_skb[i].skb) -
1960                                           np->rx_skb[i].skb->data),
1961                                          PCI_DMA_FROMDEVICE);
1962                         dev_kfree_skb(np->rx_skb[i].skb);
1963                         np->rx_skb[i].skb = NULL;
1964                 }
1965         }
1966 }
1967
1968 static void nv_drain_rxtx(struct net_device *dev)
1969 {
1970         nv_drain_tx(dev);
1971         nv_drain_rx(dev);
1972 }
1973
1974 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1975 {
1976         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1977 }
1978
1979 static void nv_legacybackoff_reseed(struct net_device *dev)
1980 {
1981         u8 __iomem *base = get_hwbase(dev);
1982         u32 reg;
1983         u32 low;
1984         int tx_status = 0;
1985
1986         reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
1987         get_random_bytes(&low, sizeof(low));
1988         reg |= low & NVREG_SLOTTIME_MASK;
1989
1990         /* Need to stop tx before change takes effect.
1991          * Caller has already gained np->lock.
1992          */
1993         tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
1994         if (tx_status)
1995                 nv_stop_tx(dev);
1996         nv_stop_rx(dev);
1997         writel(reg, base + NvRegSlotTime);
1998         if (tx_status)
1999                 nv_start_tx(dev);
2000         nv_start_rx(dev);
2001 }
2002
2003 /* Gear Backoff Seeds */
2004 #define BACKOFF_SEEDSET_ROWS    8
2005 #define BACKOFF_SEEDSET_LFSRS   15
2006
2007 /* Known Good seed sets */
2008 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2009     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2010     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2011     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2012     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2013     {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2014     {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2015     {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800,  84},
2016     {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
2017
2018 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2019     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2020     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2021     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2022     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2023     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2024     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2025     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2026     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
2027
2028 static void nv_gear_backoff_reseed(struct net_device *dev)
2029 {
2030         u8 __iomem *base = get_hwbase(dev);
2031         u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2032         u32 temp, seedset, combinedSeed;
2033         int i;
2034
2035         /* Setup seed for free running LFSR */
2036         /* We are going to read the time stamp counter 3 times
2037            and swizzle bits around to increase randomness */
2038         get_random_bytes(&miniseed1, sizeof(miniseed1));
2039         miniseed1 &= 0x0fff;
2040         if (miniseed1 == 0)
2041                 miniseed1 = 0xabc;
2042
2043         get_random_bytes(&miniseed2, sizeof(miniseed2));
2044         miniseed2 &= 0x0fff;
2045         if (miniseed2 == 0)
2046                 miniseed2 = 0xabc;
2047         miniseed2_reversed =
2048                 ((miniseed2 & 0xF00) >> 8) |
2049                  (miniseed2 & 0x0F0) |
2050                  ((miniseed2 & 0x00F) << 8);
2051
2052         get_random_bytes(&miniseed3, sizeof(miniseed3));
2053         miniseed3 &= 0x0fff;
2054         if (miniseed3 == 0)
2055                 miniseed3 = 0xabc;
2056         miniseed3_reversed =
2057                 ((miniseed3 & 0xF00) >> 8) |
2058                  (miniseed3 & 0x0F0) |
2059                  ((miniseed3 & 0x00F) << 8);
2060
2061         combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2062                        (miniseed2 ^ miniseed3_reversed);
2063
2064         /* Seeds can not be zero */
2065         if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2066                 combinedSeed |= 0x08;
2067         if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2068                 combinedSeed |= 0x8000;
2069
2070         /* No need to disable tx here */
2071         temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2072         temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2073         temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2074         writel(temp,base + NvRegBackOffControl);
2075
2076         /* Setup seeds for all gear LFSRs. */
2077         get_random_bytes(&seedset, sizeof(seedset));
2078         seedset = seedset % BACKOFF_SEEDSET_ROWS;
2079         for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++)
2080         {
2081                 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2082                 temp |= main_seedset[seedset][i-1] & 0x3ff;
2083                 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2084                 writel(temp, base + NvRegBackOffControl);
2085         }
2086 }
2087
2088 /*
2089  * nv_start_xmit: dev->hard_start_xmit function
2090  * Called with netif_tx_lock held.
2091  */
2092 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2093 {
2094         struct fe_priv *np = netdev_priv(dev);
2095         u32 tx_flags = 0;
2096         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2097         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2098         unsigned int i;
2099         u32 offset = 0;
2100         u32 bcnt;
2101         u32 size = skb->len-skb->data_len;
2102         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2103         u32 empty_slots;
2104         struct ring_desc* put_tx;
2105         struct ring_desc* start_tx;
2106         struct ring_desc* prev_tx;
2107         struct nv_skb_map* prev_tx_ctx;
2108         unsigned long flags;
2109
2110         /* add fragments to entries count */
2111         for (i = 0; i < fragments; i++) {
2112                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2113                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2114         }
2115
2116         spin_lock_irqsave(&np->lock, flags);
2117         empty_slots = nv_get_empty_tx_slots(np);
2118         if (unlikely(empty_slots <= entries)) {
2119                 netif_stop_queue(dev);
2120                 np->tx_stop = 1;
2121                 spin_unlock_irqrestore(&np->lock, flags);
2122                 return NETDEV_TX_BUSY;
2123         }
2124         spin_unlock_irqrestore(&np->lock, flags);
2125
2126         start_tx = put_tx = np->put_tx.orig;
2127
2128         /* setup the header buffer */
2129         do {
2130                 prev_tx = put_tx;
2131                 prev_tx_ctx = np->put_tx_ctx;
2132                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2133                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2134                                                 PCI_DMA_TODEVICE);
2135                 np->put_tx_ctx->dma_len = bcnt;
2136                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2137                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2138
2139                 tx_flags = np->tx_flags;
2140                 offset += bcnt;
2141                 size -= bcnt;
2142                 if (unlikely(put_tx++ == np->last_tx.orig))
2143                         put_tx = np->first_tx.orig;
2144                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2145                         np->put_tx_ctx = np->first_tx_ctx;
2146         } while (size);
2147
2148         /* setup the fragments */
2149         for (i = 0; i < fragments; i++) {
2150                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2151                 u32 size = frag->size;
2152                 offset = 0;
2153
2154                 do {
2155                         prev_tx = put_tx;
2156                         prev_tx_ctx = np->put_tx_ctx;
2157                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2158                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2159                                                            PCI_DMA_TODEVICE);
2160                         np->put_tx_ctx->dma_len = bcnt;
2161                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2162                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2163
2164                         offset += bcnt;
2165                         size -= bcnt;
2166                         if (unlikely(put_tx++ == np->last_tx.orig))
2167                                 put_tx = np->first_tx.orig;
2168                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2169                                 np->put_tx_ctx = np->first_tx_ctx;
2170                 } while (size);
2171         }
2172
2173         /* set last fragment flag  */
2174         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2175
2176         /* save skb in this slot's context area */
2177         prev_tx_ctx->skb = skb;
2178
2179         if (skb_is_gso(skb))
2180                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2181         else
2182                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2183                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2184
2185         spin_lock_irqsave(&np->lock, flags);
2186
2187         /* set tx flags */
2188         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2189         np->put_tx.orig = put_tx;
2190
2191         spin_unlock_irqrestore(&np->lock, flags);
2192
2193         dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
2194                 dev->name, entries, tx_flags_extra);
2195         {
2196                 int j;
2197                 for (j=0; j<64; j++) {
2198                         if ((j%16) == 0)
2199                                 dprintk("\n%03x:", j);
2200                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2201                 }
2202                 dprintk("\n");
2203         }
2204
2205         dev->trans_start = jiffies;
2206         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2207         return NETDEV_TX_OK;
2208 }
2209
2210 static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
2211 {
2212         struct fe_priv *np = netdev_priv(dev);
2213         u32 tx_flags = 0;
2214         u32 tx_flags_extra;
2215         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2216         unsigned int i;
2217         u32 offset = 0;
2218         u32 bcnt;
2219         u32 size = skb->len-skb->data_len;
2220         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2221         u32 empty_slots;
2222         struct ring_desc_ex* put_tx;
2223         struct ring_desc_ex* start_tx;
2224         struct ring_desc_ex* prev_tx;
2225         struct nv_skb_map* prev_tx_ctx;
2226         struct nv_skb_map* start_tx_ctx;
2227         unsigned long flags;
2228
2229         /* add fragments to entries count */
2230         for (i = 0; i < fragments; i++) {
2231                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2232                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2233         }
2234
2235         spin_lock_irqsave(&np->lock, flags);
2236         empty_slots = nv_get_empty_tx_slots(np);
2237         if (unlikely(empty_slots <= entries)) {
2238                 netif_stop_queue(dev);
2239                 np->tx_stop = 1;
2240                 spin_unlock_irqrestore(&np->lock, flags);
2241                 return NETDEV_TX_BUSY;
2242         }
2243         spin_unlock_irqrestore(&np->lock, flags);
2244
2245         start_tx = put_tx = np->put_tx.ex;
2246         start_tx_ctx = np->put_tx_ctx;
2247
2248         /* setup the header buffer */
2249         do {
2250                 prev_tx = put_tx;
2251                 prev_tx_ctx = np->put_tx_ctx;
2252                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2253                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2254                                                 PCI_DMA_TODEVICE);
2255                 np->put_tx_ctx->dma_len = bcnt;
2256                 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2257                 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2258                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2259
2260                 tx_flags = NV_TX2_VALID;
2261                 offset += bcnt;
2262                 size -= bcnt;
2263                 if (unlikely(put_tx++ == np->last_tx.ex))
2264                         put_tx = np->first_tx.ex;
2265                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2266                         np->put_tx_ctx = np->first_tx_ctx;
2267         } while (size);
2268
2269         /* setup the fragments */
2270         for (i = 0; i < fragments; i++) {
2271                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2272                 u32 size = frag->size;
2273                 offset = 0;
2274
2275                 do {
2276                         prev_tx = put_tx;
2277                         prev_tx_ctx = np->put_tx_ctx;
2278                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2279                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2280                                                            PCI_DMA_TODEVICE);
2281                         np->put_tx_ctx->dma_len = bcnt;
2282                         put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2283                         put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2284                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2285
2286                         offset += bcnt;
2287                         size -= bcnt;
2288                         if (unlikely(put_tx++ == np->last_tx.ex))
2289                                 put_tx = np->first_tx.ex;
2290                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2291                                 np->put_tx_ctx = np->first_tx_ctx;
2292                 } while (size);
2293         }
2294
2295         /* set last fragment flag  */
2296         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2297
2298         /* save skb in this slot's context area */
2299         prev_tx_ctx->skb = skb;
2300
2301         if (skb_is_gso(skb))
2302                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2303         else
2304                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2305                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2306
2307         /* vlan tag */
2308         if (likely(!np->vlangrp)) {
2309                 start_tx->txvlan = 0;
2310         } else {
2311                 if (vlan_tx_tag_present(skb))
2312                         start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
2313                 else
2314                         start_tx->txvlan = 0;
2315         }
2316
2317         spin_lock_irqsave(&np->lock, flags);
2318
2319         if (np->tx_limit) {
2320                 /* Limit the number of outstanding tx. Setup all fragments, but
2321                  * do not set the VALID bit on the first descriptor. Save a pointer
2322                  * to that descriptor and also for next skb_map element.
2323                  */
2324
2325                 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2326                         if (!np->tx_change_owner)
2327                                 np->tx_change_owner = start_tx_ctx;
2328
2329                         /* remove VALID bit */
2330                         tx_flags &= ~NV_TX2_VALID;
2331                         start_tx_ctx->first_tx_desc = start_tx;
2332                         start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2333                         np->tx_end_flip = np->put_tx_ctx;
2334                 } else {
2335                         np->tx_pkts_in_progress++;
2336                 }
2337         }
2338
2339         /* set tx flags */
2340         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2341         np->put_tx.ex = put_tx;
2342
2343         spin_unlock_irqrestore(&np->lock, flags);
2344
2345         dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2346                 dev->name, entries, tx_flags_extra);
2347         {
2348                 int j;
2349                 for (j=0; j<64; j++) {
2350                         if ((j%16) == 0)
2351                                 dprintk("\n%03x:", j);
2352                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2353                 }
2354                 dprintk("\n");
2355         }
2356
2357         dev->trans_start = jiffies;
2358         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2359         return NETDEV_TX_OK;
2360 }
2361
2362 static inline void nv_tx_flip_ownership(struct net_device *dev)
2363 {
2364         struct fe_priv *np = netdev_priv(dev);
2365
2366         np->tx_pkts_in_progress--;
2367         if (np->tx_change_owner) {
2368                 np->tx_change_owner->first_tx_desc->flaglen |=
2369                         cpu_to_le32(NV_TX2_VALID);
2370                 np->tx_pkts_in_progress++;
2371
2372                 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2373                 if (np->tx_change_owner == np->tx_end_flip)
2374                         np->tx_change_owner = NULL;
2375
2376                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2377         }
2378 }
2379
2380 /*
2381  * nv_tx_done: check for completed packets, release the skbs.
2382  *
2383  * Caller must own np->lock.
2384  */
2385 static void nv_tx_done(struct net_device *dev)
2386 {
2387         struct fe_priv *np = netdev_priv(dev);
2388         u32 flags;
2389         struct ring_desc* orig_get_tx = np->get_tx.orig;
2390
2391         while ((np->get_tx.orig != np->put_tx.orig) &&
2392                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID)) {
2393
2394                 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2395                                         dev->name, flags);
2396
2397                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2398                                np->get_tx_ctx->dma_len,
2399                                PCI_DMA_TODEVICE);
2400                 np->get_tx_ctx->dma = 0;
2401
2402                 if (np->desc_ver == DESC_VER_1) {
2403                         if (flags & NV_TX_LASTPACKET) {
2404                                 if (flags & NV_TX_ERROR) {
2405                                         if (flags & NV_TX_UNDERFLOW)
2406                                                 dev->stats.tx_fifo_errors++;
2407                                         if (flags & NV_TX_CARRIERLOST)
2408                                                 dev->stats.tx_carrier_errors++;
2409                                         if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2410                                                 nv_legacybackoff_reseed(dev);
2411                                         dev->stats.tx_errors++;
2412                                 } else {
2413                                         dev->stats.tx_packets++;
2414                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2415                                 }
2416                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2417                                 np->get_tx_ctx->skb = NULL;
2418                         }
2419                 } else {
2420                         if (flags & NV_TX2_LASTPACKET) {
2421                                 if (flags & NV_TX2_ERROR) {
2422                                         if (flags & NV_TX2_UNDERFLOW)
2423                                                 dev->stats.tx_fifo_errors++;
2424                                         if (flags & NV_TX2_CARRIERLOST)
2425                                                 dev->stats.tx_carrier_errors++;
2426                                         if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2427                                                 nv_legacybackoff_reseed(dev);
2428                                         dev->stats.tx_errors++;
2429                                 } else {
2430                                         dev->stats.tx_packets++;
2431                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2432                                 }
2433                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2434                                 np->get_tx_ctx->skb = NULL;
2435                         }
2436                 }
2437                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2438                         np->get_tx.orig = np->first_tx.orig;
2439                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2440                         np->get_tx_ctx = np->first_tx_ctx;
2441         }
2442         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2443                 np->tx_stop = 0;
2444                 netif_wake_queue(dev);
2445         }
2446 }
2447
2448 static void nv_tx_done_optimized(struct net_device *dev, int limit)
2449 {
2450         struct fe_priv *np = netdev_priv(dev);
2451         u32 flags;
2452         struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
2453
2454         while ((np->get_tx.ex != np->put_tx.ex) &&
2455                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
2456                (limit-- > 0)) {
2457
2458                 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2459                                         dev->name, flags);
2460
2461                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2462                                np->get_tx_ctx->dma_len,
2463                                PCI_DMA_TODEVICE);
2464                 np->get_tx_ctx->dma = 0;
2465
2466                 if (flags & NV_TX2_LASTPACKET) {
2467                         if (!(flags & NV_TX2_ERROR))
2468                                 dev->stats.tx_packets++;
2469                         else {
2470                                 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2471                                         if (np->driver_data & DEV_HAS_GEAR_MODE)
2472                                                 nv_gear_backoff_reseed(dev);
2473                                         else
2474                                                 nv_legacybackoff_reseed(dev);
2475                                 }
2476                         }
2477
2478                         dev_kfree_skb_any(np->get_tx_ctx->skb);
2479                         np->get_tx_ctx->skb = NULL;
2480
2481                         if (np->tx_limit) {
2482                                 nv_tx_flip_ownership(dev);
2483                         }
2484                 }
2485                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2486                         np->get_tx.ex = np->first_tx.ex;
2487                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2488                         np->get_tx_ctx = np->first_tx_ctx;
2489         }
2490         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2491                 np->tx_stop = 0;
2492                 netif_wake_queue(dev);
2493         }
2494 }
2495
2496 /*
2497  * nv_tx_timeout: dev->tx_timeout function
2498  * Called with netif_tx_lock held.
2499  */
2500 static void nv_tx_timeout(struct net_device *dev)
2501 {
2502         struct fe_priv *np = netdev_priv(dev);
2503         u8 __iomem *base = get_hwbase(dev);
2504         u32 status;
2505
2506         if (np->msi_flags & NV_MSI_X_ENABLED)
2507                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2508         else
2509                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2510
2511         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
2512
2513         {
2514                 int i;
2515
2516                 printk(KERN_INFO "%s: Ring at %lx\n",
2517                        dev->name, (unsigned long)np->ring_addr);
2518                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
2519                 for (i=0;i<=np->register_size;i+= 32) {
2520                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2521                                         i,
2522                                         readl(base + i + 0), readl(base + i + 4),
2523                                         readl(base + i + 8), readl(base + i + 12),
2524                                         readl(base + i + 16), readl(base + i + 20),
2525                                         readl(base + i + 24), readl(base + i + 28));
2526                 }
2527                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
2528                 for (i=0;i<np->tx_ring_size;i+= 4) {
2529                         if (!nv_optimized(np)) {
2530                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2531                                        i,
2532                                        le32_to_cpu(np->tx_ring.orig[i].buf),
2533                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
2534                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
2535                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2536                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
2537                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2538                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
2539                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2540                         } else {
2541                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2542                                        i,
2543                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2544                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
2545                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
2546                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2547                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2548                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2549                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2550                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2551                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2552                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2553                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2554                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2555                         }
2556                 }
2557         }
2558
2559         spin_lock_irq(&np->lock);
2560
2561         /* 1) stop tx engine */
2562         nv_stop_tx(dev);
2563
2564         /* 2) check that the packets were not sent already: */
2565         if (!nv_optimized(np))
2566                 nv_tx_done(dev);
2567         else
2568                 nv_tx_done_optimized(dev, np->tx_ring_size);
2569
2570         /* 3) if there are dead entries: clear everything */
2571         if (np->get_tx_ctx != np->put_tx_ctx) {
2572                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
2573                 nv_drain_tx(dev);
2574                 nv_init_tx(dev);
2575                 setup_hw_rings(dev, NV_SETUP_TX_RING);
2576         }
2577
2578         netif_wake_queue(dev);
2579
2580         /* 4) restart tx engine */
2581         nv_start_tx(dev);
2582         spin_unlock_irq(&np->lock);
2583 }
2584
2585 /*
2586  * Called when the nic notices a mismatch between the actual data len on the
2587  * wire and the len indicated in the 802 header
2588  */
2589 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2590 {
2591         int hdrlen;     /* length of the 802 header */
2592         int protolen;   /* length as stored in the proto field */
2593
2594         /* 1) calculate len according to header */
2595         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2596                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2597                 hdrlen = VLAN_HLEN;
2598         } else {
2599                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2600                 hdrlen = ETH_HLEN;
2601         }
2602         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2603                                 dev->name, datalen, protolen, hdrlen);
2604         if (protolen > ETH_DATA_LEN)
2605                 return datalen; /* Value in proto field not a len, no checks possible */
2606
2607         protolen += hdrlen;
2608         /* consistency checks: */
2609         if (datalen > ETH_ZLEN) {
2610                 if (datalen >= protolen) {
2611                         /* more data on wire than in 802 header, trim of
2612                          * additional data.
2613                          */
2614                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2615                                         dev->name, protolen);
2616                         return protolen;
2617                 } else {
2618                         /* less data on wire than mentioned in header.
2619                          * Discard the packet.
2620                          */
2621                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2622                                         dev->name);
2623                         return -1;
2624                 }
2625         } else {
2626                 /* short packet. Accept only if 802 values are also short */
2627                 if (protolen > ETH_ZLEN) {
2628                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2629                                         dev->name);
2630                         return -1;
2631                 }
2632                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2633                                 dev->name, datalen);
2634                 return datalen;
2635         }
2636 }
2637
2638 static int nv_rx_process(struct net_device *dev, int limit)
2639 {
2640         struct fe_priv *np = netdev_priv(dev);
2641         u32 flags;
2642         int rx_work = 0;
2643         struct sk_buff *skb;
2644         int len;
2645
2646         while((np->get_rx.orig != np->put_rx.orig) &&
2647               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2648                 (rx_work < limit)) {
2649
2650                 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2651                                         dev->name, flags);
2652
2653                 /*
2654                  * the packet is for us - immediately tear down the pci mapping.
2655                  * TODO: check if a prefetch of the first cacheline improves
2656                  * the performance.
2657                  */
2658                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2659                                 np->get_rx_ctx->dma_len,
2660                                 PCI_DMA_FROMDEVICE);
2661                 skb = np->get_rx_ctx->skb;
2662                 np->get_rx_ctx->skb = NULL;
2663
2664                 {
2665                         int j;
2666                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2667                         for (j=0; j<64; j++) {
2668                                 if ((j%16) == 0)
2669                                         dprintk("\n%03x:", j);
2670                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2671                         }
2672                         dprintk("\n");
2673                 }
2674                 /* look at what we actually got: */
2675                 if (np->desc_ver == DESC_VER_1) {
2676                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2677                                 len = flags & LEN_MASK_V1;
2678                                 if (unlikely(flags & NV_RX_ERROR)) {
2679                                         if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2680                                                 len = nv_getlen(dev, skb->data, len);
2681                                                 if (len < 0) {
2682                                                         dev->stats.rx_errors++;
2683                                                         dev_kfree_skb(skb);
2684                                                         goto next_pkt;
2685                                                 }
2686                                         }
2687                                         /* framing errors are soft errors */
2688                                         else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2689                                                 if (flags & NV_RX_SUBSTRACT1) {
2690                                                         len--;
2691                                                 }
2692                                         }
2693                                         /* the rest are hard errors */
2694                                         else {
2695                                                 if (flags & NV_RX_MISSEDFRAME)
2696                                                         dev->stats.rx_missed_errors++;
2697                                                 if (flags & NV_RX_CRCERR)
2698                                                         dev->stats.rx_crc_errors++;
2699                                                 if (flags & NV_RX_OVERFLOW)
2700                                                         dev->stats.rx_over_errors++;
2701                                                 dev->stats.rx_errors++;
2702                                                 dev_kfree_skb(skb);
2703                                                 goto next_pkt;
2704                                         }
2705                                 }
2706                         } else {
2707                                 dev_kfree_skb(skb);
2708                                 goto next_pkt;
2709                         }
2710                 } else {
2711                         if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2712                                 len = flags & LEN_MASK_V2;
2713                                 if (unlikely(flags & NV_RX2_ERROR)) {
2714                                         if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2715                                                 len = nv_getlen(dev, skb->data, len);
2716                                                 if (len < 0) {
2717                                                         dev->stats.rx_errors++;
2718                                                         dev_kfree_skb(skb);
2719                                                         goto next_pkt;
2720                                                 }
2721                                         }
2722                                         /* framing errors are soft errors */
2723                                         else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2724                                                 if (flags & NV_RX2_SUBSTRACT1) {
2725                                                         len--;
2726                                                 }
2727                                         }
2728                                         /* the rest are hard errors */
2729                                         else {
2730                                                 if (flags & NV_RX2_CRCERR)
2731                                                         dev->stats.rx_crc_errors++;
2732                                                 if (flags & NV_RX2_OVERFLOW)
2733                                                         dev->stats.rx_over_errors++;
2734                                                 dev->stats.rx_errors++;
2735                                                 dev_kfree_skb(skb);
2736                                                 goto next_pkt;
2737                                         }
2738                                 }
2739                                 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2740                                     ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2741                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2742                         } else {
2743                                 dev_kfree_skb(skb);
2744                                 goto next_pkt;
2745                         }
2746                 }
2747                 /* got a valid packet - forward it to the network core */
2748                 skb_put(skb, len);
2749                 skb->protocol = eth_type_trans(skb, dev);
2750                 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2751                                         dev->name, len, skb->protocol);
2752 #ifdef CONFIG_FORCEDETH_NAPI
2753                 netif_receive_skb(skb);
2754 #else
2755                 netif_rx(skb);
2756 #endif
2757                 dev->stats.rx_packets++;
2758                 dev->stats.rx_bytes += len;
2759 next_pkt:
2760                 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2761                         np->get_rx.orig = np->first_rx.orig;
2762                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2763                         np->get_rx_ctx = np->first_rx_ctx;
2764
2765                 rx_work++;
2766         }
2767
2768         return rx_work;
2769 }
2770
2771 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2772 {
2773         struct fe_priv *np = netdev_priv(dev);
2774         u32 flags;
2775         u32 vlanflags = 0;
2776         int rx_work = 0;
2777         struct sk_buff *skb;
2778         int len;
2779
2780         while((np->get_rx.ex != np->put_rx.ex) &&
2781               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2782               (rx_work < limit)) {
2783
2784                 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2785                                         dev->name, flags);
2786
2787                 /*
2788                  * the packet is for us - immediately tear down the pci mapping.
2789                  * TODO: check if a prefetch of the first cacheline improves
2790                  * the performance.
2791                  */
2792                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2793                                 np->get_rx_ctx->dma_len,
2794                                 PCI_DMA_FROMDEVICE);
2795                 skb = np->get_rx_ctx->skb;
2796                 np->get_rx_ctx->skb = NULL;
2797
2798                 {
2799                         int j;
2800                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2801                         for (j=0; j<64; j++) {
2802                                 if ((j%16) == 0)
2803                                         dprintk("\n%03x:", j);
2804                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2805                         }
2806                         dprintk("\n");
2807                 }
2808                 /* look at what we actually got: */
2809                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2810                         len = flags & LEN_MASK_V2;
2811                         if (unlikely(flags & NV_RX2_ERROR)) {
2812                                 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2813                                         len = nv_getlen(dev, skb->data, len);
2814                                         if (len < 0) {
2815                                                 dev_kfree_skb(skb);
2816                                                 goto next_pkt;
2817                                         }
2818                                 }
2819                                 /* framing errors are soft errors */
2820                                 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2821                                         if (flags & NV_RX2_SUBSTRACT1) {
2822                                                 len--;
2823                                         }
2824                                 }
2825                                 /* the rest are hard errors */
2826                                 else {
2827                                         dev_kfree_skb(skb);
2828                                         goto next_pkt;
2829                                 }
2830                         }
2831
2832                         if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2833                             ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2834                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2835
2836                         /* got a valid packet - forward it to the network core */
2837                         skb_put(skb, len);
2838                         skb->protocol = eth_type_trans(skb, dev);
2839                         prefetch(skb->data);
2840
2841                         dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2842                                 dev->name, len, skb->protocol);
2843
2844                         if (likely(!np->vlangrp)) {
2845 #ifdef CONFIG_FORCEDETH_NAPI
2846                                 netif_receive_skb(skb);
2847 #else
2848                                 netif_rx(skb);
2849 #endif
2850                         } else {
2851                                 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2852                                 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2853 #ifdef CONFIG_FORCEDETH_NAPI
2854                                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
2855                                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
2856 #else
2857                                         vlan_hwaccel_rx(skb, np->vlangrp,
2858                                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
2859 #endif
2860                                 } else {
2861 #ifdef CONFIG_FORCEDETH_NAPI
2862                                         netif_receive_skb(skb);
2863 #else
2864                                         netif_rx(skb);
2865 #endif
2866                                 }
2867                         }
2868
2869                         dev->stats.rx_packets++;
2870                         dev->stats.rx_bytes += len;
2871                 } else {
2872                         dev_kfree_skb(skb);
2873                 }
2874 next_pkt:
2875                 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2876                         np->get_rx.ex = np->first_rx.ex;
2877                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2878                         np->get_rx_ctx = np->first_rx_ctx;
2879
2880                 rx_work++;
2881         }
2882
2883         return rx_work;
2884 }
2885
2886 static void set_bufsize(struct net_device *dev)
2887 {
2888         struct fe_priv *np = netdev_priv(dev);
2889
2890         if (dev->mtu <= ETH_DATA_LEN)
2891                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2892         else
2893                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2894 }
2895
2896 /*
2897  * nv_change_mtu: dev->change_mtu function
2898  * Called with dev_base_lock held for read.
2899  */
2900 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2901 {
2902         struct fe_priv *np = netdev_priv(dev);
2903         int old_mtu;
2904
2905         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2906                 return -EINVAL;
2907
2908         old_mtu = dev->mtu;
2909         dev->mtu = new_mtu;
2910
2911         /* return early if the buffer sizes will not change */
2912         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2913                 return 0;
2914         if (old_mtu == new_mtu)
2915                 return 0;
2916
2917         /* synchronized against open : rtnl_lock() held by caller */
2918         if (netif_running(dev)) {
2919                 u8 __iomem *base = get_hwbase(dev);
2920                 /*
2921                  * It seems that the nic preloads valid ring entries into an
2922                  * internal buffer. The procedure for flushing everything is
2923                  * guessed, there is probably a simpler approach.
2924                  * Changing the MTU is a rare event, it shouldn't matter.
2925                  */
2926                 nv_disable_irq(dev);
2927                 netif_tx_lock_bh(dev);
2928                 netif_addr_lock(dev);
2929                 spin_lock(&np->lock);
2930                 /* stop engines */
2931                 nv_stop_rxtx(dev);
2932                 nv_txrx_reset(dev);
2933                 /* drain rx queue */
2934                 nv_drain_rxtx(dev);
2935                 /* reinit driver view of the rx queue */
2936                 set_bufsize(dev);
2937                 if (nv_init_ring(dev)) {
2938                         if (!np->in_shutdown)
2939                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2940                 }
2941                 /* reinit nic view of the rx queue */
2942                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2943                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2944                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2945                         base + NvRegRingSizes);
2946                 pci_push(base);
2947                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2948                 pci_push(base);
2949
2950                 /* restart rx engine */
2951                 nv_start_rxtx(dev);
2952                 spin_unlock(&np->lock);
2953                 netif_addr_unlock(dev);
2954                 netif_tx_unlock_bh(dev);
2955                 nv_enable_irq(dev);
2956         }
2957         return 0;
2958 }
2959
2960 static void nv_copy_mac_to_hw(struct net_device *dev)
2961 {
2962         u8 __iomem *base = get_hwbase(dev);
2963         u32 mac[2];
2964
2965         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2966                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2967         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2968
2969         writel(mac[0], base + NvRegMacAddrA);
2970         writel(mac[1], base + NvRegMacAddrB);
2971 }
2972
2973 /*
2974  * nv_set_mac_address: dev->set_mac_address function
2975  * Called with rtnl_lock() held.
2976  */
2977 static int nv_set_mac_address(struct net_device *dev, void *addr)
2978 {
2979         struct fe_priv *np = netdev_priv(dev);
2980         struct sockaddr *macaddr = (struct sockaddr*)addr;
2981
2982         if (!is_valid_ether_addr(macaddr->sa_data))
2983                 return -EADDRNOTAVAIL;
2984
2985         /* synchronized against open : rtnl_lock() held by caller */
2986         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2987
2988         if (netif_running(dev)) {
2989                 netif_tx_lock_bh(dev);
2990                 netif_addr_lock(dev);
2991                 spin_lock_irq(&np->lock);
2992
2993                 /* stop rx engine */
2994                 nv_stop_rx(dev);
2995
2996                 /* set mac address */
2997                 nv_copy_mac_to_hw(dev);
2998
2999                 /* restart rx engine */
3000                 nv_start_rx(dev);
3001                 spin_unlock_irq(&np->lock);
3002                 netif_addr_unlock(dev);
3003                 netif_tx_unlock_bh(dev);
3004         } else {
3005                 nv_copy_mac_to_hw(dev);
3006         }
3007         return 0;
3008 }
3009
3010 /*
3011  * nv_set_multicast: dev->set_multicast function
3012  * Called with netif_tx_lock held.
3013  */
3014 static void nv_set_multicast(struct net_device *dev)
3015 {
3016         struct fe_priv *np = netdev_priv(dev);
3017         u8 __iomem *base = get_hwbase(dev);
3018         u32 addr[2];
3019         u32 mask[2];
3020         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
3021
3022         memset(addr, 0, sizeof(addr));
3023         memset(mask, 0, sizeof(mask));
3024
3025         if (dev->flags & IFF_PROMISC) {
3026                 pff |= NVREG_PFF_PROMISC;
3027         } else {
3028                 pff |= NVREG_PFF_MYADDR;
3029
3030                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
3031                         u32 alwaysOff[2];
3032                         u32 alwaysOn[2];
3033
3034                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3035                         if (dev->flags & IFF_ALLMULTI) {
3036                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3037                         } else {
3038                                 struct dev_mc_list *walk;
3039
3040                                 walk = dev->mc_list;
3041                                 while (walk != NULL) {
3042                                         u32 a, b;
3043                                         a = le32_to_cpu(*(__le32 *) walk->dmi_addr);
3044                                         b = le16_to_cpu(*(__le16 *) (&walk->dmi_addr[4]));
3045                                         alwaysOn[0] &= a;
3046                                         alwaysOff[0] &= ~a;
3047                                         alwaysOn[1] &= b;
3048                                         alwaysOff[1] &= ~b;
3049                                         walk = walk->next;
3050                                 }
3051                         }
3052                         addr[0] = alwaysOn[0];
3053                         addr[1] = alwaysOn[1];
3054                         mask[0] = alwaysOn[0] | alwaysOff[0];
3055                         mask[1] = alwaysOn[1] | alwaysOff[1];
3056                 } else {
3057                         mask[0] = NVREG_MCASTMASKA_NONE;
3058                         mask[1] = NVREG_MCASTMASKB_NONE;
3059                 }
3060         }
3061         addr[0] |= NVREG_MCASTADDRA_FORCE;
3062         pff |= NVREG_PFF_ALWAYS;
3063         spin_lock_irq(&np->lock);
3064         nv_stop_rx(dev);
3065         writel(addr[0], base + NvRegMulticastAddrA);
3066         writel(addr[1], base + NvRegMulticastAddrB);
3067         writel(mask[0], base + NvRegMulticastMaskA);
3068         writel(mask[1], base + NvRegMulticastMaskB);
3069         writel(pff, base + NvRegPacketFilterFlags);
3070         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
3071                 dev->name);
3072         nv_start_rx(dev);
3073         spin_unlock_irq(&np->lock);
3074 }
3075
3076 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
3077 {
3078         struct fe_priv *np = netdev_priv(dev);
3079         u8 __iomem *base = get_hwbase(dev);
3080
3081         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3082
3083         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3084                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3085                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3086                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3087                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3088                 } else {
3089                         writel(pff, base + NvRegPacketFilterFlags);
3090                 }
3091         }
3092         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3093                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3094                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3095                         u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3096                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3097                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3098                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3099                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3100                                 /* limit the number of tx pause frames to a default of 8 */
3101                                 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3102                         }
3103                         writel(pause_enable,  base + NvRegTxPauseFrame);
3104                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3105                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3106                 } else {
3107                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
3108                         writel(regmisc, base + NvRegMisc1);
3109                 }
3110         }
3111 }
3112
3113 /**
3114  * nv_update_linkspeed: Setup the MAC according to the link partner
3115  * @dev: Network device to be configured
3116  *
3117  * The function queries the PHY and checks if there is a link partner.
3118  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3119  * set to 10 MBit HD.
3120  *
3121  * The function returns 0 if there is no link partner and 1 if there is
3122  * a good link partner.
3123  */
3124 static int nv_update_linkspeed(struct net_device *dev)
3125 {
3126         struct fe_priv *np = netdev_priv(dev);
3127         u8 __iomem *base = get_hwbase(dev);
3128         int adv = 0;
3129         int lpa = 0;
3130         int adv_lpa, adv_pause, lpa_pause;
3131         int newls = np->linkspeed;
3132         int newdup = np->duplex;
3133         int mii_status;
3134         int retval = 0;
3135         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3136         u32 txrxFlags = 0;
3137         u32 phy_exp;
3138
3139         /* BMSR_LSTATUS is latched, read it twice:
3140          * we want the current value.
3141          */
3142         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3143         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3144
3145         if (!(mii_status & BMSR_LSTATUS)) {
3146                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
3147                                 dev->name);
3148                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3149                 newdup = 0;
3150                 retval = 0;
3151                 goto set_speed;
3152         }
3153
3154         if (np->autoneg == 0) {
3155                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
3156                                 dev->name, np->fixed_mode);
3157                 if (np->fixed_mode & LPA_100FULL) {
3158                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3159                         newdup = 1;
3160                 } else if (np->fixed_mode & LPA_100HALF) {
3161                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3162                         newdup = 0;
3163                 } else if (np->fixed_mode & LPA_10FULL) {
3164                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3165                         newdup = 1;
3166                 } else {
3167                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3168                         newdup = 0;
3169                 }
3170                 retval = 1;
3171                 goto set_speed;
3172         }
3173         /* check auto negotiation is complete */
3174         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3175                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3176                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3177                 newdup = 0;
3178                 retval = 0;
3179                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
3180                 goto set_speed;
3181         }
3182
3183         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3184         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3185         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
3186                                 dev->name, adv, lpa);
3187
3188         retval = 1;
3189         if (np->gigabit == PHY_GIGABIT) {
3190                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3191                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3192
3193                 if ((control_1000 & ADVERTISE_1000FULL) &&
3194                         (status_1000 & LPA_1000FULL)) {
3195                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
3196                                 dev->name);
3197                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3198                         newdup = 1;
3199                         goto set_speed;
3200                 }
3201         }
3202
3203         /* FIXME: handle parallel detection properly */
3204         adv_lpa = lpa & adv;
3205         if (adv_lpa & LPA_100FULL) {
3206                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3207                 newdup = 1;
3208         } else if (adv_lpa & LPA_100HALF) {
3209                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3210                 newdup = 0;
3211         } else if (adv_lpa & LPA_10FULL) {
3212                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3213                 newdup = 1;
3214         } else if (adv_lpa & LPA_10HALF) {
3215                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3216                 newdup = 0;
3217         } else {
3218                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
3219                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3220                 newdup = 0;
3221         }
3222
3223 set_speed:
3224         if (np->duplex == newdup && np->linkspeed == newls)
3225                 return retval;
3226
3227         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
3228                         dev->name, np->linkspeed, np->duplex, newls, newdup);
3229
3230         np->duplex = newdup;
3231         np->linkspeed = newls;
3232
3233         /* The transmitter and receiver must be restarted for safe update */
3234         if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3235                 txrxFlags |= NV_RESTART_TX;
3236                 nv_stop_tx(dev);
3237         }
3238         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3239                 txrxFlags |= NV_RESTART_RX;
3240                 nv_stop_rx(dev);
3241         }
3242
3243         if (np->gigabit == PHY_GIGABIT) {
3244                 phyreg = readl(base + NvRegSlotTime);
3245                 phyreg &= ~(0x3FF00);
3246                 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3247                     ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3248                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3249                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3250                         phyreg |= NVREG_SLOTTIME_1000_FULL;
3251                 writel(phyreg, base + NvRegSlotTime);
3252         }
3253
3254         phyreg = readl(base + NvRegPhyInterface);
3255         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3256         if (np->duplex == 0)
3257                 phyreg |= PHY_HALF;
3258         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3259                 phyreg |= PHY_100;
3260         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3261                 phyreg |= PHY_1000;
3262         writel(phyreg, base + NvRegPhyInterface);
3263
3264         phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3265         if (phyreg & PHY_RGMII) {
3266                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3267                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3268                 } else {
3269                         if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3270                                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3271                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3272                                 else
3273                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3274                         } else {
3275                                 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3276                         }
3277                 }
3278         } else {
3279                 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3280                         txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3281                 else
3282                         txreg = NVREG_TX_DEFERRAL_DEFAULT;
3283         }
3284         writel(txreg, base + NvRegTxDeferral);
3285
3286         if (np->desc_ver == DESC_VER_1) {
3287                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3288         } else {
3289                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3290                         txreg = NVREG_TX_WM_DESC2_3_1000;
3291                 else
3292                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3293         }
3294         writel(txreg, base + NvRegTxWatermark);
3295
3296         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
3297                 base + NvRegMisc1);
3298         pci_push(base);
3299         writel(np->linkspeed, base + NvRegLinkSpeed);
3300         pci_push(base);
3301
3302         pause_flags = 0;
3303         /* setup pause frame */
3304         if (np->duplex != 0) {
3305                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3306                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
3307                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
3308
3309                         switch (adv_pause) {
3310                         case ADVERTISE_PAUSE_CAP:
3311                                 if (lpa_pause & LPA_PAUSE_CAP) {
3312                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3313                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3314                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3315                                 }
3316                                 break;
3317                         case ADVERTISE_PAUSE_ASYM:
3318                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
3319                                 {
3320                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3321                                 }
3322                                 break;
3323                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
3324                                 if (lpa_pause & LPA_PAUSE_CAP)
3325                                 {
3326                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
3327                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3328                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3329                                 }
3330                                 if (lpa_pause == LPA_PAUSE_ASYM)
3331                                 {
3332                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3333                                 }
3334                                 break;
3335                         }
3336                 } else {
3337                         pause_flags = np->pause_flags;
3338                 }
3339         }
3340         nv_update_pause(dev, pause_flags);
3341
3342         if (txrxFlags & NV_RESTART_TX)
3343                 nv_start_tx(dev);
3344         if (txrxFlags & NV_RESTART_RX)
3345                 nv_start_rx(dev);
3346
3347         return retval;
3348 }
3349
3350 static void nv_linkchange(struct net_device *dev)
3351 {
3352         if (nv_update_linkspeed(dev)) {
3353                 if (!netif_carrier_ok(dev)) {
3354                         netif_carrier_on(dev);
3355                         printk(KERN_INFO "%s: link up.\n", dev->name);
3356                         nv_start_rx(dev);
3357                 }
3358         } else {
3359                 if (netif_carrier_ok(dev)) {
3360                         netif_carrier_off(dev);
3361                         printk(KERN_INFO "%s: link down.\n", dev->name);
3362                         nv_stop_rx(dev);
3363                 }
3364         }
3365 }
3366
3367 static void nv_link_irq(struct net_device *dev)
3368 {
3369         u8 __iomem *base = get_hwbase(dev);
3370         u32 miistat;
3371
3372         miistat = readl(base + NvRegMIIStatus);
3373         writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3374         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3375
3376         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3377                 nv_linkchange(dev);
3378         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
3379 }
3380
3381 static void nv_msi_workaround(struct fe_priv *np)
3382 {
3383
3384         /* Need to toggle the msi irq mask within the ethernet device,
3385          * otherwise, future interrupts will not be detected.
3386          */
3387         if (np->msi_flags & NV_MSI_ENABLED) {
3388                 u8 __iomem *base = np->base;
3389
3390                 writel(0, base + NvRegMSIIrqMask);
3391                 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3392         }
3393 }
3394
3395 static irqreturn_t nv_nic_irq(int foo, void *data)
3396 {
3397         struct net_device *dev = (struct net_device *) data;
3398         struct fe_priv *np = netdev_priv(dev);
3399         u8 __iomem *base = get_hwbase(dev);
3400         u32 events;
3401         int i;
3402
3403         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
3404
3405         for (i=0; ; i++) {
3406                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3407                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3408                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3409                 } else {
3410                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3411                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3412                 }
3413                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3414                 if (!(events & np->irqmask))
3415                         break;
3416
3417                 nv_msi_workaround(np);
3418
3419                 spin_lock(&np->lock);
3420                 nv_tx_done(dev);
3421                 spin_unlock(&np->lock);
3422
3423 #ifdef CONFIG_FORCEDETH_NAPI
3424                 if (events & NVREG_IRQ_RX_ALL) {
3425                         spin_lock(&np->lock);
3426                         napi_schedule(&np->napi);
3427
3428                         /* Disable furthur receive irq's */
3429                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
3430
3431                         if (np->msi_flags & NV_MSI_X_ENABLED)
3432                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3433                         else
3434                                 writel(np->irqmask, base + NvRegIrqMask);
3435                         spin_unlock(&np->lock);
3436                 }
3437 #else
3438                 if (nv_rx_process(dev, RX_WORK_PER_LOOP)) {
3439                         if (unlikely(nv_alloc_rx(dev))) {
3440                                 spin_lock(&np->lock);
3441                                 if (!np->in_shutdown)
3442                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3443                                 spin_unlock(&np->lock);
3444                         }
3445                 }
3446 #endif
3447                 if (unlikely(events & NVREG_IRQ_LINK)) {
3448                         spin_lock(&np->lock);
3449                         nv_link_irq(dev);
3450                         spin_unlock(&np->lock);
3451                 }
3452                 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3453                         spin_lock(&np->lock);
3454                         nv_linkchange(dev);
3455                         spin_unlock(&np->lock);
3456                         np->link_timeout = jiffies + LINK_TIMEOUT;
3457                 }
3458                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3459                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3460                                                 dev->name, events);
3461                 }
3462                 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3463                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3464                                                 dev->name, events);
3465                 }
3466                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3467                         spin_lock(&np->lock);
3468                         /* disable interrupts on the nic */
3469                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3470                                 writel(0, base + NvRegIrqMask);
3471                         else
3472                                 writel(np->irqmask, base + NvRegIrqMask);
3473                         pci_push(base);
3474
3475                         if (!np->in_shutdown) {
3476                                 np->nic_poll_irq = np->irqmask;
3477                                 np->recover_error = 1;
3478                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3479                         }
3480                         spin_unlock(&np->lock);
3481                         break;
3482                 }
3483                 if (unlikely(i > max_interrupt_work)) {
3484                         spin_lock(&np->lock);
3485                         /* disable interrupts on the nic */
3486                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3487                                 writel(0, base + NvRegIrqMask);
3488                         else
3489                                 writel(np->irqmask, base + NvRegIrqMask);
3490                         pci_push(base);
3491
3492                         if (!np->in_shutdown) {
3493                                 np->nic_poll_irq = np->irqmask;
3494                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3495                         }
3496                         spin_unlock(&np->lock);
3497                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3498                         break;
3499                 }
3500
3501         }
3502         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3503
3504         return IRQ_RETVAL(i);
3505 }
3506
3507 /**
3508  * All _optimized functions are used to help increase performance
3509  * (reduce CPU and increase throughput). They use descripter version 3,
3510  * compiler directives, and reduce memory accesses.
3511  */
3512 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3513 {
3514         struct net_device *dev = (struct net_device *) data;
3515         struct fe_priv *np = netdev_priv(dev);
3516         u8 __iomem *base = get_hwbase(dev);
3517         u32 events;
3518         int i;
3519
3520         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3521
3522         for (i=0; ; i++) {
3523                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3524                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3525                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3526                 } else {
3527                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3528                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3529                 }
3530                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3531                 if (!(events & np->irqmask))
3532                         break;
3533
3534                 nv_msi_workaround(np);
3535
3536                 spin_lock(&np->lock);
3537                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3538                 spin_unlock(&np->lock);
3539
3540 #ifdef CONFIG_FORCEDETH_NAPI
3541                 if (events & NVREG_IRQ_RX_ALL) {
3542                         spin_lock(&np->lock);
3543                         napi_schedule(&np->napi);
3544
3545                         /* Disable furthur receive irq's */
3546                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
3547
3548                         if (np->msi_flags & NV_MSI_X_ENABLED)
3549                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3550                         else
3551                                 writel(np->irqmask, base + NvRegIrqMask);
3552                         spin_unlock(&np->lock);
3553                 }
3554 #else
3555                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3556                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3557                                 spin_lock(&np->lock);
3558                                 if (!np->in_shutdown)
3559                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3560                                 spin_unlock(&np->lock);
3561                         }
3562                 }
3563 #endif
3564                 if (unlikely(events & NVREG_IRQ_LINK)) {
3565                         spin_lock(&np->lock);
3566                         nv_link_irq(dev);
3567                         spin_unlock(&np->lock);
3568                 }
3569                 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3570                         spin_lock(&np->lock);
3571                         nv_linkchange(dev);
3572                         spin_unlock(&np->lock);
3573                         np->link_timeout = jiffies + LINK_TIMEOUT;
3574                 }
3575                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3576                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3577                                                 dev->name, events);
3578                 }
3579                 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3580                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3581                                                 dev->name, events);
3582                 }
3583                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3584                         spin_lock(&np->lock);
3585                         /* disable interrupts on the nic */
3586                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3587                                 writel(0, base + NvRegIrqMask);
3588                         else
3589                                 writel(np->irqmask, base + NvRegIrqMask);
3590                         pci_push(base);
3591
3592                         if (!np->in_shutdown) {
3593                                 np->nic_poll_irq = np->irqmask;
3594                                 np->recover_error = 1;
3595                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3596                         }
3597                         spin_unlock(&np->lock);
3598                         break;
3599                 }
3600
3601                 if (unlikely(i > max_interrupt_work)) {
3602                         spin_lock(&np->lock);
3603                         /* disable interrupts on the nic */
3604                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3605                                 writel(0, base + NvRegIrqMask);
3606                         else
3607                                 writel(np->irqmask, base + NvRegIrqMask);
3608                         pci_push(base);
3609
3610                         if (!np->in_shutdown) {
3611                                 np->nic_poll_irq = np->irqmask;
3612                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3613                         }
3614                         spin_unlock(&np->lock);
3615                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3616                         break;
3617                 }
3618
3619         }
3620         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3621
3622         return IRQ_RETVAL(i);
3623 }
3624
3625 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3626 {
3627         struct net_device *dev = (struct net_device *) data;
3628         struct fe_priv *np = netdev_priv(dev);
3629         u8 __iomem *base = get_hwbase(dev);
3630         u32 events;
3631         int i;
3632         unsigned long flags;
3633
3634         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3635
3636         for (i=0; ; i++) {
3637                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3638                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3639                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3640                 if (!(events & np->irqmask))
3641                         break;
3642
3643                 spin_lock_irqsave(&np->lock, flags);
3644                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3645                 spin_unlock_irqrestore(&np->lock, flags);
3646
3647                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3648                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3649                                                 dev->name, events);
3650                 }
3651                 if (unlikely(i > max_interrupt_work)) {
3652                         spin_lock_irqsave(&np->lock, flags);
3653                         /* disable interrupts on the nic */
3654                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3655                         pci_push(base);
3656
3657                         if (!np->in_shutdown) {
3658                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3659                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3660                         }
3661                         spin_unlock_irqrestore(&np->lock, flags);
3662                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3663                         break;
3664                 }
3665
3666         }
3667         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3668
3669         return IRQ_RETVAL(i);
3670 }
3671
3672 #ifdef CONFIG_FORCEDETH_NAPI
3673 static int nv_napi_poll(struct napi_struct *napi, int budget)
3674 {
3675         struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3676         struct net_device *dev = np->dev;
3677         u8 __iomem *base = get_hwbase(dev);
3678         unsigned long flags;
3679         int pkts, retcode;
3680
3681         if (!nv_optimized(np)) {
3682                 pkts = nv_rx_process(dev, budget);
3683                 retcode = nv_alloc_rx(dev);
3684         } else {
3685                 pkts = nv_rx_process_optimized(dev, budget);
3686                 retcode = nv_alloc_rx_optimized(dev);
3687         }
3688
3689         if (retcode) {
3690                 spin_lock_irqsave(&np->lock, flags);
3691                 if (!np->in_shutdown)
3692                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3693                 spin_unlock_irqrestore(&np->lock, flags);
3694         }
3695
3696         if (pkts < budget) {
3697                 /* re-enable receive interrupts */
3698                 spin_lock_irqsave(&np->lock, flags);
3699
3700                 __napi_complete(napi);
3701
3702                 np->irqmask |= NVREG_IRQ_RX_ALL;
3703                 if (np->msi_flags & NV_MSI_X_ENABLED)
3704                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3705                 else
3706                         writel(np->irqmask, base + NvRegIrqMask);
3707
3708                 spin_unlock_irqrestore(&np->lock, flags);
3709         }
3710         return pkts;
3711 }
3712 #endif
3713
3714 #ifdef CONFIG_FORCEDETH_NAPI
3715 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3716 {
3717         struct net_device *dev = (struct net_device *) data;
3718         struct fe_priv *np = netdev_priv(dev);
3719         u8 __iomem *base = get_hwbase(dev);
3720         u32 events;
3721
3722         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3723
3724         if (events) {
3725                 /* disable receive interrupts on the nic */
3726                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3727                 pci_push(base);
3728                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3729                 napi_schedule(&np->napi);
3730         }
3731         return IRQ_HANDLED;
3732 }
3733 #else
3734 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3735 {
3736         struct net_device *dev = (struct net_device *) data;
3737         struct fe_priv *np = netdev_priv(dev);
3738         u8 __iomem *base = get_hwbase(dev);
3739         u32 events;
3740         int i;
3741         unsigned long flags;
3742
3743         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3744
3745         for (i=0; ; i++) {
3746                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3747                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3748                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3749                 if (!(events & np->irqmask))
3750                         break;
3751
3752                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3753                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3754                                 spin_lock_irqsave(&np->lock, flags);
3755                                 if (!np->in_shutdown)
3756                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3757                                 spin_unlock_irqrestore(&np->lock, flags);
3758                         }
3759                 }
3760
3761                 if (unlikely(i > max_interrupt_work)) {
3762                         spin_lock_irqsave(&np->lock, flags);
3763                         /* disable interrupts on the nic */
3764                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3765                         pci_push(base);
3766
3767                         if (!np->in_shutdown) {
3768                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3769                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3770                         }
3771                         spin_unlock_irqrestore(&np->lock, flags);
3772                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3773                         break;
3774                 }
3775         }
3776         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3777
3778         return IRQ_RETVAL(i);
3779 }
3780 #endif
3781
3782 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3783 {
3784         struct net_device *dev = (struct net_device *) data;
3785         struct fe_priv *np = netdev_priv(dev);
3786         u8 __iomem *base = get_hwbase(dev);
3787         u32 events;
3788         int i;
3789         unsigned long flags;
3790
3791         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3792
3793         for (i=0; ; i++) {
3794                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3795                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3796                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3797                 if (!(events & np->irqmask))
3798                         break;
3799
3800                 /* check tx in case we reached max loop limit in tx isr */
3801                 spin_lock_irqsave(&np->lock, flags);
3802                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3803                 spin_unlock_irqrestore(&np->lock, flags);
3804
3805                 if (events & NVREG_IRQ_LINK) {
3806                         spin_lock_irqsave(&np->lock, flags);
3807                         nv_link_irq(dev);
3808                         spin_unlock_irqrestore(&np->lock, flags);
3809                 }
3810                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3811                         spin_lock_irqsave(&np->lock, flags);
3812                         nv_linkchange(dev);
3813                         spin_unlock_irqrestore(&np->lock, flags);
3814                         np->link_timeout = jiffies + LINK_TIMEOUT;
3815                 }
3816                 if (events & NVREG_IRQ_RECOVER_ERROR) {
3817                         spin_lock_irq(&np->lock);
3818                         /* disable interrupts on the nic */
3819                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3820                         pci_push(base);
3821
3822                         if (!np->in_shutdown) {
3823                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3824                                 np->recover_error = 1;
3825                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3826                         }
3827                         spin_unlock_irq(&np->lock);
3828                         break;
3829                 }
3830                 if (events & (NVREG_IRQ_UNKNOWN)) {
3831                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3832                                                 dev->name, events);
3833                 }
3834                 if (unlikely(i > max_interrupt_work)) {
3835                         spin_lock_irqsave(&np->lock, flags);
3836                         /* disable interrupts on the nic */
3837                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3838                         pci_push(base);
3839
3840                         if (!np->in_shutdown) {
3841                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3842                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3843                         }
3844                         spin_unlock_irqrestore(&np->lock, flags);
3845                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3846                         break;
3847                 }
3848
3849         }
3850         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3851
3852         return IRQ_RETVAL(i);
3853 }
3854
3855 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3856 {
3857         struct net_device *dev = (struct net_device *) data;
3858         struct fe_priv *np = netdev_priv(dev);
3859         u8 __iomem *base = get_hwbase(dev);
3860         u32 events;
3861
3862         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3863
3864         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3865                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3866                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3867         } else {
3868                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3869                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3870         }
3871         pci_push(base);
3872         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3873         if (!(events & NVREG_IRQ_TIMER))
3874                 return IRQ_RETVAL(0);
3875
3876         nv_msi_workaround(np);
3877
3878         spin_lock(&np->lock);
3879         np->intr_test = 1;
3880         spin_unlock(&np->lock);
3881
3882         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3883
3884         return IRQ_RETVAL(1);
3885 }
3886
3887 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3888 {
3889         u8 __iomem *base = get_hwbase(dev);
3890         int i;
3891         u32 msixmap = 0;
3892
3893         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3894          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3895          * the remaining 8 interrupts.
3896          */
3897         for (i = 0; i < 8; i++) {
3898                 if ((irqmask >> i) & 0x1) {
3899                         msixmap |= vector << (i << 2);
3900                 }
3901         }
3902         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3903
3904         msixmap = 0;
3905         for (i = 0; i < 8; i++) {
3906                 if ((irqmask >> (i + 8)) & 0x1) {
3907                         msixmap |= vector << (i << 2);
3908                 }
3909         }
3910         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3911 }
3912
3913 static int nv_request_irq(struct net_device *dev, int intr_test)
3914 {
3915         struct fe_priv *np = get_nvpriv(dev);
3916         u8 __iomem *base = get_hwbase(dev);
3917         int ret = 1;
3918         int i;
3919         irqreturn_t (*handler)(int foo, void *data);
3920
3921         if (intr_test) {
3922                 handler = nv_nic_irq_test;
3923         } else {
3924                 if (nv_optimized(np))
3925                         handler = nv_nic_irq_optimized;
3926                 else
3927                         handler = nv_nic_irq;
3928         }
3929
3930         if (np->msi_flags & NV_MSI_X_CAPABLE) {
3931                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3932                         np->msi_x_entry[i].entry = i;
3933                 }
3934                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3935                         np->msi_flags |= NV_MSI_X_ENABLED;
3936                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3937                                 /* Request irq for rx handling */
3938                                 sprintf(np->name_rx, "%s-rx", dev->name);
3939                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3940                                                 &nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
3941                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3942                                         pci_disable_msix(np->pci_dev);
3943                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3944                                         goto out_err;
3945                                 }
3946                                 /* Request irq for tx handling */
3947                                 sprintf(np->name_tx, "%s-tx", dev->name);
3948                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
3949                                                 &nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
3950                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3951                                         pci_disable_msix(np->pci_dev);
3952                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3953                                         goto out_free_rx;
3954                                 }
3955                                 /* Request irq for link and timer handling */
3956                                 sprintf(np->name_other, "%s-other", dev->name);
3957                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
3958                                                 &nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
3959                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
3960                                         pci_disable_msix(np->pci_dev);
3961                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3962                                         goto out_free_tx;
3963                                 }
3964                                 /* map interrupts to their respective vector */
3965                                 writel(0, base + NvRegMSIXMap0);
3966                                 writel(0, base + NvRegMSIXMap1);
3967                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3968                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3969                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3970                         } else {
3971                                 /* Request irq for all interrupts */
3972                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3973                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3974                                         pci_disable_msix(np->pci_dev);
3975                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3976                                         goto out_err;
3977                                 }
3978
3979                                 /* map interrupts to vector 0 */
3980                                 writel(0, base + NvRegMSIXMap0);
3981                                 writel(0, base + NvRegMSIXMap1);
3982                         }
3983                 }
3984         }
3985         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3986                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
3987                         np->msi_flags |= NV_MSI_ENABLED;
3988                         dev->irq = np->pci_dev->irq;
3989                         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3990                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3991                                 pci_disable_msi(np->pci_dev);
3992                                 np->msi_flags &= ~NV_MSI_ENABLED;
3993                                 dev->irq = np->pci_dev->irq;
3994                                 goto out_err;
3995                         }
3996
3997                         /* map interrupts to vector 0 */
3998                         writel(0, base + NvRegMSIMap0);
3999                         writel(0, base + NvRegMSIMap1);
4000                         /* enable msi vector 0 */
4001                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
4002                 }
4003         }
4004         if (ret != 0) {
4005                 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
4006                         goto out_err;
4007
4008         }
4009
4010         return 0;
4011 out_free_tx:
4012         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
4013 out_free_rx:
4014         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
4015 out_err:
4016         return 1;
4017 }
4018
4019 static void nv_free_irq(struct net_device *dev)
4020 {
4021         struct fe_priv *np = get_nvpriv(dev);
4022         int i;
4023
4024         if (np->msi_flags & NV_MSI_X_ENABLED) {
4025                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
4026                         free_irq(np->msi_x_entry[i].vector, dev);
4027                 }
4028                 pci_disable_msix(np->pci_dev);
4029                 np->msi_flags &= ~NV_MSI_X_ENABLED;
4030         } else {
4031                 free_irq(np->pci_dev->irq, dev);
4032                 if (np->msi_flags & NV_MSI_ENABLED) {
4033                         pci_disable_msi(np->pci_dev);
4034                         np->msi_flags &= ~NV_MSI_ENABLED;
4035                 }
4036         }
4037 }
4038
4039 static void nv_do_nic_poll(unsigned long data)
4040 {
4041         struct net_device *dev = (struct net_device *) data;
4042         struct fe_priv *np = netdev_priv(dev);
4043         u8 __iomem *base = get_hwbase(dev);
4044         u32 mask = 0;
4045
4046         /*
4047          * First disable irq(s) and then
4048          * reenable interrupts on the nic, we have to do this before calling
4049          * nv_nic_irq because that may decide to do otherwise
4050          */
4051
4052         if (!using_multi_irqs(dev)) {
4053                 if (np->msi_flags & NV_MSI_X_ENABLED)
4054                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4055                 else
4056                         disable_irq_lockdep(np->pci_dev->irq);
4057                 mask = np->irqmask;
4058         } else {
4059                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4060                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4061                         mask |= NVREG_IRQ_RX_ALL;
4062                 }
4063                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4064                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4065                         mask |= NVREG_IRQ_TX_ALL;
4066                 }
4067                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4068                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4069                         mask |= NVREG_IRQ_OTHER;
4070                 }
4071         }
4072         /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
4073
4074         if (np->recover_error) {
4075                 np->recover_error = 0;
4076                 printk(KERN_INFO "%s: MAC in recoverable error state\n", dev->name);
4077                 if (netif_running(dev)) {
4078                         netif_tx_lock_bh(dev);
4079                         netif_addr_lock(dev);
4080                         spin_lock(&np->lock);
4081                         /* stop engines */
4082                         nv_stop_rxtx(dev);
4083                         if (np->driver_data & DEV_HAS_POWER_CNTRL)
4084                                 nv_mac_reset(dev);
4085                         nv_txrx_reset(dev);
4086                         /* drain rx queue */
4087                         nv_drain_rxtx(dev);
4088                         /* reinit driver view of the rx queue */
4089                         set_bufsize(dev);
4090                         if (nv_init_ring(dev)) {
4091                                 if (!np->in_shutdown)
4092                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4093                         }
4094                         /* reinit nic view of the rx queue */
4095                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4096                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4097                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4098                                 base + NvRegRingSizes);
4099                         pci_push(base);
4100                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4101                         pci_push(base);
4102                         /* clear interrupts */
4103                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4104                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4105                         else
4106                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4107
4108                         /* restart rx engine */
4109                         nv_start_rxtx(dev);
4110                         spin_unlock(&np->lock);
4111                         netif_addr_unlock(dev);
4112                         netif_tx_unlock_bh(dev);
4113                 }
4114         }
4115
4116         writel(mask, base + NvRegIrqMask);
4117         pci_push(base);
4118
4119         if (!using_multi_irqs(dev)) {
4120                 np->nic_poll_irq = 0;
4121                 if (nv_optimized(np))
4122                         nv_nic_irq_optimized(0, dev);
4123                 else
4124                         nv_nic_irq(0, dev);
4125                 if (np->msi_flags & NV_MSI_X_ENABLED)
4126                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4127                 else
4128                         enable_irq_lockdep(np->pci_dev->irq);
4129         } else {
4130                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4131                         np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
4132                         nv_nic_irq_rx(0, dev);
4133                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4134                 }
4135                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4136                         np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
4137                         nv_nic_irq_tx(0, dev);
4138                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4139                 }
4140                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4141                         np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
4142                         nv_nic_irq_other(0, dev);
4143                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4144                 }
4145         }
4146
4147 }
4148
4149 #ifdef CONFIG_NET_POLL_CONTROLLER
4150 static void nv_poll_controller(struct net_device *dev)
4151 {
4152         nv_do_nic_poll((unsigned long) dev);
4153 }
4154 #endif
4155
4156 static void nv_do_stats_poll(unsigned long data)
4157 {
4158         struct net_device *dev = (struct net_device *) data;
4159         struct fe_priv *np = netdev_priv(dev);
4160
4161         nv_get_hw_stats(dev);
4162
4163         if (!np->in_shutdown)
4164                 mod_timer(&np->stats_poll,
4165                         round_jiffies(jiffies + STATS_INTERVAL));
4166 }
4167
4168 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4169 {
4170         struct fe_priv *np = netdev_priv(dev);
4171         strcpy(info->driver, DRV_NAME);
4172         strcpy(info->version, FORCEDETH_VERSION);
4173         strcpy(info->bus_info, pci_name(np->pci_dev));
4174 }
4175
4176 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4177 {
4178         struct fe_priv *np = netdev_priv(dev);
4179         wolinfo->supported = WAKE_MAGIC;
4180
4181         spin_lock_irq(&np->lock);
4182         if (np->wolenabled)
4183                 wolinfo->wolopts = WAKE_MAGIC;
4184         spin_unlock_irq(&np->lock);
4185 }
4186
4187 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4188 {
4189         struct fe_priv *np = netdev_priv(dev);
4190         u8 __iomem *base = get_hwbase(dev);
4191         u32 flags = 0;
4192
4193         if (wolinfo->wolopts == 0) {
4194                 np->wolenabled = 0;
4195         } else if (wolinfo->wolopts & WAKE_MAGIC) {
4196                 np->wolenabled = 1;
4197                 flags = NVREG_WAKEUPFLAGS_ENABLE;
4198         }
4199         if (netif_running(dev)) {
4200                 spin_lock_irq(&np->lock);
4201                 writel(flags, base + NvRegWakeUpFlags);
4202                 spin_unlock_irq(&np->lock);
4203         }
4204         return 0;
4205 }
4206
4207 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4208 {
4209         struct fe_priv *np = netdev_priv(dev);
4210         int adv;
4211
4212         spin_lock_irq(&np->lock);
4213         ecmd->port = PORT_MII;
4214         if (!netif_running(dev)) {
4215                 /* We do not track link speed / duplex setting if the
4216                  * interface is disabled. Force a link check */
4217                 if (nv_update_linkspeed(dev)) {
4218                         if (!netif_carrier_ok(dev))
4219                                 netif_carrier_on(dev);
4220                 } else {
4221                         if (netif_carrier_ok(dev))
4222                                 netif_carrier_off(dev);
4223                 }
4224         }
4225
4226         if (netif_carrier_ok(dev)) {
4227                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4228                 case NVREG_LINKSPEED_10:
4229                         ecmd->speed = SPEED_10;
4230                         break;
4231                 case NVREG_LINKSPEED_100:
4232                         ecmd->speed = SPEED_100;
4233                         break;
4234                 case NVREG_LINKSPEED_1000:
4235                         ecmd->speed = SPEED_1000;
4236                         break;
4237                 }
4238                 ecmd->duplex = DUPLEX_HALF;
4239                 if (np->duplex)
4240                         ecmd->duplex = DUPLEX_FULL;
4241         } else {
4242                 ecmd->speed = -1;
4243                 ecmd->duplex = -1;
4244         }
4245
4246         ecmd->autoneg = np->autoneg;
4247
4248         ecmd->advertising = ADVERTISED_MII;
4249         if (np->autoneg) {
4250                 ecmd->advertising |= ADVERTISED_Autoneg;
4251                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4252                 if (adv & ADVERTISE_10HALF)
4253                         ecmd->advertising |= ADVERTISED_10baseT_Half;
4254                 if (adv & ADVERTISE_10FULL)
4255                         ecmd->advertising |= ADVERTISED_10baseT_Full;
4256                 if (adv & ADVERTISE_100HALF)
4257                         ecmd->advertising |= ADVERTISED_100baseT_Half;
4258                 if (adv & ADVERTISE_100FULL)
4259                         ecmd->advertising |= ADVERTISED_100baseT_Full;
4260                 if (np->gigabit == PHY_GIGABIT) {
4261                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4262                         if (adv & ADVERTISE_1000FULL)
4263                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4264                 }
4265         }
4266         ecmd->supported = (SUPPORTED_Autoneg |
4267                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4268                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4269                 SUPPORTED_MII);
4270         if (np->gigabit == PHY_GIGABIT)
4271                 ecmd->supported |= SUPPORTED_1000baseT_Full;
4272
4273         ecmd->phy_address = np->phyaddr;
4274         ecmd->transceiver = XCVR_EXTERNAL;
4275
4276         /* ignore maxtxpkt, maxrxpkt for now */
4277         spin_unlock_irq(&np->lock);
4278         return 0;
4279 }
4280
4281 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4282 {
4283         struct fe_priv *np = netdev_priv(dev);
4284
4285         if (ecmd->port != PORT_MII)
4286                 return -EINVAL;
4287         if (ecmd->transceiver != XCVR_EXTERNAL)
4288                 return -EINVAL;
4289         if (ecmd->phy_address != np->phyaddr) {
4290                 /* TODO: support switching between multiple phys. Should be
4291                  * trivial, but not enabled due to lack of test hardware. */
4292                 return -EINVAL;
4293         }
4294         if (ecmd->autoneg == AUTONEG_ENABLE) {
4295                 u32 mask;
4296
4297                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4298                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4299                 if (np->gigabit == PHY_GIGABIT)
4300                         mask |= ADVERTISED_1000baseT_Full;
4301
4302                 if ((ecmd->advertising & mask) == 0)
4303                         return -EINVAL;
4304
4305         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4306                 /* Note: autonegotiation disable, speed 1000 intentionally
4307                  * forbidden - noone should need that. */
4308
4309                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4310                         return -EINVAL;
4311                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4312                         return -EINVAL;
4313         } else {
4314                 return -EINVAL;
4315         }
4316
4317         netif_carrier_off(dev);
4318         if (netif_running(dev)) {
4319                 unsigned long flags;
4320
4321                 nv_disable_irq(dev);
4322                 netif_tx_lock_bh(dev);
4323                 netif_addr_lock(dev);
4324                 /* with plain spinlock lockdep complains */
4325                 spin_lock_irqsave(&np->lock, flags);
4326                 /* stop engines */
4327                 /* FIXME:
4328                  * this can take some time, and interrupts are disabled
4329                  * due to spin_lock_irqsave, but let's hope no daemon
4330                  * is going to change the settings very often...
4331                  * Worst case:
4332                  * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4333                  * + some minor delays, which is up to a second approximately
4334                  */
4335                 nv_stop_rxtx(dev);
4336                 spin_unlock_irqrestore(&np->lock, flags);
4337                 netif_addr_unlock(dev);
4338                 netif_tx_unlock_bh(dev);
4339         }
4340
4341         if (ecmd->autoneg == AUTONEG_ENABLE) {
4342                 int adv, bmcr;
4343
4344                 np->autoneg = 1;
4345
4346                 /* advertise only what has been requested */
4347                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4348                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4349                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4350                         adv |= ADVERTISE_10HALF;
4351                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4352                         adv |= ADVERTISE_10FULL;
4353                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4354                         adv |= ADVERTISE_100HALF;
4355                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4356                         adv |= ADVERTISE_100FULL;
4357                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
4358                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4359                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4360                         adv |=  ADVERTISE_PAUSE_ASYM;
4361                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4362
4363                 if (np->gigabit == PHY_GIGABIT) {
4364                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4365                         adv &= ~ADVERTISE_1000FULL;
4366                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4367                                 adv |= ADVERTISE_1000FULL;
4368                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4369                 }
4370
4371                 if (netif_running(dev))
4372                         printk(KERN_INFO "%s: link down.\n", dev->name);
4373                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4374                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4375                         bmcr |= BMCR_ANENABLE;
4376                         /* reset the phy in order for settings to stick,
4377                          * and cause autoneg to start */
4378                         if (phy_reset(dev, bmcr)) {
4379                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4380                                 return -EINVAL;
4381                         }
4382                 } else {
4383                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4384                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4385                 }
4386         } else {
4387                 int adv, bmcr;
4388
4389                 np->autoneg = 0;
4390
4391                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4392                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4393                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4394                         adv |= ADVERTISE_10HALF;
4395                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4396                         adv |= ADVERTISE_10FULL;
4397                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4398                         adv |= ADVERTISE_100HALF;
4399                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4400                         adv |= ADVERTISE_100FULL;
4401                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4402                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4403                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4404                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4405                 }
4406                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4407                         adv |=  ADVERTISE_PAUSE_ASYM;
4408                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4409                 }
4410                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4411                 np->fixed_mode = adv;
4412
4413                 if (np->gigabit == PHY_GIGABIT) {
4414                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4415                         adv &= ~ADVERTISE_1000FULL;
4416                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4417                 }
4418
4419                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4420                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4421                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4422                         bmcr |= BMCR_FULLDPLX;
4423                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4424                         bmcr |= BMCR_SPEED100;
4425                 if (np->phy_oui == PHY_OUI_MARVELL) {
4426                         /* reset the phy in order for forced mode settings to stick */
4427                         if (phy_reset(dev, bmcr)) {
4428                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4429                                 return -EINVAL;
4430                         }
4431                 } else {
4432                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4433                         if (netif_running(dev)) {
4434                                 /* Wait a bit and then reconfigure the nic. */
4435                                 udelay(10);
4436                                 nv_linkchange(dev);
4437                         }
4438                 }
4439         }
4440
4441         if (netif_running(dev)) {
4442                 nv_start_rxtx(dev);
4443                 nv_enable_irq(dev);
4444         }
4445
4446         return 0;
4447 }
4448
4449 #define FORCEDETH_REGS_VER      1
4450
4451 static int nv_get_regs_len(struct net_device *dev)
4452 {
4453         struct fe_priv *np = netdev_priv(dev);
4454         return np->register_size;
4455 }
4456
4457 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4458 {
4459         struct fe_priv *np = netdev_priv(dev);
4460         u8 __iomem *base = get_hwbase(dev);
4461         u32 *rbuf = buf;
4462         int i;
4463
4464         regs->version = FORCEDETH_REGS_VER;
4465         spin_lock_irq(&np->lock);
4466         for (i = 0;i <= np->register_size/sizeof(u32); i++)
4467                 rbuf[i] = readl(base + i*sizeof(u32));
4468         spin_unlock_irq(&np->lock);
4469 }
4470
4471 static int nv_nway_reset(struct net_device *dev)
4472 {
4473         struct fe_priv *np = netdev_priv(dev);
4474         int ret;
4475
4476         if (np->autoneg) {
4477                 int bmcr;
4478
4479                 netif_carrier_off(dev);
4480                 if (netif_running(dev)) {
4481                         nv_disable_irq(dev);
4482                         netif_tx_lock_bh(dev);
4483                         netif_addr_lock(dev);
4484                         spin_lock(&np->lock);
4485                         /* stop engines */
4486                         nv_stop_rxtx(dev);
4487                         spin_unlock(&np->lock);
4488                         netif_addr_unlock(dev);
4489                         netif_tx_unlock_bh(dev);
4490                         printk(KERN_INFO "%s: link down.\n", dev->name);
4491                 }
4492
4493                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4494                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4495                         bmcr |= BMCR_ANENABLE;
4496                         /* reset the phy in order for settings to stick*/
4497                         if (phy_reset(dev, bmcr)) {
4498                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4499                                 return -EINVAL;
4500                         }
4501                 } else {
4502                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4503                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4504                 }
4505
4506                 if (netif_running(dev)) {
4507                         nv_start_rxtx(dev);
4508                         nv_enable_irq(dev);
4509                 }
4510                 ret = 0;
4511         } else {
4512                 ret = -EINVAL;
4513         }
4514
4515         return ret;
4516 }
4517
4518 static int nv_set_tso(struct net_device *dev, u32 value)
4519 {
4520         struct fe_priv *np = netdev_priv(dev);
4521
4522         if ((np->driver_data & DEV_HAS_CHECKSUM))
4523                 return ethtool_op_set_tso(dev, value);
4524         else
4525                 return -EOPNOTSUPP;
4526 }
4527
4528 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4529 {
4530         struct fe_priv *np = netdev_priv(dev);
4531
4532         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4533         ring->rx_mini_max_pending = 0;
4534         ring->rx_jumbo_max_pending = 0;
4535         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4536
4537         ring->rx_pending = np->rx_ring_size;
4538         ring->rx_mini_pending = 0;
4539         ring->rx_jumbo_pending = 0;
4540         ring->tx_pending = np->tx_ring_size;
4541 }
4542
4543 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4544 {
4545         struct fe_priv *np = netdev_priv(dev);
4546         u8 __iomem *base = get_hwbase(dev);
4547         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4548         dma_addr_t ring_addr;
4549
4550         if (ring->rx_pending < RX_RING_MIN ||
4551             ring->tx_pending < TX_RING_MIN ||
4552             ring->rx_mini_pending != 0 ||
4553             ring->rx_jumbo_pending != 0 ||
4554             (np->desc_ver == DESC_VER_1 &&
4555              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4556               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4557             (np->desc_ver != DESC_VER_1 &&
4558              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4559               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4560                 return -EINVAL;
4561         }
4562
4563         /* allocate new rings */
4564         if (!nv_optimized(np)) {
4565                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4566                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4567                                             &ring_addr);
4568         } else {
4569                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4570                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4571                                             &ring_addr);
4572         }
4573         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4574         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4575         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4576                 /* fall back to old rings */
4577                 if (!nv_optimized(np)) {
4578                         if (rxtx_ring)
4579                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4580                                                     rxtx_ring, ring_addr);
4581                 } else {
4582                         if (rxtx_ring)
4583                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4584                                                     rxtx_ring, ring_addr);
4585                 }
4586                 if (rx_skbuff)
4587                         kfree(rx_skbuff);
4588                 if (tx_skbuff)
4589                         kfree(tx_skbuff);
4590                 goto exit;
4591         }
4592
4593         if (netif_running(dev)) {
4594                 nv_disable_irq(dev);
4595                 netif_tx_lock_bh(dev);
4596                 netif_addr_lock(dev);
4597                 spin_lock(&np->lock);
4598                 /* stop engines */
4599                 nv_stop_rxtx(dev);
4600                 nv_txrx_reset(dev);
4601                 /* drain queues */
4602                 nv_drain_rxtx(dev);
4603                 /* delete queues */
4604                 free_rings(dev);
4605         }
4606
4607         /* set new values */
4608         np->rx_ring_size = ring->rx_pending;
4609         np->tx_ring_size = ring->tx_pending;
4610
4611         if (!nv_optimized(np)) {
4612                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4613                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4614         } else {
4615                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4616                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4617         }
4618         np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4619         np->tx_skb = (struct nv_skb_map*)tx_skbuff;
4620         np->ring_addr = ring_addr;
4621
4622         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4623         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4624
4625         if (netif_running(dev)) {
4626                 /* reinit driver view of the queues */
4627                 set_bufsize(dev);
4628                 if (nv_init_ring(dev)) {
4629                         if (!np->in_shutdown)
4630                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4631                 }
4632
4633                 /* reinit nic view of the queues */
4634                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4635                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4636                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4637                         base + NvRegRingSizes);
4638                 pci_push(base);
4639                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4640                 pci_push(base);
4641
4642                 /* restart engines */
4643                 nv_start_rxtx(dev);
4644                 spin_unlock(&np->lock);
4645                 netif_addr_unlock(dev);
4646                 netif_tx_unlock_bh(dev);
4647                 nv_enable_irq(dev);
4648         }
4649         return 0;
4650 exit:
4651         return -ENOMEM;
4652 }
4653
4654 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4655 {
4656         struct fe_priv *np = netdev_priv(dev);
4657
4658         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4659         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4660         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4661 }
4662
4663 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4664 {
4665         struct fe_priv *np = netdev_priv(dev);
4666         int adv, bmcr;
4667
4668         if ((!np->autoneg && np->duplex == 0) ||
4669             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4670                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4671                        dev->name);
4672                 return -EINVAL;
4673         }
4674         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4675                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4676                 return -EINVAL;
4677         }
4678
4679         netif_carrier_off(dev);
4680         if (netif_running(dev)) {
4681                 nv_disable_irq(dev);
4682                 netif_tx_lock_bh(dev);
4683                 netif_addr_lock(dev);
4684                 spin_lock(&np->lock);
4685                 /* stop engines */
4686                 nv_stop_rxtx(dev);
4687                 spin_unlock(&np->lock);
4688                 netif_addr_unlock(dev);
4689                 netif_tx_unlock_bh(dev);
4690         }
4691
4692         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4693         if (pause->rx_pause)
4694                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4695         if (pause->tx_pause)
4696                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4697
4698         if (np->autoneg && pause->autoneg) {
4699                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4700
4701                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4702                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4703                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4704                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4705                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4706                         adv |=  ADVERTISE_PAUSE_ASYM;
4707                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4708
4709                 if (netif_running(dev))
4710                         printk(KERN_INFO "%s: link down.\n", dev->name);
4711                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4712                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4713                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4714         } else {
4715                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4716                 if (pause->rx_pause)
4717                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4718                 if (pause->tx_pause)
4719                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4720
4721                 if (!netif_running(dev))
4722                         nv_update_linkspeed(dev);
4723                 else
4724                         nv_update_pause(dev, np->pause_flags);
4725         }
4726
4727         if (netif_running(dev)) {
4728                 nv_start_rxtx(dev);
4729                 nv_enable_irq(dev);
4730         }
4731         return 0;
4732 }
4733
4734 static u32 nv_get_rx_csum(struct net_device *dev)
4735 {
4736         struct fe_priv *np = netdev_priv(dev);
4737         return (np->rx_csum) != 0;
4738 }
4739
4740 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4741 {
4742         struct fe_priv *np = netdev_priv(dev);
4743         u8 __iomem *base = get_hwbase(dev);
4744         int retcode = 0;
4745
4746         if (np->driver_data & DEV_HAS_CHECKSUM) {
4747                 if (data) {
4748                         np->rx_csum = 1;
4749                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4750                 } else {
4751                         np->rx_csum = 0;
4752                         /* vlan is dependent on rx checksum offload */
4753                         if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4754                                 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4755                 }
4756                 if (netif_running(dev)) {
4757                         spin_lock_irq(&np->lock);
4758                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4759                         spin_unlock_irq(&np->lock);
4760                 }
4761         } else {
4762                 return -EINVAL;
4763         }
4764
4765         return retcode;
4766 }
4767
4768 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4769 {
4770         struct fe_priv *np = netdev_priv(dev);
4771
4772         if (np->driver_data & DEV_HAS_CHECKSUM)
4773                 return ethtool_op_set_tx_csum(dev, data);
4774         else
4775                 return -EOPNOTSUPP;
4776 }
4777
4778 static int nv_set_sg(struct net_device *dev, u32 data)
4779 {
4780         struct fe_priv *np = netdev_priv(dev);
4781
4782         if (np->driver_data & DEV_HAS_CHECKSUM)
4783                 return ethtool_op_set_sg(dev, data);
4784         else
4785                 return -EOPNOTSUPP;
4786 }
4787
4788 static int nv_get_sset_count(struct net_device *dev, int sset)
4789 {
4790         struct fe_priv *np = netdev_priv(dev);
4791
4792         switch (sset) {
4793         case ETH_SS_TEST:
4794                 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4795                         return NV_TEST_COUNT_EXTENDED;
4796                 else
4797                         return NV_TEST_COUNT_BASE;
4798         case ETH_SS_STATS:
4799                 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4800                         return NV_DEV_STATISTICS_V3_COUNT;
4801                 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4802                         return NV_DEV_STATISTICS_V2_COUNT;
4803                 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4804                         return NV_DEV_STATISTICS_V1_COUNT;
4805                 else
4806                         return 0;
4807         default:
4808                 return -EOPNOTSUPP;
4809         }
4810 }
4811
4812 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4813 {
4814         struct fe_priv *np = netdev_priv(dev);
4815
4816         /* update stats */
4817         nv_do_stats_poll((unsigned long)dev);
4818
4819         memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4820 }
4821
4822 static int nv_link_test(struct net_device *dev)
4823 {
4824         struct fe_priv *np = netdev_priv(dev);
4825         int mii_status;
4826
4827         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4828         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4829
4830         /* check phy link status */
4831         if (!(mii_status & BMSR_LSTATUS))
4832                 return 0;
4833         else
4834                 return 1;
4835 }
4836
4837 static int nv_register_test(struct net_device *dev)
4838 {
4839         u8 __iomem *base = get_hwbase(dev);
4840         int i = 0;
4841         u32 orig_read, new_read;
4842
4843         do {
4844                 orig_read = readl(base + nv_registers_test[i].reg);
4845
4846                 /* xor with mask to toggle bits */
4847                 orig_read ^= nv_registers_test[i].mask;
4848
4849                 writel(orig_read, base + nv_registers_test[i].reg);
4850
4851                 new_read = readl(base + nv_registers_test[i].reg);
4852
4853                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4854                         return 0;
4855
4856                 /* restore original value */
4857                 orig_read ^= nv_registers_test[i].mask;
4858                 writel(orig_read, base + nv_registers_test[i].reg);
4859
4860         } while (nv_registers_test[++i].reg != 0);
4861
4862         return 1;
4863 }
4864
4865 static int nv_interrupt_test(struct net_device *dev)
4866 {
4867         struct fe_priv *np = netdev_priv(dev);
4868         u8 __iomem *base = get_hwbase(dev);
4869         int ret = 1;
4870         int testcnt;
4871         u32 save_msi_flags, save_poll_interval = 0;
4872
4873         if (netif_running(dev)) {
4874                 /* free current irq */
4875                 nv_free_irq(dev);
4876                 save_poll_interval = readl(base+NvRegPollingInterval);
4877         }
4878
4879         /* flag to test interrupt handler */
4880         np->intr_test = 0;
4881
4882         /* setup test irq */
4883         save_msi_flags = np->msi_flags;
4884         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4885         np->msi_flags |= 0x001; /* setup 1 vector */
4886         if (nv_request_irq(dev, 1))
4887                 return 0;
4888
4889         /* setup timer interrupt */
4890         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4891         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4892
4893         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4894
4895         /* wait for at least one interrupt */
4896         msleep(100);
4897
4898         spin_lock_irq(&np->lock);
4899
4900         /* flag should be set within ISR */
4901         testcnt = np->intr_test;
4902         if (!testcnt)
4903                 ret = 2;
4904
4905         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4906         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4907                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4908         else
4909                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4910
4911         spin_unlock_irq(&np->lock);
4912
4913         nv_free_irq(dev);
4914
4915         np->msi_flags = save_msi_flags;
4916
4917         if (netif_running(dev)) {
4918                 writel(save_poll_interval, base + NvRegPollingInterval);
4919                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4920                 /* restore original irq */
4921                 if (nv_request_irq(dev, 0))
4922                         return 0;
4923         }
4924
4925         return ret;
4926 }
4927
4928 static int nv_loopback_test(struct net_device *dev)
4929 {
4930         struct fe_priv *np = netdev_priv(dev);
4931         u8 __iomem *base = get_hwbase(dev);
4932         struct sk_buff *tx_skb, *rx_skb;
4933         dma_addr_t test_dma_addr;
4934         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4935         u32 flags;
4936         int len, i, pkt_len;
4937         u8 *pkt_data;
4938         u32 filter_flags = 0;
4939         u32 misc1_flags = 0;
4940         int ret = 1;
4941
4942         if (netif_running(dev)) {
4943                 nv_disable_irq(dev);
4944                 filter_flags = readl(base + NvRegPacketFilterFlags);
4945                 misc1_flags = readl(base + NvRegMisc1);
4946         } else {
4947                 nv_txrx_reset(dev);
4948         }
4949
4950         /* reinit driver view of the rx queue */
4951         set_bufsize(dev);
4952         nv_init_ring(dev);
4953
4954         /* setup hardware for loopback */
4955         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4956         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4957
4958         /* reinit nic view of the rx queue */
4959         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4960         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4961         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4962                 base + NvRegRingSizes);
4963         pci_push(base);
4964
4965         /* restart rx engine */
4966         nv_start_rxtx(dev);
4967
4968         /* setup packet for tx */
4969         pkt_len = ETH_DATA_LEN;
4970         tx_skb = dev_alloc_skb(pkt_len);
4971         if (!tx_skb) {
4972                 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
4973                          " of %s\n", dev->name);
4974                 ret = 0;
4975                 goto out;
4976         }
4977         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4978                                        skb_tailroom(tx_skb),
4979                                        PCI_DMA_FROMDEVICE);
4980         pkt_data = skb_put(tx_skb, pkt_len);
4981         for (i = 0; i < pkt_len; i++)
4982                 pkt_data[i] = (u8)(i & 0xff);
4983
4984         if (!nv_optimized(np)) {
4985                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4986                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4987         } else {
4988                 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4989                 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
4990                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4991         }
4992         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4993         pci_push(get_hwbase(dev));
4994
4995         msleep(500);
4996
4997         /* check for rx of the packet */
4998         if (!nv_optimized(np)) {
4999                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
5000                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
5001
5002         } else {
5003                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
5004                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
5005         }
5006
5007         if (flags & NV_RX_AVAIL) {
5008                 ret = 0;
5009         } else if (np->desc_ver == DESC_VER_1) {
5010                 if (flags & NV_RX_ERROR)
5011                         ret = 0;
5012         } else {
5013                 if (flags & NV_RX2_ERROR) {
5014                         ret = 0;
5015                 }
5016         }
5017
5018         if (ret) {
5019                 if (len != pkt_len) {
5020                         ret = 0;
5021                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
5022                                 dev->name, len, pkt_len);
5023                 } else {
5024                         rx_skb = np->rx_skb[0].skb;
5025                         for (i = 0; i < pkt_len; i++) {
5026                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
5027                                         ret = 0;
5028                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
5029                                                 dev->name, i);
5030                                         break;
5031                                 }
5032                         }
5033                 }
5034         } else {
5035                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
5036         }
5037
5038         pci_unmap_page(np->pci_dev, test_dma_addr,
5039                        (skb_end_pointer(tx_skb) - tx_skb->data),
5040                        PCI_DMA_TODEVICE);
5041         dev_kfree_skb_any(tx_skb);
5042  out:
5043         /* stop engines */
5044         nv_stop_rxtx(dev);
5045         nv_txrx_reset(dev);
5046         /* drain rx queue */
5047         nv_drain_rxtx(dev);
5048
5049         if (netif_running(dev)) {
5050                 writel(misc1_flags, base + NvRegMisc1);
5051                 writel(filter_flags, base + NvRegPacketFilterFlags);
5052                 nv_enable_irq(dev);
5053         }
5054
5055         return ret;
5056 }
5057
5058 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
5059 {
5060         struct fe_priv *np = netdev_priv(dev);
5061         u8 __iomem *base = get_hwbase(dev);
5062         int result;
5063         memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
5064
5065         if (!nv_link_test(dev)) {
5066                 test->flags |= ETH_TEST_FL_FAILED;
5067                 buffer[0] = 1;
5068         }
5069
5070         if (test->flags & ETH_TEST_FL_OFFLINE) {
5071                 if (netif_running(dev)) {
5072                         netif_stop_queue(dev);
5073 #ifdef CONFIG_FORCEDETH_NAPI
5074                         napi_disable(&np->napi);
5075 #endif
5076                         netif_tx_lock_bh(dev);
5077                         netif_addr_lock(dev);
5078                         spin_lock_irq(&np->lock);
5079                         nv_disable_hw_interrupts(dev, np->irqmask);
5080                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
5081                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5082                         } else {
5083                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5084                         }
5085                         /* stop engines */
5086                         nv_stop_rxtx(dev);
5087                         nv_txrx_reset(dev);
5088                         /* drain rx queue */
5089                         nv_drain_rxtx(dev);
5090                         spin_unlock_irq(&np->lock);
5091                         netif_addr_unlock(dev);
5092                         netif_tx_unlock_bh(dev);
5093                 }
5094
5095                 if (!nv_register_test(dev)) {
5096                         test->flags |= ETH_TEST_FL_FAILED;
5097                         buffer[1] = 1;
5098                 }
5099
5100                 result = nv_interrupt_test(dev);
5101                 if (result != 1) {
5102                         test->flags |= ETH_TEST_FL_FAILED;
5103                         buffer[2] = 1;
5104                 }
5105                 if (result == 0) {
5106                         /* bail out */
5107                         return;
5108                 }
5109
5110                 if (!nv_loopback_test(dev)) {
5111                         test->flags |= ETH_TEST_FL_FAILED;
5112                         buffer[3] = 1;
5113                 }
5114
5115                 if (netif_running(dev)) {
5116                         /* reinit driver view of the rx queue */
5117                         set_bufsize(dev);
5118                         if (nv_init_ring(dev)) {
5119                                 if (!np->in_shutdown)
5120                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5121                         }
5122                         /* reinit nic view of the rx queue */
5123                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5124                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5125                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5126                                 base + NvRegRingSizes);
5127                         pci_push(base);
5128                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5129                         pci_push(base);
5130                         /* restart rx engine */
5131                         nv_start_rxtx(dev);
5132                         netif_start_queue(dev);
5133 #ifdef CONFIG_FORCEDETH_NAPI
5134                         napi_enable(&np->napi);
5135 #endif
5136                         nv_enable_hw_interrupts(dev, np->irqmask);
5137                 }
5138         }
5139 }
5140
5141 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5142 {
5143         switch (stringset) {
5144         case ETH_SS_STATS:
5145                 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
5146                 break;
5147         case ETH_SS_TEST:
5148                 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
5149                 break;
5150         }
5151 }
5152
5153 static const struct ethtool_ops ops = {
5154         .get_drvinfo = nv_get_drvinfo,
5155         .get_link = ethtool_op_get_link,
5156         .get_wol = nv_get_wol,
5157         .set_wol = nv_set_wol,
5158         .get_settings = nv_get_settings,
5159         .set_settings = nv_set_settings,
5160         .get_regs_len = nv_get_regs_len,
5161         .get_regs = nv_get_regs,
5162         .nway_reset = nv_nway_reset,
5163         .set_tso = nv_set_tso,
5164         .get_ringparam = nv_get_ringparam,
5165         .set_ringparam = nv_set_ringparam,
5166         .get_pauseparam = nv_get_pauseparam,
5167         .set_pauseparam = nv_set_pauseparam,
5168         .get_rx_csum = nv_get_rx_csum,
5169         .set_rx_csum = nv_set_rx_csum,
5170         .set_tx_csum = nv_set_tx_csum,
5171         .set_sg = nv_set_sg,
5172         .get_strings = nv_get_strings,
5173         .get_ethtool_stats = nv_get_ethtool_stats,
5174         .get_sset_count = nv_get_sset_count,
5175         .self_test = nv_self_test,
5176 };
5177
5178 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
5179 {
5180         struct fe_priv *np = get_nvpriv(dev);
5181
5182         spin_lock_irq(&np->lock);
5183
5184         /* save vlan group */
5185         np->vlangrp = grp;
5186
5187         if (grp) {
5188                 /* enable vlan on MAC */
5189                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
5190         } else {
5191                 /* disable vlan on MAC */
5192                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
5193                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
5194         }
5195
5196         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5197
5198         spin_unlock_irq(&np->lock);
5199 }
5200
5201 /* The mgmt unit and driver use a semaphore to access the phy during init */
5202 static int nv_mgmt_acquire_sema(struct net_device *dev)
5203 {
5204         struct fe_priv *np = netdev_priv(dev);
5205         u8 __iomem *base = get_hwbase(dev);
5206         int i;
5207         u32 tx_ctrl, mgmt_sema;
5208
5209         for (i = 0; i < 10; i++) {
5210                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5211                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5212                         break;
5213                 msleep(500);
5214         }
5215
5216         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5217                 return 0;
5218
5219         for (i = 0; i < 2; i++) {
5220                 tx_ctrl = readl(base + NvRegTransmitterControl);
5221                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5222                 writel(tx_ctrl, base + NvRegTransmitterControl);
5223
5224                 /* verify that semaphore was acquired */
5225                 tx_ctrl = readl(base + NvRegTransmitterControl);
5226                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5227                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5228                         np->mgmt_sema = 1;
5229                         return 1;
5230                 }
5231                 else
5232                         udelay(50);
5233         }
5234
5235         return 0;
5236 }
5237
5238 static void nv_mgmt_release_sema(struct net_device *dev)
5239 {
5240         struct fe_priv *np = netdev_priv(dev);
5241         u8 __iomem *base = get_hwbase(dev);
5242         u32 tx_ctrl;
5243
5244         if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5245                 if (np->mgmt_sema) {
5246                         tx_ctrl = readl(base + NvRegTransmitterControl);
5247                         tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5248                         writel(tx_ctrl, base + NvRegTransmitterControl);
5249                 }
5250         }
5251 }
5252
5253
5254 static int nv_mgmt_get_version(struct net_device *dev)
5255 {
5256         struct fe_priv *np = netdev_priv(dev);
5257         u8 __iomem *base = get_hwbase(dev);
5258         u32 data_ready = readl(base + NvRegTransmitterControl);
5259         u32 data_ready2 = 0;
5260         unsigned long start;
5261         int ready = 0;
5262
5263         writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5264         writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5265         start = jiffies;
5266         while (time_before(jiffies, start + 5*HZ)) {
5267                 data_ready2 = readl(base + NvRegTransmitterControl);
5268                 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5269                         ready = 1;
5270                         break;
5271                 }
5272                 schedule_timeout_uninterruptible(1);
5273         }
5274
5275         if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5276                 return 0;
5277
5278         np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5279
5280         return 1;
5281 }
5282
5283 static int nv_open(struct net_device *dev)
5284 {
5285         struct fe_priv *np = netdev_priv(dev);
5286         u8 __iomem *base = get_hwbase(dev);
5287         int ret = 1;
5288         int oom, i;
5289         u32 low;
5290
5291         dprintk(KERN_DEBUG "nv_open: begin\n");
5292
5293         /* power up phy */
5294         mii_rw(dev, np->phyaddr, MII_BMCR,
5295                mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5296
5297         /* erase previous misconfiguration */
5298         if (np->driver_data & DEV_HAS_POWER_CNTRL)
5299                 nv_mac_reset(dev);
5300         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5301         writel(0, base + NvRegMulticastAddrB);
5302         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5303         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5304         writel(0, base + NvRegPacketFilterFlags);
5305
5306         writel(0, base + NvRegTransmitterControl);
5307         writel(0, base + NvRegReceiverControl);
5308
5309         writel(0, base + NvRegAdapterControl);
5310
5311         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5312                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
5313
5314         /* initialize descriptor rings */
5315         set_bufsize(dev);
5316         oom = nv_init_ring(dev);
5317
5318         writel(0, base + NvRegLinkSpeed);
5319         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5320         nv_txrx_reset(dev);
5321         writel(0, base + NvRegUnknownSetupReg6);
5322
5323         np->in_shutdown = 0;
5324
5325         /* give hw rings */
5326         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5327         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5328                 base + NvRegRingSizes);
5329
5330         writel(np->linkspeed, base + NvRegLinkSpeed);
5331         if (np->desc_ver == DESC_VER_1)
5332                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5333         else
5334                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5335         writel(np->txrxctl_bits, base + NvRegTxRxControl);
5336         writel(np->vlanctl_bits, base + NvRegVlanControl);
5337         pci_push(base);
5338         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5339         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5340                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
5341                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
5342
5343         writel(0, base + NvRegMIIMask);
5344         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5345         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5346
5347         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5348         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5349         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5350         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5351
5352         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5353
5354         get_random_bytes(&low, sizeof(low));
5355         low &= NVREG_SLOTTIME_MASK;
5356         if (np->desc_ver == DESC_VER_1) {
5357                 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5358         } else {
5359                 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5360                         /* setup legacy backoff */
5361                         writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5362                 } else {
5363                         writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5364                         nv_gear_backoff_reseed(dev);
5365                 }
5366         }
5367         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5368         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5369         if (poll_interval == -1) {
5370                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5371                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5372                 else
5373                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5374         }
5375         else
5376                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5377         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5378         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5379                         base + NvRegAdapterControl);
5380         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5381         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5382         if (np->wolenabled)
5383                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5384
5385         i = readl(base + NvRegPowerState);
5386         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
5387                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5388
5389         pci_push(base);
5390         udelay(10);
5391         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5392
5393         nv_disable_hw_interrupts(dev, np->irqmask);
5394         pci_push(base);
5395         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5396         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5397         pci_push(base);
5398
5399         if (nv_request_irq(dev, 0)) {
5400                 goto out_drain;
5401         }
5402
5403         /* ask for interrupts */
5404         nv_enable_hw_interrupts(dev, np->irqmask);
5405
5406         spin_lock_irq(&np->lock);
5407         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5408         writel(0, base + NvRegMulticastAddrB);
5409         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5410         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5411         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5412         /* One manual link speed update: Interrupts are enabled, future link
5413          * speed changes cause interrupts and are handled by nv_link_irq().
5414          */
5415         {
5416                 u32 miistat;
5417                 miistat = readl(base + NvRegMIIStatus);
5418                 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5419                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
5420         }
5421         /* set linkspeed to invalid value, thus force nv_update_linkspeed
5422          * to init hw */
5423         np->linkspeed = 0;
5424         ret = nv_update_linkspeed(dev);
5425         nv_start_rxtx(dev);
5426         netif_start_queue(dev);
5427 #ifdef CONFIG_FORCEDETH_NAPI
5428         napi_enable(&np->napi);
5429 #endif
5430
5431         if (ret) {
5432                 netif_carrier_on(dev);
5433         } else {
5434                 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
5435                 netif_carrier_off(dev);
5436         }
5437         if (oom)
5438                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5439
5440         /* start statistics timer */
5441         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5442                 mod_timer(&np->stats_poll,
5443                         round_jiffies(jiffies + STATS_INTERVAL));
5444
5445         spin_unlock_irq(&np->lock);
5446
5447         return 0;
5448 out_drain:
5449         nv_drain_rxtx(dev);
5450         return ret;
5451 }
5452
5453 static int nv_close(struct net_device *dev)
5454 {
5455         struct fe_priv *np = netdev_priv(dev);
5456         u8 __iomem *base;
5457
5458         spin_lock_irq(&np->lock);
5459         np->in_shutdown = 1;
5460         spin_unlock_irq(&np->lock);
5461 #ifdef CONFIG_FORCEDETH_NAPI
5462         napi_disable(&np->napi);
5463 #endif
5464         synchronize_irq(np->pci_dev->irq);
5465
5466         del_timer_sync(&np->oom_kick);
5467         del_timer_sync(&np->nic_poll);
5468         del_timer_sync(&np->stats_poll);
5469
5470         netif_stop_queue(dev);
5471         spin_lock_irq(&np->lock);
5472         nv_stop_rxtx(dev);
5473         nv_txrx_reset(dev);
5474
5475         /* disable interrupts on the nic or we will lock up */
5476         base = get_hwbase(dev);
5477         nv_disable_hw_interrupts(dev, np->irqmask);
5478         pci_push(base);
5479         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5480
5481         spin_unlock_irq(&np->lock);
5482
5483         nv_free_irq(dev);
5484
5485         nv_drain_rxtx(dev);
5486
5487         if (np->wolenabled) {
5488                 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5489                 nv_start_rx(dev);
5490         } else {
5491                 /* power down phy */
5492                 mii_rw(dev, np->phyaddr, MII_BMCR,
5493                        mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5494         }
5495
5496         /* FIXME: power down nic */
5497
5498         return 0;
5499 }
5500
5501 static const struct net_device_ops nv_netdev_ops = {
5502         .ndo_open               = nv_open,
5503         .ndo_stop               = nv_close,
5504         .ndo_get_stats          = nv_get_stats,
5505         .ndo_start_xmit         = nv_start_xmit,
5506         .ndo_tx_timeout         = nv_tx_timeout,
5507         .ndo_change_mtu         = nv_change_mtu,
5508         .ndo_validate_addr      = eth_validate_addr,
5509         .ndo_set_mac_address    = nv_set_mac_address,
5510         .ndo_set_multicast_list = nv_set_multicast,
5511         .ndo_vlan_rx_register   = nv_vlan_rx_register,
5512 #ifdef CONFIG_NET_POLL_CONTROLLER
5513         .ndo_poll_controller    = nv_poll_controller,
5514 #endif
5515 };
5516
5517 static const struct net_device_ops nv_netdev_ops_optimized = {
5518         .ndo_open               = nv_open,
5519         .ndo_stop               = nv_close,
5520         .ndo_get_stats          = nv_get_stats,
5521         .ndo_start_xmit         = nv_start_xmit_optimized,
5522         .ndo_tx_timeout         = nv_tx_timeout,
5523         .ndo_change_mtu         = nv_change_mtu,
5524         .ndo_validate_addr      = eth_validate_addr,
5525         .ndo_set_mac_address    = nv_set_mac_address,
5526         .ndo_set_multicast_list = nv_set_multicast,
5527         .ndo_vlan_rx_register   = nv_vlan_rx_register,
5528 #ifdef CONFIG_NET_POLL_CONTROLLER
5529         .ndo_poll_controller    = nv_poll_controller,
5530 #endif
5531 };
5532
5533 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5534 {
5535         struct net_device *dev;
5536         struct fe_priv *np;
5537         unsigned long addr;
5538         u8 __iomem *base;
5539         int err, i;
5540         u32 powerstate, txreg;
5541         u32 phystate_orig = 0, phystate;
5542         int phyinitialized = 0;
5543         static int printed_version;
5544
5545         if (!printed_version++)
5546                 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
5547                        " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
5548
5549         dev = alloc_etherdev(sizeof(struct fe_priv));
5550         err = -ENOMEM;
5551         if (!dev)
5552                 goto out;
5553
5554         np = netdev_priv(dev);
5555         np->dev = dev;
5556         np->pci_dev = pci_dev;
5557         spin_lock_init(&np->lock);
5558         SET_NETDEV_DEV(dev, &pci_dev->dev);
5559
5560         init_timer(&np->oom_kick);
5561         np->oom_kick.data = (unsigned long) dev;
5562         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
5563         init_timer(&np->nic_poll);
5564         np->nic_poll.data = (unsigned long) dev;
5565         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
5566         init_timer(&np->stats_poll);
5567         np->stats_poll.data = (unsigned long) dev;
5568         np->stats_poll.function = &nv_do_stats_poll;    /* timer handler */
5569
5570         err = pci_enable_device(pci_dev);
5571         if (err)
5572                 goto out_free;
5573
5574         pci_set_master(pci_dev);
5575
5576         err = pci_request_regions(pci_dev, DRV_NAME);
5577         if (err < 0)
5578                 goto out_disable;
5579
5580         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5581                 np->register_size = NV_PCI_REGSZ_VER3;
5582         else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5583                 np->register_size = NV_PCI_REGSZ_VER2;
5584         else
5585                 np->register_size = NV_PCI_REGSZ_VER1;
5586
5587         err = -EINVAL;
5588         addr = 0;
5589         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5590                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
5591                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
5592                                 pci_resource_len(pci_dev, i),
5593                                 pci_resource_flags(pci_dev, i));
5594                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5595                                 pci_resource_len(pci_dev, i) >= np->register_size) {
5596                         addr = pci_resource_start(pci_dev, i);
5597                         break;
5598                 }
5599         }
5600         if (i == DEVICE_COUNT_RESOURCE) {
5601                 dev_printk(KERN_INFO, &pci_dev->dev,
5602                            "Couldn't find register window\n");
5603                 goto out_relreg;
5604         }
5605
5606         /* copy of driver data */
5607         np->driver_data = id->driver_data;
5608         /* copy of device id */
5609         np->device_id = id->device;
5610
5611         /* handle different descriptor versions */
5612         if (id->driver_data & DEV_HAS_HIGH_DMA) {
5613                 /* packet format 3: supports 40-bit addressing */
5614                 np->desc_ver = DESC_VER_3;
5615                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5616                 if (dma_64bit) {
5617                         if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK))
5618                                 dev_printk(KERN_INFO, &pci_dev->dev,
5619                                         "64-bit DMA failed, using 32-bit addressing\n");
5620                         else
5621                                 dev->features |= NETIF_F_HIGHDMA;
5622                         if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
5623                                 dev_printk(KERN_INFO, &pci_dev->dev,
5624                                         "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5625                         }
5626                 }
5627         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5628                 /* packet format 2: supports jumbo frames */
5629                 np->desc_ver = DESC_VER_2;
5630                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5631         } else {
5632                 /* original packet format */
5633                 np->desc_ver = DESC_VER_1;
5634                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5635         }
5636
5637         np->pkt_limit = NV_PKTLIMIT_1;
5638         if (id->driver_data & DEV_HAS_LARGEDESC)
5639                 np->pkt_limit = NV_PKTLIMIT_2;
5640
5641         if (id->driver_data & DEV_HAS_CHECKSUM) {
5642                 np->rx_csum = 1;
5643                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5644                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
5645                 dev->features |= NETIF_F_TSO;
5646         }
5647
5648         np->vlanctl_bits = 0;
5649         if (id->driver_data & DEV_HAS_VLAN) {
5650                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5651                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5652         }
5653
5654         np->msi_flags = 0;
5655         if ((id->driver_data & DEV_HAS_MSI) && msi) {
5656                 np->msi_flags |= NV_MSI_CAPABLE;
5657         }
5658         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5659                 np->msi_flags |= NV_MSI_X_CAPABLE;
5660         }
5661
5662         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5663         if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5664             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5665             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5666                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5667         }
5668
5669
5670         err = -ENOMEM;
5671         np->base = ioremap(addr, np->register_size);
5672         if (!np->base)
5673                 goto out_relreg;
5674         dev->base_addr = (unsigned long)np->base;
5675
5676         dev->irq = pci_dev->irq;
5677
5678         np->rx_ring_size = RX_RING_DEFAULT;
5679         np->tx_ring_size = TX_RING_DEFAULT;
5680
5681         if (!nv_optimized(np)) {
5682                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5683                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5684                                         &np->ring_addr);
5685                 if (!np->rx_ring.orig)
5686                         goto out_unmap;
5687                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5688         } else {
5689                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5690                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5691                                         &np->ring_addr);
5692                 if (!np->rx_ring.ex)
5693                         goto out_unmap;
5694                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5695         }
5696         np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5697         np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5698         if (!np->rx_skb || !np->tx_skb)
5699                 goto out_freering;
5700
5701         if (!nv_optimized(np))
5702                 dev->netdev_ops = &nv_netdev_ops;
5703         else
5704                 dev->netdev_ops = &nv_netdev_ops_optimized;
5705
5706 #ifdef CONFIG_FORCEDETH_NAPI
5707         netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5708 #endif
5709         SET_ETHTOOL_OPS(dev, &ops);
5710         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5711
5712         pci_set_drvdata(pci_dev, dev);
5713
5714         /* read the mac address */
5715         base = get_hwbase(dev);
5716         np->orig_mac[0] = readl(base + NvRegMacAddrA);
5717         np->orig_mac[1] = readl(base + NvRegMacAddrB);
5718
5719         /* check the workaround bit for correct mac address order */
5720         txreg = readl(base + NvRegTransmitPoll);
5721         if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5722                 /* mac address is already in correct order */
5723                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5724                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5725                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5726                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5727                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5728                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5729         } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5730                 /* mac address is already in correct order */
5731                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5732                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5733                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5734                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5735                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5736                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5737                 /*
5738                  * Set orig mac address back to the reversed version.
5739                  * This flag will be cleared during low power transition.
5740                  * Therefore, we should always put back the reversed address.
5741                  */
5742                 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5743                         (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5744                 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5745         } else {
5746                 /* need to reverse mac address to correct order */
5747                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
5748                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
5749                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5750                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5751                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
5752                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
5753                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5754                 printk(KERN_DEBUG "nv_probe: set workaround bit for reversed mac addr\n");
5755         }
5756         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5757
5758         if (!is_valid_ether_addr(dev->perm_addr)) {
5759                 /*
5760                  * Bad mac address. At least one bios sets the mac address
5761                  * to 01:23:45:67:89:ab
5762                  */
5763                 dev_printk(KERN_ERR, &pci_dev->dev,
5764                         "Invalid Mac address detected: %pM\n",
5765                         dev->dev_addr);
5766                 dev_printk(KERN_ERR, &pci_dev->dev,
5767                         "Please complain to your hardware vendor. Switching to a random MAC.\n");
5768                 dev->dev_addr[0] = 0x00;
5769                 dev->dev_addr[1] = 0x00;
5770                 dev->dev_addr[2] = 0x6c;
5771                 get_random_bytes(&dev->dev_addr[3], 3);
5772         }
5773
5774         dprintk(KERN_DEBUG "%s: MAC Address %pM\n",
5775                 pci_name(pci_dev), dev->dev_addr);
5776
5777         /* set mac address */
5778         nv_copy_mac_to_hw(dev);
5779
5780         /* Workaround current PCI init glitch:  wakeup bits aren't
5781          * being set from PCI PM capability.
5782          */
5783         device_init_wakeup(&pci_dev->dev, 1);
5784
5785         /* disable WOL */
5786         writel(0, base + NvRegWakeUpFlags);
5787         np->wolenabled = 0;
5788
5789         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5790
5791                 /* take phy and nic out of low power mode */
5792                 powerstate = readl(base + NvRegPowerState2);
5793                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5794                 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
5795                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
5796                     pci_dev->revision >= 0xA3)
5797                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5798                 writel(powerstate, base + NvRegPowerState2);
5799         }
5800
5801         if (np->desc_ver == DESC_VER_1) {
5802                 np->tx_flags = NV_TX_VALID;
5803         } else {
5804                 np->tx_flags = NV_TX2_VALID;
5805         }
5806         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
5807                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5808                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5809                         np->msi_flags |= 0x0003;
5810         } else {
5811                 np->irqmask = NVREG_IRQMASK_CPU;
5812                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5813                         np->msi_flags |= 0x0001;
5814         }
5815
5816         if (id->driver_data & DEV_NEED_TIMERIRQ)
5817                 np->irqmask |= NVREG_IRQ_TIMER;
5818         if (id->driver_data & DEV_NEED_LINKTIMER) {
5819                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5820                 np->need_linktimer = 1;
5821                 np->link_timeout = jiffies + LINK_TIMEOUT;
5822         } else {
5823                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5824                 np->need_linktimer = 0;
5825         }
5826
5827         /* Limit the number of tx's outstanding for hw bug */
5828         if (id->driver_data & DEV_NEED_TX_LIMIT) {
5829                 np->tx_limit = 1;
5830                 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
5831                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
5832                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
5833                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
5834                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
5835                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
5836                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
5837                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_39) &&
5838                     pci_dev->revision >= 0xA2)
5839                         np->tx_limit = 0;
5840         }
5841
5842         /* clear phy state and temporarily halt phy interrupts */
5843         writel(0, base + NvRegMIIMask);
5844         phystate = readl(base + NvRegAdapterControl);
5845         if (phystate & NVREG_ADAPTCTL_RUNNING) {
5846                 phystate_orig = 1;
5847                 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5848                 writel(phystate, base + NvRegAdapterControl);
5849         }
5850         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5851
5852         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5853                 /* management unit running on the mac? */
5854                 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5855                     (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5856                     nv_mgmt_acquire_sema(dev) &&
5857                     nv_mgmt_get_version(dev)) {
5858                         np->mac_in_use = 1;
5859                         if (np->mgmt_version > 0) {
5860                                 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
5861                         }
5862                         dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n",
5863                                 pci_name(pci_dev), np->mac_in_use);
5864                         /* management unit setup the phy already? */
5865                         if (np->mac_in_use &&
5866                             ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5867                              NVREG_XMITCTL_SYNC_PHY_INIT)) {
5868                                 /* phy is inited by mgmt unit */
5869                                 phyinitialized = 1;
5870                                 dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n",
5871                                         pci_name(pci_dev));
5872                         } else {
5873                                 /* we need to init the phy */
5874                         }
5875                 }
5876         }
5877
5878         /* find a suitable phy */
5879         for (i = 1; i <= 32; i++) {
5880                 int id1, id2;
5881                 int phyaddr = i & 0x1F;
5882
5883                 spin_lock_irq(&np->lock);
5884                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5885                 spin_unlock_irq(&np->lock);
5886                 if (id1 < 0 || id1 == 0xffff)
5887                         continue;
5888                 spin_lock_irq(&np->lock);
5889                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5890                 spin_unlock_irq(&np->lock);
5891                 if (id2 < 0 || id2 == 0xffff)
5892                         continue;
5893
5894                 np->phy_model = id2 & PHYID2_MODEL_MASK;
5895                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5896                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5897                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
5898                         pci_name(pci_dev), id1, id2, phyaddr);
5899                 np->phyaddr = phyaddr;
5900                 np->phy_oui = id1 | id2;
5901
5902                 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5903                 if (np->phy_oui == PHY_OUI_REALTEK2)
5904                         np->phy_oui = PHY_OUI_REALTEK;
5905                 /* Setup phy revision for Realtek */
5906                 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5907                         np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5908
5909                 break;
5910         }
5911         if (i == 33) {
5912                 dev_printk(KERN_INFO, &pci_dev->dev,
5913                         "open: Could not find a valid PHY.\n");
5914                 goto out_error;
5915         }
5916
5917         if (!phyinitialized) {
5918                 /* reset it */
5919                 phy_init(dev);
5920         } else {
5921                 /* see if it is a gigabit phy */
5922                 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5923                 if (mii_status & PHY_GIGABIT) {
5924                         np->gigabit = PHY_GIGABIT;
5925                 }
5926         }
5927
5928         /* set default link speed settings */
5929         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5930         np->duplex = 0;
5931         np->autoneg = 1;
5932
5933         err = register_netdev(dev);
5934         if (err) {
5935                 dev_printk(KERN_INFO, &pci_dev->dev,
5936                            "unable to register netdev: %d\n", err);
5937                 goto out_error;
5938         }
5939
5940         dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, "
5941                    "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
5942                    dev->name,
5943                    np->phy_oui,
5944                    np->phyaddr,
5945                    dev->dev_addr[0],
5946                    dev->dev_addr[1],
5947                    dev->dev_addr[2],
5948                    dev->dev_addr[3],
5949                    dev->dev_addr[4],
5950                    dev->dev_addr[5]);
5951
5952         dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5953                    dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5954                    dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
5955                         "csum " : "",
5956                    dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5957                         "vlan " : "",
5958                    id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5959                    id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5960                    id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5961                    np->gigabit == PHY_GIGABIT ? "gbit " : "",
5962                    np->need_linktimer ? "lnktim " : "",
5963                    np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5964                    np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5965                    np->desc_ver);
5966
5967         return 0;
5968
5969 out_error:
5970         if (phystate_orig)
5971                 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5972         pci_set_drvdata(pci_dev, NULL);
5973 out_freering:
5974         free_rings(dev);
5975 out_unmap:
5976         iounmap(get_hwbase(dev));
5977 out_relreg:
5978         pci_release_regions(pci_dev);
5979 out_disable:
5980         pci_disable_device(pci_dev);
5981 out_free:
5982         free_netdev(dev);
5983 out:
5984         return err;
5985 }
5986
5987 static void nv_restore_phy(struct net_device *dev)
5988 {
5989         struct fe_priv *np = netdev_priv(dev);
5990         u16 phy_reserved, mii_control;
5991
5992         if (np->phy_oui == PHY_OUI_REALTEK &&
5993             np->phy_model == PHY_MODEL_REALTEK_8201 &&
5994             phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
5995                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
5996                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
5997                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
5998                 phy_reserved |= PHY_REALTEK_INIT8;
5999                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
6000                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
6001
6002                 /* restart auto negotiation */
6003                 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
6004                 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
6005                 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
6006         }
6007 }
6008
6009 static void nv_restore_mac_addr(struct pci_dev *pci_dev)
6010 {
6011         struct net_device *dev = pci_get_drvdata(pci_dev);
6012         struct fe_priv *np = netdev_priv(dev);
6013         u8 __iomem *base = get_hwbase(dev);
6014
6015         /* special op: write back the misordered MAC address - otherwise
6016          * the next nv_probe would see a wrong address.
6017          */
6018         writel(np->orig_mac[0], base + NvRegMacAddrA);
6019         writel(np->orig_mac[1], base + NvRegMacAddrB);
6020         writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
6021                base + NvRegTransmitPoll);
6022 }
6023
6024 static void __devexit nv_remove(struct pci_dev *pci_dev)
6025 {
6026         struct net_device *dev = pci_get_drvdata(pci_dev);
6027
6028         unregister_netdev(dev);
6029
6030         nv_restore_mac_addr(pci_dev);
6031
6032         /* restore any phy related changes */
6033         nv_restore_phy(dev);
6034
6035         nv_mgmt_release_sema(dev);
6036
6037         /* free all structures */
6038         free_rings(dev);
6039         iounmap(get_hwbase(dev));
6040         pci_release_regions(pci_dev);
6041         pci_disable_device(pci_dev);
6042         free_netdev(dev);
6043         pci_set_drvdata(pci_dev, NULL);
6044 }
6045
6046 #ifdef CONFIG_PM
6047 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
6048 {
6049         struct net_device *dev = pci_get_drvdata(pdev);
6050         struct fe_priv *np = netdev_priv(dev);
6051         u8 __iomem *base = get_hwbase(dev);
6052         int i;
6053
6054         if (netif_running(dev)) {
6055                 // Gross.
6056                 nv_close(dev);
6057         }
6058         netif_device_detach(dev);
6059
6060         /* save non-pci configuration space */
6061         for (i = 0;i <= np->register_size/sizeof(u32); i++)
6062                 np->saved_config_space[i] = readl(base + i*sizeof(u32));
6063
6064         pci_save_state(pdev);
6065         pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
6066         pci_disable_device(pdev);
6067         pci_set_power_state(pdev, pci_choose_state(pdev, state));
6068         return 0;
6069 }
6070
6071 static int nv_resume(struct pci_dev *pdev)
6072 {
6073         struct net_device *dev = pci_get_drvdata(pdev);
6074         struct fe_priv *np = netdev_priv(dev);
6075         u8 __iomem *base = get_hwbase(dev);
6076         int i, rc = 0;
6077
6078         pci_set_power_state(pdev, PCI_D0);
6079         pci_restore_state(pdev);
6080         /* ack any pending wake events, disable PME */
6081         pci_enable_wake(pdev, PCI_D0, 0);
6082
6083         /* restore non-pci configuration space */
6084         for (i = 0;i <= np->register_size/sizeof(u32); i++)
6085                 writel(np->saved_config_space[i], base+i*sizeof(u32));
6086
6087         pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
6088
6089         netif_device_attach(dev);
6090         if (netif_running(dev)) {
6091                 rc = nv_open(dev);
6092                 nv_set_multicast(dev);
6093         }
6094         return rc;
6095 }
6096
6097 static void nv_shutdown(struct pci_dev *pdev)
6098 {
6099         struct net_device *dev = pci_get_drvdata(pdev);
6100         struct fe_priv *np = netdev_priv(dev);
6101
6102         if (netif_running(dev))
6103                 nv_close(dev);
6104
6105         /*
6106          * Restore the MAC so a kernel started by kexec won't get confused.
6107          * If we really go for poweroff, we must not restore the MAC,
6108          * otherwise the MAC for WOL will be reversed at least on some boards.
6109          */
6110         if (system_state != SYSTEM_POWER_OFF) {
6111                 nv_restore_mac_addr(pdev);
6112         }
6113
6114         pci_disable_device(pdev);
6115         /*
6116          * Apparently it is not possible to reinitialise from D3 hot,
6117          * only put the device into D3 if we really go for poweroff.
6118          */
6119         if (system_state == SYSTEM_POWER_OFF) {
6120                 if (pci_enable_wake(pdev, PCI_D3cold, np->wolenabled))
6121                         pci_enable_wake(pdev, PCI_D3hot, np->wolenabled);
6122                 pci_set_power_state(pdev, PCI_D3hot);
6123         }
6124 }
6125 #else
6126 #define nv_suspend NULL
6127 #define nv_shutdown NULL
6128 #define nv_resume NULL
6129 #endif /* CONFIG_PM */
6130
6131 static struct pci_device_id pci_tbl[] = {
6132         {       /* nForce Ethernet Controller */
6133                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
6134                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6135         },
6136         {       /* nForce2 Ethernet Controller */
6137                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
6138                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6139         },
6140         {       /* nForce3 Ethernet Controller */
6141                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
6142                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6143         },
6144         {       /* nForce3 Ethernet Controller */
6145                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
6146                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6147         },
6148         {       /* nForce3 Ethernet Controller */
6149                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
6150                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6151         },
6152         {       /* nForce3 Ethernet Controller */
6153                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
6154                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6155         },
6156         {       /* nForce3 Ethernet Controller */
6157                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
6158                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6159         },
6160         {       /* CK804 Ethernet Controller */
6161                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
6162                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6163         },
6164         {       /* CK804 Ethernet Controller */
6165                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
6166                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6167         },
6168         {       /* MCP04 Ethernet Controller */
6169                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
6170                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6171         },
6172         {       /* MCP04 Ethernet Controller */
6173                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
6174                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6175         },
6176         {       /* MCP51 Ethernet Controller */
6177                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
6178                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
6179         },
6180         {       /* MCP51 Ethernet Controller */
6181                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
6182                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
6183         },
6184         {       /* MCP55 Ethernet Controller */
6185                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
6186                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT,
6187         },
6188         {       /* MCP55 Ethernet Controller */
6189                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
6190                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT,
6191         },
6192         {       /* MCP61 Ethernet Controller */
6193                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
6194                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
6195         },
6196         {       /* MCP61 Ethernet Controller */
6197                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
6198                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
6199         },
6200         {       /* MCP61 Ethernet Controller */
6201                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
6202                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
6203         },
6204         {       /* MCP61 Ethernet Controller */
6205                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
6206                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
6207         },
6208         {       /* MCP65 Ethernet Controller */
6209                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
6210                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6211         },
6212         {       /* MCP65 Ethernet Controller */
6213                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
6214                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6215         },
6216         {       /* MCP65 Ethernet Controller */
6217                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
6218                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6219         },
6220         {       /* MCP65 Ethernet Controller */
6221                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
6222                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6223         },
6224         {       /* MCP67 Ethernet Controller */
6225                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
6226                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
6227         },
6228         {       /* MCP67 Ethernet Controller */
6229                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
6230                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
6231         },
6232         {       /* MCP67 Ethernet Controller */
6233                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
6234                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
6235         },
6236         {       /* MCP67 Ethernet Controller */
6237                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
6238                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
6239         },
6240         {       /* MCP73 Ethernet Controller */
6241                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_28),
6242                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
6243         },
6244         {       /* MCP73 Ethernet Controller */
6245                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_29),
6246                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
6247         },
6248         {       /* MCP73 Ethernet Controller */
6249                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_30),
6250                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
6251         },
6252         {       /* MCP73 Ethernet Controller */
6253                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_31),
6254                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
6255         },
6256         {       /* MCP77 Ethernet Controller */
6257                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32),
6258                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6259         },
6260         {       /* MCP77 Ethernet Controller */
6261                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33),
6262                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6263         },
6264         {       /* MCP77 Ethernet Controller */
6265                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34),
6266                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6267         },
6268         {       /* MCP77 Ethernet Controller */
6269                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35),
6270                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6271         },
6272         {       /* MCP79 Ethernet Controller */
6273                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36),
6274                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6275         },
6276         {       /* MCP79 Ethernet Controller */
6277                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37),
6278                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6279         },
6280         {       /* MCP79 Ethernet Controller */
6281                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38),
6282                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6283         },
6284         {       /* MCP79 Ethernet Controller */
6285                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39),
6286                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6287         },
6288         {0,},
6289 };
6290
6291 static struct pci_driver driver = {
6292         .name           = DRV_NAME,
6293         .id_table       = pci_tbl,
6294         .probe          = nv_probe,
6295         .remove         = __devexit_p(nv_remove),
6296         .suspend        = nv_suspend,
6297         .resume         = nv_resume,
6298         .shutdown       = nv_shutdown,
6299 };
6300
6301 static int __init init_nic(void)
6302 {
6303         return pci_register_driver(&driver);
6304 }
6305
6306 static void __exit exit_nic(void)
6307 {
6308         pci_unregister_driver(&driver);
6309 }
6310
6311 module_param(max_interrupt_work, int, 0);
6312 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
6313 module_param(optimization_mode, int, 0);
6314 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
6315 module_param(poll_interval, int, 0);
6316 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6317 module_param(msi, int, 0);
6318 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6319 module_param(msix, int, 0);
6320 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6321 module_param(dma_64bit, int, 0);
6322 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6323 module_param(phy_cross, int, 0);
6324 MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6325
6326 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6327 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6328 MODULE_LICENSE("GPL");
6329
6330 MODULE_DEVICE_TABLE(pci, pci_tbl);
6331
6332 module_init(init_nic);
6333 module_exit(exit_nic);