drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey.
   7  *
   8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
   9  * trademarks of NVIDIA Corporation in the United States and other
  10  * countries.
  11  *
  12  * Copyright (C) 2003,4,5 Manfred Spraul
  13  * Copyright (C) 2004 Andrew de Quincey (wol support)
  14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  16  * Copyright (c) 2004,5,6 NVIDIA Corporation
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License as published by
  20  * the Free Software Foundation; either version 2 of the License, or
  21  * (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  31  *
  32  * Changelog:
  33  *      0.01: 05 Oct 2003: First release that compiles without warnings.
  34  *      0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
  35  *                         Check all PCI BARs for the register window.
  36  *                         udelay added to mii_rw.
  37  *      0.03: 06 Oct 2003: Initialize dev->irq.
  38  *      0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
  39  *      0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
  40  *      0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
  41  *                         irq mask updated
  42  *      0.07: 14 Oct 2003: Further irq mask updates.
  43  *      0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
  44  *                         added into irq handler, NULL check for drain_ring.
  45  *      0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
  46  *                         requested interrupt sources.
  47  *      0.10: 20 Oct 2003: First cleanup for release.
  48  *      0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
  49  *                         MAC Address init fix, set_multicast cleanup.
  50  *      0.12: 23 Oct 2003: Cleanups for release.
  51  *      0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
  52  *                         Set link speed correctly. start rx before starting
  53  *                         tx (nv_start_rx sets the link speed).
  54  *      0.14: 25 Oct 2003: Nic dependant irq mask.
  55  *      0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
  56  *                         open.
  57  *      0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
  58  *                         increased to 1628 bytes.
  59  *      0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
  60  *                         the tx length.
  61  *      0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
  62  *      0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
  63  *                         addresses, really stop rx if already running
  64  *                         in nv_start_rx, clean up a bit.
  65  *      0.20: 07 Dec 2003: alloc fixes
  66  *      0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
  67  *      0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
  68  *                         on close.
  69  *      0.23: 26 Jan 2004: various small cleanups
  70  *      0.24: 27 Feb 2004: make driver even less anonymous in backtraces
  71  *      0.25: 09 Mar 2004: wol support
  72  *      0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
  73  *      0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
  74  *                         added CK804/MCP04 device IDs, code fixes
  75  *                         for registers, link status and other minor fixes.
  76  *      0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
  77  *      0.29: 31 Aug 2004: Add backup timer for link change notification.
  78  *      0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
  79  *                         into nv_close, otherwise reenabling for wol can
  80  *                         cause DMA to kfree'd memory.
  81  *      0.31: 14 Nov 2004: ethtool support for getting/setting link
  82  *                         capabilities.
  83  *      0.32: 16 Apr 2005: RX_ERROR4 handling added.
  84  *      0.33: 16 May 2005: Support for MCP51 added.
  85  *      0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
  86  *      0.35: 26 Jun 2005: Support for MCP55 added.
  87  *      0.36: 28 Jun 2005: Add jumbo frame support.
  88  *      0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
  89  *      0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
  90  *                         per-packet flags.
  91  *      0.39: 18 Jul 2005: Add 64bit descriptor support.
  92  *      0.40: 19 Jul 2005: Add support for mac address change.
  93  *      0.41: 30 Jul 2005: Write back original MAC in nv_close instead
  94  *                         of nv_remove
  95  *      0.42: 06 Aug 2005: Fix lack of link speed initialization
  96  *                         in the second (and later) nv_open call
  97  *      0.43: 10 Aug 2005: Add support for tx checksum.
  98  *      0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
  99  *      0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
 100  *      0.46: 20 Oct 2005: Add irq optimization modes.
 101  *      0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
 102  *      0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
 103  *      0.49: 10 Dec 2005: Fix tso for large buffers.
 104  *      0.50: 20 Jan 2006: Add 8021pq tagging support.
 105  *      0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
 106  *      0.52: 20 Jan 2006: Add MSI/MSIX support.
 107  *      0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
 108  *      0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
 109  *      0.55: 22 Mar 2006: Add flow control (pause frame).
 110  *      0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
 111  *      0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
 112  *      0.58: 30 Oct 2006: Added support for sideband management unit.
 113  *      0.59: 30 Oct 2006: Added support for recoverable error.
 114  *      0.60: 20 Jan 2007: Code optimizations for rings, rx & tx data paths, and stats.
 115  *
 116  * Known bugs:
 117  * We suspect that on some hardware no TX done interrupts are generated.
 118  * This means recovery from netif_stop_queue only happens if the hw timer
 119  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
 120  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
 121  * If your hardware reliably generates tx done interrupts, then you can remove
 122  * DEV_NEED_TIMERIRQ from the driver_data flags.
 123  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
 124  * superfluous timer interrupts from the nic.
 125  */
 126 #ifdef CONFIG_FORCEDETH_NAPI
 127 #define DRIVERNAPI "-NAPI"
 128 #else
 129 #define DRIVERNAPI
 130 #endif
 131 #define FORCEDETH_VERSION               "0.60"
 132 #define DRV_NAME                        "forcedeth"
 133
 134 #include <linux/module.h>
 135 #include <linux/types.h>
 136 #include <linux/pci.h>
 137 #include <linux/interrupt.h>
 138 #include <linux/netdevice.h>
 139 #include <linux/etherdevice.h>
 140 #include <linux/delay.h>
 141 #include <linux/spinlock.h>
 142 #include <linux/ethtool.h>
 143 #include <linux/timer.h>
 144 #include <linux/skbuff.h>
 145 #include <linux/mii.h>
 146 #include <linux/random.h>
 147 #include <linux/init.h>
 148 #include <linux/if_vlan.h>
 149 #include <linux/dma-mapping.h>
 150
 151 #include <asm/irq.h>
 152 #include <asm/io.h>
 153 #include <asm/uaccess.h>
 154 #include <asm/system.h>
 155
 156 #if 0
 157 #define dprintk                 printk
 158 #else
 159 #define dprintk(x...)           do { } while (0)
 160 #endif
 161
 162
 163 /*
 164  * Hardware access:
 165  */
 166
 167 #define DEV_NEED_TIMERIRQ       0x0001  /* set the timer irq flag in the irq mask */
 168 #define DEV_NEED_LINKTIMER      0x0002  /* poll link settings. Relies on the timer irq */
 169 #define DEV_HAS_LARGEDESC       0x0004  /* device supports jumbo frames and needs packet format 2 */
 170 #define DEV_HAS_HIGH_DMA        0x0008  /* device supports 64bit dma */
 171 #define DEV_HAS_CHECKSUM        0x0010  /* device supports tx and rx checksum offloads */
 172 #define DEV_HAS_VLAN            0x0020  /* device supports vlan tagging and striping */
 173 #define DEV_HAS_MSI             0x0040  /* device supports MSI */
 174 #define DEV_HAS_MSI_X           0x0080  /* device supports MSI-X */
 175 #define DEV_HAS_POWER_CNTRL     0x0100  /* device supports power savings */
 176 #define DEV_HAS_PAUSEFRAME_TX   0x0200  /* device supports tx pause frames */
 177 #define DEV_HAS_STATISTICS_V1   0x0400  /* device supports hw statistics version 1 */
 178 #define DEV_HAS_STATISTICS_V2   0x0800  /* device supports hw statistics version 2 */
 179 #define DEV_HAS_TEST_EXTENDED   0x1000  /* device supports extended diagnostic test */
 180 #define DEV_HAS_MGMT_UNIT       0x2000  /* device supports management unit */
 181
 182 enum {
 183         NvRegIrqStatus = 0x000,
 184 #define NVREG_IRQSTAT_MIIEVENT  0x040
 185 #define NVREG_IRQSTAT_MASK              0x81ff
 186         NvRegIrqMask = 0x004,
 187 #define NVREG_IRQ_RX_ERROR              0x0001
 188 #define NVREG_IRQ_RX                    0x0002
 189 #define NVREG_IRQ_RX_NOBUF              0x0004
 190 #define NVREG_IRQ_TX_ERR                0x0008
 191 #define NVREG_IRQ_TX_OK                 0x0010
 192 #define NVREG_IRQ_TIMER                 0x0020
 193 #define NVREG_IRQ_LINK                  0x0040
 194 #define NVREG_IRQ_RX_FORCED             0x0080
 195 #define NVREG_IRQ_TX_FORCED             0x0100
 196 #define NVREG_IRQ_RECOVER_ERROR         0x8000
 197 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 198 #define NVREG_IRQMASK_CPU               0x0040
 199 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 200 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 201 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
 202
 203 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
 204                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
 205                                         NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
 206
 207         NvRegUnknownSetupReg6 = 0x008,
 208 #define NVREG_UNKSETUP6_VAL             3
 209
 210 /*
 211  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 212  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 213  */
 214         NvRegPollingInterval = 0x00c,
 215 #define NVREG_POLL_DEFAULT_THROUGHPUT   970 /* backup tx cleanup if loop max reached */
 216 #define NVREG_POLL_DEFAULT_CPU  13
 217         NvRegMSIMap0 = 0x020,
 218         NvRegMSIMap1 = 0x024,
 219         NvRegMSIIrqMask = 0x030,
 220 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 221         NvRegMisc1 = 0x080,
 222 #define NVREG_MISC1_PAUSE_TX    0x01
 223 #define NVREG_MISC1_HD          0x02
 224 #define NVREG_MISC1_FORCE       0x3b0f3c
 225
 226         NvRegMacReset = 0x3c,
 227 #define NVREG_MAC_RESET_ASSERT  0x0F3
 228         NvRegTransmitterControl = 0x084,
 229 #define NVREG_XMITCTL_START     0x01
 230 #define NVREG_XMITCTL_MGMT_ST   0x40000000
 231 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
 232 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
 233 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
 234 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
 235 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
 236 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
 237 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
 238 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
 239 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
 240         NvRegTransmitterStatus = 0x088,
 241 #define NVREG_XMITSTAT_BUSY     0x01
 242
 243         NvRegPacketFilterFlags = 0x8c,
 244 #define NVREG_PFF_PAUSE_RX      0x08
 245 #define NVREG_PFF_ALWAYS        0x7F0000
 246 #define NVREG_PFF_PROMISC       0x80
 247 #define NVREG_PFF_MYADDR        0x20
 248 #define NVREG_PFF_LOOPBACK      0x10
 249
 250         NvRegOffloadConfig = 0x90,
 251 #define NVREG_OFFLOAD_HOMEPHY   0x601
 252 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 253         NvRegReceiverControl = 0x094,
 254 #define NVREG_RCVCTL_START      0x01
 255 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
 256         NvRegReceiverStatus = 0x98,
 257 #define NVREG_RCVSTAT_BUSY      0x01
 258
 259         NvRegRandomSeed = 0x9c,
 260 #define NVREG_RNDSEED_MASK      0x00ff
 261 #define NVREG_RNDSEED_FORCE     0x7f00
 262 #define NVREG_RNDSEED_FORCE2    0x2d00
 263 #define NVREG_RNDSEED_FORCE3    0x7400
 264
 265         NvRegTxDeferral = 0xA0,
 266 #define NVREG_TX_DEFERRAL_DEFAULT       0x15050f
 267 #define NVREG_TX_DEFERRAL_RGMII_10_100  0x16070f
 268 #define NVREG_TX_DEFERRAL_RGMII_1000    0x14050f
 269         NvRegRxDeferral = 0xA4,
 270 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
 271         NvRegMacAddrA = 0xA8,
 272         NvRegMacAddrB = 0xAC,
 273         NvRegMulticastAddrA = 0xB0,
 274 #define NVREG_MCASTADDRA_FORCE  0x01
 275         NvRegMulticastAddrB = 0xB4,
 276         NvRegMulticastMaskA = 0xB8,
 277         NvRegMulticastMaskB = 0xBC,
 278
 279         NvRegPhyInterface = 0xC0,
 280 #define PHY_RGMII               0x10000000
 281
 282         NvRegTxRingPhysAddr = 0x100,
 283         NvRegRxRingPhysAddr = 0x104,
 284         NvRegRingSizes = 0x108,
 285 #define NVREG_RINGSZ_TXSHIFT 0
 286 #define NVREG_RINGSZ_RXSHIFT 16
 287         NvRegTransmitPoll = 0x10c,
 288 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
 289         NvRegLinkSpeed = 0x110,
 290 #define NVREG_LINKSPEED_FORCE 0x10000
 291 #define NVREG_LINKSPEED_10      1000
 292 #define NVREG_LINKSPEED_100     100
 293 #define NVREG_LINKSPEED_1000    50
 294 #define NVREG_LINKSPEED_MASK    (0xFFF)
 295         NvRegUnknownSetupReg5 = 0x130,
 296 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 297         NvRegTxWatermark = 0x13c,
 298 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
 299 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
 300 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
 301         NvRegTxRxControl = 0x144,
 302 #define NVREG_TXRXCTL_KICK      0x0001
 303 #define NVREG_TXRXCTL_BIT1      0x0002
 304 #define NVREG_TXRXCTL_BIT2      0x0004
 305 #define NVREG_TXRXCTL_IDLE      0x0008
 306 #define NVREG_TXRXCTL_RESET     0x0010
 307 #define NVREG_TXRXCTL_RXCHECK   0x0400
 308 #define NVREG_TXRXCTL_DESC_1    0
 309 #define NVREG_TXRXCTL_DESC_2    0x002100
 310 #define NVREG_TXRXCTL_DESC_3    0xc02200
 311 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 312 #define NVREG_TXRXCTL_VLANINS   0x00080
 313         NvRegTxRingPhysAddrHigh = 0x148,
 314         NvRegRxRingPhysAddrHigh = 0x14C,
 315         NvRegTxPauseFrame = 0x170,
 316 #define NVREG_TX_PAUSEFRAME_DISABLE     0x1ff0080
 317 #define NVREG_TX_PAUSEFRAME_ENABLE      0x0c00030
 318         NvRegMIIStatus = 0x180,
 319 #define NVREG_MIISTAT_ERROR             0x0001
 320 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 321 #define NVREG_MIISTAT_MASK              0x000f
 322 #define NVREG_MIISTAT_MASK2             0x000f
 323         NvRegMIIMask = 0x184,
 324 #define NVREG_MII_LINKCHANGE            0x0008
 325
 326         NvRegAdapterControl = 0x188,
 327 #define NVREG_ADAPTCTL_START    0x02
 328 #define NVREG_ADAPTCTL_LINKUP   0x04
 329 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 330 #define NVREG_ADAPTCTL_RUNNING  0x100000
 331 #define NVREG_ADAPTCTL_PHYSHIFT 24
 332         NvRegMIISpeed = 0x18c,
 333 #define NVREG_MIISPEED_BIT8     (1<<8)
 334 #define NVREG_MIIDELAY  5
 335         NvRegMIIControl = 0x190,
 336 #define NVREG_MIICTL_INUSE      0x08000
 337 #define NVREG_MIICTL_WRITE      0x00400
 338 #define NVREG_MIICTL_ADDRSHIFT  5
 339         NvRegMIIData = 0x194,
 340         NvRegWakeUpFlags = 0x200,
 341 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 342 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 343 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 344 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 345 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 346 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 347 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 348 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 349 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 350 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 351 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 352
 353         NvRegPatternCRC = 0x204,
 354         NvRegPatternMask = 0x208,
 355         NvRegPowerCap = 0x268,
 356 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 357 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 358 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 359         NvRegPowerState = 0x26c,
 360 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 361 #define NVREG_POWERSTATE_VALID          0x0100
 362 #define NVREG_POWERSTATE_MASK           0x0003
 363 #define NVREG_POWERSTATE_D0             0x0000
 364 #define NVREG_POWERSTATE_D1             0x0001
 365 #define NVREG_POWERSTATE_D2             0x0002
 366 #define NVREG_POWERSTATE_D3             0x0003
 367         NvRegTxCnt = 0x280,
 368         NvRegTxZeroReXmt = 0x284,
 369         NvRegTxOneReXmt = 0x288,
 370         NvRegTxManyReXmt = 0x28c,
 371         NvRegTxLateCol = 0x290,
 372         NvRegTxUnderflow = 0x294,
 373         NvRegTxLossCarrier = 0x298,
 374         NvRegTxExcessDef = 0x29c,
 375         NvRegTxRetryErr = 0x2a0,
 376         NvRegRxFrameErr = 0x2a4,
 377         NvRegRxExtraByte = 0x2a8,
 378         NvRegRxLateCol = 0x2ac,
 379         NvRegRxRunt = 0x2b0,
 380         NvRegRxFrameTooLong = 0x2b4,
 381         NvRegRxOverflow = 0x2b8,
 382         NvRegRxFCSErr = 0x2bc,
 383         NvRegRxFrameAlignErr = 0x2c0,
 384         NvRegRxLenErr = 0x2c4,
 385         NvRegRxUnicast = 0x2c8,
 386         NvRegRxMulticast = 0x2cc,
 387         NvRegRxBroadcast = 0x2d0,
 388         NvRegTxDef = 0x2d4,
 389         NvRegTxFrame = 0x2d8,
 390         NvRegRxCnt = 0x2dc,
 391         NvRegTxPause = 0x2e0,
 392         NvRegRxPause = 0x2e4,
 393         NvRegRxDropFrame = 0x2e8,
 394         NvRegVlanControl = 0x300,
 395 #define NVREG_VLANCONTROL_ENABLE        0x2000
 396         NvRegMSIXMap0 = 0x3e0,
 397         NvRegMSIXMap1 = 0x3e4,
 398         NvRegMSIXIrqStatus = 0x3f0,
 399
 400         NvRegPowerState2 = 0x600,
 401 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F11
 402 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 403 };
 404
 405 /* Big endian: should work, but is untested */
 406 struct ring_desc {
 407         __le32 buf;
 408         __le32 flaglen;
 409 };
 410
 411 struct ring_desc_ex {
 412         __le32 bufhigh;
 413         __le32 buflow;
 414         __le32 txvlan;
 415         __le32 flaglen;
 416 };
 417
 418 union ring_type {
 419         struct ring_desc* orig;
 420         struct ring_desc_ex* ex;
 421 };
 422
 423 #define FLAG_MASK_V1 0xffff0000
 424 #define FLAG_MASK_V2 0xffffc000
 425 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 426 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 427
 428 #define NV_TX_LASTPACKET        (1<<16)
 429 #define NV_TX_RETRYERROR        (1<<19)
 430 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 431 #define NV_TX_DEFERRED          (1<<26)
 432 #define NV_TX_CARRIERLOST       (1<<27)
 433 #define NV_TX_LATECOLLISION     (1<<28)
 434 #define NV_TX_UNDERFLOW         (1<<29)
 435 #define NV_TX_ERROR             (1<<30)
 436 #define NV_TX_VALID             (1<<31)
 437
 438 #define NV_TX2_LASTPACKET       (1<<29)
 439 #define NV_TX2_RETRYERROR       (1<<18)
 440 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 441 #define NV_TX2_DEFERRED         (1<<25)
 442 #define NV_TX2_CARRIERLOST      (1<<26)
 443 #define NV_TX2_LATECOLLISION    (1<<27)
 444 #define NV_TX2_UNDERFLOW        (1<<28)
 445 /* error and valid are the same for both */
 446 #define NV_TX2_ERROR            (1<<30)
 447 #define NV_TX2_VALID            (1<<31)
 448 #define NV_TX2_TSO              (1<<28)
 449 #define NV_TX2_TSO_SHIFT        14
 450 #define NV_TX2_TSO_MAX_SHIFT    14
 451 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 452 #define NV_TX2_CHECKSUM_L3      (1<<27)
 453 #define NV_TX2_CHECKSUM_L4      (1<<26)
 454
 455 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 456
 457 #define NV_RX_DESCRIPTORVALID   (1<<16)
 458 #define NV_RX_MISSEDFRAME       (1<<17)
 459 #define NV_RX_SUBSTRACT1        (1<<18)
 460 #define NV_RX_ERROR1            (1<<23)
 461 #define NV_RX_ERROR2            (1<<24)
 462 #define NV_RX_ERROR3            (1<<25)
 463 #define NV_RX_ERROR4            (1<<26)
 464 #define NV_RX_CRCERR            (1<<27)
 465 #define NV_RX_OVERFLOW          (1<<28)
 466 #define NV_RX_FRAMINGERR        (1<<29)
 467 #define NV_RX_ERROR             (1<<30)
 468 #define NV_RX_AVAIL             (1<<31)
 469
 470 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 471 #define NV_RX2_CHECKSUMOK1      (0x10000000)
 472 #define NV_RX2_CHECKSUMOK2      (0x14000000)
 473 #define NV_RX2_CHECKSUMOK3      (0x18000000)
 474 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 475 #define NV_RX2_SUBSTRACT1       (1<<25)
 476 #define NV_RX2_ERROR1           (1<<18)
 477 #define NV_RX2_ERROR2           (1<<19)
 478 #define NV_RX2_ERROR3           (1<<20)
 479 #define NV_RX2_ERROR4           (1<<21)
 480 #define NV_RX2_CRCERR           (1<<22)
 481 #define NV_RX2_OVERFLOW         (1<<23)
 482 #define NV_RX2_FRAMINGERR       (1<<24)
 483 /* error and avail are the same for both */
 484 #define NV_RX2_ERROR            (1<<30)
 485 #define NV_RX2_AVAIL            (1<<31)
 486
 487 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 488 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 489
 490 /* Miscelaneous hardware related defines: */
 491 #define NV_PCI_REGSZ_VER1       0x270
 492 #define NV_PCI_REGSZ_VER2       0x2d4
 493 #define NV_PCI_REGSZ_VER3       0x604
 494
 495 /* various timeout delays: all in usec */
 496 #define NV_TXRX_RESET_DELAY     4
 497 #define NV_TXSTOP_DELAY1        10
 498 #define NV_TXSTOP_DELAY1MAX     500000
 499 #define NV_TXSTOP_DELAY2        100
 500 #define NV_RXSTOP_DELAY1        10
 501 #define NV_RXSTOP_DELAY1MAX     500000
 502 #define NV_RXSTOP_DELAY2        100
 503 #define NV_SETUP5_DELAY         5
 504 #define NV_SETUP5_DELAYMAX      50000
 505 #define NV_POWERUP_DELAY        5
 506 #define NV_POWERUP_DELAYMAX     5000
 507 #define NV_MIIBUSY_DELAY        50
 508 #define NV_MIIPHY_DELAY 10
 509 #define NV_MIIPHY_DELAYMAX      10000
 510 #define NV_MAC_RESET_DELAY      64
 511
 512 #define NV_WAKEUPPATTERNS       5
 513 #define NV_WAKEUPMASKENTRIES    4
 514
 515 /* General driver defaults */
 516 #define NV_WATCHDOG_TIMEO       (5*HZ)
 517
 518 #define RX_RING_DEFAULT         128
 519 #define TX_RING_DEFAULT         256
 520 #define RX_RING_MIN             128
 521 #define TX_RING_MIN             64
 522 #define RING_MAX_DESC_VER_1     1024
 523 #define RING_MAX_DESC_VER_2_3   16384
 524
 525 /* rx/tx mac addr + type + vlan + align + slack*/
 526 #define NV_RX_HEADERS           (64)
 527 /* even more slack. */
 528 #define NV_RX_ALLOC_PAD         (64)
 529
 530 /* maximum mtu size */
 531 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 532 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 533
 534 #define OOM_REFILL      (1+HZ/20)
 535 #define POLL_WAIT       (1+HZ/100)
 536 #define LINK_TIMEOUT    (3*HZ)
 537 #define STATS_INTERVAL  (10*HZ)
 538
 539 /*
 540  * desc_ver values:
 541  * The nic supports three different descriptor types:
 542  * - DESC_VER_1: Original
 543  * - DESC_VER_2: support for jumbo frames.
 544  * - DESC_VER_3: 64-bit format.
 545  */
 546 #define DESC_VER_1      1
 547 #define DESC_VER_2      2
 548 #define DESC_VER_3      3
 549
 550 /* PHY defines */
 551 #define PHY_OUI_MARVELL 0x5043
 552 #define PHY_OUI_CICADA  0x03f1
 553 #define PHYID1_OUI_MASK 0x03ff
 554 #define PHYID1_OUI_SHFT 6
 555 #define PHYID2_OUI_MASK 0xfc00
 556 #define PHYID2_OUI_SHFT 10
 557 #define PHYID2_MODEL_MASK               0x03f0
 558 #define PHY_MODEL_MARVELL_E3016         0x220
 559 #define PHY_MARVELL_E3016_INITMASK      0x0300
 560 #define PHY_INIT1       0x0f000
 561 #define PHY_INIT2       0x0e00
 562 #define PHY_INIT3       0x01000
 563 #define PHY_INIT4       0x0200
 564 #define PHY_INIT5       0x0004
 565 #define PHY_INIT6       0x02000
 566 #define PHY_GIGABIT     0x0100
 567
 568 #define PHY_TIMEOUT     0x1
 569 #define PHY_ERROR       0x2
 570
 571 #define PHY_100 0x1
 572 #define PHY_1000        0x2
 573 #define PHY_HALF        0x100
 574
 575 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 576 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 577 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 578 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 579 #define NV_PAUSEFRAME_RX_REQ     0x0010
 580 #define NV_PAUSEFRAME_TX_REQ     0x0020
 581 #define NV_PAUSEFRAME_AUTONEG    0x0040
 582
 583 /* MSI/MSI-X defines */
 584 #define NV_MSI_X_MAX_VECTORS  8
 585 #define NV_MSI_X_VECTORS_MASK 0x000f
 586 #define NV_MSI_CAPABLE        0x0010
 587 #define NV_MSI_X_CAPABLE      0x0020
 588 #define NV_MSI_ENABLED        0x0040
 589 #define NV_MSI_X_ENABLED      0x0080
 590
 591 #define NV_MSI_X_VECTOR_ALL   0x0
 592 #define NV_MSI_X_VECTOR_RX    0x0
 593 #define NV_MSI_X_VECTOR_TX    0x1
 594 #define NV_MSI_X_VECTOR_OTHER 0x2
 595
 596 /* statistics */
 597 struct nv_ethtool_str {
 598         char name[ETH_GSTRING_LEN];
 599 };
 600
 601 static const struct nv_ethtool_str nv_estats_str[] = {
 602         { "tx_bytes" },
 603         { "tx_zero_rexmt" },
 604         { "tx_one_rexmt" },
 605         { "tx_many_rexmt" },
 606         { "tx_late_collision" },
 607         { "tx_fifo_errors" },
 608         { "tx_carrier_errors" },
 609         { "tx_excess_deferral" },
 610         { "tx_retry_error" },
 611         { "rx_frame_error" },
 612         { "rx_extra_byte" },
 613         { "rx_late_collision" },
 614         { "rx_runt" },
 615         { "rx_frame_too_long" },
 616         { "rx_over_errors" },
 617         { "rx_crc_errors" },
 618         { "rx_frame_align_error" },
 619         { "rx_length_error" },
 620         { "rx_unicast" },
 621         { "rx_multicast" },
 622         { "rx_broadcast" },
 623         { "rx_packets" },
 624         { "rx_errors_total" },
 625         { "tx_errors_total" },
 626
 627         /* version 2 stats */
 628         { "tx_deferral" },
 629         { "tx_packets" },
 630         { "rx_bytes" },
 631         { "tx_pause" },
 632         { "rx_pause" },
 633         { "rx_drop_frame" }
 634 };
 635
 636 struct nv_ethtool_stats {
 637         u64 tx_bytes;
 638         u64 tx_zero_rexmt;
 639         u64 tx_one_rexmt;
 640         u64 tx_many_rexmt;
 641         u64 tx_late_collision;
 642         u64 tx_fifo_errors;
 643         u64 tx_carrier_errors;
 644         u64 tx_excess_deferral;
 645         u64 tx_retry_error;
 646         u64 rx_frame_error;
 647         u64 rx_extra_byte;
 648         u64 rx_late_collision;
 649         u64 rx_runt;
 650         u64 rx_frame_too_long;
 651         u64 rx_over_errors;
 652         u64 rx_crc_errors;
 653         u64 rx_frame_align_error;
 654         u64 rx_length_error;
 655         u64 rx_unicast;
 656         u64 rx_multicast;
 657         u64 rx_broadcast;
 658         u64 rx_packets;
 659         u64 rx_errors_total;
 660         u64 tx_errors_total;
 661
 662         /* version 2 stats */
 663         u64 tx_deferral;
 664         u64 tx_packets;
 665         u64 rx_bytes;
 666         u64 tx_pause;
 667         u64 rx_pause;
 668         u64 rx_drop_frame;
 669 };
 670
 671 #define NV_DEV_STATISTICS_V2_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
 672 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
 673
 674 /* diagnostics */
 675 #define NV_TEST_COUNT_BASE 3
 676 #define NV_TEST_COUNT_EXTENDED 4
 677
 678 static const struct nv_ethtool_str nv_etests_str[] = {
 679         { "link      (online/offline)" },
 680         { "register  (offline)       " },
 681         { "interrupt (offline)       " },
 682         { "loopback  (offline)       " }
 683 };
 684
 685 struct register_test {
 686         __le32 reg;
 687         __le32 mask;
 688 };
 689
 690 static const struct register_test nv_registers_test[] = {
 691         { NvRegUnknownSetupReg6, 0x01 },
 692         { NvRegMisc1, 0x03c },
 693         { NvRegOffloadConfig, 0x03ff },
 694         { NvRegMulticastAddrA, 0xffffffff },
 695         { NvRegTxWatermark, 0x0ff },
 696         { NvRegWakeUpFlags, 0x07777 },
 697         { 0,0 }
 698 };
 699
 700 struct nv_skb_map {
 701         struct sk_buff *skb;
 702         dma_addr_t dma;
 703         unsigned int dma_len;
 704 };
 705
 706 /*
 707  * SMP locking:
 708  * All hardware access under dev->priv->lock, except the performance
 709  * critical parts:
 710  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 711  *      by the arch code for interrupts.
 712  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 713  *      needs dev->priv->lock :-(
 714  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 715  */
 716
 717 /* in dev: base, irq */
 718 struct fe_priv {
 719         spinlock_t lock;
 720
 721         /* General data:
 722          * Locking: spin_lock(&np->lock); */
 723         struct net_device_stats stats;
 724         struct nv_ethtool_stats estats;
 725         int in_shutdown;
 726         u32 linkspeed;
 727         int duplex;
 728         int autoneg;
 729         int fixed_mode;
 730         int phyaddr;
 731         int wolenabled;
 732         unsigned int phy_oui;
 733         unsigned int phy_model;
 734         u16 gigabit;
 735         int intr_test;
 736         int recover_error;
 737
 738         /* General data: RO fields */
 739         dma_addr_t ring_addr;
 740         struct pci_dev *pci_dev;
 741         u32 orig_mac[2];
 742         u32 irqmask;
 743         u32 desc_ver;
 744         u32 txrxctl_bits;
 745         u32 vlanctl_bits;
 746         u32 driver_data;
 747         u32 register_size;
 748         int rx_csum;
 749         u32 mac_in_use;
 750
 751         void __iomem *base;
 752
 753         /* rx specific fields.
 754          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 755          */
 756         union ring_type get_rx, put_rx, first_rx, last_rx;
 757         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
 758         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
 759         struct nv_skb_map *rx_skb;
 760
 761         union ring_type rx_ring;
 762         unsigned int rx_buf_sz;
 763         unsigned int pkt_limit;
 764         struct timer_list oom_kick;
 765         struct timer_list nic_poll;
 766         struct timer_list stats_poll;
 767         u32 nic_poll_irq;
 768         int rx_ring_size;
 769
 770         /* media detection workaround.
 771          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 772          */
 773         int need_linktimer;
 774         unsigned long link_timeout;
 775         /*
 776          * tx specific fields.
 777          */
 778         union ring_type get_tx, put_tx, first_tx, last_tx;
 779         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
 780         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
 781         struct nv_skb_map *tx_skb;
 782
 783         union ring_type tx_ring;
 784         u32 tx_flags;
 785         int tx_ring_size;
 786         int tx_stop;
 787
 788         /* vlan fields */
 789         struct vlan_group *vlangrp;
 790
 791         /* msi/msi-x fields */
 792         u32 msi_flags;
 793         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 794
 795         /* flow control */
 796         u32 pause_flags;
 797 };
 798
 799 /*
 800  * Maximum number of loops until we assume that a bit in the irq mask
 801  * is stuck. Overridable with module param.
 802  */
 803 static int max_interrupt_work = 5;
 804
 805 /*
 806  * Optimization can be either throuput mode or cpu mode
 807  *
 808  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 809  * CPU Mode: Interrupts are controlled by a timer.
 810  */
 811 enum {
 812         NV_OPTIMIZATION_MODE_THROUGHPUT,
 813         NV_OPTIMIZATION_MODE_CPU
 814 };
 815 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
 816
 817 /*
 818  * Poll interval for timer irq
 819  *
 820  * This interval determines how frequent an interrupt is generated.
 821  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 822  * Min = 0, and Max = 65535
 823  */
 824 static int poll_interval = -1;
 825
 826 /*
 827  * MSI interrupts
 828  */
 829 enum {
 830         NV_MSI_INT_DISABLED,
 831         NV_MSI_INT_ENABLED
 832 };
 833 static int msi = NV_MSI_INT_ENABLED;
 834
 835 /*
 836  * MSIX interrupts
 837  */
 838 enum {
 839         NV_MSIX_INT_DISABLED,
 840         NV_MSIX_INT_ENABLED
 841 };
 842 static int msix = NV_MSIX_INT_DISABLED;
 843
 844 /*
 845  * DMA 64bit
 846  */
 847 enum {
 848         NV_DMA_64BIT_DISABLED,
 849         NV_DMA_64BIT_ENABLED
 850 };
 851 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 852
 853 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 854 {
 855         return netdev_priv(dev);
 856 }
 857
 858 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 859 {
 860         return ((struct fe_priv *)netdev_priv(dev))->base;
 861 }
 862
 863 static inline void pci_push(u8 __iomem *base)
 864 {
 865         /* force out pending posted writes */
 866         readl(base);
 867 }
 868
 869 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 870 {
 871         return le32_to_cpu(prd->flaglen)
 872                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 873 }
 874
 875 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 876 {
 877         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
 878 }
 879
 880 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 881                                 int delay, int delaymax, const char *msg)
 882 {
 883         u8 __iomem *base = get_hwbase(dev);
 884
 885         pci_push(base);
 886         do {
 887                 udelay(delay);
 888                 delaymax -= delay;
 889                 if (delaymax < 0) {
 890                         if (msg)
 891                                 printk(msg);
 892                         return 1;
 893                 }
 894         } while ((readl(base + offset) & mask) != target);
 895         return 0;
 896 }
 897
 898 #define NV_SETUP_RX_RING 0x01
 899 #define NV_SETUP_TX_RING 0x02
 900
 901 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
 902 {
 903         struct fe_priv *np = get_nvpriv(dev);
 904         u8 __iomem *base = get_hwbase(dev);
 905
 906         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 907                 if (rxtx_flags & NV_SETUP_RX_RING) {
 908                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 909                 }
 910                 if (rxtx_flags & NV_SETUP_TX_RING) {
 911                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
 912                 }
 913         } else {
 914                 if (rxtx_flags & NV_SETUP_RX_RING) {
 915                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 916                         writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
 917                 }
 918                 if (rxtx_flags & NV_SETUP_TX_RING) {
 919                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
 920                         writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
 921                 }
 922         }
 923 }
 924
 925 static void free_rings(struct net_device *dev)
 926 {
 927         struct fe_priv *np = get_nvpriv(dev);
 928
 929         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 930                 if (np->rx_ring.orig)
 931                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
 932                                             np->rx_ring.orig, np->ring_addr);
 933         } else {
 934                 if (np->rx_ring.ex)
 935                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
 936                                             np->rx_ring.ex, np->ring_addr);
 937         }
 938         if (np->rx_skb)
 939                 kfree(np->rx_skb);
 940         if (np->tx_skb)
 941                 kfree(np->tx_skb);
 942 }
 943
 944 static int using_multi_irqs(struct net_device *dev)
 945 {
 946         struct fe_priv *np = get_nvpriv(dev);
 947
 948         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
 949             ((np->msi_flags & NV_MSI_X_ENABLED) &&
 950              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
 951                 return 0;
 952         else
 953                 return 1;
 954 }
 955
 956 static void nv_enable_irq(struct net_device *dev)
 957 {
 958         struct fe_priv *np = get_nvpriv(dev);
 959
 960         if (!using_multi_irqs(dev)) {
 961                 if (np->msi_flags & NV_MSI_X_ENABLED)
 962                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 963                 else
 964                         enable_irq(dev->irq);
 965         } else {
 966                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 967                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 968                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
 969         }
 970 }
 971
 972 static void nv_disable_irq(struct net_device *dev)
 973 {
 974         struct fe_priv *np = get_nvpriv(dev);
 975
 976         if (!using_multi_irqs(dev)) {
 977                 if (np->msi_flags & NV_MSI_X_ENABLED)
 978                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 979                 else
 980                         disable_irq(dev->irq);
 981         } else {
 982                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 983                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 984                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
 985         }
 986 }
 987
 988 /* In MSIX mode, a write to irqmask behaves as XOR */
 989 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
 990 {
 991         u8 __iomem *base = get_hwbase(dev);
 992
 993         writel(mask, base + NvRegIrqMask);
 994 }
 995
 996 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
 997 {
 998         struct fe_priv *np = get_nvpriv(dev);
 999         u8 __iomem *base = get_hwbase(dev);
1000
1001         if (np->msi_flags & NV_MSI_X_ENABLED) {
1002                 writel(mask, base + NvRegIrqMask);
1003         } else {
1004                 if (np->msi_flags & NV_MSI_ENABLED)
1005                         writel(0, base + NvRegMSIIrqMask);
1006                 writel(0, base + NvRegIrqMask);
1007         }
1008 }
1009
1010 #define MII_READ        (-1)
1011 /* mii_rw: read/write a register on the PHY.
1012  *
1013  * Caller must guarantee serialization
1014  */
1015 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1016 {
1017         u8 __iomem *base = get_hwbase(dev);
1018         u32 reg;
1019         int retval;
1020
1021         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1022
1023         reg = readl(base + NvRegMIIControl);
1024         if (reg & NVREG_MIICTL_INUSE) {
1025                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1026                 udelay(NV_MIIBUSY_DELAY);
1027         }
1028
1029         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1030         if (value != MII_READ) {
1031                 writel(value, base + NvRegMIIData);
1032                 reg |= NVREG_MIICTL_WRITE;
1033         }
1034         writel(reg, base + NvRegMIIControl);
1035
1036         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1037                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1038                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1039                                 dev->name, miireg, addr);
1040                 retval = -1;
1041         } else if (value != MII_READ) {
1042                 /* it was a write operation - fewer failures are detectable */
1043                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1044                                 dev->name, value, miireg, addr);
1045                 retval = 0;
1046         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1047                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1048                                 dev->name, miireg, addr);
1049                 retval = -1;
1050         } else {
1051                 retval = readl(base + NvRegMIIData);
1052                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1053                                 dev->name, miireg, addr, retval);
1054         }
1055
1056         return retval;
1057 }
1058
1059 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1060 {
1061         struct fe_priv *np = netdev_priv(dev);
1062         u32 miicontrol;
1063         unsigned int tries = 0;
1064
1065         miicontrol = BMCR_RESET | bmcr_setup;
1066         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1067                 return -1;
1068         }
1069
1070         /* wait for 500ms */
1071         msleep(500);
1072
1073         /* must wait till reset is deasserted */
1074         while (miicontrol & BMCR_RESET) {
1075                 msleep(10);
1076                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1077                 /* FIXME: 100 tries seem excessive */
1078                 if (tries++ > 100)
1079                         return -1;
1080         }
1081         return 0;
1082 }
1083
1084 static int phy_init(struct net_device *dev)
1085 {
1086         struct fe_priv *np = get_nvpriv(dev);
1087         u8 __iomem *base = get_hwbase(dev);
1088         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1089
1090         /* phy errata for E3016 phy */
1091         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1092                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1093                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1094                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1095                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1096                         return PHY_ERROR;
1097                 }
1098         }
1099
1100         /* set advertise register */
1101         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1102         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1103         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1104                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1105                 return PHY_ERROR;
1106         }
1107
1108         /* get phy interface type */
1109         phyinterface = readl(base + NvRegPhyInterface);
1110
1111         /* see if gigabit phy */
1112         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1113         if (mii_status & PHY_GIGABIT) {
1114                 np->gigabit = PHY_GIGABIT;
1115                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1116                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1117                 if (phyinterface & PHY_RGMII)
1118                         mii_control_1000 |= ADVERTISE_1000FULL;
1119                 else
1120                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1121
1122                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1123                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1124                         return PHY_ERROR;
1125                 }
1126         }
1127         else
1128                 np->gigabit = 0;
1129
1130         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1131         mii_control |= BMCR_ANENABLE;
1132
1133         /* reset the phy
1134          * (certain phys need bmcr to be setup with reset)
1135          */
1136         if (phy_reset(dev, mii_control)) {
1137                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1138                 return PHY_ERROR;
1139         }
1140
1141         /* phy vendor specific configuration */
1142         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1143                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1144                 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
1145                 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
1146                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1147                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1148                         return PHY_ERROR;
1149                 }
1150                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1151                 phy_reserved |= PHY_INIT5;
1152                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1153                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1154                         return PHY_ERROR;
1155                 }
1156         }
1157         if (np->phy_oui == PHY_OUI_CICADA) {
1158                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1159                 phy_reserved |= PHY_INIT6;
1160                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1161                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1162                         return PHY_ERROR;
1163                 }
1164         }
1165         /* some phys clear out pause advertisment on reset, set it back */
1166         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1167
1168         /* restart auto negotiation */
1169         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1170         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1171         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1172                 return PHY_ERROR;
1173         }
1174
1175         return 0;
1176 }
1177
1178 static void nv_start_rx(struct net_device *dev)
1179 {
1180         struct fe_priv *np = netdev_priv(dev);
1181         u8 __iomem *base = get_hwbase(dev);
1182         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1183
1184         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1185         /* Already running? Stop it. */
1186         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1187                 rx_ctrl &= ~NVREG_RCVCTL_START;
1188                 writel(rx_ctrl, base + NvRegReceiverControl);
1189                 pci_push(base);
1190         }
1191         writel(np->linkspeed, base + NvRegLinkSpeed);
1192         pci_push(base);
1193         rx_ctrl |= NVREG_RCVCTL_START;
1194         if (np->mac_in_use)
1195                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1196         writel(rx_ctrl, base + NvRegReceiverControl);
1197         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1198                                 dev->name, np->duplex, np->linkspeed);
1199         pci_push(base);
1200 }
1201
1202 static void nv_stop_rx(struct net_device *dev)
1203 {
1204         struct fe_priv *np = netdev_priv(dev);
1205         u8 __iomem *base = get_hwbase(dev);
1206         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1207
1208         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1209         if (!np->mac_in_use)
1210                 rx_ctrl &= ~NVREG_RCVCTL_START;
1211         else
1212                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1213         writel(rx_ctrl, base + NvRegReceiverControl);
1214         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1215                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1216                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1217
1218         udelay(NV_RXSTOP_DELAY2);
1219         if (!np->mac_in_use)
1220                 writel(0, base + NvRegLinkSpeed);
1221 }
1222
1223 static void nv_start_tx(struct net_device *dev)
1224 {
1225         struct fe_priv *np = netdev_priv(dev);
1226         u8 __iomem *base = get_hwbase(dev);
1227         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1228
1229         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1230         tx_ctrl |= NVREG_XMITCTL_START;
1231         if (np->mac_in_use)
1232                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1233         writel(tx_ctrl, base + NvRegTransmitterControl);
1234         pci_push(base);
1235 }
1236
1237 static void nv_stop_tx(struct net_device *dev)
1238 {
1239         struct fe_priv *np = netdev_priv(dev);
1240         u8 __iomem *base = get_hwbase(dev);
1241         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1242
1243         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1244         if (!np->mac_in_use)
1245                 tx_ctrl &= ~NVREG_XMITCTL_START;
1246         else
1247                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1248         writel(tx_ctrl, base + NvRegTransmitterControl);
1249         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1250                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1251                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1252
1253         udelay(NV_TXSTOP_DELAY2);
1254         if (!np->mac_in_use)
1255                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1256                        base + NvRegTransmitPoll);
1257 }
1258
1259 static void nv_txrx_reset(struct net_device *dev)
1260 {
1261         struct fe_priv *np = netdev_priv(dev);
1262         u8 __iomem *base = get_hwbase(dev);
1263
1264         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1265         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1266         pci_push(base);
1267         udelay(NV_TXRX_RESET_DELAY);
1268         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1269         pci_push(base);
1270 }
1271
1272 static void nv_mac_reset(struct net_device *dev)
1273 {
1274         struct fe_priv *np = netdev_priv(dev);
1275         u8 __iomem *base = get_hwbase(dev);
1276
1277         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1278         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1279         pci_push(base);
1280         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1281         pci_push(base);
1282         udelay(NV_MAC_RESET_DELAY);
1283         writel(0, base + NvRegMacReset);
1284         pci_push(base);
1285         udelay(NV_MAC_RESET_DELAY);
1286         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1287         pci_push(base);
1288 }
1289
1290 static void nv_get_hw_stats(struct net_device *dev)
1291 {
1292         struct fe_priv *np = netdev_priv(dev);
1293         u8 __iomem *base = get_hwbase(dev);
1294
1295         np->estats.tx_bytes += readl(base + NvRegTxCnt);
1296         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1297         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1298         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1299         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1300         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1301         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1302         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1303         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1304         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1305         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1306         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1307         np->estats.rx_runt += readl(base + NvRegRxRunt);
1308         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1309         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1310         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1311         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1312         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1313         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1314         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1315         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1316         np->estats.rx_packets =
1317                 np->estats.rx_unicast +
1318                 np->estats.rx_multicast +
1319                 np->estats.rx_broadcast;
1320         np->estats.rx_errors_total =
1321                 np->estats.rx_crc_errors +
1322                 np->estats.rx_over_errors +
1323                 np->estats.rx_frame_error +
1324                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1325                 np->estats.rx_late_collision +
1326                 np->estats.rx_runt +
1327                 np->estats.rx_frame_too_long;
1328         np->estats.tx_errors_total =
1329                 np->estats.tx_late_collision +
1330                 np->estats.tx_fifo_errors +
1331                 np->estats.tx_carrier_errors +
1332                 np->estats.tx_excess_deferral +
1333                 np->estats.tx_retry_error;
1334
1335         if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1336                 np->estats.tx_deferral += readl(base + NvRegTxDef);
1337                 np->estats.tx_packets += readl(base + NvRegTxFrame);
1338                 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1339                 np->estats.tx_pause += readl(base + NvRegTxPause);
1340                 np->estats.rx_pause += readl(base + NvRegRxPause);
1341                 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1342         }
1343 }
1344
1345 /*
1346  * nv_get_stats: dev->get_stats function
1347  * Get latest stats value from the nic.
1348  * Called with read_lock(&dev_base_lock) held for read -
1349  * only synchronized against unregister_netdevice.
1350  */
1351 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1352 {
1353         struct fe_priv *np = netdev_priv(dev);
1354
1355         /* If the nic supports hw counters then retrieve latest values */
1356         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2)) {
1357                 nv_get_hw_stats(dev);
1358
1359                 /* copy to net_device stats */
1360                 np->stats.tx_bytes = np->estats.tx_bytes;
1361                 np->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1362                 np->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1363                 np->stats.rx_crc_errors = np->estats.rx_crc_errors;
1364                 np->stats.rx_over_errors = np->estats.rx_over_errors;
1365                 np->stats.rx_errors = np->estats.rx_errors_total;
1366                 np->stats.tx_errors = np->estats.tx_errors_total;
1367         }
1368         return &np->stats;
1369 }
1370
1371 /*
1372  * nv_alloc_rx: fill rx ring entries.
1373  * Return 1 if the allocations for the skbs failed and the
1374  * rx engine is without Available descriptors
1375  */
1376 static int nv_alloc_rx(struct net_device *dev)
1377 {
1378         struct fe_priv *np = netdev_priv(dev);
1379         struct ring_desc* less_rx;
1380
1381         less_rx = np->get_rx.orig;
1382         if (less_rx-- == np->first_rx.orig)
1383                 less_rx = np->last_rx.orig;
1384
1385         while (np->put_rx.orig != less_rx) {
1386                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1387                 if (skb) {
1388                         skb->dev = dev;
1389                         np->put_rx_ctx->skb = skb;
1390                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev, skb->data,
1391                                                              skb->end-skb->data, PCI_DMA_FROMDEVICE);
1392                         np->put_rx_ctx->dma_len = skb->end-skb->data;
1393                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1394                         wmb();
1395                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1396                         if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1397                                 np->put_rx.orig = np->first_rx.orig;
1398                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1399                                 np->put_rx_ctx = np->first_rx_ctx;
1400                 } else {
1401                         return 1;
1402                 }
1403         }
1404         return 0;
1405 }
1406
1407 static int nv_alloc_rx_optimized(struct net_device *dev)
1408 {
1409         struct fe_priv *np = netdev_priv(dev);
1410         struct ring_desc_ex* less_rx;
1411
1412         less_rx = np->get_rx.ex;
1413         if (less_rx-- == np->first_rx.ex)
1414                 less_rx = np->last_rx.ex;
1415
1416         while (np->put_rx.ex != less_rx) {
1417                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1418                 if (skb) {
1419                         skb->dev = dev;
1420                         np->put_rx_ctx->skb = skb;
1421                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev, skb->data,
1422                                                              skb->end-skb->data, PCI_DMA_FROMDEVICE);
1423                         np->put_rx_ctx->dma_len = skb->end-skb->data;
1424                         np->put_rx.ex->bufhigh = cpu_to_le64(np->put_rx_ctx->dma) >> 32;
1425                         np->put_rx.ex->buflow = cpu_to_le64(np->put_rx_ctx->dma) & 0x0FFFFFFFF;
1426                         wmb();
1427                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1428                         if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1429                                 np->put_rx.ex = np->first_rx.ex;
1430                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1431                                 np->put_rx_ctx = np->first_rx_ctx;
1432                 } else {
1433                         return 1;
1434                 }
1435         }
1436         return 0;
1437 }
1438
1439 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1440 #ifdef CONFIG_FORCEDETH_NAPI
1441 static void nv_do_rx_refill(unsigned long data)
1442 {
1443         struct net_device *dev = (struct net_device *) data;
1444
1445         /* Just reschedule NAPI rx processing */
1446         netif_rx_schedule(dev);
1447 }
1448 #else
1449 static void nv_do_rx_refill(unsigned long data)
1450 {
1451         struct net_device *dev = (struct net_device *) data;
1452         struct fe_priv *np = netdev_priv(dev);
1453         int retcode;
1454
1455         if (!using_multi_irqs(dev)) {
1456                 if (np->msi_flags & NV_MSI_X_ENABLED)
1457                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1458                 else
1459                         disable_irq(dev->irq);
1460         } else {
1461                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1462         }
1463         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1464                 retcode = nv_alloc_rx(dev);
1465         else
1466                 retcode = nv_alloc_rx_optimized(dev);
1467         if (retcode) {
1468                 spin_lock_irq(&np->lock);
1469                 if (!np->in_shutdown)
1470                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1471                 spin_unlock_irq(&np->lock);
1472         }
1473         if (!using_multi_irqs(dev)) {
1474                 if (np->msi_flags & NV_MSI_X_ENABLED)
1475                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1476                 else
1477                         enable_irq(dev->irq);
1478         } else {
1479                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1480         }
1481 }
1482 #endif
1483
1484 static void nv_init_rx(struct net_device *dev)
1485 {
1486         struct fe_priv *np = netdev_priv(dev);
1487         int i;
1488         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1489         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1490                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1491         else
1492                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1493         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1494         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1495
1496         for (i = 0; i < np->rx_ring_size; i++) {
1497                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1498                         np->rx_ring.orig[i].flaglen = 0;
1499                         np->rx_ring.orig[i].buf = 0;
1500                 } else {
1501                         np->rx_ring.ex[i].flaglen = 0;
1502                         np->rx_ring.ex[i].txvlan = 0;
1503                         np->rx_ring.ex[i].bufhigh = 0;
1504                         np->rx_ring.ex[i].buflow = 0;
1505                 }
1506                 np->rx_skb[i].skb = NULL;
1507                 np->rx_skb[i].dma = 0;
1508         }
1509 }
1510
1511 static void nv_init_tx(struct net_device *dev)
1512 {
1513         struct fe_priv *np = netdev_priv(dev);
1514         int i;
1515         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1516         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1517                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1518         else
1519                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1520         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1521         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1522
1523         for (i = 0; i < np->tx_ring_size; i++) {
1524                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1525                         np->tx_ring.orig[i].flaglen = 0;
1526                         np->tx_ring.orig[i].buf = 0;
1527                 } else {
1528                         np->tx_ring.ex[i].flaglen = 0;
1529                         np->tx_ring.ex[i].txvlan = 0;
1530                         np->tx_ring.ex[i].bufhigh = 0;
1531                         np->tx_ring.ex[i].buflow = 0;
1532                 }
1533                 np->tx_skb[i].skb = NULL;
1534                 np->tx_skb[i].dma = 0;
1535         }
1536 }
1537
1538 static int nv_init_ring(struct net_device *dev)
1539 {
1540         struct fe_priv *np = netdev_priv(dev);
1541
1542         nv_init_tx(dev);
1543         nv_init_rx(dev);
1544         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1545                 return nv_alloc_rx(dev);
1546         else
1547                 return nv_alloc_rx_optimized(dev);
1548 }
1549
1550 static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
1551 {
1552         struct fe_priv *np = netdev_priv(dev);
1553
1554         if (tx_skb->dma) {
1555                 pci_unmap_page(np->pci_dev, tx_skb->dma,
1556                                tx_skb->dma_len,
1557                                PCI_DMA_TODEVICE);
1558                 tx_skb->dma = 0;
1559         }
1560         if (tx_skb->skb) {
1561                 dev_kfree_skb_any(tx_skb->skb);
1562                 tx_skb->skb = NULL;
1563                 return 1;
1564         } else {
1565                 return 0;
1566         }
1567 }
1568
1569 static void nv_drain_tx(struct net_device *dev)
1570 {
1571         struct fe_priv *np = netdev_priv(dev);
1572         unsigned int i;
1573
1574         for (i = 0; i < np->tx_ring_size; i++) {
1575                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1576                         np->tx_ring.orig[i].flaglen = 0;
1577                         np->tx_ring.orig[i].buf = 0;
1578                 } else {
1579                         np->tx_ring.ex[i].flaglen = 0;
1580                         np->tx_ring.ex[i].txvlan = 0;
1581                         np->tx_ring.ex[i].bufhigh = 0;
1582                         np->tx_ring.ex[i].buflow = 0;
1583                 }
1584                 if (nv_release_txskb(dev, &np->tx_skb[i]))
1585                         np->stats.tx_dropped++;
1586         }
1587 }
1588
1589 static void nv_drain_rx(struct net_device *dev)
1590 {
1591         struct fe_priv *np = netdev_priv(dev);
1592         int i;
1593
1594         for (i = 0; i < np->rx_ring_size; i++) {
1595                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1596                         np->rx_ring.orig[i].flaglen = 0;
1597                         np->rx_ring.orig[i].buf = 0;
1598                 } else {
1599                         np->rx_ring.ex[i].flaglen = 0;
1600                         np->rx_ring.ex[i].txvlan = 0;
1601                         np->rx_ring.ex[i].bufhigh = 0;
1602                         np->rx_ring.ex[i].buflow = 0;
1603                 }
1604                 wmb();
1605                 if (np->rx_skb[i].skb) {
1606                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1607                                                 np->rx_skb[i].skb->end-np->rx_skb[i].skb->data,
1608                                                 PCI_DMA_FROMDEVICE);
1609                         dev_kfree_skb(np->rx_skb[i].skb);
1610                         np->rx_skb[i].skb = NULL;
1611                 }
1612         }
1613 }
1614
1615 static void drain_ring(struct net_device *dev)
1616 {
1617         nv_drain_tx(dev);
1618         nv_drain_rx(dev);
1619 }
1620
1621 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1622 {
1623         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1624 }
1625
1626 /*
1627  * nv_start_xmit: dev->hard_start_xmit function
1628  * Called with netif_tx_lock held.
1629  */
1630 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1631 {
1632         struct fe_priv *np = netdev_priv(dev);
1633         u32 tx_flags = 0;
1634         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1635         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1636         unsigned int i;
1637         u32 offset = 0;
1638         u32 bcnt;
1639         u32 size = skb->len-skb->data_len;
1640         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1641         u32 empty_slots;
1642         struct ring_desc* put_tx;
1643         struct ring_desc* start_tx;
1644         struct ring_desc* prev_tx;
1645         struct nv_skb_map* prev_tx_ctx;
1646
1647         /* add fragments to entries count */
1648         for (i = 0; i < fragments; i++) {
1649                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1650                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1651         }
1652
1653         empty_slots = nv_get_empty_tx_slots(np);
1654         if (unlikely(empty_slots <= entries)) {
1655                 spin_lock_irq(&np->lock);
1656                 netif_stop_queue(dev);
1657                 np->tx_stop = 1;
1658                 spin_unlock_irq(&np->lock);
1659                 return NETDEV_TX_BUSY;
1660         }
1661
1662         start_tx = put_tx = np->put_tx.orig;
1663
1664         /* setup the header buffer */
1665         do {
1666                 prev_tx = put_tx;
1667                 prev_tx_ctx = np->put_tx_ctx;
1668                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1669                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1670                                                 PCI_DMA_TODEVICE);
1671                 np->put_tx_ctx->dma_len = bcnt;
1672                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
1673                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1674
1675                 tx_flags = np->tx_flags;
1676                 offset += bcnt;
1677                 size -= bcnt;
1678                 if (unlikely(put_tx++ == np->last_tx.orig))
1679                         put_tx = np->first_tx.orig;
1680                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1681                         np->put_tx_ctx = np->first_tx_ctx;
1682         } while (size);
1683
1684         /* setup the fragments */
1685         for (i = 0; i < fragments; i++) {
1686                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1687                 u32 size = frag->size;
1688                 offset = 0;
1689
1690                 do {
1691                         prev_tx = put_tx;
1692                         prev_tx_ctx = np->put_tx_ctx;
1693                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1694                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1695                                                            PCI_DMA_TODEVICE);
1696                         np->put_tx_ctx->dma_len = bcnt;
1697                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
1698                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1699
1700                         offset += bcnt;
1701                         size -= bcnt;
1702                         if (unlikely(put_tx++ == np->last_tx.orig))
1703                                 put_tx = np->first_tx.orig;
1704                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1705                                 np->put_tx_ctx = np->first_tx_ctx;
1706                 } while (size);
1707         }
1708
1709         /* set last fragment flag  */
1710         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
1711
1712         /* save skb in this slot's context area */
1713         prev_tx_ctx->skb = skb;
1714
1715         if (skb_is_gso(skb))
1716                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1717         else
1718                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1719                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1720
1721         spin_lock_irq(&np->lock);
1722
1723         /* set tx flags */
1724         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1725         np->put_tx.orig = put_tx;
1726
1727         spin_unlock_irq(&np->lock);
1728
1729         dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
1730                 dev->name, entries, tx_flags_extra);
1731         {
1732                 int j;
1733                 for (j=0; j<64; j++) {
1734                         if ((j%16) == 0)
1735                                 dprintk("\n%03x:", j);
1736                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1737                 }
1738                 dprintk("\n");
1739         }
1740
1741         dev->trans_start = jiffies;
1742         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1743         return NETDEV_TX_OK;
1744 }
1745
1746 static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
1747 {
1748         struct fe_priv *np = netdev_priv(dev);
1749         u32 tx_flags = 0;
1750         u32 tx_flags_extra;
1751         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1752         unsigned int i;
1753         u32 offset = 0;
1754         u32 bcnt;
1755         u32 size = skb->len-skb->data_len;
1756         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1757         u32 empty_slots;
1758         struct ring_desc_ex* put_tx;
1759         struct ring_desc_ex* start_tx;
1760         struct ring_desc_ex* prev_tx;
1761         struct nv_skb_map* prev_tx_ctx;
1762
1763         /* add fragments to entries count */
1764         for (i = 0; i < fragments; i++) {
1765                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1766                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1767         }
1768
1769         empty_slots = nv_get_empty_tx_slots(np);
1770         if (unlikely(empty_slots <= entries)) {
1771                 spin_lock_irq(&np->lock);
1772                 netif_stop_queue(dev);
1773                 np->tx_stop = 1;
1774                 spin_unlock_irq(&np->lock);
1775                 return NETDEV_TX_BUSY;
1776         }
1777
1778         start_tx = put_tx = np->put_tx.ex;
1779
1780         /* setup the header buffer */
1781         do {
1782                 prev_tx = put_tx;
1783                 prev_tx_ctx = np->put_tx_ctx;
1784                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1785                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1786                                                 PCI_DMA_TODEVICE);
1787                 np->put_tx_ctx->dma_len = bcnt;
1788                 put_tx->bufhigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32;
1789                 put_tx->buflow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF;
1790                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1791
1792                 tx_flags = NV_TX2_VALID;
1793                 offset += bcnt;
1794                 size -= bcnt;
1795                 if (unlikely(put_tx++ == np->last_tx.ex))
1796                         put_tx = np->first_tx.ex;
1797                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1798                         np->put_tx_ctx = np->first_tx_ctx;
1799         } while (size);
1800
1801         /* setup the fragments */
1802         for (i = 0; i < fragments; i++) {
1803                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1804                 u32 size = frag->size;
1805                 offset = 0;
1806
1807                 do {
1808                         prev_tx = put_tx;
1809                         prev_tx_ctx = np->put_tx_ctx;
1810                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1811                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1812                                                            PCI_DMA_TODEVICE);
1813                         np->put_tx_ctx->dma_len = bcnt;
1814                         put_tx->bufhigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32;
1815                         put_tx->buflow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF;
1816                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1817
1818                         offset += bcnt;
1819                         size -= bcnt;
1820                         if (unlikely(put_tx++ == np->last_tx.ex))
1821                                 put_tx = np->first_tx.ex;
1822                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1823                                 np->put_tx_ctx = np->first_tx_ctx;
1824                 } while (size);
1825         }
1826
1827         /* set last fragment flag  */
1828         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
1829
1830         /* save skb in this slot's context area */
1831         prev_tx_ctx->skb = skb;
1832
1833         if (skb_is_gso(skb))
1834                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1835         else
1836                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1837                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1838
1839         /* vlan tag */
1840         if (likely(!np->vlangrp)) {
1841                 start_tx->txvlan = 0;
1842         } else {
1843                 if (vlan_tx_tag_present(skb))
1844                         start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
1845                 else
1846                         start_tx->txvlan = 0;
1847         }
1848
1849         spin_lock_irq(&np->lock);
1850
1851         /* set tx flags */
1852         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1853         np->put_tx.ex = put_tx;
1854
1855         spin_unlock_irq(&np->lock);
1856
1857         dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
1858                 dev->name, entries, tx_flags_extra);
1859         {
1860                 int j;
1861                 for (j=0; j<64; j++) {
1862                         if ((j%16) == 0)
1863                                 dprintk("\n%03x:", j);
1864                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1865                 }
1866                 dprintk("\n");
1867         }
1868
1869         dev->trans_start = jiffies;
1870         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1871         return NETDEV_TX_OK;
1872 }
1873
1874 /*
1875  * nv_tx_done: check for completed packets, release the skbs.
1876  *
1877  * Caller must own np->lock.
1878  */
1879 static void nv_tx_done(struct net_device *dev)
1880 {
1881         struct fe_priv *np = netdev_priv(dev);
1882         u32 flags;
1883         struct ring_desc* orig_get_tx = np->get_tx.orig;
1884
1885         while ((np->get_tx.orig != np->put_tx.orig) &&
1886                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID)) {
1887
1888                 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
1889                                         dev->name, flags);
1890
1891                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
1892                                np->get_tx_ctx->dma_len,
1893                                PCI_DMA_TODEVICE);
1894                 np->get_tx_ctx->dma = 0;
1895
1896                 if (np->desc_ver == DESC_VER_1) {
1897                         if (flags & NV_TX_LASTPACKET) {
1898                                 if (flags & NV_TX_ERROR) {
1899                                         if (flags & NV_TX_UNDERFLOW)
1900                                                 np->stats.tx_fifo_errors++;
1901                                         if (flags & NV_TX_CARRIERLOST)
1902                                                 np->stats.tx_carrier_errors++;
1903                                         np->stats.tx_errors++;
1904                                 } else {
1905                                         np->stats.tx_packets++;
1906                                         np->stats.tx_bytes += np->get_tx_ctx->skb->len;
1907                                 }
1908                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
1909                                 np->get_tx_ctx->skb = NULL;
1910                         }
1911                 } else {
1912                         if (flags & NV_TX2_LASTPACKET) {
1913                                 if (flags & NV_TX2_ERROR) {
1914                                         if (flags & NV_TX2_UNDERFLOW)
1915                                                 np->stats.tx_fifo_errors++;
1916                                         if (flags & NV_TX2_CARRIERLOST)
1917                                                 np->stats.tx_carrier_errors++;
1918                                         np->stats.tx_errors++;
1919                                 } else {
1920                                         np->stats.tx_packets++;
1921                                         np->stats.tx_bytes += np->get_tx_ctx->skb->len;
1922                                 }
1923                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
1924                                 np->get_tx_ctx->skb = NULL;
1925                         }
1926                 }
1927                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
1928                         np->get_tx.orig = np->first_tx.orig;
1929                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
1930                         np->get_tx_ctx = np->first_tx_ctx;
1931         }
1932         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
1933                 np->tx_stop = 0;
1934                 netif_wake_queue(dev);
1935         }
1936 }
1937
1938 static void nv_tx_done_optimized(struct net_device *dev, int limit)
1939 {
1940         struct fe_priv *np = netdev_priv(dev);
1941         u32 flags;
1942         struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
1943
1944         while ((np->get_tx.ex != np->put_tx.ex) &&
1945                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
1946                (limit-- > 0)) {
1947
1948                 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
1949                                         dev->name, flags);
1950
1951                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
1952                                np->get_tx_ctx->dma_len,
1953                                PCI_DMA_TODEVICE);
1954                 np->get_tx_ctx->dma = 0;
1955
1956                 if (flags & NV_TX2_LASTPACKET) {
1957                         if (!(flags & NV_TX2_ERROR))
1958                                 np->stats.tx_packets++;
1959                         dev_kfree_skb_any(np->get_tx_ctx->skb);
1960                         np->get_tx_ctx->skb = NULL;
1961                 }
1962                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
1963                         np->get_tx.ex = np->first_tx.ex;
1964                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
1965                         np->get_tx_ctx = np->first_tx_ctx;
1966         }
1967         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
1968                 np->tx_stop = 0;
1969                 netif_wake_queue(dev);
1970         }
1971 }
1972
1973 /*
1974  * nv_tx_timeout: dev->tx_timeout function
1975  * Called with netif_tx_lock held.
1976  */
1977 static void nv_tx_timeout(struct net_device *dev)
1978 {
1979         struct fe_priv *np = netdev_priv(dev);
1980         u8 __iomem *base = get_hwbase(dev);
1981         u32 status;
1982
1983         if (np->msi_flags & NV_MSI_X_ENABLED)
1984                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
1985         else
1986                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1987
1988         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
1989
1990         {
1991                 int i;
1992
1993                 printk(KERN_INFO "%s: Ring at %lx\n",
1994                        dev->name, (unsigned long)np->ring_addr);
1995                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1996                 for (i=0;i<=np->register_size;i+= 32) {
1997                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1998                                         i,
1999                                         readl(base + i + 0), readl(base + i + 4),
2000                                         readl(base + i + 8), readl(base + i + 12),
2001                                         readl(base + i + 16), readl(base + i + 20),
2002                                         readl(base + i + 24), readl(base + i + 28));
2003                 }
2004                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
2005                 for (i=0;i<np->tx_ring_size;i+= 4) {
2006                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
2007                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2008                                        i,
2009                                        le32_to_cpu(np->tx_ring.orig[i].buf),
2010                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
2011                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
2012                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2013                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
2014                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2015                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
2016                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2017                         } else {
2018                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2019                                        i,
2020                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2021                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
2022                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
2023                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2024                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2025                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2026                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2027                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2028                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2029                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2030                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2031                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2032                         }
2033                 }
2034         }
2035
2036         spin_lock_irq(&np->lock);
2037
2038         /* 1) stop tx engine */
2039         nv_stop_tx(dev);
2040
2041         /* 2) check that the packets were not sent already: */
2042         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2043                 nv_tx_done(dev);
2044         else
2045                 nv_tx_done_optimized(dev, np->tx_ring_size);
2046
2047         /* 3) if there are dead entries: clear everything */
2048         if (np->get_tx_ctx != np->put_tx_ctx) {
2049                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
2050                 nv_drain_tx(dev);
2051                 nv_init_tx(dev);
2052                 setup_hw_rings(dev, NV_SETUP_TX_RING);
2053                 netif_wake_queue(dev);
2054         }
2055
2056         /* 4) restart tx engine */
2057         nv_start_tx(dev);
2058         spin_unlock_irq(&np->lock);
2059 }
2060
2061 /*
2062  * Called when the nic notices a mismatch between the actual data len on the
2063  * wire and the len indicated in the 802 header
2064  */
2065 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2066 {
2067         int hdrlen;     /* length of the 802 header */
2068         int protolen;   /* length as stored in the proto field */
2069
2070         /* 1) calculate len according to header */
2071         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2072                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2073                 hdrlen = VLAN_HLEN;
2074         } else {
2075                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2076                 hdrlen = ETH_HLEN;
2077         }
2078         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2079                                 dev->name, datalen, protolen, hdrlen);
2080         if (protolen > ETH_DATA_LEN)
2081                 return datalen; /* Value in proto field not a len, no checks possible */
2082
2083         protolen += hdrlen;
2084         /* consistency checks: */
2085         if (datalen > ETH_ZLEN) {
2086                 if (datalen >= protolen) {
2087                         /* more data on wire than in 802 header, trim of
2088                          * additional data.
2089                          */
2090                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2091                                         dev->name, protolen);
2092                         return protolen;
2093                 } else {
2094                         /* less data on wire than mentioned in header.
2095                          * Discard the packet.
2096                          */
2097                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2098                                         dev->name);
2099                         return -1;
2100                 }
2101         } else {
2102                 /* short packet. Accept only if 802 values are also short */
2103                 if (protolen > ETH_ZLEN) {
2104                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2105                                         dev->name);
2106                         return -1;
2107                 }
2108                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2109                                 dev->name, datalen);
2110                 return datalen;
2111         }
2112 }
2113
2114 static int nv_rx_process(struct net_device *dev, int limit)
2115 {
2116         struct fe_priv *np = netdev_priv(dev);
2117         u32 flags;
2118         u32 rx_processed_cnt = 0;
2119         struct sk_buff *skb;
2120         int len;
2121
2122         while((np->get_rx.orig != np->put_rx.orig) &&
2123               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2124                 (rx_processed_cnt++ < limit)) {
2125
2126                 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2127                                         dev->name, flags);
2128
2129                 /*
2130                  * the packet is for us - immediately tear down the pci mapping.
2131                  * TODO: check if a prefetch of the first cacheline improves
2132                  * the performance.
2133                  */
2134                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2135                                 np->get_rx_ctx->dma_len,
2136                                 PCI_DMA_FROMDEVICE);
2137                 skb = np->get_rx_ctx->skb;
2138                 np->get_rx_ctx->skb = NULL;
2139
2140                 {
2141                         int j;
2142                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2143                         for (j=0; j<64; j++) {
2144                                 if ((j%16) == 0)
2145                                         dprintk("\n%03x:", j);
2146                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2147                         }
2148                         dprintk("\n");
2149                 }
2150                 /* look at what we actually got: */
2151                 if (np->desc_ver == DESC_VER_1) {
2152                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2153                                 len = flags & LEN_MASK_V1;
2154                                 if (unlikely(flags & NV_RX_ERROR)) {
2155                                         if (flags & NV_RX_ERROR4) {
2156                                                 len = nv_getlen(dev, skb->data, len);
2157                                                 if (len < 0) {
2158                                                         np->stats.rx_errors++;
2159                                                         dev_kfree_skb(skb);
2160                                                         goto next_pkt;
2161                                                 }
2162                                         }
2163                                         /* framing errors are soft errors */
2164                                         else if (flags & NV_RX_FRAMINGERR) {
2165                                                 if (flags & NV_RX_SUBSTRACT1) {
2166                                                         len--;
2167                                                 }
2168                                         }
2169                                         /* the rest are hard errors */
2170                                         else {
2171                                                 if (flags & NV_RX_MISSEDFRAME)
2172                                                         np->stats.rx_missed_errors++;
2173                                                 if (flags & NV_RX_CRCERR)
2174                                                         np->stats.rx_crc_errors++;
2175                                                 if (flags & NV_RX_OVERFLOW)
2176                                                         np->stats.rx_over_errors++;
2177                                                 np->stats.rx_errors++;
2178                                                 dev_kfree_skb(skb);
2179                                                 goto next_pkt;
2180                                         }
2181                                 }
2182                         } else {
2183                                 dev_kfree_skb(skb);
2184                                 goto next_pkt;
2185                         }
2186                 } else {
2187                         if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2188                                 len = flags & LEN_MASK_V2;
2189                                 if (unlikely(flags & NV_RX2_ERROR)) {
2190                                         if (flags & NV_RX2_ERROR4) {
2191                                                 len = nv_getlen(dev, skb->data, len);
2192                                                 if (len < 0) {
2193                                                         np->stats.rx_errors++;
2194                                                         dev_kfree_skb(skb);
2195                                                         goto next_pkt;
2196                                                 }
2197                                         }
2198                                         /* framing errors are soft errors */
2199                                         else if (flags & NV_RX2_FRAMINGERR) {
2200                                                 if (flags & NV_RX2_SUBSTRACT1) {
2201                                                         len--;
2202                                                 }
2203                                         }
2204                                         /* the rest are hard errors */
2205                                         else {
2206                                                 if (flags & NV_RX2_CRCERR)
2207                                                         np->stats.rx_crc_errors++;
2208                                                 if (flags & NV_RX2_OVERFLOW)
2209                                                         np->stats.rx_over_errors++;
2210                                                 np->stats.rx_errors++;
2211                                                 dev_kfree_skb(skb);
2212                                                 goto next_pkt;
2213                                         }
2214                                 }
2215                                 if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK2)/*ip and tcp */ {
2216                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2217                                 } else {
2218                                         if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK1 ||
2219                                             (flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK3) {
2220                                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2221                                         }
2222                                 }
2223                         } else {
2224                                 dev_kfree_skb(skb);
2225                                 goto next_pkt;
2226                         }
2227                 }
2228                 /* got a valid packet - forward it to the network core */
2229                 skb_put(skb, len);
2230                 skb->protocol = eth_type_trans(skb, dev);
2231                 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2232                                         dev->name, len, skb->protocol);
2233 #ifdef CONFIG_FORCEDETH_NAPI
2234                 netif_receive_skb(skb);
2235 #else
2236                 netif_rx(skb);
2237 #endif
2238                 dev->last_rx = jiffies;
2239                 np->stats.rx_packets++;
2240                 np->stats.rx_bytes += len;
2241 next_pkt:
2242                 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2243                         np->get_rx.orig = np->first_rx.orig;
2244                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2245                         np->get_rx_ctx = np->first_rx_ctx;
2246         }
2247
2248         return rx_processed_cnt;
2249 }
2250
2251 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2252 {
2253         struct fe_priv *np = netdev_priv(dev);
2254         u32 flags;
2255         u32 vlanflags = 0;
2256         u32 rx_processed_cnt = 0;
2257         struct sk_buff *skb;
2258         int len;
2259
2260         while((np->get_rx.ex != np->put_rx.ex) &&
2261               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2262               (rx_processed_cnt++ < limit)) {
2263
2264                 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2265                                         dev->name, flags);
2266
2267                 /*
2268                  * the packet is for us - immediately tear down the pci mapping.
2269                  * TODO: check if a prefetch of the first cacheline improves
2270                  * the performance.
2271                  */
2272                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2273                                 np->get_rx_ctx->dma_len,
2274                                 PCI_DMA_FROMDEVICE);
2275                 skb = np->get_rx_ctx->skb;
2276                 np->get_rx_ctx->skb = NULL;
2277
2278                 {
2279                         int j;
2280                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2281                         for (j=0; j<64; j++) {
2282                                 if ((j%16) == 0)
2283                                         dprintk("\n%03x:", j);
2284                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2285                         }
2286                         dprintk("\n");
2287                 }
2288                 /* look at what we actually got: */
2289                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2290                         len = flags & LEN_MASK_V2;
2291                         if (unlikely(flags & NV_RX2_ERROR)) {
2292                                 if (flags & NV_RX2_ERROR4) {
2293                                         len = nv_getlen(dev, skb->data, len);
2294                                         if (len < 0) {
2295                                                 dev_kfree_skb(skb);
2296                                                 goto next_pkt;
2297                                         }
2298                                 }
2299                                 /* framing errors are soft errors */
2300                                 else if (flags & NV_RX2_FRAMINGERR) {
2301                                         if (flags & NV_RX2_SUBSTRACT1) {
2302                                                 len--;
2303                                         }
2304                                 }
2305                                 /* the rest are hard errors */
2306                                 else {
2307                                         dev_kfree_skb(skb);
2308                                         goto next_pkt;
2309                                 }
2310                         }
2311
2312                         if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK2)/*ip and tcp */ {
2313                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2314                         } else {
2315                                 if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK1 ||
2316                                     (flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK3) {
2317                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2318                                 }
2319                         }
2320
2321                         /* got a valid packet - forward it to the network core */
2322                         skb_put(skb, len);
2323                         skb->protocol = eth_type_trans(skb, dev);
2324                         prefetch(skb->data);
2325
2326                         dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2327                                 dev->name, len, skb->protocol);
2328
2329                         if (likely(!np->vlangrp)) {
2330 #ifdef CONFIG_FORCEDETH_NAPI
2331                                 netif_receive_skb(skb);
2332 #else
2333                                 netif_rx(skb);
2334 #endif
2335                         } else {
2336                                 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2337                                 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2338 #ifdef CONFIG_FORCEDETH_NAPI
2339                                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
2340                                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
2341 #else
2342                                         vlan_hwaccel_rx(skb, np->vlangrp,
2343                                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
2344 #endif
2345                                 } else {
2346 #ifdef CONFIG_FORCEDETH_NAPI
2347                                         netif_receive_skb(skb);
2348 #else
2349                                         netif_rx(skb);
2350 #endif
2351                                 }
2352                         }
2353
2354                         dev->last_rx = jiffies;
2355                         np->stats.rx_packets++;
2356                         np->stats.rx_bytes += len;
2357                 } else {
2358                         dev_kfree_skb(skb);
2359                 }
2360 next_pkt:
2361                 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2362                         np->get_rx.ex = np->first_rx.ex;
2363                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2364                         np->get_rx_ctx = np->first_rx_ctx;
2365         }
2366
2367         return rx_processed_cnt;
2368 }
2369
2370 static void set_bufsize(struct net_device *dev)
2371 {
2372         struct fe_priv *np = netdev_priv(dev);
2373
2374         if (dev->mtu <= ETH_DATA_LEN)
2375                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2376         else
2377                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2378 }
2379
2380 /*
2381  * nv_change_mtu: dev->change_mtu function
2382  * Called with dev_base_lock held for read.
2383  */
2384 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2385 {
2386         struct fe_priv *np = netdev_priv(dev);
2387         int old_mtu;
2388
2389         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2390                 return -EINVAL;
2391
2392         old_mtu = dev->mtu;
2393         dev->mtu = new_mtu;
2394
2395         /* return early if the buffer sizes will not change */
2396         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2397                 return 0;
2398         if (old_mtu == new_mtu)
2399                 return 0;
2400
2401         /* synchronized against open : rtnl_lock() held by caller */
2402         if (netif_running(dev)) {
2403                 u8 __iomem *base = get_hwbase(dev);
2404                 /*
2405                  * It seems that the nic preloads valid ring entries into an
2406                  * internal buffer. The procedure for flushing everything is
2407                  * guessed, there is probably a simpler approach.
2408                  * Changing the MTU is a rare event, it shouldn't matter.
2409                  */
2410                 nv_disable_irq(dev);
2411                 netif_tx_lock_bh(dev);
2412                 spin_lock(&np->lock);
2413                 /* stop engines */
2414                 nv_stop_rx(dev);
2415                 nv_stop_tx(dev);
2416                 nv_txrx_reset(dev);
2417                 /* drain rx queue */
2418                 nv_drain_rx(dev);
2419                 nv_drain_tx(dev);
2420                 /* reinit driver view of the rx queue */
2421                 set_bufsize(dev);
2422                 if (nv_init_ring(dev)) {
2423                         if (!np->in_shutdown)
2424                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2425                 }
2426                 /* reinit nic view of the rx queue */
2427                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2428                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2429                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2430                         base + NvRegRingSizes);
2431                 pci_push(base);
2432                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2433                 pci_push(base);
2434
2435                 /* restart rx engine */
2436                 nv_start_rx(dev);
2437                 nv_start_tx(dev);
2438                 spin_unlock(&np->lock);
2439                 netif_tx_unlock_bh(dev);
2440                 nv_enable_irq(dev);
2441         }
2442         return 0;
2443 }
2444
2445 static void nv_copy_mac_to_hw(struct net_device *dev)
2446 {
2447         u8 __iomem *base = get_hwbase(dev);
2448         u32 mac[2];
2449
2450         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2451                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2452         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2453
2454         writel(mac[0], base + NvRegMacAddrA);
2455         writel(mac[1], base + NvRegMacAddrB);
2456 }
2457
2458 /*
2459  * nv_set_mac_address: dev->set_mac_address function
2460  * Called with rtnl_lock() held.
2461  */
2462 static int nv_set_mac_address(struct net_device *dev, void *addr)
2463 {
2464         struct fe_priv *np = netdev_priv(dev);
2465         struct sockaddr *macaddr = (struct sockaddr*)addr;
2466
2467         if (!is_valid_ether_addr(macaddr->sa_data))
2468                 return -EADDRNOTAVAIL;
2469
2470         /* synchronized against open : rtnl_lock() held by caller */
2471         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2472
2473         if (netif_running(dev)) {
2474                 netif_tx_lock_bh(dev);
2475                 spin_lock_irq(&np->lock);
2476
2477                 /* stop rx engine */
2478                 nv_stop_rx(dev);
2479
2480                 /* set mac address */
2481                 nv_copy_mac_to_hw(dev);
2482
2483                 /* restart rx engine */
2484                 nv_start_rx(dev);
2485                 spin_unlock_irq(&np->lock);
2486                 netif_tx_unlock_bh(dev);
2487         } else {
2488                 nv_copy_mac_to_hw(dev);
2489         }
2490         return 0;
2491 }
2492
2493 /*
2494  * nv_set_multicast: dev->set_multicast function
2495  * Called with netif_tx_lock held.
2496  */
2497 static void nv_set_multicast(struct net_device *dev)
2498 {
2499         struct fe_priv *np = netdev_priv(dev);
2500         u8 __iomem *base = get_hwbase(dev);
2501         u32 addr[2];
2502         u32 mask[2];
2503         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2504
2505         memset(addr, 0, sizeof(addr));
2506         memset(mask, 0, sizeof(mask));
2507
2508         if (dev->flags & IFF_PROMISC) {
2509                 pff |= NVREG_PFF_PROMISC;
2510         } else {
2511                 pff |= NVREG_PFF_MYADDR;
2512
2513                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2514                         u32 alwaysOff[2];
2515                         u32 alwaysOn[2];
2516
2517                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2518                         if (dev->flags & IFF_ALLMULTI) {
2519                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2520                         } else {
2521                                 struct dev_mc_list *walk;
2522
2523                                 walk = dev->mc_list;
2524                                 while (walk != NULL) {
2525                                         u32 a, b;
2526                                         a = le32_to_cpu(*(u32 *) walk->dmi_addr);
2527                                         b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
2528                                         alwaysOn[0] &= a;
2529                                         alwaysOff[0] &= ~a;
2530                                         alwaysOn[1] &= b;
2531                                         alwaysOff[1] &= ~b;
2532                                         walk = walk->next;
2533                                 }
2534                         }
2535                         addr[0] = alwaysOn[0];
2536                         addr[1] = alwaysOn[1];
2537                         mask[0] = alwaysOn[0] | alwaysOff[0];
2538                         mask[1] = alwaysOn[1] | alwaysOff[1];
2539                 }
2540         }
2541         addr[0] |= NVREG_MCASTADDRA_FORCE;
2542         pff |= NVREG_PFF_ALWAYS;
2543         spin_lock_irq(&np->lock);
2544         nv_stop_rx(dev);
2545         writel(addr[0], base + NvRegMulticastAddrA);
2546         writel(addr[1], base + NvRegMulticastAddrB);
2547         writel(mask[0], base + NvRegMulticastMaskA);
2548         writel(mask[1], base + NvRegMulticastMaskB);
2549         writel(pff, base + NvRegPacketFilterFlags);
2550         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2551                 dev->name);
2552         nv_start_rx(dev);
2553         spin_unlock_irq(&np->lock);
2554 }
2555
2556 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2557 {
2558         struct fe_priv *np = netdev_priv(dev);
2559         u8 __iomem *base = get_hwbase(dev);
2560
2561         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2562
2563         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2564                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2565                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2566                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2567                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2568                 } else {
2569                         writel(pff, base + NvRegPacketFilterFlags);
2570                 }
2571         }
2572         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2573                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2574                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2575                         writel(NVREG_TX_PAUSEFRAME_ENABLE,  base + NvRegTxPauseFrame);
2576                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2577                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2578                 } else {
2579                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
2580                         writel(regmisc, base + NvRegMisc1);
2581                 }
2582         }
2583 }
2584
2585 /**
2586  * nv_update_linkspeed: Setup the MAC according to the link partner
2587  * @dev: Network device to be configured
2588  *
2589  * The function queries the PHY and checks if there is a link partner.
2590  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2591  * set to 10 MBit HD.
2592  *
2593  * The function returns 0 if there is no link partner and 1 if there is
2594  * a good link partner.
2595  */
2596 static int nv_update_linkspeed(struct net_device *dev)
2597 {
2598         struct fe_priv *np = netdev_priv(dev);
2599         u8 __iomem *base = get_hwbase(dev);
2600         int adv = 0;
2601         int lpa = 0;
2602         int adv_lpa, adv_pause, lpa_pause;
2603         int newls = np->linkspeed;
2604         int newdup = np->duplex;
2605         int mii_status;
2606         int retval = 0;
2607         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
2608
2609         /* BMSR_LSTATUS is latched, read it twice:
2610          * we want the current value.
2611          */
2612         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2613         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2614
2615         if (!(mii_status & BMSR_LSTATUS)) {
2616                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2617                                 dev->name);
2618                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2619                 newdup = 0;
2620                 retval = 0;
2621                 goto set_speed;
2622         }
2623
2624         if (np->autoneg == 0) {
2625                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2626                                 dev->name, np->fixed_mode);
2627                 if (np->fixed_mode & LPA_100FULL) {
2628                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2629                         newdup = 1;
2630                 } else if (np->fixed_mode & LPA_100HALF) {
2631                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2632                         newdup = 0;
2633                 } else if (np->fixed_mode & LPA_10FULL) {
2634                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2635                         newdup = 1;
2636                 } else {
2637                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2638                         newdup = 0;
2639                 }
2640                 retval = 1;
2641                 goto set_speed;
2642         }
2643         /* check auto negotiation is complete */
2644         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2645                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2646                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2647                 newdup = 0;
2648                 retval = 0;
2649                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2650                 goto set_speed;
2651         }
2652
2653         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2654         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2655         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2656                                 dev->name, adv, lpa);
2657
2658         retval = 1;
2659         if (np->gigabit == PHY_GIGABIT) {
2660                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2661                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2662
2663                 if ((control_1000 & ADVERTISE_1000FULL) &&
2664                         (status_1000 & LPA_1000FULL)) {
2665                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2666                                 dev->name);
2667                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2668                         newdup = 1;
2669                         goto set_speed;
2670                 }
2671         }
2672
2673         /* FIXME: handle parallel detection properly */
2674         adv_lpa = lpa & adv;
2675         if (adv_lpa & LPA_100FULL) {
2676                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2677                 newdup = 1;
2678         } else if (adv_lpa & LPA_100HALF) {
2679                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2680                 newdup = 0;
2681         } else if (adv_lpa & LPA_10FULL) {
2682                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2683                 newdup = 1;
2684         } else if (adv_lpa & LPA_10HALF) {
2685                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2686                 newdup = 0;
2687         } else {
2688                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2689                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2690                 newdup = 0;
2691         }
2692
2693 set_speed:
2694         if (np->duplex == newdup && np->linkspeed == newls)
2695                 return retval;
2696
2697         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2698                         dev->name, np->linkspeed, np->duplex, newls, newdup);
2699
2700         np->duplex = newdup;
2701         np->linkspeed = newls;
2702
2703         if (np->gigabit == PHY_GIGABIT) {
2704                 phyreg = readl(base + NvRegRandomSeed);
2705                 phyreg &= ~(0x3FF00);
2706                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2707                         phyreg |= NVREG_RNDSEED_FORCE3;
2708                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2709                         phyreg |= NVREG_RNDSEED_FORCE2;
2710                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2711                         phyreg |= NVREG_RNDSEED_FORCE;
2712                 writel(phyreg, base + NvRegRandomSeed);
2713         }
2714
2715         phyreg = readl(base + NvRegPhyInterface);
2716         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2717         if (np->duplex == 0)
2718                 phyreg |= PHY_HALF;
2719         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2720                 phyreg |= PHY_100;
2721         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2722                 phyreg |= PHY_1000;
2723         writel(phyreg, base + NvRegPhyInterface);
2724
2725         if (phyreg & PHY_RGMII) {
2726                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2727                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
2728                 else
2729                         txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
2730         } else {
2731                 txreg = NVREG_TX_DEFERRAL_DEFAULT;
2732         }
2733         writel(txreg, base + NvRegTxDeferral);
2734
2735         if (np->desc_ver == DESC_VER_1) {
2736                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
2737         } else {
2738                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2739                         txreg = NVREG_TX_WM_DESC2_3_1000;
2740                 else
2741                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
2742         }
2743         writel(txreg, base + NvRegTxWatermark);
2744
2745         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2746                 base + NvRegMisc1);
2747         pci_push(base);
2748         writel(np->linkspeed, base + NvRegLinkSpeed);
2749         pci_push(base);
2750
2751         pause_flags = 0;
2752         /* setup pause frame */
2753         if (np->duplex != 0) {
2754                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
2755                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
2756                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
2757
2758                         switch (adv_pause) {
2759                         case ADVERTISE_PAUSE_CAP:
2760                                 if (lpa_pause & LPA_PAUSE_CAP) {
2761                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2762                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2763                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2764                                 }
2765                                 break;
2766                         case ADVERTISE_PAUSE_ASYM:
2767                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
2768                                 {
2769                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2770                                 }
2771                                 break;
2772                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
2773                                 if (lpa_pause & LPA_PAUSE_CAP)
2774                                 {
2775                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
2776                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2777                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2778                                 }
2779                                 if (lpa_pause == LPA_PAUSE_ASYM)
2780                                 {
2781                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2782                                 }
2783                                 break;
2784                         }
2785                 } else {
2786                         pause_flags = np->pause_flags;
2787                 }
2788         }
2789         nv_update_pause(dev, pause_flags);
2790
2791         return retval;
2792 }
2793
2794 static void nv_linkchange(struct net_device *dev)
2795 {
2796         if (nv_update_linkspeed(dev)) {
2797                 if (!netif_carrier_ok(dev)) {
2798                         netif_carrier_on(dev);
2799                         printk(KERN_INFO "%s: link up.\n", dev->name);
2800                         nv_start_rx(dev);
2801                 }
2802         } else {
2803                 if (netif_carrier_ok(dev)) {
2804                         netif_carrier_off(dev);
2805                         printk(KERN_INFO "%s: link down.\n", dev->name);
2806                         nv_stop_rx(dev);
2807                 }
2808         }
2809 }
2810
2811 static void nv_link_irq(struct net_device *dev)
2812 {
2813         u8 __iomem *base = get_hwbase(dev);
2814         u32 miistat;
2815
2816         miistat = readl(base + NvRegMIIStatus);
2817         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2818         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
2819
2820         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
2821                 nv_linkchange(dev);
2822         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
2823 }
2824
2825 static irqreturn_t nv_nic_irq(int foo, void *data)
2826 {
2827         struct net_device *dev = (struct net_device *) data;
2828         struct fe_priv *np = netdev_priv(dev);
2829         u8 __iomem *base = get_hwbase(dev);
2830         u32 events;
2831         int i;
2832
2833         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
2834
2835         for (i=0; ; i++) {
2836                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2837                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2838                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2839                 } else {
2840                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2841                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2842                 }
2843                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2844                 if (!(events & np->irqmask))
2845                         break;
2846
2847                 spin_lock(&np->lock);
2848                 nv_tx_done(dev);
2849                 spin_unlock(&np->lock);
2850
2851 #ifdef CONFIG_FORCEDETH_NAPI
2852                 if (events & NVREG_IRQ_RX_ALL) {
2853                         netif_rx_schedule(dev);
2854
2855                         /* Disable furthur receive irq's */
2856                         spin_lock(&np->lock);
2857                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
2858
2859                         if (np->msi_flags & NV_MSI_X_ENABLED)
2860                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2861                         else
2862                                 writel(np->irqmask, base + NvRegIrqMask);
2863                         spin_unlock(&np->lock);
2864                 }
2865 #else
2866                 if (nv_rx_process(dev, dev->weight)) {
2867                         if (unlikely(nv_alloc_rx(dev))) {
2868                                 spin_lock(&np->lock);
2869                                 if (!np->in_shutdown)
2870                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2871                                 spin_unlock(&np->lock);
2872                         }
2873                 }
2874 #endif
2875                 if (unlikely(events & NVREG_IRQ_LINK)) {
2876                         spin_lock(&np->lock);
2877                         nv_link_irq(dev);
2878                         spin_unlock(&np->lock);
2879                 }
2880                 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
2881                         spin_lock(&np->lock);
2882                         nv_linkchange(dev);
2883                         spin_unlock(&np->lock);
2884                         np->link_timeout = jiffies + LINK_TIMEOUT;
2885                 }
2886                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
2887                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2888                                                 dev->name, events);
2889                 }
2890                 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
2891                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2892                                                 dev->name, events);
2893                 }
2894                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
2895                         spin_lock(&np->lock);
2896                         /* disable interrupts on the nic */
2897                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
2898                                 writel(0, base + NvRegIrqMask);
2899                         else
2900                                 writel(np->irqmask, base + NvRegIrqMask);
2901                         pci_push(base);
2902
2903                         if (!np->in_shutdown) {
2904                                 np->nic_poll_irq = np->irqmask;
2905                                 np->recover_error = 1;
2906                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2907                         }
2908                         spin_unlock(&np->lock);
2909                         break;
2910                 }
2911                 if (unlikely(i > max_interrupt_work)) {
2912                         spin_lock(&np->lock);
2913                         /* disable interrupts on the nic */
2914                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
2915                                 writel(0, base + NvRegIrqMask);
2916                         else
2917                                 writel(np->irqmask, base + NvRegIrqMask);
2918                         pci_push(base);
2919
2920                         if (!np->in_shutdown) {
2921                                 np->nic_poll_irq = np->irqmask;
2922                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2923                         }
2924                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
2925                         spin_unlock(&np->lock);
2926                         break;
2927                 }
2928
2929         }
2930         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
2931
2932         return IRQ_RETVAL(i);
2933 }
2934
2935 #define TX_WORK_PER_LOOP  64
2936 #define RX_WORK_PER_LOOP  64
2937 /**
2938  * All _optimized functions are used to help increase performance
2939  * (reduce CPU and increase throughput). They use descripter version 3,
2940  * compiler directives, and reduce memory accesses.
2941  */
2942 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
2943 {
2944         struct net_device *dev = (struct net_device *) data;
2945         struct fe_priv *np = netdev_priv(dev);
2946         u8 __iomem *base = get_hwbase(dev);
2947         u32 events;
2948         int i;
2949
2950         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
2951
2952         for (i=0; ; i++) {
2953                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2954                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2955                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2956                 } else {
2957                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2958                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2959                 }
2960                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2961                 if (!(events & np->irqmask))
2962                         break;
2963
2964                 spin_lock(&np->lock);
2965                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
2966                 spin_unlock(&np->lock);
2967
2968 #ifdef CONFIG_FORCEDETH_NAPI
2969                 if (events & NVREG_IRQ_RX_ALL) {
2970                         netif_rx_schedule(dev);
2971
2972                         /* Disable furthur receive irq's */
2973                         spin_lock(&np->lock);
2974                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
2975
2976                         if (np->msi_flags & NV_MSI_X_ENABLED)
2977                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2978                         else
2979                                 writel(np->irqmask, base + NvRegIrqMask);
2980                         spin_unlock(&np->lock);
2981                 }
2982 #else
2983                 if (nv_rx_process_optimized(dev, dev->weight)) {
2984                         if (unlikely(nv_alloc_rx_optimized(dev))) {
2985                                 spin_lock(&np->lock);
2986                                 if (!np->in_shutdown)
2987                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2988                                 spin_unlock(&np->lock);
2989                         }
2990                 }
2991 #endif
2992                 if (unlikely(events & NVREG_IRQ_LINK)) {
2993                         spin_lock(&np->lock);
2994                         nv_link_irq(dev);
2995                         spin_unlock(&np->lock);
2996                 }
2997                 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
2998                         spin_lock(&np->lock);
2999                         nv_linkchange(dev);
3000                         spin_unlock(&np->lock);
3001                         np->link_timeout = jiffies + LINK_TIMEOUT;
3002                 }
3003                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3004                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3005                                                 dev->name, events);
3006                 }
3007                 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3008                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3009                                                 dev->name, events);
3010                 }
3011                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3012                         spin_lock(&np->lock);
3013                         /* disable interrupts on the nic */
3014                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3015                                 writel(0, base + NvRegIrqMask);
3016                         else
3017                                 writel(np->irqmask, base + NvRegIrqMask);
3018                         pci_push(base);
3019
3020                         if (!np->in_shutdown) {
3021                                 np->nic_poll_irq = np->irqmask;
3022                                 np->recover_error = 1;
3023                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3024                         }
3025                         spin_unlock(&np->lock);
3026                         break;
3027                 }
3028
3029                 if (unlikely(i > max_interrupt_work)) {
3030                         spin_lock(&np->lock);
3031                         /* disable interrupts on the nic */
3032                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3033                                 writel(0, base + NvRegIrqMask);
3034                         else
3035                                 writel(np->irqmask, base + NvRegIrqMask);
3036                         pci_push(base);
3037
3038                         if (!np->in_shutdown) {
3039                                 np->nic_poll_irq = np->irqmask;
3040                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3041                         }
3042                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3043                         spin_unlock(&np->lock);
3044                         break;
3045                 }
3046
3047         }
3048         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3049
3050         return IRQ_RETVAL(i);
3051 }
3052
3053 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3054 {
3055         struct net_device *dev = (struct net_device *) data;
3056         struct fe_priv *np = netdev_priv(dev);
3057         u8 __iomem *base = get_hwbase(dev);
3058         u32 events;
3059         int i;
3060         unsigned long flags;
3061
3062         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3063
3064         for (i=0; ; i++) {
3065                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3066                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3067                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3068                 if (!(events & np->irqmask))
3069                         break;
3070
3071                 spin_lock_irqsave(&np->lock, flags);
3072                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3073                 spin_unlock_irqrestore(&np->lock, flags);
3074
3075                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3076                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3077                                                 dev->name, events);
3078                 }
3079                 if (unlikely(i > max_interrupt_work)) {
3080                         spin_lock_irqsave(&np->lock, flags);
3081                         /* disable interrupts on the nic */
3082                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3083                         pci_push(base);
3084
3085                         if (!np->in_shutdown) {
3086                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3087                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3088                         }
3089                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3090                         spin_unlock_irqrestore(&np->lock, flags);
3091                         break;
3092                 }
3093
3094         }
3095         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3096
3097         return IRQ_RETVAL(i);
3098 }
3099
3100 #ifdef CONFIG_FORCEDETH_NAPI
3101 static int nv_napi_poll(struct net_device *dev, int *budget)
3102 {
3103         int pkts, limit = min(*budget, dev->quota);
3104         struct fe_priv *np = netdev_priv(dev);
3105         u8 __iomem *base = get_hwbase(dev);
3106         unsigned long flags;
3107         int retcode;
3108
3109         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3110                 pkts = nv_rx_process(dev, limit);
3111                 retcode = nv_alloc_rx(dev);
3112         } else {
3113                 pkts = nv_rx_process_optimized(dev, limit);
3114                 retcode = nv_alloc_rx_optimized(dev);
3115         }
3116
3117         if (retcode) {
3118                 spin_lock_irqsave(&np->lock, flags);
3119                 if (!np->in_shutdown)
3120                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3121                 spin_unlock_irqrestore(&np->lock, flags);
3122         }
3123
3124         if (pkts < limit) {
3125                 /* all done, no more packets present */
3126                 netif_rx_complete(dev);
3127
3128                 /* re-enable receive interrupts */
3129                 spin_lock_irqsave(&np->lock, flags);
3130
3131                 np->irqmask |= NVREG_IRQ_RX_ALL;
3132                 if (np->msi_flags & NV_MSI_X_ENABLED)
3133                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3134                 else
3135                         writel(np->irqmask, base + NvRegIrqMask);
3136
3137                 spin_unlock_irqrestore(&np->lock, flags);
3138                 return 0;
3139         } else {
3140                 /* used up our quantum, so reschedule */
3141                 dev->quota -= pkts;
3142                 *budget -= pkts;
3143                 return 1;
3144         }
3145 }
3146 #endif
3147
3148 #ifdef CONFIG_FORCEDETH_NAPI
3149 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3150 {
3151         struct net_device *dev = (struct net_device *) data;
3152         u8 __iomem *base = get_hwbase(dev);
3153         u32 events;
3154
3155         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3156         writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3157
3158         if (events) {
3159                 netif_rx_schedule(dev);
3160                 /* disable receive interrupts on the nic */
3161                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3162                 pci_push(base);
3163         }
3164         return IRQ_HANDLED;
3165 }
3166 #else
3167 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3168 {
3169         struct net_device *dev = (struct net_device *) data;
3170         struct fe_priv *np = netdev_priv(dev);
3171         u8 __iomem *base = get_hwbase(dev);
3172         u32 events;
3173         int i;
3174         unsigned long flags;
3175
3176         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3177
3178         for (i=0; ; i++) {
3179                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3180                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3181                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3182                 if (!(events & np->irqmask))
3183                         break;
3184
3185                 if (nv_rx_process_optimized(dev, dev->weight)) {
3186                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3187                                 spin_lock_irqsave(&np->lock, flags);
3188                                 if (!np->in_shutdown)
3189                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3190                                 spin_unlock_irqrestore(&np->lock, flags);
3191                         }
3192                 }
3193
3194                 if (unlikely(i > max_interrupt_work)) {
3195                         spin_lock_irqsave(&np->lock, flags);
3196                         /* disable interrupts on the nic */
3197                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3198                         pci_push(base);
3199
3200                         if (!np->in_shutdown) {
3201                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3202                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3203                         }
3204                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3205                         spin_unlock_irqrestore(&np->lock, flags);
3206                         break;
3207                 }
3208         }
3209         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3210
3211         return IRQ_RETVAL(i);
3212 }
3213 #endif
3214
3215 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3216 {
3217         struct net_device *dev = (struct net_device *) data;
3218         struct fe_priv *np = netdev_priv(dev);
3219         u8 __iomem *base = get_hwbase(dev);
3220         u32 events;
3221         int i;
3222         unsigned long flags;
3223
3224         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3225
3226         for (i=0; ; i++) {
3227                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3228                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3229                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3230                 if (!(events & np->irqmask))
3231                         break;
3232
3233                 /* check tx in case we reached max loop limit in tx isr */
3234                 spin_lock_irqsave(&np->lock, flags);
3235                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3236                 spin_unlock_irqrestore(&np->lock, flags);
3237
3238                 if (events & NVREG_IRQ_LINK) {
3239                         spin_lock_irqsave(&np->lock, flags);
3240                         nv_link_irq(dev);
3241                         spin_unlock_irqrestore(&np->lock, flags);
3242                 }
3243                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3244                         spin_lock_irqsave(&np->lock, flags);
3245                         nv_linkchange(dev);
3246                         spin_unlock_irqrestore(&np->lock, flags);
3247                         np->link_timeout = jiffies + LINK_TIMEOUT;
3248                 }
3249                 if (events & NVREG_IRQ_RECOVER_ERROR) {
3250                         spin_lock_irq(&np->lock);
3251                         /* disable interrupts on the nic */
3252                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3253                         pci_push(base);
3254
3255                         if (!np->in_shutdown) {
3256                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3257                                 np->recover_error = 1;
3258                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3259                         }
3260                         spin_unlock_irq(&np->lock);
3261                         break;
3262                 }
3263                 if (events & (NVREG_IRQ_UNKNOWN)) {
3264                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3265                                                 dev->name, events);
3266                 }
3267                 if (unlikely(i > max_interrupt_work)) {
3268                         spin_lock_irqsave(&np->lock, flags);
3269                         /* disable interrupts on the nic */
3270                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3271                         pci_push(base);
3272
3273                         if (!np->in_shutdown) {
3274                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3275                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3276                         }
3277                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3278                         spin_unlock_irqrestore(&np->lock, flags);
3279                         break;
3280                 }
3281
3282         }
3283         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3284
3285         return IRQ_RETVAL(i);
3286 }
3287
3288 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3289 {
3290         struct net_device *dev = (struct net_device *) data;
3291         struct fe_priv *np = netdev_priv(dev);
3292         u8 __iomem *base = get_hwbase(dev);
3293         u32 events;
3294
3295         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3296
3297         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3298                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3299                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3300         } else {
3301                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3302                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3303         }
3304         pci_push(base);
3305         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3306         if (!(events & NVREG_IRQ_TIMER))
3307                 return IRQ_RETVAL(0);
3308
3309         spin_lock(&np->lock);
3310         np->intr_test = 1;
3311         spin_unlock(&np->lock);
3312
3313         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3314
3315         return IRQ_RETVAL(1);
3316 }
3317
3318 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3319 {
3320         u8 __iomem *base = get_hwbase(dev);
3321         int i;
3322         u32 msixmap = 0;
3323
3324         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3325          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3326          * the remaining 8 interrupts.
3327          */
3328         for (i = 0; i < 8; i++) {
3329                 if ((irqmask >> i) & 0x1) {
3330                         msixmap |= vector << (i << 2);
3331                 }
3332         }
3333         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3334
3335         msixmap = 0;
3336         for (i = 0; i < 8; i++) {
3337                 if ((irqmask >> (i + 8)) & 0x1) {
3338                         msixmap |= vector << (i << 2);
3339                 }
3340         }
3341         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3342 }
3343
3344 static int nv_request_irq(struct net_device *dev, int intr_test)
3345 {
3346         struct fe_priv *np = get_nvpriv(dev);
3347         u8 __iomem *base = get_hwbase(dev);
3348         int ret = 1;
3349         int i;
3350         irqreturn_t (*handler)(int foo, void *data);
3351
3352         if (intr_test) {
3353                 handler = nv_nic_irq_test;
3354         } else {
3355                 if (np->desc_ver == DESC_VER_3)
3356                         handler = nv_nic_irq_optimized;
3357                 else
3358                         handler = nv_nic_irq;
3359         }
3360
3361         if (np->msi_flags & NV_MSI_X_CAPABLE) {
3362                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3363                         np->msi_x_entry[i].entry = i;
3364                 }
3365                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3366                         np->msi_flags |= NV_MSI_X_ENABLED;
3367                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3368                                 /* Request irq for rx handling */
3369                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
3370                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3371                                         pci_disable_msix(np->pci_dev);
3372                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3373                                         goto out_err;
3374                                 }
3375                                 /* Request irq for tx handling */
3376                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
3377                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3378                                         pci_disable_msix(np->pci_dev);
3379                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3380                                         goto out_free_rx;
3381                                 }
3382                                 /* Request irq for link and timer handling */
3383                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
3384                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
3385                                         pci_disable_msix(np->pci_dev);
3386                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3387                                         goto out_free_tx;
3388                                 }
3389                                 /* map interrupts to their respective vector */
3390                                 writel(0, base + NvRegMSIXMap0);
3391                                 writel(0, base + NvRegMSIXMap1);
3392                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3393                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3394                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3395                         } else {
3396                                 /* Request irq for all interrupts */
3397                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3398                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3399                                         pci_disable_msix(np->pci_dev);
3400                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3401                                         goto out_err;
3402                                 }
3403
3404                                 /* map interrupts to vector 0 */
3405                                 writel(0, base + NvRegMSIXMap0);
3406                                 writel(0, base + NvRegMSIXMap1);
3407                         }
3408                 }
3409         }
3410         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3411                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
3412                         np->msi_flags |= NV_MSI_ENABLED;
3413                         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3414                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3415                                 pci_disable_msi(np->pci_dev);
3416                                 np->msi_flags &= ~NV_MSI_ENABLED;
3417                                 goto out_err;
3418                         }
3419
3420                         /* map interrupts to vector 0 */
3421                         writel(0, base + NvRegMSIMap0);
3422                         writel(0, base + NvRegMSIMap1);
3423                         /* enable msi vector 0 */
3424                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3425                 }
3426         }
3427         if (ret != 0) {
3428                 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3429                         goto out_err;
3430
3431         }
3432
3433         return 0;
3434 out_free_tx:
3435         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3436 out_free_rx:
3437         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3438 out_err:
3439         return 1;
3440 }
3441
3442 static void nv_free_irq(struct net_device *dev)
3443 {
3444         struct fe_priv *np = get_nvpriv(dev);
3445         int i;
3446
3447         if (np->msi_flags & NV_MSI_X_ENABLED) {
3448                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3449                         free_irq(np->msi_x_entry[i].vector, dev);
3450                 }
3451                 pci_disable_msix(np->pci_dev);
3452                 np->msi_flags &= ~NV_MSI_X_ENABLED;
3453         } else {
3454                 free_irq(np->pci_dev->irq, dev);
3455                 if (np->msi_flags & NV_MSI_ENABLED) {
3456                         pci_disable_msi(np->pci_dev);
3457                         np->msi_flags &= ~NV_MSI_ENABLED;
3458                 }
3459         }
3460 }
3461
3462 static void nv_do_nic_poll(unsigned long data)
3463 {
3464         struct net_device *dev = (struct net_device *) data;
3465         struct fe_priv *np = netdev_priv(dev);
3466         u8 __iomem *base = get_hwbase(dev);
3467         u32 mask = 0;
3468
3469         /*
3470          * First disable irq(s) and then
3471          * reenable interrupts on the nic, we have to do this before calling
3472          * nv_nic_irq because that may decide to do otherwise
3473          */
3474
3475         if (!using_multi_irqs(dev)) {
3476                 if (np->msi_flags & NV_MSI_X_ENABLED)
3477                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3478                 else
3479                         disable_irq_lockdep(dev->irq);
3480                 mask = np->irqmask;
3481         } else {
3482                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3483                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3484                         mask |= NVREG_IRQ_RX_ALL;
3485                 }
3486                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3487                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3488                         mask |= NVREG_IRQ_TX_ALL;
3489                 }
3490                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3491                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3492                         mask |= NVREG_IRQ_OTHER;
3493                 }
3494         }
3495         np->nic_poll_irq = 0;
3496
3497         if (np->recover_error) {
3498                 np->recover_error = 0;
3499                 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
3500                 if (netif_running(dev)) {
3501                         netif_tx_lock_bh(dev);
3502                         spin_lock(&np->lock);
3503                         /* stop engines */
3504                         nv_stop_rx(dev);
3505                         nv_stop_tx(dev);
3506                         nv_txrx_reset(dev);
3507                         /* drain rx queue */
3508                         nv_drain_rx(dev);
3509                         nv_drain_tx(dev);
3510                         /* reinit driver view of the rx queue */
3511                         set_bufsize(dev);
3512                         if (nv_init_ring(dev)) {
3513                                 if (!np->in_shutdown)
3514                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3515                         }
3516                         /* reinit nic view of the rx queue */
3517                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3518                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3519                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3520                                 base + NvRegRingSizes);
3521                         pci_push(base);
3522                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3523                         pci_push(base);
3524
3525                         /* restart rx engine */
3526                         nv_start_rx(dev);
3527                         nv_start_tx(dev);
3528                         spin_unlock(&np->lock);
3529                         netif_tx_unlock_bh(dev);
3530                 }
3531         }
3532
3533         /* FIXME: Do we need synchronize_irq(dev->irq) here? */
3534
3535         writel(mask, base + NvRegIrqMask);
3536         pci_push(base);
3537
3538         if (!using_multi_irqs(dev)) {
3539                 nv_nic_irq(0, dev);
3540                 if (np->msi_flags & NV_MSI_X_ENABLED)
3541                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3542                 else
3543                         enable_irq_lockdep(dev->irq);
3544         } else {
3545                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3546                         nv_nic_irq_rx(0, dev);
3547                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3548                 }
3549                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3550                         nv_nic_irq_tx(0, dev);
3551                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3552                 }
3553                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3554                         nv_nic_irq_other(0, dev);
3555                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3556                 }
3557         }
3558 }
3559
3560 #ifdef CONFIG_NET_POLL_CONTROLLER
3561 static void nv_poll_controller(struct net_device *dev)
3562 {
3563         nv_do_nic_poll((unsigned long) dev);
3564 }
3565 #endif
3566
3567 static void nv_do_stats_poll(unsigned long data)
3568 {
3569         struct net_device *dev = (struct net_device *) data;
3570         struct fe_priv *np = netdev_priv(dev);
3571
3572         nv_get_hw_stats(dev);
3573
3574         if (!np->in_shutdown)
3575                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
3576 }
3577
3578 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3579 {
3580         struct fe_priv *np = netdev_priv(dev);
3581         strcpy(info->driver, "forcedeth");
3582         strcpy(info->version, FORCEDETH_VERSION);
3583         strcpy(info->bus_info, pci_name(np->pci_dev));
3584 }
3585
3586 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3587 {
3588         struct fe_priv *np = netdev_priv(dev);
3589         wolinfo->supported = WAKE_MAGIC;
3590
3591         spin_lock_irq(&np->lock);
3592         if (np->wolenabled)
3593                 wolinfo->wolopts = WAKE_MAGIC;
3594         spin_unlock_irq(&np->lock);
3595 }
3596
3597 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3598 {
3599         struct fe_priv *np = netdev_priv(dev);
3600         u8 __iomem *base = get_hwbase(dev);
3601         u32 flags = 0;
3602
3603         if (wolinfo->wolopts == 0) {
3604                 np->wolenabled = 0;
3605         } else if (wolinfo->wolopts & WAKE_MAGIC) {
3606                 np->wolenabled = 1;
3607                 flags = NVREG_WAKEUPFLAGS_ENABLE;
3608         }
3609         if (netif_running(dev)) {
3610                 spin_lock_irq(&np->lock);
3611                 writel(flags, base + NvRegWakeUpFlags);
3612                 spin_unlock_irq(&np->lock);
3613         }
3614         return 0;
3615 }
3616
3617 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3618 {
3619         struct fe_priv *np = netdev_priv(dev);
3620         int adv;
3621
3622         spin_lock_irq(&np->lock);
3623         ecmd->port = PORT_MII;
3624         if (!netif_running(dev)) {
3625                 /* We do not track link speed / duplex setting if the
3626                  * interface is disabled. Force a link check */
3627                 if (nv_update_linkspeed(dev)) {
3628                         if (!netif_carrier_ok(dev))
3629                                 netif_carrier_on(dev);
3630                 } else {
3631                         if (netif_carrier_ok(dev))
3632                                 netif_carrier_off(dev);
3633                 }
3634         }
3635
3636         if (netif_carrier_ok(dev)) {
3637                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
3638                 case NVREG_LINKSPEED_10:
3639                         ecmd->speed = SPEED_10;
3640                         break;
3641                 case NVREG_LINKSPEED_100:
3642                         ecmd->speed = SPEED_100;
3643                         break;
3644                 case NVREG_LINKSPEED_1000:
3645                         ecmd->speed = SPEED_1000;
3646                         break;
3647                 }
3648                 ecmd->duplex = DUPLEX_HALF;
3649                 if (np->duplex)
3650                         ecmd->duplex = DUPLEX_FULL;
3651         } else {
3652                 ecmd->speed = -1;
3653                 ecmd->duplex = -1;
3654         }
3655
3656         ecmd->autoneg = np->autoneg;
3657
3658         ecmd->advertising = ADVERTISED_MII;
3659         if (np->autoneg) {
3660                 ecmd->advertising |= ADVERTISED_Autoneg;
3661                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3662                 if (adv & ADVERTISE_10HALF)
3663                         ecmd->advertising |= ADVERTISED_10baseT_Half;
3664                 if (adv & ADVERTISE_10FULL)
3665                         ecmd->advertising |= ADVERTISED_10baseT_Full;
3666                 if (adv & ADVERTISE_100HALF)
3667                         ecmd->advertising |= ADVERTISED_100baseT_Half;
3668                 if (adv & ADVERTISE_100FULL)
3669                         ecmd->advertising |= ADVERTISED_100baseT_Full;
3670                 if (np->gigabit == PHY_GIGABIT) {
3671                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3672                         if (adv & ADVERTISE_1000FULL)
3673                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3674                 }
3675         }
3676         ecmd->supported = (SUPPORTED_Autoneg |
3677                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
3678                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
3679                 SUPPORTED_MII);
3680         if (np->gigabit == PHY_GIGABIT)
3681                 ecmd->supported |= SUPPORTED_1000baseT_Full;
3682
3683         ecmd->phy_address = np->phyaddr;
3684         ecmd->transceiver = XCVR_EXTERNAL;
3685
3686         /* ignore maxtxpkt, maxrxpkt for now */
3687         spin_unlock_irq(&np->lock);
3688         return 0;
3689 }
3690
3691 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3692 {
3693         struct fe_priv *np = netdev_priv(dev);
3694
3695         if (ecmd->port != PORT_MII)
3696                 return -EINVAL;
3697         if (ecmd->transceiver != XCVR_EXTERNAL)
3698                 return -EINVAL;
3699         if (ecmd->phy_address != np->phyaddr) {
3700                 /* TODO: support switching between multiple phys. Should be
3701                  * trivial, but not enabled due to lack of test hardware. */
3702                 return -EINVAL;
3703         }
3704         if (ecmd->autoneg == AUTONEG_ENABLE) {
3705                 u32 mask;
3706
3707                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3708                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3709                 if (np->gigabit == PHY_GIGABIT)
3710                         mask |= ADVERTISED_1000baseT_Full;
3711
3712                 if ((ecmd->advertising & mask) == 0)
3713                         return -EINVAL;
3714
3715         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
3716                 /* Note: autonegotiation disable, speed 1000 intentionally
3717                  * forbidden - noone should need that. */
3718
3719                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
3720                         return -EINVAL;
3721                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
3722                         return -EINVAL;
3723         } else {
3724                 return -EINVAL;
3725         }
3726
3727         netif_carrier_off(dev);
3728         if (netif_running(dev)) {
3729                 nv_disable_irq(dev);
3730                 netif_tx_lock_bh(dev);
3731                 spin_lock(&np->lock);
3732                 /* stop engines */
3733                 nv_stop_rx(dev);
3734                 nv_stop_tx(dev);
3735                 spin_unlock(&np->lock);
3736                 netif_tx_unlock_bh(dev);
3737         }
3738
3739         if (ecmd->autoneg == AUTONEG_ENABLE) {
3740                 int adv, bmcr;
3741
3742                 np->autoneg = 1;
3743
3744                 /* advertise only what has been requested */
3745                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3746                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3747                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
3748                         adv |= ADVERTISE_10HALF;
3749                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
3750                         adv |= ADVERTISE_10FULL;
3751                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
3752                         adv |= ADVERTISE_100HALF;
3753                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
3754                         adv |= ADVERTISE_100FULL;
3755                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
3756                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3757                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3758                         adv |=  ADVERTISE_PAUSE_ASYM;
3759                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3760
3761                 if (np->gigabit == PHY_GIGABIT) {
3762                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3763                         adv &= ~ADVERTISE_1000FULL;
3764                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
3765                                 adv |= ADVERTISE_1000FULL;
3766                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3767                 }
3768
3769                 if (netif_running(dev))
3770                         printk(KERN_INFO "%s: link down.\n", dev->name);
3771                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3772                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3773                         bmcr |= BMCR_ANENABLE;
3774                         /* reset the phy in order for settings to stick,
3775                          * and cause autoneg to start */
3776                         if (phy_reset(dev, bmcr)) {
3777                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3778                                 return -EINVAL;
3779                         }
3780                 } else {
3781                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3782                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3783                 }
3784         } else {
3785                 int adv, bmcr;
3786
3787                 np->autoneg = 0;
3788
3789                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3790                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3791                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
3792                         adv |= ADVERTISE_10HALF;
3793                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
3794                         adv |= ADVERTISE_10FULL;
3795                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
3796                         adv |= ADVERTISE_100HALF;
3797                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
3798                         adv |= ADVERTISE_100FULL;
3799                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3800                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
3801                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3802                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3803                 }
3804                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
3805                         adv |=  ADVERTISE_PAUSE_ASYM;
3806                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3807                 }
3808                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3809                 np->fixed_mode = adv;
3810
3811                 if (np->gigabit == PHY_GIGABIT) {
3812                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3813                         adv &= ~ADVERTISE_1000FULL;
3814                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3815                 }
3816
3817                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3818                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
3819                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
3820                         bmcr |= BMCR_FULLDPLX;
3821                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
3822                         bmcr |= BMCR_SPEED100;
3823                 if (np->phy_oui == PHY_OUI_MARVELL) {
3824                         /* reset the phy in order for forced mode settings to stick */
3825                         if (phy_reset(dev, bmcr)) {
3826                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3827                                 return -EINVAL;
3828                         }
3829                 } else {
3830                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3831                         if (netif_running(dev)) {
3832                                 /* Wait a bit and then reconfigure the nic. */
3833                                 udelay(10);
3834                                 nv_linkchange(dev);
3835                         }
3836                 }
3837         }
3838
3839         if (netif_running(dev)) {
3840                 nv_start_rx(dev);
3841                 nv_start_tx(dev);
3842                 nv_enable_irq(dev);
3843         }
3844
3845         return 0;
3846 }
3847
3848 #define FORCEDETH_REGS_VER      1
3849
3850 static int nv_get_regs_len(struct net_device *dev)
3851 {
3852         struct fe_priv *np = netdev_priv(dev);
3853         return np->register_size;
3854 }
3855
3856 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
3857 {
3858         struct fe_priv *np = netdev_priv(dev);
3859         u8 __iomem *base = get_hwbase(dev);
3860         u32 *rbuf = buf;
3861         int i;
3862
3863         regs->version = FORCEDETH_REGS_VER;
3864         spin_lock_irq(&np->lock);
3865         for (i = 0;i <= np->register_size/sizeof(u32); i++)
3866                 rbuf[i] = readl(base + i*sizeof(u32));
3867         spin_unlock_irq(&np->lock);
3868 }
3869
3870 static int nv_nway_reset(struct net_device *dev)
3871 {
3872         struct fe_priv *np = netdev_priv(dev);
3873         int ret;
3874
3875         if (np->autoneg) {
3876                 int bmcr;
3877
3878                 netif_carrier_off(dev);
3879                 if (netif_running(dev)) {
3880                         nv_disable_irq(dev);
3881                         netif_tx_lock_bh(dev);
3882                         spin_lock(&np->lock);
3883                         /* stop engines */
3884                         nv_stop_rx(dev);
3885                         nv_stop_tx(dev);
3886                         spin_unlock(&np->lock);
3887                         netif_tx_unlock_bh(dev);
3888                         printk(KERN_INFO "%s: link down.\n", dev->name);
3889                 }
3890
3891                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3892                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3893                         bmcr |= BMCR_ANENABLE;
3894                         /* reset the phy in order for settings to stick*/
3895                         if (phy_reset(dev, bmcr)) {
3896                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3897                                 return -EINVAL;
3898                         }
3899                 } else {
3900                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3901                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3902                 }
3903
3904                 if (netif_running(dev)) {
3905                         nv_start_rx(dev);
3906                         nv_start_tx(dev);
3907                         nv_enable_irq(dev);
3908                 }
3909                 ret = 0;
3910         } else {
3911                 ret = -EINVAL;
3912         }
3913
3914         return ret;
3915 }
3916
3917 static int nv_set_tso(struct net_device *dev, u32 value)
3918 {
3919         struct fe_priv *np = netdev_priv(dev);
3920
3921         if ((np->driver_data & DEV_HAS_CHECKSUM))
3922                 return ethtool_op_set_tso(dev, value);
3923         else
3924                 return -EOPNOTSUPP;
3925 }
3926
3927 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3928 {
3929         struct fe_priv *np = netdev_priv(dev);
3930
3931         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3932         ring->rx_mini_max_pending = 0;
3933         ring->rx_jumbo_max_pending = 0;
3934         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3935
3936         ring->rx_pending = np->rx_ring_size;
3937         ring->rx_mini_pending = 0;
3938         ring->rx_jumbo_pending = 0;
3939         ring->tx_pending = np->tx_ring_size;
3940 }
3941
3942 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3943 {
3944         struct fe_priv *np = netdev_priv(dev);
3945         u8 __iomem *base = get_hwbase(dev);
3946         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
3947         dma_addr_t ring_addr;
3948
3949         if (ring->rx_pending < RX_RING_MIN ||
3950             ring->tx_pending < TX_RING_MIN ||
3951             ring->rx_mini_pending != 0 ||
3952             ring->rx_jumbo_pending != 0 ||
3953             (np->desc_ver == DESC_VER_1 &&
3954              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
3955               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
3956             (np->desc_ver != DESC_VER_1 &&
3957              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
3958               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
3959                 return -EINVAL;
3960         }
3961
3962         /* allocate new rings */
3963         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3964                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3965                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3966                                             &ring_addr);
3967         } else {
3968                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3969                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3970                                             &ring_addr);
3971         }
3972         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
3973         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
3974         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
3975                 /* fall back to old rings */
3976                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3977                         if (rxtx_ring)
3978                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3979                                                     rxtx_ring, ring_addr);
3980                 } else {
3981                         if (rxtx_ring)
3982                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3983                                                     rxtx_ring, ring_addr);
3984                 }
3985                 if (rx_skbuff)
3986                         kfree(rx_skbuff);
3987                 if (tx_skbuff)
3988                         kfree(tx_skbuff);
3989                 goto exit;
3990         }
3991
3992         if (netif_running(dev)) {
3993                 nv_disable_irq(dev);
3994                 netif_tx_lock_bh(dev);
3995                 spin_lock(&np->lock);
3996                 /* stop engines */
3997                 nv_stop_rx(dev);
3998                 nv_stop_tx(dev);
3999                 nv_txrx_reset(dev);
4000                 /* drain queues */
4001                 nv_drain_rx(dev);
4002                 nv_drain_tx(dev);
4003                 /* delete queues */
4004                 free_rings(dev);
4005         }
4006
4007         /* set new values */
4008         np->rx_ring_size = ring->rx_pending;
4009         np->tx_ring_size = ring->tx_pending;
4010         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4011                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4012                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4013         } else {
4014                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4015                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4016         }
4017         np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4018         np->tx_skb = (struct nv_skb_map*)tx_skbuff;
4019         np->ring_addr = ring_addr;
4020
4021         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4022         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4023
4024         if (netif_running(dev)) {
4025                 /* reinit driver view of the queues */
4026                 set_bufsize(dev);
4027                 if (nv_init_ring(dev)) {
4028                         if (!np->in_shutdown)
4029                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4030                 }
4031
4032                 /* reinit nic view of the queues */
4033                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4034                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4035                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4036                         base + NvRegRingSizes);
4037                 pci_push(base);
4038                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4039                 pci_push(base);
4040
4041                 /* restart engines */
4042                 nv_start_rx(dev);
4043                 nv_start_tx(dev);
4044                 spin_unlock(&np->lock);
4045                 netif_tx_unlock_bh(dev);
4046                 nv_enable_irq(dev);
4047         }
4048         return 0;
4049 exit:
4050         return -ENOMEM;
4051 }
4052
4053 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4054 {
4055         struct fe_priv *np = netdev_priv(dev);
4056
4057         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4058         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4059         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4060 }
4061
4062 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4063 {
4064         struct fe_priv *np = netdev_priv(dev);
4065         int adv, bmcr;
4066
4067         if ((!np->autoneg && np->duplex == 0) ||
4068             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4069                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4070                        dev->name);
4071                 return -EINVAL;
4072         }
4073         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4074                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4075                 return -EINVAL;
4076         }
4077
4078         netif_carrier_off(dev);
4079         if (netif_running(dev)) {
4080                 nv_disable_irq(dev);
4081                 netif_tx_lock_bh(dev);
4082                 spin_lock(&np->lock);
4083                 /* stop engines */
4084                 nv_stop_rx(dev);
4085                 nv_stop_tx(dev);
4086                 spin_unlock(&np->lock);
4087                 netif_tx_unlock_bh(dev);
4088         }
4089
4090         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4091         if (pause->rx_pause)
4092                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4093         if (pause->tx_pause)
4094                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4095
4096         if (np->autoneg && pause->autoneg) {
4097                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4098
4099                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4100                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4101                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4102                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4103                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4104                         adv |=  ADVERTISE_PAUSE_ASYM;
4105                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4106
4107                 if (netif_running(dev))
4108                         printk(KERN_INFO "%s: link down.\n", dev->name);
4109                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4110                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4111                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4112         } else {
4113                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4114                 if (pause->rx_pause)
4115                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4116                 if (pause->tx_pause)
4117                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4118
4119                 if (!netif_running(dev))
4120                         nv_update_linkspeed(dev);
4121                 else
4122                         nv_update_pause(dev, np->pause_flags);
4123         }
4124
4125         if (netif_running(dev)) {
4126                 nv_start_rx(dev);
4127                 nv_start_tx(dev);
4128                 nv_enable_irq(dev);
4129         }
4130         return 0;
4131 }
4132
4133 static u32 nv_get_rx_csum(struct net_device *dev)
4134 {
4135         struct fe_priv *np = netdev_priv(dev);
4136         return (np->rx_csum) != 0;
4137 }
4138
4139 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4140 {
4141         struct fe_priv *np = netdev_priv(dev);
4142         u8 __iomem *base = get_hwbase(dev);
4143         int retcode = 0;
4144
4145         if (np->driver_data & DEV_HAS_CHECKSUM) {
4146                 if (data) {
4147                         np->rx_csum = 1;
4148                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4149                 } else {
4150                         np->rx_csum = 0;
4151                         /* vlan is dependent on rx checksum offload */
4152                         if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4153                                 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4154                 }
4155                 if (netif_running(dev)) {
4156                         spin_lock_irq(&np->lock);
4157                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4158                         spin_unlock_irq(&np->lock);
4159                 }
4160         } else {
4161                 return -EINVAL;
4162         }
4163
4164         return retcode;
4165 }
4166
4167 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4168 {
4169         struct fe_priv *np = netdev_priv(dev);
4170
4171         if (np->driver_data & DEV_HAS_CHECKSUM)
4172                 return ethtool_op_set_tx_hw_csum(dev, data);
4173         else
4174                 return -EOPNOTSUPP;
4175 }
4176
4177 static int nv_set_sg(struct net_device *dev, u32 data)
4178 {
4179         struct fe_priv *np = netdev_priv(dev);
4180
4181         if (np->driver_data & DEV_HAS_CHECKSUM)
4182                 return ethtool_op_set_sg(dev, data);
4183         else
4184                 return -EOPNOTSUPP;
4185 }
4186
4187 static int nv_get_stats_count(struct net_device *dev)
4188 {
4189         struct fe_priv *np = netdev_priv(dev);
4190
4191         if (np->driver_data & DEV_HAS_STATISTICS_V1)
4192                 return NV_DEV_STATISTICS_V1_COUNT;
4193         else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4194                 return NV_DEV_STATISTICS_V2_COUNT;
4195         else
4196                 return 0;
4197 }
4198
4199 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4200 {
4201         struct fe_priv *np = netdev_priv(dev);
4202
4203         /* update stats */
4204         nv_do_stats_poll((unsigned long)dev);
4205
4206         memcpy(buffer, &np->estats, nv_get_stats_count(dev)*sizeof(u64));
4207 }
4208
4209 static int nv_self_test_count(struct net_device *dev)
4210 {
4211         struct fe_priv *np = netdev_priv(dev);
4212
4213         if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4214                 return NV_TEST_COUNT_EXTENDED;
4215         else
4216                 return NV_TEST_COUNT_BASE;
4217 }
4218
4219 static int nv_link_test(struct net_device *dev)
4220 {
4221         struct fe_priv *np = netdev_priv(dev);
4222         int mii_status;
4223
4224         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4225         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4226
4227         /* check phy link status */
4228         if (!(mii_status & BMSR_LSTATUS))
4229                 return 0;
4230         else
4231                 return 1;
4232 }
4233
4234 static int nv_register_test(struct net_device *dev)
4235 {
4236         u8 __iomem *base = get_hwbase(dev);
4237         int i = 0;
4238         u32 orig_read, new_read;
4239
4240         do {
4241                 orig_read = readl(base + nv_registers_test[i].reg);
4242
4243                 /* xor with mask to toggle bits */
4244                 orig_read ^= nv_registers_test[i].mask;
4245
4246                 writel(orig_read, base + nv_registers_test[i].reg);
4247
4248                 new_read = readl(base + nv_registers_test[i].reg);
4249
4250                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4251                         return 0;
4252
4253                 /* restore original value */
4254                 orig_read ^= nv_registers_test[i].mask;
4255                 writel(orig_read, base + nv_registers_test[i].reg);
4256
4257         } while (nv_registers_test[++i].reg != 0);
4258
4259         return 1;
4260 }
4261
4262 static int nv_interrupt_test(struct net_device *dev)
4263 {
4264         struct fe_priv *np = netdev_priv(dev);
4265         u8 __iomem *base = get_hwbase(dev);
4266         int ret = 1;
4267         int testcnt;
4268         u32 save_msi_flags, save_poll_interval = 0;
4269
4270         if (netif_running(dev)) {
4271                 /* free current irq */
4272                 nv_free_irq(dev);
4273                 save_poll_interval = readl(base+NvRegPollingInterval);
4274         }
4275
4276         /* flag to test interrupt handler */
4277         np->intr_test = 0;
4278
4279         /* setup test irq */
4280         save_msi_flags = np->msi_flags;
4281         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4282         np->msi_flags |= 0x001; /* setup 1 vector */
4283         if (nv_request_irq(dev, 1))
4284                 return 0;
4285
4286         /* setup timer interrupt */
4287         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4288         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4289
4290         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4291
4292         /* wait for at least one interrupt */
4293         msleep(100);
4294
4295         spin_lock_irq(&np->lock);
4296
4297         /* flag should be set within ISR */
4298         testcnt = np->intr_test;
4299         if (!testcnt)
4300                 ret = 2;
4301
4302         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4303         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4304                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4305         else
4306                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4307
4308         spin_unlock_irq(&np->lock);
4309
4310         nv_free_irq(dev);
4311
4312         np->msi_flags = save_msi_flags;
4313
4314         if (netif_running(dev)) {
4315                 writel(save_poll_interval, base + NvRegPollingInterval);
4316                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4317                 /* restore original irq */
4318                 if (nv_request_irq(dev, 0))
4319                         return 0;
4320         }
4321
4322         return ret;
4323 }
4324
4325 static int nv_loopback_test(struct net_device *dev)
4326 {
4327         struct fe_priv *np = netdev_priv(dev);
4328         u8 __iomem *base = get_hwbase(dev);
4329         struct sk_buff *tx_skb, *rx_skb;
4330         dma_addr_t test_dma_addr;
4331         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4332         u32 flags;
4333         int len, i, pkt_len;
4334         u8 *pkt_data;
4335         u32 filter_flags = 0;
4336         u32 misc1_flags = 0;
4337         int ret = 1;
4338
4339         if (netif_running(dev)) {
4340                 nv_disable_irq(dev);
4341                 filter_flags = readl(base + NvRegPacketFilterFlags);
4342                 misc1_flags = readl(base + NvRegMisc1);
4343         } else {
4344                 nv_txrx_reset(dev);
4345         }
4346
4347         /* reinit driver view of the rx queue */
4348         set_bufsize(dev);
4349         nv_init_ring(dev);
4350
4351         /* setup hardware for loopback */
4352         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4353         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4354
4355         /* reinit nic view of the rx queue */
4356         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4357         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4358         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4359                 base + NvRegRingSizes);
4360         pci_push(base);
4361
4362         /* restart rx engine */
4363         nv_start_rx(dev);
4364         nv_start_tx(dev);
4365
4366         /* setup packet for tx */
4367         pkt_len = ETH_DATA_LEN;
4368         tx_skb = dev_alloc_skb(pkt_len);
4369         if (!tx_skb) {
4370                 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
4371                          " of %s\n", dev->name);
4372                 ret = 0;
4373                 goto out;
4374         }
4375         pkt_data = skb_put(tx_skb, pkt_len);
4376         for (i = 0; i < pkt_len; i++)
4377                 pkt_data[i] = (u8)(i & 0xff);
4378         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4379                                        tx_skb->end-tx_skb->data, PCI_DMA_FROMDEVICE);
4380
4381         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4382                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4383                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4384         } else {
4385                 np->tx_ring.ex[0].bufhigh = cpu_to_le64(test_dma_addr) >> 32;
4386                 np->tx_ring.ex[0].buflow = cpu_to_le64(test_dma_addr) & 0x0FFFFFFFF;
4387                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4388         }
4389         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4390         pci_push(get_hwbase(dev));
4391
4392         msleep(500);
4393
4394         /* check for rx of the packet */
4395         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4396                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4397                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4398
4399         } else {
4400                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4401                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4402         }
4403
4404         if (flags & NV_RX_AVAIL) {
4405                 ret = 0;
4406         } else if (np->desc_ver == DESC_VER_1) {
4407                 if (flags & NV_RX_ERROR)
4408                         ret = 0;
4409         } else {
4410                 if (flags & NV_RX2_ERROR) {
4411                         ret = 0;
4412                 }
4413         }
4414
4415         if (ret) {
4416                 if (len != pkt_len) {
4417                         ret = 0;
4418                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
4419                                 dev->name, len, pkt_len);
4420                 } else {
4421                         rx_skb = np->rx_skb[0].skb;
4422                         for (i = 0; i < pkt_len; i++) {
4423                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4424                                         ret = 0;
4425                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
4426                                                 dev->name, i);
4427                                         break;
4428                                 }
4429                         }
4430                 }
4431         } else {
4432                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
4433         }
4434
4435         pci_unmap_page(np->pci_dev, test_dma_addr,
4436                        tx_skb->end-tx_skb->data,
4437                        PCI_DMA_TODEVICE);
4438         dev_kfree_skb_any(tx_skb);
4439  out:
4440         /* stop engines */
4441         nv_stop_rx(dev);
4442         nv_stop_tx(dev);
4443         nv_txrx_reset(dev);
4444         /* drain rx queue */
4445         nv_drain_rx(dev);
4446         nv_drain_tx(dev);
4447
4448         if (netif_running(dev)) {
4449                 writel(misc1_flags, base + NvRegMisc1);
4450                 writel(filter_flags, base + NvRegPacketFilterFlags);
4451                 nv_enable_irq(dev);
4452         }
4453
4454         return ret;
4455 }
4456
4457 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4458 {
4459         struct fe_priv *np = netdev_priv(dev);
4460         u8 __iomem *base = get_hwbase(dev);
4461         int result;
4462         memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64));
4463
4464         if (!nv_link_test(dev)) {
4465                 test->flags |= ETH_TEST_FL_FAILED;
4466                 buffer[0] = 1;
4467         }
4468
4469         if (test->flags & ETH_TEST_FL_OFFLINE) {
4470                 if (netif_running(dev)) {
4471                         netif_stop_queue(dev);
4472                         netif_poll_disable(dev);
4473                         netif_tx_lock_bh(dev);
4474                         spin_lock_irq(&np->lock);
4475                         nv_disable_hw_interrupts(dev, np->irqmask);
4476                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
4477                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4478                         } else {
4479                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4480                         }
4481                         /* stop engines */
4482                         nv_stop_rx(dev);
4483                         nv_stop_tx(dev);
4484                         nv_txrx_reset(dev);
4485                         /* drain rx queue */
4486                         nv_drain_rx(dev);
4487                         nv_drain_tx(dev);
4488                         spin_unlock_irq(&np->lock);
4489                         netif_tx_unlock_bh(dev);
4490                 }
4491
4492                 if (!nv_register_test(dev)) {
4493                         test->flags |= ETH_TEST_FL_FAILED;
4494                         buffer[1] = 1;
4495                 }
4496
4497                 result = nv_interrupt_test(dev);
4498                 if (result != 1) {
4499                         test->flags |= ETH_TEST_FL_FAILED;
4500                         buffer[2] = 1;
4501                 }
4502                 if (result == 0) {
4503                         /* bail out */
4504                         return;
4505                 }
4506
4507                 if (!nv_loopback_test(dev)) {
4508                         test->flags |= ETH_TEST_FL_FAILED;
4509                         buffer[3] = 1;
4510                 }
4511
4512                 if (netif_running(dev)) {
4513                         /* reinit driver view of the rx queue */
4514                         set_bufsize(dev);
4515                         if (nv_init_ring(dev)) {
4516                                 if (!np->in_shutdown)
4517                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4518                         }
4519                         /* reinit nic view of the rx queue */
4520                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4521                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4522                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4523                                 base + NvRegRingSizes);
4524                         pci_push(base);
4525                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4526                         pci_push(base);
4527                         /* restart rx engine */
4528                         nv_start_rx(dev);
4529                         nv_start_tx(dev);
4530                         netif_start_queue(dev);
4531                         netif_poll_enable(dev);
4532                         nv_enable_hw_interrupts(dev, np->irqmask);
4533                 }
4534         }
4535 }
4536
4537 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4538 {
4539         switch (stringset) {
4540         case ETH_SS_STATS:
4541                 memcpy(buffer, &nv_estats_str, nv_get_stats_count(dev)*sizeof(struct nv_ethtool_str));
4542                 break;
4543         case ETH_SS_TEST:
4544                 memcpy(buffer, &nv_etests_str, nv_self_test_count(dev)*sizeof(struct nv_ethtool_str));
4545                 break;
4546         }
4547 }
4548
4549 static const struct ethtool_ops ops = {
4550         .get_drvinfo = nv_get_drvinfo,
4551         .get_link = ethtool_op_get_link,
4552         .get_wol = nv_get_wol,
4553         .set_wol = nv_set_wol,
4554         .get_settings = nv_get_settings,
4555         .set_settings = nv_set_settings,
4556         .get_regs_len = nv_get_regs_len,
4557         .get_regs = nv_get_regs,
4558         .nway_reset = nv_nway_reset,
4559         .get_perm_addr = ethtool_op_get_perm_addr,
4560         .get_tso = ethtool_op_get_tso,
4561         .set_tso = nv_set_tso,
4562         .get_ringparam = nv_get_ringparam,
4563         .set_ringparam = nv_set_ringparam,
4564         .get_pauseparam = nv_get_pauseparam,
4565         .set_pauseparam = nv_set_pauseparam,
4566         .get_rx_csum = nv_get_rx_csum,
4567         .set_rx_csum = nv_set_rx_csum,
4568         .get_tx_csum = ethtool_op_get_tx_csum,
4569         .set_tx_csum = nv_set_tx_csum,
4570         .get_sg = ethtool_op_get_sg,
4571         .set_sg = nv_set_sg,
4572         .get_strings = nv_get_strings,
4573         .get_stats_count = nv_get_stats_count,
4574         .get_ethtool_stats = nv_get_ethtool_stats,
4575         .self_test_count = nv_self_test_count,
4576         .self_test = nv_self_test,
4577 };
4578
4579 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
4580 {
4581         struct fe_priv *np = get_nvpriv(dev);
4582
4583         spin_lock_irq(&np->lock);
4584
4585         /* save vlan group */
4586         np->vlangrp = grp;
4587
4588         if (grp) {
4589                 /* enable vlan on MAC */
4590                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
4591         } else {
4592                 /* disable vlan on MAC */
4593                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4594                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4595         }
4596
4597         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4598
4599         spin_unlock_irq(&np->lock);
4600 };
4601
4602 static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
4603 {
4604         /* nothing to do */
4605 };
4606
4607 /* The mgmt unit and driver use a semaphore to access the phy during init */
4608 static int nv_mgmt_acquire_sema(struct net_device *dev)
4609 {
4610         u8 __iomem *base = get_hwbase(dev);
4611         int i;
4612         u32 tx_ctrl, mgmt_sema;
4613
4614         for (i = 0; i < 10; i++) {
4615                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
4616                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
4617                         break;
4618                 msleep(500);
4619         }
4620
4621         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
4622                 return 0;
4623
4624         for (i = 0; i < 2; i++) {
4625                 tx_ctrl = readl(base + NvRegTransmitterControl);
4626                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
4627                 writel(tx_ctrl, base + NvRegTransmitterControl);
4628
4629                 /* verify that semaphore was acquired */
4630                 tx_ctrl = readl(base + NvRegTransmitterControl);
4631                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
4632                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE))
4633                         return 1;
4634                 else
4635                         udelay(50);
4636         }
4637
4638         return 0;
4639 }
4640
4641 static int nv_open(struct net_device *dev)
4642 {
4643         struct fe_priv *np = netdev_priv(dev);
4644         u8 __iomem *base = get_hwbase(dev);
4645         int ret = 1;
4646         int oom, i;
4647
4648         dprintk(KERN_DEBUG "nv_open: begin\n");
4649
4650         /* erase previous misconfiguration */
4651         if (np->driver_data & DEV_HAS_POWER_CNTRL)
4652                 nv_mac_reset(dev);
4653         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4654         writel(0, base + NvRegMulticastAddrB);
4655         writel(0, base + NvRegMulticastMaskA);
4656         writel(0, base + NvRegMulticastMaskB);
4657         writel(0, base + NvRegPacketFilterFlags);
4658
4659         writel(0, base + NvRegTransmitterControl);
4660         writel(0, base + NvRegReceiverControl);
4661
4662         writel(0, base + NvRegAdapterControl);
4663
4664         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
4665                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
4666
4667         /* initialize descriptor rings */
4668         set_bufsize(dev);
4669         oom = nv_init_ring(dev);
4670
4671         writel(0, base + NvRegLinkSpeed);
4672         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4673         nv_txrx_reset(dev);
4674         writel(0, base + NvRegUnknownSetupReg6);
4675
4676         np->in_shutdown = 0;
4677
4678         /* give hw rings */
4679         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4680         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4681                 base + NvRegRingSizes);
4682
4683         writel(np->linkspeed, base + NvRegLinkSpeed);
4684         if (np->desc_ver == DESC_VER_1)
4685                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
4686         else
4687                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
4688         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4689         writel(np->vlanctl_bits, base + NvRegVlanControl);
4690         pci_push(base);
4691         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
4692         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
4693                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
4694                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
4695
4696         writel(0, base + NvRegMIIMask);
4697         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4698         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4699
4700         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
4701         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
4702         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
4703         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4704
4705         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
4706         get_random_bytes(&i, sizeof(i));
4707         writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
4708         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
4709         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
4710         if (poll_interval == -1) {
4711                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
4712                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
4713                 else
4714                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4715         }
4716         else
4717                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
4718         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4719         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
4720                         base + NvRegAdapterControl);
4721         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
4722         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
4723         if (np->wolenabled)
4724                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
4725
4726         i = readl(base + NvRegPowerState);
4727         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
4728                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
4729
4730         pci_push(base);
4731         udelay(10);
4732         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
4733
4734         nv_disable_hw_interrupts(dev, np->irqmask);
4735         pci_push(base);
4736         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4737         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4738         pci_push(base);
4739
4740         if (nv_request_irq(dev, 0)) {
4741                 goto out_drain;
4742         }
4743
4744         /* ask for interrupts */
4745         nv_enable_hw_interrupts(dev, np->irqmask);
4746
4747         spin_lock_irq(&np->lock);
4748         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4749         writel(0, base + NvRegMulticastAddrB);
4750         writel(0, base + NvRegMulticastMaskA);
4751         writel(0, base + NvRegMulticastMaskB);
4752         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
4753         /* One manual link speed update: Interrupts are enabled, future link
4754          * speed changes cause interrupts and are handled by nv_link_irq().
4755          */
4756         {
4757                 u32 miistat;
4758                 miistat = readl(base + NvRegMIIStatus);
4759                 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
4760                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
4761         }
4762         /* set linkspeed to invalid value, thus force nv_update_linkspeed
4763          * to init hw */
4764         np->linkspeed = 0;
4765         ret = nv_update_linkspeed(dev);
4766         nv_start_rx(dev);
4767         nv_start_tx(dev);
4768         netif_start_queue(dev);
4769         netif_poll_enable(dev);
4770
4771         if (ret) {
4772                 netif_carrier_on(dev);
4773         } else {
4774                 printk("%s: no link during initialization.\n", dev->name);
4775                 netif_carrier_off(dev);
4776         }
4777         if (oom)
4778                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4779
4780         /* start statistics timer */
4781         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2))
4782                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
4783
4784         spin_unlock_irq(&np->lock);
4785
4786         return 0;
4787 out_drain:
4788         drain_ring(dev);
4789         return ret;
4790 }
4791
4792 static int nv_close(struct net_device *dev)
4793 {
4794         struct fe_priv *np = netdev_priv(dev);
4795         u8 __iomem *base;
4796
4797         spin_lock_irq(&np->lock);
4798         np->in_shutdown = 1;
4799         spin_unlock_irq(&np->lock);
4800         netif_poll_disable(dev);
4801         synchronize_irq(dev->irq);
4802
4803         del_timer_sync(&np->oom_kick);
4804         del_timer_sync(&np->nic_poll);
4805         del_timer_sync(&np->stats_poll);
4806
4807         netif_stop_queue(dev);
4808         spin_lock_irq(&np->lock);
4809         nv_stop_tx(dev);
4810         nv_stop_rx(dev);
4811         nv_txrx_reset(dev);
4812
4813         /* disable interrupts on the nic or we will lock up */
4814         base = get_hwbase(dev);
4815         nv_disable_hw_interrupts(dev, np->irqmask);
4816         pci_push(base);
4817         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
4818
4819         spin_unlock_irq(&np->lock);
4820
4821         nv_free_irq(dev);
4822
4823         drain_ring(dev);
4824
4825         if (np->wolenabled)
4826                 nv_start_rx(dev);
4827
4828         /* FIXME: power down nic */
4829
4830         return 0;
4831 }
4832
4833 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
4834 {
4835         struct net_device *dev;
4836         struct fe_priv *np;
4837         unsigned long addr;
4838         u8 __iomem *base;
4839         int err, i;
4840         u32 powerstate, txreg;
4841         u32 phystate_orig = 0, phystate;
4842         int phyinitialized = 0;
4843
4844         dev = alloc_etherdev(sizeof(struct fe_priv));
4845         err = -ENOMEM;
4846         if (!dev)
4847                 goto out;
4848
4849         np = netdev_priv(dev);
4850         np->pci_dev = pci_dev;
4851         spin_lock_init(&np->lock);
4852         SET_MODULE_OWNER(dev);
4853         SET_NETDEV_DEV(dev, &pci_dev->dev);
4854
4855         init_timer(&np->oom_kick);
4856         np->oom_kick.data = (unsigned long) dev;
4857         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
4858         init_timer(&np->nic_poll);
4859         np->nic_poll.data = (unsigned long) dev;
4860         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
4861         init_timer(&np->stats_poll);
4862         np->stats_poll.data = (unsigned long) dev;
4863         np->stats_poll.function = &nv_do_stats_poll;    /* timer handler */
4864
4865         err = pci_enable_device(pci_dev);
4866         if (err) {
4867                 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
4868                                 err, pci_name(pci_dev));
4869                 goto out_free;
4870         }
4871
4872         pci_set_master(pci_dev);
4873
4874         err = pci_request_regions(pci_dev, DRV_NAME);
4875         if (err < 0)
4876                 goto out_disable;
4877
4878         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2))
4879                 np->register_size = NV_PCI_REGSZ_VER3;
4880         else if (id->driver_data & DEV_HAS_STATISTICS_V1)
4881                 np->register_size = NV_PCI_REGSZ_VER2;
4882         else
4883                 np->register_size = NV_PCI_REGSZ_VER1;
4884
4885         err = -EINVAL;
4886         addr = 0;
4887         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
4888                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
4889                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
4890                                 pci_resource_len(pci_dev, i),
4891                                 pci_resource_flags(pci_dev, i));
4892                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
4893                                 pci_resource_len(pci_dev, i) >= np->register_size) {
4894                         addr = pci_resource_start(pci_dev, i);
4895                         break;
4896                 }
4897         }
4898         if (i == DEVICE_COUNT_RESOURCE) {
4899                 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
4900                                         pci_name(pci_dev));
4901                 goto out_relreg;
4902         }
4903
4904         /* copy of driver data */
4905         np->driver_data = id->driver_data;
4906
4907         /* handle different descriptor versions */
4908         if (id->driver_data & DEV_HAS_HIGH_DMA) {
4909                 /* packet format 3: supports 40-bit addressing */
4910                 np->desc_ver = DESC_VER_3;
4911                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
4912                 if (dma_64bit) {
4913                         if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4914                                 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
4915                                        pci_name(pci_dev));
4916                         } else {
4917                                 dev->features |= NETIF_F_HIGHDMA;
4918                                 printk(KERN_INFO "forcedeth: using HIGHDMA\n");
4919                         }
4920                         if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4921                                 printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n",
4922                                        pci_name(pci_dev));
4923                         }
4924                 }
4925         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
4926                 /* packet format 2: supports jumbo frames */
4927                 np->desc_ver = DESC_VER_2;
4928                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
4929         } else {
4930                 /* original packet format */
4931                 np->desc_ver = DESC_VER_1;
4932                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
4933         }
4934
4935         np->pkt_limit = NV_PKTLIMIT_1;
4936         if (id->driver_data & DEV_HAS_LARGEDESC)
4937                 np->pkt_limit = NV_PKTLIMIT_2;
4938
4939         if (id->driver_data & DEV_HAS_CHECKSUM) {
4940                 np->rx_csum = 1;
4941                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4942                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
4943                 dev->features |= NETIF_F_TSO;
4944         }
4945
4946         np->vlanctl_bits = 0;
4947         if (id->driver_data & DEV_HAS_VLAN) {
4948                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
4949                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
4950                 dev->vlan_rx_register = nv_vlan_rx_register;
4951                 dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid;
4952         }
4953
4954         np->msi_flags = 0;
4955         if ((id->driver_data & DEV_HAS_MSI) && msi) {
4956                 np->msi_flags |= NV_MSI_CAPABLE;
4957         }
4958         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
4959                 np->msi_flags |= NV_MSI_X_CAPABLE;
4960         }
4961
4962         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
4963         if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {
4964                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
4965         }
4966
4967
4968         err = -ENOMEM;
4969         np->base = ioremap(addr, np->register_size);
4970         if (!np->base)
4971                 goto out_relreg;
4972         dev->base_addr = (unsigned long)np->base;
4973
4974         dev->irq = pci_dev->irq;
4975
4976         np->rx_ring_size = RX_RING_DEFAULT;
4977         np->tx_ring_size = TX_RING_DEFAULT;
4978
4979         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4980                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
4981                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
4982                                         &np->ring_addr);
4983                 if (!np->rx_ring.orig)
4984                         goto out_unmap;
4985                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4986         } else {
4987                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
4988                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
4989                                         &np->ring_addr);
4990                 if (!np->rx_ring.ex)
4991                         goto out_unmap;
4992                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4993         }
4994         np->rx_skb = kmalloc(sizeof(struct nv_skb_map) * np->rx_ring_size, GFP_KERNEL);
4995         np->tx_skb = kmalloc(sizeof(struct nv_skb_map) * np->tx_ring_size, GFP_KERNEL);
4996         if (!np->rx_skb || !np->tx_skb)
4997                 goto out_freering;
4998         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4999         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
5000
5001         dev->open = nv_open;
5002         dev->stop = nv_close;
5003         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
5004                 dev->hard_start_xmit = nv_start_xmit;
5005         else
5006                 dev->hard_start_xmit = nv_start_xmit_optimized;
5007         dev->get_stats = nv_get_stats;
5008         dev->change_mtu = nv_change_mtu;
5009         dev->set_mac_address = nv_set_mac_address;
5010         dev->set_multicast_list = nv_set_multicast;
5011 #ifdef CONFIG_NET_POLL_CONTROLLER
5012         dev->poll_controller = nv_poll_controller;
5013 #endif
5014         dev->weight = RX_WORK_PER_LOOP;
5015 #ifdef CONFIG_FORCEDETH_NAPI
5016         dev->poll = nv_napi_poll;
5017 #endif
5018         SET_ETHTOOL_OPS(dev, &ops);
5019         dev->tx_timeout = nv_tx_timeout;
5020         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5021
5022         pci_set_drvdata(pci_dev, dev);
5023
5024         /* read the mac address */
5025         base = get_hwbase(dev);
5026         np->orig_mac[0] = readl(base + NvRegMacAddrA);
5027         np->orig_mac[1] = readl(base + NvRegMacAddrB);
5028
5029         /* check the workaround bit for correct mac address order */
5030         txreg = readl(base + NvRegTransmitPoll);
5031         if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5032                 /* mac address is already in correct order */
5033                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5034                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5035                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5036                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5037                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5038                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5039         } else {
5040                 /* need to reverse mac address to correct order */
5041                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
5042                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
5043                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5044                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5045                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
5046                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
5047                 /* set permanent address to be correct aswell */
5048                 np->orig_mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
5049                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
5050                 np->orig_mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
5051                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5052         }
5053         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5054
5055         if (!is_valid_ether_addr(dev->perm_addr)) {
5056                 /*
5057                  * Bad mac address. At least one bios sets the mac address
5058                  * to 01:23:45:67:89:ab
5059                  */
5060                 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
5061                         pci_name(pci_dev),
5062                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
5063                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
5064                 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
5065                 dev->dev_addr[0] = 0x00;
5066                 dev->dev_addr[1] = 0x00;
5067                 dev->dev_addr[2] = 0x6c;
5068                 get_random_bytes(&dev->dev_addr[3], 3);
5069         }
5070
5071         dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
5072                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
5073                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
5074
5075         /* set mac address */
5076         nv_copy_mac_to_hw(dev);
5077
5078         /* disable WOL */
5079         writel(0, base + NvRegWakeUpFlags);
5080         np->wolenabled = 0;
5081
5082         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5083                 u8 revision_id;
5084                 pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id);
5085
5086                 /* take phy and nic out of low power mode */
5087                 powerstate = readl(base + NvRegPowerState2);
5088                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5089                 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
5090                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
5091                     revision_id >= 0xA3)
5092                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5093                 writel(powerstate, base + NvRegPowerState2);
5094         }
5095
5096         if (np->desc_ver == DESC_VER_1) {
5097                 np->tx_flags = NV_TX_VALID;
5098         } else {
5099                 np->tx_flags = NV_TX2_VALID;
5100         }
5101         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
5102                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5103                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5104                         np->msi_flags |= 0x0003;
5105         } else {
5106                 np->irqmask = NVREG_IRQMASK_CPU;
5107                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5108                         np->msi_flags |= 0x0001;
5109         }
5110
5111         if (id->driver_data & DEV_NEED_TIMERIRQ)
5112                 np->irqmask |= NVREG_IRQ_TIMER;
5113         if (id->driver_data & DEV_NEED_LINKTIMER) {
5114                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5115                 np->need_linktimer = 1;
5116                 np->link_timeout = jiffies + LINK_TIMEOUT;
5117         } else {
5118                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5119                 np->need_linktimer = 0;
5120         }
5121
5122         /* clear phy state and temporarily halt phy interrupts */
5123         writel(0, base + NvRegMIIMask);
5124         phystate = readl(base + NvRegAdapterControl);
5125         if (phystate & NVREG_ADAPTCTL_RUNNING) {
5126                 phystate_orig = 1;
5127                 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5128                 writel(phystate, base + NvRegAdapterControl);
5129         }
5130         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
5131
5132         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5133                 /* management unit running on the mac? */
5134                 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) {
5135                         np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST;
5136                         dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev), np->mac_in_use);
5137                         for (i = 0; i < 5000; i++) {
5138                                 msleep(1);
5139                                 if (nv_mgmt_acquire_sema(dev)) {
5140                                         /* management unit setup the phy already? */
5141                                         if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5142                                             NVREG_XMITCTL_SYNC_PHY_INIT) {
5143                                                 /* phy is inited by mgmt unit */
5144                                                 phyinitialized = 1;
5145                                                 dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev));
5146                                         } else {
5147                                                 /* we need to init the phy */
5148                                         }
5149                                         break;
5150                                 }
5151                         }
5152                 }
5153         }
5154
5155         /* find a suitable phy */
5156         for (i = 1; i <= 32; i++) {
5157                 int id1, id2;
5158                 int phyaddr = i & 0x1F;
5159
5160                 spin_lock_irq(&np->lock);
5161                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5162                 spin_unlock_irq(&np->lock);
5163                 if (id1 < 0 || id1 == 0xffff)
5164                         continue;
5165                 spin_lock_irq(&np->lock);
5166                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5167                 spin_unlock_irq(&np->lock);
5168                 if (id2 < 0 || id2 == 0xffff)
5169                         continue;
5170
5171                 np->phy_model = id2 & PHYID2_MODEL_MASK;
5172                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5173                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5174                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
5175                         pci_name(pci_dev), id1, id2, phyaddr);
5176                 np->phyaddr = phyaddr;
5177                 np->phy_oui = id1 | id2;
5178                 break;
5179         }
5180         if (i == 33) {
5181                 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
5182                        pci_name(pci_dev));
5183                 goto out_error;
5184         }
5185
5186         if (!phyinitialized) {
5187                 /* reset it */
5188                 phy_init(dev);
5189         } else {
5190                 /* see if it is a gigabit phy */
5191                 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5192                 if (mii_status & PHY_GIGABIT) {
5193                         np->gigabit = PHY_GIGABIT;
5194                 }
5195         }
5196
5197         /* set default link speed settings */
5198         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5199         np->duplex = 0;
5200         np->autoneg = 1;
5201
5202         err = register_netdev(dev);
5203         if (err) {
5204                 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
5205                 goto out_error;
5206         }
5207         printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
5208                         dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
5209                         pci_name(pci_dev));
5210
5211         return 0;
5212
5213 out_error:
5214         if (phystate_orig)
5215                 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5216         pci_set_drvdata(pci_dev, NULL);
5217 out_freering:
5218         free_rings(dev);
5219 out_unmap:
5220         iounmap(get_hwbase(dev));
5221 out_relreg:
5222         pci_release_regions(pci_dev);
5223 out_disable:
5224         pci_disable_device(pci_dev);
5225 out_free:
5226         free_netdev(dev);
5227 out:
5228         return err;
5229 }
5230
5231 static void __devexit nv_remove(struct pci_dev *pci_dev)
5232 {
5233         struct net_device *dev = pci_get_drvdata(pci_dev);
5234         struct fe_priv *np = netdev_priv(dev);
5235         u8 __iomem *base = get_hwbase(dev);
5236
5237         unregister_netdev(dev);
5238
5239         /* special op: write back the misordered MAC address - otherwise
5240          * the next nv_probe would see a wrong address.
5241          */
5242         writel(np->orig_mac[0], base + NvRegMacAddrA);
5243         writel(np->orig_mac[1], base + NvRegMacAddrB);
5244
5245         /* free all structures */
5246         free_rings(dev);
5247         iounmap(get_hwbase(dev));
5248         pci_release_regions(pci_dev);
5249         pci_disable_device(pci_dev);
5250         free_netdev(dev);
5251         pci_set_drvdata(pci_dev, NULL);
5252 }
5253
5254 #ifdef CONFIG_PM
5255 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
5256 {
5257         struct net_device *dev = pci_get_drvdata(pdev);
5258         struct fe_priv *np = netdev_priv(dev);
5259
5260         if (!netif_running(dev))
5261                 goto out;
5262
5263         netif_device_detach(dev);
5264
5265         // Gross.
5266         nv_close(dev);
5267
5268         pci_save_state(pdev);
5269         pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
5270         pci_set_power_state(pdev, pci_choose_state(pdev, state));
5271 out:
5272         return 0;
5273 }
5274
5275 static int nv_resume(struct pci_dev *pdev)
5276 {
5277         struct net_device *dev = pci_get_drvdata(pdev);
5278         int rc = 0;
5279
5280         if (!netif_running(dev))
5281                 goto out;
5282
5283         netif_device_attach(dev);
5284
5285         pci_set_power_state(pdev, PCI_D0);
5286         pci_restore_state(pdev);
5287         pci_enable_wake(pdev, PCI_D0, 0);
5288
5289         rc = nv_open(dev);
5290 out:
5291         return rc;
5292 }
5293 #else
5294 #define nv_suspend NULL
5295 #define nv_resume NULL
5296 #endif /* CONFIG_PM */
5297
5298 static struct pci_device_id pci_tbl[] = {
5299         {       /* nForce Ethernet Controller */
5300                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
5301                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5302         },
5303         {       /* nForce2 Ethernet Controller */
5304                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
5305                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5306         },
5307         {       /* nForce3 Ethernet Controller */
5308                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
5309                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5310         },
5311         {       /* nForce3 Ethernet Controller */
5312                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
5313                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5314         },
5315         {       /* nForce3 Ethernet Controller */
5316                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
5317                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5318         },
5319         {       /* nForce3 Ethernet Controller */
5320                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
5321                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5322         },
5323         {       /* nForce3 Ethernet Controller */
5324                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
5325                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5326         },
5327         {       /* CK804 Ethernet Controller */
5328                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
5329                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
5330         },
5331         {       /* CK804 Ethernet Controller */
5332                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
5333                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
5334         },
5335         {       /* MCP04 Ethernet Controller */
5336                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
5337                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
5338         },
5339         {       /* MCP04 Ethernet Controller */
5340                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
5341                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
5342         },
5343         {       /* MCP51 Ethernet Controller */
5344                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
5345                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
5346         },
5347         {       /* MCP51 Ethernet Controller */
5348                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
5349                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
5350         },
5351         {       /* MCP55 Ethernet Controller */
5352                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
5353                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5354         },
5355         {       /* MCP55 Ethernet Controller */
5356                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
5357                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5358         },
5359         {       /* MCP61 Ethernet Controller */
5360                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
5361                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5362         },
5363         {       /* MCP61 Ethernet Controller */
5364                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
5365                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5366         },
5367         {       /* MCP61 Ethernet Controller */
5368                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
5369                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5370         },
5371         {       /* MCP61 Ethernet Controller */
5372                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
5373                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5374         },
5375         {       /* MCP65 Ethernet Controller */
5376                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
5377                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5378         },
5379         {       /* MCP65 Ethernet Controller */
5380                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
5381                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5382         },
5383         {       /* MCP65 Ethernet Controller */
5384                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
5385                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5386         },
5387         {       /* MCP65 Ethernet Controller */
5388                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
5389                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5390         },
5391         {       /* MCP67 Ethernet Controller */
5392                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
5393                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5394         },
5395         {       /* MCP67 Ethernet Controller */
5396                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
5397                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5398         },
5399         {       /* MCP67 Ethernet Controller */
5400                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
5401                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5402         },
5403         {       /* MCP67 Ethernet Controller */
5404                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
5405                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5406         },
5407         {0,},
5408 };
5409
5410 static struct pci_driver driver = {
5411         .name = "forcedeth",
5412         .id_table = pci_tbl,
5413         .probe = nv_probe,
5414         .remove = __devexit_p(nv_remove),
5415         .suspend = nv_suspend,
5416         .resume = nv_resume,
5417 };
5418
5419 static int __init init_nic(void)
5420 {
5421         printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
5422         return pci_register_driver(&driver);
5423 }
5424
5425 static void __exit exit_nic(void)
5426 {
5427         pci_unregister_driver(&driver);
5428 }
5429
5430 module_param(max_interrupt_work, int, 0);
5431 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
5432 module_param(optimization_mode, int, 0);
5433 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
5434 module_param(poll_interval, int, 0);
5435 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
5436 module_param(msi, int, 0);
5437 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
5438 module_param(msix, int, 0);
5439 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
5440 module_param(dma_64bit, int, 0);
5441 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
5442
5443 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
5444 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
5445 MODULE_LICENSE("GPL");
5446
5447 MODULE_DEVICE_TABLE(pci, pci_tbl);
5448
5449 module_init(init_nic);
5450 module_exit(exit_nic);