drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey.
   7  *
   8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
   9  * trademarks of NVIDIA Corporation in the United States and other
  10  * countries.
  11  *
  12  * Copyright (C) 2003,4,5 Manfred Spraul
  13  * Copyright (C) 2004 Andrew de Quincey (wol support)
  14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  16  * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License as published by
  20  * the Free Software Foundation; either version 2 of the License, or
  21  * (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  31  *
  32  * Known bugs:
  33  * We suspect that on some hardware no TX done interrupts are generated.
  34  * This means recovery from netif_stop_queue only happens if the hw timer
  35  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
  36  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
  37  * If your hardware reliably generates tx done interrupts, then you can remove
  38  * DEV_NEED_TIMERIRQ from the driver_data flags.
  39  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
  40  * superfluous timer interrupts from the nic.
  41  */
  42
  43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  44
  45 #define FORCEDETH_VERSION               "0.64"
  46 #define DRV_NAME                        "forcedeth"
  47
  48 #include <linux/module.h>
  49 #include <linux/types.h>
  50 #include <linux/pci.h>
  51 #include <linux/interrupt.h>
  52 #include <linux/netdevice.h>
  53 #include <linux/etherdevice.h>
  54 #include <linux/delay.h>
  55 #include <linux/sched.h>
  56 #include <linux/spinlock.h>
  57 #include <linux/ethtool.h>
  58 #include <linux/timer.h>
  59 #include <linux/skbuff.h>
  60 #include <linux/mii.h>
  61 #include <linux/random.h>
  62 #include <linux/init.h>
  63 #include <linux/if_vlan.h>
  64 #include <linux/dma-mapping.h>
  65 #include <linux/slab.h>
  66 #include <linux/uaccess.h>
  67 #include  <linux/io.h>
  68
  69 #include <asm/irq.h>
  70 #include <asm/system.h>
  71
  72 #define TX_WORK_PER_LOOP  64
  73 #define RX_WORK_PER_LOOP  64
  74
  75 /*
  76  * Hardware access:
  77  */
  78
  79 #define DEV_NEED_TIMERIRQ          0x0000001  /* set the timer irq flag in the irq mask */
  80 #define DEV_NEED_LINKTIMER         0x0000002  /* poll link settings. Relies on the timer irq */
  81 #define DEV_HAS_LARGEDESC          0x0000004  /* device supports jumbo frames and needs packet format 2 */
  82 #define DEV_HAS_HIGH_DMA           0x0000008  /* device supports 64bit dma */
  83 #define DEV_HAS_CHECKSUM           0x0000010  /* device supports tx and rx checksum offloads */
  84 #define DEV_HAS_VLAN               0x0000020  /* device supports vlan tagging and striping */
  85 #define DEV_HAS_MSI                0x0000040  /* device supports MSI */
  86 #define DEV_HAS_MSI_X              0x0000080  /* device supports MSI-X */
  87 #define DEV_HAS_POWER_CNTRL        0x0000100  /* device supports power savings */
  88 #define DEV_HAS_STATISTICS_V1      0x0000200  /* device supports hw statistics version 1 */
  89 #define DEV_HAS_STATISTICS_V2      0x0000400  /* device supports hw statistics version 2 */
  90 #define DEV_HAS_STATISTICS_V3      0x0000800  /* device supports hw statistics version 3 */
  91 #define DEV_HAS_STATISTICS_V12     0x0000600  /* device supports hw statistics version 1 and 2 */
  92 #define DEV_HAS_STATISTICS_V123    0x0000e00  /* device supports hw statistics version 1, 2, and 3 */
  93 #define DEV_HAS_TEST_EXTENDED      0x0001000  /* device supports extended diagnostic test */
  94 #define DEV_HAS_MGMT_UNIT          0x0002000  /* device supports management unit */
  95 #define DEV_HAS_CORRECT_MACADDR    0x0004000  /* device supports correct mac address order */
  96 #define DEV_HAS_COLLISION_FIX      0x0008000  /* device supports tx collision fix */
  97 #define DEV_HAS_PAUSEFRAME_TX_V1   0x0010000  /* device supports tx pause frames version 1 */
  98 #define DEV_HAS_PAUSEFRAME_TX_V2   0x0020000  /* device supports tx pause frames version 2 */
  99 #define DEV_HAS_PAUSEFRAME_TX_V3   0x0040000  /* device supports tx pause frames version 3 */
 100 #define DEV_NEED_TX_LIMIT          0x0080000  /* device needs to limit tx */
 101 #define DEV_NEED_TX_LIMIT2         0x0180000  /* device needs to limit tx, expect for some revs */
 102 #define DEV_HAS_GEAR_MODE          0x0200000  /* device supports gear mode */
 103 #define DEV_NEED_PHY_INIT_FIX      0x0400000  /* device needs specific phy workaround */
 104 #define DEV_NEED_LOW_POWER_FIX     0x0800000  /* device needs special power up workaround */
 105 #define DEV_NEED_MSI_FIX           0x1000000  /* device needs msi workaround */
 106
 107 enum {
 108         NvRegIrqStatus = 0x000,
 109 #define NVREG_IRQSTAT_MIIEVENT  0x040
 110 #define NVREG_IRQSTAT_MASK              0x83ff
 111         NvRegIrqMask = 0x004,
 112 #define NVREG_IRQ_RX_ERROR              0x0001
 113 #define NVREG_IRQ_RX                    0x0002
 114 #define NVREG_IRQ_RX_NOBUF              0x0004
 115 #define NVREG_IRQ_TX_ERR                0x0008
 116 #define NVREG_IRQ_TX_OK                 0x0010
 117 #define NVREG_IRQ_TIMER                 0x0020
 118 #define NVREG_IRQ_LINK                  0x0040
 119 #define NVREG_IRQ_RX_FORCED             0x0080
 120 #define NVREG_IRQ_TX_FORCED             0x0100
 121 #define NVREG_IRQ_RECOVER_ERROR         0x8200
 122 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 123 #define NVREG_IRQMASK_CPU               0x0060
 124 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 125 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 126 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
 127
 128         NvRegUnknownSetupReg6 = 0x008,
 129 #define NVREG_UNKSETUP6_VAL             3
 130
 131 /*
 132  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 133  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 134  */
 135         NvRegPollingInterval = 0x00c,
 136 #define NVREG_POLL_DEFAULT_THROUGHPUT   65535 /* backup tx cleanup if loop max reached */
 137 #define NVREG_POLL_DEFAULT_CPU  13
 138         NvRegMSIMap0 = 0x020,
 139         NvRegMSIMap1 = 0x024,
 140         NvRegMSIIrqMask = 0x030,
 141 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 142         NvRegMisc1 = 0x080,
 143 #define NVREG_MISC1_PAUSE_TX    0x01
 144 #define NVREG_MISC1_HD          0x02
 145 #define NVREG_MISC1_FORCE       0x3b0f3c
 146
 147         NvRegMacReset = 0x34,
 148 #define NVREG_MAC_RESET_ASSERT  0x0F3
 149         NvRegTransmitterControl = 0x084,
 150 #define NVREG_XMITCTL_START     0x01
 151 #define NVREG_XMITCTL_MGMT_ST   0x40000000
 152 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
 153 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
 154 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
 155 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
 156 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
 157 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
 158 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
 159 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
 160 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
 161 #define NVREG_XMITCTL_DATA_START        0x00100000
 162 #define NVREG_XMITCTL_DATA_READY        0x00010000
 163 #define NVREG_XMITCTL_DATA_ERROR        0x00020000
 164         NvRegTransmitterStatus = 0x088,
 165 #define NVREG_XMITSTAT_BUSY     0x01
 166
 167         NvRegPacketFilterFlags = 0x8c,
 168 #define NVREG_PFF_PAUSE_RX      0x08
 169 #define NVREG_PFF_ALWAYS        0x7F0000
 170 #define NVREG_PFF_PROMISC       0x80
 171 #define NVREG_PFF_MYADDR        0x20
 172 #define NVREG_PFF_LOOPBACK      0x10
 173
 174         NvRegOffloadConfig = 0x90,
 175 #define NVREG_OFFLOAD_HOMEPHY   0x601
 176 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 177         NvRegReceiverControl = 0x094,
 178 #define NVREG_RCVCTL_START      0x01
 179 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
 180         NvRegReceiverStatus = 0x98,
 181 #define NVREG_RCVSTAT_BUSY      0x01
 182
 183         NvRegSlotTime = 0x9c,
 184 #define NVREG_SLOTTIME_LEGBF_ENABLED    0x80000000
 185 #define NVREG_SLOTTIME_10_100_FULL      0x00007f00
 186 #define NVREG_SLOTTIME_1000_FULL        0x0003ff00
 187 #define NVREG_SLOTTIME_HALF             0x0000ff00
 188 #define NVREG_SLOTTIME_DEFAULT          0x00007f00
 189 #define NVREG_SLOTTIME_MASK             0x000000ff
 190
 191         NvRegTxDeferral = 0xA0,
 192 #define NVREG_TX_DEFERRAL_DEFAULT               0x15050f
 193 #define NVREG_TX_DEFERRAL_RGMII_10_100          0x16070f
 194 #define NVREG_TX_DEFERRAL_RGMII_1000            0x14050f
 195 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10      0x16190f
 196 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100     0x16300f
 197 #define NVREG_TX_DEFERRAL_MII_STRETCH           0x152000
 198         NvRegRxDeferral = 0xA4,
 199 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
 200         NvRegMacAddrA = 0xA8,
 201         NvRegMacAddrB = 0xAC,
 202         NvRegMulticastAddrA = 0xB0,
 203 #define NVREG_MCASTADDRA_FORCE  0x01
 204         NvRegMulticastAddrB = 0xB4,
 205         NvRegMulticastMaskA = 0xB8,
 206 #define NVREG_MCASTMASKA_NONE           0xffffffff
 207         NvRegMulticastMaskB = 0xBC,
 208 #define NVREG_MCASTMASKB_NONE           0xffff
 209
 210         NvRegPhyInterface = 0xC0,
 211 #define PHY_RGMII               0x10000000
 212         NvRegBackOffControl = 0xC4,
 213 #define NVREG_BKOFFCTRL_DEFAULT                 0x70000000
 214 #define NVREG_BKOFFCTRL_SEED_MASK               0x000003ff
 215 #define NVREG_BKOFFCTRL_SELECT                  24
 216 #define NVREG_BKOFFCTRL_GEAR                    12
 217
 218         NvRegTxRingPhysAddr = 0x100,
 219         NvRegRxRingPhysAddr = 0x104,
 220         NvRegRingSizes = 0x108,
 221 #define NVREG_RINGSZ_TXSHIFT 0
 222 #define NVREG_RINGSZ_RXSHIFT 16
 223         NvRegTransmitPoll = 0x10c,
 224 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
 225         NvRegLinkSpeed = 0x110,
 226 #define NVREG_LINKSPEED_FORCE 0x10000
 227 #define NVREG_LINKSPEED_10      1000
 228 #define NVREG_LINKSPEED_100     100
 229 #define NVREG_LINKSPEED_1000    50
 230 #define NVREG_LINKSPEED_MASK    (0xFFF)
 231         NvRegUnknownSetupReg5 = 0x130,
 232 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 233         NvRegTxWatermark = 0x13c,
 234 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
 235 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
 236 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
 237         NvRegTxRxControl = 0x144,
 238 #define NVREG_TXRXCTL_KICK      0x0001
 239 #define NVREG_TXRXCTL_BIT1      0x0002
 240 #define NVREG_TXRXCTL_BIT2      0x0004
 241 #define NVREG_TXRXCTL_IDLE      0x0008
 242 #define NVREG_TXRXCTL_RESET     0x0010
 243 #define NVREG_TXRXCTL_RXCHECK   0x0400
 244 #define NVREG_TXRXCTL_DESC_1    0
 245 #define NVREG_TXRXCTL_DESC_2    0x002100
 246 #define NVREG_TXRXCTL_DESC_3    0xc02200
 247 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 248 #define NVREG_TXRXCTL_VLANINS   0x00080
 249         NvRegTxRingPhysAddrHigh = 0x148,
 250         NvRegRxRingPhysAddrHigh = 0x14C,
 251         NvRegTxPauseFrame = 0x170,
 252 #define NVREG_TX_PAUSEFRAME_DISABLE     0x0fff0080
 253 #define NVREG_TX_PAUSEFRAME_ENABLE_V1   0x01800010
 254 #define NVREG_TX_PAUSEFRAME_ENABLE_V2   0x056003f0
 255 #define NVREG_TX_PAUSEFRAME_ENABLE_V3   0x09f00880
 256         NvRegTxPauseFrameLimit = 0x174,
 257 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
 258         NvRegMIIStatus = 0x180,
 259 #define NVREG_MIISTAT_ERROR             0x0001
 260 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 261 #define NVREG_MIISTAT_MASK_RW           0x0007
 262 #define NVREG_MIISTAT_MASK_ALL          0x000f
 263         NvRegMIIMask = 0x184,
 264 #define NVREG_MII_LINKCHANGE            0x0008
 265
 266         NvRegAdapterControl = 0x188,
 267 #define NVREG_ADAPTCTL_START    0x02
 268 #define NVREG_ADAPTCTL_LINKUP   0x04
 269 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 270 #define NVREG_ADAPTCTL_RUNNING  0x100000
 271 #define NVREG_ADAPTCTL_PHYSHIFT 24
 272         NvRegMIISpeed = 0x18c,
 273 #define NVREG_MIISPEED_BIT8     (1<<8)
 274 #define NVREG_MIIDELAY  5
 275         NvRegMIIControl = 0x190,
 276 #define NVREG_MIICTL_INUSE      0x08000
 277 #define NVREG_MIICTL_WRITE      0x00400
 278 #define NVREG_MIICTL_ADDRSHIFT  5
 279         NvRegMIIData = 0x194,
 280         NvRegTxUnicast = 0x1a0,
 281         NvRegTxMulticast = 0x1a4,
 282         NvRegTxBroadcast = 0x1a8,
 283         NvRegWakeUpFlags = 0x200,
 284 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 285 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 286 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 287 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 288 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 289 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 290 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 291 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 292 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 293 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 294 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 295
 296         NvRegMgmtUnitGetVersion = 0x204,
 297 #define NVREG_MGMTUNITGETVERSION        0x01
 298         NvRegMgmtUnitVersion = 0x208,
 299 #define NVREG_MGMTUNITVERSION           0x08
 300         NvRegPowerCap = 0x268,
 301 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 302 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 303 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 304         NvRegPowerState = 0x26c,
 305 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 306 #define NVREG_POWERSTATE_VALID          0x0100
 307 #define NVREG_POWERSTATE_MASK           0x0003
 308 #define NVREG_POWERSTATE_D0             0x0000
 309 #define NVREG_POWERSTATE_D1             0x0001
 310 #define NVREG_POWERSTATE_D2             0x0002
 311 #define NVREG_POWERSTATE_D3             0x0003
 312         NvRegMgmtUnitControl = 0x278,
 313 #define NVREG_MGMTUNITCONTROL_INUSE     0x20000
 314         NvRegTxCnt = 0x280,
 315         NvRegTxZeroReXmt = 0x284,
 316         NvRegTxOneReXmt = 0x288,
 317         NvRegTxManyReXmt = 0x28c,
 318         NvRegTxLateCol = 0x290,
 319         NvRegTxUnderflow = 0x294,
 320         NvRegTxLossCarrier = 0x298,
 321         NvRegTxExcessDef = 0x29c,
 322         NvRegTxRetryErr = 0x2a0,
 323         NvRegRxFrameErr = 0x2a4,
 324         NvRegRxExtraByte = 0x2a8,
 325         NvRegRxLateCol = 0x2ac,
 326         NvRegRxRunt = 0x2b0,
 327         NvRegRxFrameTooLong = 0x2b4,
 328         NvRegRxOverflow = 0x2b8,
 329         NvRegRxFCSErr = 0x2bc,
 330         NvRegRxFrameAlignErr = 0x2c0,
 331         NvRegRxLenErr = 0x2c4,
 332         NvRegRxUnicast = 0x2c8,
 333         NvRegRxMulticast = 0x2cc,
 334         NvRegRxBroadcast = 0x2d0,
 335         NvRegTxDef = 0x2d4,
 336         NvRegTxFrame = 0x2d8,
 337         NvRegRxCnt = 0x2dc,
 338         NvRegTxPause = 0x2e0,
 339         NvRegRxPause = 0x2e4,
 340         NvRegRxDropFrame = 0x2e8,
 341         NvRegVlanControl = 0x300,
 342 #define NVREG_VLANCONTROL_ENABLE        0x2000
 343         NvRegMSIXMap0 = 0x3e0,
 344         NvRegMSIXMap1 = 0x3e4,
 345         NvRegMSIXIrqStatus = 0x3f0,
 346
 347         NvRegPowerState2 = 0x600,
 348 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F15
 349 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 350 #define NVREG_POWERSTATE2_PHY_RESET             0x0004
 351 #define NVREG_POWERSTATE2_GATE_CLOCKS           0x0F00
 352 };
 353
 354 /* Big endian: should work, but is untested */
 355 struct ring_desc {
 356         __le32 buf;
 357         __le32 flaglen;
 358 };
 359
 360 struct ring_desc_ex {
 361         __le32 bufhigh;
 362         __le32 buflow;
 363         __le32 txvlan;
 364         __le32 flaglen;
 365 };
 366
 367 union ring_type {
 368         struct ring_desc *orig;
 369         struct ring_desc_ex *ex;
 370 };
 371
 372 #define FLAG_MASK_V1 0xffff0000
 373 #define FLAG_MASK_V2 0xffffc000
 374 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 375 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 376
 377 #define NV_TX_LASTPACKET        (1<<16)
 378 #define NV_TX_RETRYERROR        (1<<19)
 379 #define NV_TX_RETRYCOUNT_MASK   (0xF<<20)
 380 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 381 #define NV_TX_DEFERRED          (1<<26)
 382 #define NV_TX_CARRIERLOST       (1<<27)
 383 #define NV_TX_LATECOLLISION     (1<<28)
 384 #define NV_TX_UNDERFLOW         (1<<29)
 385 #define NV_TX_ERROR             (1<<30)
 386 #define NV_TX_VALID             (1<<31)
 387
 388 #define NV_TX2_LASTPACKET       (1<<29)
 389 #define NV_TX2_RETRYERROR       (1<<18)
 390 #define NV_TX2_RETRYCOUNT_MASK  (0xF<<19)
 391 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 392 #define NV_TX2_DEFERRED         (1<<25)
 393 #define NV_TX2_CARRIERLOST      (1<<26)
 394 #define NV_TX2_LATECOLLISION    (1<<27)
 395 #define NV_TX2_UNDERFLOW        (1<<28)
 396 /* error and valid are the same for both */
 397 #define NV_TX2_ERROR            (1<<30)
 398 #define NV_TX2_VALID            (1<<31)
 399 #define NV_TX2_TSO              (1<<28)
 400 #define NV_TX2_TSO_SHIFT        14
 401 #define NV_TX2_TSO_MAX_SHIFT    14
 402 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 403 #define NV_TX2_CHECKSUM_L3      (1<<27)
 404 #define NV_TX2_CHECKSUM_L4      (1<<26)
 405
 406 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 407
 408 #define NV_RX_DESCRIPTORVALID   (1<<16)
 409 #define NV_RX_MISSEDFRAME       (1<<17)
 410 #define NV_RX_SUBSTRACT1        (1<<18)
 411 #define NV_RX_ERROR1            (1<<23)
 412 #define NV_RX_ERROR2            (1<<24)
 413 #define NV_RX_ERROR3            (1<<25)
 414 #define NV_RX_ERROR4            (1<<26)
 415 #define NV_RX_CRCERR            (1<<27)
 416 #define NV_RX_OVERFLOW          (1<<28)
 417 #define NV_RX_FRAMINGERR        (1<<29)
 418 #define NV_RX_ERROR             (1<<30)
 419 #define NV_RX_AVAIL             (1<<31)
 420 #define NV_RX_ERROR_MASK        (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
 421
 422 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 423 #define NV_RX2_CHECKSUM_IP      (0x10000000)
 424 #define NV_RX2_CHECKSUM_IP_TCP  (0x14000000)
 425 #define NV_RX2_CHECKSUM_IP_UDP  (0x18000000)
 426 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 427 #define NV_RX2_SUBSTRACT1       (1<<25)
 428 #define NV_RX2_ERROR1           (1<<18)
 429 #define NV_RX2_ERROR2           (1<<19)
 430 #define NV_RX2_ERROR3           (1<<20)
 431 #define NV_RX2_ERROR4           (1<<21)
 432 #define NV_RX2_CRCERR           (1<<22)
 433 #define NV_RX2_OVERFLOW         (1<<23)
 434 #define NV_RX2_FRAMINGERR       (1<<24)
 435 /* error and avail are the same for both */
 436 #define NV_RX2_ERROR            (1<<30)
 437 #define NV_RX2_AVAIL            (1<<31)
 438 #define NV_RX2_ERROR_MASK       (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
 439
 440 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 441 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 442
 443 /* Miscelaneous hardware related defines: */
 444 #define NV_PCI_REGSZ_VER1       0x270
 445 #define NV_PCI_REGSZ_VER2       0x2d4
 446 #define NV_PCI_REGSZ_VER3       0x604
 447 #define NV_PCI_REGSZ_MAX        0x604
 448
 449 /* various timeout delays: all in usec */
 450 #define NV_TXRX_RESET_DELAY     4
 451 #define NV_TXSTOP_DELAY1        10
 452 #define NV_TXSTOP_DELAY1MAX     500000
 453 #define NV_TXSTOP_DELAY2        100
 454 #define NV_RXSTOP_DELAY1        10
 455 #define NV_RXSTOP_DELAY1MAX     500000
 456 #define NV_RXSTOP_DELAY2        100
 457 #define NV_SETUP5_DELAY         5
 458 #define NV_SETUP5_DELAYMAX      50000
 459 #define NV_POWERUP_DELAY        5
 460 #define NV_POWERUP_DELAYMAX     5000
 461 #define NV_MIIBUSY_DELAY        50
 462 #define NV_MIIPHY_DELAY 10
 463 #define NV_MIIPHY_DELAYMAX      10000
 464 #define NV_MAC_RESET_DELAY      64
 465
 466 #define NV_WAKEUPPATTERNS       5
 467 #define NV_WAKEUPMASKENTRIES    4
 468
 469 /* General driver defaults */
 470 #define NV_WATCHDOG_TIMEO       (5*HZ)
 471
 472 #define RX_RING_DEFAULT         512
 473 #define TX_RING_DEFAULT         256
 474 #define RX_RING_MIN             128
 475 #define TX_RING_MIN             64
 476 #define RING_MAX_DESC_VER_1     1024
 477 #define RING_MAX_DESC_VER_2_3   16384
 478
 479 /* rx/tx mac addr + type + vlan + align + slack*/
 480 #define NV_RX_HEADERS           (64)
 481 /* even more slack. */
 482 #define NV_RX_ALLOC_PAD         (64)
 483
 484 /* maximum mtu size */
 485 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 486 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 487
 488 #define OOM_REFILL      (1+HZ/20)
 489 #define POLL_WAIT       (1+HZ/100)
 490 #define LINK_TIMEOUT    (3*HZ)
 491 #define STATS_INTERVAL  (10*HZ)
 492
 493 /*
 494  * desc_ver values:
 495  * The nic supports three different descriptor types:
 496  * - DESC_VER_1: Original
 497  * - DESC_VER_2: support for jumbo frames.
 498  * - DESC_VER_3: 64-bit format.
 499  */
 500 #define DESC_VER_1      1
 501 #define DESC_VER_2      2
 502 #define DESC_VER_3      3
 503
 504 /* PHY defines */
 505 #define PHY_OUI_MARVELL         0x5043
 506 #define PHY_OUI_CICADA          0x03f1
 507 #define PHY_OUI_VITESSE         0x01c1
 508 #define PHY_OUI_REALTEK         0x0732
 509 #define PHY_OUI_REALTEK2        0x0020
 510 #define PHYID1_OUI_MASK 0x03ff
 511 #define PHYID1_OUI_SHFT 6
 512 #define PHYID2_OUI_MASK 0xfc00
 513 #define PHYID2_OUI_SHFT 10
 514 #define PHYID2_MODEL_MASK               0x03f0
 515 #define PHY_MODEL_REALTEK_8211          0x0110
 516 #define PHY_REV_MASK                    0x0001
 517 #define PHY_REV_REALTEK_8211B           0x0000
 518 #define PHY_REV_REALTEK_8211C           0x0001
 519 #define PHY_MODEL_REALTEK_8201          0x0200
 520 #define PHY_MODEL_MARVELL_E3016         0x0220
 521 #define PHY_MARVELL_E3016_INITMASK      0x0300
 522 #define PHY_CICADA_INIT1        0x0f000
 523 #define PHY_CICADA_INIT2        0x0e00
 524 #define PHY_CICADA_INIT3        0x01000
 525 #define PHY_CICADA_INIT4        0x0200
 526 #define PHY_CICADA_INIT5        0x0004
 527 #define PHY_CICADA_INIT6        0x02000
 528 #define PHY_VITESSE_INIT_REG1   0x1f
 529 #define PHY_VITESSE_INIT_REG2   0x10
 530 #define PHY_VITESSE_INIT_REG3   0x11
 531 #define PHY_VITESSE_INIT_REG4   0x12
 532 #define PHY_VITESSE_INIT_MSK1   0xc
 533 #define PHY_VITESSE_INIT_MSK2   0x0180
 534 #define PHY_VITESSE_INIT1       0x52b5
 535 #define PHY_VITESSE_INIT2       0xaf8a
 536 #define PHY_VITESSE_INIT3       0x8
 537 #define PHY_VITESSE_INIT4       0x8f8a
 538 #define PHY_VITESSE_INIT5       0xaf86
 539 #define PHY_VITESSE_INIT6       0x8f86
 540 #define PHY_VITESSE_INIT7       0xaf82
 541 #define PHY_VITESSE_INIT8       0x0100
 542 #define PHY_VITESSE_INIT9       0x8f82
 543 #define PHY_VITESSE_INIT10      0x0
 544 #define PHY_REALTEK_INIT_REG1   0x1f
 545 #define PHY_REALTEK_INIT_REG2   0x19
 546 #define PHY_REALTEK_INIT_REG3   0x13
 547 #define PHY_REALTEK_INIT_REG4   0x14
 548 #define PHY_REALTEK_INIT_REG5   0x18
 549 #define PHY_REALTEK_INIT_REG6   0x11
 550 #define PHY_REALTEK_INIT_REG7   0x01
 551 #define PHY_REALTEK_INIT1       0x0000
 552 #define PHY_REALTEK_INIT2       0x8e00
 553 #define PHY_REALTEK_INIT3       0x0001
 554 #define PHY_REALTEK_INIT4       0xad17
 555 #define PHY_REALTEK_INIT5       0xfb54
 556 #define PHY_REALTEK_INIT6       0xf5c7
 557 #define PHY_REALTEK_INIT7       0x1000
 558 #define PHY_REALTEK_INIT8       0x0003
 559 #define PHY_REALTEK_INIT9       0x0008
 560 #define PHY_REALTEK_INIT10      0x0005
 561 #define PHY_REALTEK_INIT11      0x0200
 562 #define PHY_REALTEK_INIT_MSK1   0x0003
 563
 564 #define PHY_GIGABIT     0x0100
 565
 566 #define PHY_TIMEOUT     0x1
 567 #define PHY_ERROR       0x2
 568
 569 #define PHY_100 0x1
 570 #define PHY_1000        0x2
 571 #define PHY_HALF        0x100
 572
 573 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 574 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 575 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 576 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 577 #define NV_PAUSEFRAME_RX_REQ     0x0010
 578 #define NV_PAUSEFRAME_TX_REQ     0x0020
 579 #define NV_PAUSEFRAME_AUTONEG    0x0040
 580
 581 /* MSI/MSI-X defines */
 582 #define NV_MSI_X_MAX_VECTORS  8
 583 #define NV_MSI_X_VECTORS_MASK 0x000f
 584 #define NV_MSI_CAPABLE        0x0010
 585 #define NV_MSI_X_CAPABLE      0x0020
 586 #define NV_MSI_ENABLED        0x0040
 587 #define NV_MSI_X_ENABLED      0x0080
 588
 589 #define NV_MSI_X_VECTOR_ALL   0x0
 590 #define NV_MSI_X_VECTOR_RX    0x0
 591 #define NV_MSI_X_VECTOR_TX    0x1
 592 #define NV_MSI_X_VECTOR_OTHER 0x2
 593
 594 #define NV_MSI_PRIV_OFFSET 0x68
 595 #define NV_MSI_PRIV_VALUE  0xffffffff
 596
 597 #define NV_RESTART_TX         0x1
 598 #define NV_RESTART_RX         0x2
 599
 600 #define NV_TX_LIMIT_COUNT     16
 601
 602 #define NV_DYNAMIC_THRESHOLD        4
 603 #define NV_DYNAMIC_MAX_QUIET_COUNT  2048
 604
 605 /* statistics */
 606 struct nv_ethtool_str {
 607         char name[ETH_GSTRING_LEN];
 608 };
 609
 610 static const struct nv_ethtool_str nv_estats_str[] = {
 611         { "tx_bytes" },
 612         { "tx_zero_rexmt" },
 613         { "tx_one_rexmt" },
 614         { "tx_many_rexmt" },
 615         { "tx_late_collision" },
 616         { "tx_fifo_errors" },
 617         { "tx_carrier_errors" },
 618         { "tx_excess_deferral" },
 619         { "tx_retry_error" },
 620         { "rx_frame_error" },
 621         { "rx_extra_byte" },
 622         { "rx_late_collision" },
 623         { "rx_runt" },
 624         { "rx_frame_too_long" },
 625         { "rx_over_errors" },
 626         { "rx_crc_errors" },
 627         { "rx_frame_align_error" },
 628         { "rx_length_error" },
 629         { "rx_unicast" },
 630         { "rx_multicast" },
 631         { "rx_broadcast" },
 632         { "rx_packets" },
 633         { "rx_errors_total" },
 634         { "tx_errors_total" },
 635
 636         /* version 2 stats */
 637         { "tx_deferral" },
 638         { "tx_packets" },
 639         { "rx_bytes" },
 640         { "tx_pause" },
 641         { "rx_pause" },
 642         { "rx_drop_frame" },
 643
 644         /* version 3 stats */
 645         { "tx_unicast" },
 646         { "tx_multicast" },
 647         { "tx_broadcast" }
 648 };
 649
 650 struct nv_ethtool_stats {
 651         u64 tx_bytes;
 652         u64 tx_zero_rexmt;
 653         u64 tx_one_rexmt;
 654         u64 tx_many_rexmt;
 655         u64 tx_late_collision;
 656         u64 tx_fifo_errors;
 657         u64 tx_carrier_errors;
 658         u64 tx_excess_deferral;
 659         u64 tx_retry_error;
 660         u64 rx_frame_error;
 661         u64 rx_extra_byte;
 662         u64 rx_late_collision;
 663         u64 rx_runt;
 664         u64 rx_frame_too_long;
 665         u64 rx_over_errors;
 666         u64 rx_crc_errors;
 667         u64 rx_frame_align_error;
 668         u64 rx_length_error;
 669         u64 rx_unicast;
 670         u64 rx_multicast;
 671         u64 rx_broadcast;
 672         u64 rx_packets;
 673         u64 rx_errors_total;
 674         u64 tx_errors_total;
 675
 676         /* version 2 stats */
 677         u64 tx_deferral;
 678         u64 tx_packets;
 679         u64 rx_bytes;
 680         u64 tx_pause;
 681         u64 rx_pause;
 682         u64 rx_drop_frame;
 683
 684         /* version 3 stats */
 685         u64 tx_unicast;
 686         u64 tx_multicast;
 687         u64 tx_broadcast;
 688 };
 689
 690 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
 691 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
 692 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
 693
 694 /* diagnostics */
 695 #define NV_TEST_COUNT_BASE 3
 696 #define NV_TEST_COUNT_EXTENDED 4
 697
 698 static const struct nv_ethtool_str nv_etests_str[] = {
 699         { "link      (online/offline)" },
 700         { "register  (offline)       " },
 701         { "interrupt (offline)       " },
 702         { "loopback  (offline)       " }
 703 };
 704
 705 struct register_test {
 706         __u32 reg;
 707         __u32 mask;
 708 };
 709
 710 static const struct register_test nv_registers_test[] = {
 711         { NvRegUnknownSetupReg6, 0x01 },
 712         { NvRegMisc1, 0x03c },
 713         { NvRegOffloadConfig, 0x03ff },
 714         { NvRegMulticastAddrA, 0xffffffff },
 715         { NvRegTxWatermark, 0x0ff },
 716         { NvRegWakeUpFlags, 0x07777 },
 717         { 0, 0 }
 718 };
 719
 720 struct nv_skb_map {
 721         struct sk_buff *skb;
 722         dma_addr_t dma;
 723         unsigned int dma_len:31;
 724         unsigned int dma_single:1;
 725         struct ring_desc_ex *first_tx_desc;
 726         struct nv_skb_map *next_tx_ctx;
 727 };
 728
 729 /*
 730  * SMP locking:
 731  * All hardware access under netdev_priv(dev)->lock, except the performance
 732  * critical parts:
 733  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 734  *      by the arch code for interrupts.
 735  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 736  *      needs netdev_priv(dev)->lock :-(
 737  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 738  */
 739
 740 /* in dev: base, irq */
 741 struct fe_priv {
 742         spinlock_t lock;
 743
 744         struct net_device *dev;
 745         struct napi_struct napi;
 746
 747         /* General data:
 748          * Locking: spin_lock(&np->lock); */
 749         struct nv_ethtool_stats estats;
 750         int in_shutdown;
 751         u32 linkspeed;
 752         int duplex;
 753         int autoneg;
 754         int fixed_mode;
 755         int phyaddr;
 756         int wolenabled;
 757         unsigned int phy_oui;
 758         unsigned int phy_model;
 759         unsigned int phy_rev;
 760         u16 gigabit;
 761         int intr_test;
 762         int recover_error;
 763         int quiet_count;
 764
 765         /* General data: RO fields */
 766         dma_addr_t ring_addr;
 767         struct pci_dev *pci_dev;
 768         u32 orig_mac[2];
 769         u32 events;
 770         u32 irqmask;
 771         u32 desc_ver;
 772         u32 txrxctl_bits;
 773         u32 vlanctl_bits;
 774         u32 driver_data;
 775         u32 device_id;
 776         u32 register_size;
 777         int rx_csum;
 778         u32 mac_in_use;
 779         int mgmt_version;
 780         int mgmt_sema;
 781
 782         void __iomem *base;
 783
 784         /* rx specific fields.
 785          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 786          */
 787         union ring_type get_rx, put_rx, first_rx, last_rx;
 788         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
 789         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
 790         struct nv_skb_map *rx_skb;
 791
 792         union ring_type rx_ring;
 793         unsigned int rx_buf_sz;
 794         unsigned int pkt_limit;
 795         struct timer_list oom_kick;
 796         struct timer_list nic_poll;
 797         struct timer_list stats_poll;
 798         u32 nic_poll_irq;
 799         int rx_ring_size;
 800
 801         /* media detection workaround.
 802          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 803          */
 804         int need_linktimer;
 805         unsigned long link_timeout;
 806         /*
 807          * tx specific fields.
 808          */
 809         union ring_type get_tx, put_tx, first_tx, last_tx;
 810         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
 811         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
 812         struct nv_skb_map *tx_skb;
 813
 814         union ring_type tx_ring;
 815         u32 tx_flags;
 816         int tx_ring_size;
 817         int tx_limit;
 818         u32 tx_pkts_in_progress;
 819         struct nv_skb_map *tx_change_owner;
 820         struct nv_skb_map *tx_end_flip;
 821         int tx_stop;
 822
 823         /* vlan fields */
 824         struct vlan_group *vlangrp;
 825
 826         /* msi/msi-x fields */
 827         u32 msi_flags;
 828         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 829
 830         /* flow control */
 831         u32 pause_flags;
 832
 833         /* power saved state */
 834         u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
 835
 836         /* for different msi-x irq type */
 837         char name_rx[IFNAMSIZ + 3];       /* -rx    */
 838         char name_tx[IFNAMSIZ + 3];       /* -tx    */
 839         char name_other[IFNAMSIZ + 6];    /* -other */
 840 };
 841
 842 /*
 843  * Maximum number of loops until we assume that a bit in the irq mask
 844  * is stuck. Overridable with module param.
 845  */
 846 static int max_interrupt_work = 4;
 847
 848 /*
 849  * Optimization can be either throuput mode or cpu mode
 850  *
 851  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 852  * CPU Mode: Interrupts are controlled by a timer.
 853  */
 854 enum {
 855         NV_OPTIMIZATION_MODE_THROUGHPUT,
 856         NV_OPTIMIZATION_MODE_CPU,
 857         NV_OPTIMIZATION_MODE_DYNAMIC
 858 };
 859 static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
 860
 861 /*
 862  * Poll interval for timer irq
 863  *
 864  * This interval determines how frequent an interrupt is generated.
 865  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 866  * Min = 0, and Max = 65535
 867  */
 868 static int poll_interval = -1;
 869
 870 /*
 871  * MSI interrupts
 872  */
 873 enum {
 874         NV_MSI_INT_DISABLED,
 875         NV_MSI_INT_ENABLED
 876 };
 877 static int msi = NV_MSI_INT_ENABLED;
 878
 879 /*
 880  * MSIX interrupts
 881  */
 882 enum {
 883         NV_MSIX_INT_DISABLED,
 884         NV_MSIX_INT_ENABLED
 885 };
 886 static int msix = NV_MSIX_INT_ENABLED;
 887
 888 /*
 889  * DMA 64bit
 890  */
 891 enum {
 892         NV_DMA_64BIT_DISABLED,
 893         NV_DMA_64BIT_ENABLED
 894 };
 895 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 896
 897 /*
 898  * Crossover Detection
 899  * Realtek 8201 phy + some OEM boards do not work properly.
 900  */
 901 enum {
 902         NV_CROSSOVER_DETECTION_DISABLED,
 903         NV_CROSSOVER_DETECTION_ENABLED
 904 };
 905 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
 906
 907 /*
 908  * Power down phy when interface is down (persists through reboot;
 909  * older Linux and other OSes may not power it up again)
 910  */
 911 static int phy_power_down;
 912
 913 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 914 {
 915         return netdev_priv(dev);
 916 }
 917
 918 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 919 {
 920         return ((struct fe_priv *)netdev_priv(dev))->base;
 921 }
 922
 923 static inline void pci_push(u8 __iomem *base)
 924 {
 925         /* force out pending posted writes */
 926         readl(base);
 927 }
 928
 929 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 930 {
 931         return le32_to_cpu(prd->flaglen)
 932                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 933 }
 934
 935 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 936 {
 937         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
 938 }
 939
 940 static bool nv_optimized(struct fe_priv *np)
 941 {
 942         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 943                 return false;
 944         return true;
 945 }
 946
 947 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 948                      int delay, int delaymax)
 949 {
 950         u8 __iomem *base = get_hwbase(dev);
 951
 952         pci_push(base);
 953         do {
 954                 udelay(delay);
 955                 delaymax -= delay;
 956                 if (delaymax < 0)
 957                         return 1;
 958         } while ((readl(base + offset) & mask) != target);
 959         return 0;
 960 }
 961
 962 #define NV_SETUP_RX_RING 0x01
 963 #define NV_SETUP_TX_RING 0x02
 964
 965 static inline u32 dma_low(dma_addr_t addr)
 966 {
 967         return addr;
 968 }
 969
 970 static inline u32 dma_high(dma_addr_t addr)
 971 {
 972         return addr>>31>>1;     /* 0 if 32bit, shift down by 32 if 64bit */
 973 }
 974
 975 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
 976 {
 977         struct fe_priv *np = get_nvpriv(dev);
 978         u8 __iomem *base = get_hwbase(dev);
 979
 980         if (!nv_optimized(np)) {
 981                 if (rxtx_flags & NV_SETUP_RX_RING)
 982                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
 983                 if (rxtx_flags & NV_SETUP_TX_RING)
 984                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
 985         } else {
 986                 if (rxtx_flags & NV_SETUP_RX_RING) {
 987                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
 988                         writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
 989                 }
 990                 if (rxtx_flags & NV_SETUP_TX_RING) {
 991                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
 992                         writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
 993                 }
 994         }
 995 }
 996
 997 static void free_rings(struct net_device *dev)
 998 {
 999         struct fe_priv *np = get_nvpriv(dev);
1000
1001         if (!nv_optimized(np)) {
1002                 if (np->rx_ring.orig)
1003                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
1004                                             np->rx_ring.orig, np->ring_addr);
1005         } else {
1006                 if (np->rx_ring.ex)
1007                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1008                                             np->rx_ring.ex, np->ring_addr);
1009         }
1010         kfree(np->rx_skb);
1011         kfree(np->tx_skb);
1012 }
1013
1014 static int using_multi_irqs(struct net_device *dev)
1015 {
1016         struct fe_priv *np = get_nvpriv(dev);
1017
1018         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1019             ((np->msi_flags & NV_MSI_X_ENABLED) &&
1020              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1021                 return 0;
1022         else
1023                 return 1;
1024 }
1025
1026 static void nv_txrx_gate(struct net_device *dev, bool gate)
1027 {
1028         struct fe_priv *np = get_nvpriv(dev);
1029         u8 __iomem *base = get_hwbase(dev);
1030         u32 powerstate;
1031
1032         if (!np->mac_in_use &&
1033             (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1034                 powerstate = readl(base + NvRegPowerState2);
1035                 if (gate)
1036                         powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1037                 else
1038                         powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1039                 writel(powerstate, base + NvRegPowerState2);
1040         }
1041 }
1042
1043 static void nv_enable_irq(struct net_device *dev)
1044 {
1045         struct fe_priv *np = get_nvpriv(dev);
1046
1047         if (!using_multi_irqs(dev)) {
1048                 if (np->msi_flags & NV_MSI_X_ENABLED)
1049                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1050                 else
1051                         enable_irq(np->pci_dev->irq);
1052         } else {
1053                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1054                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1055                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1056         }
1057 }
1058
1059 static void nv_disable_irq(struct net_device *dev)
1060 {
1061         struct fe_priv *np = get_nvpriv(dev);
1062
1063         if (!using_multi_irqs(dev)) {
1064                 if (np->msi_flags & NV_MSI_X_ENABLED)
1065                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1066                 else
1067                         disable_irq(np->pci_dev->irq);
1068         } else {
1069                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1070                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1071                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1072         }
1073 }
1074
1075 /* In MSIX mode, a write to irqmask behaves as XOR */
1076 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1077 {
1078         u8 __iomem *base = get_hwbase(dev);
1079
1080         writel(mask, base + NvRegIrqMask);
1081 }
1082
1083 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1084 {
1085         struct fe_priv *np = get_nvpriv(dev);
1086         u8 __iomem *base = get_hwbase(dev);
1087
1088         if (np->msi_flags & NV_MSI_X_ENABLED) {
1089                 writel(mask, base + NvRegIrqMask);
1090         } else {
1091                 if (np->msi_flags & NV_MSI_ENABLED)
1092                         writel(0, base + NvRegMSIIrqMask);
1093                 writel(0, base + NvRegIrqMask);
1094         }
1095 }
1096
1097 static void nv_napi_enable(struct net_device *dev)
1098 {
1099         struct fe_priv *np = get_nvpriv(dev);
1100
1101         napi_enable(&np->napi);
1102 }
1103
1104 static void nv_napi_disable(struct net_device *dev)
1105 {
1106         struct fe_priv *np = get_nvpriv(dev);
1107
1108         napi_disable(&np->napi);
1109 }
1110
1111 #define MII_READ        (-1)
1112 /* mii_rw: read/write a register on the PHY.
1113  *
1114  * Caller must guarantee serialization
1115  */
1116 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1117 {
1118         u8 __iomem *base = get_hwbase(dev);
1119         u32 reg;
1120         int retval;
1121
1122         writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1123
1124         reg = readl(base + NvRegMIIControl);
1125         if (reg & NVREG_MIICTL_INUSE) {
1126                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1127                 udelay(NV_MIIBUSY_DELAY);
1128         }
1129
1130         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1131         if (value != MII_READ) {
1132                 writel(value, base + NvRegMIIData);
1133                 reg |= NVREG_MIICTL_WRITE;
1134         }
1135         writel(reg, base + NvRegMIIControl);
1136
1137         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1138                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) {
1139                 netdev_dbg(dev, "mii_rw of reg %d at PHY %d timed out\n",
1140                            miireg, addr);
1141                 retval = -1;
1142         } else if (value != MII_READ) {
1143                 /* it was a write operation - fewer failures are detectable */
1144                 netdev_dbg(dev, "mii_rw wrote 0x%x to reg %d at PHY %d\n",
1145                            value, miireg, addr);
1146                 retval = 0;
1147         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1148                 netdev_dbg(dev, "mii_rw of reg %d at PHY %d failed\n",
1149                            miireg, addr);
1150                 retval = -1;
1151         } else {
1152                 retval = readl(base + NvRegMIIData);
1153                 netdev_dbg(dev, "mii_rw read from reg %d at PHY %d: 0x%x\n",
1154                            miireg, addr, retval);
1155         }
1156
1157         return retval;
1158 }
1159
1160 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1161 {
1162         struct fe_priv *np = netdev_priv(dev);
1163         u32 miicontrol;
1164         unsigned int tries = 0;
1165
1166         miicontrol = BMCR_RESET | bmcr_setup;
1167         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
1168                 return -1;
1169
1170         /* wait for 500ms */
1171         msleep(500);
1172
1173         /* must wait till reset is deasserted */
1174         while (miicontrol & BMCR_RESET) {
1175                 usleep_range(10000, 20000);
1176                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1177                 /* FIXME: 100 tries seem excessive */
1178                 if (tries++ > 100)
1179                         return -1;
1180         }
1181         return 0;
1182 }
1183
1184 static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np)
1185 {
1186         static const struct {
1187                 int reg;
1188                 int init;
1189         } ri[] = {
1190                 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1191                 { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 },
1192                 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 },
1193                 { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 },
1194                 { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 },
1195                 { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 },
1196                 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1197         };
1198         int i;
1199
1200         for (i = 0; i < ARRAY_SIZE(ri); i++) {
1201                 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init))
1202                         return PHY_ERROR;
1203         }
1204
1205         return 0;
1206 }
1207
1208 static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np)
1209 {
1210         u32 reg;
1211         u8 __iomem *base = get_hwbase(dev);
1212         u32 powerstate = readl(base + NvRegPowerState2);
1213
1214         /* need to perform hw phy reset */
1215         powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1216         writel(powerstate, base + NvRegPowerState2);
1217         msleep(25);
1218
1219         powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1220         writel(powerstate, base + NvRegPowerState2);
1221         msleep(25);
1222
1223         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1224         reg |= PHY_REALTEK_INIT9;
1225         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg))
1226                 return PHY_ERROR;
1227         if (mii_rw(dev, np->phyaddr,
1228                    PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10))
1229                 return PHY_ERROR;
1230         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1231         if (!(reg & PHY_REALTEK_INIT11)) {
1232                 reg |= PHY_REALTEK_INIT11;
1233                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg))
1234                         return PHY_ERROR;
1235         }
1236         if (mii_rw(dev, np->phyaddr,
1237                    PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1238                 return PHY_ERROR;
1239
1240         return 0;
1241 }
1242
1243 static int init_realtek_8201(struct net_device *dev, struct fe_priv *np)
1244 {
1245         u32 phy_reserved;
1246
1247         if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1248                 phy_reserved = mii_rw(dev, np->phyaddr,
1249                                       PHY_REALTEK_INIT_REG6, MII_READ);
1250                 phy_reserved |= PHY_REALTEK_INIT7;
1251                 if (mii_rw(dev, np->phyaddr,
1252                            PHY_REALTEK_INIT_REG6, phy_reserved))
1253                         return PHY_ERROR;
1254         }
1255
1256         return 0;
1257 }
1258
1259 static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np)
1260 {
1261         u32 phy_reserved;
1262
1263         if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1264                 if (mii_rw(dev, np->phyaddr,
1265                            PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3))
1266                         return PHY_ERROR;
1267                 phy_reserved = mii_rw(dev, np->phyaddr,
1268                                       PHY_REALTEK_INIT_REG2, MII_READ);
1269                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1270                 phy_reserved |= PHY_REALTEK_INIT3;
1271                 if (mii_rw(dev, np->phyaddr,
1272                            PHY_REALTEK_INIT_REG2, phy_reserved))
1273                         return PHY_ERROR;
1274                 if (mii_rw(dev, np->phyaddr,
1275                            PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1276                         return PHY_ERROR;
1277         }
1278
1279         return 0;
1280 }
1281
1282 static int init_cicada(struct net_device *dev, struct fe_priv *np,
1283                        u32 phyinterface)
1284 {
1285         u32 phy_reserved;
1286
1287         if (phyinterface & PHY_RGMII) {
1288                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1289                 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1290                 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1291                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))
1292                         return PHY_ERROR;
1293                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1294                 phy_reserved |= PHY_CICADA_INIT5;
1295                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))
1296                         return PHY_ERROR;
1297         }
1298         phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1299         phy_reserved |= PHY_CICADA_INIT6;
1300         if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))
1301                 return PHY_ERROR;
1302
1303         return 0;
1304 }
1305
1306 static int init_vitesse(struct net_device *dev, struct fe_priv *np)
1307 {
1308         u32 phy_reserved;
1309
1310         if (mii_rw(dev, np->phyaddr,
1311                    PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1))
1312                 return PHY_ERROR;
1313         if (mii_rw(dev, np->phyaddr,
1314                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2))
1315                 return PHY_ERROR;
1316         phy_reserved = mii_rw(dev, np->phyaddr,
1317                               PHY_VITESSE_INIT_REG4, MII_READ);
1318         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1319                 return PHY_ERROR;
1320         phy_reserved = mii_rw(dev, np->phyaddr,
1321                               PHY_VITESSE_INIT_REG3, MII_READ);
1322         phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1323         phy_reserved |= PHY_VITESSE_INIT3;
1324         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1325                 return PHY_ERROR;
1326         if (mii_rw(dev, np->phyaddr,
1327                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4))
1328                 return PHY_ERROR;
1329         if (mii_rw(dev, np->phyaddr,
1330                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5))
1331                 return PHY_ERROR;
1332         phy_reserved = mii_rw(dev, np->phyaddr,
1333                               PHY_VITESSE_INIT_REG4, MII_READ);
1334         phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1335         phy_reserved |= PHY_VITESSE_INIT3;
1336         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1337                 return PHY_ERROR;
1338         phy_reserved = mii_rw(dev, np->phyaddr,
1339                               PHY_VITESSE_INIT_REG3, MII_READ);
1340         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1341                 return PHY_ERROR;
1342         if (mii_rw(dev, np->phyaddr,
1343                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6))
1344                 return PHY_ERROR;
1345         if (mii_rw(dev, np->phyaddr,
1346                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7))
1347                 return PHY_ERROR;
1348         phy_reserved = mii_rw(dev, np->phyaddr,
1349                               PHY_VITESSE_INIT_REG4, MII_READ);
1350         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1351                 return PHY_ERROR;
1352         phy_reserved = mii_rw(dev, np->phyaddr,
1353                               PHY_VITESSE_INIT_REG3, MII_READ);
1354         phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1355         phy_reserved |= PHY_VITESSE_INIT8;
1356         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1357                 return PHY_ERROR;
1358         if (mii_rw(dev, np->phyaddr,
1359                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9))
1360                 return PHY_ERROR;
1361         if (mii_rw(dev, np->phyaddr,
1362                    PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10))
1363                 return PHY_ERROR;
1364
1365         return 0;
1366 }
1367
1368 static int phy_init(struct net_device *dev)
1369 {
1370         struct fe_priv *np = get_nvpriv(dev);
1371         u8 __iomem *base = get_hwbase(dev);
1372         u32 phyinterface;
1373         u32 mii_status, mii_control, mii_control_1000, reg;
1374
1375         /* phy errata for E3016 phy */
1376         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1377                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1378                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1379                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1380                         netdev_info(dev, "%s: phy write to errata reg failed\n",
1381                                     pci_name(np->pci_dev));
1382                         return PHY_ERROR;
1383                 }
1384         }
1385         if (np->phy_oui == PHY_OUI_REALTEK) {
1386                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1387                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1388                         if (init_realtek_8211b(dev, np)) {
1389                                 netdev_info(dev, "%s: phy init failed\n",
1390                                             pci_name(np->pci_dev));
1391                                 return PHY_ERROR;
1392                         }
1393                 } else if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1394                            np->phy_rev == PHY_REV_REALTEK_8211C) {
1395                         if (init_realtek_8211c(dev, np)) {
1396                                 netdev_info(dev, "%s: phy init failed\n",
1397                                             pci_name(np->pci_dev));
1398                                 return PHY_ERROR;
1399                         }
1400                 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1401                         if (init_realtek_8201(dev, np)) {
1402                                 netdev_info(dev, "%s: phy init failed\n",
1403                                             pci_name(np->pci_dev));
1404                                 return PHY_ERROR;
1405                         }
1406                 }
1407         }
1408
1409         /* set advertise register */
1410         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1411         reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1412                 ADVERTISE_100HALF | ADVERTISE_100FULL |
1413                 ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1414         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1415                 netdev_info(dev, "%s: phy write to advertise failed\n",
1416                             pci_name(np->pci_dev));
1417                 return PHY_ERROR;
1418         }
1419
1420         /* get phy interface type */
1421         phyinterface = readl(base + NvRegPhyInterface);
1422
1423         /* see if gigabit phy */
1424         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1425         if (mii_status & PHY_GIGABIT) {
1426                 np->gigabit = PHY_GIGABIT;
1427                 mii_control_1000 = mii_rw(dev, np->phyaddr,
1428                                           MII_CTRL1000, MII_READ);
1429                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1430                 if (phyinterface & PHY_RGMII)
1431                         mii_control_1000 |= ADVERTISE_1000FULL;
1432                 else
1433                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1434
1435                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1436                         netdev_info(dev, "%s: phy init failed\n",
1437                                     pci_name(np->pci_dev));
1438                         return PHY_ERROR;
1439                 }
1440         } else
1441                 np->gigabit = 0;
1442
1443         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1444         mii_control |= BMCR_ANENABLE;
1445
1446         if (np->phy_oui == PHY_OUI_REALTEK &&
1447             np->phy_model == PHY_MODEL_REALTEK_8211 &&
1448             np->phy_rev == PHY_REV_REALTEK_8211C) {
1449                 /* start autoneg since we already performed hw reset above */
1450                 mii_control |= BMCR_ANRESTART;
1451                 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1452                         netdev_info(dev, "%s: phy init failed\n",
1453                                     pci_name(np->pci_dev));
1454                         return PHY_ERROR;
1455                 }
1456         } else {
1457                 /* reset the phy
1458                  * (certain phys need bmcr to be setup with reset)
1459                  */
1460                 if (phy_reset(dev, mii_control)) {
1461                         netdev_info(dev, "%s: phy reset failed\n",
1462                                     pci_name(np->pci_dev));
1463                         return PHY_ERROR;
1464                 }
1465         }
1466
1467         /* phy vendor specific configuration */
1468         if ((np->phy_oui == PHY_OUI_CICADA)) {
1469                 if (init_cicada(dev, np, phyinterface)) {
1470                         netdev_info(dev, "%s: phy init failed\n",
1471                                     pci_name(np->pci_dev));
1472                         return PHY_ERROR;
1473                 }
1474         } else if (np->phy_oui == PHY_OUI_VITESSE) {
1475                 if (init_vitesse(dev, np)) {
1476                         netdev_info(dev, "%s: phy init failed\n",
1477                                     pci_name(np->pci_dev));
1478                         return PHY_ERROR;
1479                 }
1480         } else if (np->phy_oui == PHY_OUI_REALTEK) {
1481                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1482                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1483                         /* reset could have cleared these out, set them back */
1484                         if (init_realtek_8211b(dev, np)) {
1485                                 netdev_info(dev, "%s: phy init failed\n",
1486                                             pci_name(np->pci_dev));
1487                                 return PHY_ERROR;
1488                         }
1489                 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1490                         if (init_realtek_8201(dev, np) ||
1491                             init_realtek_8201_cross(dev, np)) {
1492                                 netdev_info(dev, "%s: phy init failed\n",
1493                                             pci_name(np->pci_dev));
1494                                 return PHY_ERROR;
1495                         }
1496                 }
1497         }
1498
1499         /* some phys clear out pause advertisment on reset, set it back */
1500         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1501
1502         /* restart auto negotiation, power down phy */
1503         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1504         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1505         if (phy_power_down)
1506                 mii_control |= BMCR_PDOWN;
1507         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
1508                 return PHY_ERROR;
1509
1510         return 0;
1511 }
1512
1513 static void nv_start_rx(struct net_device *dev)
1514 {
1515         struct fe_priv *np = netdev_priv(dev);
1516         u8 __iomem *base = get_hwbase(dev);
1517         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1518
1519         netdev_dbg(dev, "%s\n", __func__);
1520         /* Already running? Stop it. */
1521         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1522                 rx_ctrl &= ~NVREG_RCVCTL_START;
1523                 writel(rx_ctrl, base + NvRegReceiverControl);
1524                 pci_push(base);
1525         }
1526         writel(np->linkspeed, base + NvRegLinkSpeed);
1527         pci_push(base);
1528         rx_ctrl |= NVREG_RCVCTL_START;
1529         if (np->mac_in_use)
1530                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1531         writel(rx_ctrl, base + NvRegReceiverControl);
1532         netdev_dbg(dev, "%s: duplex %d, speed 0x%08x\n",
1533                    __func__, np->duplex, np->linkspeed);
1534         pci_push(base);
1535 }
1536
1537 static void nv_stop_rx(struct net_device *dev)
1538 {
1539         struct fe_priv *np = netdev_priv(dev);
1540         u8 __iomem *base = get_hwbase(dev);
1541         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1542
1543         netdev_dbg(dev, "%s\n", __func__);
1544         if (!np->mac_in_use)
1545                 rx_ctrl &= ~NVREG_RCVCTL_START;
1546         else
1547                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1548         writel(rx_ctrl, base + NvRegReceiverControl);
1549         if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1550                       NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX))
1551                 netdev_info(dev, "%s: ReceiverStatus remained busy\n",
1552                             __func__);
1553
1554         udelay(NV_RXSTOP_DELAY2);
1555         if (!np->mac_in_use)
1556                 writel(0, base + NvRegLinkSpeed);
1557 }
1558
1559 static void nv_start_tx(struct net_device *dev)
1560 {
1561         struct fe_priv *np = netdev_priv(dev);
1562         u8 __iomem *base = get_hwbase(dev);
1563         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1564
1565         netdev_dbg(dev, "%s\n", __func__);
1566         tx_ctrl |= NVREG_XMITCTL_START;
1567         if (np->mac_in_use)
1568                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1569         writel(tx_ctrl, base + NvRegTransmitterControl);
1570         pci_push(base);
1571 }
1572
1573 static void nv_stop_tx(struct net_device *dev)
1574 {
1575         struct fe_priv *np = netdev_priv(dev);
1576         u8 __iomem *base = get_hwbase(dev);
1577         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1578
1579         netdev_dbg(dev, "%s\n", __func__);
1580         if (!np->mac_in_use)
1581                 tx_ctrl &= ~NVREG_XMITCTL_START;
1582         else
1583                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1584         writel(tx_ctrl, base + NvRegTransmitterControl);
1585         if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1586                       NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX))
1587                 netdev_info(dev, "%s: TransmitterStatus remained busy\n",
1588                             __func__);
1589
1590         udelay(NV_TXSTOP_DELAY2);
1591         if (!np->mac_in_use)
1592                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1593                        base + NvRegTransmitPoll);
1594 }
1595
1596 static void nv_start_rxtx(struct net_device *dev)
1597 {
1598         nv_start_rx(dev);
1599         nv_start_tx(dev);
1600 }
1601
1602 static void nv_stop_rxtx(struct net_device *dev)
1603 {
1604         nv_stop_rx(dev);
1605         nv_stop_tx(dev);
1606 }
1607
1608 static void nv_txrx_reset(struct net_device *dev)
1609 {
1610         struct fe_priv *np = netdev_priv(dev);
1611         u8 __iomem *base = get_hwbase(dev);
1612
1613         netdev_dbg(dev, "%s\n", __func__);
1614         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1615         pci_push(base);
1616         udelay(NV_TXRX_RESET_DELAY);
1617         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1618         pci_push(base);
1619 }
1620
1621 static void nv_mac_reset(struct net_device *dev)
1622 {
1623         struct fe_priv *np = netdev_priv(dev);
1624         u8 __iomem *base = get_hwbase(dev);
1625         u32 temp1, temp2, temp3;
1626
1627         netdev_dbg(dev, "%s\n", __func__);
1628
1629         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1630         pci_push(base);
1631
1632         /* save registers since they will be cleared on reset */
1633         temp1 = readl(base + NvRegMacAddrA);
1634         temp2 = readl(base + NvRegMacAddrB);
1635         temp3 = readl(base + NvRegTransmitPoll);
1636
1637         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1638         pci_push(base);
1639         udelay(NV_MAC_RESET_DELAY);
1640         writel(0, base + NvRegMacReset);
1641         pci_push(base);
1642         udelay(NV_MAC_RESET_DELAY);
1643
1644         /* restore saved registers */
1645         writel(temp1, base + NvRegMacAddrA);
1646         writel(temp2, base + NvRegMacAddrB);
1647         writel(temp3, base + NvRegTransmitPoll);
1648
1649         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1650         pci_push(base);
1651 }
1652
1653 static void nv_get_hw_stats(struct net_device *dev)
1654 {
1655         struct fe_priv *np = netdev_priv(dev);
1656         u8 __iomem *base = get_hwbase(dev);
1657
1658         np->estats.tx_bytes += readl(base + NvRegTxCnt);
1659         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1660         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1661         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1662         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1663         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1664         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1665         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1666         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1667         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1668         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1669         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1670         np->estats.rx_runt += readl(base + NvRegRxRunt);
1671         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1672         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1673         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1674         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1675         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1676         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1677         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1678         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1679         np->estats.rx_packets =
1680                 np->estats.rx_unicast +
1681                 np->estats.rx_multicast +
1682                 np->estats.rx_broadcast;
1683         np->estats.rx_errors_total =
1684                 np->estats.rx_crc_errors +
1685                 np->estats.rx_over_errors +
1686                 np->estats.rx_frame_error +
1687                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1688                 np->estats.rx_late_collision +
1689                 np->estats.rx_runt +
1690                 np->estats.rx_frame_too_long;
1691         np->estats.tx_errors_total =
1692                 np->estats.tx_late_collision +
1693                 np->estats.tx_fifo_errors +
1694                 np->estats.tx_carrier_errors +
1695                 np->estats.tx_excess_deferral +
1696                 np->estats.tx_retry_error;
1697
1698         if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1699                 np->estats.tx_deferral += readl(base + NvRegTxDef);
1700                 np->estats.tx_packets += readl(base + NvRegTxFrame);
1701                 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1702                 np->estats.tx_pause += readl(base + NvRegTxPause);
1703                 np->estats.rx_pause += readl(base + NvRegRxPause);
1704                 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1705         }
1706
1707         if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1708                 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1709                 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1710                 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1711         }
1712 }
1713
1714 /*
1715  * nv_get_stats: dev->get_stats function
1716  * Get latest stats value from the nic.
1717  * Called with read_lock(&dev_base_lock) held for read -
1718  * only synchronized against unregister_netdevice.
1719  */
1720 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1721 {
1722         struct fe_priv *np = netdev_priv(dev);
1723
1724         /* If the nic supports hw counters then retrieve latest values */
1725         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
1726                 nv_get_hw_stats(dev);
1727
1728                 /* copy to net_device stats */
1729                 dev->stats.tx_bytes = np->estats.tx_bytes;
1730                 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1731                 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1732                 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1733                 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1734                 dev->stats.rx_errors = np->estats.rx_errors_total;
1735                 dev->stats.tx_errors = np->estats.tx_errors_total;
1736         }
1737
1738         return &dev->stats;
1739 }
1740
1741 /*
1742  * nv_alloc_rx: fill rx ring entries.
1743  * Return 1 if the allocations for the skbs failed and the
1744  * rx engine is without Available descriptors
1745  */
1746 static int nv_alloc_rx(struct net_device *dev)
1747 {
1748         struct fe_priv *np = netdev_priv(dev);
1749         struct ring_desc *less_rx;
1750
1751         less_rx = np->get_rx.orig;
1752         if (less_rx-- == np->first_rx.orig)
1753                 less_rx = np->last_rx.orig;
1754
1755         while (np->put_rx.orig != less_rx) {
1756                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1757                 if (skb) {
1758                         np->put_rx_ctx->skb = skb;
1759                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1760                                                              skb->data,
1761                                                              skb_tailroom(skb),
1762                                                              PCI_DMA_FROMDEVICE);
1763                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1764                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1765                         wmb();
1766                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1767                         if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1768                                 np->put_rx.orig = np->first_rx.orig;
1769                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1770                                 np->put_rx_ctx = np->first_rx_ctx;
1771                 } else
1772                         return 1;
1773         }
1774         return 0;
1775 }
1776
1777 static int nv_alloc_rx_optimized(struct net_device *dev)
1778 {
1779         struct fe_priv *np = netdev_priv(dev);
1780         struct ring_desc_ex *less_rx;
1781
1782         less_rx = np->get_rx.ex;
1783         if (less_rx-- == np->first_rx.ex)
1784                 less_rx = np->last_rx.ex;
1785
1786         while (np->put_rx.ex != less_rx) {
1787                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1788                 if (skb) {
1789                         np->put_rx_ctx->skb = skb;
1790                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1791                                                              skb->data,
1792                                                              skb_tailroom(skb),
1793                                                              PCI_DMA_FROMDEVICE);
1794                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1795                         np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1796                         np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1797                         wmb();
1798                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1799                         if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1800                                 np->put_rx.ex = np->first_rx.ex;
1801                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1802                                 np->put_rx_ctx = np->first_rx_ctx;
1803                 } else
1804                         return 1;
1805         }
1806         return 0;
1807 }
1808
1809 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1810 static void nv_do_rx_refill(unsigned long data)
1811 {
1812         struct net_device *dev = (struct net_device *) data;
1813         struct fe_priv *np = netdev_priv(dev);
1814
1815         /* Just reschedule NAPI rx processing */
1816         napi_schedule(&np->napi);
1817 }
1818
1819 static void nv_init_rx(struct net_device *dev)
1820 {
1821         struct fe_priv *np = netdev_priv(dev);
1822         int i;
1823
1824         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1825
1826         if (!nv_optimized(np))
1827                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1828         else
1829                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1830         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1831         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1832
1833         for (i = 0; i < np->rx_ring_size; i++) {
1834                 if (!nv_optimized(np)) {
1835                         np->rx_ring.orig[i].flaglen = 0;
1836                         np->rx_ring.orig[i].buf = 0;
1837                 } else {
1838                         np->rx_ring.ex[i].flaglen = 0;
1839                         np->rx_ring.ex[i].txvlan = 0;
1840                         np->rx_ring.ex[i].bufhigh = 0;
1841                         np->rx_ring.ex[i].buflow = 0;
1842                 }
1843                 np->rx_skb[i].skb = NULL;
1844                 np->rx_skb[i].dma = 0;
1845         }
1846 }
1847
1848 static void nv_init_tx(struct net_device *dev)
1849 {
1850         struct fe_priv *np = netdev_priv(dev);
1851         int i;
1852
1853         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1854
1855         if (!nv_optimized(np))
1856                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1857         else
1858                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1859         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1860         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1861         np->tx_pkts_in_progress = 0;
1862         np->tx_change_owner = NULL;
1863         np->tx_end_flip = NULL;
1864         np->tx_stop = 0;
1865
1866         for (i = 0; i < np->tx_ring_size; i++) {
1867                 if (!nv_optimized(np)) {
1868                         np->tx_ring.orig[i].flaglen = 0;
1869                         np->tx_ring.orig[i].buf = 0;
1870                 } else {
1871                         np->tx_ring.ex[i].flaglen = 0;
1872                         np->tx_ring.ex[i].txvlan = 0;
1873                         np->tx_ring.ex[i].bufhigh = 0;
1874                         np->tx_ring.ex[i].buflow = 0;
1875                 }
1876                 np->tx_skb[i].skb = NULL;
1877                 np->tx_skb[i].dma = 0;
1878                 np->tx_skb[i].dma_len = 0;
1879                 np->tx_skb[i].dma_single = 0;
1880                 np->tx_skb[i].first_tx_desc = NULL;
1881                 np->tx_skb[i].next_tx_ctx = NULL;
1882         }
1883 }
1884
1885 static int nv_init_ring(struct net_device *dev)
1886 {
1887         struct fe_priv *np = netdev_priv(dev);
1888
1889         nv_init_tx(dev);
1890         nv_init_rx(dev);
1891
1892         if (!nv_optimized(np))
1893                 return nv_alloc_rx(dev);
1894         else
1895                 return nv_alloc_rx_optimized(dev);
1896 }
1897
1898 static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1899 {
1900         if (tx_skb->dma) {
1901                 if (tx_skb->dma_single)
1902                         pci_unmap_single(np->pci_dev, tx_skb->dma,
1903                                          tx_skb->dma_len,
1904                                          PCI_DMA_TODEVICE);
1905                 else
1906                         pci_unmap_page(np->pci_dev, tx_skb->dma,
1907                                        tx_skb->dma_len,
1908                                        PCI_DMA_TODEVICE);
1909                 tx_skb->dma = 0;
1910         }
1911 }
1912
1913 static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1914 {
1915         nv_unmap_txskb(np, tx_skb);
1916         if (tx_skb->skb) {
1917                 dev_kfree_skb_any(tx_skb->skb);
1918                 tx_skb->skb = NULL;
1919                 return 1;
1920         }
1921         return 0;
1922 }
1923
1924 static void nv_drain_tx(struct net_device *dev)
1925 {
1926         struct fe_priv *np = netdev_priv(dev);
1927         unsigned int i;
1928
1929         for (i = 0; i < np->tx_ring_size; i++) {
1930                 if (!nv_optimized(np)) {
1931                         np->tx_ring.orig[i].flaglen = 0;
1932                         np->tx_ring.orig[i].buf = 0;
1933                 } else {
1934                         np->tx_ring.ex[i].flaglen = 0;
1935                         np->tx_ring.ex[i].txvlan = 0;
1936                         np->tx_ring.ex[i].bufhigh = 0;
1937                         np->tx_ring.ex[i].buflow = 0;
1938                 }
1939                 if (nv_release_txskb(np, &np->tx_skb[i]))
1940                         dev->stats.tx_dropped++;
1941                 np->tx_skb[i].dma = 0;
1942                 np->tx_skb[i].dma_len = 0;
1943                 np->tx_skb[i].dma_single = 0;
1944                 np->tx_skb[i].first_tx_desc = NULL;
1945                 np->tx_skb[i].next_tx_ctx = NULL;
1946         }
1947         np->tx_pkts_in_progress = 0;
1948         np->tx_change_owner = NULL;
1949         np->tx_end_flip = NULL;
1950 }
1951
1952 static void nv_drain_rx(struct net_device *dev)
1953 {
1954         struct fe_priv *np = netdev_priv(dev);
1955         int i;
1956
1957         for (i = 0; i < np->rx_ring_size; i++) {
1958                 if (!nv_optimized(np)) {
1959                         np->rx_ring.orig[i].flaglen = 0;
1960                         np->rx_ring.orig[i].buf = 0;
1961                 } else {
1962                         np->rx_ring.ex[i].flaglen = 0;
1963                         np->rx_ring.ex[i].txvlan = 0;
1964                         np->rx_ring.ex[i].bufhigh = 0;
1965                         np->rx_ring.ex[i].buflow = 0;
1966                 }
1967                 wmb();
1968                 if (np->rx_skb[i].skb) {
1969                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1970                                          (skb_end_pointer(np->rx_skb[i].skb) -
1971                                           np->rx_skb[i].skb->data),
1972                                          PCI_DMA_FROMDEVICE);
1973                         dev_kfree_skb(np->rx_skb[i].skb);
1974                         np->rx_skb[i].skb = NULL;
1975                 }
1976         }
1977 }
1978
1979 static void nv_drain_rxtx(struct net_device *dev)
1980 {
1981         nv_drain_tx(dev);
1982         nv_drain_rx(dev);
1983 }
1984
1985 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1986 {
1987         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1988 }
1989
1990 static void nv_legacybackoff_reseed(struct net_device *dev)
1991 {
1992         u8 __iomem *base = get_hwbase(dev);
1993         u32 reg;
1994         u32 low;
1995         int tx_status = 0;
1996
1997         reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
1998         get_random_bytes(&low, sizeof(low));
1999         reg |= low & NVREG_SLOTTIME_MASK;
2000
2001         /* Need to stop tx before change takes effect.
2002          * Caller has already gained np->lock.
2003          */
2004         tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
2005         if (tx_status)
2006                 nv_stop_tx(dev);
2007         nv_stop_rx(dev);
2008         writel(reg, base + NvRegSlotTime);
2009         if (tx_status)
2010                 nv_start_tx(dev);
2011         nv_start_rx(dev);
2012 }
2013
2014 /* Gear Backoff Seeds */
2015 #define BACKOFF_SEEDSET_ROWS    8
2016 #define BACKOFF_SEEDSET_LFSRS   15
2017
2018 /* Known Good seed sets */
2019 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2020         {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2021         {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2022         {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2023         {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2024         {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2025         {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2026         {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800,  84},
2027         {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} };
2028
2029 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2030         {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2031         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2032         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2033         {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2034         {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2035         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2036         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2037         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} };
2038
2039 static void nv_gear_backoff_reseed(struct net_device *dev)
2040 {
2041         u8 __iomem *base = get_hwbase(dev);
2042         u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2043         u32 temp, seedset, combinedSeed;
2044         int i;
2045
2046         /* Setup seed for free running LFSR */
2047         /* We are going to read the time stamp counter 3 times
2048            and swizzle bits around to increase randomness */
2049         get_random_bytes(&miniseed1, sizeof(miniseed1));
2050         miniseed1 &= 0x0fff;
2051         if (miniseed1 == 0)
2052                 miniseed1 = 0xabc;
2053
2054         get_random_bytes(&miniseed2, sizeof(miniseed2));
2055         miniseed2 &= 0x0fff;
2056         if (miniseed2 == 0)
2057                 miniseed2 = 0xabc;
2058         miniseed2_reversed =
2059                 ((miniseed2 & 0xF00) >> 8) |
2060                  (miniseed2 & 0x0F0) |
2061                  ((miniseed2 & 0x00F) << 8);
2062
2063         get_random_bytes(&miniseed3, sizeof(miniseed3));
2064         miniseed3 &= 0x0fff;
2065         if (miniseed3 == 0)
2066                 miniseed3 = 0xabc;
2067         miniseed3_reversed =
2068                 ((miniseed3 & 0xF00) >> 8) |
2069                  (miniseed3 & 0x0F0) |
2070                  ((miniseed3 & 0x00F) << 8);
2071
2072         combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2073                        (miniseed2 ^ miniseed3_reversed);
2074
2075         /* Seeds can not be zero */
2076         if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2077                 combinedSeed |= 0x08;
2078         if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2079                 combinedSeed |= 0x8000;
2080
2081         /* No need to disable tx here */
2082         temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2083         temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2084         temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2085         writel(temp, base + NvRegBackOffControl);
2086
2087         /* Setup seeds for all gear LFSRs. */
2088         get_random_bytes(&seedset, sizeof(seedset));
2089         seedset = seedset % BACKOFF_SEEDSET_ROWS;
2090         for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) {
2091                 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2092                 temp |= main_seedset[seedset][i-1] & 0x3ff;
2093                 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2094                 writel(temp, base + NvRegBackOffControl);
2095         }
2096 }
2097
2098 /*
2099  * nv_start_xmit: dev->hard_start_xmit function
2100  * Called with netif_tx_lock held.
2101  */
2102 static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2103 {
2104         struct fe_priv *np = netdev_priv(dev);
2105         u32 tx_flags = 0;
2106         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2107         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2108         unsigned int i;
2109         u32 offset = 0;
2110         u32 bcnt;
2111         u32 size = skb_headlen(skb);
2112         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2113         u32 empty_slots;
2114         struct ring_desc *put_tx;
2115         struct ring_desc *start_tx;
2116         struct ring_desc *prev_tx;
2117         struct nv_skb_map *prev_tx_ctx;
2118         unsigned long flags;
2119
2120         /* add fragments to entries count */
2121         for (i = 0; i < fragments; i++) {
2122                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2123                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2124         }
2125
2126         spin_lock_irqsave(&np->lock, flags);
2127         empty_slots = nv_get_empty_tx_slots(np);
2128         if (unlikely(empty_slots <= entries)) {
2129                 netif_stop_queue(dev);
2130                 np->tx_stop = 1;
2131                 spin_unlock_irqrestore(&np->lock, flags);
2132                 return NETDEV_TX_BUSY;
2133         }
2134         spin_unlock_irqrestore(&np->lock, flags);
2135
2136         start_tx = put_tx = np->put_tx.orig;
2137
2138         /* setup the header buffer */
2139         do {
2140                 prev_tx = put_tx;
2141                 prev_tx_ctx = np->put_tx_ctx;
2142                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2143                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2144                                                 PCI_DMA_TODEVICE);
2145                 np->put_tx_ctx->dma_len = bcnt;
2146                 np->put_tx_ctx->dma_single = 1;
2147                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2148                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2149
2150                 tx_flags = np->tx_flags;
2151                 offset += bcnt;
2152                 size -= bcnt;
2153                 if (unlikely(put_tx++ == np->last_tx.orig))
2154                         put_tx = np->first_tx.orig;
2155                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2156                         np->put_tx_ctx = np->first_tx_ctx;
2157         } while (size);
2158
2159         /* setup the fragments */
2160         for (i = 0; i < fragments; i++) {
2161                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2162                 u32 size = frag->size;
2163                 offset = 0;
2164
2165                 do {
2166                         prev_tx = put_tx;
2167                         prev_tx_ctx = np->put_tx_ctx;
2168                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2169                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2170                                                            PCI_DMA_TODEVICE);
2171                         np->put_tx_ctx->dma_len = bcnt;
2172                         np->put_tx_ctx->dma_single = 0;
2173                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2174                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2175
2176                         offset += bcnt;
2177                         size -= bcnt;
2178                         if (unlikely(put_tx++ == np->last_tx.orig))
2179                                 put_tx = np->first_tx.orig;
2180                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2181                                 np->put_tx_ctx = np->first_tx_ctx;
2182                 } while (size);
2183         }
2184
2185         /* set last fragment flag  */
2186         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2187
2188         /* save skb in this slot's context area */
2189         prev_tx_ctx->skb = skb;
2190
2191         if (skb_is_gso(skb))
2192                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2193         else
2194                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2195                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2196
2197         spin_lock_irqsave(&np->lock, flags);
2198
2199         /* set tx flags */
2200         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2201         np->put_tx.orig = put_tx;
2202
2203         spin_unlock_irqrestore(&np->lock, flags);
2204
2205         netdev_dbg(dev, "%s: entries %d queued for transmission. tx_flags_extra: %x\n",
2206                    __func__, entries, tx_flags_extra);
2207 #ifdef DEBUG
2208         print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 16, 1,
2209                        skb->data, 64, true);
2210 #endif
2211
2212         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2213         return NETDEV_TX_OK;
2214 }
2215
2216 static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2217                                            struct net_device *dev)
2218 {
2219         struct fe_priv *np = netdev_priv(dev);
2220         u32 tx_flags = 0;
2221         u32 tx_flags_extra;
2222         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2223         unsigned int i;
2224         u32 offset = 0;
2225         u32 bcnt;
2226         u32 size = skb_headlen(skb);
2227         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2228         u32 empty_slots;
2229         struct ring_desc_ex *put_tx;
2230         struct ring_desc_ex *start_tx;
2231         struct ring_desc_ex *prev_tx;
2232         struct nv_skb_map *prev_tx_ctx;
2233         struct nv_skb_map *start_tx_ctx;
2234         unsigned long flags;
2235
2236         /* add fragments to entries count */
2237         for (i = 0; i < fragments; i++) {
2238                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2239                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2240         }
2241
2242         spin_lock_irqsave(&np->lock, flags);
2243         empty_slots = nv_get_empty_tx_slots(np);
2244         if (unlikely(empty_slots <= entries)) {
2245                 netif_stop_queue(dev);
2246                 np->tx_stop = 1;
2247                 spin_unlock_irqrestore(&np->lock, flags);
2248                 return NETDEV_TX_BUSY;
2249         }
2250         spin_unlock_irqrestore(&np->lock, flags);
2251
2252         start_tx = put_tx = np->put_tx.ex;
2253         start_tx_ctx = np->put_tx_ctx;
2254
2255         /* setup the header buffer */
2256         do {
2257                 prev_tx = put_tx;
2258                 prev_tx_ctx = np->put_tx_ctx;
2259                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2260                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2261                                                 PCI_DMA_TODEVICE);
2262                 np->put_tx_ctx->dma_len = bcnt;
2263                 np->put_tx_ctx->dma_single = 1;
2264                 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2265                 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2266                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2267
2268                 tx_flags = NV_TX2_VALID;
2269                 offset += bcnt;
2270                 size -= bcnt;
2271                 if (unlikely(put_tx++ == np->last_tx.ex))
2272                         put_tx = np->first_tx.ex;
2273                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2274                         np->put_tx_ctx = np->first_tx_ctx;
2275         } while (size);
2276
2277         /* setup the fragments */
2278         for (i = 0; i < fragments; i++) {
2279                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2280                 u32 size = frag->size;
2281                 offset = 0;
2282
2283                 do {
2284                         prev_tx = put_tx;
2285                         prev_tx_ctx = np->put_tx_ctx;
2286                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2287                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2288                                                            PCI_DMA_TODEVICE);
2289                         np->put_tx_ctx->dma_len = bcnt;
2290                         np->put_tx_ctx->dma_single = 0;
2291                         put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2292                         put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2293                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2294
2295                         offset += bcnt;
2296                         size -= bcnt;
2297                         if (unlikely(put_tx++ == np->last_tx.ex))
2298                                 put_tx = np->first_tx.ex;
2299                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2300                                 np->put_tx_ctx = np->first_tx_ctx;
2301                 } while (size);
2302         }
2303
2304         /* set last fragment flag  */
2305         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2306
2307         /* save skb in this slot's context area */
2308         prev_tx_ctx->skb = skb;
2309
2310         if (skb_is_gso(skb))
2311                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2312         else
2313                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2314                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2315
2316         /* vlan tag */
2317         if (vlan_tx_tag_present(skb))
2318                 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT |
2319                                         vlan_tx_tag_get(skb));
2320         else
2321                 start_tx->txvlan = 0;
2322
2323         spin_lock_irqsave(&np->lock, flags);
2324
2325         if (np->tx_limit) {
2326                 /* Limit the number of outstanding tx. Setup all fragments, but
2327                  * do not set the VALID bit on the first descriptor. Save a pointer
2328                  * to that descriptor and also for next skb_map element.
2329                  */
2330
2331                 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2332                         if (!np->tx_change_owner)
2333                                 np->tx_change_owner = start_tx_ctx;
2334
2335                         /* remove VALID bit */
2336                         tx_flags &= ~NV_TX2_VALID;
2337                         start_tx_ctx->first_tx_desc = start_tx;
2338                         start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2339                         np->tx_end_flip = np->put_tx_ctx;
2340                 } else {
2341                         np->tx_pkts_in_progress++;
2342                 }
2343         }
2344
2345         /* set tx flags */
2346         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2347         np->put_tx.ex = put_tx;
2348
2349         spin_unlock_irqrestore(&np->lock, flags);
2350
2351         netdev_dbg(dev, "%s: entries %d queued for transmission. tx_flags_extra: %x\n",
2352                    __func__, entries, tx_flags_extra);
2353 #ifdef DEBUG
2354         print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 16, 1,
2355                        skb->data, 64, true);
2356 #endif
2357
2358         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2359         return NETDEV_TX_OK;
2360 }
2361
2362 static inline void nv_tx_flip_ownership(struct net_device *dev)
2363 {
2364         struct fe_priv *np = netdev_priv(dev);
2365
2366         np->tx_pkts_in_progress--;
2367         if (np->tx_change_owner) {
2368                 np->tx_change_owner->first_tx_desc->flaglen |=
2369                         cpu_to_le32(NV_TX2_VALID);
2370                 np->tx_pkts_in_progress++;
2371
2372                 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2373                 if (np->tx_change_owner == np->tx_end_flip)
2374                         np->tx_change_owner = NULL;
2375
2376                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2377         }
2378 }
2379
2380 /*
2381  * nv_tx_done: check for completed packets, release the skbs.
2382  *
2383  * Caller must own np->lock.
2384  */
2385 static int nv_tx_done(struct net_device *dev, int limit)
2386 {
2387         struct fe_priv *np = netdev_priv(dev);
2388         u32 flags;
2389         int tx_work = 0;
2390         struct ring_desc *orig_get_tx = np->get_tx.orig;
2391
2392         while ((np->get_tx.orig != np->put_tx.orig) &&
2393                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2394                (tx_work < limit)) {
2395
2396                 netdev_dbg(dev, "%s: flags 0x%x\n", __func__, flags);
2397
2398                 nv_unmap_txskb(np, np->get_tx_ctx);
2399
2400                 if (np->desc_ver == DESC_VER_1) {
2401                         if (flags & NV_TX_LASTPACKET) {
2402                                 if (flags & NV_TX_ERROR) {
2403                                         if (flags & NV_TX_UNDERFLOW)
2404                                                 dev->stats.tx_fifo_errors++;
2405                                         if (flags & NV_TX_CARRIERLOST)
2406                                                 dev->stats.tx_carrier_errors++;
2407                                         if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2408                                                 nv_legacybackoff_reseed(dev);
2409                                         dev->stats.tx_errors++;
2410                                 } else {
2411                                         dev->stats.tx_packets++;
2412                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2413                                 }
2414                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2415                                 np->get_tx_ctx->skb = NULL;
2416                                 tx_work++;
2417                         }
2418                 } else {
2419                         if (flags & NV_TX2_LASTPACKET) {
2420                                 if (flags & NV_TX2_ERROR) {
2421                                         if (flags & NV_TX2_UNDERFLOW)
2422                                                 dev->stats.tx_fifo_errors++;
2423                                         if (flags & NV_TX2_CARRIERLOST)
2424                                                 dev->stats.tx_carrier_errors++;
2425                                         if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2426                                                 nv_legacybackoff_reseed(dev);
2427                                         dev->stats.tx_errors++;
2428                                 } else {
2429                                         dev->stats.tx_packets++;
2430                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2431                                 }
2432                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2433                                 np->get_tx_ctx->skb = NULL;
2434                                 tx_work++;
2435                         }
2436                 }
2437                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2438                         np->get_tx.orig = np->first_tx.orig;
2439                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2440                         np->get_tx_ctx = np->first_tx_ctx;
2441         }
2442         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2443                 np->tx_stop = 0;
2444                 netif_wake_queue(dev);
2445         }
2446         return tx_work;
2447 }
2448
2449 static int nv_tx_done_optimized(struct net_device *dev, int limit)
2450 {
2451         struct fe_priv *np = netdev_priv(dev);
2452         u32 flags;
2453         int tx_work = 0;
2454         struct ring_desc_ex *orig_get_tx = np->get_tx.ex;
2455
2456         while ((np->get_tx.ex != np->put_tx.ex) &&
2457                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&
2458                (tx_work < limit)) {
2459
2460                 netdev_dbg(dev, "%s: flags 0x%x\n", __func__, flags);
2461
2462                 nv_unmap_txskb(np, np->get_tx_ctx);
2463
2464                 if (flags & NV_TX2_LASTPACKET) {
2465                         if (!(flags & NV_TX2_ERROR))
2466                                 dev->stats.tx_packets++;
2467                         else {
2468                                 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2469                                         if (np->driver_data & DEV_HAS_GEAR_MODE)
2470                                                 nv_gear_backoff_reseed(dev);
2471                                         else
2472                                                 nv_legacybackoff_reseed(dev);
2473                                 }
2474                         }
2475
2476                         dev_kfree_skb_any(np->get_tx_ctx->skb);
2477                         np->get_tx_ctx->skb = NULL;
2478                         tx_work++;
2479
2480                         if (np->tx_limit)
2481                                 nv_tx_flip_ownership(dev);
2482                 }
2483                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2484                         np->get_tx.ex = np->first_tx.ex;
2485                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2486                         np->get_tx_ctx = np->first_tx_ctx;
2487         }
2488         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2489                 np->tx_stop = 0;
2490                 netif_wake_queue(dev);
2491         }
2492         return tx_work;
2493 }
2494
2495 /*
2496  * nv_tx_timeout: dev->tx_timeout function
2497  * Called with netif_tx_lock held.
2498  */
2499 static void nv_tx_timeout(struct net_device *dev)
2500 {
2501         struct fe_priv *np = netdev_priv(dev);
2502         u8 __iomem *base = get_hwbase(dev);
2503         u32 status;
2504         union ring_type put_tx;
2505         int saved_tx_limit;
2506         int i;
2507
2508         if (np->msi_flags & NV_MSI_X_ENABLED)
2509                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2510         else
2511                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2512
2513         netdev_info(dev, "Got tx_timeout. irq: %08x\n", status);
2514
2515         netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr);
2516         netdev_info(dev, "Dumping tx registers\n");
2517         for (i = 0; i <= np->register_size; i += 32) {
2518                 netdev_info(dev,
2519                             "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2520                             i,
2521                             readl(base + i + 0), readl(base + i + 4),
2522                             readl(base + i + 8), readl(base + i + 12),
2523                             readl(base + i + 16), readl(base + i + 20),
2524                             readl(base + i + 24), readl(base + i + 28));
2525         }
2526         netdev_info(dev, "Dumping tx ring\n");
2527         for (i = 0; i < np->tx_ring_size; i += 4) {
2528                 if (!nv_optimized(np)) {
2529                         netdev_info(dev,
2530                                     "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2531                                     i,
2532                                     le32_to_cpu(np->tx_ring.orig[i].buf),
2533                                     le32_to_cpu(np->tx_ring.orig[i].flaglen),
2534                                     le32_to_cpu(np->tx_ring.orig[i+1].buf),
2535                                     le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2536                                     le32_to_cpu(np->tx_ring.orig[i+2].buf),
2537                                     le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2538                                     le32_to_cpu(np->tx_ring.orig[i+3].buf),
2539                                     le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2540                 } else {
2541                         netdev_info(dev,
2542                                     "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2543                                     i,
2544                                     le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2545                                     le32_to_cpu(np->tx_ring.ex[i].buflow),
2546                                     le32_to_cpu(np->tx_ring.ex[i].flaglen),
2547                                     le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2548                                     le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2549                                     le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2550                                     le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2551                                     le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2552                                     le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2553                                     le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2554                                     le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2555                                     le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2556                 }
2557         }
2558
2559         spin_lock_irq(&np->lock);
2560
2561         /* 1) stop tx engine */
2562         nv_stop_tx(dev);
2563
2564         /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2565         saved_tx_limit = np->tx_limit;
2566         np->tx_limit = 0; /* prevent giving HW any limited pkts */
2567         np->tx_stop = 0;  /* prevent waking tx queue */
2568         if (!nv_optimized(np))
2569                 nv_tx_done(dev, np->tx_ring_size);
2570         else
2571                 nv_tx_done_optimized(dev, np->tx_ring_size);
2572
2573         /* save current HW postion */
2574         if (np->tx_change_owner)
2575                 put_tx.ex = np->tx_change_owner->first_tx_desc;
2576         else
2577                 put_tx = np->put_tx;
2578
2579         /* 3) clear all tx state */
2580         nv_drain_tx(dev);
2581         nv_init_tx(dev);
2582
2583         /* 4) restore state to current HW position */
2584         np->get_tx = np->put_tx = put_tx;
2585         np->tx_limit = saved_tx_limit;
2586
2587         /* 5) restart tx engine */
2588         nv_start_tx(dev);
2589         netif_wake_queue(dev);
2590         spin_unlock_irq(&np->lock);
2591 }
2592
2593 /*
2594  * Called when the nic notices a mismatch between the actual data len on the
2595  * wire and the len indicated in the 802 header
2596  */
2597 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2598 {
2599         int hdrlen;     /* length of the 802 header */
2600         int protolen;   /* length as stored in the proto field */
2601
2602         /* 1) calculate len according to header */
2603         if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2604                 protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto);
2605                 hdrlen = VLAN_HLEN;
2606         } else {
2607                 protolen = ntohs(((struct ethhdr *)packet)->h_proto);
2608                 hdrlen = ETH_HLEN;
2609         }
2610         netdev_dbg(dev, "%s: datalen %d, protolen %d, hdrlen %d\n",
2611                    __func__, datalen, protolen, hdrlen);
2612         if (protolen > ETH_DATA_LEN)
2613                 return datalen; /* Value in proto field not a len, no checks possible */
2614
2615         protolen += hdrlen;
2616         /* consistency checks: */
2617         if (datalen > ETH_ZLEN) {
2618                 if (datalen >= protolen) {
2619                         /* more data on wire than in 802 header, trim of
2620                          * additional data.
2621                          */
2622                         netdev_dbg(dev, "%s: accepting %d bytes\n",
2623                                    __func__, protolen);
2624                         return protolen;
2625                 } else {
2626                         /* less data on wire than mentioned in header.
2627                          * Discard the packet.
2628                          */
2629                         netdev_dbg(dev, "%s: discarding long packet\n",
2630                                    __func__);
2631                         return -1;
2632                 }
2633         } else {
2634                 /* short packet. Accept only if 802 values are also short */
2635                 if (protolen > ETH_ZLEN) {
2636                         netdev_dbg(dev, "%s: discarding short packet\n",
2637                                    __func__);
2638                         return -1;
2639                 }
2640                 netdev_dbg(dev, "%s: accepting %d bytes\n", __func__, datalen);
2641                 return datalen;
2642         }
2643 }
2644
2645 static int nv_rx_process(struct net_device *dev, int limit)
2646 {
2647         struct fe_priv *np = netdev_priv(dev);
2648         u32 flags;
2649         int rx_work = 0;
2650         struct sk_buff *skb;
2651         int len;
2652
2653         while ((np->get_rx.orig != np->put_rx.orig) &&
2654               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2655                 (rx_work < limit)) {
2656
2657                 netdev_dbg(dev, "%s: flags 0x%x\n", __func__, flags);
2658
2659                 /*
2660                  * the packet is for us - immediately tear down the pci mapping.
2661                  * TODO: check if a prefetch of the first cacheline improves
2662                  * the performance.
2663                  */
2664                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2665                                 np->get_rx_ctx->dma_len,
2666                                 PCI_DMA_FROMDEVICE);
2667                 skb = np->get_rx_ctx->skb;
2668                 np->get_rx_ctx->skb = NULL;
2669
2670                         netdev_dbg(dev, "Dumping packet (flags 0x%x)\n", flags);
2671 #ifdef DEBUG
2672                         print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET,
2673                                        16, 1, skb->data, 64, true);
2674 #endif
2675                 /* look at what we actually got: */
2676                 if (np->desc_ver == DESC_VER_1) {
2677                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2678                                 len = flags & LEN_MASK_V1;
2679                                 if (unlikely(flags & NV_RX_ERROR)) {
2680                                         if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2681                                                 len = nv_getlen(dev, skb->data, len);
2682                                                 if (len < 0) {
2683                                                         dev->stats.rx_errors++;
2684                                                         dev_kfree_skb(skb);
2685                                                         goto next_pkt;
2686                                                 }
2687                                         }
2688                                         /* framing errors are soft errors */
2689                                         else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2690                                                 if (flags & NV_RX_SUBSTRACT1)
2691                                                         len--;
2692                                         }
2693                                         /* the rest are hard errors */
2694                                         else {
2695                                                 if (flags & NV_RX_MISSEDFRAME)
2696                                                         dev->stats.rx_missed_errors++;
2697                                                 if (flags & NV_RX_CRCERR)
2698                                                         dev->stats.rx_crc_errors++;
2699                                                 if (flags & NV_RX_OVERFLOW)
2700                                                         dev->stats.rx_over_errors++;
2701                                                 dev->stats.rx_errors++;
2702                                                 dev_kfree_skb(skb);
2703                                                 goto next_pkt;
2704                                         }
2705                                 }
2706                         } else {
2707                                 dev_kfree_skb(skb);
2708                                 goto next_pkt;
2709                         }
2710                 } else {
2711                         if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2712                                 len = flags & LEN_MASK_V2;
2713                                 if (unlikely(flags & NV_RX2_ERROR)) {
2714                                         if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2715                                                 len = nv_getlen(dev, skb->data, len);
2716                                                 if (len < 0) {
2717                                                         dev->stats.rx_errors++;
2718                                                         dev_kfree_skb(skb);
2719                                                         goto next_pkt;
2720                                                 }
2721                                         }
2722                                         /* framing errors are soft errors */
2723                                         else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2724                                                 if (flags & NV_RX2_SUBSTRACT1)
2725                                                         len--;
2726                                         }
2727                                         /* the rest are hard errors */
2728                                         else {
2729                                                 if (flags & NV_RX2_CRCERR)
2730                                                         dev->stats.rx_crc_errors++;
2731                                                 if (flags & NV_RX2_OVERFLOW)
2732                                                         dev->stats.rx_over_errors++;
2733                                                 dev->stats.rx_errors++;
2734                                                 dev_kfree_skb(skb);
2735                                                 goto next_pkt;
2736                                         }
2737                                 }
2738                                 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2739                                     ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2740                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2741                         } else {
2742                                 dev_kfree_skb(skb);
2743                                 goto next_pkt;
2744                         }
2745                 }
2746                 /* got a valid packet - forward it to the network core */
2747                 skb_put(skb, len);
2748                 skb->protocol = eth_type_trans(skb, dev);
2749                 netdev_dbg(dev, "%s: %d bytes, proto %d accepted\n",
2750                            __func__, len, skb->protocol);
2751                 napi_gro_receive(&np->napi, skb);
2752                 dev->stats.rx_packets++;
2753                 dev->stats.rx_bytes += len;
2754 next_pkt:
2755                 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2756                         np->get_rx.orig = np->first_rx.orig;
2757                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2758                         np->get_rx_ctx = np->first_rx_ctx;
2759
2760                 rx_work++;
2761         }
2762
2763         return rx_work;
2764 }
2765
2766 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2767 {
2768         struct fe_priv *np = netdev_priv(dev);
2769         u32 flags;
2770         u32 vlanflags = 0;
2771         int rx_work = 0;
2772         struct sk_buff *skb;
2773         int len;
2774
2775         while ((np->get_rx.ex != np->put_rx.ex) &&
2776               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2777               (rx_work < limit)) {
2778
2779                 netdev_dbg(dev, "%s: flags 0x%x\n", __func__, flags);
2780
2781                 /*
2782                  * the packet is for us - immediately tear down the pci mapping.
2783                  * TODO: check if a prefetch of the first cacheline improves
2784                  * the performance.
2785                  */
2786                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2787                                 np->get_rx_ctx->dma_len,
2788                                 PCI_DMA_FROMDEVICE);
2789                 skb = np->get_rx_ctx->skb;
2790                 np->get_rx_ctx->skb = NULL;
2791
2792                 netdev_dbg(dev, "Dumping packet (flags 0x%x)\n", flags);
2793 #ifdef DEBUG
2794                 print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 16, 1,
2795                                skb->data, 64, true);
2796 #endif
2797                 /* look at what we actually got: */
2798                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2799                         len = flags & LEN_MASK_V2;
2800                         if (unlikely(flags & NV_RX2_ERROR)) {
2801                                 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2802                                         len = nv_getlen(dev, skb->data, len);
2803                                         if (len < 0) {
2804                                                 dev_kfree_skb(skb);
2805                                                 goto next_pkt;
2806                                         }
2807                                 }
2808                                 /* framing errors are soft errors */
2809                                 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2810                                         if (flags & NV_RX2_SUBSTRACT1)
2811                                                 len--;
2812                                 }
2813                                 /* the rest are hard errors */
2814                                 else {
2815                                         dev_kfree_skb(skb);
2816                                         goto next_pkt;
2817                                 }
2818                         }
2819
2820                         if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2821                             ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2822                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2823
2824                         /* got a valid packet - forward it to the network core */
2825                         skb_put(skb, len);
2826                         skb->protocol = eth_type_trans(skb, dev);
2827                         prefetch(skb->data);
2828
2829                         netdev_dbg(dev, "%s: %d bytes, proto %d accepted\n",
2830                                    __func__, len, skb->protocol);
2831
2832                         if (likely(!np->vlangrp)) {
2833                                 napi_gro_receive(&np->napi, skb);
2834                         } else {
2835                                 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2836                                 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2837                                         vlan_gro_receive(&np->napi, np->vlangrp,
2838                                                          vlanflags & NV_RX3_VLAN_TAG_MASK, skb);
2839                                 } else {
2840                                         napi_gro_receive(&np->napi, skb);
2841                                 }
2842                         }
2843
2844                         dev->stats.rx_packets++;
2845                         dev->stats.rx_bytes += len;
2846                 } else {
2847                         dev_kfree_skb(skb);
2848                 }
2849 next_pkt:
2850                 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2851                         np->get_rx.ex = np->first_rx.ex;
2852                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2853                         np->get_rx_ctx = np->first_rx_ctx;
2854
2855                 rx_work++;
2856         }
2857
2858         return rx_work;
2859 }
2860
2861 static void set_bufsize(struct net_device *dev)
2862 {
2863         struct fe_priv *np = netdev_priv(dev);
2864
2865         if (dev->mtu <= ETH_DATA_LEN)
2866                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2867         else
2868                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2869 }
2870
2871 /*
2872  * nv_change_mtu: dev->change_mtu function
2873  * Called with dev_base_lock held for read.
2874  */
2875 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2876 {
2877         struct fe_priv *np = netdev_priv(dev);
2878         int old_mtu;
2879
2880         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2881                 return -EINVAL;
2882
2883         old_mtu = dev->mtu;
2884         dev->mtu = new_mtu;
2885
2886         /* return early if the buffer sizes will not change */
2887         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2888                 return 0;
2889         if (old_mtu == new_mtu)
2890                 return 0;
2891
2892         /* synchronized against open : rtnl_lock() held by caller */
2893         if (netif_running(dev)) {
2894                 u8 __iomem *base = get_hwbase(dev);
2895                 /*
2896                  * It seems that the nic preloads valid ring entries into an
2897                  * internal buffer. The procedure for flushing everything is
2898                  * guessed, there is probably a simpler approach.
2899                  * Changing the MTU is a rare event, it shouldn't matter.
2900                  */
2901                 nv_disable_irq(dev);
2902                 nv_napi_disable(dev);
2903                 netif_tx_lock_bh(dev);
2904                 netif_addr_lock(dev);
2905                 spin_lock(&np->lock);
2906                 /* stop engines */
2907                 nv_stop_rxtx(dev);
2908                 nv_txrx_reset(dev);
2909                 /* drain rx queue */
2910                 nv_drain_rxtx(dev);
2911                 /* reinit driver view of the rx queue */
2912                 set_bufsize(dev);
2913                 if (nv_init_ring(dev)) {
2914                         if (!np->in_shutdown)
2915                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2916                 }
2917                 /* reinit nic view of the rx queue */
2918                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2919                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2920                 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2921                         base + NvRegRingSizes);
2922                 pci_push(base);
2923                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2924                 pci_push(base);
2925
2926                 /* restart rx engine */
2927                 nv_start_rxtx(dev);
2928                 spin_unlock(&np->lock);
2929                 netif_addr_unlock(dev);
2930                 netif_tx_unlock_bh(dev);
2931                 nv_napi_enable(dev);
2932                 nv_enable_irq(dev);
2933         }
2934         return 0;
2935 }
2936
2937 static void nv_copy_mac_to_hw(struct net_device *dev)
2938 {
2939         u8 __iomem *base = get_hwbase(dev);
2940         u32 mac[2];
2941
2942         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2943                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2944         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2945
2946         writel(mac[0], base + NvRegMacAddrA);
2947         writel(mac[1], base + NvRegMacAddrB);
2948 }
2949
2950 /*
2951  * nv_set_mac_address: dev->set_mac_address function
2952  * Called with rtnl_lock() held.
2953  */
2954 static int nv_set_mac_address(struct net_device *dev, void *addr)
2955 {
2956         struct fe_priv *np = netdev_priv(dev);
2957         struct sockaddr *macaddr = (struct sockaddr *)addr;
2958
2959         if (!is_valid_ether_addr(macaddr->sa_data))
2960                 return -EADDRNOTAVAIL;
2961
2962         /* synchronized against open : rtnl_lock() held by caller */
2963         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2964
2965         if (netif_running(dev)) {
2966                 netif_tx_lock_bh(dev);
2967                 netif_addr_lock(dev);
2968                 spin_lock_irq(&np->lock);
2969
2970                 /* stop rx engine */
2971                 nv_stop_rx(dev);
2972
2973                 /* set mac address */
2974                 nv_copy_mac_to_hw(dev);
2975
2976                 /* restart rx engine */
2977                 nv_start_rx(dev);
2978                 spin_unlock_irq(&np->lock);
2979                 netif_addr_unlock(dev);
2980                 netif_tx_unlock_bh(dev);
2981         } else {
2982                 nv_copy_mac_to_hw(dev);
2983         }
2984         return 0;
2985 }
2986
2987 /*
2988  * nv_set_multicast: dev->set_multicast function
2989  * Called with netif_tx_lock held.
2990  */
2991 static void nv_set_multicast(struct net_device *dev)
2992 {
2993         struct fe_priv *np = netdev_priv(dev);
2994         u8 __iomem *base = get_hwbase(dev);
2995         u32 addr[2];
2996         u32 mask[2];
2997         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2998
2999         memset(addr, 0, sizeof(addr));
3000         memset(mask, 0, sizeof(mask));
3001
3002         if (dev->flags & IFF_PROMISC) {
3003                 pff |= NVREG_PFF_PROMISC;
3004         } else {
3005                 pff |= NVREG_PFF_MYADDR;
3006
3007                 if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
3008                         u32 alwaysOff[2];
3009                         u32 alwaysOn[2];
3010
3011                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3012                         if (dev->flags & IFF_ALLMULTI) {
3013                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3014                         } else {
3015                                 struct netdev_hw_addr *ha;
3016
3017                                 netdev_for_each_mc_addr(ha, dev) {
3018                                         unsigned char *addr = ha->addr;
3019                                         u32 a, b;
3020
3021                                         a = le32_to_cpu(*(__le32 *) addr);
3022                                         b = le16_to_cpu(*(__le16 *) (&addr[4]));
3023                                         alwaysOn[0] &= a;
3024                                         alwaysOff[0] &= ~a;
3025                                         alwaysOn[1] &= b;
3026                                         alwaysOff[1] &= ~b;
3027                                 }
3028                         }
3029                         addr[0] = alwaysOn[0];
3030                         addr[1] = alwaysOn[1];
3031                         mask[0] = alwaysOn[0] | alwaysOff[0];
3032                         mask[1] = alwaysOn[1] | alwaysOff[1];
3033                 } else {
3034                         mask[0] = NVREG_MCASTMASKA_NONE;
3035                         mask[1] = NVREG_MCASTMASKB_NONE;
3036                 }
3037         }
3038         addr[0] |= NVREG_MCASTADDRA_FORCE;
3039         pff |= NVREG_PFF_ALWAYS;
3040         spin_lock_irq(&np->lock);
3041         nv_stop_rx(dev);
3042         writel(addr[0], base + NvRegMulticastAddrA);
3043         writel(addr[1], base + NvRegMulticastAddrB);
3044         writel(mask[0], base + NvRegMulticastMaskA);
3045         writel(mask[1], base + NvRegMulticastMaskB);
3046         writel(pff, base + NvRegPacketFilterFlags);
3047         netdev_dbg(dev, "reconfiguration for multicast lists\n");
3048         nv_start_rx(dev);
3049         spin_unlock_irq(&np->lock);
3050 }
3051
3052 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
3053 {
3054         struct fe_priv *np = netdev_priv(dev);
3055         u8 __iomem *base = get_hwbase(dev);
3056
3057         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3058
3059         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3060                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3061                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3062                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3063                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3064                 } else {
3065                         writel(pff, base + NvRegPacketFilterFlags);
3066                 }
3067         }
3068         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3069                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3070                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3071                         u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3072                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3073                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3074                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3075                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3076                                 /* limit the number of tx pause frames to a default of 8 */
3077                                 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3078                         }
3079                         writel(pause_enable,  base + NvRegTxPauseFrame);
3080                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3081                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3082                 } else {
3083                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
3084                         writel(regmisc, base + NvRegMisc1);
3085                 }
3086         }
3087 }
3088
3089 /**
3090  * nv_update_linkspeed: Setup the MAC according to the link partner
3091  * @dev: Network device to be configured
3092  *
3093  * The function queries the PHY and checks if there is a link partner.
3094  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3095  * set to 10 MBit HD.
3096  *
3097  * The function returns 0 if there is no link partner and 1 if there is
3098  * a good link partner.
3099  */
3100 static int nv_update_linkspeed(struct net_device *dev)
3101 {
3102         struct fe_priv *np = netdev_priv(dev);
3103         u8 __iomem *base = get_hwbase(dev);
3104         int adv = 0;
3105         int lpa = 0;
3106         int adv_lpa, adv_pause, lpa_pause;
3107         int newls = np->linkspeed;
3108         int newdup = np->duplex;
3109         int mii_status;
3110         int retval = 0;
3111         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3112         u32 txrxFlags = 0;
3113         u32 phy_exp;
3114
3115         /* BMSR_LSTATUS is latched, read it twice:
3116          * we want the current value.
3117          */
3118         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3119         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3120
3121         if (!(mii_status & BMSR_LSTATUS)) {
3122                 netdev_dbg(dev,
3123                            "no link detected by phy - falling back to 10HD\n");
3124                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3125                 newdup = 0;
3126                 retval = 0;
3127                 goto set_speed;
3128         }
3129
3130         if (np->autoneg == 0) {
3131                 netdev_dbg(dev, "%s: autoneg off, PHY set to 0x%04x\n",
3132                            __func__, np->fixed_mode);
3133                 if (np->fixed_mode & LPA_100FULL) {
3134                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3135                         newdup = 1;
3136                 } else if (np->fixed_mode & LPA_100HALF) {
3137                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3138                         newdup = 0;
3139                 } else if (np->fixed_mode & LPA_10FULL) {
3140                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3141                         newdup = 1;
3142                 } else {
3143                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3144                         newdup = 0;
3145                 }
3146                 retval = 1;
3147                 goto set_speed;
3148         }
3149         /* check auto negotiation is complete */
3150         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3151                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3152                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3153                 newdup = 0;
3154                 retval = 0;
3155                 netdev_dbg(dev,
3156                            "autoneg not completed - falling back to 10HD\n");
3157                 goto set_speed;
3158         }
3159
3160         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3161         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3162         netdev_dbg(dev, "%s: PHY advertises 0x%04x, lpa 0x%04x\n",
3163                    __func__, adv, lpa);
3164
3165         retval = 1;
3166         if (np->gigabit == PHY_GIGABIT) {
3167                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3168                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3169
3170                 if ((control_1000 & ADVERTISE_1000FULL) &&
3171                         (status_1000 & LPA_1000FULL)) {
3172                         netdev_dbg(dev, "%s: GBit ethernet detected\n",
3173                                    __func__);
3174                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3175                         newdup = 1;
3176                         goto set_speed;
3177                 }
3178         }
3179
3180         /* FIXME: handle parallel detection properly */
3181         adv_lpa = lpa & adv;
3182         if (adv_lpa & LPA_100FULL) {
3183                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3184                 newdup = 1;
3185         } else if (adv_lpa & LPA_100HALF) {
3186                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3187                 newdup = 0;
3188         } else if (adv_lpa & LPA_10FULL) {
3189                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3190                 newdup = 1;
3191         } else if (adv_lpa & LPA_10HALF) {
3192                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3193                 newdup = 0;
3194         } else {
3195                 netdev_dbg(dev, "bad ability %04x - falling back to 10HD\n",
3196                            adv_lpa);
3197                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3198                 newdup = 0;
3199         }
3200
3201 set_speed:
3202         if (np->duplex == newdup && np->linkspeed == newls)
3203                 return retval;
3204
3205         netdev_dbg(dev, "changing link setting from %d/%d to %d/%d\n",
3206                    np->linkspeed, np->duplex, newls, newdup);
3207
3208         np->duplex = newdup;
3209         np->linkspeed = newls;
3210
3211         /* The transmitter and receiver must be restarted for safe update */
3212         if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3213                 txrxFlags |= NV_RESTART_TX;
3214                 nv_stop_tx(dev);
3215         }
3216         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3217                 txrxFlags |= NV_RESTART_RX;
3218                 nv_stop_rx(dev);
3219         }
3220
3221         if (np->gigabit == PHY_GIGABIT) {
3222                 phyreg = readl(base + NvRegSlotTime);
3223                 phyreg &= ~(0x3FF00);
3224                 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3225                     ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3226                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3227                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3228                         phyreg |= NVREG_SLOTTIME_1000_FULL;
3229                 writel(phyreg, base + NvRegSlotTime);
3230         }
3231
3232         phyreg = readl(base + NvRegPhyInterface);
3233         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3234         if (np->duplex == 0)
3235                 phyreg |= PHY_HALF;
3236         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3237                 phyreg |= PHY_100;
3238         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3239                 phyreg |= PHY_1000;
3240         writel(phyreg, base + NvRegPhyInterface);
3241
3242         phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3243         if (phyreg & PHY_RGMII) {
3244                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3245                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3246                 } else {
3247                         if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3248                                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3249                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3250                                 else
3251                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3252                         } else {
3253                                 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3254                         }
3255                 }
3256         } else {
3257                 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3258                         txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3259                 else
3260                         txreg = NVREG_TX_DEFERRAL_DEFAULT;
3261         }
3262         writel(txreg, base + NvRegTxDeferral);
3263
3264         if (np->desc_ver == DESC_VER_1) {
3265                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3266         } else {
3267                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3268                         txreg = NVREG_TX_WM_DESC2_3_1000;
3269                 else
3270                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3271         }
3272         writel(txreg, base + NvRegTxWatermark);
3273
3274         writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3275                 base + NvRegMisc1);
3276         pci_push(base);
3277         writel(np->linkspeed, base + NvRegLinkSpeed);
3278         pci_push(base);
3279
3280         pause_flags = 0;
3281         /* setup pause frame */
3282         if (np->duplex != 0) {
3283                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3284                         adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3285                         lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
3286
3287                         switch (adv_pause) {
3288                         case ADVERTISE_PAUSE_CAP:
3289                                 if (lpa_pause & LPA_PAUSE_CAP) {
3290                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3291                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3292                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3293                                 }
3294                                 break;
3295                         case ADVERTISE_PAUSE_ASYM:
3296                                 if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM))
3297                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3298                                 break;
3299                         case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM:
3300                                 if (lpa_pause & LPA_PAUSE_CAP) {
3301                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
3302                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3303                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3304                                 }
3305                                 if (lpa_pause == LPA_PAUSE_ASYM)
3306                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3307                                 break;
3308                         }
3309                 } else {
3310                         pause_flags = np->pause_flags;
3311                 }
3312         }
3313         nv_update_pause(dev, pause_flags);
3314
3315         if (txrxFlags & NV_RESTART_TX)
3316                 nv_start_tx(dev);
3317         if (txrxFlags & NV_RESTART_RX)
3318                 nv_start_rx(dev);
3319
3320         return retval;
3321 }
3322
3323 static void nv_linkchange(struct net_device *dev)
3324 {
3325         if (nv_update_linkspeed(dev)) {
3326                 if (!netif_carrier_ok(dev)) {
3327                         netif_carrier_on(dev);
3328                         netdev_info(dev, "link up\n");
3329                         nv_txrx_gate(dev, false);
3330                         nv_start_rx(dev);
3331                 }
3332         } else {
3333                 if (netif_carrier_ok(dev)) {
3334                         netif_carrier_off(dev);
3335                         netdev_info(dev, "link down\n");
3336                         nv_txrx_gate(dev, true);
3337                         nv_stop_rx(dev);
3338                 }
3339         }
3340 }
3341
3342 static void nv_link_irq(struct net_device *dev)
3343 {
3344         u8 __iomem *base = get_hwbase(dev);
3345         u32 miistat;
3346
3347         miistat = readl(base + NvRegMIIStatus);
3348         writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3349         netdev_dbg(dev, "link change irq, status 0x%x\n", miistat);
3350
3351         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3352                 nv_linkchange(dev);
3353         netdev_dbg(dev, "link change notification done\n");
3354 }
3355
3356 static void nv_msi_workaround(struct fe_priv *np)
3357 {
3358
3359         /* Need to toggle the msi irq mask within the ethernet device,
3360          * otherwise, future interrupts will not be detected.
3361          */
3362         if (np->msi_flags & NV_MSI_ENABLED) {
3363                 u8 __iomem *base = np->base;
3364
3365                 writel(0, base + NvRegMSIIrqMask);
3366                 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3367         }
3368 }
3369
3370 static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3371 {
3372         struct fe_priv *np = netdev_priv(dev);
3373
3374         if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3375                 if (total_work > NV_DYNAMIC_THRESHOLD) {
3376                         /* transition to poll based interrupts */
3377                         np->quiet_count = 0;
3378                         if (np->irqmask != NVREG_IRQMASK_CPU) {
3379                                 np->irqmask = NVREG_IRQMASK_CPU;
3380                                 return 1;
3381                         }
3382                 } else {
3383                         if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3384                                 np->quiet_count++;
3385                         } else {
3386                                 /* reached a period of low activity, switch
3387                                    to per tx/rx packet interrupts */
3388                                 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3389                                         np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3390                                         return 1;
3391                                 }
3392                         }
3393                 }
3394         }
3395         return 0;
3396 }
3397
3398 static irqreturn_t nv_nic_irq(int foo, void *data)
3399 {
3400         struct net_device *dev = (struct net_device *) data;
3401         struct fe_priv *np = netdev_priv(dev);
3402         u8 __iomem *base = get_hwbase(dev);
3403
3404         netdev_dbg(dev, "%s\n", __func__);
3405
3406         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3407                 np->events = readl(base + NvRegIrqStatus);
3408                 writel(np->events, base + NvRegIrqStatus);
3409         } else {
3410                 np->events = readl(base + NvRegMSIXIrqStatus);
3411                 writel(np->events, base + NvRegMSIXIrqStatus);
3412         }
3413         netdev_dbg(dev, "irq: %08x\n", np->events);
3414         if (!(np->events & np->irqmask))
3415                 return IRQ_NONE;
3416
3417         nv_msi_workaround(np);
3418
3419         if (napi_schedule_prep(&np->napi)) {
3420                 /*
3421                  * Disable further irq's (msix not enabled with napi)
3422                  */
3423                 writel(0, base + NvRegIrqMask);
3424                 __napi_schedule(&np->napi);
3425         }
3426
3427         netdev_dbg(dev, "%s: completed\n", __func__);
3428
3429         return IRQ_HANDLED;
3430 }
3431
3432 /**
3433  * All _optimized functions are used to help increase performance
3434  * (reduce CPU and increase throughput). They use descripter version 3,
3435  * compiler directives, and reduce memory accesses.
3436  */
3437 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3438 {
3439         struct net_device *dev = (struct net_device *) data;
3440         struct fe_priv *np = netdev_priv(dev);
3441         u8 __iomem *base = get_hwbase(dev);
3442
3443         netdev_dbg(dev, "%s\n", __func__);
3444
3445         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3446                 np->events = readl(base + NvRegIrqStatus);
3447                 writel(np->events, base + NvRegIrqStatus);
3448         } else {
3449                 np->events = readl(base + NvRegMSIXIrqStatus);
3450                 writel(np->events, base + NvRegMSIXIrqStatus);
3451         }
3452         netdev_dbg(dev, "irq: %08x\n", np->events);
3453         if (!(np->events & np->irqmask))
3454                 return IRQ_NONE;
3455
3456         nv_msi_workaround(np);
3457
3458         if (napi_schedule_prep(&np->napi)) {
3459                 /*
3460                  * Disable further irq's (msix not enabled with napi)
3461                  */
3462                 writel(0, base + NvRegIrqMask);
3463                 __napi_schedule(&np->napi);
3464         }
3465         netdev_dbg(dev, "%s: completed\n", __func__);
3466
3467         return IRQ_HANDLED;
3468 }
3469
3470 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3471 {
3472         struct net_device *dev = (struct net_device *) data;
3473         struct fe_priv *np = netdev_priv(dev);
3474         u8 __iomem *base = get_hwbase(dev);
3475         u32 events;
3476         int i;
3477         unsigned long flags;
3478
3479         netdev_dbg(dev, "%s\n", __func__);
3480
3481         for (i = 0;; i++) {
3482                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3483                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3484                 netdev_dbg(dev, "tx irq: %08x\n", events);
3485                 if (!(events & np->irqmask))
3486                         break;
3487
3488                 spin_lock_irqsave(&np->lock, flags);
3489                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3490                 spin_unlock_irqrestore(&np->lock, flags);
3491
3492                 if (unlikely(i > max_interrupt_work)) {
3493                         spin_lock_irqsave(&np->lock, flags);
3494                         /* disable interrupts on the nic */
3495                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3496                         pci_push(base);
3497
3498                         if (!np->in_shutdown) {
3499                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3500                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3501                         }
3502                         spin_unlock_irqrestore(&np->lock, flags);
3503                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3504                         break;
3505                 }
3506
3507         }
3508         netdev_dbg(dev, "%s: completed\n", __func__);
3509
3510         return IRQ_RETVAL(i);
3511 }
3512
3513 static int nv_napi_poll(struct napi_struct *napi, int budget)
3514 {
3515         struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3516         struct net_device *dev = np->dev;
3517         u8 __iomem *base = get_hwbase(dev);
3518         unsigned long flags;
3519         int retcode;
3520         int rx_count, tx_work = 0, rx_work = 0;
3521
3522         do {
3523                 if (!nv_optimized(np)) {
3524                         spin_lock_irqsave(&np->lock, flags);
3525                         tx_work += nv_tx_done(dev, np->tx_ring_size);
3526                         spin_unlock_irqrestore(&np->lock, flags);
3527
3528                         rx_count = nv_rx_process(dev, budget - rx_work);
3529                         retcode = nv_alloc_rx(dev);
3530                 } else {
3531                         spin_lock_irqsave(&np->lock, flags);
3532                         tx_work += nv_tx_done_optimized(dev, np->tx_ring_size);
3533                         spin_unlock_irqrestore(&np->lock, flags);
3534
3535                         rx_count = nv_rx_process_optimized(dev,
3536                             budget - rx_work);
3537                         retcode = nv_alloc_rx_optimized(dev);
3538                 }
3539         } while (retcode == 0 &&
3540                  rx_count > 0 && (rx_work += rx_count) < budget);
3541
3542         if (retcode) {
3543                 spin_lock_irqsave(&np->lock, flags);
3544                 if (!np->in_shutdown)
3545                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3546                 spin_unlock_irqrestore(&np->lock, flags);
3547         }
3548
3549         nv_change_interrupt_mode(dev, tx_work + rx_work);
3550
3551         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3552                 spin_lock_irqsave(&np->lock, flags);
3553                 nv_link_irq(dev);
3554                 spin_unlock_irqrestore(&np->lock, flags);
3555         }
3556         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3557                 spin_lock_irqsave(&np->lock, flags);
3558                 nv_linkchange(dev);
3559                 spin_unlock_irqrestore(&np->lock, flags);
3560                 np->link_timeout = jiffies + LINK_TIMEOUT;
3561         }
3562         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3563                 spin_lock_irqsave(&np->lock, flags);
3564                 if (!np->in_shutdown) {
3565                         np->nic_poll_irq = np->irqmask;
3566                         np->recover_error = 1;
3567                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3568                 }
3569                 spin_unlock_irqrestore(&np->lock, flags);
3570                 napi_complete(napi);
3571                 return rx_work;
3572         }
3573
3574         if (rx_work < budget) {
3575                 /* re-enable interrupts
3576                    (msix not enabled in napi) */
3577                 napi_complete(napi);
3578
3579                 writel(np->irqmask, base + NvRegIrqMask);
3580         }
3581         return rx_work;
3582 }
3583
3584 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3585 {
3586         struct net_device *dev = (struct net_device *) data;
3587         struct fe_priv *np = netdev_priv(dev);
3588         u8 __iomem *base = get_hwbase(dev);
3589         u32 events;
3590         int i;
3591         unsigned long flags;
3592
3593         netdev_dbg(dev, "%s\n", __func__);
3594
3595         for (i = 0;; i++) {
3596                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3597                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3598                 netdev_dbg(dev, "rx irq: %08x\n", events);
3599                 if (!(events & np->irqmask))
3600                         break;
3601
3602                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3603                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3604                                 spin_lock_irqsave(&np->lock, flags);
3605                                 if (!np->in_shutdown)
3606                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3607                                 spin_unlock_irqrestore(&np->lock, flags);
3608                         }
3609                 }
3610
3611                 if (unlikely(i > max_interrupt_work)) {
3612                         spin_lock_irqsave(&np->lock, flags);
3613                         /* disable interrupts on the nic */
3614                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3615                         pci_push(base);
3616
3617                         if (!np->in_shutdown) {
3618                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3619                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3620                         }
3621                         spin_unlock_irqrestore(&np->lock, flags);
3622                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3623                         break;
3624                 }
3625         }
3626         netdev_dbg(dev, "%s: completed\n", __func__);
3627
3628         return IRQ_RETVAL(i);
3629 }
3630
3631 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3632 {
3633         struct net_device *dev = (struct net_device *) data;
3634         struct fe_priv *np = netdev_priv(dev);
3635         u8 __iomem *base = get_hwbase(dev);
3636         u32 events;
3637         int i;
3638         unsigned long flags;
3639
3640         netdev_dbg(dev, "%s\n", __func__);
3641
3642         for (i = 0;; i++) {
3643                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3644                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3645                 netdev_dbg(dev, "irq: %08x\n", events);
3646                 if (!(events & np->irqmask))
3647                         break;
3648
3649                 /* check tx in case we reached max loop limit in tx isr */
3650                 spin_lock_irqsave(&np->lock, flags);
3651                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3652                 spin_unlock_irqrestore(&np->lock, flags);
3653
3654                 if (events & NVREG_IRQ_LINK) {
3655                         spin_lock_irqsave(&np->lock, flags);
3656                         nv_link_irq(dev);
3657                         spin_unlock_irqrestore(&np->lock, flags);
3658                 }
3659                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3660                         spin_lock_irqsave(&np->lock, flags);
3661                         nv_linkchange(dev);
3662                         spin_unlock_irqrestore(&np->lock, flags);
3663                         np->link_timeout = jiffies + LINK_TIMEOUT;
3664                 }
3665                 if (events & NVREG_IRQ_RECOVER_ERROR) {
3666                         spin_lock_irq(&np->lock);
3667                         /* disable interrupts on the nic */
3668                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3669                         pci_push(base);
3670
3671                         if (!np->in_shutdown) {
3672                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3673                                 np->recover_error = 1;
3674                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3675                         }
3676                         spin_unlock_irq(&np->lock);
3677                         break;
3678                 }
3679                 if (unlikely(i > max_interrupt_work)) {
3680                         spin_lock_irqsave(&np->lock, flags);
3681                         /* disable interrupts on the nic */
3682                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3683                         pci_push(base);
3684
3685                         if (!np->in_shutdown) {
3686                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3687                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3688                         }
3689                         spin_unlock_irqrestore(&np->lock, flags);
3690                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3691                         break;
3692                 }
3693
3694         }
3695         netdev_dbg(dev, "%s: completed\n", __func__);
3696
3697         return IRQ_RETVAL(i);
3698 }
3699
3700 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3701 {
3702         struct net_device *dev = (struct net_device *) data;
3703         struct fe_priv *np = netdev_priv(dev);
3704         u8 __iomem *base = get_hwbase(dev);
3705         u32 events;
3706
3707         netdev_dbg(dev, "%s\n", __func__);
3708
3709         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3710                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3711                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3712         } else {
3713                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3714                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3715         }
3716         pci_push(base);
3717         netdev_dbg(dev, "irq: %08x\n", events);
3718         if (!(events & NVREG_IRQ_TIMER))
3719                 return IRQ_RETVAL(0);
3720
3721         nv_msi_workaround(np);
3722
3723         spin_lock(&np->lock);
3724         np->intr_test = 1;
3725         spin_unlock(&np->lock);
3726
3727         netdev_dbg(dev, "%s: completed\n", __func__);
3728
3729         return IRQ_RETVAL(1);
3730 }
3731
3732 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3733 {
3734         u8 __iomem *base = get_hwbase(dev);
3735         int i;
3736         u32 msixmap = 0;
3737
3738         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3739          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3740          * the remaining 8 interrupts.
3741          */
3742         for (i = 0; i < 8; i++) {
3743                 if ((irqmask >> i) & 0x1)
3744                         msixmap |= vector << (i << 2);
3745         }
3746         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3747
3748         msixmap = 0;
3749         for (i = 0; i < 8; i++) {
3750                 if ((irqmask >> (i + 8)) & 0x1)
3751                         msixmap |= vector << (i << 2);
3752         }
3753         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3754 }
3755
3756 static int nv_request_irq(struct net_device *dev, int intr_test)
3757 {
3758         struct fe_priv *np = get_nvpriv(dev);
3759         u8 __iomem *base = get_hwbase(dev);
3760         int ret = 1;
3761         int i;
3762         irqreturn_t (*handler)(int foo, void *data);
3763
3764         if (intr_test) {
3765                 handler = nv_nic_irq_test;
3766         } else {
3767                 if (nv_optimized(np))
3768                         handler = nv_nic_irq_optimized;
3769                 else
3770                         handler = nv_nic_irq;
3771         }
3772
3773         if (np->msi_flags & NV_MSI_X_CAPABLE) {
3774                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3775                         np->msi_x_entry[i].entry = i;
3776                 ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK));
3777                 if (ret == 0) {
3778                         np->msi_flags |= NV_MSI_X_ENABLED;
3779                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3780                                 /* Request irq for rx handling */
3781                                 sprintf(np->name_rx, "%s-rx", dev->name);
3782                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3783                                                 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
3784                                         netdev_info(dev,
3785                                                     "request_irq failed for rx %d\n",
3786                                                     ret);
3787                                         pci_disable_msix(np->pci_dev);
3788                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3789                                         goto out_err;
3790                                 }
3791                                 /* Request irq for tx handling */
3792                                 sprintf(np->name_tx, "%s-tx", dev->name);
3793                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
3794                                                 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
3795                                         netdev_info(dev,
3796                                                     "request_irq failed for tx %d\n",
3797                                                     ret);
3798                                         pci_disable_msix(np->pci_dev);
3799                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3800                                         goto out_free_rx;
3801                                 }
3802                                 /* Request irq for link and timer handling */
3803                                 sprintf(np->name_other, "%s-other", dev->name);
3804                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
3805                                                 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
3806                                         netdev_info(dev,
3807                                                     "request_irq failed for link %d\n",
3808                                                     ret);
3809                                         pci_disable_msix(np->pci_dev);
3810                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3811                                         goto out_free_tx;
3812                                 }
3813                                 /* map interrupts to their respective vector */
3814                                 writel(0, base + NvRegMSIXMap0);
3815                                 writel(0, base + NvRegMSIXMap1);
3816                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3817                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3818                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3819                         } else {
3820                                 /* Request irq for all interrupts */
3821                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3822                                         netdev_info(dev,
3823                                                     "request_irq failed %d\n",
3824                                                     ret);
3825                                         pci_disable_msix(np->pci_dev);
3826                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3827                                         goto out_err;
3828                                 }
3829
3830                                 /* map interrupts to vector 0 */
3831                                 writel(0, base + NvRegMSIXMap0);
3832                                 writel(0, base + NvRegMSIXMap1);
3833                         }
3834                 }
3835         }
3836         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3837                 ret = pci_enable_msi(np->pci_dev);
3838                 if (ret == 0) {
3839                         np->msi_flags |= NV_MSI_ENABLED;
3840                         dev->irq = np->pci_dev->irq;
3841                         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3842                                 netdev_info(dev, "request_irq failed %d\n",
3843                                             ret);
3844                                 pci_disable_msi(np->pci_dev);
3845                                 np->msi_flags &= ~NV_MSI_ENABLED;
3846                                 dev->irq = np->pci_dev->irq;
3847                                 goto out_err;
3848                         }
3849
3850                         /* map interrupts to vector 0 */
3851                         writel(0, base + NvRegMSIMap0);
3852                         writel(0, base + NvRegMSIMap1);
3853                         /* enable msi vector 0 */
3854                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3855                 }
3856         }
3857         if (ret != 0) {
3858                 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3859                         goto out_err;
3860
3861         }
3862
3863         return 0;
3864 out_free_tx:
3865         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3866 out_free_rx:
3867         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3868 out_err:
3869         return 1;
3870 }
3871
3872 static void nv_free_irq(struct net_device *dev)
3873 {
3874         struct fe_priv *np = get_nvpriv(dev);
3875         int i;
3876
3877         if (np->msi_flags & NV_MSI_X_ENABLED) {
3878                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3879                         free_irq(np->msi_x_entry[i].vector, dev);
3880                 pci_disable_msix(np->pci_dev);
3881                 np->msi_flags &= ~NV_MSI_X_ENABLED;
3882         } else {
3883                 free_irq(np->pci_dev->irq, dev);
3884                 if (np->msi_flags & NV_MSI_ENABLED) {
3885                         pci_disable_msi(np->pci_dev);
3886                         np->msi_flags &= ~NV_MSI_ENABLED;
3887                 }
3888         }
3889 }
3890
3891 static void nv_do_nic_poll(unsigned long data)
3892 {
3893         struct net_device *dev = (struct net_device *) data;
3894         struct fe_priv *np = netdev_priv(dev);
3895         u8 __iomem *base = get_hwbase(dev);
3896         u32 mask = 0;
3897
3898         /*
3899          * First disable irq(s) and then
3900          * reenable interrupts on the nic, we have to do this before calling
3901          * nv_nic_irq because that may decide to do otherwise
3902          */
3903
3904         if (!using_multi_irqs(dev)) {
3905                 if (np->msi_flags & NV_MSI_X_ENABLED)
3906                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3907                 else
3908                         disable_irq_lockdep(np->pci_dev->irq);
3909                 mask = np->irqmask;
3910         } else {
3911                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3912                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3913                         mask |= NVREG_IRQ_RX_ALL;
3914                 }
3915                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3916                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3917                         mask |= NVREG_IRQ_TX_ALL;
3918                 }
3919                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3920                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3921                         mask |= NVREG_IRQ_OTHER;
3922                 }
3923         }
3924         /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
3925
3926         if (np->recover_error) {
3927                 np->recover_error = 0;
3928                 netdev_info(dev, "MAC in recoverable error state\n");
3929                 if (netif_running(dev)) {
3930                         netif_tx_lock_bh(dev);
3931                         netif_addr_lock(dev);
3932                         spin_lock(&np->lock);
3933                         /* stop engines */
3934                         nv_stop_rxtx(dev);
3935                         if (np->driver_data & DEV_HAS_POWER_CNTRL)
3936                                 nv_mac_reset(dev);
3937                         nv_txrx_reset(dev);
3938                         /* drain rx queue */
3939                         nv_drain_rxtx(dev);
3940                         /* reinit driver view of the rx queue */
3941                         set_bufsize(dev);
3942                         if (nv_init_ring(dev)) {
3943                                 if (!np->in_shutdown)
3944                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3945                         }
3946                         /* reinit nic view of the rx queue */
3947                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3948                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3949                         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3950                                 base + NvRegRingSizes);
3951                         pci_push(base);
3952                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3953                         pci_push(base);
3954                         /* clear interrupts */
3955                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3956                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3957                         else
3958                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3959
3960                         /* restart rx engine */
3961                         nv_start_rxtx(dev);
3962                         spin_unlock(&np->lock);
3963                         netif_addr_unlock(dev);
3964                         netif_tx_unlock_bh(dev);
3965                 }
3966         }
3967
3968         writel(mask, base + NvRegIrqMask);
3969         pci_push(base);
3970
3971         if (!using_multi_irqs(dev)) {
3972                 np->nic_poll_irq = 0;
3973                 if (nv_optimized(np))
3974                         nv_nic_irq_optimized(0, dev);
3975                 else
3976                         nv_nic_irq(0, dev);
3977                 if (np->msi_flags & NV_MSI_X_ENABLED)
3978                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3979                 else
3980                         enable_irq_lockdep(np->pci_dev->irq);
3981         } else {
3982                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3983                         np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
3984                         nv_nic_irq_rx(0, dev);
3985                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3986                 }
3987                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3988                         np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
3989                         nv_nic_irq_tx(0, dev);
3990                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3991                 }
3992                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3993                         np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
3994                         nv_nic_irq_other(0, dev);
3995                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3996                 }
3997         }
3998
3999 }
4000
4001 #ifdef CONFIG_NET_POLL_CONTROLLER
4002 static void nv_poll_controller(struct net_device *dev)
4003 {
4004         nv_do_nic_poll((unsigned long) dev);
4005 }
4006 #endif
4007
4008 static void nv_do_stats_poll(unsigned long data)
4009 {
4010         struct net_device *dev = (struct net_device *) data;
4011         struct fe_priv *np = netdev_priv(dev);
4012
4013         nv_get_hw_stats(dev);
4014
4015         if (!np->in_shutdown)
4016                 mod_timer(&np->stats_poll,
4017                         round_jiffies(jiffies + STATS_INTERVAL));
4018 }
4019
4020 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4021 {
4022         struct fe_priv *np = netdev_priv(dev);
4023         strcpy(info->driver, DRV_NAME);
4024         strcpy(info->version, FORCEDETH_VERSION);
4025         strcpy(info->bus_info, pci_name(np->pci_dev));
4026 }
4027
4028 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4029 {
4030         struct fe_priv *np = netdev_priv(dev);
4031         wolinfo->supported = WAKE_MAGIC;
4032
4033         spin_lock_irq(&np->lock);
4034         if (np->wolenabled)
4035                 wolinfo->wolopts = WAKE_MAGIC;
4036         spin_unlock_irq(&np->lock);
4037 }
4038
4039 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4040 {
4041         struct fe_priv *np = netdev_priv(dev);
4042         u8 __iomem *base = get_hwbase(dev);
4043         u32 flags = 0;
4044
4045         if (wolinfo->wolopts == 0) {
4046                 np->wolenabled = 0;
4047         } else if (wolinfo->wolopts & WAKE_MAGIC) {
4048                 np->wolenabled = 1;
4049                 flags = NVREG_WAKEUPFLAGS_ENABLE;
4050         }
4051         if (netif_running(dev)) {
4052                 spin_lock_irq(&np->lock);
4053                 writel(flags, base + NvRegWakeUpFlags);
4054                 spin_unlock_irq(&np->lock);
4055         }
4056         return 0;
4057 }
4058
4059 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4060 {
4061         struct fe_priv *np = netdev_priv(dev);
4062         int adv;
4063
4064         spin_lock_irq(&np->lock);
4065         ecmd->port = PORT_MII;
4066         if (!netif_running(dev)) {
4067                 /* We do not track link speed / duplex setting if the
4068                  * interface is disabled. Force a link check */
4069                 if (nv_update_linkspeed(dev)) {
4070                         if (!netif_carrier_ok(dev))
4071                                 netif_carrier_on(dev);
4072                 } else {
4073                         if (netif_carrier_ok(dev))
4074                                 netif_carrier_off(dev);
4075                 }
4076         }
4077
4078         if (netif_carrier_ok(dev)) {
4079                 switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4080                 case NVREG_LINKSPEED_10:
4081                         ecmd->speed = SPEED_10;
4082                         break;
4083                 case NVREG_LINKSPEED_100:
4084                         ecmd->speed = SPEED_100;
4085                         break;
4086                 case NVREG_LINKSPEED_1000:
4087                         ecmd->speed = SPEED_1000;
4088                         break;
4089                 }
4090                 ecmd->duplex = DUPLEX_HALF;
4091                 if (np->duplex)
4092                         ecmd->duplex = DUPLEX_FULL;
4093         } else {
4094                 ecmd->speed = -1;
4095                 ecmd->duplex = -1;
4096         }
4097
4098         ecmd->autoneg = np->autoneg;
4099
4100         ecmd->advertising = ADVERTISED_MII;
4101         if (np->autoneg) {
4102                 ecmd->advertising |= ADVERTISED_Autoneg;
4103                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4104                 if (adv & ADVERTISE_10HALF)
4105                         ecmd->advertising |= ADVERTISED_10baseT_Half;
4106                 if (adv & ADVERTISE_10FULL)
4107                         ecmd->advertising |= ADVERTISED_10baseT_Full;
4108                 if (adv & ADVERTISE_100HALF)
4109                         ecmd->advertising |= ADVERTISED_100baseT_Half;
4110                 if (adv & ADVERTISE_100FULL)
4111                         ecmd->advertising |= ADVERTISED_100baseT_Full;
4112                 if (np->gigabit == PHY_GIGABIT) {
4113                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4114                         if (adv & ADVERTISE_1000FULL)
4115                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4116                 }
4117         }
4118         ecmd->supported = (SUPPORTED_Autoneg |
4119                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4120                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4121                 SUPPORTED_MII);
4122         if (np->gigabit == PHY_GIGABIT)
4123                 ecmd->supported |= SUPPORTED_1000baseT_Full;
4124
4125         ecmd->phy_address = np->phyaddr;
4126         ecmd->transceiver = XCVR_EXTERNAL;
4127
4128         /* ignore maxtxpkt, maxrxpkt for now */
4129         spin_unlock_irq(&np->lock);
4130         return 0;
4131 }
4132
4133 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4134 {
4135         struct fe_priv *np = netdev_priv(dev);
4136
4137         if (ecmd->port != PORT_MII)
4138                 return -EINVAL;
4139         if (ecmd->transceiver != XCVR_EXTERNAL)
4140                 return -EINVAL;
4141         if (ecmd->phy_address != np->phyaddr) {
4142                 /* TODO: support switching between multiple phys. Should be
4143                  * trivial, but not enabled due to lack of test hardware. */
4144                 return -EINVAL;
4145         }
4146         if (ecmd->autoneg == AUTONEG_ENABLE) {
4147                 u32 mask;
4148
4149                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4150                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4151                 if (np->gigabit == PHY_GIGABIT)
4152                         mask |= ADVERTISED_1000baseT_Full;
4153
4154                 if ((ecmd->advertising & mask) == 0)
4155                         return -EINVAL;
4156
4157         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4158                 /* Note: autonegotiation disable, speed 1000 intentionally
4159                  * forbidden - noone should need that. */
4160
4161                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4162                         return -EINVAL;
4163                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4164                         return -EINVAL;
4165         } else {
4166                 return -EINVAL;
4167         }
4168
4169         netif_carrier_off(dev);
4170         if (netif_running(dev)) {
4171                 unsigned long flags;
4172
4173                 nv_disable_irq(dev);
4174                 netif_tx_lock_bh(dev);
4175                 netif_addr_lock(dev);
4176                 /* with plain spinlock lockdep complains */
4177                 spin_lock_irqsave(&np->lock, flags);
4178                 /* stop engines */
4179                 /* FIXME:
4180                  * this can take some time, and interrupts are disabled
4181                  * due to spin_lock_irqsave, but let's hope no daemon
4182                  * is going to change the settings very often...
4183                  * Worst case:
4184                  * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4185                  * + some minor delays, which is up to a second approximately
4186                  */
4187                 nv_stop_rxtx(dev);
4188                 spin_unlock_irqrestore(&np->lock, flags);
4189                 netif_addr_unlock(dev);
4190                 netif_tx_unlock_bh(dev);
4191         }
4192
4193         if (ecmd->autoneg == AUTONEG_ENABLE) {
4194                 int adv, bmcr;
4195
4196                 np->autoneg = 1;
4197
4198                 /* advertise only what has been requested */
4199                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4200                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4201                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4202                         adv |= ADVERTISE_10HALF;
4203                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4204                         adv |= ADVERTISE_10FULL;
4205                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4206                         adv |= ADVERTISE_100HALF;
4207                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4208                         adv |= ADVERTISE_100FULL;
4209                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
4210                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4211                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4212                         adv |=  ADVERTISE_PAUSE_ASYM;
4213                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4214
4215                 if (np->gigabit == PHY_GIGABIT) {
4216                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4217                         adv &= ~ADVERTISE_1000FULL;
4218                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4219                                 adv |= ADVERTISE_1000FULL;
4220                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4221                 }
4222
4223                 if (netif_running(dev))
4224                         netdev_info(dev, "link down\n");
4225                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4226                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4227                         bmcr |= BMCR_ANENABLE;
4228                         /* reset the phy in order for settings to stick,
4229                          * and cause autoneg to start */
4230                         if (phy_reset(dev, bmcr)) {
4231                                 netdev_info(dev, "phy reset failed\n");
4232                                 return -EINVAL;
4233                         }
4234                 } else {
4235                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4236                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4237                 }
4238         } else {
4239                 int adv, bmcr;
4240
4241                 np->autoneg = 0;
4242
4243                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4244                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4245                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4246                         adv |= ADVERTISE_10HALF;
4247                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4248                         adv |= ADVERTISE_10FULL;
4249                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4250                         adv |= ADVERTISE_100HALF;
4251                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4252                         adv |= ADVERTISE_100FULL;
4253                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4254                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4255                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4256                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4257                 }
4258                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4259                         adv |=  ADVERTISE_PAUSE_ASYM;
4260                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4261                 }
4262                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4263                 np->fixed_mode = adv;
4264
4265                 if (np->gigabit == PHY_GIGABIT) {
4266                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4267                         adv &= ~ADVERTISE_1000FULL;
4268                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4269                 }
4270
4271                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4272                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4273                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4274                         bmcr |= BMCR_FULLDPLX;
4275                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4276                         bmcr |= BMCR_SPEED100;
4277                 if (np->phy_oui == PHY_OUI_MARVELL) {
4278                         /* reset the phy in order for forced mode settings to stick */
4279                         if (phy_reset(dev, bmcr)) {
4280                                 netdev_info(dev, "phy reset failed\n");
4281                                 return -EINVAL;
4282                         }
4283                 } else {
4284                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4285                         if (netif_running(dev)) {
4286                                 /* Wait a bit and then reconfigure the nic. */
4287                                 udelay(10);
4288                                 nv_linkchange(dev);
4289                         }
4290                 }
4291         }
4292
4293         if (netif_running(dev)) {
4294                 nv_start_rxtx(dev);
4295                 nv_enable_irq(dev);
4296         }
4297
4298         return 0;
4299 }
4300
4301 #define FORCEDETH_REGS_VER      1
4302
4303 static int nv_get_regs_len(struct net_device *dev)
4304 {
4305         struct fe_priv *np = netdev_priv(dev);
4306         return np->register_size;
4307 }
4308
4309 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4310 {
4311         struct fe_priv *np = netdev_priv(dev);
4312         u8 __iomem *base = get_hwbase(dev);
4313         u32 *rbuf = buf;
4314         int i;
4315
4316         regs->version = FORCEDETH_REGS_VER;
4317         spin_lock_irq(&np->lock);
4318         for (i = 0; i <= np->register_size/sizeof(u32); i++)
4319                 rbuf[i] = readl(base + i*sizeof(u32));
4320         spin_unlock_irq(&np->lock);
4321 }
4322
4323 static int nv_nway_reset(struct net_device *dev)
4324 {
4325         struct fe_priv *np = netdev_priv(dev);
4326         int ret;
4327
4328         if (np->autoneg) {
4329                 int bmcr;
4330
4331                 netif_carrier_off(dev);
4332                 if (netif_running(dev)) {
4333                         nv_disable_irq(dev);
4334                         netif_tx_lock_bh(dev);
4335                         netif_addr_lock(dev);
4336                         spin_lock(&np->lock);
4337                         /* stop engines */
4338                         nv_stop_rxtx(dev);
4339                         spin_unlock(&np->lock);
4340                         netif_addr_unlock(dev);
4341                         netif_tx_unlock_bh(dev);
4342                         netdev_info(dev, "link down\n");
4343                 }
4344
4345                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4346                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4347                         bmcr |= BMCR_ANENABLE;
4348                         /* reset the phy in order for settings to stick*/
4349                         if (phy_reset(dev, bmcr)) {
4350                                 netdev_info(dev, "phy reset failed\n");
4351                                 return -EINVAL;
4352                         }
4353                 } else {
4354                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4355                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4356                 }
4357
4358                 if (netif_running(dev)) {
4359                         nv_start_rxtx(dev);
4360                         nv_enable_irq(dev);
4361                 }
4362                 ret = 0;
4363         } else {
4364                 ret = -EINVAL;
4365         }
4366
4367         return ret;
4368 }
4369
4370 static int nv_set_tso(struct net_device *dev, u32 value)
4371 {
4372         struct fe_priv *np = netdev_priv(dev);
4373
4374         if ((np->driver_data & DEV_HAS_CHECKSUM))
4375                 return ethtool_op_set_tso(dev, value);
4376         else
4377                 return -EOPNOTSUPP;
4378 }
4379
4380 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4381 {
4382         struct fe_priv *np = netdev_priv(dev);
4383
4384         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4385         ring->rx_mini_max_pending = 0;
4386         ring->rx_jumbo_max_pending = 0;
4387         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4388
4389         ring->rx_pending = np->rx_ring_size;
4390         ring->rx_mini_pending = 0;
4391         ring->rx_jumbo_pending = 0;
4392         ring->tx_pending = np->tx_ring_size;
4393 }
4394
4395 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4396 {
4397         struct fe_priv *np = netdev_priv(dev);
4398         u8 __iomem *base = get_hwbase(dev);
4399         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4400         dma_addr_t ring_addr;
4401
4402         if (ring->rx_pending < RX_RING_MIN ||
4403             ring->tx_pending < TX_RING_MIN ||
4404             ring->rx_mini_pending != 0 ||
4405             ring->rx_jumbo_pending != 0 ||
4406             (np->desc_ver == DESC_VER_1 &&
4407              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4408               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4409             (np->desc_ver != DESC_VER_1 &&
4410              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4411               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4412                 return -EINVAL;
4413         }
4414
4415         /* allocate new rings */
4416         if (!nv_optimized(np)) {
4417                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4418                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4419                                             &ring_addr);
4420         } else {
4421                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4422                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4423                                             &ring_addr);
4424         }
4425         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4426         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4427         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4428                 /* fall back to old rings */
4429                 if (!nv_optimized(np)) {
4430                         if (rxtx_ring)
4431                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4432                                                     rxtx_ring, ring_addr);
4433                 } else {
4434                         if (rxtx_ring)
4435                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4436                                                     rxtx_ring, ring_addr);
4437                 }
4438
4439                 kfree(rx_skbuff);
4440                 kfree(tx_skbuff);
4441                 goto exit;
4442         }
4443
4444         if (netif_running(dev)) {
4445                 nv_disable_irq(dev);
4446                 nv_napi_disable(dev);
4447                 netif_tx_lock_bh(dev);
4448                 netif_addr_lock(dev);
4449                 spin_lock(&np->lock);
4450                 /* stop engines */
4451                 nv_stop_rxtx(dev);
4452                 nv_txrx_reset(dev);
4453                 /* drain queues */
4454                 nv_drain_rxtx(dev);
4455                 /* delete queues */
4456                 free_rings(dev);
4457         }
4458
4459         /* set new values */
4460         np->rx_ring_size = ring->rx_pending;
4461         np->tx_ring_size = ring->tx_pending;
4462
4463         if (!nv_optimized(np)) {
4464                 np->rx_ring.orig = (struct ring_desc *)rxtx_ring;
4465                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4466         } else {
4467                 np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring;
4468                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4469         }
4470         np->rx_skb = (struct nv_skb_map *)rx_skbuff;
4471         np->tx_skb = (struct nv_skb_map *)tx_skbuff;
4472         np->ring_addr = ring_addr;
4473
4474         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4475         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4476
4477         if (netif_running(dev)) {
4478                 /* reinit driver view of the queues */
4479                 set_bufsize(dev);
4480                 if (nv_init_ring(dev)) {
4481                         if (!np->in_shutdown)
4482                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4483                 }
4484
4485                 /* reinit nic view of the queues */
4486                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4487                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4488                 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4489                         base + NvRegRingSizes);
4490                 pci_push(base);
4491                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4492                 pci_push(base);
4493
4494                 /* restart engines */
4495                 nv_start_rxtx(dev);
4496                 spin_unlock(&np->lock);
4497                 netif_addr_unlock(dev);
4498                 netif_tx_unlock_bh(dev);
4499                 nv_napi_enable(dev);
4500                 nv_enable_irq(dev);
4501         }
4502         return 0;
4503 exit:
4504         return -ENOMEM;
4505 }
4506
4507 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4508 {
4509         struct fe_priv *np = netdev_priv(dev);
4510
4511         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4512         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4513         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4514 }
4515
4516 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4517 {
4518         struct fe_priv *np = netdev_priv(dev);
4519         int adv, bmcr;
4520
4521         if ((!np->autoneg && np->duplex == 0) ||
4522             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4523                 netdev_info(dev, "can not set pause settings when forced link is in half duplex\n");
4524                 return -EINVAL;
4525         }
4526         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4527                 netdev_info(dev, "hardware does not support tx pause frames\n");
4528                 return -EINVAL;
4529         }
4530
4531         netif_carrier_off(dev);
4532         if (netif_running(dev)) {
4533                 nv_disable_irq(dev);
4534                 netif_tx_lock_bh(dev);
4535                 netif_addr_lock(dev);
4536                 spin_lock(&np->lock);
4537                 /* stop engines */
4538                 nv_stop_rxtx(dev);
4539                 spin_unlock(&np->lock);
4540                 netif_addr_unlock(dev);
4541                 netif_tx_unlock_bh(dev);
4542         }
4543
4544         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4545         if (pause->rx_pause)
4546                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4547         if (pause->tx_pause)
4548                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4549
4550         if (np->autoneg && pause->autoneg) {
4551                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4552
4553                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4554                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4555                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4556                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4557                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4558                         adv |=  ADVERTISE_PAUSE_ASYM;
4559                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4560
4561                 if (netif_running(dev))
4562                         netdev_info(dev, "link down\n");
4563                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4564                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4565                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4566         } else {
4567                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4568                 if (pause->rx_pause)
4569                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4570                 if (pause->tx_pause)
4571                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4572
4573                 if (!netif_running(dev))
4574                         nv_update_linkspeed(dev);
4575                 else
4576                         nv_update_pause(dev, np->pause_flags);
4577         }
4578
4579         if (netif_running(dev)) {
4580                 nv_start_rxtx(dev);
4581                 nv_enable_irq(dev);
4582         }
4583         return 0;
4584 }
4585
4586 static u32 nv_get_rx_csum(struct net_device *dev)
4587 {
4588         struct fe_priv *np = netdev_priv(dev);
4589         return np->rx_csum != 0;
4590 }
4591
4592 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4593 {
4594         struct fe_priv *np = netdev_priv(dev);
4595         u8 __iomem *base = get_hwbase(dev);
4596         int retcode = 0;
4597
4598         if (np->driver_data & DEV_HAS_CHECKSUM) {
4599                 if (data) {
4600                         np->rx_csum = 1;
4601                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4602                 } else {
4603                         np->rx_csum = 0;
4604                         /* vlan is dependent on rx checksum offload */
4605                         if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4606                                 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4607                 }
4608                 if (netif_running(dev)) {
4609                         spin_lock_irq(&np->lock);
4610                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4611                         spin_unlock_irq(&np->lock);
4612                 }
4613         } else {
4614                 return -EINVAL;
4615         }
4616
4617         return retcode;
4618 }
4619
4620 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4621 {
4622         struct fe_priv *np = netdev_priv(dev);
4623
4624         if (np->driver_data & DEV_HAS_CHECKSUM)
4625                 return ethtool_op_set_tx_csum(dev, data);
4626         else
4627                 return -EOPNOTSUPP;
4628 }
4629
4630 static int nv_set_sg(struct net_device *dev, u32 data)
4631 {
4632         struct fe_priv *np = netdev_priv(dev);
4633
4634         if (np->driver_data & DEV_HAS_CHECKSUM)
4635                 return ethtool_op_set_sg(dev, data);
4636         else
4637                 return -EOPNOTSUPP;
4638 }
4639
4640 static int nv_get_sset_count(struct net_device *dev, int sset)
4641 {
4642         struct fe_priv *np = netdev_priv(dev);
4643
4644         switch (sset) {
4645         case ETH_SS_TEST:
4646                 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4647                         return NV_TEST_COUNT_EXTENDED;
4648                 else
4649                         return NV_TEST_COUNT_BASE;
4650         case ETH_SS_STATS:
4651                 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4652                         return NV_DEV_STATISTICS_V3_COUNT;
4653                 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4654                         return NV_DEV_STATISTICS_V2_COUNT;
4655                 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4656                         return NV_DEV_STATISTICS_V1_COUNT;
4657                 else
4658                         return 0;
4659         default:
4660                 return -EOPNOTSUPP;
4661         }
4662 }
4663
4664 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4665 {
4666         struct fe_priv *np = netdev_priv(dev);
4667
4668         /* update stats */
4669         nv_do_stats_poll((unsigned long)dev);
4670
4671         memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4672 }
4673
4674 static int nv_link_test(struct net_device *dev)
4675 {
4676         struct fe_priv *np = netdev_priv(dev);
4677         int mii_status;
4678
4679         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4680         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4681
4682         /* check phy link status */
4683         if (!(mii_status & BMSR_LSTATUS))
4684                 return 0;
4685         else
4686                 return 1;
4687 }
4688
4689 static int nv_register_test(struct net_device *dev)
4690 {
4691         u8 __iomem *base = get_hwbase(dev);
4692         int i = 0;
4693         u32 orig_read, new_read;
4694
4695         do {
4696                 orig_read = readl(base + nv_registers_test[i].reg);
4697
4698                 /* xor with mask to toggle bits */
4699                 orig_read ^= nv_registers_test[i].mask;
4700
4701                 writel(orig_read, base + nv_registers_test[i].reg);
4702
4703                 new_read = readl(base + nv_registers_test[i].reg);
4704
4705                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4706                         return 0;
4707
4708                 /* restore original value */
4709                 orig_read ^= nv_registers_test[i].mask;
4710                 writel(orig_read, base + nv_registers_test[i].reg);
4711
4712         } while (nv_registers_test[++i].reg != 0);
4713
4714         return 1;
4715 }
4716
4717 static int nv_interrupt_test(struct net_device *dev)
4718 {
4719         struct fe_priv *np = netdev_priv(dev);
4720         u8 __iomem *base = get_hwbase(dev);
4721         int ret = 1;
4722         int testcnt;
4723         u32 save_msi_flags, save_poll_interval = 0;
4724
4725         if (netif_running(dev)) {
4726                 /* free current irq */
4727                 nv_free_irq(dev);
4728                 save_poll_interval = readl(base+NvRegPollingInterval);
4729         }
4730
4731         /* flag to test interrupt handler */
4732         np->intr_test = 0;
4733
4734         /* setup test irq */
4735         save_msi_flags = np->msi_flags;
4736         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4737         np->msi_flags |= 0x001; /* setup 1 vector */
4738         if (nv_request_irq(dev, 1))
4739                 return 0;
4740
4741         /* setup timer interrupt */
4742         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4743         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4744
4745         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4746
4747         /* wait for at least one interrupt */
4748         msleep(100);
4749
4750         spin_lock_irq(&np->lock);
4751
4752         /* flag should be set within ISR */
4753         testcnt = np->intr_test;
4754         if (!testcnt)
4755                 ret = 2;
4756
4757         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4758         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4759                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4760         else
4761                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4762
4763         spin_unlock_irq(&np->lock);
4764
4765         nv_free_irq(dev);
4766
4767         np->msi_flags = save_msi_flags;
4768
4769         if (netif_running(dev)) {
4770                 writel(save_poll_interval, base + NvRegPollingInterval);
4771                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4772                 /* restore original irq */
4773                 if (nv_request_irq(dev, 0))
4774                         return 0;
4775         }
4776
4777         return ret;
4778 }
4779
4780 static int nv_loopback_test(struct net_device *dev)
4781 {
4782         struct fe_priv *np = netdev_priv(dev);
4783         u8 __iomem *base = get_hwbase(dev);
4784         struct sk_buff *tx_skb, *rx_skb;
4785         dma_addr_t test_dma_addr;
4786         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4787         u32 flags;
4788         int len, i, pkt_len;
4789         u8 *pkt_data;
4790         u32 filter_flags = 0;
4791         u32 misc1_flags = 0;
4792         int ret = 1;
4793
4794         if (netif_running(dev)) {
4795                 nv_disable_irq(dev);
4796                 filter_flags = readl(base + NvRegPacketFilterFlags);
4797                 misc1_flags = readl(base + NvRegMisc1);
4798         } else {
4799                 nv_txrx_reset(dev);
4800         }
4801
4802         /* reinit driver view of the rx queue */
4803         set_bufsize(dev);
4804         nv_init_ring(dev);
4805
4806         /* setup hardware for loopback */
4807         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4808         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4809
4810         /* reinit nic view of the rx queue */
4811         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4812         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4813         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4814                 base + NvRegRingSizes);
4815         pci_push(base);
4816
4817         /* restart rx engine */
4818         nv_start_rxtx(dev);
4819
4820         /* setup packet for tx */
4821         pkt_len = ETH_DATA_LEN;
4822         tx_skb = dev_alloc_skb(pkt_len);
4823         if (!tx_skb) {
4824                 netdev_err(dev, "dev_alloc_skb() failed during loopback test\n");
4825                 ret = 0;
4826                 goto out;
4827         }
4828         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4829                                        skb_tailroom(tx_skb),
4830                                        PCI_DMA_FROMDEVICE);
4831         pkt_data = skb_put(tx_skb, pkt_len);
4832         for (i = 0; i < pkt_len; i++)
4833                 pkt_data[i] = (u8)(i & 0xff);
4834
4835         if (!nv_optimized(np)) {
4836                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4837                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4838         } else {
4839                 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4840                 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
4841                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4842         }
4843         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4844         pci_push(get_hwbase(dev));
4845
4846         msleep(500);
4847
4848         /* check for rx of the packet */
4849         if (!nv_optimized(np)) {
4850                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4851                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4852
4853         } else {
4854                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4855                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4856         }
4857
4858         if (flags & NV_RX_AVAIL) {
4859                 ret = 0;
4860         } else if (np->desc_ver == DESC_VER_1) {
4861                 if (flags & NV_RX_ERROR)
4862                         ret = 0;
4863         } else {
4864                 if (flags & NV_RX2_ERROR)
4865                         ret = 0;
4866         }
4867
4868         if (ret) {
4869                 if (len != pkt_len) {
4870                         ret = 0;
4871                         netdev_dbg(dev, "loopback len mismatch %d vs %d\n",
4872                                    len, pkt_len);
4873                 } else {
4874                         rx_skb = np->rx_skb[0].skb;
4875                         for (i = 0; i < pkt_len; i++) {
4876                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4877                                         ret = 0;
4878                                         netdev_dbg(dev, "loopback pattern check failed on byte %d\n",
4879                                                    i);
4880                                         break;
4881                                 }
4882                         }
4883                 }
4884         } else {
4885                 netdev_dbg(dev, "loopback - did not receive test packet\n");
4886         }
4887
4888         pci_unmap_single(np->pci_dev, test_dma_addr,
4889                        (skb_end_pointer(tx_skb) - tx_skb->data),
4890                        PCI_DMA_TODEVICE);
4891         dev_kfree_skb_any(tx_skb);
4892  out:
4893         /* stop engines */
4894         nv_stop_rxtx(dev);
4895         nv_txrx_reset(dev);
4896         /* drain rx queue */
4897         nv_drain_rxtx(dev);
4898
4899         if (netif_running(dev)) {
4900                 writel(misc1_flags, base + NvRegMisc1);
4901                 writel(filter_flags, base + NvRegPacketFilterFlags);
4902                 nv_enable_irq(dev);
4903         }
4904
4905         return ret;
4906 }
4907
4908 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4909 {
4910         struct fe_priv *np = netdev_priv(dev);
4911         u8 __iomem *base = get_hwbase(dev);
4912         int result;
4913         memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
4914
4915         if (!nv_link_test(dev)) {
4916                 test->flags |= ETH_TEST_FL_FAILED;
4917                 buffer[0] = 1;
4918         }
4919
4920         if (test->flags & ETH_TEST_FL_OFFLINE) {
4921                 if (netif_running(dev)) {
4922                         netif_stop_queue(dev);
4923                         nv_napi_disable(dev);
4924                         netif_tx_lock_bh(dev);
4925                         netif_addr_lock(dev);
4926                         spin_lock_irq(&np->lock);
4927                         nv_disable_hw_interrupts(dev, np->irqmask);
4928                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4929                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4930                         else
4931                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4932                         /* stop engines */
4933                         nv_stop_rxtx(dev);
4934                         nv_txrx_reset(dev);
4935                         /* drain rx queue */
4936                         nv_drain_rxtx(dev);
4937                         spin_unlock_irq(&np->lock);
4938                         netif_addr_unlock(dev);
4939                         netif_tx_unlock_bh(dev);
4940                 }
4941
4942                 if (!nv_register_test(dev)) {
4943                         test->flags |= ETH_TEST_FL_FAILED;
4944                         buffer[1] = 1;
4945                 }
4946
4947                 result = nv_interrupt_test(dev);
4948                 if (result != 1) {
4949                         test->flags |= ETH_TEST_FL_FAILED;
4950                         buffer[2] = 1;
4951                 }
4952                 if (result == 0) {
4953                         /* bail out */
4954                         return;
4955                 }
4956
4957                 if (!nv_loopback_test(dev)) {
4958                         test->flags |= ETH_TEST_FL_FAILED;
4959                         buffer[3] = 1;
4960                 }
4961
4962                 if (netif_running(dev)) {
4963                         /* reinit driver view of the rx queue */
4964                         set_bufsize(dev);
4965                         if (nv_init_ring(dev)) {
4966                                 if (!np->in_shutdown)
4967                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4968                         }
4969                         /* reinit nic view of the rx queue */
4970                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4971                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4972                         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4973                                 base + NvRegRingSizes);
4974                         pci_push(base);
4975                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4976                         pci_push(base);
4977                         /* restart rx engine */
4978                         nv_start_rxtx(dev);
4979                         netif_start_queue(dev);
4980                         nv_napi_enable(dev);
4981                         nv_enable_hw_interrupts(dev, np->irqmask);
4982                 }
4983         }
4984 }
4985
4986 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4987 {
4988         switch (stringset) {
4989         case ETH_SS_STATS:
4990                 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
4991                 break;
4992         case ETH_SS_TEST:
4993                 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
4994                 break;
4995         }
4996 }
4997
4998 static const struct ethtool_ops ops = {
4999         .get_drvinfo = nv_get_drvinfo,
5000         .get_link = ethtool_op_get_link,
5001         .get_wol = nv_get_wol,
5002         .set_wol = nv_set_wol,
5003         .get_settings = nv_get_settings,
5004         .set_settings = nv_set_settings,
5005         .get_regs_len = nv_get_regs_len,
5006         .get_regs = nv_get_regs,
5007         .nway_reset = nv_nway_reset,
5008         .set_tso = nv_set_tso,
5009         .get_ringparam = nv_get_ringparam,
5010         .set_ringparam = nv_set_ringparam,
5011         .get_pauseparam = nv_get_pauseparam,
5012         .set_pauseparam = nv_set_pauseparam,
5013         .get_rx_csum = nv_get_rx_csum,
5014         .set_rx_csum = nv_set_rx_csum,
5015         .set_tx_csum = nv_set_tx_csum,
5016         .set_sg = nv_set_sg,
5017         .get_strings = nv_get_strings,
5018         .get_ethtool_stats = nv_get_ethtool_stats,
5019         .get_sset_count = nv_get_sset_count,
5020         .self_test = nv_self_test,
5021 };
5022
5023 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
5024 {
5025         struct fe_priv *np = get_nvpriv(dev);
5026
5027         spin_lock_irq(&np->lock);
5028
5029         /* save vlan group */
5030         np->vlangrp = grp;
5031
5032         if (grp) {
5033                 /* enable vlan on MAC */
5034                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
5035         } else {
5036                 /* disable vlan on MAC */
5037                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
5038                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
5039         }
5040
5041         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5042
5043         spin_unlock_irq(&np->lock);
5044 }
5045
5046 /* The mgmt unit and driver use a semaphore to access the phy during init */
5047 static int nv_mgmt_acquire_sema(struct net_device *dev)
5048 {
5049         struct fe_priv *np = netdev_priv(dev);
5050         u8 __iomem *base = get_hwbase(dev);
5051         int i;
5052         u32 tx_ctrl, mgmt_sema;
5053
5054         for (i = 0; i < 10; i++) {
5055                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5056                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5057                         break;
5058                 msleep(500);
5059         }
5060
5061         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5062                 return 0;
5063
5064         for (i = 0; i < 2; i++) {
5065                 tx_ctrl = readl(base + NvRegTransmitterControl);
5066                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5067                 writel(tx_ctrl, base + NvRegTransmitterControl);
5068
5069                 /* verify that semaphore was acquired */
5070                 tx_ctrl = readl(base + NvRegTransmitterControl);
5071                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5072                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5073                         np->mgmt_sema = 1;
5074                         return 1;
5075                 } else
5076                         udelay(50);
5077         }
5078
5079         return 0;
5080 }
5081
5082 static void nv_mgmt_release_sema(struct net_device *dev)
5083 {
5084         struct fe_priv *np = netdev_priv(dev);
5085         u8 __iomem *base = get_hwbase(dev);
5086         u32 tx_ctrl;
5087
5088         if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5089                 if (np->mgmt_sema) {
5090                         tx_ctrl = readl(base + NvRegTransmitterControl);
5091                         tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5092                         writel(tx_ctrl, base + NvRegTransmitterControl);
5093                 }
5094         }
5095 }
5096
5097
5098 static int nv_mgmt_get_version(struct net_device *dev)
5099 {
5100         struct fe_priv *np = netdev_priv(dev);
5101         u8 __iomem *base = get_hwbase(dev);
5102         u32 data_ready = readl(base + NvRegTransmitterControl);
5103         u32 data_ready2 = 0;
5104         unsigned long start;
5105         int ready = 0;
5106
5107         writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5108         writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5109         start = jiffies;
5110         while (time_before(jiffies, start + 5*HZ)) {
5111                 data_ready2 = readl(base + NvRegTransmitterControl);
5112                 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5113                         ready = 1;
5114                         break;
5115                 }
5116                 schedule_timeout_uninterruptible(1);
5117         }
5118
5119         if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5120                 return 0;
5121
5122         np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5123
5124         return 1;
5125 }
5126
5127 static int nv_open(struct net_device *dev)
5128 {
5129         struct fe_priv *np = netdev_priv(dev);
5130         u8 __iomem *base = get_hwbase(dev);
5131         int ret = 1;
5132         int oom, i;
5133         u32 low;
5134
5135         netdev_dbg(dev, "%s\n", __func__);
5136
5137         /* power up phy */
5138         mii_rw(dev, np->phyaddr, MII_BMCR,
5139                mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5140
5141         nv_txrx_gate(dev, false);
5142         /* erase previous misconfiguration */
5143         if (np->driver_data & DEV_HAS_POWER_CNTRL)
5144                 nv_mac_reset(dev);
5145         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5146         writel(0, base + NvRegMulticastAddrB);
5147         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5148         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5149         writel(0, base + NvRegPacketFilterFlags);
5150
5151         writel(0, base + NvRegTransmitterControl);
5152         writel(0, base + NvRegReceiverControl);
5153
5154         writel(0, base + NvRegAdapterControl);
5155
5156         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5157                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
5158
5159         /* initialize descriptor rings */
5160         set_bufsize(dev);
5161         oom = nv_init_ring(dev);
5162
5163         writel(0, base + NvRegLinkSpeed);
5164         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5165         nv_txrx_reset(dev);
5166         writel(0, base + NvRegUnknownSetupReg6);
5167
5168         np->in_shutdown = 0;
5169
5170         /* give hw rings */
5171         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5172         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5173                 base + NvRegRingSizes);
5174
5175         writel(np->linkspeed, base + NvRegLinkSpeed);
5176         if (np->desc_ver == DESC_VER_1)
5177                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5178         else
5179                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5180         writel(np->txrxctl_bits, base + NvRegTxRxControl);
5181         writel(np->vlanctl_bits, base + NvRegVlanControl);
5182         pci_push(base);
5183         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5184         if (reg_delay(dev, NvRegUnknownSetupReg5,
5185                       NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5186                       NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX))
5187                 netdev_info(dev,
5188                             "%s: SetupReg5, Bit 31 remained off\n", __func__);
5189
5190         writel(0, base + NvRegMIIMask);
5191         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5192         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5193
5194         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5195         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5196         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5197         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5198
5199         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5200
5201         get_random_bytes(&low, sizeof(low));
5202         low &= NVREG_SLOTTIME_MASK;
5203         if (np->desc_ver == DESC_VER_1) {
5204                 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5205         } else {
5206                 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5207                         /* setup legacy backoff */
5208                         writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5209                 } else {
5210                         writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5211                         nv_gear_backoff_reseed(dev);
5212                 }
5213         }
5214         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5215         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5216         if (poll_interval == -1) {
5217                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5218                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5219                 else
5220                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5221         } else
5222                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5223         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5224         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5225                         base + NvRegAdapterControl);
5226         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5227         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5228         if (np->wolenabled)
5229                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5230
5231         i = readl(base + NvRegPowerState);
5232         if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
5233                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5234
5235         pci_push(base);
5236         udelay(10);
5237         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5238
5239         nv_disable_hw_interrupts(dev, np->irqmask);
5240         pci_push(base);
5241         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5242         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5243         pci_push(base);
5244
5245         if (nv_request_irq(dev, 0))
5246                 goto out_drain;
5247
5248         /* ask for interrupts */
5249         nv_enable_hw_interrupts(dev, np->irqmask);
5250
5251         spin_lock_irq(&np->lock);
5252         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5253         writel(0, base + NvRegMulticastAddrB);
5254         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5255         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5256         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5257         /* One manual link speed update: Interrupts are enabled, future link
5258          * speed changes cause interrupts and are handled by nv_link_irq().
5259          */
5260         {
5261                 u32 miistat;
5262                 miistat = readl(base + NvRegMIIStatus);
5263                 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5264                 netdev_dbg(dev, "startup: got 0x%08x\n", miistat);
5265         }
5266         /* set linkspeed to invalid value, thus force nv_update_linkspeed
5267          * to init hw */
5268         np->linkspeed = 0;
5269         ret = nv_update_linkspeed(dev);
5270         nv_start_rxtx(dev);
5271         netif_start_queue(dev);
5272         nv_napi_enable(dev);
5273
5274         if (ret) {
5275                 netif_carrier_on(dev);
5276         } else {
5277                 netdev_info(dev, "no link during initialization\n");
5278                 netif_carrier_off(dev);
5279         }
5280         if (oom)
5281                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5282
5283         /* start statistics timer */
5284         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5285                 mod_timer(&np->stats_poll,
5286                         round_jiffies(jiffies + STATS_INTERVAL));
5287
5288         spin_unlock_irq(&np->lock);
5289
5290         return 0;
5291 out_drain:
5292         nv_drain_rxtx(dev);
5293         return ret;
5294 }
5295
5296 static int nv_close(struct net_device *dev)
5297 {
5298         struct fe_priv *np = netdev_priv(dev);
5299         u8 __iomem *base;
5300
5301         spin_lock_irq(&np->lock);
5302         np->in_shutdown = 1;
5303         spin_unlock_irq(&np->lock);
5304         nv_napi_disable(dev);
5305         synchronize_irq(np->pci_dev->irq);
5306
5307         del_timer_sync(&np->oom_kick);
5308         del_timer_sync(&np->nic_poll);
5309         del_timer_sync(&np->stats_poll);
5310
5311         netif_stop_queue(dev);
5312         spin_lock_irq(&np->lock);
5313         nv_stop_rxtx(dev);
5314         nv_txrx_reset(dev);
5315
5316         /* disable interrupts on the nic or we will lock up */
5317         base = get_hwbase(dev);
5318         nv_disable_hw_interrupts(dev, np->irqmask);
5319         pci_push(base);
5320         netdev_dbg(dev, "Irqmask is zero again\n");
5321
5322         spin_unlock_irq(&np->lock);
5323
5324         nv_free_irq(dev);
5325
5326         nv_drain_rxtx(dev);
5327
5328         if (np->wolenabled || !phy_power_down) {
5329                 nv_txrx_gate(dev, false);
5330                 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5331                 nv_start_rx(dev);
5332         } else {
5333                 /* power down phy */
5334                 mii_rw(dev, np->phyaddr, MII_BMCR,
5335                        mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5336                 nv_txrx_gate(dev, true);
5337         }
5338
5339         /* FIXME: power down nic */
5340
5341         return 0;
5342 }
5343
5344 static const struct net_device_ops nv_netdev_ops = {
5345         .ndo_open               = nv_open,
5346         .ndo_stop               = nv_close,
5347         .ndo_get_stats          = nv_get_stats,
5348         .ndo_start_xmit         = nv_start_xmit,
5349         .ndo_tx_timeout         = nv_tx_timeout,
5350         .ndo_change_mtu         = nv_change_mtu,
5351         .ndo_validate_addr      = eth_validate_addr,
5352         .ndo_set_mac_address    = nv_set_mac_address,
5353         .ndo_set_multicast_list = nv_set_multicast,
5354         .ndo_vlan_rx_register   = nv_vlan_rx_register,
5355 #ifdef CONFIG_NET_POLL_CONTROLLER
5356         .ndo_poll_controller    = nv_poll_controller,
5357 #endif
5358 };
5359
5360 static const struct net_device_ops nv_netdev_ops_optimized = {
5361         .ndo_open               = nv_open,
5362         .ndo_stop               = nv_close,
5363         .ndo_get_stats          = nv_get_stats,
5364         .ndo_start_xmit         = nv_start_xmit_optimized,
5365         .ndo_tx_timeout         = nv_tx_timeout,
5366         .ndo_change_mtu         = nv_change_mtu,
5367         .ndo_validate_addr      = eth_validate_addr,
5368         .ndo_set_mac_address    = nv_set_mac_address,
5369         .ndo_set_multicast_list = nv_set_multicast,
5370         .ndo_vlan_rx_register   = nv_vlan_rx_register,
5371 #ifdef CONFIG_NET_POLL_CONTROLLER
5372         .ndo_poll_controller    = nv_poll_controller,
5373 #endif
5374 };
5375
5376 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5377 {
5378         struct net_device *dev;
5379         struct fe_priv *np;
5380         unsigned long addr;
5381         u8 __iomem *base;
5382         int err, i;
5383         u32 powerstate, txreg;
5384         u32 phystate_orig = 0, phystate;
5385         int phyinitialized = 0;
5386         static int printed_version;
5387
5388         if (!printed_version++)
5389                 pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n",
5390                         FORCEDETH_VERSION);
5391
5392         dev = alloc_etherdev(sizeof(struct fe_priv));
5393         err = -ENOMEM;
5394         if (!dev)
5395                 goto out;
5396
5397         np = netdev_priv(dev);
5398         np->dev = dev;
5399         np->pci_dev = pci_dev;
5400         spin_lock_init(&np->lock);
5401         SET_NETDEV_DEV(dev, &pci_dev->dev);
5402
5403         init_timer(&np->oom_kick);
5404         np->oom_kick.data = (unsigned long) dev;
5405         np->oom_kick.function = nv_do_rx_refill;        /* timer handler */
5406         init_timer(&np->nic_poll);
5407         np->nic_poll.data = (unsigned long) dev;
5408         np->nic_poll.function = nv_do_nic_poll; /* timer handler */
5409         init_timer(&np->stats_poll);
5410         np->stats_poll.data = (unsigned long) dev;
5411         np->stats_poll.function = nv_do_stats_poll;     /* timer handler */
5412
5413         err = pci_enable_device(pci_dev);
5414         if (err)
5415                 goto out_free;
5416
5417         pci_set_master(pci_dev);
5418
5419         err = pci_request_regions(pci_dev, DRV_NAME);
5420         if (err < 0)
5421                 goto out_disable;
5422
5423         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5424                 np->register_size = NV_PCI_REGSZ_VER3;
5425         else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5426                 np->register_size = NV_PCI_REGSZ_VER2;
5427         else
5428                 np->register_size = NV_PCI_REGSZ_VER1;
5429
5430         err = -EINVAL;
5431         addr = 0;
5432         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5433                 netdev_dbg(dev, "%s: resource %d start %p len %lld flags 0x%08lx\n",
5434                            pci_name(pci_dev), i,
5435                            (void *)(unsigned long)pci_resource_start(pci_dev, i),
5436                            (long long)pci_resource_len(pci_dev, i),
5437                            pci_resource_flags(pci_dev, i));
5438                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5439                                 pci_resource_len(pci_dev, i) >= np->register_size) {
5440                         addr = pci_resource_start(pci_dev, i);
5441                         break;
5442                 }
5443         }
5444         if (i == DEVICE_COUNT_RESOURCE) {
5445                 dev_printk(KERN_INFO, &pci_dev->dev,
5446                            "Couldn't find register window\n");
5447                 goto out_relreg;
5448         }
5449
5450         /* copy of driver data */
5451         np->driver_data = id->driver_data;
5452         /* copy of device id */
5453         np->device_id = id->device;
5454
5455         /* handle different descriptor versions */
5456         if (id->driver_data & DEV_HAS_HIGH_DMA) {
5457                 /* packet format 3: supports 40-bit addressing */
5458                 np->desc_ver = DESC_VER_3;
5459                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5460                 if (dma_64bit) {
5461                         if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
5462                                 dev_printk(KERN_INFO, &pci_dev->dev,
5463                                         "64-bit DMA failed, using 32-bit addressing\n");
5464                         else
5465                                 dev->features |= NETIF_F_HIGHDMA;
5466                         if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
5467                                 dev_printk(KERN_INFO, &pci_dev->dev,
5468                                         "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5469                         }
5470                 }
5471         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5472                 /* packet format 2: supports jumbo frames */
5473                 np->desc_ver = DESC_VER_2;
5474                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5475         } else {
5476                 /* original packet format */
5477                 np->desc_ver = DESC_VER_1;
5478                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5479         }
5480
5481         np->pkt_limit = NV_PKTLIMIT_1;
5482         if (id->driver_data & DEV_HAS_LARGEDESC)
5483                 np->pkt_limit = NV_PKTLIMIT_2;
5484
5485         if (id->driver_data & DEV_HAS_CHECKSUM) {
5486                 np->rx_csum = 1;
5487                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5488                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
5489                 dev->features |= NETIF_F_TSO;
5490                 dev->features |= NETIF_F_GRO;
5491         }
5492
5493         np->vlanctl_bits = 0;
5494         if (id->driver_data & DEV_HAS_VLAN) {
5495                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5496                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5497         }
5498
5499         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5500         if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5501             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5502             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5503                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5504         }
5505
5506
5507         err = -ENOMEM;
5508         np->base = ioremap(addr, np->register_size);
5509         if (!np->base)
5510                 goto out_relreg;
5511         dev->base_addr = (unsigned long)np->base;
5512
5513         dev->irq = pci_dev->irq;
5514
5515         np->rx_ring_size = RX_RING_DEFAULT;
5516         np->tx_ring_size = TX_RING_DEFAULT;
5517
5518         if (!nv_optimized(np)) {
5519                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5520                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5521                                         &np->ring_addr);
5522                 if (!np->rx_ring.orig)
5523                         goto out_unmap;
5524                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5525         } else {
5526                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5527                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5528                                         &np->ring_addr);
5529                 if (!np->rx_ring.ex)
5530                         goto out_unmap;
5531                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5532         }
5533         np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5534         np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5535         if (!np->rx_skb || !np->tx_skb)
5536                 goto out_freering;
5537
5538         if (!nv_optimized(np))
5539                 dev->netdev_ops = &nv_netdev_ops;
5540         else
5541                 dev->netdev_ops = &nv_netdev_ops_optimized;
5542
5543         netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5544         SET_ETHTOOL_OPS(dev, &ops);
5545         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5546
5547         pci_set_drvdata(pci_dev, dev);
5548
5549         /* read the mac address */
5550         base = get_hwbase(dev);
5551         np->orig_mac[0] = readl(base + NvRegMacAddrA);
5552         np->orig_mac[1] = readl(base + NvRegMacAddrB);
5553
5554         /* check the workaround bit for correct mac address order */
5555         txreg = readl(base + NvRegTransmitPoll);
5556         if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5557                 /* mac address is already in correct order */
5558                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5559                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5560                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5561                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5562                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5563                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5564         } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5565                 /* mac address is already in correct order */
5566                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5567                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5568                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5569                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5570                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5571                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5572                 /*
5573                  * Set orig mac address back to the reversed version.
5574                  * This flag will be cleared during low power transition.
5575                  * Therefore, we should always put back the reversed address.
5576                  */
5577                 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5578                         (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5579                 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5580         } else {
5581                 /* need to reverse mac address to correct order */
5582                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
5583                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
5584                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5585                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5586                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
5587                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
5588                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5589                 printk(KERN_DEBUG "nv_probe: set workaround bit for reversed mac addr\n");
5590         }
5591         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5592
5593         if (!is_valid_ether_addr(dev->perm_addr)) {
5594                 /*
5595                  * Bad mac address. At least one bios sets the mac address
5596                  * to 01:23:45:67:89:ab
5597                  */
5598                 dev_printk(KERN_ERR, &pci_dev->dev,
5599                         "Invalid Mac address detected: %pM\n",
5600                         dev->dev_addr);
5601                 dev_printk(KERN_ERR, &pci_dev->dev,
5602                         "Please complain to your hardware vendor. Switching to a random MAC.\n");
5603                 random_ether_addr(dev->dev_addr);
5604         }
5605
5606         netdev_dbg(dev, "%s: MAC Address %pM\n",
5607                    pci_name(pci_dev), dev->dev_addr);
5608
5609         /* set mac address */
5610         nv_copy_mac_to_hw(dev);
5611
5612         /* Workaround current PCI init glitch:  wakeup bits aren't
5613          * being set from PCI PM capability.
5614          */
5615         device_init_wakeup(&pci_dev->dev, 1);
5616
5617         /* disable WOL */
5618         writel(0, base + NvRegWakeUpFlags);
5619         np->wolenabled = 0;
5620
5621         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5622
5623                 /* take phy and nic out of low power mode */
5624                 powerstate = readl(base + NvRegPowerState2);
5625                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5626                 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
5627                     pci_dev->revision >= 0xA3)
5628                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5629                 writel(powerstate, base + NvRegPowerState2);
5630         }
5631
5632         if (np->desc_ver == DESC_VER_1)
5633                 np->tx_flags = NV_TX_VALID;
5634         else
5635                 np->tx_flags = NV_TX2_VALID;
5636
5637         np->msi_flags = 0;
5638         if ((id->driver_data & DEV_HAS_MSI) && msi)
5639                 np->msi_flags |= NV_MSI_CAPABLE;
5640
5641         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5642                 /* msix has had reported issues when modifying irqmask
5643                    as in the case of napi, therefore, disable for now
5644                 */
5645 #if 0
5646                 np->msi_flags |= NV_MSI_X_CAPABLE;
5647 #endif
5648         }
5649
5650         if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
5651                 np->irqmask = NVREG_IRQMASK_CPU;
5652                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5653                         np->msi_flags |= 0x0001;
5654         } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5655                    !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5656                 /* start off in throughput mode */
5657                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5658                 /* remove support for msix mode */
5659                 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5660         } else {
5661                 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5662                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5663                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5664                         np->msi_flags |= 0x0003;
5665         }
5666
5667         if (id->driver_data & DEV_NEED_TIMERIRQ)
5668                 np->irqmask |= NVREG_IRQ_TIMER;
5669         if (id->driver_data & DEV_NEED_LINKTIMER) {
5670                 netdev_dbg(dev, "%s: link timer on\n", pci_name(pci_dev));
5671                 np->need_linktimer = 1;
5672                 np->link_timeout = jiffies + LINK_TIMEOUT;
5673         } else {
5674                 netdev_dbg(dev, "%s: link timer off\n", pci_name(pci_dev));
5675                 np->need_linktimer = 0;
5676         }
5677
5678         /* Limit the number of tx's outstanding for hw bug */
5679         if (id->driver_data & DEV_NEED_TX_LIMIT) {
5680                 np->tx_limit = 1;
5681                 if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) &&
5682                     pci_dev->revision >= 0xA2)
5683                         np->tx_limit = 0;
5684         }
5685
5686         /* clear phy state and temporarily halt phy interrupts */
5687         writel(0, base + NvRegMIIMask);
5688         phystate = readl(base + NvRegAdapterControl);
5689         if (phystate & NVREG_ADAPTCTL_RUNNING) {
5690                 phystate_orig = 1;
5691                 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5692                 writel(phystate, base + NvRegAdapterControl);
5693         }
5694         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5695
5696         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5697                 /* management unit running on the mac? */
5698                 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5699                     (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5700                     nv_mgmt_acquire_sema(dev) &&
5701                     nv_mgmt_get_version(dev)) {
5702                         np->mac_in_use = 1;
5703                         if (np->mgmt_version > 0)
5704                                 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
5705                         netdev_dbg(dev, "%s: mgmt unit is running. mac in use %x\n",
5706                                    pci_name(pci_dev), np->mac_in_use);
5707                         /* management unit setup the phy already? */
5708                         if (np->mac_in_use &&
5709                             ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5710                              NVREG_XMITCTL_SYNC_PHY_INIT)) {
5711                                 /* phy is inited by mgmt unit */
5712                                 phyinitialized = 1;
5713                                 netdev_dbg(dev, "%s: Phy already initialized by mgmt unit\n",
5714                                            pci_name(pci_dev));
5715                         } else {
5716                                 /* we need to init the phy */
5717                         }
5718                 }
5719         }
5720
5721         /* find a suitable phy */
5722         for (i = 1; i <= 32; i++) {
5723                 int id1, id2;
5724                 int phyaddr = i & 0x1F;
5725
5726                 spin_lock_irq(&np->lock);
5727                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5728                 spin_unlock_irq(&np->lock);
5729                 if (id1 < 0 || id1 == 0xffff)
5730                         continue;
5731                 spin_lock_irq(&np->lock);
5732                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5733                 spin_unlock_irq(&np->lock);
5734                 if (id2 < 0 || id2 == 0xffff)
5735                         continue;
5736
5737                 np->phy_model = id2 & PHYID2_MODEL_MASK;
5738                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5739                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5740                 netdev_dbg(dev, "%s: %s: Found PHY %04x:%04x at address %d\n",
5741                            pci_name(pci_dev), __func__, id1, id2, phyaddr);
5742                 np->phyaddr = phyaddr;
5743                 np->phy_oui = id1 | id2;
5744
5745                 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5746                 if (np->phy_oui == PHY_OUI_REALTEK2)
5747                         np->phy_oui = PHY_OUI_REALTEK;
5748                 /* Setup phy revision for Realtek */
5749                 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5750                         np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5751
5752                 break;
5753         }
5754         if (i == 33) {
5755                 dev_printk(KERN_INFO, &pci_dev->dev,
5756                         "open: Could not find a valid PHY.\n");
5757                 goto out_error;
5758         }
5759
5760         if (!phyinitialized) {
5761                 /* reset it */
5762                 phy_init(dev);
5763         } else {
5764                 /* see if it is a gigabit phy */
5765                 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5766                 if (mii_status & PHY_GIGABIT)
5767                         np->gigabit = PHY_GIGABIT;
5768         }
5769
5770         /* set default link speed settings */
5771         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5772         np->duplex = 0;
5773         np->autoneg = 1;
5774
5775         err = register_netdev(dev);
5776         if (err) {
5777                 dev_printk(KERN_INFO, &pci_dev->dev,
5778                            "unable to register netdev: %d\n", err);
5779                 goto out_error;
5780         }
5781
5782         dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, "
5783                    "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
5784                    dev->name,
5785                    np->phy_oui,
5786                    np->phyaddr,
5787                    dev->dev_addr[0],
5788                    dev->dev_addr[1],
5789                    dev->dev_addr[2],
5790                    dev->dev_addr[3],
5791                    dev->dev_addr[4],
5792                    dev->dev_addr[5]);
5793
5794         dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5795                 dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5796                 dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
5797                         "csum " : "",
5798                 dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5799                         "vlan " : "",
5800                 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5801                 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5802                 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5803                 np->gigabit == PHY_GIGABIT ? "gbit " : "",
5804                 np->need_linktimer ? "lnktim " : "",
5805                 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5806                 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5807                 np->desc_ver);
5808
5809         return 0;
5810
5811 out_error:
5812         if (phystate_orig)
5813                 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5814         pci_set_drvdata(pci_dev, NULL);
5815 out_freering:
5816         free_rings(dev);
5817 out_unmap:
5818         iounmap(get_hwbase(dev));
5819 out_relreg:
5820         pci_release_regions(pci_dev);
5821 out_disable:
5822         pci_disable_device(pci_dev);
5823 out_free:
5824         free_netdev(dev);
5825 out:
5826         return err;
5827 }
5828
5829 static void nv_restore_phy(struct net_device *dev)
5830 {
5831         struct fe_priv *np = netdev_priv(dev);
5832         u16 phy_reserved, mii_control;
5833
5834         if (np->phy_oui == PHY_OUI_REALTEK &&
5835             np->phy_model == PHY_MODEL_REALTEK_8201 &&
5836             phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
5837                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
5838                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
5839                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
5840                 phy_reserved |= PHY_REALTEK_INIT8;
5841                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
5842                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
5843
5844                 /* restart auto negotiation */
5845                 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
5846                 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
5847                 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
5848         }
5849 }
5850
5851 static void nv_restore_mac_addr(struct pci_dev *pci_dev)
5852 {
5853         struct net_device *dev = pci_get_drvdata(pci_dev);
5854         struct fe_priv *np = netdev_priv(dev);
5855         u8 __iomem *base = get_hwbase(dev);
5856
5857         /* special op: write back the misordered MAC address - otherwise
5858          * the next nv_probe would see a wrong address.
5859          */
5860         writel(np->orig_mac[0], base + NvRegMacAddrA);
5861         writel(np->orig_mac[1], base + NvRegMacAddrB);
5862         writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5863                base + NvRegTransmitPoll);
5864 }
5865
5866 static void __devexit nv_remove(struct pci_dev *pci_dev)
5867 {
5868         struct net_device *dev = pci_get_drvdata(pci_dev);
5869
5870         unregister_netdev(dev);
5871
5872         nv_restore_mac_addr(pci_dev);
5873
5874         /* restore any phy related changes */
5875         nv_restore_phy(dev);
5876
5877         nv_mgmt_release_sema(dev);
5878
5879         /* free all structures */
5880         free_rings(dev);
5881         iounmap(get_hwbase(dev));
5882         pci_release_regions(pci_dev);
5883         pci_disable_device(pci_dev);
5884         free_netdev(dev);
5885         pci_set_drvdata(pci_dev, NULL);
5886 }
5887
5888 #ifdef CONFIG_PM
5889 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
5890 {
5891         struct net_device *dev = pci_get_drvdata(pdev);
5892         struct fe_priv *np = netdev_priv(dev);
5893         u8 __iomem *base = get_hwbase(dev);
5894         int i;
5895
5896         if (netif_running(dev)) {
5897                 /* Gross. */
5898                 nv_close(dev);
5899         }
5900         netif_device_detach(dev);
5901
5902         /* save non-pci configuration space */
5903         for (i = 0; i <= np->register_size/sizeof(u32); i++)
5904                 np->saved_config_space[i] = readl(base + i*sizeof(u32));
5905
5906         pci_save_state(pdev);
5907         pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
5908         pci_disable_device(pdev);
5909         pci_set_power_state(pdev, pci_choose_state(pdev, state));
5910         return 0;
5911 }
5912
5913 static int nv_resume(struct pci_dev *pdev)
5914 {
5915         struct net_device *dev = pci_get_drvdata(pdev);
5916         struct fe_priv *np = netdev_priv(dev);
5917         u8 __iomem *base = get_hwbase(dev);
5918         int i, rc = 0;
5919
5920         pci_set_power_state(pdev, PCI_D0);
5921         pci_restore_state(pdev);
5922         /* ack any pending wake events, disable PME */
5923         pci_enable_wake(pdev, PCI_D0, 0);
5924
5925         /* restore non-pci configuration space */
5926         for (i = 0; i <= np->register_size/sizeof(u32); i++)
5927                 writel(np->saved_config_space[i], base+i*sizeof(u32));
5928
5929         if (np->driver_data & DEV_NEED_MSI_FIX)
5930                 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
5931
5932         /* restore phy state, including autoneg */
5933         phy_init(dev);
5934
5935         netif_device_attach(dev);
5936         if (netif_running(dev)) {
5937                 rc = nv_open(dev);
5938                 nv_set_multicast(dev);
5939         }
5940         return rc;
5941 }
5942
5943 static void nv_shutdown(struct pci_dev *pdev)
5944 {
5945         struct net_device *dev = pci_get_drvdata(pdev);
5946         struct fe_priv *np = netdev_priv(dev);
5947
5948         if (netif_running(dev))
5949                 nv_close(dev);
5950
5951         /*
5952          * Restore the MAC so a kernel started by kexec won't get confused.
5953          * If we really go for poweroff, we must not restore the MAC,
5954          * otherwise the MAC for WOL will be reversed at least on some boards.
5955          */
5956         if (system_state != SYSTEM_POWER_OFF)
5957                 nv_restore_mac_addr(pdev);
5958
5959         pci_disable_device(pdev);
5960         /*
5961          * Apparently it is not possible to reinitialise from D3 hot,
5962          * only put the device into D3 if we really go for poweroff.
5963          */
5964         if (system_state == SYSTEM_POWER_OFF) {
5965                 if (pci_enable_wake(pdev, PCI_D3cold, np->wolenabled))
5966                         pci_enable_wake(pdev, PCI_D3hot, np->wolenabled);
5967                 pci_set_power_state(pdev, PCI_D3hot);
5968         }
5969 }
5970 #else
5971 #define nv_suspend NULL
5972 #define nv_shutdown NULL
5973 #define nv_resume NULL
5974 #endif /* CONFIG_PM */
5975
5976 static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
5977         {       /* nForce Ethernet Controller */
5978                 PCI_DEVICE(0x10DE, 0x01C3),
5979                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5980         },
5981         {       /* nForce2 Ethernet Controller */
5982                 PCI_DEVICE(0x10DE, 0x0066),
5983                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5984         },
5985         {       /* nForce3 Ethernet Controller */
5986                 PCI_DEVICE(0x10DE, 0x00D6),
5987                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5988         },
5989         {       /* nForce3 Ethernet Controller */
5990                 PCI_DEVICE(0x10DE, 0x0086),
5991                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5992         },
5993         {       /* nForce3 Ethernet Controller */
5994                 PCI_DEVICE(0x10DE, 0x008C),
5995                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5996         },
5997         {       /* nForce3 Ethernet Controller */
5998                 PCI_DEVICE(0x10DE, 0x00E6),
5999                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6000         },
6001         {       /* nForce3 Ethernet Controller */
6002                 PCI_DEVICE(0x10DE, 0x00DF),
6003                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6004         },
6005         {       /* CK804 Ethernet Controller */
6006                 PCI_DEVICE(0x10DE, 0x0056),
6007                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6008         },
6009         {       /* CK804 Ethernet Controller */
6010                 PCI_DEVICE(0x10DE, 0x0057),
6011                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6012         },
6013         {       /* MCP04 Ethernet Controller */
6014                 PCI_DEVICE(0x10DE, 0x0037),
6015                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6016         },
6017         {       /* MCP04 Ethernet Controller */
6018                 PCI_DEVICE(0x10DE, 0x0038),
6019                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6020         },
6021         {       /* MCP51 Ethernet Controller */
6022                 PCI_DEVICE(0x10DE, 0x0268),
6023                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6024         },
6025         {       /* MCP51 Ethernet Controller */
6026                 PCI_DEVICE(0x10DE, 0x0269),
6027                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6028         },
6029         {       /* MCP55 Ethernet Controller */
6030                 PCI_DEVICE(0x10DE, 0x0372),
6031                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6032         },
6033         {       /* MCP55 Ethernet Controller */
6034                 PCI_DEVICE(0x10DE, 0x0373),
6035                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6036         },
6037         {       /* MCP61 Ethernet Controller */
6038                 PCI_DEVICE(0x10DE, 0x03E5),
6039                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6040         },
6041         {       /* MCP61 Ethernet Controller */
6042                 PCI_DEVICE(0x10DE, 0x03E6),
6043                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6044         },
6045         {       /* MCP61 Ethernet Controller */
6046                 PCI_DEVICE(0x10DE, 0x03EE),
6047                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6048         },
6049         {       /* MCP61 Ethernet Controller */
6050                 PCI_DEVICE(0x10DE, 0x03EF),
6051                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6052         },
6053         {       /* MCP65 Ethernet Controller */
6054                 PCI_DEVICE(0x10DE, 0x0450),
6055                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6056         },
6057         {       /* MCP65 Ethernet Controller */
6058                 PCI_DEVICE(0x10DE, 0x0451),
6059                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6060         },
6061         {       /* MCP65 Ethernet Controller */
6062                 PCI_DEVICE(0x10DE, 0x0452),
6063                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6064         },
6065         {       /* MCP65 Ethernet Controller */
6066                 PCI_DEVICE(0x10DE, 0x0453),
6067                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6068         },
6069         {       /* MCP67 Ethernet Controller */
6070                 PCI_DEVICE(0x10DE, 0x054C),
6071                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6072         },
6073         {       /* MCP67 Ethernet Controller */
6074                 PCI_DEVICE(0x10DE, 0x054D),
6075                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6076         },
6077         {       /* MCP67 Ethernet Controller */
6078                 PCI_DEVICE(0x10DE, 0x054E),
6079                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6080         },
6081         {       /* MCP67 Ethernet Controller */
6082                 PCI_DEVICE(0x10DE, 0x054F),
6083                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6084         },
6085         {       /* MCP73 Ethernet Controller */
6086                 PCI_DEVICE(0x10DE, 0x07DC),
6087                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6088         },
6089         {       /* MCP73 Ethernet Controller */
6090                 PCI_DEVICE(0x10DE, 0x07DD),
6091                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6092         },
6093         {       /* MCP73 Ethernet Controller */
6094                 PCI_DEVICE(0x10DE, 0x07DE),
6095                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6096         },
6097         {       /* MCP73 Ethernet Controller */
6098                 PCI_DEVICE(0x10DE, 0x07DF),
6099                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6100         },
6101         {       /* MCP77 Ethernet Controller */
6102                 PCI_DEVICE(0x10DE, 0x0760),
6103                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6104         },
6105         {       /* MCP77 Ethernet Controller */
6106                 PCI_DEVICE(0x10DE, 0x0761),
6107                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6108         },
6109         {       /* MCP77 Ethernet Controller */
6110                 PCI_DEVICE(0x10DE, 0x0762),
6111                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6112         },
6113         {       /* MCP77 Ethernet Controller */
6114                 PCI_DEVICE(0x10DE, 0x0763),
6115                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6116         },
6117         {       /* MCP79 Ethernet Controller */
6118                 PCI_DEVICE(0x10DE, 0x0AB0),
6119                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6120         },
6121         {       /* MCP79 Ethernet Controller */
6122                 PCI_DEVICE(0x10DE, 0x0AB1),
6123                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6124         },
6125         {       /* MCP79 Ethernet Controller */
6126                 PCI_DEVICE(0x10DE, 0x0AB2),
6127                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6128         },
6129         {       /* MCP79 Ethernet Controller */
6130                 PCI_DEVICE(0x10DE, 0x0AB3),
6131                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6132         },
6133         {       /* MCP89 Ethernet Controller */
6134                 PCI_DEVICE(0x10DE, 0x0D7D),
6135                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
6136         },
6137         {0,},
6138 };
6139
6140 static struct pci_driver driver = {
6141         .name           = DRV_NAME,
6142         .id_table       = pci_tbl,
6143         .probe          = nv_probe,
6144         .remove         = __devexit_p(nv_remove),
6145         .suspend        = nv_suspend,
6146         .resume         = nv_resume,
6147         .shutdown       = nv_shutdown,
6148 };
6149
6150 static int __init init_nic(void)
6151 {
6152         return pci_register_driver(&driver);
6153 }
6154
6155 static void __exit exit_nic(void)
6156 {
6157         pci_unregister_driver(&driver);
6158 }
6159
6160 module_param(max_interrupt_work, int, 0);
6161 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
6162 module_param(optimization_mode, int, 0);
6163 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
6164 module_param(poll_interval, int, 0);
6165 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6166 module_param(msi, int, 0);
6167 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6168 module_param(msix, int, 0);
6169 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6170 module_param(dma_64bit, int, 0);
6171 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6172 module_param(phy_cross, int, 0);
6173 MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6174 module_param(phy_power_down, int, 0);
6175 MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6176
6177 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6178 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6179 MODULE_LICENSE("GPL");
6180
6181 MODULE_DEVICE_TABLE(pci, pci_tbl);
6182
6183 module_init(init_nic);
6184 module_exit(exit_nic);