2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/pci.h>
33 #include <linux/init.h>
34 #include <linux/delay.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
38 #include <linux/spinlock.h>
39 #include <linux/workqueue.h>
40 #include <linux/bitops.h>
42 #include <linux/irq.h>
43 #include <linux/clk.h>
44 #include <linux/platform_device.h>
45 #include <linux/phy.h>
46 #include <linux/fec.h>
48 #include <asm/cacheflush.h>
51 #include <asm/coldfire.h>
52 #include <asm/mcfsim.h>
57 #if defined(CONFIG_ARM)
58 #define FEC_ALIGNMENT 0xf
60 #define FEC_ALIGNMENT 0x3
63 #define DRIVER_NAME "fec"
65 /* Controller is ENET-MAC */
66 #define FEC_QUIRK_ENET_MAC (1 << 0)
67 /* Controller needs driver to swap frame */
68 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
69 /* Controller uses gasket */
70 #define FEC_QUIRK_USE_GASKET (1 << 2)
72 static struct platform_device_id fec_devtype[] = {
74 /* keep it for coldfire */
79 .driver_data = FEC_QUIRK_USE_GASKET,
85 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
90 MODULE_DEVICE_TABLE(platform, fec_devtype);
92 static unsigned char macaddr[ETH_ALEN];
93 module_param_array(macaddr, byte, NULL, 0);
94 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
96 #if defined(CONFIG_M5272)
98 * Some hardware gets it MAC address out of local flash memory.
99 * if this is non-zero then assume it is the address to get MAC from.
101 #if defined(CONFIG_NETtel)
102 #define FEC_FLASHMAC 0xf0006006
103 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
104 #define FEC_FLASHMAC 0xf0006000
105 #elif defined(CONFIG_CANCam)
106 #define FEC_FLASHMAC 0xf0020000
107 #elif defined (CONFIG_M5272C3)
108 #define FEC_FLASHMAC (0xffe04000 + 4)
109 #elif defined(CONFIG_MOD5272)
110 #define FEC_FLASHMAC 0xffc0406b
112 #define FEC_FLASHMAC 0
114 #endif /* CONFIG_M5272 */
116 /* The number of Tx and Rx buffers. These are allocated from the page
117 * pool. The code may assume these are power of two, so it it best
118 * to keep them that size.
119 * We don't need to allocate pages for the transmitter. We just use
120 * the skbuffer directly.
122 #define FEC_ENET_RX_PAGES 8
123 #define FEC_ENET_RX_FRSIZE 2048
124 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
125 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
126 #define FEC_ENET_TX_FRSIZE 2048
127 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
128 #define TX_RING_SIZE 16 /* Must be power of two */
129 #define TX_RING_MOD_MASK 15 /* for this to work */
131 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
132 #error "FEC: descriptor ring size constants too large"
135 /* Interrupt events/masks. */
136 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
137 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
138 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
139 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
140 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
141 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
142 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
143 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
144 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
145 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
147 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
149 /* The FEC stores dest/src/type, data, and checksum for receive packets.
151 #define PKT_MAXBUF_SIZE 1518
152 #define PKT_MINBUF_SIZE 64
153 #define PKT_MAXBLR_SIZE 1520
157 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
158 * size bits. Other FEC hardware does not, so we need to take that into
159 * account when setting it.
161 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
162 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
163 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
165 #define OPT_FRAME_SIZE 0
168 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
169 * tx_bd_base always point to the base of the buffer descriptors. The
170 * cur_rx and cur_tx point to the currently available buffer.
171 * The dirty_tx tracks the current buffer that is being sent by the
172 * controller. The cur_tx and dirty_tx are equal under both completely
173 * empty and completely full conditions. The empty/ready indicator in
174 * the buffer descriptor determines the actual condition.
176 struct fec_enet_private {
177 /* Hardware registers of the FEC device */
180 struct net_device *netdev;
184 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
185 unsigned char *tx_bounce[TX_RING_SIZE];
186 struct sk_buff* tx_skbuff[TX_RING_SIZE];
187 struct sk_buff* rx_skbuff[RX_RING_SIZE];
191 /* CPM dual port RAM relative addresses */
193 /* Address of Rx and Tx buffers */
194 struct bufdesc *rx_bd_base;
195 struct bufdesc *tx_bd_base;
196 /* The next free ring entry */
197 struct bufdesc *cur_rx, *cur_tx;
198 /* The ring entries to be free()ed */
199 struct bufdesc *dirty_tx;
202 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
205 struct platform_device *pdev;
209 /* Phylib and MDIO interface */
210 struct mii_bus *mii_bus;
211 struct phy_device *phy_dev;
214 phy_interface_t phy_interface;
217 struct completion mdio_done;
220 /* FEC MII MMFR bits definition */
221 #define FEC_MMFR_ST (1 << 30)
222 #define FEC_MMFR_OP_READ (2 << 28)
223 #define FEC_MMFR_OP_WRITE (1 << 28)
224 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
225 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
226 #define FEC_MMFR_TA (2 << 16)
227 #define FEC_MMFR_DATA(v) (v & 0xffff)
229 #define FEC_MII_TIMEOUT 1000 /* us */
231 /* Transmitter timeout */
232 #define TX_TIMEOUT (2 * HZ)
234 static void *swap_buffer(void *bufaddr, int len)
237 unsigned int *buf = bufaddr;
239 for (i = 0; i < (len + 3) / 4; i++, buf++)
240 *buf = cpu_to_be32(*buf);
246 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
248 struct fec_enet_private *fep = netdev_priv(ndev);
249 const struct platform_device_id *id_entry =
250 platform_get_device_id(fep->pdev);
253 unsigned short status;
257 /* Link is down or autonegotiation is in progress. */
258 return NETDEV_TX_BUSY;
261 spin_lock_irqsave(&fep->hw_lock, flags);
262 /* Fill in a Tx ring entry */
265 status = bdp->cbd_sc;
267 if (status & BD_ENET_TX_READY) {
268 /* Ooops. All transmit buffers are full. Bail out.
269 * This should not happen, since ndev->tbusy should be set.
271 printk("%s: tx queue full!.\n", ndev->name);
272 spin_unlock_irqrestore(&fep->hw_lock, flags);
273 return NETDEV_TX_BUSY;
276 /* Clear all of the status flags */
277 status &= ~BD_ENET_TX_STATS;
279 /* Set buffer length and buffer pointer */
281 bdp->cbd_datlen = skb->len;
284 * On some FEC implementations data must be aligned on
285 * 4-byte boundaries. Use bounce buffers to copy data
286 * and get it aligned. Ugh.
288 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
290 index = bdp - fep->tx_bd_base;
291 memcpy(fep->tx_bounce[index], skb->data, skb->len);
292 bufaddr = fep->tx_bounce[index];
296 * Some design made an incorrect assumption on endian mode of
297 * the system that it's running on. As the result, driver has to
298 * swap every frame going to and coming from the controller.
300 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
301 swap_buffer(bufaddr, skb->len);
303 /* Save skb pointer */
304 fep->tx_skbuff[fep->skb_cur] = skb;
306 ndev->stats.tx_bytes += skb->len;
307 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
309 /* Push the data cache so the CPM does not get stale memory
312 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
313 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
315 /* Send it on its way. Tell FEC it's ready, interrupt when done,
316 * it's the last BD of the frame, and to put the CRC on the end.
318 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
319 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
320 bdp->cbd_sc = status;
322 /* Trigger transmission start */
323 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
325 /* If this was the last BD in the ring, start at the beginning again. */
326 if (status & BD_ENET_TX_WRAP)
327 bdp = fep->tx_bd_base;
331 if (bdp == fep->dirty_tx) {
333 netif_stop_queue(ndev);
338 skb_tx_timestamp(skb);
340 spin_unlock_irqrestore(&fep->hw_lock, flags);
345 /* This function is called to start or restart the FEC during a link
346 * change. This only happens when switching between half and full
350 fec_restart(struct net_device *ndev, int duplex)
352 struct fec_enet_private *fep = netdev_priv(ndev);
353 const struct platform_device_id *id_entry =
354 platform_get_device_id(fep->pdev);
357 u32 rcntl = OPT_FRAME_SIZE | 0x04;
359 /* Whack a reset. We should wait for this. */
360 writel(1, fep->hwp + FEC_ECNTRL);
364 * enet-mac reset will reset mac address registers too,
365 * so need to reconfigure it.
367 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
368 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
369 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
370 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
373 /* Clear any outstanding interrupt. */
374 writel(0xffc00000, fep->hwp + FEC_IEVENT);
376 /* Reset all multicast. */
377 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
378 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
380 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
381 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
384 /* Set maximum receive buffer size. */
385 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
387 /* Set receive and transmit descriptor base. */
388 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
389 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE,
390 fep->hwp + FEC_X_DES_START);
392 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
393 fep->cur_rx = fep->rx_bd_base;
395 /* Reset SKB transmit buffers. */
396 fep->skb_cur = fep->skb_dirty = 0;
397 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
398 if (fep->tx_skbuff[i]) {
399 dev_kfree_skb_any(fep->tx_skbuff[i]);
400 fep->tx_skbuff[i] = NULL;
404 /* Enable MII mode */
407 writel(0x04, fep->hwp + FEC_X_CNTRL);
411 writel(0x0, fep->hwp + FEC_X_CNTRL);
414 fep->full_duplex = duplex;
417 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
420 * The phy interface and speed need to get configured
421 * differently on enet-mac.
423 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
424 /* Enable flow control and length check */
425 rcntl |= 0x40000000 | 0x00000020;
428 if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
434 if (fep->phy_dev && fep->phy_dev->speed == SPEED_100)
440 #ifdef FEC_MIIGSK_ENR
441 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
442 /* disable the gasket and wait */
443 writel(0, fep->hwp + FEC_MIIGSK_ENR);
444 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
448 * configure the gasket:
449 * RMII, 50 MHz, no loopback, no echo
450 * MII, 25 MHz, no loopback, no echo
452 writel((fep->phy_interface == PHY_INTERFACE_MODE_RMII) ?
453 1 : 0, fep->hwp + FEC_MIIGSK_CFGR);
456 /* re-enable the gasket */
457 writel(2, fep->hwp + FEC_MIIGSK_ENR);
461 writel(rcntl, fep->hwp + FEC_R_CNTRL);
463 /* And last, enable the transmit and receive processing */
464 writel(2, fep->hwp + FEC_ECNTRL);
465 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
467 /* Enable interrupts we wish to service */
468 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
472 fec_stop(struct net_device *ndev)
474 struct fec_enet_private *fep = netdev_priv(ndev);
476 /* We cannot expect a graceful transmit stop without link !!! */
478 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
480 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
481 printk("fec_stop : Graceful transmit stop did not complete !\n");
484 /* Whack a reset. We should wait for this. */
485 writel(1, fep->hwp + FEC_ECNTRL);
487 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
488 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
493 fec_timeout(struct net_device *ndev)
495 struct fec_enet_private *fep = netdev_priv(ndev);
497 ndev->stats.tx_errors++;
499 fec_restart(ndev, fep->full_duplex);
500 netif_wake_queue(ndev);
504 fec_enet_tx(struct net_device *ndev)
506 struct fec_enet_private *fep;
508 unsigned short status;
511 fep = netdev_priv(ndev);
512 spin_lock(&fep->hw_lock);
515 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
516 if (bdp == fep->cur_tx && fep->tx_full == 0)
519 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
520 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
521 bdp->cbd_bufaddr = 0;
523 skb = fep->tx_skbuff[fep->skb_dirty];
524 /* Check for errors. */
525 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
526 BD_ENET_TX_RL | BD_ENET_TX_UN |
528 ndev->stats.tx_errors++;
529 if (status & BD_ENET_TX_HB) /* No heartbeat */
530 ndev->stats.tx_heartbeat_errors++;
531 if (status & BD_ENET_TX_LC) /* Late collision */
532 ndev->stats.tx_window_errors++;
533 if (status & BD_ENET_TX_RL) /* Retrans limit */
534 ndev->stats.tx_aborted_errors++;
535 if (status & BD_ENET_TX_UN) /* Underrun */
536 ndev->stats.tx_fifo_errors++;
537 if (status & BD_ENET_TX_CSL) /* Carrier lost */
538 ndev->stats.tx_carrier_errors++;
540 ndev->stats.tx_packets++;
543 if (status & BD_ENET_TX_READY)
544 printk("HEY! Enet xmit interrupt and TX_READY.\n");
546 /* Deferred means some collisions occurred during transmit,
547 * but we eventually sent the packet OK.
549 if (status & BD_ENET_TX_DEF)
550 ndev->stats.collisions++;
552 /* Free the sk buffer associated with this last transmit */
553 dev_kfree_skb_any(skb);
554 fep->tx_skbuff[fep->skb_dirty] = NULL;
555 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
557 /* Update pointer to next buffer descriptor to be transmitted */
558 if (status & BD_ENET_TX_WRAP)
559 bdp = fep->tx_bd_base;
563 /* Since we have freed up a buffer, the ring is no longer full
567 if (netif_queue_stopped(ndev))
568 netif_wake_queue(ndev);
572 spin_unlock(&fep->hw_lock);
576 /* During a receive, the cur_rx points to the current incoming buffer.
577 * When we update through the ring, if the next incoming buffer has
578 * not been given to the system, we just set the empty indicator,
579 * effectively tossing the packet.
582 fec_enet_rx(struct net_device *ndev)
584 struct fec_enet_private *fep = netdev_priv(ndev);
585 const struct platform_device_id *id_entry =
586 platform_get_device_id(fep->pdev);
588 unsigned short status;
597 spin_lock(&fep->hw_lock);
599 /* First, grab all of the stats for the incoming packet.
600 * These get messed up if we get called due to a busy condition.
604 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
606 /* Since we have allocated space to hold a complete frame,
607 * the last indicator should be set.
609 if ((status & BD_ENET_RX_LAST) == 0)
610 printk("FEC ENET: rcv is not +last\n");
613 goto rx_processing_done;
615 /* Check for errors. */
616 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
617 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
618 ndev->stats.rx_errors++;
619 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
620 /* Frame too long or too short. */
621 ndev->stats.rx_length_errors++;
623 if (status & BD_ENET_RX_NO) /* Frame alignment */
624 ndev->stats.rx_frame_errors++;
625 if (status & BD_ENET_RX_CR) /* CRC Error */
626 ndev->stats.rx_crc_errors++;
627 if (status & BD_ENET_RX_OV) /* FIFO overrun */
628 ndev->stats.rx_fifo_errors++;
631 /* Report late collisions as a frame error.
632 * On this error, the BD is closed, but we don't know what we
633 * have in the buffer. So, just drop this frame on the floor.
635 if (status & BD_ENET_RX_CL) {
636 ndev->stats.rx_errors++;
637 ndev->stats.rx_frame_errors++;
638 goto rx_processing_done;
641 /* Process the incoming frame. */
642 ndev->stats.rx_packets++;
643 pkt_len = bdp->cbd_datlen;
644 ndev->stats.rx_bytes += pkt_len;
645 data = (__u8*)__va(bdp->cbd_bufaddr);
647 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
648 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
650 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
651 swap_buffer(data, pkt_len);
653 /* This does 16 byte alignment, exactly what we need.
654 * The packet length includes FCS, but we don't want to
655 * include that when passing upstream as it messes up
656 * bridging applications.
658 skb = dev_alloc_skb(pkt_len - 4 + NET_IP_ALIGN);
660 if (unlikely(!skb)) {
661 printk("%s: Memory squeeze, dropping packet.\n",
663 ndev->stats.rx_dropped++;
665 skb_reserve(skb, NET_IP_ALIGN);
666 skb_put(skb, pkt_len - 4); /* Make room */
667 skb_copy_to_linear_data(skb, data, pkt_len - 4);
668 skb->protocol = eth_type_trans(skb, ndev);
669 if (!skb_defer_rx_timestamp(skb))
673 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
674 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
676 /* Clear the status flags for this buffer */
677 status &= ~BD_ENET_RX_STATS;
679 /* Mark the buffer empty */
680 status |= BD_ENET_RX_EMPTY;
681 bdp->cbd_sc = status;
683 /* Update BD pointer to next entry */
684 if (status & BD_ENET_RX_WRAP)
685 bdp = fep->rx_bd_base;
688 /* Doing this here will keep the FEC running while we process
689 * incoming frames. On a heavily loaded network, we should be
690 * able to keep up at the expense of system resources.
692 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
696 spin_unlock(&fep->hw_lock);
700 fec_enet_interrupt(int irq, void *dev_id)
702 struct net_device *ndev = dev_id;
703 struct fec_enet_private *fep = netdev_priv(ndev);
705 irqreturn_t ret = IRQ_NONE;
708 int_events = readl(fep->hwp + FEC_IEVENT);
709 writel(int_events, fep->hwp + FEC_IEVENT);
711 if (int_events & FEC_ENET_RXF) {
716 /* Transmit OK, or non-fatal error. Update the buffer
717 * descriptors. FEC handles all errors, we just discover
718 * them as part of the transmit process.
720 if (int_events & FEC_ENET_TXF) {
725 if (int_events & FEC_ENET_MII) {
727 complete(&fep->mdio_done);
729 } while (int_events);
736 /* ------------------------------------------------------------------------- */
737 static void __inline__ fec_get_mac(struct net_device *ndev)
739 struct fec_enet_private *fep = netdev_priv(ndev);
740 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
741 unsigned char *iap, tmpaddr[ETH_ALEN];
744 * try to get mac address in following order:
746 * 1) module parameter via kernel command line in form
747 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
752 * 2) from flash or fuse (via platform data)
754 if (!is_valid_ether_addr(iap)) {
757 iap = (unsigned char *)FEC_FLASHMAC;
760 memcpy(iap, pdata->mac, ETH_ALEN);
765 * 3) FEC mac registers set by bootloader
767 if (!is_valid_ether_addr(iap)) {
768 *((unsigned long *) &tmpaddr[0]) =
769 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
770 *((unsigned short *) &tmpaddr[4]) =
771 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
775 memcpy(ndev->dev_addr, iap, ETH_ALEN);
777 /* Adjust MAC if using macaddr */
779 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->pdev->id;
782 /* ------------------------------------------------------------------------- */
787 static void fec_enet_adjust_link(struct net_device *ndev)
789 struct fec_enet_private *fep = netdev_priv(ndev);
790 struct phy_device *phy_dev = fep->phy_dev;
793 int status_change = 0;
795 spin_lock_irqsave(&fep->hw_lock, flags);
797 /* Prevent a state halted on mii error */
798 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
799 phy_dev->state = PHY_RESUMING;
803 /* Duplex link change */
805 if (fep->full_duplex != phy_dev->duplex) {
806 fec_restart(ndev, phy_dev->duplex);
811 /* Link on or off change */
812 if (phy_dev->link != fep->link) {
813 fep->link = phy_dev->link;
815 fec_restart(ndev, phy_dev->duplex);
822 spin_unlock_irqrestore(&fep->hw_lock, flags);
825 phy_print_status(phy_dev);
828 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
830 struct fec_enet_private *fep = bus->priv;
831 unsigned long time_left;
833 fep->mii_timeout = 0;
834 init_completion(&fep->mdio_done);
836 /* start a read op */
837 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
838 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
839 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
841 /* wait for end of transfer */
842 time_left = wait_for_completion_timeout(&fep->mdio_done,
843 usecs_to_jiffies(FEC_MII_TIMEOUT));
844 if (time_left == 0) {
845 fep->mii_timeout = 1;
846 printk(KERN_ERR "FEC: MDIO read timeout\n");
851 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
854 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
857 struct fec_enet_private *fep = bus->priv;
858 unsigned long time_left;
860 fep->mii_timeout = 0;
861 init_completion(&fep->mdio_done);
863 /* start a write op */
864 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
865 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
866 FEC_MMFR_TA | FEC_MMFR_DATA(value),
867 fep->hwp + FEC_MII_DATA);
869 /* wait for end of transfer */
870 time_left = wait_for_completion_timeout(&fep->mdio_done,
871 usecs_to_jiffies(FEC_MII_TIMEOUT));
872 if (time_left == 0) {
873 fep->mii_timeout = 1;
874 printk(KERN_ERR "FEC: MDIO write timeout\n");
881 static int fec_enet_mdio_reset(struct mii_bus *bus)
886 static int fec_enet_mii_probe(struct net_device *ndev)
888 struct fec_enet_private *fep = netdev_priv(ndev);
889 struct phy_device *phy_dev = NULL;
890 char mdio_bus_id[MII_BUS_ID_SIZE];
891 char phy_name[MII_BUS_ID_SIZE + 3];
893 int dev_id = fep->pdev->id;
897 /* check for attached phy */
898 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
899 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
901 if (fep->mii_bus->phy_map[phy_id] == NULL)
903 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
907 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
911 if (phy_id >= PHY_MAX_ADDR) {
912 printk(KERN_INFO "%s: no PHY, assuming direct connection "
913 "to switch\n", ndev->name);
914 strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE);
918 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id);
919 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 0,
920 PHY_INTERFACE_MODE_MII);
921 if (IS_ERR(phy_dev)) {
922 printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name);
923 return PTR_ERR(phy_dev);
926 /* mask with MAC supported features */
927 phy_dev->supported &= PHY_BASIC_FEATURES;
928 phy_dev->advertising = phy_dev->supported;
930 fep->phy_dev = phy_dev;
932 fep->full_duplex = 0;
934 printk(KERN_INFO "%s: Freescale FEC PHY driver [%s] "
935 "(mii_bus:phy_addr=%s, irq=%d)\n", ndev->name,
936 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
942 static int fec_enet_mii_init(struct platform_device *pdev)
944 static struct mii_bus *fec0_mii_bus;
945 struct net_device *ndev = platform_get_drvdata(pdev);
946 struct fec_enet_private *fep = netdev_priv(ndev);
947 const struct platform_device_id *id_entry =
948 platform_get_device_id(fep->pdev);
952 * The dual fec interfaces are not equivalent with enet-mac.
953 * Here are the differences:
955 * - fec0 supports MII & RMII modes while fec1 only supports RMII
956 * - fec0 acts as the 1588 time master while fec1 is slave
957 * - external phys can only be configured by fec0
959 * That is to say fec1 can not work independently. It only works
960 * when fec0 is working. The reason behind this design is that the
961 * second interface is added primarily for Switch mode.
963 * Because of the last point above, both phys are attached on fec0
964 * mdio interface in board design, and need to be configured by
967 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && pdev->id) {
968 /* fec1 uses fec0 mii_bus */
969 fep->mii_bus = fec0_mii_bus;
973 fep->mii_timeout = 0;
976 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
978 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1;
979 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
981 fep->mii_bus = mdiobus_alloc();
982 if (fep->mii_bus == NULL) {
987 fep->mii_bus->name = "fec_enet_mii_bus";
988 fep->mii_bus->read = fec_enet_mdio_read;
989 fep->mii_bus->write = fec_enet_mdio_write;
990 fep->mii_bus->reset = fec_enet_mdio_reset;
991 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id + 1);
992 fep->mii_bus->priv = fep;
993 fep->mii_bus->parent = &pdev->dev;
995 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
996 if (!fep->mii_bus->irq) {
998 goto err_out_free_mdiobus;
1001 for (i = 0; i < PHY_MAX_ADDR; i++)
1002 fep->mii_bus->irq[i] = PHY_POLL;
1004 if (mdiobus_register(fep->mii_bus))
1005 goto err_out_free_mdio_irq;
1007 /* save fec0 mii_bus */
1008 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1009 fec0_mii_bus = fep->mii_bus;
1013 err_out_free_mdio_irq:
1014 kfree(fep->mii_bus->irq);
1015 err_out_free_mdiobus:
1016 mdiobus_free(fep->mii_bus);
1021 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1024 phy_disconnect(fep->phy_dev);
1025 mdiobus_unregister(fep->mii_bus);
1026 kfree(fep->mii_bus->irq);
1027 mdiobus_free(fep->mii_bus);
1030 static int fec_enet_get_settings(struct net_device *ndev,
1031 struct ethtool_cmd *cmd)
1033 struct fec_enet_private *fep = netdev_priv(ndev);
1034 struct phy_device *phydev = fep->phy_dev;
1039 return phy_ethtool_gset(phydev, cmd);
1042 static int fec_enet_set_settings(struct net_device *ndev,
1043 struct ethtool_cmd *cmd)
1045 struct fec_enet_private *fep = netdev_priv(ndev);
1046 struct phy_device *phydev = fep->phy_dev;
1051 return phy_ethtool_sset(phydev, cmd);
1054 static void fec_enet_get_drvinfo(struct net_device *ndev,
1055 struct ethtool_drvinfo *info)
1057 struct fec_enet_private *fep = netdev_priv(ndev);
1059 strcpy(info->driver, fep->pdev->dev.driver->name);
1060 strcpy(info->version, "Revision: 1.0");
1061 strcpy(info->bus_info, dev_name(&ndev->dev));
1064 static struct ethtool_ops fec_enet_ethtool_ops = {
1065 .get_settings = fec_enet_get_settings,
1066 .set_settings = fec_enet_set_settings,
1067 .get_drvinfo = fec_enet_get_drvinfo,
1068 .get_link = ethtool_op_get_link,
1071 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1073 struct fec_enet_private *fep = netdev_priv(ndev);
1074 struct phy_device *phydev = fep->phy_dev;
1076 if (!netif_running(ndev))
1082 return phy_mii_ioctl(phydev, rq, cmd);
1085 static void fec_enet_free_buffers(struct net_device *ndev)
1087 struct fec_enet_private *fep = netdev_priv(ndev);
1089 struct sk_buff *skb;
1090 struct bufdesc *bdp;
1092 bdp = fep->rx_bd_base;
1093 for (i = 0; i < RX_RING_SIZE; i++) {
1094 skb = fep->rx_skbuff[i];
1096 if (bdp->cbd_bufaddr)
1097 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1098 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1104 bdp = fep->tx_bd_base;
1105 for (i = 0; i < TX_RING_SIZE; i++)
1106 kfree(fep->tx_bounce[i]);
1109 static int fec_enet_alloc_buffers(struct net_device *ndev)
1111 struct fec_enet_private *fep = netdev_priv(ndev);
1113 struct sk_buff *skb;
1114 struct bufdesc *bdp;
1116 bdp = fep->rx_bd_base;
1117 for (i = 0; i < RX_RING_SIZE; i++) {
1118 skb = dev_alloc_skb(FEC_ENET_RX_FRSIZE);
1120 fec_enet_free_buffers(ndev);
1123 fep->rx_skbuff[i] = skb;
1125 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1126 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1127 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1131 /* Set the last buffer to wrap. */
1133 bdp->cbd_sc |= BD_SC_WRAP;
1135 bdp = fep->tx_bd_base;
1136 for (i = 0; i < TX_RING_SIZE; i++) {
1137 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1140 bdp->cbd_bufaddr = 0;
1144 /* Set the last buffer to wrap. */
1146 bdp->cbd_sc |= BD_SC_WRAP;
1152 fec_enet_open(struct net_device *ndev)
1154 struct fec_enet_private *fep = netdev_priv(ndev);
1157 /* I should reset the ring buffers here, but I don't yet know
1158 * a simple way to do that.
1161 ret = fec_enet_alloc_buffers(ndev);
1165 /* Probe and connect to PHY when open the interface */
1166 ret = fec_enet_mii_probe(ndev);
1168 fec_enet_free_buffers(ndev);
1171 phy_start(fep->phy_dev);
1172 netif_start_queue(ndev);
1178 fec_enet_close(struct net_device *ndev)
1180 struct fec_enet_private *fep = netdev_priv(ndev);
1182 /* Don't know what to do yet. */
1184 netif_stop_queue(ndev);
1188 phy_stop(fep->phy_dev);
1189 phy_disconnect(fep->phy_dev);
1192 fec_enet_free_buffers(ndev);
1197 /* Set or clear the multicast filter for this adaptor.
1198 * Skeleton taken from sunlance driver.
1199 * The CPM Ethernet implementation allows Multicast as well as individual
1200 * MAC address filtering. Some of the drivers check to make sure it is
1201 * a group multicast address, and discard those that are not. I guess I
1202 * will do the same for now, but just remove the test if you want
1203 * individual filtering as well (do the upper net layers want or support
1204 * this kind of feature?).
1207 #define HASH_BITS 6 /* #bits in hash */
1208 #define CRC32_POLY 0xEDB88320
1210 static void set_multicast_list(struct net_device *ndev)
1212 struct fec_enet_private *fep = netdev_priv(ndev);
1213 struct netdev_hw_addr *ha;
1214 unsigned int i, bit, data, crc, tmp;
1217 if (ndev->flags & IFF_PROMISC) {
1218 tmp = readl(fep->hwp + FEC_R_CNTRL);
1220 writel(tmp, fep->hwp + FEC_R_CNTRL);
1224 tmp = readl(fep->hwp + FEC_R_CNTRL);
1226 writel(tmp, fep->hwp + FEC_R_CNTRL);
1228 if (ndev->flags & IFF_ALLMULTI) {
1229 /* Catch all multicast addresses, so set the
1232 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1233 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1238 /* Clear filter and add the addresses in hash register
1240 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1241 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1243 netdev_for_each_mc_addr(ha, ndev) {
1244 /* calculate crc32 value of mac address */
1247 for (i = 0; i < ndev->addr_len; i++) {
1249 for (bit = 0; bit < 8; bit++, data >>= 1) {
1251 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1255 /* only upper 6 bits (HASH_BITS) are used
1256 * which point to specific bit in he hash registers
1258 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1261 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1262 tmp |= 1 << (hash - 32);
1263 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1265 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1267 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1272 /* Set a MAC change in hardware. */
1274 fec_set_mac_address(struct net_device *ndev, void *p)
1276 struct fec_enet_private *fep = netdev_priv(ndev);
1277 struct sockaddr *addr = p;
1279 if (!is_valid_ether_addr(addr->sa_data))
1280 return -EADDRNOTAVAIL;
1282 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1284 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1285 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1286 fep->hwp + FEC_ADDR_LOW);
1287 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1288 fep->hwp + FEC_ADDR_HIGH);
1292 static const struct net_device_ops fec_netdev_ops = {
1293 .ndo_open = fec_enet_open,
1294 .ndo_stop = fec_enet_close,
1295 .ndo_start_xmit = fec_enet_start_xmit,
1296 .ndo_set_multicast_list = set_multicast_list,
1297 .ndo_change_mtu = eth_change_mtu,
1298 .ndo_validate_addr = eth_validate_addr,
1299 .ndo_tx_timeout = fec_timeout,
1300 .ndo_set_mac_address = fec_set_mac_address,
1301 .ndo_do_ioctl = fec_enet_ioctl,
1305 * XXX: We need to clean up on failure exits here.
1308 static int fec_enet_init(struct net_device *ndev)
1310 struct fec_enet_private *fep = netdev_priv(ndev);
1311 struct bufdesc *cbd_base;
1312 struct bufdesc *bdp;
1315 /* Allocate memory for buffer descriptors. */
1316 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1319 printk("FEC: allocate descriptor memory failed?\n");
1323 spin_lock_init(&fep->hw_lock);
1327 /* Get the Ethernet address */
1330 /* Set receive and transmit descriptor base. */
1331 fep->rx_bd_base = cbd_base;
1332 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1334 /* The FEC Ethernet specific entries in the device structure */
1335 ndev->watchdog_timeo = TX_TIMEOUT;
1336 ndev->netdev_ops = &fec_netdev_ops;
1337 ndev->ethtool_ops = &fec_enet_ethtool_ops;
1339 /* Initialize the receive buffer descriptors. */
1340 bdp = fep->rx_bd_base;
1341 for (i = 0; i < RX_RING_SIZE; i++) {
1343 /* Initialize the BD for every fragment in the page. */
1348 /* Set the last buffer to wrap */
1350 bdp->cbd_sc |= BD_SC_WRAP;
1352 /* ...and the same for transmit */
1353 bdp = fep->tx_bd_base;
1354 for (i = 0; i < TX_RING_SIZE; i++) {
1356 /* Initialize the BD for every fragment in the page. */
1358 bdp->cbd_bufaddr = 0;
1362 /* Set the last buffer to wrap */
1364 bdp->cbd_sc |= BD_SC_WRAP;
1366 fec_restart(ndev, 0);
1371 static int __devinit
1372 fec_probe(struct platform_device *pdev)
1374 struct fec_enet_private *fep;
1375 struct fec_platform_data *pdata;
1376 struct net_device *ndev;
1377 int i, irq, ret = 0;
1380 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1384 r = request_mem_region(r->start, resource_size(r), pdev->name);
1388 /* Init network device */
1389 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
1392 goto failed_alloc_etherdev;
1395 SET_NETDEV_DEV(ndev, &pdev->dev);
1397 /* setup board info structure */
1398 fep = netdev_priv(ndev);
1400 fep->hwp = ioremap(r->start, resource_size(r));
1405 goto failed_ioremap;
1408 platform_set_drvdata(pdev, ndev);
1410 pdata = pdev->dev.platform_data;
1412 fep->phy_interface = pdata->phy;
1414 /* This device has up to three irqs on some platforms */
1415 for (i = 0; i < 3; i++) {
1416 irq = platform_get_irq(pdev, i);
1419 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
1422 irq = platform_get_irq(pdev, i);
1423 free_irq(irq, ndev);
1429 fep->clk = clk_get(&pdev->dev, "fec_clk");
1430 if (IS_ERR(fep->clk)) {
1431 ret = PTR_ERR(fep->clk);
1434 clk_enable(fep->clk);
1436 ret = fec_enet_init(ndev);
1440 ret = fec_enet_mii_init(pdev);
1442 goto failed_mii_init;
1444 /* Carrier starts down, phylib will bring it up */
1445 netif_carrier_off(ndev);
1447 ret = register_netdev(ndev);
1449 goto failed_register;
1454 fec_enet_mii_remove(fep);
1457 clk_disable(fep->clk);
1460 for (i = 0; i < 3; i++) {
1461 irq = platform_get_irq(pdev, i);
1463 free_irq(irq, ndev);
1469 failed_alloc_etherdev:
1470 release_mem_region(r->start, resource_size(r));
1475 static int __devexit
1476 fec_drv_remove(struct platform_device *pdev)
1478 struct net_device *ndev = platform_get_drvdata(pdev);
1479 struct fec_enet_private *fep = netdev_priv(ndev);
1483 fec_enet_mii_remove(fep);
1484 clk_disable(fep->clk);
1487 unregister_netdev(ndev);
1490 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1492 release_mem_region(r->start, resource_size(r));
1494 platform_set_drvdata(pdev, NULL);
1501 fec_suspend(struct device *dev)
1503 struct net_device *ndev = dev_get_drvdata(dev);
1504 struct fec_enet_private *fep = netdev_priv(ndev);
1506 if (netif_running(ndev)) {
1508 netif_device_detach(ndev);
1510 clk_disable(fep->clk);
1516 fec_resume(struct device *dev)
1518 struct net_device *ndev = dev_get_drvdata(dev);
1519 struct fec_enet_private *fep = netdev_priv(ndev);
1521 clk_enable(fep->clk);
1522 if (netif_running(ndev)) {
1523 fec_restart(ndev, fep->full_duplex);
1524 netif_device_attach(ndev);
1530 static const struct dev_pm_ops fec_pm_ops = {
1531 .suspend = fec_suspend,
1532 .resume = fec_resume,
1533 .freeze = fec_suspend,
1535 .poweroff = fec_suspend,
1536 .restore = fec_resume,
1540 static struct platform_driver fec_driver = {
1542 .name = DRIVER_NAME,
1543 .owner = THIS_MODULE,
1548 .id_table = fec_devtype,
1550 .remove = __devexit_p(fec_drv_remove),
1554 fec_enet_module_init(void)
1556 printk(KERN_INFO "FEC Ethernet Driver\n");
1558 return platform_driver_register(&fec_driver);
1562 fec_enet_cleanup(void)
1564 platform_driver_unregister(&fec_driver);
1567 module_exit(fec_enet_cleanup);
1568 module_init(fec_enet_module_init);
1570 MODULE_LICENSE("GPL");