2 * linux/drivers/net/ethoc.c
4 * Copyright (C) 2007-2008 Avionic Design Development GmbH
5 * Copyright (C) 2008-2009 Avionic Design GmbH
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * Written by Thierry Reding <thierry.reding@avionic-design.de>
14 #include <linux/etherdevice.h>
15 #include <linux/crc32.h>
17 #include <linux/mii.h>
18 #include <linux/phy.h>
19 #include <linux/platform_device.h>
20 #include <linux/sched.h>
21 #include <linux/slab.h>
22 #include <net/ethoc.h>
24 static int buffer_size = 0x8000; /* 32 KBytes */
25 module_param(buffer_size, int, 0);
26 MODULE_PARM_DESC(buffer_size, "DMA buffer allocation size");
28 /* register offsets */
30 #define INT_SOURCE 0x04
35 #define PACKETLEN 0x18
37 #define TX_BD_NUM 0x20
38 #define CTRLMODER 0x24
40 #define MIICOMMAND 0x2c
41 #define MIIADDRESS 0x30
42 #define MIITX_DATA 0x34
43 #define MIIRX_DATA 0x38
44 #define MIISTATUS 0x3c
45 #define MAC_ADDR0 0x40
46 #define MAC_ADDR1 0x44
47 #define ETH_HASH0 0x48
48 #define ETH_HASH1 0x4c
49 #define ETH_TXCTRL 0x50
52 #define MODER_RXEN (1 << 0) /* receive enable */
53 #define MODER_TXEN (1 << 1) /* transmit enable */
54 #define MODER_NOPRE (1 << 2) /* no preamble */
55 #define MODER_BRO (1 << 3) /* broadcast address */
56 #define MODER_IAM (1 << 4) /* individual address mode */
57 #define MODER_PRO (1 << 5) /* promiscuous mode */
58 #define MODER_IFG (1 << 6) /* interframe gap for incoming frames */
59 #define MODER_LOOP (1 << 7) /* loopback */
60 #define MODER_NBO (1 << 8) /* no back-off */
61 #define MODER_EDE (1 << 9) /* excess defer enable */
62 #define MODER_FULLD (1 << 10) /* full duplex */
63 #define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */
64 #define MODER_DCRC (1 << 12) /* delayed CRC enable */
65 #define MODER_CRC (1 << 13) /* CRC enable */
66 #define MODER_HUGE (1 << 14) /* huge packets enable */
67 #define MODER_PAD (1 << 15) /* padding enabled */
68 #define MODER_RSM (1 << 16) /* receive small packets */
70 /* interrupt source and mask registers */
71 #define INT_MASK_TXF (1 << 0) /* transmit frame */
72 #define INT_MASK_TXE (1 << 1) /* transmit error */
73 #define INT_MASK_RXF (1 << 2) /* receive frame */
74 #define INT_MASK_RXE (1 << 3) /* receive error */
75 #define INT_MASK_BUSY (1 << 4)
76 #define INT_MASK_TXC (1 << 5) /* transmit control frame */
77 #define INT_MASK_RXC (1 << 6) /* receive control frame */
79 #define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE)
80 #define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE)
82 #define INT_MASK_ALL ( \
83 INT_MASK_TXF | INT_MASK_TXE | \
84 INT_MASK_RXF | INT_MASK_RXE | \
85 INT_MASK_TXC | INT_MASK_RXC | \
89 /* packet length register */
90 #define PACKETLEN_MIN(min) (((min) & 0xffff) << 16)
91 #define PACKETLEN_MAX(max) (((max) & 0xffff) << 0)
92 #define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \
95 /* transmit buffer number register */
96 #define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80)
98 /* control module mode register */
99 #define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */
100 #define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */
101 #define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */
103 /* MII mode register */
104 #define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */
105 #define MIIMODER_NOPRE (1 << 8) /* no preamble */
107 /* MII command register */
108 #define MIICOMMAND_SCAN (1 << 0) /* scan status */
109 #define MIICOMMAND_READ (1 << 1) /* read status */
110 #define MIICOMMAND_WRITE (1 << 2) /* write control data */
112 /* MII address register */
113 #define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0)
114 #define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
115 #define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \
116 MIIADDRESS_RGAD(reg))
118 /* MII transmit data register */
119 #define MIITX_DATA_VAL(x) ((x) & 0xffff)
121 /* MII receive data register */
122 #define MIIRX_DATA_VAL(x) ((x) & 0xffff)
124 /* MII status register */
125 #define MIISTATUS_LINKFAIL (1 << 0)
126 #define MIISTATUS_BUSY (1 << 1)
127 #define MIISTATUS_INVALID (1 << 2)
129 /* TX buffer descriptor */
130 #define TX_BD_CS (1 << 0) /* carrier sense lost */
131 #define TX_BD_DF (1 << 1) /* defer indication */
132 #define TX_BD_LC (1 << 2) /* late collision */
133 #define TX_BD_RL (1 << 3) /* retransmission limit */
134 #define TX_BD_RETRY_MASK (0x00f0)
135 #define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4)
136 #define TX_BD_UR (1 << 8) /* transmitter underrun */
137 #define TX_BD_CRC (1 << 11) /* TX CRC enable */
138 #define TX_BD_PAD (1 << 12) /* pad enable for short packets */
139 #define TX_BD_WRAP (1 << 13)
140 #define TX_BD_IRQ (1 << 14) /* interrupt request enable */
141 #define TX_BD_READY (1 << 15) /* TX buffer ready */
142 #define TX_BD_LEN(x) (((x) & 0xffff) << 16)
143 #define TX_BD_LEN_MASK (0xffff << 16)
145 #define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
146 TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
148 /* RX buffer descriptor */
149 #define RX_BD_LC (1 << 0) /* late collision */
150 #define RX_BD_CRC (1 << 1) /* RX CRC error */
151 #define RX_BD_SF (1 << 2) /* short frame */
152 #define RX_BD_TL (1 << 3) /* too long */
153 #define RX_BD_DN (1 << 4) /* dribble nibble */
154 #define RX_BD_IS (1 << 5) /* invalid symbol */
155 #define RX_BD_OR (1 << 6) /* receiver overrun */
156 #define RX_BD_MISS (1 << 7)
157 #define RX_BD_CF (1 << 8) /* control frame */
158 #define RX_BD_WRAP (1 << 13)
159 #define RX_BD_IRQ (1 << 14) /* interrupt request enable */
160 #define RX_BD_EMPTY (1 << 15)
161 #define RX_BD_LEN(x) (((x) & 0xffff) << 16)
163 #define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
164 RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
166 #define ETHOC_BUFSIZ 1536
167 #define ETHOC_ZLEN 64
168 #define ETHOC_BD_BASE 0x400
169 #define ETHOC_TIMEOUT (HZ / 2)
170 #define ETHOC_MII_TIMEOUT (1 + (HZ / 5))
173 * struct ethoc - driver-private device structure
174 * @iobase: pointer to I/O memory region
175 * @membase: pointer to buffer memory region
176 * @dma_alloc: dma allocated buffer size
177 * @io_region_size: I/O memory region size
178 * @num_tx: number of send buffers
179 * @cur_tx: last send buffer written
180 * @dty_tx: last buffer actually sent
181 * @num_rx: number of receive buffers
182 * @cur_rx: current receive buffer
183 * @vma: pointer to array of virtual memory addresses for buffers
184 * @netdev: pointer to network device structure
185 * @napi: NAPI structure
186 * @stats: network device statistics
187 * @msg_enable: device state flags
188 * @rx_lock: receive lock
191 * @mdio: MDIO bus for PHY access
192 * @phy_id: address of attached PHY
195 void __iomem *iobase;
196 void __iomem *membase;
198 resource_size_t io_region_size;
209 struct net_device *netdev;
210 struct napi_struct napi;
211 struct net_device_stats stats;
217 struct phy_device *phy;
218 struct mii_bus *mdio;
223 * struct ethoc_bd - buffer descriptor
224 * @stat: buffer statistics
225 * @addr: physical memory address
232 static inline u32 ethoc_read(struct ethoc *dev, loff_t offset)
234 return ioread32(dev->iobase + offset);
237 static inline void ethoc_write(struct ethoc *dev, loff_t offset, u32 data)
239 iowrite32(data, dev->iobase + offset);
242 static inline void ethoc_read_bd(struct ethoc *dev, int index,
245 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
246 bd->stat = ethoc_read(dev, offset + 0);
247 bd->addr = ethoc_read(dev, offset + 4);
250 static inline void ethoc_write_bd(struct ethoc *dev, int index,
251 const struct ethoc_bd *bd)
253 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
254 ethoc_write(dev, offset + 0, bd->stat);
255 ethoc_write(dev, offset + 4, bd->addr);
258 static inline void ethoc_enable_irq(struct ethoc *dev, u32 mask)
260 u32 imask = ethoc_read(dev, INT_MASK);
262 ethoc_write(dev, INT_MASK, imask);
265 static inline void ethoc_disable_irq(struct ethoc *dev, u32 mask)
267 u32 imask = ethoc_read(dev, INT_MASK);
269 ethoc_write(dev, INT_MASK, imask);
272 static inline void ethoc_ack_irq(struct ethoc *dev, u32 mask)
274 ethoc_write(dev, INT_SOURCE, mask);
277 static inline void ethoc_enable_rx_and_tx(struct ethoc *dev)
279 u32 mode = ethoc_read(dev, MODER);
280 mode |= MODER_RXEN | MODER_TXEN;
281 ethoc_write(dev, MODER, mode);
284 static inline void ethoc_disable_rx_and_tx(struct ethoc *dev)
286 u32 mode = ethoc_read(dev, MODER);
287 mode &= ~(MODER_RXEN | MODER_TXEN);
288 ethoc_write(dev, MODER, mode);
291 static int ethoc_init_ring(struct ethoc *dev, void* mem_start)
301 ethoc_write(dev, TX_BD_NUM, dev->num_tx);
303 /* setup transmission buffers */
305 bd.stat = TX_BD_IRQ | TX_BD_CRC;
308 for (i = 0; i < dev->num_tx; i++) {
309 if (i == dev->num_tx - 1)
310 bd.stat |= TX_BD_WRAP;
312 ethoc_write_bd(dev, i, &bd);
313 bd.addr += ETHOC_BUFSIZ;
319 bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
321 for (i = 0; i < dev->num_rx; i++) {
322 if (i == dev->num_rx - 1)
323 bd.stat |= RX_BD_WRAP;
325 ethoc_write_bd(dev, dev->num_tx + i, &bd);
326 bd.addr += ETHOC_BUFSIZ;
328 dev->vma[dev->num_tx + i] = vma;
335 static int ethoc_reset(struct ethoc *dev)
339 /* TODO: reset controller? */
341 ethoc_disable_rx_and_tx(dev);
343 /* TODO: setup registers */
345 /* enable FCS generation and automatic padding */
346 mode = ethoc_read(dev, MODER);
347 mode |= MODER_CRC | MODER_PAD;
348 ethoc_write(dev, MODER, mode);
350 /* set full-duplex mode */
351 mode = ethoc_read(dev, MODER);
353 ethoc_write(dev, MODER, mode);
354 ethoc_write(dev, IPGT, 0x15);
356 ethoc_ack_irq(dev, INT_MASK_ALL);
357 ethoc_enable_irq(dev, INT_MASK_ALL);
358 ethoc_enable_rx_and_tx(dev);
362 static unsigned int ethoc_update_rx_stats(struct ethoc *dev,
365 struct net_device *netdev = dev->netdev;
366 unsigned int ret = 0;
368 if (bd->stat & RX_BD_TL) {
369 dev_err(&netdev->dev, "RX: frame too long\n");
370 dev->stats.rx_length_errors++;
374 if (bd->stat & RX_BD_SF) {
375 dev_err(&netdev->dev, "RX: frame too short\n");
376 dev->stats.rx_length_errors++;
380 if (bd->stat & RX_BD_DN) {
381 dev_err(&netdev->dev, "RX: dribble nibble\n");
382 dev->stats.rx_frame_errors++;
385 if (bd->stat & RX_BD_CRC) {
386 dev_err(&netdev->dev, "RX: wrong CRC\n");
387 dev->stats.rx_crc_errors++;
391 if (bd->stat & RX_BD_OR) {
392 dev_err(&netdev->dev, "RX: overrun\n");
393 dev->stats.rx_over_errors++;
397 if (bd->stat & RX_BD_MISS)
398 dev->stats.rx_missed_errors++;
400 if (bd->stat & RX_BD_LC) {
401 dev_err(&netdev->dev, "RX: late collision\n");
402 dev->stats.collisions++;
409 static int ethoc_rx(struct net_device *dev, int limit)
411 struct ethoc *priv = netdev_priv(dev);
414 for (count = 0; count < limit; ++count) {
418 entry = priv->num_tx + (priv->cur_rx % priv->num_rx);
419 ethoc_read_bd(priv, entry, &bd);
420 if (bd.stat & RX_BD_EMPTY)
423 if (ethoc_update_rx_stats(priv, &bd) == 0) {
424 int size = bd.stat >> 16;
427 size -= 4; /* strip the CRC */
428 skb = netdev_alloc_skb_ip_align(dev, size);
431 void *src = priv->vma[entry];
432 memcpy_fromio(skb_put(skb, size), src, size);
433 skb->protocol = eth_type_trans(skb, dev);
434 priv->stats.rx_packets++;
435 priv->stats.rx_bytes += size;
436 netif_receive_skb(skb);
439 dev_warn(&dev->dev, "low on memory - "
442 priv->stats.rx_dropped++;
447 /* clear the buffer descriptor so it can be reused */
448 bd.stat &= ~RX_BD_STATS;
449 bd.stat |= RX_BD_EMPTY;
450 ethoc_write_bd(priv, entry, &bd);
457 static int ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd)
459 struct net_device *netdev = dev->netdev;
461 if (bd->stat & TX_BD_LC) {
462 dev_err(&netdev->dev, "TX: late collision\n");
463 dev->stats.tx_window_errors++;
466 if (bd->stat & TX_BD_RL) {
467 dev_err(&netdev->dev, "TX: retransmit limit\n");
468 dev->stats.tx_aborted_errors++;
471 if (bd->stat & TX_BD_UR) {
472 dev_err(&netdev->dev, "TX: underrun\n");
473 dev->stats.tx_fifo_errors++;
476 if (bd->stat & TX_BD_CS) {
477 dev_err(&netdev->dev, "TX: carrier sense lost\n");
478 dev->stats.tx_carrier_errors++;
481 if (bd->stat & TX_BD_STATS)
482 dev->stats.tx_errors++;
484 dev->stats.collisions += (bd->stat >> 4) & 0xf;
485 dev->stats.tx_bytes += bd->stat >> 16;
486 dev->stats.tx_packets++;
490 static void ethoc_tx(struct net_device *dev)
492 struct ethoc *priv = netdev_priv(dev);
494 spin_lock(&priv->lock);
496 while (priv->dty_tx != priv->cur_tx) {
497 unsigned int entry = priv->dty_tx % priv->num_tx;
500 ethoc_read_bd(priv, entry, &bd);
501 if (bd.stat & TX_BD_READY)
504 entry = (++priv->dty_tx) % priv->num_tx;
505 (void)ethoc_update_tx_stats(priv, &bd);
508 if ((priv->cur_tx - priv->dty_tx) <= (priv->num_tx / 2))
509 netif_wake_queue(dev);
511 ethoc_ack_irq(priv, INT_MASK_TX);
512 spin_unlock(&priv->lock);
515 static irqreturn_t ethoc_interrupt(int irq, void *dev_id)
517 struct net_device *dev = (struct net_device *)dev_id;
518 struct ethoc *priv = netdev_priv(dev);
521 ethoc_disable_irq(priv, INT_MASK_ALL);
522 pending = ethoc_read(priv, INT_SOURCE);
523 if (unlikely(pending == 0)) {
524 ethoc_enable_irq(priv, INT_MASK_ALL);
528 ethoc_ack_irq(priv, pending);
530 if (pending & INT_MASK_BUSY) {
531 dev_err(&dev->dev, "packet dropped\n");
532 priv->stats.rx_dropped++;
535 if (pending & INT_MASK_RX) {
536 if (napi_schedule_prep(&priv->napi))
537 __napi_schedule(&priv->napi);
539 ethoc_enable_irq(priv, INT_MASK_RX);
542 if (pending & INT_MASK_TX)
545 ethoc_enable_irq(priv, INT_MASK_ALL & ~INT_MASK_RX);
549 static int ethoc_get_mac_address(struct net_device *dev, void *addr)
551 struct ethoc *priv = netdev_priv(dev);
552 u8 *mac = (u8 *)addr;
555 reg = ethoc_read(priv, MAC_ADDR0);
556 mac[2] = (reg >> 24) & 0xff;
557 mac[3] = (reg >> 16) & 0xff;
558 mac[4] = (reg >> 8) & 0xff;
559 mac[5] = (reg >> 0) & 0xff;
561 reg = ethoc_read(priv, MAC_ADDR1);
562 mac[0] = (reg >> 8) & 0xff;
563 mac[1] = (reg >> 0) & 0xff;
568 static int ethoc_poll(struct napi_struct *napi, int budget)
570 struct ethoc *priv = container_of(napi, struct ethoc, napi);
573 work_done = ethoc_rx(priv->netdev, budget);
574 if (work_done < budget) {
575 ethoc_enable_irq(priv, INT_MASK_RX);
582 static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg)
584 unsigned long timeout = jiffies + ETHOC_MII_TIMEOUT;
585 struct ethoc *priv = bus->priv;
587 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
588 ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
590 while (time_before(jiffies, timeout)) {
591 u32 status = ethoc_read(priv, MIISTATUS);
592 if (!(status & MIISTATUS_BUSY)) {
593 u32 data = ethoc_read(priv, MIIRX_DATA);
594 /* reset MII command register */
595 ethoc_write(priv, MIICOMMAND, 0);
605 static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
607 unsigned long timeout = jiffies + ETHOC_MII_TIMEOUT;
608 struct ethoc *priv = bus->priv;
610 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
611 ethoc_write(priv, MIITX_DATA, val);
612 ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
614 while (time_before(jiffies, timeout)) {
615 u32 stat = ethoc_read(priv, MIISTATUS);
616 if (!(stat & MIISTATUS_BUSY)) {
617 /* reset MII command register */
618 ethoc_write(priv, MIICOMMAND, 0);
628 static int ethoc_mdio_reset(struct mii_bus *bus)
633 static void ethoc_mdio_poll(struct net_device *dev)
637 static int ethoc_mdio_probe(struct net_device *dev)
639 struct ethoc *priv = netdev_priv(dev);
640 struct phy_device *phy;
643 if (priv->phy_id != -1) {
644 phy = priv->mdio->phy_map[priv->phy_id];
646 phy = phy_find_first(priv->mdio);
650 dev_err(&dev->dev, "no PHY found\n");
654 err = phy_connect_direct(dev, phy, ethoc_mdio_poll, 0,
655 PHY_INTERFACE_MODE_GMII);
657 dev_err(&dev->dev, "could not attach to PHY\n");
665 static int ethoc_open(struct net_device *dev)
667 struct ethoc *priv = netdev_priv(dev);
670 ret = request_irq(dev->irq, ethoc_interrupt, IRQF_SHARED,
675 ethoc_init_ring(priv, (void*)dev->mem_start);
678 if (netif_queue_stopped(dev)) {
679 dev_dbg(&dev->dev, " resuming queue\n");
680 netif_wake_queue(dev);
682 dev_dbg(&dev->dev, " starting queue\n");
683 netif_start_queue(dev);
686 phy_start(priv->phy);
687 napi_enable(&priv->napi);
689 if (netif_msg_ifup(priv)) {
690 dev_info(&dev->dev, "I/O: %08lx Memory: %08lx-%08lx\n",
691 dev->base_addr, dev->mem_start, dev->mem_end);
697 static int ethoc_stop(struct net_device *dev)
699 struct ethoc *priv = netdev_priv(dev);
701 napi_disable(&priv->napi);
706 ethoc_disable_rx_and_tx(priv);
707 free_irq(dev->irq, dev);
709 if (!netif_queue_stopped(dev))
710 netif_stop_queue(dev);
715 static int ethoc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
717 struct ethoc *priv = netdev_priv(dev);
718 struct mii_ioctl_data *mdio = if_mii(ifr);
719 struct phy_device *phy = NULL;
721 if (!netif_running(dev))
724 if (cmd != SIOCGMIIPHY) {
725 if (mdio->phy_id >= PHY_MAX_ADDR)
728 phy = priv->mdio->phy_map[mdio->phy_id];
735 return phy_mii_ioctl(phy, mdio, cmd);
738 static int ethoc_config(struct net_device *dev, struct ifmap *map)
743 static int ethoc_set_mac_address(struct net_device *dev, void *addr)
745 struct ethoc *priv = netdev_priv(dev);
746 u8 *mac = (u8 *)addr;
748 ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
749 (mac[4] << 8) | (mac[5] << 0));
750 ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
755 static void ethoc_set_multicast_list(struct net_device *dev)
757 struct ethoc *priv = netdev_priv(dev);
758 u32 mode = ethoc_read(priv, MODER);
759 struct netdev_hw_addr *ha;
760 u32 hash[2] = { 0, 0 };
762 /* set loopback mode if requested */
763 if (dev->flags & IFF_LOOPBACK)
768 /* receive broadcast frames if requested */
769 if (dev->flags & IFF_BROADCAST)
774 /* enable promiscuous mode if requested */
775 if (dev->flags & IFF_PROMISC)
780 ethoc_write(priv, MODER, mode);
782 /* receive multicast frames */
783 if (dev->flags & IFF_ALLMULTI) {
784 hash[0] = 0xffffffff;
785 hash[1] = 0xffffffff;
787 netdev_for_each_mc_addr(ha, dev) {
788 u32 crc = ether_crc(ETH_ALEN, ha->addr);
789 int bit = (crc >> 26) & 0x3f;
790 hash[bit >> 5] |= 1 << (bit & 0x1f);
794 ethoc_write(priv, ETH_HASH0, hash[0]);
795 ethoc_write(priv, ETH_HASH1, hash[1]);
798 static int ethoc_change_mtu(struct net_device *dev, int new_mtu)
803 static void ethoc_tx_timeout(struct net_device *dev)
805 struct ethoc *priv = netdev_priv(dev);
806 u32 pending = ethoc_read(priv, INT_SOURCE);
808 ethoc_interrupt(dev->irq, dev);
811 static struct net_device_stats *ethoc_stats(struct net_device *dev)
813 struct ethoc *priv = netdev_priv(dev);
817 static netdev_tx_t ethoc_start_xmit(struct sk_buff *skb, struct net_device *dev)
819 struct ethoc *priv = netdev_priv(dev);
824 if (unlikely(skb->len > ETHOC_BUFSIZ)) {
825 priv->stats.tx_errors++;
829 entry = priv->cur_tx % priv->num_tx;
830 spin_lock_irq(&priv->lock);
833 ethoc_read_bd(priv, entry, &bd);
834 if (unlikely(skb->len < ETHOC_ZLEN))
835 bd.stat |= TX_BD_PAD;
837 bd.stat &= ~TX_BD_PAD;
839 dest = priv->vma[entry];
840 memcpy_toio(dest, skb->data, skb->len);
842 bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
843 bd.stat |= TX_BD_LEN(skb->len);
844 ethoc_write_bd(priv, entry, &bd);
846 bd.stat |= TX_BD_READY;
847 ethoc_write_bd(priv, entry, &bd);
849 if (priv->cur_tx == (priv->dty_tx + priv->num_tx)) {
850 dev_dbg(&dev->dev, "stopping queue\n");
851 netif_stop_queue(dev);
854 spin_unlock_irq(&priv->lock);
860 static const struct net_device_ops ethoc_netdev_ops = {
861 .ndo_open = ethoc_open,
862 .ndo_stop = ethoc_stop,
863 .ndo_do_ioctl = ethoc_ioctl,
864 .ndo_set_config = ethoc_config,
865 .ndo_set_mac_address = ethoc_set_mac_address,
866 .ndo_set_multicast_list = ethoc_set_multicast_list,
867 .ndo_change_mtu = ethoc_change_mtu,
868 .ndo_tx_timeout = ethoc_tx_timeout,
869 .ndo_get_stats = ethoc_stats,
870 .ndo_start_xmit = ethoc_start_xmit,
874 * ethoc_probe() - initialize OpenCores ethernet MAC
875 * pdev: platform device
877 static int ethoc_probe(struct platform_device *pdev)
879 struct net_device *netdev = NULL;
880 struct resource *res = NULL;
881 struct resource *mmio = NULL;
882 struct resource *mem = NULL;
883 struct ethoc *priv = NULL;
888 /* allocate networking device */
889 netdev = alloc_etherdev(sizeof(struct ethoc));
891 dev_err(&pdev->dev, "cannot allocate network device\n");
896 SET_NETDEV_DEV(netdev, &pdev->dev);
897 platform_set_drvdata(pdev, netdev);
899 /* obtain I/O memory space */
900 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
902 dev_err(&pdev->dev, "cannot obtain I/O memory space\n");
907 mmio = devm_request_mem_region(&pdev->dev, res->start,
908 resource_size(res), res->name);
910 dev_err(&pdev->dev, "cannot request I/O memory space\n");
915 netdev->base_addr = mmio->start;
917 /* obtain buffer memory space */
918 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
920 mem = devm_request_mem_region(&pdev->dev, res->start,
921 resource_size(res), res->name);
923 dev_err(&pdev->dev, "cannot request memory space\n");
928 netdev->mem_start = mem->start;
929 netdev->mem_end = mem->end;
933 /* obtain device IRQ number */
934 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
936 dev_err(&pdev->dev, "cannot obtain IRQ\n");
941 netdev->irq = res->start;
943 /* setup driver-private data */
944 priv = netdev_priv(netdev);
945 priv->netdev = netdev;
947 priv->io_region_size = mmio->end - mmio->start + 1;
949 priv->iobase = devm_ioremap_nocache(&pdev->dev, netdev->base_addr,
950 resource_size(mmio));
952 dev_err(&pdev->dev, "cannot remap I/O memory space\n");
957 if (netdev->mem_end) {
958 priv->membase = devm_ioremap_nocache(&pdev->dev,
959 netdev->mem_start, resource_size(mem));
960 if (!priv->membase) {
961 dev_err(&pdev->dev, "cannot remap memory space\n");
966 /* Allocate buffer memory */
967 priv->membase = dmam_alloc_coherent(&pdev->dev,
968 buffer_size, (void *)&netdev->mem_start,
970 if (!priv->membase) {
971 dev_err(&pdev->dev, "cannot allocate %dB buffer\n",
976 netdev->mem_end = netdev->mem_start + buffer_size;
977 priv->dma_alloc = buffer_size;
980 /* calculate the number of TX/RX buffers, maximum 128 supported */
981 num_bd = min_t(unsigned int,
982 128, (netdev->mem_end - netdev->mem_start + 1) / ETHOC_BUFSIZ);
983 priv->num_tx = max(2, num_bd / 4);
984 priv->num_rx = num_bd - priv->num_tx;
986 priv->vma = devm_kzalloc(&pdev->dev, num_bd*sizeof(void*), GFP_KERNEL);
992 /* Allow the platform setup code to pass in a MAC address. */
993 if (pdev->dev.platform_data) {
994 struct ethoc_platform_data *pdata =
995 (struct ethoc_platform_data *)pdev->dev.platform_data;
996 memcpy(netdev->dev_addr, pdata->hwaddr, IFHWADDRLEN);
997 priv->phy_id = pdata->phy_id;
1000 /* Check that the given MAC address is valid. If it isn't, read the
1001 * current MAC from the controller. */
1002 if (!is_valid_ether_addr(netdev->dev_addr))
1003 ethoc_get_mac_address(netdev, netdev->dev_addr);
1005 /* Check the MAC again for validity, if it still isn't choose and
1006 * program a random one. */
1007 if (!is_valid_ether_addr(netdev->dev_addr))
1008 random_ether_addr(netdev->dev_addr);
1010 ethoc_set_mac_address(netdev, netdev->dev_addr);
1012 /* register MII bus */
1013 priv->mdio = mdiobus_alloc();
1019 priv->mdio->name = "ethoc-mdio";
1020 snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%d",
1021 priv->mdio->name, pdev->id);
1022 priv->mdio->read = ethoc_mdio_read;
1023 priv->mdio->write = ethoc_mdio_write;
1024 priv->mdio->reset = ethoc_mdio_reset;
1025 priv->mdio->priv = priv;
1027 priv->mdio->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1028 if (!priv->mdio->irq) {
1033 for (phy = 0; phy < PHY_MAX_ADDR; phy++)
1034 priv->mdio->irq[phy] = PHY_POLL;
1036 ret = mdiobus_register(priv->mdio);
1038 dev_err(&netdev->dev, "failed to register MDIO bus\n");
1042 ret = ethoc_mdio_probe(netdev);
1044 dev_err(&netdev->dev, "failed to probe MDIO bus\n");
1048 ether_setup(netdev);
1050 /* setup the net_device structure */
1051 netdev->netdev_ops = ðoc_netdev_ops;
1052 netdev->watchdog_timeo = ETHOC_TIMEOUT;
1053 netdev->features |= 0;
1056 netif_napi_add(netdev, &priv->napi, ethoc_poll, 64);
1058 spin_lock_init(&priv->rx_lock);
1059 spin_lock_init(&priv->lock);
1061 ret = register_netdev(netdev);
1063 dev_err(&netdev->dev, "failed to register interface\n");
1070 netif_napi_del(&priv->napi);
1072 mdiobus_unregister(priv->mdio);
1074 kfree(priv->mdio->irq);
1075 mdiobus_free(priv->mdio);
1077 free_netdev(netdev);
1083 * ethoc_remove() - shutdown OpenCores ethernet MAC
1084 * @pdev: platform device
1086 static int ethoc_remove(struct platform_device *pdev)
1088 struct net_device *netdev = platform_get_drvdata(pdev);
1089 struct ethoc *priv = netdev_priv(netdev);
1091 platform_set_drvdata(pdev, NULL);
1094 netif_napi_del(&priv->napi);
1095 phy_disconnect(priv->phy);
1099 mdiobus_unregister(priv->mdio);
1100 kfree(priv->mdio->irq);
1101 mdiobus_free(priv->mdio);
1103 unregister_netdev(netdev);
1104 free_netdev(netdev);
1111 static int ethoc_suspend(struct platform_device *pdev, pm_message_t state)
1116 static int ethoc_resume(struct platform_device *pdev)
1121 # define ethoc_suspend NULL
1122 # define ethoc_resume NULL
1125 static struct platform_driver ethoc_driver = {
1126 .probe = ethoc_probe,
1127 .remove = ethoc_remove,
1128 .suspend = ethoc_suspend,
1129 .resume = ethoc_resume,
1135 static int __init ethoc_init(void)
1137 return platform_driver_register(ðoc_driver);
1140 static void __exit ethoc_exit(void)
1142 platform_driver_unregister(ðoc_driver);
1145 module_init(ethoc_init);
1146 module_exit(ethoc_exit);
1148 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1149 MODULE_DESCRIPTION("OpenCores Ethernet MAC driver");
1150 MODULE_LICENSE("GPL v2");