1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2010 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/random.h>
17 #include "net_driver.h"
26 #include "workarounds.h"
28 #include "mcdi_pcol.h"
30 /* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
32 static void siena_init_wol(struct efx_nic *efx);
35 static void siena_push_irq_moderation(struct efx_channel *channel)
37 efx_dword_t timer_cmd;
39 BUILD_BUG_ON(EFX_IRQ_MOD_MAX > (1 << FRF_CZ_TC_TIMER_VAL_WIDTH));
41 if (channel->irq_moderation)
42 EFX_POPULATE_DWORD_2(timer_cmd,
44 FFE_CZ_TIMER_MODE_INT_HLDOFF,
46 channel->irq_moderation - 1);
48 EFX_POPULATE_DWORD_2(timer_cmd,
50 FFE_CZ_TIMER_MODE_DIS,
51 FRF_CZ_TC_TIMER_VAL, 0);
52 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
56 static void siena_push_multicast_hash(struct efx_nic *efx)
58 WARN_ON(!mutex_is_locked(&efx->mac_lock));
60 efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
61 efx->multicast_hash.byte, sizeof(efx->multicast_hash),
65 static int siena_mdio_write(struct net_device *net_dev,
66 int prtad, int devad, u16 addr, u16 value)
68 struct efx_nic *efx = netdev_priv(net_dev);
72 rc = efx_mcdi_mdio_write(efx, efx->mdio_bus, prtad, devad,
73 addr, value, &status);
76 if (status != MC_CMD_MDIO_STATUS_GOOD)
82 static int siena_mdio_read(struct net_device *net_dev,
83 int prtad, int devad, u16 addr)
85 struct efx_nic *efx = netdev_priv(net_dev);
90 rc = efx_mcdi_mdio_read(efx, efx->mdio_bus, prtad, devad,
91 addr, &value, &status);
94 if (status != MC_CMD_MDIO_STATUS_GOOD)
100 /* This call is responsible for hooking in the MAC and PHY operations */
101 static int siena_probe_port(struct efx_nic *efx)
105 /* Hook in PHY operations table */
106 efx->phy_op = &efx_mcdi_phy_ops;
108 /* Set up MDIO structure for PHY */
109 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
110 efx->mdio.mdio_read = siena_mdio_read;
111 efx->mdio.mdio_write = siena_mdio_write;
113 /* Fill out MDIO structure, loopback modes, and initial link state */
114 rc = efx->phy_op->probe(efx);
118 /* Allocate buffer for stats */
119 rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
120 MC_CMD_MAC_NSTATS * sizeof(u64));
123 netif_dbg(efx, probe, efx->net_dev,
124 "stats buffer at %llx (virt %p phys %llx)\n",
125 (u64)efx->stats_buffer.dma_addr,
126 efx->stats_buffer.addr,
127 (u64)virt_to_phys(efx->stats_buffer.addr));
129 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 1);
134 static void siena_remove_port(struct efx_nic *efx)
136 efx->phy_op->remove(efx);
137 efx_nic_free_buffer(efx, &efx->stats_buffer);
140 void siena_prepare_flush(struct efx_nic *efx)
142 if (efx->fc_disable++ == 0)
143 efx_mcdi_set_mac(efx);
146 void siena_finish_flush(struct efx_nic *efx)
148 if (--efx->fc_disable == 0)
149 efx_mcdi_set_mac(efx);
152 static const struct efx_nic_register_test siena_register_tests[] = {
154 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
156 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
158 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
160 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
162 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
163 { FR_AZ_SRM_TX_DC_CFG,
164 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
166 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
168 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
170 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
172 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
173 { FR_CZ_RX_RSS_IPV6_REG1,
174 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
175 { FR_CZ_RX_RSS_IPV6_REG2,
176 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
177 { FR_CZ_RX_RSS_IPV6_REG3,
178 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
181 static int siena_test_registers(struct efx_nic *efx)
183 return efx_nic_test_registers(efx, siena_register_tests,
184 ARRAY_SIZE(siena_register_tests));
187 /**************************************************************************
191 **************************************************************************
194 static enum reset_type siena_map_reset_reason(enum reset_type reason)
196 return RESET_TYPE_ALL;
199 static int siena_map_reset_flags(u32 *flags)
202 SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER |
203 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
205 SIENA_RESET_MC = (SIENA_RESET_PORT |
206 ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT),
209 if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) {
210 *flags &= ~SIENA_RESET_MC;
211 return RESET_TYPE_WORLD;
214 if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) {
215 *flags &= ~SIENA_RESET_PORT;
216 return RESET_TYPE_ALL;
219 /* no invisible reset implemented */
224 static int siena_reset_hw(struct efx_nic *efx, enum reset_type method)
228 /* Recover from a failed assertion pre-reset */
229 rc = efx_mcdi_handle_assertion(efx);
233 if (method == RESET_TYPE_WORLD)
234 return efx_mcdi_reset_mc(efx);
236 return efx_mcdi_reset_port(efx);
239 static int siena_probe_nvconfig(struct efx_nic *efx)
241 return efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL);
244 static int siena_probe_nic(struct efx_nic *efx)
246 struct siena_nic_data *nic_data;
247 bool already_attached = 0;
251 /* Allocate storage for hardware specific data */
252 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
255 efx->nic_data = nic_data;
257 if (efx_nic_fpga_ver(efx) != 0) {
258 netif_err(efx, probe, efx->net_dev,
259 "Siena FPGA not supported\n");
264 efx_reado(efx, ®, FR_AZ_CS_DEBUG);
265 efx->net_dev->dev_id = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
269 /* Recover from a failed assertion before probing */
270 rc = efx_mcdi_handle_assertion(efx);
274 /* Let the BMC know that the driver is now in charge of link and
275 * filter settings. We must do this before we reset the NIC */
276 rc = efx_mcdi_drv_attach(efx, true, &already_attached);
278 netif_err(efx, probe, efx->net_dev,
279 "Unable to register driver with MCPU\n");
282 if (already_attached)
283 /* Not a fatal error */
284 netif_err(efx, probe, efx->net_dev,
285 "Host already registered with MCPU\n");
287 /* Now we can reset the NIC */
288 rc = siena_reset_hw(efx, RESET_TYPE_ALL);
290 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
296 /* Allocate memory for INT_KER */
297 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
300 BUG_ON(efx->irq_status.dma_addr & 0x0f);
302 netif_dbg(efx, probe, efx->net_dev,
303 "INT_KER at %llx (virt %p phys %llx)\n",
304 (unsigned long long)efx->irq_status.dma_addr,
305 efx->irq_status.addr,
306 (unsigned long long)virt_to_phys(efx->irq_status.addr));
308 /* Read in the non-volatile configuration */
309 rc = siena_probe_nvconfig(efx);
311 netif_err(efx, probe, efx->net_dev,
312 "NVRAM is invalid therefore using defaults\n");
313 efx->phy_type = PHY_TYPE_NONE;
314 efx->mdio.prtad = MDIO_PRTAD_NONE;
322 efx_nic_free_buffer(efx, &efx->irq_status);
325 efx_mcdi_drv_attach(efx, false, NULL);
328 kfree(efx->nic_data);
332 /* This call performs hardware-specific global initialisation, such as
333 * defining the descriptor cache sizes and number of RSS channels.
334 * It does not set up any buffers, descriptor rings or event queues.
336 static int siena_init_nic(struct efx_nic *efx)
341 /* Recover from a failed assertion post-reset */
342 rc = efx_mcdi_handle_assertion(efx);
346 /* Squash TX of packets of 16 bytes or less */
347 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
348 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
349 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
351 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
352 * descriptors (which is bad).
354 efx_reado(efx, &temp, FR_AZ_TX_CFG);
355 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
356 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
357 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
359 efx_reado(efx, &temp, FR_AZ_RX_CFG);
360 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
361 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
362 /* Enable hash insertion. This is broken for the 'Falcon' hash
363 * if IPv6 hashing is also enabled, so also select Toeplitz
364 * TCP/IPv4 and IPv4 hashes. */
365 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
366 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
367 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
368 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
370 /* Set hash key for IPv4 */
371 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
372 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
374 /* Enable IPv6 RSS */
375 BUILD_BUG_ON(sizeof(efx->rx_hash_key) <
376 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
377 FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
378 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
379 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
380 memcpy(&temp, efx->rx_hash_key + sizeof(temp), sizeof(temp));
381 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
382 EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
383 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
384 memcpy(&temp, efx->rx_hash_key + 2 * sizeof(temp),
385 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
386 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
388 /* Enable event logging */
389 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
393 /* Set destination of both TX and RX Flush events */
394 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
395 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
397 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
398 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
400 efx_nic_init_common(efx);
404 static void siena_remove_nic(struct efx_nic *efx)
406 efx_nic_free_buffer(efx, &efx->irq_status);
408 siena_reset_hw(efx, RESET_TYPE_ALL);
410 /* Relinquish the device back to the BMC */
411 if (efx_nic_has_mc(efx))
412 efx_mcdi_drv_attach(efx, false, NULL);
414 /* Tear down the private nic state */
415 kfree(efx->nic_data);
416 efx->nic_data = NULL;
419 #define STATS_GENERATION_INVALID ((__force __le64)(-1))
421 static int siena_try_update_nic_stats(struct efx_nic *efx)
424 struct efx_mac_stats *mac_stats;
425 __le64 generation_start, generation_end;
427 mac_stats = &efx->mac_stats;
428 dma_stats = efx->stats_buffer.addr;
430 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
431 if (generation_end == STATS_GENERATION_INVALID)
435 #define MAC_STAT(M, D) \
436 mac_stats->M = le64_to_cpu(dma_stats[MC_CMD_MAC_ ## D])
438 MAC_STAT(tx_bytes, TX_BYTES);
439 MAC_STAT(tx_bad_bytes, TX_BAD_BYTES);
440 mac_stats->tx_good_bytes = (mac_stats->tx_bytes -
441 mac_stats->tx_bad_bytes);
442 MAC_STAT(tx_packets, TX_PKTS);
443 MAC_STAT(tx_bad, TX_BAD_FCS_PKTS);
444 MAC_STAT(tx_pause, TX_PAUSE_PKTS);
445 MAC_STAT(tx_control, TX_CONTROL_PKTS);
446 MAC_STAT(tx_unicast, TX_UNICAST_PKTS);
447 MAC_STAT(tx_multicast, TX_MULTICAST_PKTS);
448 MAC_STAT(tx_broadcast, TX_BROADCAST_PKTS);
449 MAC_STAT(tx_lt64, TX_LT64_PKTS);
450 MAC_STAT(tx_64, TX_64_PKTS);
451 MAC_STAT(tx_65_to_127, TX_65_TO_127_PKTS);
452 MAC_STAT(tx_128_to_255, TX_128_TO_255_PKTS);
453 MAC_STAT(tx_256_to_511, TX_256_TO_511_PKTS);
454 MAC_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS);
455 MAC_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS);
456 MAC_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS);
457 MAC_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS);
458 mac_stats->tx_collision = 0;
459 MAC_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS);
460 MAC_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS);
461 MAC_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS);
462 MAC_STAT(tx_deferred, TX_DEFERRED_PKTS);
463 MAC_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS);
464 mac_stats->tx_collision = (mac_stats->tx_single_collision +
465 mac_stats->tx_multiple_collision +
466 mac_stats->tx_excessive_collision +
467 mac_stats->tx_late_collision);
468 MAC_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS);
469 MAC_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS);
470 MAC_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS);
471 MAC_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS);
472 MAC_STAT(rx_bytes, RX_BYTES);
473 MAC_STAT(rx_bad_bytes, RX_BAD_BYTES);
474 mac_stats->rx_good_bytes = (mac_stats->rx_bytes -
475 mac_stats->rx_bad_bytes);
476 MAC_STAT(rx_packets, RX_PKTS);
477 MAC_STAT(rx_good, RX_GOOD_PKTS);
478 MAC_STAT(rx_bad, RX_BAD_FCS_PKTS);
479 MAC_STAT(rx_pause, RX_PAUSE_PKTS);
480 MAC_STAT(rx_control, RX_CONTROL_PKTS);
481 MAC_STAT(rx_unicast, RX_UNICAST_PKTS);
482 MAC_STAT(rx_multicast, RX_MULTICAST_PKTS);
483 MAC_STAT(rx_broadcast, RX_BROADCAST_PKTS);
484 MAC_STAT(rx_lt64, RX_UNDERSIZE_PKTS);
485 MAC_STAT(rx_64, RX_64_PKTS);
486 MAC_STAT(rx_65_to_127, RX_65_TO_127_PKTS);
487 MAC_STAT(rx_128_to_255, RX_128_TO_255_PKTS);
488 MAC_STAT(rx_256_to_511, RX_256_TO_511_PKTS);
489 MAC_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS);
490 MAC_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS);
491 MAC_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS);
492 MAC_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS);
493 mac_stats->rx_bad_lt64 = 0;
494 mac_stats->rx_bad_64_to_15xx = 0;
495 mac_stats->rx_bad_15xx_to_jumbo = 0;
496 MAC_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS);
497 MAC_STAT(rx_overflow, RX_OVERFLOW_PKTS);
498 mac_stats->rx_missed = 0;
499 MAC_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS);
500 MAC_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS);
501 MAC_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS);
502 MAC_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS);
503 MAC_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS);
504 mac_stats->rx_good_lt64 = 0;
506 efx->n_rx_nodesc_drop_cnt =
507 le64_to_cpu(dma_stats[MC_CMD_MAC_RX_NODESC_DROPS]);
512 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
513 if (generation_end != generation_start)
519 static void siena_update_nic_stats(struct efx_nic *efx)
523 /* If we're unlucky enough to read statistics wduring the DMA, wait
524 * up to 10ms for it to finish (typically takes <500us) */
525 for (retry = 0; retry < 100; ++retry) {
526 if (siena_try_update_nic_stats(efx) == 0)
531 /* Use the old values instead */
534 static void siena_start_nic_stats(struct efx_nic *efx)
536 __le64 *dma_stats = efx->stats_buffer.addr;
538 dma_stats[MC_CMD_MAC_GENERATION_END] = STATS_GENERATION_INVALID;
540 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr,
541 MC_CMD_MAC_NSTATS * sizeof(u64), 1, 0);
544 static void siena_stop_nic_stats(struct efx_nic *efx)
546 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 0);
549 /**************************************************************************
553 **************************************************************************
556 static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
558 struct siena_nic_data *nic_data = efx->nic_data;
560 wol->supported = WAKE_MAGIC;
561 if (nic_data->wol_filter_id != -1)
562 wol->wolopts = WAKE_MAGIC;
565 memset(&wol->sopass, 0, sizeof(wol->sopass));
569 static int siena_set_wol(struct efx_nic *efx, u32 type)
571 struct siena_nic_data *nic_data = efx->nic_data;
574 if (type & ~WAKE_MAGIC)
577 if (type & WAKE_MAGIC) {
578 if (nic_data->wol_filter_id != -1)
579 efx_mcdi_wol_filter_remove(efx,
580 nic_data->wol_filter_id);
581 rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr,
582 &nic_data->wol_filter_id);
586 pci_wake_from_d3(efx->pci_dev, true);
588 rc = efx_mcdi_wol_filter_reset(efx);
589 nic_data->wol_filter_id = -1;
590 pci_wake_from_d3(efx->pci_dev, false);
597 netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n",
603 static void siena_init_wol(struct efx_nic *efx)
605 struct siena_nic_data *nic_data = efx->nic_data;
608 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
611 /* If it failed, attempt to get into a synchronised
612 * state with MC by resetting any set WoL filters */
613 efx_mcdi_wol_filter_reset(efx);
614 nic_data->wol_filter_id = -1;
615 } else if (nic_data->wol_filter_id != -1) {
616 pci_wake_from_d3(efx->pci_dev, true);
621 /**************************************************************************
623 * Revision-dependent attributes used by efx.c and nic.c
625 **************************************************************************
628 const struct efx_nic_type siena_a0_nic_type = {
629 .probe = siena_probe_nic,
630 .remove = siena_remove_nic,
631 .init = siena_init_nic,
632 .fini = efx_port_dummy_op_void,
634 .map_reset_reason = siena_map_reset_reason,
635 .map_reset_flags = siena_map_reset_flags,
636 .reset = siena_reset_hw,
637 .probe_port = siena_probe_port,
638 .remove_port = siena_remove_port,
639 .prepare_flush = siena_prepare_flush,
640 .finish_flush = siena_finish_flush,
641 .update_stats = siena_update_nic_stats,
642 .start_stats = siena_start_nic_stats,
643 .stop_stats = siena_stop_nic_stats,
644 .set_id_led = efx_mcdi_set_id_led,
645 .push_irq_moderation = siena_push_irq_moderation,
646 .push_multicast_hash = siena_push_multicast_hash,
647 .reconfigure_port = efx_mcdi_phy_reconfigure,
648 .get_wol = siena_get_wol,
649 .set_wol = siena_set_wol,
650 .resume_wol = siena_init_wol,
651 .test_registers = siena_test_registers,
652 .test_nvram = efx_mcdi_nvram_test_all,
653 .default_mac_ops = &efx_mcdi_mac_operations,
655 .revision = EFX_REV_SIENA_A0,
656 .mem_map_size = (FR_CZ_MC_TREG_SMEM +
657 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS),
658 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
659 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
660 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
661 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
662 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
663 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
664 .rx_buffer_hash_size = 0x10,
665 .rx_buffer_padding = 0,
666 .max_interrupt_mode = EFX_INT_MODE_MSIX,
667 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
668 * interrupt handler only supports 32
670 .tx_dc_base = 0x88000,
671 .rx_dc_base = 0x68000,
672 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
673 NETIF_F_RXHASH | NETIF_F_NTUPLE),