drivers/net/ethernet/sfc/ef10.c

   1 /****************************************************************************
   2  * Driver for Solarflare network controllers and boards
   3  * Copyright 2012-2013 Solarflare Communications Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published
   7  * by the Free Software Foundation, incorporated herein by reference.
   8  */
   9
  10 #include "net_driver.h"
  11 #include "ef10_regs.h"
  12 #include "io.h"
  13 #include "mcdi.h"
  14 #include "mcdi_pcol.h"
  15 #include "nic.h"
  16 #include "workarounds.h"
  17 #include "selftest.h"
  18 #include <linux/in.h>
  19 #include <linux/jhash.h>
  20 #include <linux/wait.h>
  21 #include <linux/workqueue.h>
  22
  23 /* Hardware control for EF10 architecture including 'Huntington'. */
  24
  25 #define EFX_EF10_DRVGEN_EV              7
  26 enum {
  27         EFX_EF10_TEST = 1,
  28         EFX_EF10_REFILL,
  29 };
  30
  31 /* The reserved RSS context value */
  32 #define EFX_EF10_RSS_CONTEXT_INVALID    0xffffffff
  33
  34 /* The filter table(s) are managed by firmware and we have write-only
  35  * access.  When removing filters we must identify them to the
  36  * firmware by a 64-bit handle, but this is too wide for Linux kernel
  37  * interfaces (32-bit for RX NFC, 16-bit for RFS).  Also, we need to
  38  * be able to tell in advance whether a requested insertion will
  39  * replace an existing filter.  Therefore we maintain a software hash
  40  * table, which should be at least as large as the hardware hash
  41  * table.
  42  *
  43  * Huntington has a single 8K filter table shared between all filter
  44  * types and both ports.
  45  */
  46 #define HUNT_FILTER_TBL_ROWS 8192
  47
  48 struct efx_ef10_filter_table {
  49 /* The RX match field masks supported by this fw & hw, in order of priority */
  50         enum efx_filter_match_flags rx_match_flags[
  51                 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
  52         unsigned int rx_match_count;
  53
  54         struct {
  55                 unsigned long spec;     /* pointer to spec plus flag bits */
  56 /* BUSY flag indicates that an update is in progress.  AUTO_OLD is
  57  * used to mark and sweep MAC filters for the device address lists.
  58  */
  59 #define EFX_EF10_FILTER_FLAG_BUSY       1UL
  60 #define EFX_EF10_FILTER_FLAG_AUTO_OLD   2UL
  61 #define EFX_EF10_FILTER_FLAGS           3UL
  62                 u64 handle;             /* firmware handle */
  63         } *entry;
  64         wait_queue_head_t waitq;
  65 /* Shadow of net_device address lists, guarded by mac_lock */
  66 #define EFX_EF10_FILTER_DEV_UC_MAX      32
  67 #define EFX_EF10_FILTER_DEV_MC_MAX      256
  68         struct {
  69                 u8 addr[ETH_ALEN];
  70                 u16 id;
  71         } dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX],
  72           dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
  73         int dev_uc_count;               /* negative for PROMISC */
  74         int dev_mc_count;               /* negative for PROMISC/ALLMULTI */
  75 };
  76
  77 /* An arbitrary search limit for the software hash table */
  78 #define EFX_EF10_FILTER_SEARCH_LIMIT 200
  79
  80 static void efx_ef10_rx_push_rss_config(struct efx_nic *efx);
  81 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
  82 static void efx_ef10_filter_table_remove(struct efx_nic *efx);
  83
  84 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
  85 {
  86         efx_dword_t reg;
  87
  88         efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
  89         return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
  90                 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
  91 }
  92
  93 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
  94 {
  95         return resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]);
  96 }
  97
  98 static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
  99 {
 100         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN);
 101         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 102         size_t outlen;
 103         int rc;
 104
 105         BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
 106
 107         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
 108                           outbuf, sizeof(outbuf), &outlen);
 109         if (rc)
 110                 return rc;
 111         if (outlen < sizeof(outbuf)) {
 112                 netif_err(efx, drv, efx->net_dev,
 113                           "unable to read datapath firmware capabilities\n");
 114                 return -EIO;
 115         }
 116
 117         nic_data->datapath_caps =
 118                 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
 119
 120         if (!(nic_data->datapath_caps &
 121               (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) {
 122                 netif_err(efx, drv, efx->net_dev,
 123                           "current firmware does not support TSO\n");
 124                 return -ENODEV;
 125         }
 126
 127         if (!(nic_data->datapath_caps &
 128               (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
 129                 netif_err(efx, probe, efx->net_dev,
 130                           "current firmware does not support an RX prefix\n");
 131                 return -ENODEV;
 132         }
 133
 134         return 0;
 135 }
 136
 137 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
 138 {
 139         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
 140         int rc;
 141
 142         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
 143                           outbuf, sizeof(outbuf), NULL);
 144         if (rc)
 145                 return rc;
 146         rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
 147         return rc > 0 ? rc : -ERANGE;
 148 }
 149
 150 static int efx_ef10_get_mac_address(struct efx_nic *efx, u8 *mac_address)
 151 {
 152         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
 153         size_t outlen;
 154         int rc;
 155
 156         BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
 157
 158         rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
 159                           outbuf, sizeof(outbuf), &outlen);
 160         if (rc)
 161                 return rc;
 162         if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
 163                 return -EIO;
 164
 165         ether_addr_copy(mac_address,
 166                         MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
 167         return 0;
 168 }
 169
 170 static int efx_ef10_probe(struct efx_nic *efx)
 171 {
 172         struct efx_ef10_nic_data *nic_data;
 173         int i, rc;
 174
 175         /* We can have one VI for each 8K region.  However, until we
 176          * use TX option descriptors we need two TX queues per channel.
 177          */
 178         efx->max_channels =
 179                 min_t(unsigned int,
 180                       EFX_MAX_CHANNELS,
 181                       resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]) /
 182                       (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
 183         BUG_ON(efx->max_channels == 0);
 184
 185         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
 186         if (!nic_data)
 187                 return -ENOMEM;
 188         efx->nic_data = nic_data;
 189
 190         rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
 191                                   8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
 192         if (rc)
 193                 goto fail1;
 194
 195         /* Get the MC's warm boot count.  In case it's rebooting right
 196          * now, be prepared to retry.
 197          */
 198         i = 0;
 199         for (;;) {
 200                 rc = efx_ef10_get_warm_boot_count(efx);
 201                 if (rc >= 0)
 202                         break;
 203                 if (++i == 5)
 204                         goto fail2;
 205                 ssleep(1);
 206         }
 207         nic_data->warm_boot_count = rc;
 208
 209         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
 210
 211         /* In case we're recovering from a crash (kexec), we want to
 212          * cancel any outstanding request by the previous user of this
 213          * function.  We send a special message using the least
 214          * significant bits of the 'high' (doorbell) register.
 215          */
 216         _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
 217
 218         rc = efx_mcdi_init(efx);
 219         if (rc)
 220                 goto fail2;
 221
 222         /* Reset (most) configuration for this function */
 223         rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
 224         if (rc)
 225                 goto fail3;
 226
 227         /* Enable event logging */
 228         rc = efx_mcdi_log_ctrl(efx, true, false, 0);
 229         if (rc)
 230                 goto fail3;
 231
 232         rc = efx_ef10_init_datapath_caps(efx);
 233         if (rc < 0)
 234                 goto fail3;
 235
 236         efx->rx_packet_len_offset =
 237                 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
 238
 239         rc = efx_mcdi_port_get_number(efx);
 240         if (rc < 0)
 241                 goto fail3;
 242         efx->port_num = rc;
 243
 244         rc = efx_ef10_get_mac_address(efx, efx->net_dev->perm_addr);
 245         if (rc)
 246                 goto fail3;
 247
 248         rc = efx_ef10_get_sysclk_freq(efx);
 249         if (rc < 0)
 250                 goto fail3;
 251         efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */
 252
 253         /* Check whether firmware supports bug 35388 workaround */
 254         rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true);
 255         if (rc == 0)
 256                 nic_data->workaround_35388 = true;
 257         else if (rc != -ENOSYS && rc != -ENOENT)
 258                 goto fail3;
 259         netif_dbg(efx, probe, efx->net_dev,
 260                   "workaround for bug 35388 is %sabled\n",
 261                   nic_data->workaround_35388 ? "en" : "dis");
 262
 263         rc = efx_mcdi_mon_probe(efx);
 264         if (rc)
 265                 goto fail3;
 266
 267         efx_ptp_probe(efx, NULL);
 268
 269         return 0;
 270
 271 fail3:
 272         efx_mcdi_fini(efx);
 273 fail2:
 274         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
 275 fail1:
 276         kfree(nic_data);
 277         efx->nic_data = NULL;
 278         return rc;
 279 }
 280
 281 static int efx_ef10_free_vis(struct efx_nic *efx)
 282 {
 283         MCDI_DECLARE_BUF_OUT_OR_ERR(outbuf, 0);
 284         size_t outlen;
 285         int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
 286                                     outbuf, sizeof(outbuf), &outlen);
 287
 288         /* -EALREADY means nothing to free, so ignore */
 289         if (rc == -EALREADY)
 290                 rc = 0;
 291         if (rc)
 292                 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
 293                                        rc);
 294         return rc;
 295 }
 296
 297 #ifdef EFX_USE_PIO
 298
 299 static void efx_ef10_free_piobufs(struct efx_nic *efx)
 300 {
 301         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 302         MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
 303         unsigned int i;
 304         int rc;
 305
 306         BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
 307
 308         for (i = 0; i < nic_data->n_piobufs; i++) {
 309                 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
 310                                nic_data->piobuf_handle[i]);
 311                 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
 312                                   NULL, 0, NULL);
 313                 WARN_ON(rc);
 314         }
 315
 316         nic_data->n_piobufs = 0;
 317 }
 318
 319 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
 320 {
 321         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 322         MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
 323         unsigned int i;
 324         size_t outlen;
 325         int rc = 0;
 326
 327         BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
 328
 329         for (i = 0; i < n; i++) {
 330                 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
 331                                   outbuf, sizeof(outbuf), &outlen);
 332                 if (rc)
 333                         break;
 334                 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
 335                         rc = -EIO;
 336                         break;
 337                 }
 338                 nic_data->piobuf_handle[i] =
 339                         MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
 340                 netif_dbg(efx, probe, efx->net_dev,
 341                           "allocated PIO buffer %u handle %x\n", i,
 342                           nic_data->piobuf_handle[i]);
 343         }
 344
 345         nic_data->n_piobufs = i;
 346         if (rc)
 347                 efx_ef10_free_piobufs(efx);
 348         return rc;
 349 }
 350
 351 static int efx_ef10_link_piobufs(struct efx_nic *efx)
 352 {
 353         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 354         MCDI_DECLARE_BUF(inbuf,
 355                          max(MC_CMD_LINK_PIOBUF_IN_LEN,
 356                              MC_CMD_UNLINK_PIOBUF_IN_LEN));
 357         struct efx_channel *channel;
 358         struct efx_tx_queue *tx_queue;
 359         unsigned int offset, index;
 360         int rc;
 361
 362         BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
 363         BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
 364
 365         /* Link a buffer to each VI in the write-combining mapping */
 366         for (index = 0; index < nic_data->n_piobufs; ++index) {
 367                 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
 368                                nic_data->piobuf_handle[index]);
 369                 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
 370                                nic_data->pio_write_vi_base + index);
 371                 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
 372                                   inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
 373                                   NULL, 0, NULL);
 374                 if (rc) {
 375                         netif_err(efx, drv, efx->net_dev,
 376                                   "failed to link VI %u to PIO buffer %u (%d)\n",
 377                                   nic_data->pio_write_vi_base + index, index,
 378                                   rc);
 379                         goto fail;
 380                 }
 381                 netif_dbg(efx, probe, efx->net_dev,
 382                           "linked VI %u to PIO buffer %u\n",
 383                           nic_data->pio_write_vi_base + index, index);
 384         }
 385
 386         /* Link a buffer to each TX queue */
 387         efx_for_each_channel(channel, efx) {
 388                 efx_for_each_channel_tx_queue(tx_queue, channel) {
 389                         /* We assign the PIO buffers to queues in
 390                          * reverse order to allow for the following
 391                          * special case.
 392                          */
 393                         offset = ((efx->tx_channel_offset + efx->n_tx_channels -
 394                                    tx_queue->channel->channel - 1) *
 395                                   efx_piobuf_size);
 396                         index = offset / ER_DZ_TX_PIOBUF_SIZE;
 397                         offset = offset % ER_DZ_TX_PIOBUF_SIZE;
 398
 399                         /* When the host page size is 4K, the first
 400                          * host page in the WC mapping may be within
 401                          * the same VI page as the last TX queue.  We
 402                          * can only link one buffer to each VI.
 403                          */
 404                         if (tx_queue->queue == nic_data->pio_write_vi_base) {
 405                                 BUG_ON(index != 0);
 406                                 rc = 0;
 407                         } else {
 408                                 MCDI_SET_DWORD(inbuf,
 409                                                LINK_PIOBUF_IN_PIOBUF_HANDLE,
 410                                                nic_data->piobuf_handle[index]);
 411                                 MCDI_SET_DWORD(inbuf,
 412                                                LINK_PIOBUF_IN_TXQ_INSTANCE,
 413                                                tx_queue->queue);
 414                                 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
 415                                                   inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
 416                                                   NULL, 0, NULL);
 417                         }
 418
 419                         if (rc) {
 420                                 /* This is non-fatal; the TX path just
 421                                  * won't use PIO for this queue
 422                                  */
 423                                 netif_err(efx, drv, efx->net_dev,
 424                                           "failed to link VI %u to PIO buffer %u (%d)\n",
 425                                           tx_queue->queue, index, rc);
 426                                 tx_queue->piobuf = NULL;
 427                         } else {
 428                                 tx_queue->piobuf =
 429                                         nic_data->pio_write_base +
 430                                         index * EFX_VI_PAGE_SIZE + offset;
 431                                 tx_queue->piobuf_offset = offset;
 432                                 netif_dbg(efx, probe, efx->net_dev,
 433                                           "linked VI %u to PIO buffer %u offset %x addr %p\n",
 434                                           tx_queue->queue, index,
 435                                           tx_queue->piobuf_offset,
 436                                           tx_queue->piobuf);
 437                         }
 438                 }
 439         }
 440
 441         return 0;
 442
 443 fail:
 444         while (index--) {
 445                 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
 446                                nic_data->pio_write_vi_base + index);
 447                 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
 448                              inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
 449                              NULL, 0, NULL);
 450         }
 451         return rc;
 452 }
 453
 454 #else /* !EFX_USE_PIO */
 455
 456 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
 457 {
 458         return n == 0 ? 0 : -ENOBUFS;
 459 }
 460
 461 static int efx_ef10_link_piobufs(struct efx_nic *efx)
 462 {
 463         return 0;
 464 }
 465
 466 static void efx_ef10_free_piobufs(struct efx_nic *efx)
 467 {
 468 }
 469
 470 #endif /* EFX_USE_PIO */
 471
 472 static void efx_ef10_remove(struct efx_nic *efx)
 473 {
 474         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 475         int rc;
 476
 477         efx_ptp_remove(efx);
 478
 479         efx_mcdi_mon_remove(efx);
 480
 481         efx_ef10_rx_free_indir_table(efx);
 482
 483         if (nic_data->wc_membase)
 484                 iounmap(nic_data->wc_membase);
 485
 486         rc = efx_ef10_free_vis(efx);
 487         WARN_ON(rc != 0);
 488
 489         if (!nic_data->must_restore_piobufs)
 490                 efx_ef10_free_piobufs(efx);
 491
 492         efx_mcdi_fini(efx);
 493         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
 494         kfree(nic_data);
 495 }
 496
 497 static int efx_ef10_alloc_vis(struct efx_nic *efx,
 498                               unsigned int min_vis, unsigned int max_vis)
 499 {
 500         MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
 501         MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
 502         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 503         size_t outlen;
 504         int rc;
 505
 506         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
 507         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
 508         rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
 509                           outbuf, sizeof(outbuf), &outlen);
 510         if (rc != 0)
 511                 return rc;
 512
 513         if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
 514                 return -EIO;
 515
 516         netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
 517                   MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
 518
 519         nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
 520         nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
 521         return 0;
 522 }
 523
 524 /* Note that the failure path of this function does not free
 525  * resources, as this will be done by efx_ef10_remove().
 526  */
 527 static int efx_ef10_dimension_resources(struct efx_nic *efx)
 528 {
 529         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 530         unsigned int uc_mem_map_size, wc_mem_map_size;
 531         unsigned int min_vis, pio_write_vi_base, max_vis;
 532         void __iomem *membase;
 533         int rc;
 534
 535         min_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
 536
 537 #ifdef EFX_USE_PIO
 538         /* Try to allocate PIO buffers if wanted and if the full
 539          * number of PIO buffers would be sufficient to allocate one
 540          * copy-buffer per TX channel.  Failure is non-fatal, as there
 541          * are only a small number of PIO buffers shared between all
 542          * functions of the controller.
 543          */
 544         if (efx_piobuf_size != 0 &&
 545             ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
 546             efx->n_tx_channels) {
 547                 unsigned int n_piobufs =
 548                         DIV_ROUND_UP(efx->n_tx_channels,
 549                                      ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
 550
 551                 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
 552                 if (rc)
 553                         netif_err(efx, probe, efx->net_dev,
 554                                   "failed to allocate PIO buffers (%d)\n", rc);
 555                 else
 556                         netif_dbg(efx, probe, efx->net_dev,
 557                                   "allocated %u PIO buffers\n", n_piobufs);
 558         }
 559 #else
 560         nic_data->n_piobufs = 0;
 561 #endif
 562
 563         /* PIO buffers should be mapped with write-combining enabled,
 564          * and we want to make single UC and WC mappings rather than
 565          * several of each (in fact that's the only option if host
 566          * page size is >4K).  So we may allocate some extra VIs just
 567          * for writing PIO buffers through.
 568          *
 569          * The UC mapping contains (min_vis - 1) complete VIs and the
 570          * first half of the next VI.  Then the WC mapping begins with
 571          * the second half of this last VI.
 572          */
 573         uc_mem_map_size = PAGE_ALIGN((min_vis - 1) * EFX_VI_PAGE_SIZE +
 574                                      ER_DZ_TX_PIOBUF);
 575         if (nic_data->n_piobufs) {
 576                 /* pio_write_vi_base rounds down to give the number of complete
 577                  * VIs inside the UC mapping.
 578                  */
 579                 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
 580                 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
 581                                                nic_data->n_piobufs) *
 582                                               EFX_VI_PAGE_SIZE) -
 583                                    uc_mem_map_size);
 584                 max_vis = pio_write_vi_base + nic_data->n_piobufs;
 585         } else {
 586                 pio_write_vi_base = 0;
 587                 wc_mem_map_size = 0;
 588                 max_vis = min_vis;
 589         }
 590
 591         /* In case the last attached driver failed to free VIs, do it now */
 592         rc = efx_ef10_free_vis(efx);
 593         if (rc != 0)
 594                 return rc;
 595
 596         rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
 597         if (rc != 0)
 598                 return rc;
 599
 600         /* If we didn't get enough VIs to map all the PIO buffers, free the
 601          * PIO buffers
 602          */
 603         if (nic_data->n_piobufs &&
 604             nic_data->n_allocated_vis <
 605             pio_write_vi_base + nic_data->n_piobufs) {
 606                 netif_dbg(efx, probe, efx->net_dev,
 607                           "%u VIs are not sufficient to map %u PIO buffers\n",
 608                           nic_data->n_allocated_vis, nic_data->n_piobufs);
 609                 efx_ef10_free_piobufs(efx);
 610         }
 611
 612         /* Shrink the original UC mapping of the memory BAR */
 613         membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
 614         if (!membase) {
 615                 netif_err(efx, probe, efx->net_dev,
 616                           "could not shrink memory BAR to %x\n",
 617                           uc_mem_map_size);
 618                 return -ENOMEM;
 619         }
 620         iounmap(efx->membase);
 621         efx->membase = membase;
 622
 623         /* Set up the WC mapping if needed */
 624         if (wc_mem_map_size) {
 625                 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
 626                                                   uc_mem_map_size,
 627                                                   wc_mem_map_size);
 628                 if (!nic_data->wc_membase) {
 629                         netif_err(efx, probe, efx->net_dev,
 630                                   "could not allocate WC mapping of size %x\n",
 631                                   wc_mem_map_size);
 632                         return -ENOMEM;
 633                 }
 634                 nic_data->pio_write_vi_base = pio_write_vi_base;
 635                 nic_data->pio_write_base =
 636                         nic_data->wc_membase +
 637                         (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
 638                          uc_mem_map_size);
 639
 640                 rc = efx_ef10_link_piobufs(efx);
 641                 if (rc)
 642                         efx_ef10_free_piobufs(efx);
 643         }
 644
 645         netif_dbg(efx, probe, efx->net_dev,
 646                   "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
 647                   &efx->membase_phys, efx->membase, uc_mem_map_size,
 648                   nic_data->wc_membase, wc_mem_map_size);
 649
 650         return 0;
 651 }
 652
 653 static int efx_ef10_init_nic(struct efx_nic *efx)
 654 {
 655         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 656         int rc;
 657
 658         if (nic_data->must_check_datapath_caps) {
 659                 rc = efx_ef10_init_datapath_caps(efx);
 660                 if (rc)
 661                         return rc;
 662                 nic_data->must_check_datapath_caps = false;
 663         }
 664
 665         if (nic_data->must_realloc_vis) {
 666                 /* We cannot let the number of VIs change now */
 667                 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
 668                                         nic_data->n_allocated_vis);
 669                 if (rc)
 670                         return rc;
 671                 nic_data->must_realloc_vis = false;
 672         }
 673
 674         if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
 675                 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
 676                 if (rc == 0) {
 677                         rc = efx_ef10_link_piobufs(efx);
 678                         if (rc)
 679                                 efx_ef10_free_piobufs(efx);
 680                 }
 681
 682                 /* Log an error on failure, but this is non-fatal */
 683                 if (rc)
 684                         netif_err(efx, drv, efx->net_dev,
 685                                   "failed to restore PIO buffers (%d)\n", rc);
 686                 nic_data->must_restore_piobufs = false;
 687         }
 688
 689         efx_ef10_rx_push_rss_config(efx);
 690         return 0;
 691 }
 692
 693 static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
 694 {
 695         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 696
 697         /* All our allocations have been reset */
 698         nic_data->must_realloc_vis = true;
 699         nic_data->must_restore_filters = true;
 700         nic_data->must_restore_piobufs = true;
 701         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
 702 }
 703
 704 static int efx_ef10_map_reset_flags(u32 *flags)
 705 {
 706         enum {
 707                 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
 708                                    ETH_RESET_SHARED_SHIFT),
 709                 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
 710                                   ETH_RESET_OFFLOAD | ETH_RESET_MAC |
 711                                   ETH_RESET_PHY | ETH_RESET_MGMT) <<
 712                                  ETH_RESET_SHARED_SHIFT)
 713         };
 714
 715         /* We assume for now that our PCI function is permitted to
 716          * reset everything.
 717          */
 718
 719         if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
 720                 *flags &= ~EF10_RESET_MC;
 721                 return RESET_TYPE_WORLD;
 722         }
 723
 724         if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
 725                 *flags &= ~EF10_RESET_PORT;
 726                 return RESET_TYPE_ALL;
 727         }
 728
 729         /* no invisible reset implemented */
 730
 731         return -EINVAL;
 732 }
 733
 734 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
 735 {
 736         int rc = efx_mcdi_reset(efx, reset_type);
 737
 738         /* If it was a port reset, trigger reallocation of MC resources.
 739          * Note that on an MC reset nothing needs to be done now because we'll
 740          * detect the MC reset later and handle it then.
 741          * For an FLR, we never get an MC reset event, but the MC has reset all
 742          * resources assigned to us, so we have to trigger reallocation now.
 743          */
 744         if ((reset_type == RESET_TYPE_ALL ||
 745              reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
 746                 efx_ef10_reset_mc_allocations(efx);
 747         return rc;
 748 }
 749
 750 #define EF10_DMA_STAT(ext_name, mcdi_name)                      \
 751         [EF10_STAT_ ## ext_name] =                              \
 752         { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
 753 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name)                \
 754         [EF10_STAT_ ## int_name] =                              \
 755         { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
 756 #define EF10_OTHER_STAT(ext_name)                               \
 757         [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
 758
 759 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
 760         EF10_DMA_STAT(tx_bytes, TX_BYTES),
 761         EF10_DMA_STAT(tx_packets, TX_PKTS),
 762         EF10_DMA_STAT(tx_pause, TX_PAUSE_PKTS),
 763         EF10_DMA_STAT(tx_control, TX_CONTROL_PKTS),
 764         EF10_DMA_STAT(tx_unicast, TX_UNICAST_PKTS),
 765         EF10_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS),
 766         EF10_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS),
 767         EF10_DMA_STAT(tx_lt64, TX_LT64_PKTS),
 768         EF10_DMA_STAT(tx_64, TX_64_PKTS),
 769         EF10_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS),
 770         EF10_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS),
 771         EF10_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS),
 772         EF10_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS),
 773         EF10_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
 774         EF10_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
 775         EF10_DMA_STAT(rx_bytes, RX_BYTES),
 776         EF10_DMA_INVIS_STAT(rx_bytes_minus_good_bytes, RX_BAD_BYTES),
 777         EF10_OTHER_STAT(rx_good_bytes),
 778         EF10_OTHER_STAT(rx_bad_bytes),
 779         EF10_DMA_STAT(rx_packets, RX_PKTS),
 780         EF10_DMA_STAT(rx_good, RX_GOOD_PKTS),
 781         EF10_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS),
 782         EF10_DMA_STAT(rx_pause, RX_PAUSE_PKTS),
 783         EF10_DMA_STAT(rx_control, RX_CONTROL_PKTS),
 784         EF10_DMA_STAT(rx_unicast, RX_UNICAST_PKTS),
 785         EF10_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS),
 786         EF10_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS),
 787         EF10_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS),
 788         EF10_DMA_STAT(rx_64, RX_64_PKTS),
 789         EF10_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS),
 790         EF10_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS),
 791         EF10_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS),
 792         EF10_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS),
 793         EF10_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
 794         EF10_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
 795         EF10_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS),
 796         EF10_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS),
 797         EF10_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS),
 798         EF10_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS),
 799         EF10_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS),
 800         EF10_DMA_STAT(rx_nodesc_drops, RX_NODESC_DROPS),
 801         EF10_DMA_STAT(rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
 802         EF10_DMA_STAT(rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
 803         EF10_DMA_STAT(rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
 804         EF10_DMA_STAT(rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
 805         EF10_DMA_STAT(rx_pm_trunc_qbb, PM_TRUNC_QBB),
 806         EF10_DMA_STAT(rx_pm_discard_qbb, PM_DISCARD_QBB),
 807         EF10_DMA_STAT(rx_pm_discard_mapping, PM_DISCARD_MAPPING),
 808         EF10_DMA_STAT(rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
 809         EF10_DMA_STAT(rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
 810         EF10_DMA_STAT(rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
 811         EF10_DMA_STAT(rx_dp_hlb_fetch, RXDP_EMERGENCY_FETCH_CONDITIONS),
 812         EF10_DMA_STAT(rx_dp_hlb_wait, RXDP_EMERGENCY_WAIT_CONDITIONS),
 813 };
 814
 815 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_tx_bytes) |           \
 816                                (1ULL << EF10_STAT_tx_packets) |         \
 817                                (1ULL << EF10_STAT_tx_pause) |           \
 818                                (1ULL << EF10_STAT_tx_unicast) |         \
 819                                (1ULL << EF10_STAT_tx_multicast) |       \
 820                                (1ULL << EF10_STAT_tx_broadcast) |       \
 821                                (1ULL << EF10_STAT_rx_bytes) |           \
 822                                (1ULL << EF10_STAT_rx_bytes_minus_good_bytes) | \
 823                                (1ULL << EF10_STAT_rx_good_bytes) |      \
 824                                (1ULL << EF10_STAT_rx_bad_bytes) |       \
 825                                (1ULL << EF10_STAT_rx_packets) |         \
 826                                (1ULL << EF10_STAT_rx_good) |            \
 827                                (1ULL << EF10_STAT_rx_bad) |             \
 828                                (1ULL << EF10_STAT_rx_pause) |           \
 829                                (1ULL << EF10_STAT_rx_control) |         \
 830                                (1ULL << EF10_STAT_rx_unicast) |         \
 831                                (1ULL << EF10_STAT_rx_multicast) |       \
 832                                (1ULL << EF10_STAT_rx_broadcast) |       \
 833                                (1ULL << EF10_STAT_rx_lt64) |            \
 834                                (1ULL << EF10_STAT_rx_64) |              \
 835                                (1ULL << EF10_STAT_rx_65_to_127) |       \
 836                                (1ULL << EF10_STAT_rx_128_to_255) |      \
 837                                (1ULL << EF10_STAT_rx_256_to_511) |      \
 838                                (1ULL << EF10_STAT_rx_512_to_1023) |     \
 839                                (1ULL << EF10_STAT_rx_1024_to_15xx) |    \
 840                                (1ULL << EF10_STAT_rx_15xx_to_jumbo) |   \
 841                                (1ULL << EF10_STAT_rx_gtjumbo) |         \
 842                                (1ULL << EF10_STAT_rx_bad_gtjumbo) |     \
 843                                (1ULL << EF10_STAT_rx_overflow) |        \
 844                                (1ULL << EF10_STAT_rx_nodesc_drops))
 845
 846 /* These statistics are only provided by the 10G MAC.  For a 10G/40G
 847  * switchable port we do not expose these because they might not
 848  * include all the packets they should.
 849  */
 850 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_tx_control) |       \
 851                                  (1ULL << EF10_STAT_tx_lt64) |          \
 852                                  (1ULL << EF10_STAT_tx_64) |            \
 853                                  (1ULL << EF10_STAT_tx_65_to_127) |     \
 854                                  (1ULL << EF10_STAT_tx_128_to_255) |    \
 855                                  (1ULL << EF10_STAT_tx_256_to_511) |    \
 856                                  (1ULL << EF10_STAT_tx_512_to_1023) |   \
 857                                  (1ULL << EF10_STAT_tx_1024_to_15xx) |  \
 858                                  (1ULL << EF10_STAT_tx_15xx_to_jumbo))
 859
 860 /* These statistics are only provided by the 40G MAC.  For a 10G/40G
 861  * switchable port we do expose these because the errors will otherwise
 862  * be silent.
 863  */
 864 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_rx_align_error) |  \
 865                                   (1ULL << EF10_STAT_rx_length_error))
 866
 867 /* These statistics are only provided if the firmware supports the
 868  * capability PM_AND_RXDP_COUNTERS.
 869  */
 870 #define HUNT_PM_AND_RXDP_STAT_MASK (                                    \
 871         (1ULL << EF10_STAT_rx_pm_trunc_bb_overflow) |                   \
 872         (1ULL << EF10_STAT_rx_pm_discard_bb_overflow) |                 \
 873         (1ULL << EF10_STAT_rx_pm_trunc_vfifo_full) |                    \
 874         (1ULL << EF10_STAT_rx_pm_discard_vfifo_full) |                  \
 875         (1ULL << EF10_STAT_rx_pm_trunc_qbb) |                           \
 876         (1ULL << EF10_STAT_rx_pm_discard_qbb) |                         \
 877         (1ULL << EF10_STAT_rx_pm_discard_mapping) |                     \
 878         (1ULL << EF10_STAT_rx_dp_q_disabled_packets) |                  \
 879         (1ULL << EF10_STAT_rx_dp_di_dropped_packets) |                  \
 880         (1ULL << EF10_STAT_rx_dp_streaming_packets) |                   \
 881         (1ULL << EF10_STAT_rx_dp_hlb_fetch) |                           \
 882         (1ULL << EF10_STAT_rx_dp_hlb_wait))
 883
 884 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
 885 {
 886         u64 raw_mask = HUNT_COMMON_STAT_MASK;
 887         u32 port_caps = efx_mcdi_phy_get_caps(efx);
 888         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 889
 890         if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
 891                 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
 892         else
 893                 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
 894
 895         if (nic_data->datapath_caps &
 896             (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
 897                 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
 898
 899         return raw_mask;
 900 }
 901
 902 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
 903 {
 904         u64 raw_mask = efx_ef10_raw_stat_mask(efx);
 905
 906 #if BITS_PER_LONG == 64
 907         mask[0] = raw_mask;
 908 #else
 909         mask[0] = raw_mask & 0xffffffff;
 910         mask[1] = raw_mask >> 32;
 911 #endif
 912 }
 913
 914 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
 915 {
 916         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
 917
 918         efx_ef10_get_stat_mask(efx, mask);
 919         return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
 920                                       mask, names);
 921 }
 922
 923 static int efx_ef10_try_update_nic_stats(struct efx_nic *efx)
 924 {
 925         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 926         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
 927         __le64 generation_start, generation_end;
 928         u64 *stats = nic_data->stats;
 929         __le64 *dma_stats;
 930
 931         efx_ef10_get_stat_mask(efx, mask);
 932
 933         dma_stats = efx->stats_buffer.addr;
 934         nic_data = efx->nic_data;
 935
 936         generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
 937         if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
 938                 return 0;
 939         rmb();
 940         efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
 941                              stats, efx->stats_buffer.addr, false);
 942         rmb();
 943         generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
 944         if (generation_end != generation_start)
 945                 return -EAGAIN;
 946
 947         /* Update derived statistics */
 948         efx_nic_fix_nodesc_drop_stat(efx, &stats[EF10_STAT_rx_nodesc_drops]);
 949         stats[EF10_STAT_rx_good_bytes] =
 950                 stats[EF10_STAT_rx_bytes] -
 951                 stats[EF10_STAT_rx_bytes_minus_good_bytes];
 952         efx_update_diff_stat(&stats[EF10_STAT_rx_bad_bytes],
 953                              stats[EF10_STAT_rx_bytes_minus_good_bytes]);
 954
 955         return 0;
 956 }
 957
 958
 959 static size_t efx_ef10_update_stats(struct efx_nic *efx, u64 *full_stats,
 960                                     struct rtnl_link_stats64 *core_stats)
 961 {
 962         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
 963         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 964         u64 *stats = nic_data->stats;
 965         size_t stats_count = 0, index;
 966         int retry;
 967
 968         efx_ef10_get_stat_mask(efx, mask);
 969
 970         /* If we're unlucky enough to read statistics during the DMA, wait
 971          * up to 10ms for it to finish (typically takes <500us)
 972          */
 973         for (retry = 0; retry < 100; ++retry) {
 974                 if (efx_ef10_try_update_nic_stats(efx) == 0)
 975                         break;
 976                 udelay(100);
 977         }
 978
 979         if (full_stats) {
 980                 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
 981                         if (efx_ef10_stat_desc[index].name) {
 982                                 *full_stats++ = stats[index];
 983                                 ++stats_count;
 984                         }
 985                 }
 986         }
 987
 988         if (core_stats) {
 989                 core_stats->rx_packets = stats[EF10_STAT_rx_packets];
 990                 core_stats->tx_packets = stats[EF10_STAT_tx_packets];
 991                 core_stats->rx_bytes = stats[EF10_STAT_rx_bytes];
 992                 core_stats->tx_bytes = stats[EF10_STAT_tx_bytes];
 993                 core_stats->rx_dropped = stats[EF10_STAT_rx_nodesc_drops];
 994                 core_stats->multicast = stats[EF10_STAT_rx_multicast];
 995                 core_stats->rx_length_errors =
 996                         stats[EF10_STAT_rx_gtjumbo] +
 997                         stats[EF10_STAT_rx_length_error];
 998                 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
 999                 core_stats->rx_frame_errors = stats[EF10_STAT_rx_align_error];
1000                 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1001                 core_stats->rx_errors = (core_stats->rx_length_errors +
1002                                          core_stats->rx_crc_errors +
1003                                          core_stats->rx_frame_errors);
1004         }
1005
1006         return stats_count;
1007 }
1008
1009 static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1010 {
1011         struct efx_nic *efx = channel->efx;
1012         unsigned int mode, value;
1013         efx_dword_t timer_cmd;
1014
1015         if (channel->irq_moderation) {
1016                 mode = 3;
1017                 value = channel->irq_moderation - 1;
1018         } else {
1019                 mode = 0;
1020                 value = 0;
1021         }
1022
1023         if (EFX_EF10_WORKAROUND_35388(efx)) {
1024                 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1025                                      EFE_DD_EVQ_IND_TIMER_FLAGS,
1026                                      ERF_DD_EVQ_IND_TIMER_MODE, mode,
1027                                      ERF_DD_EVQ_IND_TIMER_VAL, value);
1028                 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1029                                 channel->channel);
1030         } else {
1031                 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1032                                      ERF_DZ_TC_TIMER_VAL, value);
1033                 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1034                                 channel->channel);
1035         }
1036 }
1037
1038 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1039 {
1040         wol->supported = 0;
1041         wol->wolopts = 0;
1042         memset(&wol->sopass, 0, sizeof(wol->sopass));
1043 }
1044
1045 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1046 {
1047         if (type != 0)
1048                 return -EINVAL;
1049         return 0;
1050 }
1051
1052 static void efx_ef10_mcdi_request(struct efx_nic *efx,
1053                                   const efx_dword_t *hdr, size_t hdr_len,
1054                                   const efx_dword_t *sdu, size_t sdu_len)
1055 {
1056         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1057         u8 *pdu = nic_data->mcdi_buf.addr;
1058
1059         memcpy(pdu, hdr, hdr_len);
1060         memcpy(pdu + hdr_len, sdu, sdu_len);
1061         wmb();
1062
1063         /* The hardware provides 'low' and 'high' (doorbell) registers
1064          * for passing the 64-bit address of an MCDI request to
1065          * firmware.  However the dwords are swapped by firmware.  The
1066          * least significant bits of the doorbell are then 0 for all
1067          * MCDI requests due to alignment.
1068          */
1069         _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1070                     ER_DZ_MC_DB_LWRD);
1071         _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1072                     ER_DZ_MC_DB_HWRD);
1073 }
1074
1075 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1076 {
1077         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1078         const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1079
1080         rmb();
1081         return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1082 }
1083
1084 static void
1085 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1086                             size_t offset, size_t outlen)
1087 {
1088         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1089         const u8 *pdu = nic_data->mcdi_buf.addr;
1090
1091         memcpy(outbuf, pdu + offset, outlen);
1092 }
1093
1094 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1095 {
1096         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1097         int rc;
1098
1099         rc = efx_ef10_get_warm_boot_count(efx);
1100         if (rc < 0) {
1101                 /* The firmware is presumably in the process of
1102                  * rebooting.  However, we are supposed to report each
1103                  * reboot just once, so we must only do that once we
1104                  * can read and store the updated warm boot count.
1105                  */
1106                 return 0;
1107         }
1108
1109         if (rc == nic_data->warm_boot_count)
1110                 return 0;
1111
1112         nic_data->warm_boot_count = rc;
1113
1114         /* All our allocations have been reset */
1115         efx_ef10_reset_mc_allocations(efx);
1116
1117         /* The datapath firmware might have been changed */
1118         nic_data->must_check_datapath_caps = true;
1119
1120         /* MAC statistics have been cleared on the NIC; clear the local
1121          * statistic that we update with efx_update_diff_stat().
1122          */
1123         nic_data->stats[EF10_STAT_rx_bad_bytes] = 0;
1124
1125         return -EIO;
1126 }
1127
1128 /* Handle an MSI interrupt
1129  *
1130  * Handle an MSI hardware interrupt.  This routine schedules event
1131  * queue processing.  No interrupt acknowledgement cycle is necessary.
1132  * Also, we never need to check that the interrupt is for us, since
1133  * MSI interrupts cannot be shared.
1134  */
1135 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
1136 {
1137         struct efx_msi_context *context = dev_id;
1138         struct efx_nic *efx = context->efx;
1139
1140         netif_vdbg(efx, intr, efx->net_dev,
1141                    "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
1142
1143         if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
1144                 /* Note test interrupts */
1145                 if (context->index == efx->irq_level)
1146                         efx->last_irq_cpu = raw_smp_processor_id();
1147
1148                 /* Schedule processing of the channel */
1149                 efx_schedule_channel_irq(efx->channel[context->index]);
1150         }
1151
1152         return IRQ_HANDLED;
1153 }
1154
1155 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
1156 {
1157         struct efx_nic *efx = dev_id;
1158         bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
1159         struct efx_channel *channel;
1160         efx_dword_t reg;
1161         u32 queues;
1162
1163         /* Read the ISR which also ACKs the interrupts */
1164         efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
1165         queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
1166
1167         if (queues == 0)
1168                 return IRQ_NONE;
1169
1170         if (likely(soft_enabled)) {
1171                 /* Note test interrupts */
1172                 if (queues & (1U << efx->irq_level))
1173                         efx->last_irq_cpu = raw_smp_processor_id();
1174
1175                 efx_for_each_channel(channel, efx) {
1176                         if (queues & 1)
1177                                 efx_schedule_channel_irq(channel);
1178                         queues >>= 1;
1179                 }
1180         }
1181
1182         netif_vdbg(efx, intr, efx->net_dev,
1183                    "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1184                    irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1185
1186         return IRQ_HANDLED;
1187 }
1188
1189 static void efx_ef10_irq_test_generate(struct efx_nic *efx)
1190 {
1191         MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
1192
1193         BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
1194
1195         MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
1196         (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
1197                             inbuf, sizeof(inbuf), NULL, 0, NULL);
1198 }
1199
1200 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
1201 {
1202         return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
1203                                     (tx_queue->ptr_mask + 1) *
1204                                     sizeof(efx_qword_t),
1205                                     GFP_KERNEL);
1206 }
1207
1208 /* This writes to the TX_DESC_WPTR and also pushes data */
1209 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
1210                                          const efx_qword_t *txd)
1211 {
1212         unsigned int write_ptr;
1213         efx_oword_t reg;
1214
1215         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1216         EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
1217         reg.qword[0] = *txd;
1218         efx_writeo_page(tx_queue->efx, &reg,
1219                         ER_DZ_TX_DESC_UPD, tx_queue->queue);
1220 }
1221
1222 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
1223 {
1224         MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1225                                                        EFX_BUF_SIZE));
1226         MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_TXQ_OUT_LEN);
1227         bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
1228         size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
1229         struct efx_channel *channel = tx_queue->channel;
1230         struct efx_nic *efx = tx_queue->efx;
1231         size_t inlen, outlen;
1232         dma_addr_t dma_addr;
1233         efx_qword_t *txd;
1234         int rc;
1235         int i;
1236
1237         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
1238         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
1239         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
1240         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
1241         MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
1242                               INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
1243                               INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
1244         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
1245         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1246
1247         dma_addr = tx_queue->txd.buf.dma_addr;
1248
1249         netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
1250                   tx_queue->queue, entries, (u64)dma_addr);
1251
1252         for (i = 0; i < entries; ++i) {
1253                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
1254                 dma_addr += EFX_BUF_SIZE;
1255         }
1256
1257         inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
1258
1259         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
1260                           outbuf, sizeof(outbuf), &outlen);
1261         if (rc)
1262                 goto fail;
1263
1264         /* A previous user of this TX queue might have set us up the
1265          * bomb by writing a descriptor to the TX push collector but
1266          * not the doorbell.  (Each collector belongs to a port, not a
1267          * queue or function, so cannot easily be reset.)  We must
1268          * attempt to push a no-op descriptor in its place.
1269          */
1270         tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
1271         tx_queue->insert_count = 1;
1272         txd = efx_tx_desc(tx_queue, 0);
1273         EFX_POPULATE_QWORD_4(*txd,
1274                              ESF_DZ_TX_DESC_IS_OPT, true,
1275                              ESF_DZ_TX_OPTION_TYPE,
1276                              ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
1277                              ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
1278                              ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
1279         tx_queue->write_count = 1;
1280         wmb();
1281         efx_ef10_push_tx_desc(tx_queue, txd);
1282
1283         return;
1284
1285 fail:
1286         netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
1287                     tx_queue->queue);
1288 }
1289
1290 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
1291 {
1292         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
1293         MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_TXQ_OUT_LEN);
1294         struct efx_nic *efx = tx_queue->efx;
1295         size_t outlen;
1296         int rc;
1297
1298         MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
1299                        tx_queue->queue);
1300
1301         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
1302                           outbuf, sizeof(outbuf), &outlen);
1303
1304         if (rc && rc != -EALREADY)
1305                 goto fail;
1306
1307         return;
1308
1309 fail:
1310         efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
1311                                outbuf, outlen, rc);
1312 }
1313
1314 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
1315 {
1316         efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
1317 }
1318
1319 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
1320 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
1321 {
1322         unsigned int write_ptr;
1323         efx_dword_t reg;
1324
1325         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1326         EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
1327         efx_writed_page(tx_queue->efx, &reg,
1328                         ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
1329 }
1330
1331 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
1332 {
1333         unsigned int old_write_count = tx_queue->write_count;
1334         struct efx_tx_buffer *buffer;
1335         unsigned int write_ptr;
1336         efx_qword_t *txd;
1337
1338         BUG_ON(tx_queue->write_count == tx_queue->insert_count);
1339
1340         do {
1341                 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1342                 buffer = &tx_queue->buffer[write_ptr];
1343                 txd = efx_tx_desc(tx_queue, write_ptr);
1344                 ++tx_queue->write_count;
1345
1346                 /* Create TX descriptor ring entry */
1347                 if (buffer->flags & EFX_TX_BUF_OPTION) {
1348                         *txd = buffer->option;
1349                 } else {
1350                         BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
1351                         EFX_POPULATE_QWORD_3(
1352                                 *txd,
1353                                 ESF_DZ_TX_KER_CONT,
1354                                 buffer->flags & EFX_TX_BUF_CONT,
1355                                 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
1356                                 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
1357                 }
1358         } while (tx_queue->write_count != tx_queue->insert_count);
1359
1360         wmb(); /* Ensure descriptors are written before they are fetched */
1361
1362         if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
1363                 txd = efx_tx_desc(tx_queue,
1364                                   old_write_count & tx_queue->ptr_mask);
1365                 efx_ef10_push_tx_desc(tx_queue, txd);
1366                 ++tx_queue->pushes;
1367         } else {
1368                 efx_ef10_notify_tx_desc(tx_queue);
1369         }
1370 }
1371
1372 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context)
1373 {
1374         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
1375         MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
1376         size_t outlen;
1377         int rc;
1378
1379         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
1380                        EVB_PORT_ID_ASSIGNED);
1381         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE,
1382                        MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE);
1383         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES,
1384                        EFX_MAX_CHANNELS);
1385
1386         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
1387                 outbuf, sizeof(outbuf), &outlen);
1388         if (rc != 0)
1389                 return rc;
1390
1391         if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
1392                 return -EIO;
1393
1394         *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
1395
1396         return 0;
1397 }
1398
1399 static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
1400 {
1401         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
1402         int rc;
1403
1404         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
1405                        context);
1406
1407         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
1408                             NULL, 0, NULL);
1409         WARN_ON(rc != 0);
1410 }
1411
1412 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context)
1413 {
1414         MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
1415         MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
1416         int i, rc;
1417
1418         MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
1419                        context);
1420         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1421                      MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
1422
1423         for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
1424                 MCDI_PTR(tablebuf,
1425                          RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
1426                                 (u8) efx->rx_indir_table[i];
1427
1428         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
1429                           sizeof(tablebuf), NULL, 0, NULL);
1430         if (rc != 0)
1431                 return rc;
1432
1433         MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
1434                        context);
1435         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
1436                      MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
1437         for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
1438                 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
1439                         efx->rx_hash_key[i];
1440
1441         return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
1442                             sizeof(keybuf), NULL, 0, NULL);
1443 }
1444
1445 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
1446 {
1447         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1448
1449         if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
1450                 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
1451         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1452 }
1453
1454 static void efx_ef10_rx_push_rss_config(struct efx_nic *efx)
1455 {
1456         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1457         int rc;
1458
1459         netif_dbg(efx, drv, efx->net_dev, "pushing RSS config\n");
1460
1461         if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID) {
1462                 rc = efx_ef10_alloc_rss_context(efx, &nic_data->rx_rss_context);
1463                 if (rc != 0)
1464                         goto fail;
1465         }
1466
1467         rc = efx_ef10_populate_rss_table(efx, nic_data->rx_rss_context);
1468         if (rc != 0)
1469                 goto fail;
1470
1471         return;
1472
1473 fail:
1474         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
1475 }
1476
1477 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
1478 {
1479         return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
1480                                     (rx_queue->ptr_mask + 1) *
1481                                     sizeof(efx_qword_t),
1482                                     GFP_KERNEL);
1483 }
1484
1485 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
1486 {
1487         MCDI_DECLARE_BUF(inbuf,
1488                          MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1489                                                 EFX_BUF_SIZE));
1490         MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_RXQ_OUT_LEN);
1491         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
1492         size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
1493         struct efx_nic *efx = rx_queue->efx;
1494         size_t inlen, outlen;
1495         dma_addr_t dma_addr;
1496         int rc;
1497         int i;
1498
1499         rx_queue->scatter_n = 0;
1500         rx_queue->scatter_len = 0;
1501
1502         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
1503         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
1504         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
1505         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
1506                        efx_rx_queue_index(rx_queue));
1507         MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
1508                               INIT_RXQ_IN_FLAG_PREFIX, 1,
1509                               INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
1510         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
1511         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1512
1513         dma_addr = rx_queue->rxd.buf.dma_addr;
1514
1515         netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
1516                   efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
1517
1518         for (i = 0; i < entries; ++i) {
1519                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
1520                 dma_addr += EFX_BUF_SIZE;
1521         }
1522
1523         inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
1524
1525         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
1526                           outbuf, sizeof(outbuf), &outlen);
1527         if (rc)
1528                 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
1529                             efx_rx_queue_index(rx_queue));
1530 }
1531
1532 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
1533 {
1534         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
1535         MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_RXQ_OUT_LEN);
1536         struct efx_nic *efx = rx_queue->efx;
1537         size_t outlen;
1538         int rc;
1539
1540         MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
1541                        efx_rx_queue_index(rx_queue));
1542
1543         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
1544                           outbuf, sizeof(outbuf), &outlen);
1545
1546         if (rc && rc != -EALREADY)
1547                 goto fail;
1548
1549         return;
1550
1551 fail:
1552         efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
1553                                outbuf, outlen, rc);
1554 }
1555
1556 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
1557 {
1558         efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
1559 }
1560
1561 /* This creates an entry in the RX descriptor queue */
1562 static inline void
1563 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
1564 {
1565         struct efx_rx_buffer *rx_buf;
1566         efx_qword_t *rxd;
1567
1568         rxd = efx_rx_desc(rx_queue, index);
1569         rx_buf = efx_rx_buffer(rx_queue, index);
1570         EFX_POPULATE_QWORD_2(*rxd,
1571                              ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
1572                              ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
1573 }
1574
1575 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
1576 {
1577         struct efx_nic *efx = rx_queue->efx;
1578         unsigned int write_count;
1579         efx_dword_t reg;
1580
1581         /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
1582         write_count = rx_queue->added_count & ~7;
1583         if (rx_queue->notified_count == write_count)
1584                 return;
1585
1586         do
1587                 efx_ef10_build_rx_desc(
1588                         rx_queue,
1589                         rx_queue->notified_count & rx_queue->ptr_mask);
1590         while (++rx_queue->notified_count != write_count);
1591
1592         wmb();
1593         EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
1594                              write_count & rx_queue->ptr_mask);
1595         efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
1596                         efx_rx_queue_index(rx_queue));
1597 }
1598
1599 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
1600
1601 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
1602 {
1603         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
1604         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
1605         efx_qword_t event;
1606
1607         EFX_POPULATE_QWORD_2(event,
1608                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
1609                              ESF_DZ_EV_DATA, EFX_EF10_REFILL);
1610
1611         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
1612
1613         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
1614          * already swapped the data to little-endian order.
1615          */
1616         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
1617                sizeof(efx_qword_t));
1618
1619         efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
1620                            inbuf, sizeof(inbuf), 0,
1621                            efx_ef10_rx_defer_refill_complete, 0);
1622 }
1623
1624 static void
1625 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
1626                                   int rc, efx_dword_t *outbuf,
1627                                   size_t outlen_actual)
1628 {
1629         /* nothing to do */
1630 }
1631
1632 static int efx_ef10_ev_probe(struct efx_channel *channel)
1633 {
1634         return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
1635                                     (channel->eventq_mask + 1) *
1636                                     sizeof(efx_qword_t),
1637                                     GFP_KERNEL);
1638 }
1639
1640 static int efx_ef10_ev_init(struct efx_channel *channel)
1641 {
1642         MCDI_DECLARE_BUF(inbuf,
1643                          MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
1644                                                 EFX_BUF_SIZE));
1645         MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN);
1646         size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
1647         struct efx_nic *efx = channel->efx;
1648         struct efx_ef10_nic_data *nic_data;
1649         bool supports_rx_merge;
1650         size_t inlen, outlen;
1651         dma_addr_t dma_addr;
1652         int rc;
1653         int i;
1654
1655         nic_data = efx->nic_data;
1656         supports_rx_merge =
1657                 !!(nic_data->datapath_caps &
1658                    1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
1659
1660         /* Fill event queue with all ones (i.e. empty events) */
1661         memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
1662
1663         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
1664         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
1665         /* INIT_EVQ expects index in vector table, not absolute */
1666         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
1667         MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
1668                               INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
1669                               INIT_EVQ_IN_FLAG_RX_MERGE, 1,
1670                               INIT_EVQ_IN_FLAG_TX_MERGE, 1,
1671                               INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge);
1672         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
1673                        MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
1674         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
1675         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
1676         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
1677                        MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
1678         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
1679
1680         dma_addr = channel->eventq.buf.dma_addr;
1681         for (i = 0; i < entries; ++i) {
1682                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
1683                 dma_addr += EFX_BUF_SIZE;
1684         }
1685
1686         inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
1687
1688         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
1689                           outbuf, sizeof(outbuf), &outlen);
1690         /* IRQ return is ignored */
1691         return rc;
1692 }
1693
1694 static void efx_ef10_ev_fini(struct efx_channel *channel)
1695 {
1696         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
1697         MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_EVQ_OUT_LEN);
1698         struct efx_nic *efx = channel->efx;
1699         size_t outlen;
1700         int rc;
1701
1702         MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
1703
1704         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
1705                           outbuf, sizeof(outbuf), &outlen);
1706
1707         if (rc && rc != -EALREADY)
1708                 goto fail;
1709
1710         return;
1711
1712 fail:
1713         efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
1714                                outbuf, outlen, rc);
1715 }
1716
1717 static void efx_ef10_ev_remove(struct efx_channel *channel)
1718 {
1719         efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
1720 }
1721
1722 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
1723                                            unsigned int rx_queue_label)
1724 {
1725         struct efx_nic *efx = rx_queue->efx;
1726
1727         netif_info(efx, hw, efx->net_dev,
1728                    "rx event arrived on queue %d labeled as queue %u\n",
1729                    efx_rx_queue_index(rx_queue), rx_queue_label);
1730
1731         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1732 }
1733
1734 static void
1735 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
1736                              unsigned int actual, unsigned int expected)
1737 {
1738         unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
1739         struct efx_nic *efx = rx_queue->efx;
1740
1741         netif_info(efx, hw, efx->net_dev,
1742                    "dropped %d events (index=%d expected=%d)\n",
1743                    dropped, actual, expected);
1744
1745         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1746 }
1747
1748 /* partially received RX was aborted. clean up. */
1749 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
1750 {
1751         unsigned int rx_desc_ptr;
1752
1753         netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
1754                   "scattered RX aborted (dropping %u buffers)\n",
1755                   rx_queue->scatter_n);
1756
1757         rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
1758
1759         efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
1760                       0, EFX_RX_PKT_DISCARD);
1761
1762         rx_queue->removed_count += rx_queue->scatter_n;
1763         rx_queue->scatter_n = 0;
1764         rx_queue->scatter_len = 0;
1765         ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
1766 }
1767
1768 static int efx_ef10_handle_rx_event(struct efx_channel *channel,
1769                                     const efx_qword_t *event)
1770 {
1771         unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
1772         unsigned int n_descs, n_packets, i;
1773         struct efx_nic *efx = channel->efx;
1774         struct efx_rx_queue *rx_queue;
1775         bool rx_cont;
1776         u16 flags = 0;
1777
1778         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
1779                 return 0;
1780
1781         /* Basic packet information */
1782         rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
1783         next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
1784         rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
1785         rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
1786         rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
1787
1788         if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
1789                 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
1790                             EFX_QWORD_FMT "\n",
1791                             EFX_QWORD_VAL(*event));
1792
1793         rx_queue = efx_channel_get_rx_queue(channel);
1794
1795         if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
1796                 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
1797
1798         n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
1799                    ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
1800
1801         if (n_descs != rx_queue->scatter_n + 1) {
1802                 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1803
1804                 /* detect rx abort */
1805                 if (unlikely(n_descs == rx_queue->scatter_n)) {
1806                         if (rx_queue->scatter_n == 0 || rx_bytes != 0)
1807                                 netdev_WARN(efx->net_dev,
1808                                             "invalid RX abort: scatter_n=%u event="
1809                                             EFX_QWORD_FMT "\n",
1810                                             rx_queue->scatter_n,
1811                                             EFX_QWORD_VAL(*event));
1812                         efx_ef10_handle_rx_abort(rx_queue);
1813                         return 0;
1814                 }
1815
1816                 /* Check that RX completion merging is valid, i.e.
1817                  * the current firmware supports it and this is a
1818                  * non-scattered packet.
1819                  */
1820                 if (!(nic_data->datapath_caps &
1821                       (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
1822                     rx_queue->scatter_n != 0 || rx_cont) {
1823                         efx_ef10_handle_rx_bad_lbits(
1824                                 rx_queue, next_ptr_lbits,
1825                                 (rx_queue->removed_count +
1826                                  rx_queue->scatter_n + 1) &
1827                                 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
1828                         return 0;
1829                 }
1830
1831                 /* Merged completion for multiple non-scattered packets */
1832                 rx_queue->scatter_n = 1;
1833                 rx_queue->scatter_len = 0;
1834                 n_packets = n_descs;
1835                 ++channel->n_rx_merge_events;
1836                 channel->n_rx_merge_packets += n_packets;
1837                 flags |= EFX_RX_PKT_PREFIX_LEN;
1838         } else {
1839                 ++rx_queue->scatter_n;
1840                 rx_queue->scatter_len += rx_bytes;
1841                 if (rx_cont)
1842                         return 0;
1843                 n_packets = 1;
1844         }
1845
1846         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
1847                 flags |= EFX_RX_PKT_DISCARD;
1848
1849         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
1850                 channel->n_rx_ip_hdr_chksum_err += n_packets;
1851         } else if (unlikely(EFX_QWORD_FIELD(*event,
1852                                             ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
1853                 channel->n_rx_tcp_udp_chksum_err += n_packets;
1854         } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
1855                    rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
1856                 flags |= EFX_RX_PKT_CSUMMED;
1857         }
1858
1859         if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
1860                 flags |= EFX_RX_PKT_TCP;
1861
1862         channel->irq_mod_score += 2 * n_packets;
1863
1864         /* Handle received packet(s) */
1865         for (i = 0; i < n_packets; i++) {
1866                 efx_rx_packet(rx_queue,
1867                               rx_queue->removed_count & rx_queue->ptr_mask,
1868                               rx_queue->scatter_n, rx_queue->scatter_len,
1869                               flags);
1870                 rx_queue->removed_count += rx_queue->scatter_n;
1871         }
1872
1873         rx_queue->scatter_n = 0;
1874         rx_queue->scatter_len = 0;
1875
1876         return n_packets;
1877 }
1878
1879 static int
1880 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
1881 {
1882         struct efx_nic *efx = channel->efx;
1883         struct efx_tx_queue *tx_queue;
1884         unsigned int tx_ev_desc_ptr;
1885         unsigned int tx_ev_q_label;
1886         int tx_descs = 0;
1887
1888         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
1889                 return 0;
1890
1891         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
1892                 return 0;
1893
1894         /* Transmit completion */
1895         tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
1896         tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
1897         tx_queue = efx_channel_get_tx_queue(channel,
1898                                             tx_ev_q_label % EFX_TXQ_TYPES);
1899         tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
1900                     tx_queue->ptr_mask);
1901         efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
1902
1903         return tx_descs;
1904 }
1905
1906 static void
1907 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
1908 {
1909         struct efx_nic *efx = channel->efx;
1910         int subcode;
1911
1912         subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
1913
1914         switch (subcode) {
1915         case ESE_DZ_DRV_TIMER_EV:
1916         case ESE_DZ_DRV_WAKE_UP_EV:
1917                 break;
1918         case ESE_DZ_DRV_START_UP_EV:
1919                 /* event queue init complete. ok. */
1920                 break;
1921         default:
1922                 netif_err(efx, hw, efx->net_dev,
1923                           "channel %d unknown driver event type %d"
1924                           " (data " EFX_QWORD_FMT ")\n",
1925                           channel->channel, subcode,
1926                           EFX_QWORD_VAL(*event));
1927
1928         }
1929 }
1930
1931 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
1932                                                    efx_qword_t *event)
1933 {
1934         struct efx_nic *efx = channel->efx;
1935         u32 subcode;
1936
1937         subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
1938
1939         switch (subcode) {
1940         case EFX_EF10_TEST:
1941                 channel->event_test_cpu = raw_smp_processor_id();
1942                 break;
1943         case EFX_EF10_REFILL:
1944                 /* The queue must be empty, so we won't receive any rx
1945                  * events, so efx_process_channel() won't refill the
1946                  * queue. Refill it here
1947                  */
1948                 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
1949                 break;
1950         default:
1951                 netif_err(efx, hw, efx->net_dev,
1952                           "channel %d unknown driver event type %u"
1953                           " (data " EFX_QWORD_FMT ")\n",
1954                           channel->channel, (unsigned) subcode,
1955                           EFX_QWORD_VAL(*event));
1956         }
1957 }
1958
1959 static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
1960 {
1961         struct efx_nic *efx = channel->efx;
1962         efx_qword_t event, *p_event;
1963         unsigned int read_ptr;
1964         int ev_code;
1965         int tx_descs = 0;
1966         int spent = 0;
1967
1968         if (quota <= 0)
1969                 return spent;
1970
1971         read_ptr = channel->eventq_read_ptr;
1972
1973         for (;;) {
1974                 p_event = efx_event(channel, read_ptr);
1975                 event = *p_event;
1976
1977                 if (!efx_event_present(&event))
1978                         break;
1979
1980                 EFX_SET_QWORD(*p_event);
1981
1982                 ++read_ptr;
1983
1984                 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
1985
1986                 netif_vdbg(efx, drv, efx->net_dev,
1987                            "processing event on %d " EFX_QWORD_FMT "\n",
1988                            channel->channel, EFX_QWORD_VAL(event));
1989
1990                 switch (ev_code) {
1991                 case ESE_DZ_EV_CODE_MCDI_EV:
1992                         efx_mcdi_process_event(channel, &event);
1993                         break;
1994                 case ESE_DZ_EV_CODE_RX_EV:
1995                         spent += efx_ef10_handle_rx_event(channel, &event);
1996                         if (spent >= quota) {
1997                                 /* XXX can we split a merged event to
1998                                  * avoid going over-quota?
1999                                  */
2000                                 spent = quota;
2001                                 goto out;
2002                         }
2003                         break;
2004                 case ESE_DZ_EV_CODE_TX_EV:
2005                         tx_descs += efx_ef10_handle_tx_event(channel, &event);
2006                         if (tx_descs > efx->txq_entries) {
2007                                 spent = quota;
2008                                 goto out;
2009                         } else if (++spent == quota) {
2010                                 goto out;
2011                         }
2012                         break;
2013                 case ESE_DZ_EV_CODE_DRIVER_EV:
2014                         efx_ef10_handle_driver_event(channel, &event);
2015                         if (++spent == quota)
2016                                 goto out;
2017                         break;
2018                 case EFX_EF10_DRVGEN_EV:
2019                         efx_ef10_handle_driver_generated_event(channel, &event);
2020                         break;
2021                 default:
2022                         netif_err(efx, hw, efx->net_dev,
2023                                   "channel %d unknown event type %d"
2024                                   " (data " EFX_QWORD_FMT ")\n",
2025                                   channel->channel, ev_code,
2026                                   EFX_QWORD_VAL(event));
2027                 }
2028         }
2029
2030 out:
2031         channel->eventq_read_ptr = read_ptr;
2032         return spent;
2033 }
2034
2035 static void efx_ef10_ev_read_ack(struct efx_channel *channel)
2036 {
2037         struct efx_nic *efx = channel->efx;
2038         efx_dword_t rptr;
2039
2040         if (EFX_EF10_WORKAROUND_35388(efx)) {
2041                 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
2042                              (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
2043                 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
2044                              (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
2045
2046                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2047                                      EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
2048                                      ERF_DD_EVQ_IND_RPTR,
2049                                      (channel->eventq_read_ptr &
2050                                       channel->eventq_mask) >>
2051                                      ERF_DD_EVQ_IND_RPTR_WIDTH);
2052                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2053                                 channel->channel);
2054                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2055                                      EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
2056                                      ERF_DD_EVQ_IND_RPTR,
2057                                      channel->eventq_read_ptr &
2058                                      ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
2059                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2060                                 channel->channel);
2061         } else {
2062                 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
2063                                      channel->eventq_read_ptr &
2064                                      channel->eventq_mask);
2065                 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
2066         }
2067 }
2068
2069 static void efx_ef10_ev_test_generate(struct efx_channel *channel)
2070 {
2071         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2072         struct efx_nic *efx = channel->efx;
2073         efx_qword_t event;
2074         int rc;
2075
2076         EFX_POPULATE_QWORD_2(event,
2077                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2078                              ESF_DZ_EV_DATA, EFX_EF10_TEST);
2079
2080         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2081
2082         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2083          * already swapped the data to little-endian order.
2084          */
2085         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2086                sizeof(efx_qword_t));
2087
2088         rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
2089                           NULL, 0, NULL);
2090         if (rc != 0)
2091                 goto fail;
2092
2093         return;
2094
2095 fail:
2096         WARN_ON(true);
2097         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2098 }
2099
2100 void efx_ef10_handle_drain_event(struct efx_nic *efx)
2101 {
2102         if (atomic_dec_and_test(&efx->active_queues))
2103                 wake_up(&efx->flush_wq);
2104
2105         WARN_ON(atomic_read(&efx->active_queues) < 0);
2106 }
2107
2108 static int efx_ef10_fini_dmaq(struct efx_nic *efx)
2109 {
2110         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2111         struct efx_channel *channel;
2112         struct efx_tx_queue *tx_queue;
2113         struct efx_rx_queue *rx_queue;
2114         int pending;
2115
2116         /* If the MC has just rebooted, the TX/RX queues will have already been
2117          * torn down, but efx->active_queues needs to be set to zero.
2118          */
2119         if (nic_data->must_realloc_vis) {
2120                 atomic_set(&efx->active_queues, 0);
2121                 return 0;
2122         }
2123
2124         /* Do not attempt to write to the NIC during EEH recovery */
2125         if (efx->state != STATE_RECOVERY) {
2126                 efx_for_each_channel(channel, efx) {
2127                         efx_for_each_channel_rx_queue(rx_queue, channel)
2128                                 efx_ef10_rx_fini(rx_queue);
2129                         efx_for_each_channel_tx_queue(tx_queue, channel)
2130                                 efx_ef10_tx_fini(tx_queue);
2131                 }
2132
2133                 wait_event_timeout(efx->flush_wq,
2134                                    atomic_read(&efx->active_queues) == 0,
2135                                    msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
2136                 pending = atomic_read(&efx->active_queues);
2137                 if (pending) {
2138                         netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
2139                                   pending);
2140                         return -ETIMEDOUT;
2141                 }
2142         }
2143
2144         return 0;
2145 }
2146
2147 static void efx_ef10_prepare_flr(struct efx_nic *efx)
2148 {
2149         atomic_set(&efx->active_queues, 0);
2150 }
2151
2152 static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
2153                                   const struct efx_filter_spec *right)
2154 {
2155         if ((left->match_flags ^ right->match_flags) |
2156             ((left->flags ^ right->flags) &
2157              (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
2158                 return false;
2159
2160         return memcmp(&left->outer_vid, &right->outer_vid,
2161                       sizeof(struct efx_filter_spec) -
2162                       offsetof(struct efx_filter_spec, outer_vid)) == 0;
2163 }
2164
2165 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
2166 {
2167         BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
2168         return jhash2((const u32 *)&spec->outer_vid,
2169                       (sizeof(struct efx_filter_spec) -
2170                        offsetof(struct efx_filter_spec, outer_vid)) / 4,
2171                       0);
2172         /* XXX should we randomise the initval? */
2173 }
2174
2175 /* Decide whether a filter should be exclusive or else should allow
2176  * delivery to additional recipients.  Currently we decide that
2177  * filters for specific local unicast MAC and IP addresses are
2178  * exclusive.
2179  */
2180 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
2181 {
2182         if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
2183             !is_multicast_ether_addr(spec->loc_mac))
2184                 return true;
2185
2186         if ((spec->match_flags &
2187              (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
2188             (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
2189                 if (spec->ether_type == htons(ETH_P_IP) &&
2190                     !ipv4_is_multicast(spec->loc_host[0]))
2191                         return true;
2192                 if (spec->ether_type == htons(ETH_P_IPV6) &&
2193                     ((const u8 *)spec->loc_host)[0] != 0xff)
2194                         return true;
2195         }
2196
2197         return false;
2198 }
2199
2200 static struct efx_filter_spec *
2201 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
2202                            unsigned int filter_idx)
2203 {
2204         return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
2205                                           ~EFX_EF10_FILTER_FLAGS);
2206 }
2207
2208 static unsigned int
2209 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
2210                            unsigned int filter_idx)
2211 {
2212         return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
2213 }
2214
2215 static void
2216 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
2217                           unsigned int filter_idx,
2218                           const struct efx_filter_spec *spec,
2219                           unsigned int flags)
2220 {
2221         table->entry[filter_idx].spec = (unsigned long)spec | flags;
2222 }
2223
2224 static void efx_ef10_filter_push_prep(struct efx_nic *efx,
2225                                       const struct efx_filter_spec *spec,
2226                                       efx_dword_t *inbuf, u64 handle,
2227                                       bool replacing)
2228 {
2229         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2230
2231         memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
2232
2233         if (replacing) {
2234                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2235                                MC_CMD_FILTER_OP_IN_OP_REPLACE);
2236                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
2237         } else {
2238                 u32 match_fields = 0;
2239
2240                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2241                                efx_ef10_filter_is_exclusive(spec) ?
2242                                MC_CMD_FILTER_OP_IN_OP_INSERT :
2243                                MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
2244
2245                 /* Convert match flags and values.  Unlike almost
2246                  * everything else in MCDI, these fields are in
2247                  * network byte order.
2248                  */
2249                 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
2250                         match_fields |=
2251                                 is_multicast_ether_addr(spec->loc_mac) ?
2252                                 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
2253                                 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
2254 #define COPY_FIELD(gen_flag, gen_field, mcdi_field)                          \
2255                 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) {     \
2256                         match_fields |=                                      \
2257                                 1 << MC_CMD_FILTER_OP_IN_MATCH_ ##           \
2258                                 mcdi_field ## _LBN;                          \
2259                         BUILD_BUG_ON(                                        \
2260                                 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
2261                                 sizeof(spec->gen_field));                    \
2262                         memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
2263                                &spec->gen_field, sizeof(spec->gen_field));   \
2264                 }
2265                 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
2266                 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
2267                 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
2268                 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
2269                 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
2270                 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
2271                 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
2272                 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
2273                 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
2274                 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
2275 #undef COPY_FIELD
2276                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
2277                                match_fields);
2278         }
2279
2280         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
2281         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
2282                        spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2283                        MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
2284                        MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
2285         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
2286                        MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
2287         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
2288                        spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2289                        0 : spec->dmaq_id);
2290         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
2291                        (spec->flags & EFX_FILTER_FLAG_RX_RSS) ?
2292                        MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
2293                        MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
2294         if (spec->flags & EFX_FILTER_FLAG_RX_RSS)
2295                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
2296                                spec->rss_context !=
2297                                EFX_FILTER_RSS_CONTEXT_DEFAULT ?
2298                                spec->rss_context : nic_data->rx_rss_context);
2299 }
2300
2301 static int efx_ef10_filter_push(struct efx_nic *efx,
2302                                 const struct efx_filter_spec *spec,
2303                                 u64 *handle, bool replacing)
2304 {
2305         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2306         MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
2307         int rc;
2308
2309         efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
2310         rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2311                           outbuf, sizeof(outbuf), NULL);
2312         if (rc == 0)
2313                 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
2314         if (rc == -ENOSPC)
2315                 rc = -EBUSY; /* to match efx_farch_filter_insert() */
2316         return rc;
2317 }
2318
2319 static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table,
2320                                         enum efx_filter_match_flags match_flags)
2321 {
2322         unsigned int match_pri;
2323
2324         for (match_pri = 0;
2325              match_pri < table->rx_match_count;
2326              match_pri++)
2327                 if (table->rx_match_flags[match_pri] == match_flags)
2328                         return match_pri;
2329
2330         return -EPROTONOSUPPORT;
2331 }
2332
2333 static s32 efx_ef10_filter_insert(struct efx_nic *efx,
2334                                   struct efx_filter_spec *spec,
2335                                   bool replace_equal)
2336 {
2337         struct efx_ef10_filter_table *table = efx->filter_state;
2338         DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
2339         struct efx_filter_spec *saved_spec;
2340         unsigned int match_pri, hash;
2341         unsigned int priv_flags;
2342         bool replacing = false;
2343         int ins_index = -1;
2344         DEFINE_WAIT(wait);
2345         bool is_mc_recip;
2346         s32 rc;
2347
2348         /* For now, only support RX filters */
2349         if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
2350             EFX_FILTER_FLAG_RX)
2351                 return -EINVAL;
2352
2353         rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags);
2354         if (rc < 0)
2355                 return rc;
2356         match_pri = rc;
2357
2358         hash = efx_ef10_filter_hash(spec);
2359         is_mc_recip = efx_filter_is_mc_recipient(spec);
2360         if (is_mc_recip)
2361                 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
2362
2363         /* Find any existing filters with the same match tuple or
2364          * else a free slot to insert at.  If any of them are busy,
2365          * we have to wait and retry.
2366          */
2367         for (;;) {
2368                 unsigned int depth = 1;
2369                 unsigned int i;
2370
2371                 spin_lock_bh(&efx->filter_lock);
2372
2373                 for (;;) {
2374                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2375                         saved_spec = efx_ef10_filter_entry_spec(table, i);
2376
2377                         if (!saved_spec) {
2378                                 if (ins_index < 0)
2379                                         ins_index = i;
2380                         } else if (efx_ef10_filter_equal(spec, saved_spec)) {
2381                                 if (table->entry[i].spec &
2382                                     EFX_EF10_FILTER_FLAG_BUSY)
2383                                         break;
2384                                 if (spec->priority < saved_spec->priority &&
2385                                     spec->priority != EFX_FILTER_PRI_AUTO) {
2386                                         rc = -EPERM;
2387                                         goto out_unlock;
2388                                 }
2389                                 if (!is_mc_recip) {
2390                                         /* This is the only one */
2391                                         if (spec->priority ==
2392                                             saved_spec->priority &&
2393                                             !replace_equal) {
2394                                                 rc = -EEXIST;
2395                                                 goto out_unlock;
2396                                         }
2397                                         ins_index = i;
2398                                         goto found;
2399                                 } else if (spec->priority >
2400                                            saved_spec->priority ||
2401                                            (spec->priority ==
2402                                             saved_spec->priority &&
2403                                             replace_equal)) {
2404                                         if (ins_index < 0)
2405                                                 ins_index = i;
2406                                         else
2407                                                 __set_bit(depth, mc_rem_map);
2408                                 }
2409                         }
2410
2411                         /* Once we reach the maximum search depth, use
2412                          * the first suitable slot or return -EBUSY if
2413                          * there was none
2414                          */
2415                         if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
2416                                 if (ins_index < 0) {
2417                                         rc = -EBUSY;
2418                                         goto out_unlock;
2419                                 }
2420                                 goto found;
2421                         }
2422
2423                         ++depth;
2424                 }
2425
2426                 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
2427                 spin_unlock_bh(&efx->filter_lock);
2428                 schedule();
2429         }
2430
2431 found:
2432         /* Create a software table entry if necessary, and mark it
2433          * busy.  We might yet fail to insert, but any attempt to
2434          * insert a conflicting filter while we're waiting for the
2435          * firmware must find the busy entry.
2436          */
2437         saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
2438         if (saved_spec) {
2439                 if (spec->priority == EFX_FILTER_PRI_AUTO &&
2440                     saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
2441                         /* Just make sure it won't be removed */
2442                         if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
2443                                 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
2444                         table->entry[ins_index].spec &=
2445                                 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
2446                         rc = ins_index;
2447                         goto out_unlock;
2448                 }
2449                 replacing = true;
2450                 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
2451         } else {
2452                 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
2453                 if (!saved_spec) {
2454                         rc = -ENOMEM;
2455                         goto out_unlock;
2456                 }
2457                 *saved_spec = *spec;
2458                 priv_flags = 0;
2459         }
2460         efx_ef10_filter_set_entry(table, ins_index, saved_spec,
2461                                   priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
2462
2463         /* Mark lower-priority multicast recipients busy prior to removal */
2464         if (is_mc_recip) {
2465                 unsigned int depth, i;
2466
2467                 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
2468                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2469                         if (test_bit(depth, mc_rem_map))
2470                                 table->entry[i].spec |=
2471                                         EFX_EF10_FILTER_FLAG_BUSY;
2472                 }
2473         }
2474
2475         spin_unlock_bh(&efx->filter_lock);
2476
2477         rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
2478                                   replacing);
2479
2480         /* Finalise the software table entry */
2481         spin_lock_bh(&efx->filter_lock);
2482         if (rc == 0) {
2483                 if (replacing) {
2484                         /* Update the fields that may differ */
2485                         if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
2486                                 saved_spec->flags |=
2487                                         EFX_FILTER_FLAG_RX_OVER_AUTO;
2488                         saved_spec->priority = spec->priority;
2489                         saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
2490                         saved_spec->flags |= spec->flags;
2491                         saved_spec->rss_context = spec->rss_context;
2492                         saved_spec->dmaq_id = spec->dmaq_id;
2493                 }
2494         } else if (!replacing) {
2495                 kfree(saved_spec);
2496                 saved_spec = NULL;
2497         }
2498         efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
2499
2500         /* Remove and finalise entries for lower-priority multicast
2501          * recipients
2502          */
2503         if (is_mc_recip) {
2504                 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2505                 unsigned int depth, i;
2506
2507                 memset(inbuf, 0, sizeof(inbuf));
2508
2509                 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
2510                         if (!test_bit(depth, mc_rem_map))
2511                                 continue;
2512
2513                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2514                         saved_spec = efx_ef10_filter_entry_spec(table, i);
2515                         priv_flags = efx_ef10_filter_entry_flags(table, i);
2516
2517                         if (rc == 0) {
2518                                 spin_unlock_bh(&efx->filter_lock);
2519                                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2520                                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2521                                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2522                                                table->entry[i].handle);
2523                                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
2524                                                   inbuf, sizeof(inbuf),
2525                                                   NULL, 0, NULL);
2526                                 spin_lock_bh(&efx->filter_lock);
2527                         }
2528
2529                         if (rc == 0) {
2530                                 kfree(saved_spec);
2531                                 saved_spec = NULL;
2532                                 priv_flags = 0;
2533                         } else {
2534                                 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
2535                         }
2536                         efx_ef10_filter_set_entry(table, i, saved_spec,
2537                                                   priv_flags);
2538                 }
2539         }
2540
2541         /* If successful, return the inserted filter ID */
2542         if (rc == 0)
2543                 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
2544
2545         wake_up_all(&table->waitq);
2546 out_unlock:
2547         spin_unlock_bh(&efx->filter_lock);
2548         finish_wait(&table->waitq, &wait);
2549         return rc;
2550 }
2551
2552 static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
2553 {
2554         /* no need to do anything here on EF10 */
2555 }
2556
2557 /* Remove a filter.
2558  * If !by_index, remove by ID
2559  * If by_index, remove by index
2560  * Filter ID may come from userland and must be range-checked.
2561  */
2562 static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
2563                                            unsigned int priority_mask,
2564                                            u32 filter_id, bool by_index)
2565 {
2566         unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
2567         struct efx_ef10_filter_table *table = efx->filter_state;
2568         MCDI_DECLARE_BUF(inbuf,
2569                          MC_CMD_FILTER_OP_IN_HANDLE_OFST +
2570                          MC_CMD_FILTER_OP_IN_HANDLE_LEN);
2571         struct efx_filter_spec *spec;
2572         DEFINE_WAIT(wait);
2573         int rc;
2574
2575         /* Find the software table entry and mark it busy.  Don't
2576          * remove it yet; any attempt to update while we're waiting
2577          * for the firmware must find the busy entry.
2578          */
2579         for (;;) {
2580                 spin_lock_bh(&efx->filter_lock);
2581                 if (!(table->entry[filter_idx].spec &
2582                       EFX_EF10_FILTER_FLAG_BUSY))
2583                         break;
2584                 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
2585                 spin_unlock_bh(&efx->filter_lock);
2586                 schedule();
2587         }
2588
2589         spec = efx_ef10_filter_entry_spec(table, filter_idx);
2590         if (!spec ||
2591             (!by_index &&
2592              efx_ef10_filter_rx_match_pri(table, spec->match_flags) !=
2593              filter_id / HUNT_FILTER_TBL_ROWS)) {
2594                 rc = -ENOENT;
2595                 goto out_unlock;
2596         }
2597
2598         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
2599             priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
2600                 /* Just remove flags */
2601                 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
2602                 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
2603                 rc = 0;
2604                 goto out_unlock;
2605         }
2606
2607         if (!(priority_mask & (1U << spec->priority))) {
2608                 rc = -ENOENT;
2609                 goto out_unlock;
2610         }
2611
2612         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
2613         spin_unlock_bh(&efx->filter_lock);
2614
2615         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
2616                 /* Reset to an automatic filter */
2617
2618                 struct efx_filter_spec new_spec = *spec;
2619
2620                 new_spec.priority = EFX_FILTER_PRI_AUTO;
2621                 new_spec.flags = (EFX_FILTER_FLAG_RX |
2622                                   EFX_FILTER_FLAG_RX_RSS);
2623                 new_spec.dmaq_id = 0;
2624                 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
2625                 rc = efx_ef10_filter_push(efx, &new_spec,
2626                                           &table->entry[filter_idx].handle,
2627                                           true);
2628
2629                 spin_lock_bh(&efx->filter_lock);
2630                 if (rc == 0)
2631                         *spec = new_spec;
2632         } else {
2633                 /* Really remove the filter */
2634
2635                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2636                                efx_ef10_filter_is_exclusive(spec) ?
2637                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
2638                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2639                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2640                                table->entry[filter_idx].handle);
2641                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
2642                                   inbuf, sizeof(inbuf), NULL, 0, NULL);
2643
2644                 spin_lock_bh(&efx->filter_lock);
2645                 if (rc == 0) {
2646                         kfree(spec);
2647                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
2648                 }
2649         }
2650
2651         table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
2652         wake_up_all(&table->waitq);
2653 out_unlock:
2654         spin_unlock_bh(&efx->filter_lock);
2655         finish_wait(&table->waitq, &wait);
2656         return rc;
2657 }
2658
2659 static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
2660                                        enum efx_filter_priority priority,
2661                                        u32 filter_id)
2662 {
2663         return efx_ef10_filter_remove_internal(efx, 1U << priority,
2664                                                filter_id, false);
2665 }
2666
2667 static int efx_ef10_filter_get_safe(struct efx_nic *efx,
2668                                     enum efx_filter_priority priority,
2669                                     u32 filter_id, struct efx_filter_spec *spec)
2670 {
2671         unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
2672         struct efx_ef10_filter_table *table = efx->filter_state;
2673         const struct efx_filter_spec *saved_spec;
2674         int rc;
2675
2676         spin_lock_bh(&efx->filter_lock);
2677         saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
2678         if (saved_spec && saved_spec->priority == priority &&
2679             efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) ==
2680             filter_id / HUNT_FILTER_TBL_ROWS) {
2681                 *spec = *saved_spec;
2682                 rc = 0;
2683         } else {
2684                 rc = -ENOENT;
2685         }
2686         spin_unlock_bh(&efx->filter_lock);
2687         return rc;
2688 }
2689
2690 static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
2691                                      enum efx_filter_priority priority)
2692 {
2693         unsigned int priority_mask;
2694         unsigned int i;
2695         int rc;
2696
2697         priority_mask = (((1U << (priority + 1)) - 1) &
2698                          ~(1U << EFX_FILTER_PRI_AUTO));
2699
2700         for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
2701                 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
2702                                                      i, true);
2703                 if (rc && rc != -ENOENT)
2704                         return rc;
2705         }
2706
2707         return 0;
2708 }
2709
2710 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
2711                                          enum efx_filter_priority priority)
2712 {
2713         struct efx_ef10_filter_table *table = efx->filter_state;
2714         unsigned int filter_idx;
2715         s32 count = 0;
2716
2717         spin_lock_bh(&efx->filter_lock);
2718         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
2719                 if (table->entry[filter_idx].spec &&
2720                     efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
2721                     priority)
2722                         ++count;
2723         }
2724         spin_unlock_bh(&efx->filter_lock);
2725         return count;
2726 }
2727
2728 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
2729 {
2730         struct efx_ef10_filter_table *table = efx->filter_state;
2731
2732         return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
2733 }
2734
2735 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
2736                                       enum efx_filter_priority priority,
2737                                       u32 *buf, u32 size)
2738 {
2739         struct efx_ef10_filter_table *table = efx->filter_state;
2740         struct efx_filter_spec *spec;
2741         unsigned int filter_idx;
2742         s32 count = 0;
2743
2744         spin_lock_bh(&efx->filter_lock);
2745         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
2746                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
2747                 if (spec && spec->priority == priority) {
2748                         if (count == size) {
2749                                 count = -EMSGSIZE;
2750                                 break;
2751                         }
2752                         buf[count++] = (efx_ef10_filter_rx_match_pri(
2753                                                 table, spec->match_flags) *
2754                                         HUNT_FILTER_TBL_ROWS +
2755                                         filter_idx);
2756                 }
2757         }
2758         spin_unlock_bh(&efx->filter_lock);
2759         return count;
2760 }
2761
2762 #ifdef CONFIG_RFS_ACCEL
2763
2764 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
2765
2766 static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
2767                                       struct efx_filter_spec *spec)
2768 {
2769         struct efx_ef10_filter_table *table = efx->filter_state;
2770         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2771         struct efx_filter_spec *saved_spec;
2772         unsigned int hash, i, depth = 1;
2773         bool replacing = false;
2774         int ins_index = -1;
2775         u64 cookie;
2776         s32 rc;
2777
2778         /* Must be an RX filter without RSS and not for a multicast
2779          * destination address (RFS only works for connected sockets).
2780          * These restrictions allow us to pass only a tiny amount of
2781          * data through to the completion function.
2782          */
2783         EFX_WARN_ON_PARANOID(spec->flags !=
2784                              (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
2785         EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
2786         EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
2787
2788         hash = efx_ef10_filter_hash(spec);
2789
2790         spin_lock_bh(&efx->filter_lock);
2791
2792         /* Find any existing filter with the same match tuple or else
2793          * a free slot to insert at.  If an existing filter is busy,
2794          * we have to give up.
2795          */
2796         for (;;) {
2797                 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2798                 saved_spec = efx_ef10_filter_entry_spec(table, i);
2799
2800                 if (!saved_spec) {
2801                         if (ins_index < 0)
2802                                 ins_index = i;
2803                 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
2804                         if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
2805                                 rc = -EBUSY;
2806                                 goto fail_unlock;
2807                         }
2808                         if (spec->priority < saved_spec->priority) {
2809                                 rc = -EPERM;
2810                                 goto fail_unlock;
2811                         }
2812                         ins_index = i;
2813                         break;
2814                 }
2815
2816                 /* Once we reach the maximum search depth, use the
2817                  * first suitable slot or return -EBUSY if there was
2818                  * none
2819                  */
2820                 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
2821                         if (ins_index < 0) {
2822                                 rc = -EBUSY;
2823                                 goto fail_unlock;
2824                         }
2825                         break;
2826                 }
2827
2828                 ++depth;
2829         }
2830
2831         /* Create a software table entry if necessary, and mark it
2832          * busy.  We might yet fail to insert, but any attempt to
2833          * insert a conflicting filter while we're waiting for the
2834          * firmware must find the busy entry.
2835          */
2836         saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
2837         if (saved_spec) {
2838                 replacing = true;
2839         } else {
2840                 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
2841                 if (!saved_spec) {
2842                         rc = -ENOMEM;
2843                         goto fail_unlock;
2844                 }
2845                 *saved_spec = *spec;
2846         }
2847         efx_ef10_filter_set_entry(table, ins_index, saved_spec,
2848                                   EFX_EF10_FILTER_FLAG_BUSY);
2849
2850         spin_unlock_bh(&efx->filter_lock);
2851
2852         /* Pack up the variables needed on completion */
2853         cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
2854
2855         efx_ef10_filter_push_prep(efx, spec, inbuf,
2856                                   table->entry[ins_index].handle, replacing);
2857         efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2858                            MC_CMD_FILTER_OP_OUT_LEN,
2859                            efx_ef10_filter_rfs_insert_complete, cookie);
2860
2861         return ins_index;
2862
2863 fail_unlock:
2864         spin_unlock_bh(&efx->filter_lock);
2865         return rc;
2866 }
2867
2868 static void
2869 efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
2870                                     int rc, efx_dword_t *outbuf,
2871                                     size_t outlen_actual)
2872 {
2873         struct efx_ef10_filter_table *table = efx->filter_state;
2874         unsigned int ins_index, dmaq_id;
2875         struct efx_filter_spec *spec;
2876         bool replacing;
2877
2878         /* Unpack the cookie */
2879         replacing = cookie >> 31;
2880         ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
2881         dmaq_id = cookie & 0xffff;
2882
2883         spin_lock_bh(&efx->filter_lock);
2884         spec = efx_ef10_filter_entry_spec(table, ins_index);
2885         if (rc == 0) {
2886                 table->entry[ins_index].handle =
2887                         MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
2888                 if (replacing)
2889                         spec->dmaq_id = dmaq_id;
2890         } else if (!replacing) {
2891                 kfree(spec);
2892                 spec = NULL;
2893         }
2894         efx_ef10_filter_set_entry(table, ins_index, spec, 0);
2895         spin_unlock_bh(&efx->filter_lock);
2896
2897         wake_up_all(&table->waitq);
2898 }
2899
2900 static void
2901 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
2902                                     unsigned long filter_idx,
2903                                     int rc, efx_dword_t *outbuf,
2904                                     size_t outlen_actual);
2905
2906 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
2907                                            unsigned int filter_idx)
2908 {
2909         struct efx_ef10_filter_table *table = efx->filter_state;
2910         struct efx_filter_spec *spec =
2911                 efx_ef10_filter_entry_spec(table, filter_idx);
2912         MCDI_DECLARE_BUF(inbuf,
2913                          MC_CMD_FILTER_OP_IN_HANDLE_OFST +
2914                          MC_CMD_FILTER_OP_IN_HANDLE_LEN);
2915
2916         if (!spec ||
2917             (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
2918             spec->priority != EFX_FILTER_PRI_HINT ||
2919             !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
2920                                  flow_id, filter_idx))
2921                 return false;
2922
2923         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2924                        MC_CMD_FILTER_OP_IN_OP_REMOVE);
2925         MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2926                        table->entry[filter_idx].handle);
2927         if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
2928                                efx_ef10_filter_rfs_expire_complete, filter_idx))
2929                 return false;
2930
2931         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
2932         return true;
2933 }
2934
2935 static void
2936 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
2937                                     unsigned long filter_idx,
2938                                     int rc, efx_dword_t *outbuf,
2939                                     size_t outlen_actual)
2940 {
2941         struct efx_ef10_filter_table *table = efx->filter_state;
2942         struct efx_filter_spec *spec =
2943                 efx_ef10_filter_entry_spec(table, filter_idx);
2944
2945         spin_lock_bh(&efx->filter_lock);
2946         if (rc == 0) {
2947                 kfree(spec);
2948                 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
2949         }
2950         table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
2951         wake_up_all(&table->waitq);
2952         spin_unlock_bh(&efx->filter_lock);
2953 }
2954
2955 #endif /* CONFIG_RFS_ACCEL */
2956
2957 static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
2958 {
2959         int match_flags = 0;
2960
2961 #define MAP_FLAG(gen_flag, mcdi_field) {                                \
2962                 u32 old_mcdi_flags = mcdi_flags;                        \
2963                 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ##      \
2964                                 mcdi_field ## _LBN);                    \
2965                 if (mcdi_flags != old_mcdi_flags)                       \
2966                         match_flags |= EFX_FILTER_MATCH_ ## gen_flag;   \
2967         }
2968         MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
2969         MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
2970         MAP_FLAG(REM_HOST, SRC_IP);
2971         MAP_FLAG(LOC_HOST, DST_IP);
2972         MAP_FLAG(REM_MAC, SRC_MAC);
2973         MAP_FLAG(REM_PORT, SRC_PORT);
2974         MAP_FLAG(LOC_MAC, DST_MAC);
2975         MAP_FLAG(LOC_PORT, DST_PORT);
2976         MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
2977         MAP_FLAG(INNER_VID, INNER_VLAN);
2978         MAP_FLAG(OUTER_VID, OUTER_VLAN);
2979         MAP_FLAG(IP_PROTO, IP_PROTO);
2980 #undef MAP_FLAG
2981
2982         /* Did we map them all? */
2983         if (mcdi_flags)
2984                 return -EINVAL;
2985
2986         return match_flags;
2987 }
2988
2989 static int efx_ef10_filter_table_probe(struct efx_nic *efx)
2990 {
2991         MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
2992         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
2993         unsigned int pd_match_pri, pd_match_count;
2994         struct efx_ef10_filter_table *table;
2995         size_t outlen;
2996         int rc;
2997
2998         table = kzalloc(sizeof(*table), GFP_KERNEL);
2999         if (!table)
3000                 return -ENOMEM;
3001
3002         /* Find out which RX filter types are supported, and their priorities */
3003         MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
3004                        MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
3005         rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
3006                           inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
3007                           &outlen);
3008         if (rc)
3009                 goto fail;
3010         pd_match_count = MCDI_VAR_ARRAY_LEN(
3011                 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
3012         table->rx_match_count = 0;
3013
3014         for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
3015                 u32 mcdi_flags =
3016                         MCDI_ARRAY_DWORD(
3017                                 outbuf,
3018                                 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
3019                                 pd_match_pri);
3020                 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
3021                 if (rc < 0) {
3022                         netif_dbg(efx, probe, efx->net_dev,
3023                                   "%s: fw flags %#x pri %u not supported in driver\n",
3024                                   __func__, mcdi_flags, pd_match_pri);
3025                 } else {
3026                         netif_dbg(efx, probe, efx->net_dev,
3027                                   "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
3028                                   __func__, mcdi_flags, pd_match_pri,
3029                                   rc, table->rx_match_count);
3030                         table->rx_match_flags[table->rx_match_count++] = rc;
3031                 }
3032         }
3033
3034         table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
3035         if (!table->entry) {
3036                 rc = -ENOMEM;
3037                 goto fail;
3038         }
3039
3040         efx->filter_state = table;
3041         init_waitqueue_head(&table->waitq);
3042         return 0;
3043
3044 fail:
3045         kfree(table);
3046         return rc;
3047 }
3048
3049 static void efx_ef10_filter_table_restore(struct efx_nic *efx)
3050 {
3051         struct efx_ef10_filter_table *table = efx->filter_state;
3052         struct efx_ef10_nic_data *nic_data = efx->nic_data;
3053         struct efx_filter_spec *spec;
3054         unsigned int filter_idx;
3055         bool failed = false;
3056         int rc;
3057
3058         if (!nic_data->must_restore_filters)
3059                 return;
3060
3061         spin_lock_bh(&efx->filter_lock);
3062
3063         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3064                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3065                 if (!spec)
3066                         continue;
3067
3068                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3069                 spin_unlock_bh(&efx->filter_lock);
3070
3071                 rc = efx_ef10_filter_push(efx, spec,
3072                                           &table->entry[filter_idx].handle,
3073                                           false);
3074                 if (rc)
3075                         failed = true;
3076
3077                 spin_lock_bh(&efx->filter_lock);
3078                 if (rc) {
3079                         kfree(spec);
3080                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3081                 } else {
3082                         table->entry[filter_idx].spec &=
3083                                 ~EFX_EF10_FILTER_FLAG_BUSY;
3084                 }
3085         }
3086
3087         spin_unlock_bh(&efx->filter_lock);
3088
3089         if (failed)
3090                 netif_err(efx, hw, efx->net_dev,
3091                           "unable to restore all filters\n");
3092         else
3093                 nic_data->must_restore_filters = false;
3094 }
3095
3096 static void efx_ef10_filter_table_remove(struct efx_nic *efx)
3097 {
3098         struct efx_ef10_filter_table *table = efx->filter_state;
3099         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3100         struct efx_filter_spec *spec;
3101         unsigned int filter_idx;
3102         int rc;
3103
3104         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3105                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3106                 if (!spec)
3107                         continue;
3108
3109                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3110                                efx_ef10_filter_is_exclusive(spec) ?
3111                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
3112                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3113                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3114                                table->entry[filter_idx].handle);
3115                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3116                                   NULL, 0, NULL);
3117                 if (rc)
3118                         netdev_WARN(efx->net_dev,
3119                                     "filter_idx=%#x handle=%#llx\n",
3120                                     filter_idx,
3121                                     table->entry[filter_idx].handle);
3122                 kfree(spec);
3123         }
3124
3125         vfree(table->entry);
3126         kfree(table);
3127 }
3128
3129 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
3130 {
3131         struct efx_ef10_filter_table *table = efx->filter_state;
3132         struct net_device *net_dev = efx->net_dev;
3133         struct efx_filter_spec spec;
3134         bool remove_failed = false;
3135         struct netdev_hw_addr *uc;
3136         struct netdev_hw_addr *mc;
3137         unsigned int filter_idx;
3138         int i, n, rc;
3139
3140         if (!efx_dev_registered(efx))
3141                 return;
3142
3143         /* Mark old filters that may need to be removed */
3144         spin_lock_bh(&efx->filter_lock);
3145         n = table->dev_uc_count < 0 ? 1 : table->dev_uc_count;
3146         for (i = 0; i < n; i++) {
3147                 filter_idx = table->dev_uc_list[i].id % HUNT_FILTER_TBL_ROWS;
3148                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
3149         }
3150         n = table->dev_mc_count < 0 ? 1 : table->dev_mc_count;
3151         for (i = 0; i < n; i++) {
3152                 filter_idx = table->dev_mc_list[i].id % HUNT_FILTER_TBL_ROWS;
3153                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
3154         }
3155         spin_unlock_bh(&efx->filter_lock);
3156
3157         /* Copy/convert the address lists; add the primary station
3158          * address and broadcast address
3159          */
3160         netif_addr_lock_bh(net_dev);
3161         if (net_dev->flags & IFF_PROMISC ||
3162             netdev_uc_count(net_dev) >= EFX_EF10_FILTER_DEV_UC_MAX) {
3163                 table->dev_uc_count = -1;
3164         } else {
3165                 table->dev_uc_count = 1 + netdev_uc_count(net_dev);
3166                 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
3167                 i = 1;
3168                 netdev_for_each_uc_addr(uc, net_dev) {
3169                         ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
3170                         i++;
3171                 }
3172         }
3173         if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI) ||
3174             netdev_mc_count(net_dev) >= EFX_EF10_FILTER_DEV_MC_MAX) {
3175                 table->dev_mc_count = -1;
3176         } else {
3177                 table->dev_mc_count = 1 + netdev_mc_count(net_dev);
3178                 eth_broadcast_addr(table->dev_mc_list[0].addr);
3179                 i = 1;
3180                 netdev_for_each_mc_addr(mc, net_dev) {
3181                         ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
3182                         i++;
3183                 }
3184         }
3185         netif_addr_unlock_bh(net_dev);
3186
3187         /* Insert/renew unicast filters */
3188         if (table->dev_uc_count >= 0) {
3189                 for (i = 0; i < table->dev_uc_count; i++) {
3190                         efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3191                                            EFX_FILTER_FLAG_RX_RSS,
3192                                            0);
3193                         efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
3194                                                  table->dev_uc_list[i].addr);
3195                         rc = efx_ef10_filter_insert(efx, &spec, true);
3196                         if (rc < 0) {
3197                                 /* Fall back to unicast-promisc */
3198                                 while (i--)
3199                                         efx_ef10_filter_remove_safe(
3200                                                 efx, EFX_FILTER_PRI_AUTO,
3201                                                 table->dev_uc_list[i].id);
3202                                 table->dev_uc_count = -1;
3203                                 break;
3204                         }
3205                         table->dev_uc_list[i].id = rc;
3206                 }
3207         }
3208         if (table->dev_uc_count < 0) {
3209                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3210                                    EFX_FILTER_FLAG_RX_RSS,
3211                                    0);
3212                 efx_filter_set_uc_def(&spec);
3213                 rc = efx_ef10_filter_insert(efx, &spec, true);
3214                 if (rc < 0) {
3215                         WARN_ON(1);
3216                         table->dev_uc_count = 0;
3217                 } else {
3218                         table->dev_uc_list[0].id = rc;
3219                 }
3220         }
3221
3222         /* Insert/renew multicast filters */
3223         if (table->dev_mc_count >= 0) {
3224                 for (i = 0; i < table->dev_mc_count; i++) {
3225                         efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3226                                            EFX_FILTER_FLAG_RX_RSS,
3227                                            0);
3228                         efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
3229                                                  table->dev_mc_list[i].addr);
3230                         rc = efx_ef10_filter_insert(efx, &spec, true);
3231                         if (rc < 0) {
3232                                 /* Fall back to multicast-promisc */
3233                                 while (i--)
3234                                         efx_ef10_filter_remove_safe(
3235                                                 efx, EFX_FILTER_PRI_AUTO,
3236                                                 table->dev_mc_list[i].id);
3237                                 table->dev_mc_count = -1;
3238                                 break;
3239                         }
3240                         table->dev_mc_list[i].id = rc;
3241                 }
3242         }
3243         if (table->dev_mc_count < 0) {
3244                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3245                                    EFX_FILTER_FLAG_RX_RSS,
3246                                    0);
3247                 efx_filter_set_mc_def(&spec);
3248                 rc = efx_ef10_filter_insert(efx, &spec, true);
3249                 if (rc < 0) {
3250                         WARN_ON(1);
3251                         table->dev_mc_count = 0;
3252                 } else {
3253                         table->dev_mc_list[0].id = rc;
3254                 }
3255         }
3256
3257         /* Remove filters that weren't renewed.  Since nothing else
3258          * changes the AUTO_OLD flag or removes these filters, we
3259          * don't need to hold the filter_lock while scanning for
3260          * these filters.
3261          */
3262         for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3263                 if (ACCESS_ONCE(table->entry[i].spec) &
3264                     EFX_EF10_FILTER_FLAG_AUTO_OLD) {
3265                         if (efx_ef10_filter_remove_internal(
3266                                     efx, 1U << EFX_FILTER_PRI_AUTO,
3267                                     i, true) < 0)
3268                                 remove_failed = true;
3269                 }
3270         }
3271         WARN_ON(remove_failed);
3272 }
3273
3274 static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
3275 {
3276         efx_ef10_filter_sync_rx_mode(efx);
3277
3278         return efx_mcdi_set_mac(efx);
3279 }
3280
3281 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
3282 {
3283         MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
3284
3285         MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
3286         return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
3287                             NULL, 0, NULL);
3288 }
3289
3290 /* MC BISTs follow a different poll mechanism to phy BISTs.
3291  * The BIST is done in the poll handler on the MC, and the MCDI command
3292  * will block until the BIST is done.
3293  */
3294 static int efx_ef10_poll_bist(struct efx_nic *efx)
3295 {
3296         int rc;
3297         MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
3298         size_t outlen;
3299         u32 result;
3300
3301         rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
3302                            outbuf, sizeof(outbuf), &outlen);
3303         if (rc != 0)
3304                 return rc;
3305
3306         if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
3307                 return -EIO;
3308
3309         result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
3310         switch (result) {
3311         case MC_CMD_POLL_BIST_PASSED:
3312                 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
3313                 return 0;
3314         case MC_CMD_POLL_BIST_TIMEOUT:
3315                 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
3316                 return -EIO;
3317         case MC_CMD_POLL_BIST_FAILED:
3318                 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
3319                 return -EIO;
3320         default:
3321                 netif_err(efx, hw, efx->net_dev,
3322                           "BIST returned unknown result %u", result);
3323                 return -EIO;
3324         }
3325 }
3326
3327 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
3328 {
3329         int rc;
3330
3331         netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
3332
3333         rc = efx_ef10_start_bist(efx, bist_type);
3334         if (rc != 0)
3335                 return rc;
3336
3337         return efx_ef10_poll_bist(efx);
3338 }
3339
3340 static int
3341 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
3342 {
3343         int rc, rc2;
3344
3345         efx_reset_down(efx, RESET_TYPE_WORLD);
3346
3347         rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
3348                           NULL, 0, NULL, 0, NULL);
3349         if (rc != 0)
3350                 goto out;
3351
3352         tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
3353         tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
3354
3355         rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
3356
3357 out:
3358         rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
3359         return rc ? rc : rc2;
3360 }
3361
3362 #ifdef CONFIG_SFC_MTD
3363
3364 struct efx_ef10_nvram_type_info {
3365         u16 type, type_mask;
3366         u8 port;
3367         const char *name;
3368 };
3369
3370 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
3371         { NVRAM_PARTITION_TYPE_MC_FIRMWARE,        0,    0, "sfc_mcfw" },
3372         { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0,    0, "sfc_mcfw_backup" },
3373         { NVRAM_PARTITION_TYPE_EXPANSION_ROM,      0,    0, "sfc_exp_rom" },
3374         { NVRAM_PARTITION_TYPE_STATIC_CONFIG,      0,    0, "sfc_static_cfg" },
3375         { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG,     0,    0, "sfc_dynamic_cfg" },
3376         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0,   0, "sfc_exp_rom_cfg" },
3377         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0,   1, "sfc_exp_rom_cfg" },
3378         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0,   2, "sfc_exp_rom_cfg" },
3379         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0,   3, "sfc_exp_rom_cfg" },
3380         { NVRAM_PARTITION_TYPE_LICENSE,            0,    0, "sfc_license" },
3381         { NVRAM_PARTITION_TYPE_PHY_MIN,            0xff, 0, "sfc_phy_fw" },
3382 };
3383
3384 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
3385                                         struct efx_mcdi_mtd_partition *part,
3386                                         unsigned int type)
3387 {
3388         MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
3389         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
3390         const struct efx_ef10_nvram_type_info *info;
3391         size_t size, erase_size, outlen;
3392         bool protected;
3393         int rc;
3394
3395         for (info = efx_ef10_nvram_types; ; info++) {
3396                 if (info ==
3397                     efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
3398                         return -ENODEV;
3399                 if ((type & ~info->type_mask) == info->type)
3400                         break;
3401         }
3402         if (info->port != efx_port_num(efx))
3403                 return -ENODEV;
3404
3405         rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
3406         if (rc)
3407                 return rc;
3408         if (protected)
3409                 return -ENODEV; /* hide it */
3410
3411         part->nvram_type = type;
3412
3413         MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
3414         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
3415                           outbuf, sizeof(outbuf), &outlen);
3416         if (rc)
3417                 return rc;
3418         if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
3419                 return -EIO;
3420         if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
3421             (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
3422                 part->fw_subtype = MCDI_DWORD(outbuf,
3423                                               NVRAM_METADATA_OUT_SUBTYPE);
3424
3425         part->common.dev_type_name = "EF10 NVRAM manager";
3426         part->common.type_name = info->name;
3427
3428         part->common.mtd.type = MTD_NORFLASH;
3429         part->common.mtd.flags = MTD_CAP_NORFLASH;
3430         part->common.mtd.size = size;
3431         part->common.mtd.erasesize = erase_size;
3432
3433         return 0;
3434 }
3435
3436 static int efx_ef10_mtd_probe(struct efx_nic *efx)
3437 {
3438         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
3439         struct efx_mcdi_mtd_partition *parts;
3440         size_t outlen, n_parts_total, i, n_parts;
3441         unsigned int type;
3442         int rc;
3443
3444         ASSERT_RTNL();
3445
3446         BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
3447         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
3448                           outbuf, sizeof(outbuf), &outlen);
3449         if (rc)
3450                 return rc;
3451         if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
3452                 return -EIO;
3453
3454         n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
3455         if (n_parts_total >
3456             MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
3457                 return -EIO;
3458
3459         parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
3460         if (!parts)
3461                 return -ENOMEM;
3462
3463         n_parts = 0;
3464         for (i = 0; i < n_parts_total; i++) {
3465                 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
3466                                         i);
3467                 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
3468                 if (rc == 0)
3469                         n_parts++;
3470                 else if (rc != -ENODEV)
3471                         goto fail;
3472         }
3473
3474         rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
3475 fail:
3476         if (rc)
3477                 kfree(parts);
3478         return rc;
3479 }
3480
3481 #endif /* CONFIG_SFC_MTD */
3482
3483 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
3484 {
3485         _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
3486 }
3487
3488 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
3489                                            bool temp)
3490 {
3491         MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
3492         int rc;
3493
3494         if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
3495             channel->sync_events_state == SYNC_EVENTS_VALID ||
3496             (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
3497                 return 0;
3498         channel->sync_events_state = SYNC_EVENTS_REQUESTED;
3499
3500         MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
3501         MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
3502         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
3503                        channel->channel);
3504
3505         rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
3506                           inbuf, sizeof(inbuf), NULL, 0, NULL);
3507
3508         if (rc != 0)
3509                 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
3510                                                     SYNC_EVENTS_DISABLED;
3511
3512         return rc;
3513 }
3514
3515 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
3516                                             bool temp)
3517 {
3518         MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
3519         int rc;
3520
3521         if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
3522             (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
3523                 return 0;
3524         if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
3525                 channel->sync_events_state = SYNC_EVENTS_DISABLED;
3526                 return 0;
3527         }
3528         channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
3529                                             SYNC_EVENTS_DISABLED;
3530
3531         MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
3532         MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
3533         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
3534                        MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
3535         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
3536                        channel->channel);
3537
3538         rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
3539                           inbuf, sizeof(inbuf), NULL, 0, NULL);
3540
3541         return rc;
3542 }
3543
3544 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
3545                                            bool temp)
3546 {
3547         int (*set)(struct efx_channel *channel, bool temp);
3548         struct efx_channel *channel;
3549
3550         set = en ?
3551               efx_ef10_rx_enable_timestamping :
3552               efx_ef10_rx_disable_timestamping;
3553
3554         efx_for_each_channel(channel, efx) {
3555                 int rc = set(channel, temp);
3556                 if (en && rc != 0) {
3557                         efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
3558                         return rc;
3559                 }
3560         }
3561
3562         return 0;
3563 }
3564
3565 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
3566                                       struct hwtstamp_config *init)
3567 {
3568         int rc;
3569
3570         switch (init->rx_filter) {
3571         case HWTSTAMP_FILTER_NONE:
3572                 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
3573                 /* if TX timestamping is still requested then leave PTP on */
3574                 return efx_ptp_change_mode(efx,
3575                                            init->tx_type != HWTSTAMP_TX_OFF, 0);
3576         case HWTSTAMP_FILTER_ALL:
3577         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3578         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3579         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3580         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3581         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3582         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3583         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3584         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3585         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3586         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3587         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3588         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3589                 init->rx_filter = HWTSTAMP_FILTER_ALL;
3590                 rc = efx_ptp_change_mode(efx, true, 0);
3591                 if (!rc)
3592                         rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
3593                 if (rc)
3594                         efx_ptp_change_mode(efx, false, 0);
3595                 return rc;
3596         default:
3597                 return -ERANGE;
3598         }
3599 }
3600
3601 const struct efx_nic_type efx_hunt_a0_nic_type = {
3602         .mem_map_size = efx_ef10_mem_map_size,
3603         .probe = efx_ef10_probe,
3604         .remove = efx_ef10_remove,
3605         .dimension_resources = efx_ef10_dimension_resources,
3606         .init = efx_ef10_init_nic,
3607         .fini = efx_port_dummy_op_void,
3608         .map_reset_reason = efx_mcdi_map_reset_reason,
3609         .map_reset_flags = efx_ef10_map_reset_flags,
3610         .reset = efx_ef10_reset,
3611         .probe_port = efx_mcdi_port_probe,
3612         .remove_port = efx_mcdi_port_remove,
3613         .fini_dmaq = efx_ef10_fini_dmaq,
3614         .prepare_flr = efx_ef10_prepare_flr,
3615         .finish_flr = efx_port_dummy_op_void,
3616         .describe_stats = efx_ef10_describe_stats,
3617         .update_stats = efx_ef10_update_stats,
3618         .start_stats = efx_mcdi_mac_start_stats,
3619         .pull_stats = efx_mcdi_mac_pull_stats,
3620         .stop_stats = efx_mcdi_mac_stop_stats,
3621         .set_id_led = efx_mcdi_set_id_led,
3622         .push_irq_moderation = efx_ef10_push_irq_moderation,
3623         .reconfigure_mac = efx_ef10_mac_reconfigure,
3624         .check_mac_fault = efx_mcdi_mac_check_fault,
3625         .reconfigure_port = efx_mcdi_port_reconfigure,
3626         .get_wol = efx_ef10_get_wol,
3627         .set_wol = efx_ef10_set_wol,
3628         .resume_wol = efx_port_dummy_op_void,
3629         .test_chip = efx_ef10_test_chip,
3630         .test_nvram = efx_mcdi_nvram_test_all,
3631         .mcdi_request = efx_ef10_mcdi_request,
3632         .mcdi_poll_response = efx_ef10_mcdi_poll_response,
3633         .mcdi_read_response = efx_ef10_mcdi_read_response,
3634         .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
3635         .irq_enable_master = efx_port_dummy_op_void,
3636         .irq_test_generate = efx_ef10_irq_test_generate,
3637         .irq_disable_non_ev = efx_port_dummy_op_void,
3638         .irq_handle_msi = efx_ef10_msi_interrupt,
3639         .irq_handle_legacy = efx_ef10_legacy_interrupt,
3640         .tx_probe = efx_ef10_tx_probe,
3641         .tx_init = efx_ef10_tx_init,
3642         .tx_remove = efx_ef10_tx_remove,
3643         .tx_write = efx_ef10_tx_write,
3644         .rx_push_rss_config = efx_ef10_rx_push_rss_config,
3645         .rx_probe = efx_ef10_rx_probe,
3646         .rx_init = efx_ef10_rx_init,
3647         .rx_remove = efx_ef10_rx_remove,
3648         .rx_write = efx_ef10_rx_write,
3649         .rx_defer_refill = efx_ef10_rx_defer_refill,
3650         .ev_probe = efx_ef10_ev_probe,
3651         .ev_init = efx_ef10_ev_init,
3652         .ev_fini = efx_ef10_ev_fini,
3653         .ev_remove = efx_ef10_ev_remove,
3654         .ev_process = efx_ef10_ev_process,
3655         .ev_read_ack = efx_ef10_ev_read_ack,
3656         .ev_test_generate = efx_ef10_ev_test_generate,
3657         .filter_table_probe = efx_ef10_filter_table_probe,
3658         .filter_table_restore = efx_ef10_filter_table_restore,
3659         .filter_table_remove = efx_ef10_filter_table_remove,
3660         .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
3661         .filter_insert = efx_ef10_filter_insert,
3662         .filter_remove_safe = efx_ef10_filter_remove_safe,
3663         .filter_get_safe = efx_ef10_filter_get_safe,
3664         .filter_clear_rx = efx_ef10_filter_clear_rx,
3665         .filter_count_rx_used = efx_ef10_filter_count_rx_used,
3666         .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
3667         .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
3668 #ifdef CONFIG_RFS_ACCEL
3669         .filter_rfs_insert = efx_ef10_filter_rfs_insert,
3670         .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
3671 #endif
3672 #ifdef CONFIG_SFC_MTD
3673         .mtd_probe = efx_ef10_mtd_probe,
3674         .mtd_rename = efx_mcdi_mtd_rename,
3675         .mtd_read = efx_mcdi_mtd_read,
3676         .mtd_erase = efx_mcdi_mtd_erase,
3677         .mtd_write = efx_mcdi_mtd_write,
3678         .mtd_sync = efx_mcdi_mtd_sync,
3679 #endif
3680         .ptp_write_host_time = efx_ef10_ptp_write_host_time,
3681         .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
3682         .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
3683
3684         .revision = EFX_REV_HUNT_A0,
3685         .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
3686         .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
3687         .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
3688         .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
3689         .can_rx_scatter = true,
3690         .always_rx_scatter = true,
3691         .max_interrupt_mode = EFX_INT_MODE_MSIX,
3692         .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
3693         .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3694                              NETIF_F_RXHASH | NETIF_F_NTUPLE),
3695         .mcdi_max_ver = 2,
3696         .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
3697         .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
3698                             1 << HWTSTAMP_FILTER_ALL,
3699 };