drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pci-aspm.h>
  30 #include <linux/prefetch.h>
  31
  32 #include <asm/system.h>
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38 #define PFX MODULENAME ": "
  39
  40 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  41 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  42 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  43 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  44 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  45 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  46 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  47 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  48
  49 #ifdef RTL8169_DEBUG
  50 #define assert(expr) \
  51         if (!(expr)) {                                  \
  52                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  53                 #expr,__FILE__,__func__,__LINE__);              \
  54         }
  55 #define dprintk(fmt, args...) \
  56         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  57 #else
  58 #define assert(expr) do {} while (0)
  59 #define dprintk(fmt, args...)   do {} while (0)
  60 #endif /* RTL8169_DEBUG */
  61
  62 #define R8169_MSG_DEFAULT \
  63         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  64
  65 #define TX_SLOTS_AVAIL(tp) \
  66         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  67
  68 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  69 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  70         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  71
  72 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  73    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  74 static const int multicast_filter_limit = 32;
  75
  76 /* MAC address length */
  77 #define MAC_ADDR_LEN    6
  78
  79 #define MAX_READ_REQUEST_SHIFT  12
  80 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  81 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  82 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  83
  84 #define R8169_REGS_SIZE         256
  85 #define R8169_NAPI_WEIGHT       64
  86 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  87 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  88 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  89 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  90 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  91
  92 #define RTL8169_TX_TIMEOUT      (6*HZ)
  93 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  94
  95 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  96 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  97 #define RTL_EEPROM_SIG_ADDR     0x0000
  98
  99 /* write/read MMIO register */
 100 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
 101 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
 102 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
 103 #define RTL_R8(reg)             readb (ioaddr + (reg))
 104 #define RTL_R16(reg)            readw (ioaddr + (reg))
 105 #define RTL_R32(reg)            readl (ioaddr + (reg))
 106
 107 enum mac_version {
 108         RTL_GIGA_MAC_VER_01 = 0,
 109         RTL_GIGA_MAC_VER_02,
 110         RTL_GIGA_MAC_VER_03,
 111         RTL_GIGA_MAC_VER_04,
 112         RTL_GIGA_MAC_VER_05,
 113         RTL_GIGA_MAC_VER_06,
 114         RTL_GIGA_MAC_VER_07,
 115         RTL_GIGA_MAC_VER_08,
 116         RTL_GIGA_MAC_VER_09,
 117         RTL_GIGA_MAC_VER_10,
 118         RTL_GIGA_MAC_VER_11,
 119         RTL_GIGA_MAC_VER_12,
 120         RTL_GIGA_MAC_VER_13,
 121         RTL_GIGA_MAC_VER_14,
 122         RTL_GIGA_MAC_VER_15,
 123         RTL_GIGA_MAC_VER_16,
 124         RTL_GIGA_MAC_VER_17,
 125         RTL_GIGA_MAC_VER_18,
 126         RTL_GIGA_MAC_VER_19,
 127         RTL_GIGA_MAC_VER_20,
 128         RTL_GIGA_MAC_VER_21,
 129         RTL_GIGA_MAC_VER_22,
 130         RTL_GIGA_MAC_VER_23,
 131         RTL_GIGA_MAC_VER_24,
 132         RTL_GIGA_MAC_VER_25,
 133         RTL_GIGA_MAC_VER_26,
 134         RTL_GIGA_MAC_VER_27,
 135         RTL_GIGA_MAC_VER_28,
 136         RTL_GIGA_MAC_VER_29,
 137         RTL_GIGA_MAC_VER_30,
 138         RTL_GIGA_MAC_VER_31,
 139         RTL_GIGA_MAC_VER_32,
 140         RTL_GIGA_MAC_VER_33,
 141         RTL_GIGA_MAC_VER_34,
 142         RTL_GIGA_MAC_VER_35,
 143         RTL_GIGA_MAC_VER_36,
 144         RTL_GIGA_MAC_NONE   = 0xff,
 145 };
 146
 147 enum rtl_tx_desc_version {
 148         RTL_TD_0        = 0,
 149         RTL_TD_1        = 1,
 150 };
 151
 152 #define JUMBO_1K        ETH_DATA_LEN
 153 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 154 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 155 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 156 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 157
 158 #define _R(NAME,TD,FW,SZ,B) {   \
 159         .name = NAME,           \
 160         .txd_version = TD,      \
 161         .fw_name = FW,          \
 162         .jumbo_max = SZ,        \
 163         .jumbo_tx_csum = B      \
 164 }
 165
 166 static const struct {
 167         const char *name;
 168         enum rtl_tx_desc_version txd_version;
 169         const char *fw_name;
 170         u16 jumbo_max;
 171         bool jumbo_tx_csum;
 172 } rtl_chip_infos[] = {
 173         /* PCI devices. */
 174         [RTL_GIGA_MAC_VER_01] =
 175                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 176         [RTL_GIGA_MAC_VER_02] =
 177                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 178         [RTL_GIGA_MAC_VER_03] =
 179                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 180         [RTL_GIGA_MAC_VER_04] =
 181                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 182         [RTL_GIGA_MAC_VER_05] =
 183                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 184         [RTL_GIGA_MAC_VER_06] =
 185                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 186         /* PCI-E devices. */
 187         [RTL_GIGA_MAC_VER_07] =
 188                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 189         [RTL_GIGA_MAC_VER_08] =
 190                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 191         [RTL_GIGA_MAC_VER_09] =
 192                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 193         [RTL_GIGA_MAC_VER_10] =
 194                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 195         [RTL_GIGA_MAC_VER_11] =
 196                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 197         [RTL_GIGA_MAC_VER_12] =
 198                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 199         [RTL_GIGA_MAC_VER_13] =
 200                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 201         [RTL_GIGA_MAC_VER_14] =
 202                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 203         [RTL_GIGA_MAC_VER_15] =
 204                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 205         [RTL_GIGA_MAC_VER_16] =
 206                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 207         [RTL_GIGA_MAC_VER_17] =
 208                 _R("RTL8168b/8111b",    RTL_TD_1, NULL, JUMBO_4K, false),
 209         [RTL_GIGA_MAC_VER_18] =
 210                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 211         [RTL_GIGA_MAC_VER_19] =
 212                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 213         [RTL_GIGA_MAC_VER_20] =
 214                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 215         [RTL_GIGA_MAC_VER_21] =
 216                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 217         [RTL_GIGA_MAC_VER_22] =
 218                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 219         [RTL_GIGA_MAC_VER_23] =
 220                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 221         [RTL_GIGA_MAC_VER_24] =
 222                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 223         [RTL_GIGA_MAC_VER_25] =
 224                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 225                                                         JUMBO_9K, false),
 226         [RTL_GIGA_MAC_VER_26] =
 227                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 228                                                         JUMBO_9K, false),
 229         [RTL_GIGA_MAC_VER_27] =
 230                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 231         [RTL_GIGA_MAC_VER_28] =
 232                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 233         [RTL_GIGA_MAC_VER_29] =
 234                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 235                                                         JUMBO_1K, true),
 236         [RTL_GIGA_MAC_VER_30] =
 237                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 238                                                         JUMBO_1K, true),
 239         [RTL_GIGA_MAC_VER_31] =
 240                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 241         [RTL_GIGA_MAC_VER_32] =
 242                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 243                                                         JUMBO_9K, false),
 244         [RTL_GIGA_MAC_VER_33] =
 245                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 246                                                         JUMBO_9K, false),
 247         [RTL_GIGA_MAC_VER_34] =
 248                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 249                                                         JUMBO_9K, false),
 250         [RTL_GIGA_MAC_VER_35] =
 251                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 252                                                         JUMBO_9K, false),
 253         [RTL_GIGA_MAC_VER_36] =
 254                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 255                                                         JUMBO_9K, false),
 256 };
 257 #undef _R
 258
 259 enum cfg_version {
 260         RTL_CFG_0 = 0x00,
 261         RTL_CFG_1,
 262         RTL_CFG_2
 263 };
 264
 265 static void rtl_hw_start_8169(struct net_device *);
 266 static void rtl_hw_start_8168(struct net_device *);
 267 static void rtl_hw_start_8101(struct net_device *);
 268
 269 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 270         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 271         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 272         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 273         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 274         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 275         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 276         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 277         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 278         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 279         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 280                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 281         { 0x0001,                               0x8168,
 282                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 283         {0,},
 284 };
 285
 286 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 287
 288 static int rx_buf_sz = 16383;
 289 static int use_dac;
 290 static struct {
 291         u32 msg_enable;
 292 } debug = { -1 };
 293
 294 enum rtl_registers {
 295         MAC0            = 0,    /* Ethernet hardware address. */
 296         MAC4            = 4,
 297         MAR0            = 8,    /* Multicast filter. */
 298         CounterAddrLow          = 0x10,
 299         CounterAddrHigh         = 0x14,
 300         TxDescStartAddrLow      = 0x20,
 301         TxDescStartAddrHigh     = 0x24,
 302         TxHDescStartAddrLow     = 0x28,
 303         TxHDescStartAddrHigh    = 0x2c,
 304         FLASH           = 0x30,
 305         ERSR            = 0x36,
 306         ChipCmd         = 0x37,
 307         TxPoll          = 0x38,
 308         IntrMask        = 0x3c,
 309         IntrStatus      = 0x3e,
 310
 311         TxConfig        = 0x40,
 312 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 313 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 314
 315         RxConfig        = 0x44,
 316 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 317 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 318 #define RXCFG_FIFO_SHIFT                13
 319                                         /* No threshold before first PCI xfer */
 320 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 321 #define RXCFG_DMA_SHIFT                 8
 322                                         /* Unlimited maximum PCI burst. */
 323 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 324
 325         RxMissed        = 0x4c,
 326         Cfg9346         = 0x50,
 327         Config0         = 0x51,
 328         Config1         = 0x52,
 329         Config2         = 0x53,
 330         Config3         = 0x54,
 331         Config4         = 0x55,
 332         Config5         = 0x56,
 333         MultiIntr       = 0x5c,
 334         PHYAR           = 0x60,
 335         PHYstatus       = 0x6c,
 336         RxMaxSize       = 0xda,
 337         CPlusCmd        = 0xe0,
 338         IntrMitigate    = 0xe2,
 339         RxDescAddrLow   = 0xe4,
 340         RxDescAddrHigh  = 0xe8,
 341         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 342
 343 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 344
 345         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 346
 347 #define TxPacketMax     (8064 >> 7)
 348 #define EarlySize       0x27
 349
 350         FuncEvent       = 0xf0,
 351         FuncEventMask   = 0xf4,
 352         FuncPresetState = 0xf8,
 353         FuncForceEvent  = 0xfc,
 354 };
 355
 356 enum rtl8110_registers {
 357         TBICSR                  = 0x64,
 358         TBI_ANAR                = 0x68,
 359         TBI_LPAR                = 0x6a,
 360 };
 361
 362 enum rtl8168_8101_registers {
 363         CSIDR                   = 0x64,
 364         CSIAR                   = 0x68,
 365 #define CSIAR_FLAG                      0x80000000
 366 #define CSIAR_WRITE_CMD                 0x80000000
 367 #define CSIAR_BYTE_ENABLE               0x0f
 368 #define CSIAR_BYTE_ENABLE_SHIFT         12
 369 #define CSIAR_ADDR_MASK                 0x0fff
 370         PMCH                    = 0x6f,
 371         EPHYAR                  = 0x80,
 372 #define EPHYAR_FLAG                     0x80000000
 373 #define EPHYAR_WRITE_CMD                0x80000000
 374 #define EPHYAR_REG_MASK                 0x1f
 375 #define EPHYAR_REG_SHIFT                16
 376 #define EPHYAR_DATA_MASK                0xffff
 377         DLLPR                   = 0xd0,
 378 #define PFM_EN                          (1 << 6)
 379         DBG_REG                 = 0xd1,
 380 #define FIX_NAK_1                       (1 << 4)
 381 #define FIX_NAK_2                       (1 << 3)
 382         TWSI                    = 0xd2,
 383         MCU                     = 0xd3,
 384 #define NOW_IS_OOB                      (1 << 7)
 385 #define EN_NDP                          (1 << 3)
 386 #define EN_OOB_RESET                    (1 << 2)
 387         EFUSEAR                 = 0xdc,
 388 #define EFUSEAR_FLAG                    0x80000000
 389 #define EFUSEAR_WRITE_CMD               0x80000000
 390 #define EFUSEAR_READ_CMD                0x00000000
 391 #define EFUSEAR_REG_MASK                0x03ff
 392 #define EFUSEAR_REG_SHIFT               8
 393 #define EFUSEAR_DATA_MASK               0xff
 394 };
 395
 396 enum rtl8168_registers {
 397         LED_FREQ                = 0x1a,
 398         EEE_LED                 = 0x1b,
 399         ERIDR                   = 0x70,
 400         ERIAR                   = 0x74,
 401 #define ERIAR_FLAG                      0x80000000
 402 #define ERIAR_WRITE_CMD                 0x80000000
 403 #define ERIAR_READ_CMD                  0x00000000
 404 #define ERIAR_ADDR_BYTE_ALIGN           4
 405 #define ERIAR_TYPE_SHIFT                16
 406 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 407 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 408 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 409 #define ERIAR_MASK_SHIFT                12
 410 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 411 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 412 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 413         EPHY_RXER_NUM           = 0x7c,
 414         OCPDR                   = 0xb0, /* OCP GPHY access */
 415 #define OCPDR_WRITE_CMD                 0x80000000
 416 #define OCPDR_READ_CMD                  0x00000000
 417 #define OCPDR_REG_MASK                  0x7f
 418 #define OCPDR_GPHY_REG_SHIFT            16
 419 #define OCPDR_DATA_MASK                 0xffff
 420         OCPAR                   = 0xb4,
 421 #define OCPAR_FLAG                      0x80000000
 422 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 423 #define OCPAR_GPHY_READ_CMD             0x0000f060
 424         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 425         MISC                    = 0xf0, /* 8168e only. */
 426 #define TXPLA_RST                       (1 << 29)
 427 #define PWM_EN                          (1 << 22)
 428 };
 429
 430 enum rtl_register_content {
 431         /* InterruptStatusBits */
 432         SYSErr          = 0x8000,
 433         PCSTimeout      = 0x4000,
 434         SWInt           = 0x0100,
 435         TxDescUnavail   = 0x0080,
 436         RxFIFOOver      = 0x0040,
 437         LinkChg         = 0x0020,
 438         RxOverflow      = 0x0010,
 439         TxErr           = 0x0008,
 440         TxOK            = 0x0004,
 441         RxErr           = 0x0002,
 442         RxOK            = 0x0001,
 443
 444         /* RxStatusDesc */
 445         RxBOVF  = (1 << 24),
 446         RxFOVF  = (1 << 23),
 447         RxRWT   = (1 << 22),
 448         RxRES   = (1 << 21),
 449         RxRUNT  = (1 << 20),
 450         RxCRC   = (1 << 19),
 451
 452         /* ChipCmdBits */
 453         StopReq         = 0x80,
 454         CmdReset        = 0x10,
 455         CmdRxEnb        = 0x08,
 456         CmdTxEnb        = 0x04,
 457         RxBufEmpty      = 0x01,
 458
 459         /* TXPoll register p.5 */
 460         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 461         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 462         FSWInt          = 0x01,         /* Forced software interrupt */
 463
 464         /* Cfg9346Bits */
 465         Cfg9346_Lock    = 0x00,
 466         Cfg9346_Unlock  = 0xc0,
 467
 468         /* rx_mode_bits */
 469         AcceptErr       = 0x20,
 470         AcceptRunt      = 0x10,
 471         AcceptBroadcast = 0x08,
 472         AcceptMulticast = 0x04,
 473         AcceptMyPhys    = 0x02,
 474         AcceptAllPhys   = 0x01,
 475 #define RX_CONFIG_ACCEPT_MASK           0x3f
 476
 477         /* TxConfigBits */
 478         TxInterFrameGapShift = 24,
 479         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 480
 481         /* Config1 register p.24 */
 482         LEDS1           = (1 << 7),
 483         LEDS0           = (1 << 6),
 484         Speed_down      = (1 << 4),
 485         MEMMAP          = (1 << 3),
 486         IOMAP           = (1 << 2),
 487         VPD             = (1 << 1),
 488         PMEnable        = (1 << 0),     /* Power Management Enable */
 489
 490         /* Config2 register p. 25 */
 491         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 492         PCI_Clock_66MHz = 0x01,
 493         PCI_Clock_33MHz = 0x00,
 494
 495         /* Config3 register p.25 */
 496         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 497         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 498         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 499         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 500
 501         /* Config4 register */
 502         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 503
 504         /* Config5 register p.27 */
 505         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 506         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 507         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 508         Spi_en          = (1 << 3),
 509         LanWake         = (1 << 1),     /* LanWake enable/disable */
 510         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 511
 512         /* TBICSR p.28 */
 513         TBIReset        = 0x80000000,
 514         TBILoopback     = 0x40000000,
 515         TBINwEnable     = 0x20000000,
 516         TBINwRestart    = 0x10000000,
 517         TBILinkOk       = 0x02000000,
 518         TBINwComplete   = 0x01000000,
 519
 520         /* CPlusCmd p.31 */
 521         EnableBist      = (1 << 15),    // 8168 8101
 522         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 523         Normal_mode     = (1 << 13),    // unused
 524         Force_half_dup  = (1 << 12),    // 8168 8101
 525         Force_rxflow_en = (1 << 11),    // 8168 8101
 526         Force_txflow_en = (1 << 10),    // 8168 8101
 527         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 528         ASF             = (1 << 8),     // 8168 8101
 529         PktCntrDisable  = (1 << 7),     // 8168 8101
 530         Mac_dbgo_sel    = 0x001c,       // 8168
 531         RxVlan          = (1 << 6),
 532         RxChkSum        = (1 << 5),
 533         PCIDAC          = (1 << 4),
 534         PCIMulRW        = (1 << 3),
 535         INTT_0          = 0x0000,       // 8168
 536         INTT_1          = 0x0001,       // 8168
 537         INTT_2          = 0x0002,       // 8168
 538         INTT_3          = 0x0003,       // 8168
 539
 540         /* rtl8169_PHYstatus */
 541         TBI_Enable      = 0x80,
 542         TxFlowCtrl      = 0x40,
 543         RxFlowCtrl      = 0x20,
 544         _1000bpsF       = 0x10,
 545         _100bps         = 0x08,
 546         _10bps          = 0x04,
 547         LinkStatus      = 0x02,
 548         FullDup         = 0x01,
 549
 550         /* _TBICSRBit */
 551         TBILinkOK       = 0x02000000,
 552
 553         /* DumpCounterCommand */
 554         CounterDump     = 0x8,
 555 };
 556
 557 enum rtl_desc_bit {
 558         /* First doubleword. */
 559         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 560         RingEnd         = (1 << 30), /* End of descriptor ring */
 561         FirstFrag       = (1 << 29), /* First segment of a packet */
 562         LastFrag        = (1 << 28), /* Final segment of a packet */
 563 };
 564
 565 /* Generic case. */
 566 enum rtl_tx_desc_bit {
 567         /* First doubleword. */
 568         TD_LSO          = (1 << 27),            /* Large Send Offload */
 569 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 570
 571         /* Second doubleword. */
 572         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 573 };
 574
 575 /* 8169, 8168b and 810x except 8102e. */
 576 enum rtl_tx_desc_bit_0 {
 577         /* First doubleword. */
 578 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 579         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 580         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 581         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 582 };
 583
 584 /* 8102e, 8168c and beyond. */
 585 enum rtl_tx_desc_bit_1 {
 586         /* Second doubleword. */
 587 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 588         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 589         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 590         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 591 };
 592
 593 static const struct rtl_tx_desc_info {
 594         struct {
 595                 u32 udp;
 596                 u32 tcp;
 597         } checksum;
 598         u16 mss_shift;
 599         u16 opts_offset;
 600 } tx_desc_info [] = {
 601         [RTL_TD_0] = {
 602                 .checksum = {
 603                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 604                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 605                 },
 606                 .mss_shift      = TD0_MSS_SHIFT,
 607                 .opts_offset    = 0
 608         },
 609         [RTL_TD_1] = {
 610                 .checksum = {
 611                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 612                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 613                 },
 614                 .mss_shift      = TD1_MSS_SHIFT,
 615                 .opts_offset    = 1
 616         }
 617 };
 618
 619 enum rtl_rx_desc_bit {
 620         /* Rx private */
 621         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 622         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 623
 624 #define RxProtoUDP      (PID1)
 625 #define RxProtoTCP      (PID0)
 626 #define RxProtoIP       (PID1 | PID0)
 627 #define RxProtoMask     RxProtoIP
 628
 629         IPFail          = (1 << 16), /* IP checksum failed */
 630         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 631         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 632         RxVlanTag       = (1 << 16), /* VLAN tag available */
 633 };
 634
 635 #define RsvdMask        0x3fffc000
 636
 637 struct TxDesc {
 638         __le32 opts1;
 639         __le32 opts2;
 640         __le64 addr;
 641 };
 642
 643 struct RxDesc {
 644         __le32 opts1;
 645         __le32 opts2;
 646         __le64 addr;
 647 };
 648
 649 struct ring_info {
 650         struct sk_buff  *skb;
 651         u32             len;
 652         u8              __pad[sizeof(void *) - sizeof(u32)];
 653 };
 654
 655 enum features {
 656         RTL_FEATURE_WOL         = (1 << 0),
 657         RTL_FEATURE_MSI         = (1 << 1),
 658         RTL_FEATURE_GMII        = (1 << 2),
 659 };
 660
 661 struct rtl8169_counters {
 662         __le64  tx_packets;
 663         __le64  rx_packets;
 664         __le64  tx_errors;
 665         __le32  rx_errors;
 666         __le16  rx_missed;
 667         __le16  align_errors;
 668         __le32  tx_one_collision;
 669         __le32  tx_multi_collision;
 670         __le64  rx_unicast;
 671         __le64  rx_broadcast;
 672         __le32  rx_multicast;
 673         __le16  tx_aborted;
 674         __le16  tx_underun;
 675 };
 676
 677 struct rtl8169_private {
 678         void __iomem *mmio_addr;        /* memory map physical address */
 679         struct pci_dev *pci_dev;
 680         struct net_device *dev;
 681         struct napi_struct napi;
 682         spinlock_t lock;
 683         u32 msg_enable;
 684         u16 txd_version;
 685         u16 mac_version;
 686         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 687         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 688         u32 dirty_rx;
 689         u32 dirty_tx;
 690         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 691         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 692         dma_addr_t TxPhyAddr;
 693         dma_addr_t RxPhyAddr;
 694         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 695         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 696         struct timer_list timer;
 697         u16 cp_cmd;
 698         u16 intr_event;
 699         u16 napi_event;
 700         u16 intr_mask;
 701
 702         struct mdio_ops {
 703                 void (*write)(void __iomem *, int, int);
 704                 int (*read)(void __iomem *, int);
 705         } mdio_ops;
 706
 707         struct pll_power_ops {
 708                 void (*down)(struct rtl8169_private *);
 709                 void (*up)(struct rtl8169_private *);
 710         } pll_power_ops;
 711
 712         struct jumbo_ops {
 713                 void (*enable)(struct rtl8169_private *);
 714                 void (*disable)(struct rtl8169_private *);
 715         } jumbo_ops;
 716
 717         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 718         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 719         void (*phy_reset_enable)(struct rtl8169_private *tp);
 720         void (*hw_start)(struct net_device *);
 721         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 722         unsigned int (*link_ok)(void __iomem *);
 723         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 724         struct delayed_work task;
 725         unsigned features;
 726
 727         struct mii_if_info mii;
 728         struct rtl8169_counters counters;
 729         u32 saved_wolopts;
 730         u32 opts1_mask;
 731
 732         struct rtl_fw {
 733                 const struct firmware *fw;
 734
 735 #define RTL_VER_SIZE            32
 736
 737                 char version[RTL_VER_SIZE];
 738
 739                 struct rtl_fw_phy_action {
 740                         __le32 *code;
 741                         size_t size;
 742                 } phy_action;
 743         } *rtl_fw;
 744 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 745 };
 746
 747 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 748 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 749 module_param(use_dac, int, 0);
 750 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 751 module_param_named(debug, debug.msg_enable, int, 0);
 752 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 753 MODULE_LICENSE("GPL");
 754 MODULE_VERSION(RTL8169_VERSION);
 755 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 756 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 757 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 758 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 759 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 760 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 761 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 762 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 763
 764 static int rtl8169_open(struct net_device *dev);
 765 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
 766                                       struct net_device *dev);
 767 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 768 static int rtl8169_init_ring(struct net_device *dev);
 769 static void rtl_hw_start(struct net_device *dev);
 770 static int rtl8169_close(struct net_device *dev);
 771 static void rtl_set_rx_mode(struct net_device *dev);
 772 static void rtl8169_tx_timeout(struct net_device *dev);
 773 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 774 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 775                                 void __iomem *, u32 budget);
 776 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 777 static void rtl8169_down(struct net_device *dev);
 778 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 779 static int rtl8169_poll(struct napi_struct *napi, int budget);
 780
 781 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 782 {
 783         int cap = pci_pcie_cap(pdev);
 784
 785         if (cap) {
 786                 u16 ctl;
 787
 788                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
 789                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
 790                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
 791         }
 792 }
 793
 794 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 795 {
 796         void __iomem *ioaddr = tp->mmio_addr;
 797         int i;
 798
 799         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 800         for (i = 0; i < 20; i++) {
 801                 udelay(100);
 802                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 803                         break;
 804         }
 805         return RTL_R32(OCPDR);
 806 }
 807
 808 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 809 {
 810         void __iomem *ioaddr = tp->mmio_addr;
 811         int i;
 812
 813         RTL_W32(OCPDR, data);
 814         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 815         for (i = 0; i < 20; i++) {
 816                 udelay(100);
 817                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 818                         break;
 819         }
 820 }
 821
 822 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 823 {
 824         void __iomem *ioaddr = tp->mmio_addr;
 825         int i;
 826
 827         RTL_W8(ERIDR, cmd);
 828         RTL_W32(ERIAR, 0x800010e8);
 829         msleep(2);
 830         for (i = 0; i < 5; i++) {
 831                 udelay(100);
 832                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
 833                         break;
 834         }
 835
 836         ocp_write(tp, 0x1, 0x30, 0x00000001);
 837 }
 838
 839 #define OOB_CMD_RESET           0x00
 840 #define OOB_CMD_DRIVER_START    0x05
 841 #define OOB_CMD_DRIVER_STOP     0x06
 842
 843 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 844 {
 845         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 846 }
 847
 848 static void rtl8168_driver_start(struct rtl8169_private *tp)
 849 {
 850         u16 reg;
 851         int i;
 852
 853         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 854
 855         reg = rtl8168_get_ocp_reg(tp);
 856
 857         for (i = 0; i < 10; i++) {
 858                 msleep(10);
 859                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
 860                         break;
 861         }
 862 }
 863
 864 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 865 {
 866         u16 reg;
 867         int i;
 868
 869         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 870
 871         reg = rtl8168_get_ocp_reg(tp);
 872
 873         for (i = 0; i < 10; i++) {
 874                 msleep(10);
 875                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
 876                         break;
 877         }
 878 }
 879
 880 static int r8168dp_check_dash(struct rtl8169_private *tp)
 881 {
 882         u16 reg = rtl8168_get_ocp_reg(tp);
 883
 884         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 885 }
 886
 887 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 888 {
 889         int i;
 890
 891         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 892
 893         for (i = 20; i > 0; i--) {
 894                 /*
 895                  * Check if the RTL8169 has completed writing to the specified
 896                  * MII register.
 897                  */
 898                 if (!(RTL_R32(PHYAR) & 0x80000000))
 899                         break;
 900                 udelay(25);
 901         }
 902         /*
 903          * According to hardware specs a 20us delay is required after write
 904          * complete indication, but before sending next command.
 905          */
 906         udelay(20);
 907 }
 908
 909 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 910 {
 911         int i, value = -1;
 912
 913         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 914
 915         for (i = 20; i > 0; i--) {
 916                 /*
 917                  * Check if the RTL8169 has completed retrieving data from
 918                  * the specified MII register.
 919                  */
 920                 if (RTL_R32(PHYAR) & 0x80000000) {
 921                         value = RTL_R32(PHYAR) & 0xffff;
 922                         break;
 923                 }
 924                 udelay(25);
 925         }
 926         /*
 927          * According to hardware specs a 20us delay is required after read
 928          * complete indication, but before sending next command.
 929          */
 930         udelay(20);
 931
 932         return value;
 933 }
 934
 935 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 936 {
 937         int i;
 938
 939         RTL_W32(OCPDR, data |
 940                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 941         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 942         RTL_W32(EPHY_RXER_NUM, 0);
 943
 944         for (i = 0; i < 100; i++) {
 945                 mdelay(1);
 946                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 947                         break;
 948         }
 949 }
 950
 951 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 952 {
 953         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 954                 (value & OCPDR_DATA_MASK));
 955 }
 956
 957 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 958 {
 959         int i;
 960
 961         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 962
 963         mdelay(1);
 964         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 965         RTL_W32(EPHY_RXER_NUM, 0);
 966
 967         for (i = 0; i < 100; i++) {
 968                 mdelay(1);
 969                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 970                         break;
 971         }
 972
 973         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 974 }
 975
 976 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 977
 978 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
 979 {
 980         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 981 }
 982
 983 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
 984 {
 985         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 986 }
 987
 988 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 989 {
 990         r8168dp_2_mdio_start(ioaddr);
 991
 992         r8169_mdio_write(ioaddr, reg_addr, value);
 993
 994         r8168dp_2_mdio_stop(ioaddr);
 995 }
 996
 997 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
 998 {
 999         int value;
1000
1001         r8168dp_2_mdio_start(ioaddr);
1002
1003         value = r8169_mdio_read(ioaddr, reg_addr);
1004
1005         r8168dp_2_mdio_stop(ioaddr);
1006
1007         return value;
1008 }
1009
1010 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1011 {
1012         tp->mdio_ops.write(tp->mmio_addr, location, val);
1013 }
1014
1015 static int rtl_readphy(struct rtl8169_private *tp, int location)
1016 {
1017         return tp->mdio_ops.read(tp->mmio_addr, location);
1018 }
1019
1020 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1021 {
1022         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1023 }
1024
1025 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1026 {
1027         int val;
1028
1029         val = rtl_readphy(tp, reg_addr);
1030         rtl_writephy(tp, reg_addr, (val | p) & ~m);
1031 }
1032
1033 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1034                            int val)
1035 {
1036         struct rtl8169_private *tp = netdev_priv(dev);
1037
1038         rtl_writephy(tp, location, val);
1039 }
1040
1041 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1042 {
1043         struct rtl8169_private *tp = netdev_priv(dev);
1044
1045         return rtl_readphy(tp, location);
1046 }
1047
1048 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1049 {
1050         unsigned int i;
1051
1052         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1053                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1054
1055         for (i = 0; i < 100; i++) {
1056                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1057                         break;
1058                 udelay(10);
1059         }
1060 }
1061
1062 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1063 {
1064         u16 value = 0xffff;
1065         unsigned int i;
1066
1067         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1068
1069         for (i = 0; i < 100; i++) {
1070                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1071                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1072                         break;
1073                 }
1074                 udelay(10);
1075         }
1076
1077         return value;
1078 }
1079
1080 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1081 {
1082         unsigned int i;
1083
1084         RTL_W32(CSIDR, value);
1085         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1086                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1087
1088         for (i = 0; i < 100; i++) {
1089                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1090                         break;
1091                 udelay(10);
1092         }
1093 }
1094
1095 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1096 {
1097         u32 value = ~0x00;
1098         unsigned int i;
1099
1100         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1101                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1102
1103         for (i = 0; i < 100; i++) {
1104                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1105                         value = RTL_R32(CSIDR);
1106                         break;
1107                 }
1108                 udelay(10);
1109         }
1110
1111         return value;
1112 }
1113
1114 static
1115 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1116 {
1117         unsigned int i;
1118
1119         BUG_ON((addr & 3) || (mask == 0));
1120         RTL_W32(ERIDR, val);
1121         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1122
1123         for (i = 0; i < 100; i++) {
1124                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1125                         break;
1126                 udelay(100);
1127         }
1128 }
1129
1130 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1131 {
1132         u32 value = ~0x00;
1133         unsigned int i;
1134
1135         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1136
1137         for (i = 0; i < 100; i++) {
1138                 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1139                         value = RTL_R32(ERIDR);
1140                         break;
1141                 }
1142                 udelay(100);
1143         }
1144
1145         return value;
1146 }
1147
1148 static void
1149 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1150 {
1151         u32 val;
1152
1153         val = rtl_eri_read(ioaddr, addr, type);
1154         rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1155 }
1156
1157 struct exgmac_reg {
1158         u16 addr;
1159         u16 mask;
1160         u32 val;
1161 };
1162
1163 static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1164                                    const struct exgmac_reg *r, int len)
1165 {
1166         while (len-- > 0) {
1167                 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1168                 r++;
1169         }
1170 }
1171
1172 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1173 {
1174         u8 value = 0xff;
1175         unsigned int i;
1176
1177         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1178
1179         for (i = 0; i < 300; i++) {
1180                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1181                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1182                         break;
1183                 }
1184                 udelay(100);
1185         }
1186
1187         return value;
1188 }
1189
1190 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1191 {
1192         void __iomem *ioaddr = tp->mmio_addr;
1193
1194         RTL_W16(IntrMask, 0x0000);
1195         RTL_W16(IntrStatus, tp->intr_event);
1196         RTL_R8(ChipCmd);
1197 }
1198
1199 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1200 {
1201         void __iomem *ioaddr = tp->mmio_addr;
1202
1203         return RTL_R32(TBICSR) & TBIReset;
1204 }
1205
1206 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1207 {
1208         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1209 }
1210
1211 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1212 {
1213         return RTL_R32(TBICSR) & TBILinkOk;
1214 }
1215
1216 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1217 {
1218         return RTL_R8(PHYstatus) & LinkStatus;
1219 }
1220
1221 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1222 {
1223         void __iomem *ioaddr = tp->mmio_addr;
1224
1225         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1226 }
1227
1228 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1229 {
1230         unsigned int val;
1231
1232         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1233         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1234 }
1235
1236 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1237 {
1238         void __iomem *ioaddr = tp->mmio_addr;
1239         struct net_device *dev = tp->dev;
1240
1241         if (!netif_running(dev))
1242                 return;
1243
1244         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1245                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1246                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1247                                       0x00000011, ERIAR_EXGMAC);
1248                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1249                                       0x00000005, ERIAR_EXGMAC);
1250                 } else if (RTL_R8(PHYstatus) & _100bps) {
1251                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1252                                       0x0000001f, ERIAR_EXGMAC);
1253                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1254                                       0x00000005, ERIAR_EXGMAC);
1255                 } else {
1256                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1257                                       0x0000001f, ERIAR_EXGMAC);
1258                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1259                                       0x0000003f, ERIAR_EXGMAC);
1260                 }
1261                 /* Reset packet filter */
1262                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1263                              ERIAR_EXGMAC);
1264                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1265                              ERIAR_EXGMAC);
1266         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1267                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1268                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1269                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1270                                       0x00000011, ERIAR_EXGMAC);
1271                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1272                                       0x00000005, ERIAR_EXGMAC);
1273                 } else {
1274                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1275                                       0x0000001f, ERIAR_EXGMAC);
1276                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1277                                       0x0000003f, ERIAR_EXGMAC);
1278                 }
1279         }
1280 }
1281
1282 static void __rtl8169_check_link_status(struct net_device *dev,
1283                                         struct rtl8169_private *tp,
1284                                         void __iomem *ioaddr, bool pm)
1285 {
1286         unsigned long flags;
1287
1288         spin_lock_irqsave(&tp->lock, flags);
1289         if (tp->link_ok(ioaddr)) {
1290                 rtl_link_chg_patch(tp);
1291                 /* This is to cancel a scheduled suspend if there's one. */
1292                 if (pm)
1293                         pm_request_resume(&tp->pci_dev->dev);
1294                 netif_carrier_on(dev);
1295                 if (net_ratelimit())
1296                         netif_info(tp, ifup, dev, "link up\n");
1297         } else {
1298                 netif_carrier_off(dev);
1299                 netif_info(tp, ifdown, dev, "link down\n");
1300                 if (pm)
1301                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1302         }
1303         spin_unlock_irqrestore(&tp->lock, flags);
1304 }
1305
1306 static void rtl8169_check_link_status(struct net_device *dev,
1307                                       struct rtl8169_private *tp,
1308                                       void __iomem *ioaddr)
1309 {
1310         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1311 }
1312
1313 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1314
1315 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1316 {
1317         void __iomem *ioaddr = tp->mmio_addr;
1318         u8 options;
1319         u32 wolopts = 0;
1320
1321         options = RTL_R8(Config1);
1322         if (!(options & PMEnable))
1323                 return 0;
1324
1325         options = RTL_R8(Config3);
1326         if (options & LinkUp)
1327                 wolopts |= WAKE_PHY;
1328         if (options & MagicPacket)
1329                 wolopts |= WAKE_MAGIC;
1330
1331         options = RTL_R8(Config5);
1332         if (options & UWF)
1333                 wolopts |= WAKE_UCAST;
1334         if (options & BWF)
1335                 wolopts |= WAKE_BCAST;
1336         if (options & MWF)
1337                 wolopts |= WAKE_MCAST;
1338
1339         return wolopts;
1340 }
1341
1342 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1343 {
1344         struct rtl8169_private *tp = netdev_priv(dev);
1345
1346         spin_lock_irq(&tp->lock);
1347
1348         wol->supported = WAKE_ANY;
1349         wol->wolopts = __rtl8169_get_wol(tp);
1350
1351         spin_unlock_irq(&tp->lock);
1352 }
1353
1354 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1355 {
1356         void __iomem *ioaddr = tp->mmio_addr;
1357         unsigned int i;
1358         static const struct {
1359                 u32 opt;
1360                 u16 reg;
1361                 u8  mask;
1362         } cfg[] = {
1363                 { WAKE_ANY,   Config1, PMEnable },
1364                 { WAKE_PHY,   Config3, LinkUp },
1365                 { WAKE_MAGIC, Config3, MagicPacket },
1366                 { WAKE_UCAST, Config5, UWF },
1367                 { WAKE_BCAST, Config5, BWF },
1368                 { WAKE_MCAST, Config5, MWF },
1369                 { WAKE_ANY,   Config5, LanWake }
1370         };
1371
1372         RTL_W8(Cfg9346, Cfg9346_Unlock);
1373
1374         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1375                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1376                 if (wolopts & cfg[i].opt)
1377                         options |= cfg[i].mask;
1378                 RTL_W8(cfg[i].reg, options);
1379         }
1380
1381         RTL_W8(Cfg9346, Cfg9346_Lock);
1382 }
1383
1384 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1385 {
1386         struct rtl8169_private *tp = netdev_priv(dev);
1387
1388         spin_lock_irq(&tp->lock);
1389
1390         if (wol->wolopts)
1391                 tp->features |= RTL_FEATURE_WOL;
1392         else
1393                 tp->features &= ~RTL_FEATURE_WOL;
1394         __rtl8169_set_wol(tp, wol->wolopts);
1395         spin_unlock_irq(&tp->lock);
1396
1397         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1398
1399         return 0;
1400 }
1401
1402 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1403 {
1404         return rtl_chip_infos[tp->mac_version].fw_name;
1405 }
1406
1407 static void rtl8169_get_drvinfo(struct net_device *dev,
1408                                 struct ethtool_drvinfo *info)
1409 {
1410         struct rtl8169_private *tp = netdev_priv(dev);
1411         struct rtl_fw *rtl_fw = tp->rtl_fw;
1412
1413         strcpy(info->driver, MODULENAME);
1414         strcpy(info->version, RTL8169_VERSION);
1415         strcpy(info->bus_info, pci_name(tp->pci_dev));
1416         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1417         strcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" :
1418                rtl_fw->version);
1419 }
1420
1421 static int rtl8169_get_regs_len(struct net_device *dev)
1422 {
1423         return R8169_REGS_SIZE;
1424 }
1425
1426 static int rtl8169_set_speed_tbi(struct net_device *dev,
1427                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1428 {
1429         struct rtl8169_private *tp = netdev_priv(dev);
1430         void __iomem *ioaddr = tp->mmio_addr;
1431         int ret = 0;
1432         u32 reg;
1433
1434         reg = RTL_R32(TBICSR);
1435         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1436             (duplex == DUPLEX_FULL)) {
1437                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1438         } else if (autoneg == AUTONEG_ENABLE)
1439                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1440         else {
1441                 netif_warn(tp, link, dev,
1442                            "incorrect speed setting refused in TBI mode\n");
1443                 ret = -EOPNOTSUPP;
1444         }
1445
1446         return ret;
1447 }
1448
1449 static int rtl8169_set_speed_xmii(struct net_device *dev,
1450                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1451 {
1452         struct rtl8169_private *tp = netdev_priv(dev);
1453         int giga_ctrl, bmcr;
1454         int rc = -EINVAL;
1455
1456         rtl_writephy(tp, 0x1f, 0x0000);
1457
1458         if (autoneg == AUTONEG_ENABLE) {
1459                 int auto_nego;
1460
1461                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1462                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1463                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1464
1465                 if (adv & ADVERTISED_10baseT_Half)
1466                         auto_nego |= ADVERTISE_10HALF;
1467                 if (adv & ADVERTISED_10baseT_Full)
1468                         auto_nego |= ADVERTISE_10FULL;
1469                 if (adv & ADVERTISED_100baseT_Half)
1470                         auto_nego |= ADVERTISE_100HALF;
1471                 if (adv & ADVERTISED_100baseT_Full)
1472                         auto_nego |= ADVERTISE_100FULL;
1473
1474                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1475
1476                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1477                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1478
1479                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1480                 if (tp->mii.supports_gmii) {
1481                         if (adv & ADVERTISED_1000baseT_Half)
1482                                 giga_ctrl |= ADVERTISE_1000HALF;
1483                         if (adv & ADVERTISED_1000baseT_Full)
1484                                 giga_ctrl |= ADVERTISE_1000FULL;
1485                 } else if (adv & (ADVERTISED_1000baseT_Half |
1486                                   ADVERTISED_1000baseT_Full)) {
1487                         netif_info(tp, link, dev,
1488                                    "PHY does not support 1000Mbps\n");
1489                         goto out;
1490                 }
1491
1492                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1493
1494                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1495                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1496         } else {
1497                 giga_ctrl = 0;
1498
1499                 if (speed == SPEED_10)
1500                         bmcr = 0;
1501                 else if (speed == SPEED_100)
1502                         bmcr = BMCR_SPEED100;
1503                 else
1504                         goto out;
1505
1506                 if (duplex == DUPLEX_FULL)
1507                         bmcr |= BMCR_FULLDPLX;
1508         }
1509
1510         rtl_writephy(tp, MII_BMCR, bmcr);
1511
1512         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1513             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1514                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1515                         rtl_writephy(tp, 0x17, 0x2138);
1516                         rtl_writephy(tp, 0x0e, 0x0260);
1517                 } else {
1518                         rtl_writephy(tp, 0x17, 0x2108);
1519                         rtl_writephy(tp, 0x0e, 0x0000);
1520                 }
1521         }
1522
1523         rc = 0;
1524 out:
1525         return rc;
1526 }
1527
1528 static int rtl8169_set_speed(struct net_device *dev,
1529                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1530 {
1531         struct rtl8169_private *tp = netdev_priv(dev);
1532         int ret;
1533
1534         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1535         if (ret < 0)
1536                 goto out;
1537
1538         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1539             (advertising & ADVERTISED_1000baseT_Full)) {
1540                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1541         }
1542 out:
1543         return ret;
1544 }
1545
1546 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1547 {
1548         struct rtl8169_private *tp = netdev_priv(dev);
1549         unsigned long flags;
1550         int ret;
1551
1552         del_timer_sync(&tp->timer);
1553
1554         spin_lock_irqsave(&tp->lock, flags);
1555         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1556                                 cmd->duplex, cmd->advertising);
1557         spin_unlock_irqrestore(&tp->lock, flags);
1558
1559         return ret;
1560 }
1561
1562 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1563 {
1564         struct rtl8169_private *tp = netdev_priv(dev);
1565
1566         if (dev->mtu > TD_MSS_MAX)
1567                 features &= ~NETIF_F_ALL_TSO;
1568
1569         if (dev->mtu > JUMBO_1K &&
1570             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1571                 features &= ~NETIF_F_IP_CSUM;
1572
1573         return features;
1574 }
1575
1576 static int rtl8169_set_features(struct net_device *dev, u32 features)
1577 {
1578         struct rtl8169_private *tp = netdev_priv(dev);
1579         void __iomem *ioaddr = tp->mmio_addr;
1580         unsigned long flags;
1581
1582         spin_lock_irqsave(&tp->lock, flags);
1583
1584         if (features & NETIF_F_RXCSUM)
1585                 tp->cp_cmd |= RxChkSum;
1586         else
1587                 tp->cp_cmd &= ~RxChkSum;
1588
1589         if (dev->features & NETIF_F_HW_VLAN_RX)
1590                 tp->cp_cmd |= RxVlan;
1591         else
1592                 tp->cp_cmd &= ~RxVlan;
1593
1594         RTL_W16(CPlusCmd, tp->cp_cmd);
1595         RTL_R16(CPlusCmd);
1596
1597         spin_unlock_irqrestore(&tp->lock, flags);
1598
1599         return 0;
1600 }
1601
1602 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1603                                       struct sk_buff *skb)
1604 {
1605         return (vlan_tx_tag_present(skb)) ?
1606                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1607 }
1608
1609 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1610 {
1611         u32 opts2 = le32_to_cpu(desc->opts2);
1612
1613         if (opts2 & RxVlanTag)
1614                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1615
1616         desc->opts2 = 0;
1617 }
1618
1619 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1620 {
1621         struct rtl8169_private *tp = netdev_priv(dev);
1622         void __iomem *ioaddr = tp->mmio_addr;
1623         u32 status;
1624
1625         cmd->supported =
1626                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1627         cmd->port = PORT_FIBRE;
1628         cmd->transceiver = XCVR_INTERNAL;
1629
1630         status = RTL_R32(TBICSR);
1631         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1632         cmd->autoneg = !!(status & TBINwEnable);
1633
1634         ethtool_cmd_speed_set(cmd, SPEED_1000);
1635         cmd->duplex = DUPLEX_FULL; /* Always set */
1636
1637         return 0;
1638 }
1639
1640 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1641 {
1642         struct rtl8169_private *tp = netdev_priv(dev);
1643
1644         return mii_ethtool_gset(&tp->mii, cmd);
1645 }
1646
1647 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1648 {
1649         struct rtl8169_private *tp = netdev_priv(dev);
1650         unsigned long flags;
1651         int rc;
1652
1653         spin_lock_irqsave(&tp->lock, flags);
1654
1655         rc = tp->get_settings(dev, cmd);
1656
1657         spin_unlock_irqrestore(&tp->lock, flags);
1658         return rc;
1659 }
1660
1661 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1662                              void *p)
1663 {
1664         struct rtl8169_private *tp = netdev_priv(dev);
1665         unsigned long flags;
1666
1667         if (regs->len > R8169_REGS_SIZE)
1668                 regs->len = R8169_REGS_SIZE;
1669
1670         spin_lock_irqsave(&tp->lock, flags);
1671         memcpy_fromio(p, tp->mmio_addr, regs->len);
1672         spin_unlock_irqrestore(&tp->lock, flags);
1673 }
1674
1675 static u32 rtl8169_get_msglevel(struct net_device *dev)
1676 {
1677         struct rtl8169_private *tp = netdev_priv(dev);
1678
1679         return tp->msg_enable;
1680 }
1681
1682 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1683 {
1684         struct rtl8169_private *tp = netdev_priv(dev);
1685
1686         tp->msg_enable = value;
1687 }
1688
1689 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1690         "tx_packets",
1691         "rx_packets",
1692         "tx_errors",
1693         "rx_errors",
1694         "rx_missed",
1695         "align_errors",
1696         "tx_single_collisions",
1697         "tx_multi_collisions",
1698         "unicast",
1699         "broadcast",
1700         "multicast",
1701         "tx_aborted",
1702         "tx_underrun",
1703 };
1704
1705 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1706 {
1707         switch (sset) {
1708         case ETH_SS_STATS:
1709                 return ARRAY_SIZE(rtl8169_gstrings);
1710         default:
1711                 return -EOPNOTSUPP;
1712         }
1713 }
1714
1715 static void rtl8169_update_counters(struct net_device *dev)
1716 {
1717         struct rtl8169_private *tp = netdev_priv(dev);
1718         void __iomem *ioaddr = tp->mmio_addr;
1719         struct device *d = &tp->pci_dev->dev;
1720         struct rtl8169_counters *counters;
1721         dma_addr_t paddr;
1722         u32 cmd;
1723         int wait = 1000;
1724
1725         /*
1726          * Some chips are unable to dump tally counters when the receiver
1727          * is disabled.
1728          */
1729         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1730                 return;
1731
1732         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1733         if (!counters)
1734                 return;
1735
1736         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1737         cmd = (u64)paddr & DMA_BIT_MASK(32);
1738         RTL_W32(CounterAddrLow, cmd);
1739         RTL_W32(CounterAddrLow, cmd | CounterDump);
1740
1741         while (wait--) {
1742                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1743                         memcpy(&tp->counters, counters, sizeof(*counters));
1744                         break;
1745                 }
1746                 udelay(10);
1747         }
1748
1749         RTL_W32(CounterAddrLow, 0);
1750         RTL_W32(CounterAddrHigh, 0);
1751
1752         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1753 }
1754
1755 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1756                                       struct ethtool_stats *stats, u64 *data)
1757 {
1758         struct rtl8169_private *tp = netdev_priv(dev);
1759
1760         ASSERT_RTNL();
1761
1762         rtl8169_update_counters(dev);
1763
1764         data[0] = le64_to_cpu(tp->counters.tx_packets);
1765         data[1] = le64_to_cpu(tp->counters.rx_packets);
1766         data[2] = le64_to_cpu(tp->counters.tx_errors);
1767         data[3] = le32_to_cpu(tp->counters.rx_errors);
1768         data[4] = le16_to_cpu(tp->counters.rx_missed);
1769         data[5] = le16_to_cpu(tp->counters.align_errors);
1770         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1771         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1772         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1773         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1774         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1775         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1776         data[12] = le16_to_cpu(tp->counters.tx_underun);
1777 }
1778
1779 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1780 {
1781         switch(stringset) {
1782         case ETH_SS_STATS:
1783                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1784                 break;
1785         }
1786 }
1787
1788 static const struct ethtool_ops rtl8169_ethtool_ops = {
1789         .get_drvinfo            = rtl8169_get_drvinfo,
1790         .get_regs_len           = rtl8169_get_regs_len,
1791         .get_link               = ethtool_op_get_link,
1792         .get_settings           = rtl8169_get_settings,
1793         .set_settings           = rtl8169_set_settings,
1794         .get_msglevel           = rtl8169_get_msglevel,
1795         .set_msglevel           = rtl8169_set_msglevel,
1796         .get_regs               = rtl8169_get_regs,
1797         .get_wol                = rtl8169_get_wol,
1798         .set_wol                = rtl8169_set_wol,
1799         .get_strings            = rtl8169_get_strings,
1800         .get_sset_count         = rtl8169_get_sset_count,
1801         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1802 };
1803
1804 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1805                                     struct net_device *dev, u8 default_version)
1806 {
1807         void __iomem *ioaddr = tp->mmio_addr;
1808         /*
1809          * The driver currently handles the 8168Bf and the 8168Be identically
1810          * but they can be identified more specifically through the test below
1811          * if needed:
1812          *
1813          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1814          *
1815          * Same thing for the 8101Eb and the 8101Ec:
1816          *
1817          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1818          */
1819         static const struct rtl_mac_info {
1820                 u32 mask;
1821                 u32 val;
1822                 int mac_version;
1823         } mac_info[] = {
1824                 /* 8168F family. */
1825                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
1826                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
1827
1828                 /* 8168E family. */
1829                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
1830                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1831                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1832                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1833
1834                 /* 8168D family. */
1835                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1836                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1837                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1838
1839                 /* 8168DP family. */
1840                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1841                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1842                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1843
1844                 /* 8168C family. */
1845                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1846                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1847                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1848                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1849                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1850                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1851                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1852                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1853                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1854
1855                 /* 8168B family. */
1856                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1857                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1858                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1859                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1860
1861                 /* 8101 family. */
1862                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1863                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1864                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1865                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1866                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1867                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1868                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1869                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1870                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1871                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1872                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1873                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1874                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1875                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1876                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1877                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1878                 /* FIXME: where did these entries come from ? -- FR */
1879                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1880                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1881
1882                 /* 8110 family. */
1883                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1884                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1885                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1886                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1887                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1888                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1889
1890                 /* Catch-all */
1891                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1892         };
1893         const struct rtl_mac_info *p = mac_info;
1894         u32 reg;
1895
1896         reg = RTL_R32(TxConfig);
1897         while ((reg & p->mask) != p->val)
1898                 p++;
1899         tp->mac_version = p->mac_version;
1900
1901         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1902                 netif_notice(tp, probe, dev,
1903                              "unknown MAC, using family default\n");
1904                 tp->mac_version = default_version;
1905         }
1906 }
1907
1908 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1909 {
1910         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1911 }
1912
1913 struct phy_reg {
1914         u16 reg;
1915         u16 val;
1916 };
1917
1918 static void rtl_writephy_batch(struct rtl8169_private *tp,
1919                                const struct phy_reg *regs, int len)
1920 {
1921         while (len-- > 0) {
1922                 rtl_writephy(tp, regs->reg, regs->val);
1923                 regs++;
1924         }
1925 }
1926
1927 #define PHY_READ                0x00000000
1928 #define PHY_DATA_OR             0x10000000
1929 #define PHY_DATA_AND            0x20000000
1930 #define PHY_BJMPN               0x30000000
1931 #define PHY_READ_EFUSE          0x40000000
1932 #define PHY_READ_MAC_BYTE       0x50000000
1933 #define PHY_WRITE_MAC_BYTE      0x60000000
1934 #define PHY_CLEAR_READCOUNT     0x70000000
1935 #define PHY_WRITE               0x80000000
1936 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1937 #define PHY_COMP_EQ_SKIPN       0xa0000000
1938 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1939 #define PHY_WRITE_PREVIOUS      0xc0000000
1940 #define PHY_SKIPN               0xd0000000
1941 #define PHY_DELAY_MS            0xe0000000
1942 #define PHY_WRITE_ERI_WORD      0xf0000000
1943
1944 struct fw_info {
1945         u32     magic;
1946         char    version[RTL_VER_SIZE];
1947         __le32  fw_start;
1948         __le32  fw_len;
1949         u8      chksum;
1950 } __packed;
1951
1952 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1953
1954 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1955 {
1956         const struct firmware *fw = rtl_fw->fw;
1957         struct fw_info *fw_info = (struct fw_info *)fw->data;
1958         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1959         char *version = rtl_fw->version;
1960         bool rc = false;
1961
1962         if (fw->size < FW_OPCODE_SIZE)
1963                 goto out;
1964
1965         if (!fw_info->magic) {
1966                 size_t i, size, start;
1967                 u8 checksum = 0;
1968
1969                 if (fw->size < sizeof(*fw_info))
1970                         goto out;
1971
1972                 for (i = 0; i < fw->size; i++)
1973                         checksum += fw->data[i];
1974                 if (checksum != 0)
1975                         goto out;
1976
1977                 start = le32_to_cpu(fw_info->fw_start);
1978                 if (start > fw->size)
1979                         goto out;
1980
1981                 size = le32_to_cpu(fw_info->fw_len);
1982                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
1983                         goto out;
1984
1985                 memcpy(version, fw_info->version, RTL_VER_SIZE);
1986
1987                 pa->code = (__le32 *)(fw->data + start);
1988                 pa->size = size;
1989         } else {
1990                 if (fw->size % FW_OPCODE_SIZE)
1991                         goto out;
1992
1993                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
1994
1995                 pa->code = (__le32 *)fw->data;
1996                 pa->size = fw->size / FW_OPCODE_SIZE;
1997         }
1998         version[RTL_VER_SIZE - 1] = 0;
1999
2000         rc = true;
2001 out:
2002         return rc;
2003 }
2004
2005 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2006                            struct rtl_fw_phy_action *pa)
2007 {
2008         bool rc = false;
2009         size_t index;
2010
2011         for (index = 0; index < pa->size; index++) {
2012                 u32 action = le32_to_cpu(pa->code[index]);
2013                 u32 regno = (action & 0x0fff0000) >> 16;
2014
2015                 switch(action & 0xf0000000) {
2016                 case PHY_READ:
2017                 case PHY_DATA_OR:
2018                 case PHY_DATA_AND:
2019                 case PHY_READ_EFUSE:
2020                 case PHY_CLEAR_READCOUNT:
2021                 case PHY_WRITE:
2022                 case PHY_WRITE_PREVIOUS:
2023                 case PHY_DELAY_MS:
2024                         break;
2025
2026                 case PHY_BJMPN:
2027                         if (regno > index) {
2028                                 netif_err(tp, ifup, tp->dev,
2029                                           "Out of range of firmware\n");
2030                                 goto out;
2031                         }
2032                         break;
2033                 case PHY_READCOUNT_EQ_SKIP:
2034                         if (index + 2 >= pa->size) {
2035                                 netif_err(tp, ifup, tp->dev,
2036                                           "Out of range of firmware\n");
2037                                 goto out;
2038                         }
2039                         break;
2040                 case PHY_COMP_EQ_SKIPN:
2041                 case PHY_COMP_NEQ_SKIPN:
2042                 case PHY_SKIPN:
2043                         if (index + 1 + regno >= pa->size) {
2044                                 netif_err(tp, ifup, tp->dev,
2045                                           "Out of range of firmware\n");
2046                                 goto out;
2047                         }
2048                         break;
2049
2050                 case PHY_READ_MAC_BYTE:
2051                 case PHY_WRITE_MAC_BYTE:
2052                 case PHY_WRITE_ERI_WORD:
2053                 default:
2054                         netif_err(tp, ifup, tp->dev,
2055                                   "Invalid action 0x%08x\n", action);
2056                         goto out;
2057                 }
2058         }
2059         rc = true;
2060 out:
2061         return rc;
2062 }
2063
2064 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2065 {
2066         struct net_device *dev = tp->dev;
2067         int rc = -EINVAL;
2068
2069         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2070                 netif_err(tp, ifup, dev, "invalid firwmare\n");
2071                 goto out;
2072         }
2073
2074         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2075                 rc = 0;
2076 out:
2077         return rc;
2078 }
2079
2080 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2081 {
2082         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2083         u32 predata, count;
2084         size_t index;
2085
2086         predata = count = 0;
2087
2088         for (index = 0; index < pa->size; ) {
2089                 u32 action = le32_to_cpu(pa->code[index]);
2090                 u32 data = action & 0x0000ffff;
2091                 u32 regno = (action & 0x0fff0000) >> 16;
2092
2093                 if (!action)
2094                         break;
2095
2096                 switch(action & 0xf0000000) {
2097                 case PHY_READ:
2098                         predata = rtl_readphy(tp, regno);
2099                         count++;
2100                         index++;
2101                         break;
2102                 case PHY_DATA_OR:
2103                         predata |= data;
2104                         index++;
2105                         break;
2106                 case PHY_DATA_AND:
2107                         predata &= data;
2108                         index++;
2109                         break;
2110                 case PHY_BJMPN:
2111                         index -= regno;
2112                         break;
2113                 case PHY_READ_EFUSE:
2114                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2115                         index++;
2116                         break;
2117                 case PHY_CLEAR_READCOUNT:
2118                         count = 0;
2119                         index++;
2120                         break;
2121                 case PHY_WRITE:
2122                         rtl_writephy(tp, regno, data);
2123                         index++;
2124                         break;
2125                 case PHY_READCOUNT_EQ_SKIP:
2126                         index += (count == data) ? 2 : 1;
2127                         break;
2128                 case PHY_COMP_EQ_SKIPN:
2129                         if (predata == data)
2130                                 index += regno;
2131                         index++;
2132                         break;
2133                 case PHY_COMP_NEQ_SKIPN:
2134                         if (predata != data)
2135                                 index += regno;
2136                         index++;
2137                         break;
2138                 case PHY_WRITE_PREVIOUS:
2139                         rtl_writephy(tp, regno, predata);
2140                         index++;
2141                         break;
2142                 case PHY_SKIPN:
2143                         index += regno + 1;
2144                         break;
2145                 case PHY_DELAY_MS:
2146                         mdelay(data);
2147                         index++;
2148                         break;
2149
2150                 case PHY_READ_MAC_BYTE:
2151                 case PHY_WRITE_MAC_BYTE:
2152                 case PHY_WRITE_ERI_WORD:
2153                 default:
2154                         BUG();
2155                 }
2156         }
2157 }
2158
2159 static void rtl_release_firmware(struct rtl8169_private *tp)
2160 {
2161         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2162                 release_firmware(tp->rtl_fw->fw);
2163                 kfree(tp->rtl_fw);
2164         }
2165         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2166 }
2167
2168 static void rtl_apply_firmware(struct rtl8169_private *tp)
2169 {
2170         struct rtl_fw *rtl_fw = tp->rtl_fw;
2171
2172         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2173         if (!IS_ERR_OR_NULL(rtl_fw))
2174                 rtl_phy_write_fw(tp, rtl_fw);
2175 }
2176
2177 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2178 {
2179         if (rtl_readphy(tp, reg) != val)
2180                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2181         else
2182                 rtl_apply_firmware(tp);
2183 }
2184
2185 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2186 {
2187         static const struct phy_reg phy_reg_init[] = {
2188                 { 0x1f, 0x0001 },
2189                 { 0x06, 0x006e },
2190                 { 0x08, 0x0708 },
2191                 { 0x15, 0x4000 },
2192                 { 0x18, 0x65c7 },
2193
2194                 { 0x1f, 0x0001 },
2195                 { 0x03, 0x00a1 },
2196                 { 0x02, 0x0008 },
2197                 { 0x01, 0x0120 },
2198                 { 0x00, 0x1000 },
2199                 { 0x04, 0x0800 },
2200                 { 0x04, 0x0000 },
2201
2202                 { 0x03, 0xff41 },
2203                 { 0x02, 0xdf60 },
2204                 { 0x01, 0x0140 },
2205                 { 0x00, 0x0077 },
2206                 { 0x04, 0x7800 },
2207                 { 0x04, 0x7000 },
2208
2209                 { 0x03, 0x802f },
2210                 { 0x02, 0x4f02 },
2211                 { 0x01, 0x0409 },
2212                 { 0x00, 0xf0f9 },
2213                 { 0x04, 0x9800 },
2214                 { 0x04, 0x9000 },
2215
2216                 { 0x03, 0xdf01 },
2217                 { 0x02, 0xdf20 },
2218                 { 0x01, 0xff95 },
2219                 { 0x00, 0xba00 },
2220                 { 0x04, 0xa800 },
2221                 { 0x04, 0xa000 },
2222
2223                 { 0x03, 0xff41 },
2224                 { 0x02, 0xdf20 },
2225                 { 0x01, 0x0140 },
2226                 { 0x00, 0x00bb },
2227                 { 0x04, 0xb800 },
2228                 { 0x04, 0xb000 },
2229
2230                 { 0x03, 0xdf41 },
2231                 { 0x02, 0xdc60 },
2232                 { 0x01, 0x6340 },
2233                 { 0x00, 0x007d },
2234                 { 0x04, 0xd800 },
2235                 { 0x04, 0xd000 },
2236
2237                 { 0x03, 0xdf01 },
2238                 { 0x02, 0xdf20 },
2239                 { 0x01, 0x100a },
2240                 { 0x00, 0xa0ff },
2241                 { 0x04, 0xf800 },
2242                 { 0x04, 0xf000 },
2243
2244                 { 0x1f, 0x0000 },
2245                 { 0x0b, 0x0000 },
2246                 { 0x00, 0x9200 }
2247         };
2248
2249         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2250 }
2251
2252 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2253 {
2254         static const struct phy_reg phy_reg_init[] = {
2255                 { 0x1f, 0x0002 },
2256                 { 0x01, 0x90d0 },
2257                 { 0x1f, 0x0000 }
2258         };
2259
2260         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2261 }
2262
2263 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2264 {
2265         struct pci_dev *pdev = tp->pci_dev;
2266
2267         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2268             (pdev->subsystem_device != 0xe000))
2269                 return;
2270
2271         rtl_writephy(tp, 0x1f, 0x0001);
2272         rtl_writephy(tp, 0x10, 0xf01b);
2273         rtl_writephy(tp, 0x1f, 0x0000);
2274 }
2275
2276 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2277 {
2278         static const struct phy_reg phy_reg_init[] = {
2279                 { 0x1f, 0x0001 },
2280                 { 0x04, 0x0000 },
2281                 { 0x03, 0x00a1 },
2282                 { 0x02, 0x0008 },
2283                 { 0x01, 0x0120 },
2284                 { 0x00, 0x1000 },
2285                 { 0x04, 0x0800 },
2286                 { 0x04, 0x9000 },
2287                 { 0x03, 0x802f },
2288                 { 0x02, 0x4f02 },
2289                 { 0x01, 0x0409 },
2290                 { 0x00, 0xf099 },
2291                 { 0x04, 0x9800 },
2292                 { 0x04, 0xa000 },
2293                 { 0x03, 0xdf01 },
2294                 { 0x02, 0xdf20 },
2295                 { 0x01, 0xff95 },
2296                 { 0x00, 0xba00 },
2297                 { 0x04, 0xa800 },
2298                 { 0x04, 0xf000 },
2299                 { 0x03, 0xdf01 },
2300                 { 0x02, 0xdf20 },
2301                 { 0x01, 0x101a },
2302                 { 0x00, 0xa0ff },
2303                 { 0x04, 0xf800 },
2304                 { 0x04, 0x0000 },
2305                 { 0x1f, 0x0000 },
2306
2307                 { 0x1f, 0x0001 },
2308                 { 0x10, 0xf41b },
2309                 { 0x14, 0xfb54 },
2310                 { 0x18, 0xf5c7 },
2311                 { 0x1f, 0x0000 },
2312
2313                 { 0x1f, 0x0001 },
2314                 { 0x17, 0x0cc0 },
2315                 { 0x1f, 0x0000 }
2316         };
2317
2318         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2319
2320         rtl8169scd_hw_phy_config_quirk(tp);
2321 }
2322
2323 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2324 {
2325         static const struct phy_reg phy_reg_init[] = {
2326                 { 0x1f, 0x0001 },
2327                 { 0x04, 0x0000 },
2328                 { 0x03, 0x00a1 },
2329                 { 0x02, 0x0008 },
2330                 { 0x01, 0x0120 },
2331                 { 0x00, 0x1000 },
2332                 { 0x04, 0x0800 },
2333                 { 0x04, 0x9000 },
2334                 { 0x03, 0x802f },
2335                 { 0x02, 0x4f02 },
2336                 { 0x01, 0x0409 },
2337                 { 0x00, 0xf099 },
2338                 { 0x04, 0x9800 },
2339                 { 0x04, 0xa000 },
2340                 { 0x03, 0xdf01 },
2341                 { 0x02, 0xdf20 },
2342                 { 0x01, 0xff95 },
2343                 { 0x00, 0xba00 },
2344                 { 0x04, 0xa800 },
2345                 { 0x04, 0xf000 },
2346                 { 0x03, 0xdf01 },
2347                 { 0x02, 0xdf20 },
2348                 { 0x01, 0x101a },
2349                 { 0x00, 0xa0ff },
2350                 { 0x04, 0xf800 },
2351                 { 0x04, 0x0000 },
2352                 { 0x1f, 0x0000 },
2353
2354                 { 0x1f, 0x0001 },
2355                 { 0x0b, 0x8480 },
2356                 { 0x1f, 0x0000 },
2357
2358                 { 0x1f, 0x0001 },
2359                 { 0x18, 0x67c7 },
2360                 { 0x04, 0x2000 },
2361                 { 0x03, 0x002f },
2362                 { 0x02, 0x4360 },
2363                 { 0x01, 0x0109 },
2364                 { 0x00, 0x3022 },
2365                 { 0x04, 0x2800 },
2366                 { 0x1f, 0x0000 },
2367
2368                 { 0x1f, 0x0001 },
2369                 { 0x17, 0x0cc0 },
2370                 { 0x1f, 0x0000 }
2371         };
2372
2373         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2374 }
2375
2376 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2377 {
2378         static const struct phy_reg phy_reg_init[] = {
2379                 { 0x10, 0xf41b },
2380                 { 0x1f, 0x0000 }
2381         };
2382
2383         rtl_writephy(tp, 0x1f, 0x0001);
2384         rtl_patchphy(tp, 0x16, 1 << 0);
2385
2386         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2387 }
2388
2389 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2390 {
2391         static const struct phy_reg phy_reg_init[] = {
2392                 { 0x1f, 0x0001 },
2393                 { 0x10, 0xf41b },
2394                 { 0x1f, 0x0000 }
2395         };
2396
2397         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2398 }
2399
2400 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2401 {
2402         static const struct phy_reg phy_reg_init[] = {
2403                 { 0x1f, 0x0000 },
2404                 { 0x1d, 0x0f00 },
2405                 { 0x1f, 0x0002 },
2406                 { 0x0c, 0x1ec8 },
2407                 { 0x1f, 0x0000 }
2408         };
2409
2410         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2411 }
2412
2413 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2414 {
2415         static const struct phy_reg phy_reg_init[] = {
2416                 { 0x1f, 0x0001 },
2417                 { 0x1d, 0x3d98 },
2418                 { 0x1f, 0x0000 }
2419         };
2420
2421         rtl_writephy(tp, 0x1f, 0x0000);
2422         rtl_patchphy(tp, 0x14, 1 << 5);
2423         rtl_patchphy(tp, 0x0d, 1 << 5);
2424
2425         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2426 }
2427
2428 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2429 {
2430         static const struct phy_reg phy_reg_init[] = {
2431                 { 0x1f, 0x0001 },
2432                 { 0x12, 0x2300 },
2433                 { 0x1f, 0x0002 },
2434                 { 0x00, 0x88d4 },
2435                 { 0x01, 0x82b1 },
2436                 { 0x03, 0x7002 },
2437                 { 0x08, 0x9e30 },
2438                 { 0x09, 0x01f0 },
2439                 { 0x0a, 0x5500 },
2440                 { 0x0c, 0x00c8 },
2441                 { 0x1f, 0x0003 },
2442                 { 0x12, 0xc096 },
2443                 { 0x16, 0x000a },
2444                 { 0x1f, 0x0000 },
2445                 { 0x1f, 0x0000 },
2446                 { 0x09, 0x2000 },
2447                 { 0x09, 0x0000 }
2448         };
2449
2450         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2451
2452         rtl_patchphy(tp, 0x14, 1 << 5);
2453         rtl_patchphy(tp, 0x0d, 1 << 5);
2454         rtl_writephy(tp, 0x1f, 0x0000);
2455 }
2456
2457 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2458 {
2459         static const struct phy_reg phy_reg_init[] = {
2460                 { 0x1f, 0x0001 },
2461                 { 0x12, 0x2300 },
2462                 { 0x03, 0x802f },
2463                 { 0x02, 0x4f02 },
2464                 { 0x01, 0x0409 },
2465                 { 0x00, 0xf099 },
2466                 { 0x04, 0x9800 },
2467                 { 0x04, 0x9000 },
2468                 { 0x1d, 0x3d98 },
2469                 { 0x1f, 0x0002 },
2470                 { 0x0c, 0x7eb8 },
2471                 { 0x06, 0x0761 },
2472                 { 0x1f, 0x0003 },
2473                 { 0x16, 0x0f0a },
2474                 { 0x1f, 0x0000 }
2475         };
2476
2477         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2478
2479         rtl_patchphy(tp, 0x16, 1 << 0);
2480         rtl_patchphy(tp, 0x14, 1 << 5);
2481         rtl_patchphy(tp, 0x0d, 1 << 5);
2482         rtl_writephy(tp, 0x1f, 0x0000);
2483 }
2484
2485 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2486 {
2487         static const struct phy_reg phy_reg_init[] = {
2488                 { 0x1f, 0x0001 },
2489                 { 0x12, 0x2300 },
2490                 { 0x1d, 0x3d98 },
2491                 { 0x1f, 0x0002 },
2492                 { 0x0c, 0x7eb8 },
2493                 { 0x06, 0x5461 },
2494                 { 0x1f, 0x0003 },
2495                 { 0x16, 0x0f0a },
2496                 { 0x1f, 0x0000 }
2497         };
2498
2499         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2500
2501         rtl_patchphy(tp, 0x16, 1 << 0);
2502         rtl_patchphy(tp, 0x14, 1 << 5);
2503         rtl_patchphy(tp, 0x0d, 1 << 5);
2504         rtl_writephy(tp, 0x1f, 0x0000);
2505 }
2506
2507 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2508 {
2509         rtl8168c_3_hw_phy_config(tp);
2510 }
2511
2512 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2513 {
2514         static const struct phy_reg phy_reg_init_0[] = {
2515                 /* Channel Estimation */
2516                 { 0x1f, 0x0001 },
2517                 { 0x06, 0x4064 },
2518                 { 0x07, 0x2863 },
2519                 { 0x08, 0x059c },
2520                 { 0x09, 0x26b4 },
2521                 { 0x0a, 0x6a19 },
2522                 { 0x0b, 0xdcc8 },
2523                 { 0x10, 0xf06d },
2524                 { 0x14, 0x7f68 },
2525                 { 0x18, 0x7fd9 },
2526                 { 0x1c, 0xf0ff },
2527                 { 0x1d, 0x3d9c },
2528                 { 0x1f, 0x0003 },
2529                 { 0x12, 0xf49f },
2530                 { 0x13, 0x070b },
2531                 { 0x1a, 0x05ad },
2532                 { 0x14, 0x94c0 },
2533
2534                 /*
2535                  * Tx Error Issue
2536                  * Enhance line driver power
2537                  */
2538                 { 0x1f, 0x0002 },
2539                 { 0x06, 0x5561 },
2540                 { 0x1f, 0x0005 },
2541                 { 0x05, 0x8332 },
2542                 { 0x06, 0x5561 },
2543
2544                 /*
2545                  * Can not link to 1Gbps with bad cable
2546                  * Decrease SNR threshold form 21.07dB to 19.04dB
2547                  */
2548                 { 0x1f, 0x0001 },
2549                 { 0x17, 0x0cc0 },
2550
2551                 { 0x1f, 0x0000 },
2552                 { 0x0d, 0xf880 }
2553         };
2554         void __iomem *ioaddr = tp->mmio_addr;
2555
2556         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2557
2558         /*
2559          * Rx Error Issue
2560          * Fine Tune Switching regulator parameter
2561          */
2562         rtl_writephy(tp, 0x1f, 0x0002);
2563         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2564         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2565
2566         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2567                 static const struct phy_reg phy_reg_init[] = {
2568                         { 0x1f, 0x0002 },
2569                         { 0x05, 0x669a },
2570                         { 0x1f, 0x0005 },
2571                         { 0x05, 0x8330 },
2572                         { 0x06, 0x669a },
2573                         { 0x1f, 0x0002 }
2574                 };
2575                 int val;
2576
2577                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2578
2579                 val = rtl_readphy(tp, 0x0d);
2580
2581                 if ((val & 0x00ff) != 0x006c) {
2582                         static const u32 set[] = {
2583                                 0x0065, 0x0066, 0x0067, 0x0068,
2584                                 0x0069, 0x006a, 0x006b, 0x006c
2585                         };
2586                         int i;
2587
2588                         rtl_writephy(tp, 0x1f, 0x0002);
2589
2590                         val &= 0xff00;
2591                         for (i = 0; i < ARRAY_SIZE(set); i++)
2592                                 rtl_writephy(tp, 0x0d, val | set[i]);
2593                 }
2594         } else {
2595                 static const struct phy_reg phy_reg_init[] = {
2596                         { 0x1f, 0x0002 },
2597                         { 0x05, 0x6662 },
2598                         { 0x1f, 0x0005 },
2599                         { 0x05, 0x8330 },
2600                         { 0x06, 0x6662 }
2601                 };
2602
2603                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2604         }
2605
2606         /* RSET couple improve */
2607         rtl_writephy(tp, 0x1f, 0x0002);
2608         rtl_patchphy(tp, 0x0d, 0x0300);
2609         rtl_patchphy(tp, 0x0f, 0x0010);
2610
2611         /* Fine tune PLL performance */
2612         rtl_writephy(tp, 0x1f, 0x0002);
2613         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2614         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2615
2616         rtl_writephy(tp, 0x1f, 0x0005);
2617         rtl_writephy(tp, 0x05, 0x001b);
2618
2619         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2620
2621         rtl_writephy(tp, 0x1f, 0x0000);
2622 }
2623
2624 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2625 {
2626         static const struct phy_reg phy_reg_init_0[] = {
2627                 /* Channel Estimation */
2628                 { 0x1f, 0x0001 },
2629                 { 0x06, 0x4064 },
2630                 { 0x07, 0x2863 },
2631                 { 0x08, 0x059c },
2632                 { 0x09, 0x26b4 },
2633                 { 0x0a, 0x6a19 },
2634                 { 0x0b, 0xdcc8 },
2635                 { 0x10, 0xf06d },
2636                 { 0x14, 0x7f68 },
2637                 { 0x18, 0x7fd9 },
2638                 { 0x1c, 0xf0ff },
2639                 { 0x1d, 0x3d9c },
2640                 { 0x1f, 0x0003 },
2641                 { 0x12, 0xf49f },
2642                 { 0x13, 0x070b },
2643                 { 0x1a, 0x05ad },
2644                 { 0x14, 0x94c0 },
2645
2646                 /*
2647                  * Tx Error Issue
2648                  * Enhance line driver power
2649                  */
2650                 { 0x1f, 0x0002 },
2651                 { 0x06, 0x5561 },
2652                 { 0x1f, 0x0005 },
2653                 { 0x05, 0x8332 },
2654                 { 0x06, 0x5561 },
2655
2656                 /*
2657                  * Can not link to 1Gbps with bad cable
2658                  * Decrease SNR threshold form 21.07dB to 19.04dB
2659                  */
2660                 { 0x1f, 0x0001 },
2661                 { 0x17, 0x0cc0 },
2662
2663                 { 0x1f, 0x0000 },
2664                 { 0x0d, 0xf880 }
2665         };
2666         void __iomem *ioaddr = tp->mmio_addr;
2667
2668         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2669
2670         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2671                 static const struct phy_reg phy_reg_init[] = {
2672                         { 0x1f, 0x0002 },
2673                         { 0x05, 0x669a },
2674                         { 0x1f, 0x0005 },
2675                         { 0x05, 0x8330 },
2676                         { 0x06, 0x669a },
2677
2678                         { 0x1f, 0x0002 }
2679                 };
2680                 int val;
2681
2682                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2683
2684                 val = rtl_readphy(tp, 0x0d);
2685                 if ((val & 0x00ff) != 0x006c) {
2686                         static const u32 set[] = {
2687                                 0x0065, 0x0066, 0x0067, 0x0068,
2688                                 0x0069, 0x006a, 0x006b, 0x006c
2689                         };
2690                         int i;
2691
2692                         rtl_writephy(tp, 0x1f, 0x0002);
2693
2694                         val &= 0xff00;
2695                         for (i = 0; i < ARRAY_SIZE(set); i++)
2696                                 rtl_writephy(tp, 0x0d, val | set[i]);
2697                 }
2698         } else {
2699                 static const struct phy_reg phy_reg_init[] = {
2700                         { 0x1f, 0x0002 },
2701                         { 0x05, 0x2642 },
2702                         { 0x1f, 0x0005 },
2703                         { 0x05, 0x8330 },
2704                         { 0x06, 0x2642 }
2705                 };
2706
2707                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2708         }
2709
2710         /* Fine tune PLL performance */
2711         rtl_writephy(tp, 0x1f, 0x0002);
2712         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2713         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2714
2715         /* Switching regulator Slew rate */
2716         rtl_writephy(tp, 0x1f, 0x0002);
2717         rtl_patchphy(tp, 0x0f, 0x0017);
2718
2719         rtl_writephy(tp, 0x1f, 0x0005);
2720         rtl_writephy(tp, 0x05, 0x001b);
2721
2722         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2723
2724         rtl_writephy(tp, 0x1f, 0x0000);
2725 }
2726
2727 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2728 {
2729         static const struct phy_reg phy_reg_init[] = {
2730                 { 0x1f, 0x0002 },
2731                 { 0x10, 0x0008 },
2732                 { 0x0d, 0x006c },
2733
2734                 { 0x1f, 0x0000 },
2735                 { 0x0d, 0xf880 },
2736
2737                 { 0x1f, 0x0001 },
2738                 { 0x17, 0x0cc0 },
2739
2740                 { 0x1f, 0x0001 },
2741                 { 0x0b, 0xa4d8 },
2742                 { 0x09, 0x281c },
2743                 { 0x07, 0x2883 },
2744                 { 0x0a, 0x6b35 },
2745                 { 0x1d, 0x3da4 },
2746                 { 0x1c, 0xeffd },
2747                 { 0x14, 0x7f52 },
2748                 { 0x18, 0x7fc6 },
2749                 { 0x08, 0x0601 },
2750                 { 0x06, 0x4063 },
2751                 { 0x10, 0xf074 },
2752                 { 0x1f, 0x0003 },
2753                 { 0x13, 0x0789 },
2754                 { 0x12, 0xf4bd },
2755                 { 0x1a, 0x04fd },
2756                 { 0x14, 0x84b0 },
2757                 { 0x1f, 0x0000 },
2758                 { 0x00, 0x9200 },
2759
2760                 { 0x1f, 0x0005 },
2761                 { 0x01, 0x0340 },
2762                 { 0x1f, 0x0001 },
2763                 { 0x04, 0x4000 },
2764                 { 0x03, 0x1d21 },
2765                 { 0x02, 0x0c32 },
2766                 { 0x01, 0x0200 },
2767                 { 0x00, 0x5554 },
2768                 { 0x04, 0x4800 },
2769                 { 0x04, 0x4000 },
2770                 { 0x04, 0xf000 },
2771                 { 0x03, 0xdf01 },
2772                 { 0x02, 0xdf20 },
2773                 { 0x01, 0x101a },
2774                 { 0x00, 0xa0ff },
2775                 { 0x04, 0xf800 },
2776                 { 0x04, 0xf000 },
2777                 { 0x1f, 0x0000 },
2778
2779                 { 0x1f, 0x0007 },
2780                 { 0x1e, 0x0023 },
2781                 { 0x16, 0x0000 },
2782                 { 0x1f, 0x0000 }
2783         };
2784
2785         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2786 }
2787
2788 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2789 {
2790         static const struct phy_reg phy_reg_init[] = {
2791                 { 0x1f, 0x0001 },
2792                 { 0x17, 0x0cc0 },
2793
2794                 { 0x1f, 0x0007 },
2795                 { 0x1e, 0x002d },
2796                 { 0x18, 0x0040 },
2797                 { 0x1f, 0x0000 }
2798         };
2799
2800         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2801         rtl_patchphy(tp, 0x0d, 1 << 5);
2802 }
2803
2804 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2805 {
2806         static const struct phy_reg phy_reg_init[] = {
2807                 /* Enable Delay cap */
2808                 { 0x1f, 0x0005 },
2809                 { 0x05, 0x8b80 },
2810                 { 0x06, 0xc896 },
2811                 { 0x1f, 0x0000 },
2812
2813                 /* Channel estimation fine tune */
2814                 { 0x1f, 0x0001 },
2815                 { 0x0b, 0x6c20 },
2816                 { 0x07, 0x2872 },
2817                 { 0x1c, 0xefff },
2818                 { 0x1f, 0x0003 },
2819                 { 0x14, 0x6420 },
2820                 { 0x1f, 0x0000 },
2821
2822                 /* Update PFM & 10M TX idle timer */
2823                 { 0x1f, 0x0007 },
2824                 { 0x1e, 0x002f },
2825                 { 0x15, 0x1919 },
2826                 { 0x1f, 0x0000 },
2827
2828                 { 0x1f, 0x0007 },
2829                 { 0x1e, 0x00ac },
2830                 { 0x18, 0x0006 },
2831                 { 0x1f, 0x0000 }
2832         };
2833
2834         rtl_apply_firmware(tp);
2835
2836         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2837
2838         /* DCO enable for 10M IDLE Power */
2839         rtl_writephy(tp, 0x1f, 0x0007);
2840         rtl_writephy(tp, 0x1e, 0x0023);
2841         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2842         rtl_writephy(tp, 0x1f, 0x0000);
2843
2844         /* For impedance matching */
2845         rtl_writephy(tp, 0x1f, 0x0002);
2846         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2847         rtl_writephy(tp, 0x1f, 0x0000);
2848
2849         /* PHY auto speed down */
2850         rtl_writephy(tp, 0x1f, 0x0007);
2851         rtl_writephy(tp, 0x1e, 0x002d);
2852         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2853         rtl_writephy(tp, 0x1f, 0x0000);
2854         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2855
2856         rtl_writephy(tp, 0x1f, 0x0005);
2857         rtl_writephy(tp, 0x05, 0x8b86);
2858         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2859         rtl_writephy(tp, 0x1f, 0x0000);
2860
2861         rtl_writephy(tp, 0x1f, 0x0005);
2862         rtl_writephy(tp, 0x05, 0x8b85);
2863         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2864         rtl_writephy(tp, 0x1f, 0x0007);
2865         rtl_writephy(tp, 0x1e, 0x0020);
2866         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2867         rtl_writephy(tp, 0x1f, 0x0006);
2868         rtl_writephy(tp, 0x00, 0x5a00);
2869         rtl_writephy(tp, 0x1f, 0x0000);
2870         rtl_writephy(tp, 0x0d, 0x0007);
2871         rtl_writephy(tp, 0x0e, 0x003c);
2872         rtl_writephy(tp, 0x0d, 0x4007);
2873         rtl_writephy(tp, 0x0e, 0x0000);
2874         rtl_writephy(tp, 0x0d, 0x0000);
2875 }
2876
2877 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2878 {
2879         static const struct phy_reg phy_reg_init[] = {
2880                 /* Enable Delay cap */
2881                 { 0x1f, 0x0004 },
2882                 { 0x1f, 0x0007 },
2883                 { 0x1e, 0x00ac },
2884                 { 0x18, 0x0006 },
2885                 { 0x1f, 0x0002 },
2886                 { 0x1f, 0x0000 },
2887                 { 0x1f, 0x0000 },
2888
2889                 /* Channel estimation fine tune */
2890                 { 0x1f, 0x0003 },
2891                 { 0x09, 0xa20f },
2892                 { 0x1f, 0x0000 },
2893                 { 0x1f, 0x0000 },
2894
2895                 /* Green Setting */
2896                 { 0x1f, 0x0005 },
2897                 { 0x05, 0x8b5b },
2898                 { 0x06, 0x9222 },
2899                 { 0x05, 0x8b6d },
2900                 { 0x06, 0x8000 },
2901                 { 0x05, 0x8b76 },
2902                 { 0x06, 0x8000 },
2903                 { 0x1f, 0x0000 }
2904         };
2905
2906         rtl_apply_firmware(tp);
2907
2908         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2909
2910         /* For 4-corner performance improve */
2911         rtl_writephy(tp, 0x1f, 0x0005);
2912         rtl_writephy(tp, 0x05, 0x8b80);
2913         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2914         rtl_writephy(tp, 0x1f, 0x0000);
2915
2916         /* PHY auto speed down */
2917         rtl_writephy(tp, 0x1f, 0x0004);
2918         rtl_writephy(tp, 0x1f, 0x0007);
2919         rtl_writephy(tp, 0x1e, 0x002d);
2920         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2921         rtl_writephy(tp, 0x1f, 0x0002);
2922         rtl_writephy(tp, 0x1f, 0x0000);
2923         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2924
2925         /* improve 10M EEE waveform */
2926         rtl_writephy(tp, 0x1f, 0x0005);
2927         rtl_writephy(tp, 0x05, 0x8b86);
2928         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2929         rtl_writephy(tp, 0x1f, 0x0000);
2930
2931         /* Improve 2-pair detection performance */
2932         rtl_writephy(tp, 0x1f, 0x0005);
2933         rtl_writephy(tp, 0x05, 0x8b85);
2934         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2935         rtl_writephy(tp, 0x1f, 0x0000);
2936
2937         /* EEE setting */
2938         rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2939                      ERIAR_EXGMAC);
2940         rtl_writephy(tp, 0x1f, 0x0005);
2941         rtl_writephy(tp, 0x05, 0x8b85);
2942         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2943         rtl_writephy(tp, 0x1f, 0x0004);
2944         rtl_writephy(tp, 0x1f, 0x0007);
2945         rtl_writephy(tp, 0x1e, 0x0020);
2946         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
2947         rtl_writephy(tp, 0x1f, 0x0002);
2948         rtl_writephy(tp, 0x1f, 0x0000);
2949         rtl_writephy(tp, 0x0d, 0x0007);
2950         rtl_writephy(tp, 0x0e, 0x003c);
2951         rtl_writephy(tp, 0x0d, 0x4007);
2952         rtl_writephy(tp, 0x0e, 0x0000);
2953         rtl_writephy(tp, 0x0d, 0x0000);
2954
2955         /* Green feature */
2956         rtl_writephy(tp, 0x1f, 0x0003);
2957         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
2958         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
2959         rtl_writephy(tp, 0x1f, 0x0000);
2960 }
2961
2962 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
2963 {
2964         static const struct phy_reg phy_reg_init[] = {
2965                 /* Channel estimation fine tune */
2966                 { 0x1f, 0x0003 },
2967                 { 0x09, 0xa20f },
2968                 { 0x1f, 0x0000 },
2969
2970                 /* Modify green table for giga & fnet */
2971                 { 0x1f, 0x0005 },
2972                 { 0x05, 0x8b55 },
2973                 { 0x06, 0x0000 },
2974                 { 0x05, 0x8b5e },
2975                 { 0x06, 0x0000 },
2976                 { 0x05, 0x8b67 },
2977                 { 0x06, 0x0000 },
2978                 { 0x05, 0x8b70 },
2979                 { 0x06, 0x0000 },
2980                 { 0x1f, 0x0000 },
2981                 { 0x1f, 0x0007 },
2982                 { 0x1e, 0x0078 },
2983                 { 0x17, 0x0000 },
2984                 { 0x19, 0x00fb },
2985                 { 0x1f, 0x0000 },
2986
2987                 /* Modify green table for 10M */
2988                 { 0x1f, 0x0005 },
2989                 { 0x05, 0x8b79 },
2990                 { 0x06, 0xaa00 },
2991                 { 0x1f, 0x0000 },
2992
2993                 /* Disable hiimpedance detection (RTCT) */
2994                 { 0x1f, 0x0003 },
2995                 { 0x01, 0x328a },
2996                 { 0x1f, 0x0000 }
2997         };
2998
2999         rtl_apply_firmware(tp);
3000
3001         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3002
3003         /* For 4-corner performance improve */
3004         rtl_writephy(tp, 0x1f, 0x0005);
3005         rtl_writephy(tp, 0x05, 0x8b80);
3006         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3007         rtl_writephy(tp, 0x1f, 0x0000);
3008
3009         /* PHY auto speed down */
3010         rtl_writephy(tp, 0x1f, 0x0007);
3011         rtl_writephy(tp, 0x1e, 0x002d);
3012         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3013         rtl_writephy(tp, 0x1f, 0x0000);
3014         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3015
3016         /* Improve 10M EEE waveform */
3017         rtl_writephy(tp, 0x1f, 0x0005);
3018         rtl_writephy(tp, 0x05, 0x8b86);
3019         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3020         rtl_writephy(tp, 0x1f, 0x0000);
3021
3022         /* Improve 2-pair detection performance */
3023         rtl_writephy(tp, 0x1f, 0x0005);
3024         rtl_writephy(tp, 0x05, 0x8b85);
3025         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3026         rtl_writephy(tp, 0x1f, 0x0000);
3027 }
3028
3029 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3030 {
3031         rtl_apply_firmware(tp);
3032
3033         /* For 4-corner performance improve */
3034         rtl_writephy(tp, 0x1f, 0x0005);
3035         rtl_writephy(tp, 0x05, 0x8b80);
3036         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3037         rtl_writephy(tp, 0x1f, 0x0000);
3038
3039         /* PHY auto speed down */
3040         rtl_writephy(tp, 0x1f, 0x0007);
3041         rtl_writephy(tp, 0x1e, 0x002d);
3042         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3043         rtl_writephy(tp, 0x1f, 0x0000);
3044         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3045
3046         /* Improve 10M EEE waveform */
3047         rtl_writephy(tp, 0x1f, 0x0005);
3048         rtl_writephy(tp, 0x05, 0x8b86);
3049         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3050         rtl_writephy(tp, 0x1f, 0x0000);
3051 }
3052
3053 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3054 {
3055         static const struct phy_reg phy_reg_init[] = {
3056                 { 0x1f, 0x0003 },
3057                 { 0x08, 0x441d },
3058                 { 0x01, 0x9100 },
3059                 { 0x1f, 0x0000 }
3060         };
3061
3062         rtl_writephy(tp, 0x1f, 0x0000);
3063         rtl_patchphy(tp, 0x11, 1 << 12);
3064         rtl_patchphy(tp, 0x19, 1 << 13);
3065         rtl_patchphy(tp, 0x10, 1 << 15);
3066
3067         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3068 }
3069
3070 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3071 {
3072         static const struct phy_reg phy_reg_init[] = {
3073                 { 0x1f, 0x0005 },
3074                 { 0x1a, 0x0000 },
3075                 { 0x1f, 0x0000 },
3076
3077                 { 0x1f, 0x0004 },
3078                 { 0x1c, 0x0000 },
3079                 { 0x1f, 0x0000 },
3080
3081                 { 0x1f, 0x0001 },
3082                 { 0x15, 0x7701 },
3083                 { 0x1f, 0x0000 }
3084         };
3085
3086         /* Disable ALDPS before ram code */
3087         rtl_writephy(tp, 0x1f, 0x0000);
3088         rtl_writephy(tp, 0x18, 0x0310);
3089         msleep(100);
3090
3091         rtl_apply_firmware(tp);
3092
3093         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3094 }
3095
3096 static void rtl_hw_phy_config(struct net_device *dev)
3097 {
3098         struct rtl8169_private *tp = netdev_priv(dev);
3099
3100         rtl8169_print_mac_version(tp);
3101
3102         switch (tp->mac_version) {
3103         case RTL_GIGA_MAC_VER_01:
3104                 break;
3105         case RTL_GIGA_MAC_VER_02:
3106         case RTL_GIGA_MAC_VER_03:
3107                 rtl8169s_hw_phy_config(tp);
3108                 break;
3109         case RTL_GIGA_MAC_VER_04:
3110                 rtl8169sb_hw_phy_config(tp);
3111                 break;
3112         case RTL_GIGA_MAC_VER_05:
3113                 rtl8169scd_hw_phy_config(tp);
3114                 break;
3115         case RTL_GIGA_MAC_VER_06:
3116                 rtl8169sce_hw_phy_config(tp);
3117                 break;
3118         case RTL_GIGA_MAC_VER_07:
3119         case RTL_GIGA_MAC_VER_08:
3120         case RTL_GIGA_MAC_VER_09:
3121                 rtl8102e_hw_phy_config(tp);
3122                 break;
3123         case RTL_GIGA_MAC_VER_11:
3124                 rtl8168bb_hw_phy_config(tp);
3125                 break;
3126         case RTL_GIGA_MAC_VER_12:
3127                 rtl8168bef_hw_phy_config(tp);
3128                 break;
3129         case RTL_GIGA_MAC_VER_17:
3130                 rtl8168bef_hw_phy_config(tp);
3131                 break;
3132         case RTL_GIGA_MAC_VER_18:
3133                 rtl8168cp_1_hw_phy_config(tp);
3134                 break;
3135         case RTL_GIGA_MAC_VER_19:
3136                 rtl8168c_1_hw_phy_config(tp);
3137                 break;
3138         case RTL_GIGA_MAC_VER_20:
3139                 rtl8168c_2_hw_phy_config(tp);
3140                 break;
3141         case RTL_GIGA_MAC_VER_21:
3142                 rtl8168c_3_hw_phy_config(tp);
3143                 break;
3144         case RTL_GIGA_MAC_VER_22:
3145                 rtl8168c_4_hw_phy_config(tp);
3146                 break;
3147         case RTL_GIGA_MAC_VER_23:
3148         case RTL_GIGA_MAC_VER_24:
3149                 rtl8168cp_2_hw_phy_config(tp);
3150                 break;
3151         case RTL_GIGA_MAC_VER_25:
3152                 rtl8168d_1_hw_phy_config(tp);
3153                 break;
3154         case RTL_GIGA_MAC_VER_26:
3155                 rtl8168d_2_hw_phy_config(tp);
3156                 break;
3157         case RTL_GIGA_MAC_VER_27:
3158                 rtl8168d_3_hw_phy_config(tp);
3159                 break;
3160         case RTL_GIGA_MAC_VER_28:
3161                 rtl8168d_4_hw_phy_config(tp);
3162                 break;
3163         case RTL_GIGA_MAC_VER_29:
3164         case RTL_GIGA_MAC_VER_30:
3165                 rtl8105e_hw_phy_config(tp);
3166                 break;
3167         case RTL_GIGA_MAC_VER_31:
3168                 /* None. */
3169                 break;
3170         case RTL_GIGA_MAC_VER_32:
3171         case RTL_GIGA_MAC_VER_33:
3172                 rtl8168e_1_hw_phy_config(tp);
3173                 break;
3174         case RTL_GIGA_MAC_VER_34:
3175                 rtl8168e_2_hw_phy_config(tp);
3176                 break;
3177         case RTL_GIGA_MAC_VER_35:
3178                 rtl8168f_1_hw_phy_config(tp);
3179                 break;
3180         case RTL_GIGA_MAC_VER_36:
3181                 rtl8168f_2_hw_phy_config(tp);
3182                 break;
3183
3184         default:
3185                 break;
3186         }
3187 }
3188
3189 static void rtl8169_phy_timer(unsigned long __opaque)
3190 {
3191         struct net_device *dev = (struct net_device *)__opaque;
3192         struct rtl8169_private *tp = netdev_priv(dev);
3193         struct timer_list *timer = &tp->timer;
3194         void __iomem *ioaddr = tp->mmio_addr;
3195         unsigned long timeout = RTL8169_PHY_TIMEOUT;
3196
3197         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3198
3199         spin_lock_irq(&tp->lock);
3200
3201         if (tp->phy_reset_pending(tp)) {
3202                 /*
3203                  * A busy loop could burn quite a few cycles on nowadays CPU.
3204                  * Let's delay the execution of the timer for a few ticks.
3205                  */
3206                 timeout = HZ/10;
3207                 goto out_mod_timer;
3208         }
3209
3210         if (tp->link_ok(ioaddr))
3211                 goto out_unlock;
3212
3213         netif_warn(tp, link, dev, "PHY reset until link up\n");
3214
3215         tp->phy_reset_enable(tp);
3216
3217 out_mod_timer:
3218         mod_timer(timer, jiffies + timeout);
3219 out_unlock:
3220         spin_unlock_irq(&tp->lock);
3221 }
3222
3223 #ifdef CONFIG_NET_POLL_CONTROLLER
3224 /*
3225  * Polling 'interrupt' - used by things like netconsole to send skbs
3226  * without having to re-enable interrupts. It's not called while
3227  * the interrupt routine is executing.
3228  */
3229 static void rtl8169_netpoll(struct net_device *dev)
3230 {
3231         struct rtl8169_private *tp = netdev_priv(dev);
3232         struct pci_dev *pdev = tp->pci_dev;
3233
3234         disable_irq(pdev->irq);
3235         rtl8169_interrupt(pdev->irq, dev);
3236         enable_irq(pdev->irq);
3237 }
3238 #endif
3239
3240 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3241                                   void __iomem *ioaddr)
3242 {
3243         iounmap(ioaddr);
3244         pci_release_regions(pdev);
3245         pci_clear_mwi(pdev);
3246         pci_disable_device(pdev);
3247         free_netdev(dev);
3248 }
3249
3250 static void rtl8169_phy_reset(struct net_device *dev,
3251                               struct rtl8169_private *tp)
3252 {
3253         unsigned int i;
3254
3255         tp->phy_reset_enable(tp);
3256         for (i = 0; i < 100; i++) {
3257                 if (!tp->phy_reset_pending(tp))
3258                         return;
3259                 msleep(1);
3260         }
3261         netif_err(tp, link, dev, "PHY reset failed\n");
3262 }
3263
3264 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3265 {
3266         void __iomem *ioaddr = tp->mmio_addr;
3267
3268         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3269             (RTL_R8(PHYstatus) & TBI_Enable);
3270 }
3271
3272 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3273 {
3274         void __iomem *ioaddr = tp->mmio_addr;
3275
3276         rtl_hw_phy_config(dev);
3277
3278         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3279                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3280                 RTL_W8(0x82, 0x01);
3281         }
3282
3283         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3284
3285         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3286                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3287
3288         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3289                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3290                 RTL_W8(0x82, 0x01);
3291                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3292                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3293         }
3294
3295         rtl8169_phy_reset(dev, tp);
3296
3297         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3298                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3299                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3300                           (tp->mii.supports_gmii ?
3301                            ADVERTISED_1000baseT_Half |
3302                            ADVERTISED_1000baseT_Full : 0));
3303
3304         if (rtl_tbi_enabled(tp))
3305                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3306 }
3307
3308 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3309 {
3310         void __iomem *ioaddr = tp->mmio_addr;
3311         u32 high;
3312         u32 low;
3313
3314         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3315         high = addr[4] | (addr[5] << 8);
3316
3317         spin_lock_irq(&tp->lock);
3318
3319         RTL_W8(Cfg9346, Cfg9346_Unlock);
3320
3321         RTL_W32(MAC4, high);
3322         RTL_R32(MAC4);
3323
3324         RTL_W32(MAC0, low);
3325         RTL_R32(MAC0);
3326
3327         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3328                 const struct exgmac_reg e[] = {
3329                         { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3330                         { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3331                         { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3332                         { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3333                                                                 low  >> 16 },
3334                 };
3335
3336                 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3337         }
3338
3339         RTL_W8(Cfg9346, Cfg9346_Lock);
3340
3341         spin_unlock_irq(&tp->lock);
3342 }
3343
3344 static int rtl_set_mac_address(struct net_device *dev, void *p)
3345 {
3346         struct rtl8169_private *tp = netdev_priv(dev);
3347         struct sockaddr *addr = p;
3348
3349         if (!is_valid_ether_addr(addr->sa_data))
3350                 return -EADDRNOTAVAIL;
3351
3352         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3353
3354         rtl_rar_set(tp, dev->dev_addr);
3355
3356         return 0;
3357 }
3358
3359 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3360 {
3361         struct rtl8169_private *tp = netdev_priv(dev);
3362         struct mii_ioctl_data *data = if_mii(ifr);
3363
3364         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3365 }
3366
3367 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3368                           struct mii_ioctl_data *data, int cmd)
3369 {
3370         switch (cmd) {
3371         case SIOCGMIIPHY:
3372                 data->phy_id = 32; /* Internal PHY */
3373                 return 0;
3374
3375         case SIOCGMIIREG:
3376                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3377                 return 0;
3378
3379         case SIOCSMIIREG:
3380                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3381                 return 0;
3382         }
3383         return -EOPNOTSUPP;
3384 }
3385
3386 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3387 {
3388         return -EOPNOTSUPP;
3389 }
3390
3391 static const struct rtl_cfg_info {
3392         void (*hw_start)(struct net_device *);
3393         unsigned int region;
3394         unsigned int align;
3395         u16 intr_event;
3396         u16 napi_event;
3397         unsigned features;
3398         u8 default_ver;
3399 } rtl_cfg_infos [] = {
3400         [RTL_CFG_0] = {
3401                 .hw_start       = rtl_hw_start_8169,
3402                 .region         = 1,
3403                 .align          = 0,
3404                 .intr_event     = SYSErr | LinkChg | RxOverflow |
3405                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3406                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3407                 .features       = RTL_FEATURE_GMII,
3408                 .default_ver    = RTL_GIGA_MAC_VER_01,
3409         },
3410         [RTL_CFG_1] = {
3411                 .hw_start       = rtl_hw_start_8168,
3412                 .region         = 2,
3413                 .align          = 8,
3414                 .intr_event     = SYSErr | LinkChg | RxOverflow |
3415                                   TxErr | TxOK | RxOK | RxErr,
3416                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
3417                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3418                 .default_ver    = RTL_GIGA_MAC_VER_11,
3419         },
3420         [RTL_CFG_2] = {
3421                 .hw_start       = rtl_hw_start_8101,
3422                 .region         = 2,
3423                 .align          = 8,
3424                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
3425                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3426                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3427                 .features       = RTL_FEATURE_MSI,
3428                 .default_ver    = RTL_GIGA_MAC_VER_13,
3429         }
3430 };
3431
3432 /* Cfg9346_Unlock assumed. */
3433 static unsigned rtl_try_msi(struct rtl8169_private *tp,
3434                             const struct rtl_cfg_info *cfg)
3435 {
3436         void __iomem *ioaddr = tp->mmio_addr;
3437         unsigned msi = 0;
3438         u8 cfg2;
3439
3440         cfg2 = RTL_R8(Config2) & ~MSIEnable;
3441         if (cfg->features & RTL_FEATURE_MSI) {
3442                 if (pci_enable_msi(tp->pci_dev)) {
3443                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
3444                 } else {
3445                         cfg2 |= MSIEnable;
3446                         msi = RTL_FEATURE_MSI;
3447                 }
3448         }
3449         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3450                 RTL_W8(Config2, cfg2);
3451         return msi;
3452 }
3453
3454 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3455 {
3456         if (tp->features & RTL_FEATURE_MSI) {
3457                 pci_disable_msi(pdev);
3458                 tp->features &= ~RTL_FEATURE_MSI;
3459         }
3460 }
3461
3462 static const struct net_device_ops rtl8169_netdev_ops = {
3463         .ndo_open               = rtl8169_open,
3464         .ndo_stop               = rtl8169_close,
3465         .ndo_get_stats          = rtl8169_get_stats,
3466         .ndo_start_xmit         = rtl8169_start_xmit,
3467         .ndo_tx_timeout         = rtl8169_tx_timeout,
3468         .ndo_validate_addr      = eth_validate_addr,
3469         .ndo_change_mtu         = rtl8169_change_mtu,
3470         .ndo_fix_features       = rtl8169_fix_features,
3471         .ndo_set_features       = rtl8169_set_features,
3472         .ndo_set_mac_address    = rtl_set_mac_address,
3473         .ndo_do_ioctl           = rtl8169_ioctl,
3474         .ndo_set_rx_mode        = rtl_set_rx_mode,
3475 #ifdef CONFIG_NET_POLL_CONTROLLER
3476         .ndo_poll_controller    = rtl8169_netpoll,
3477 #endif
3478
3479 };
3480
3481 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3482 {
3483         struct mdio_ops *ops = &tp->mdio_ops;
3484
3485         switch (tp->mac_version) {
3486         case RTL_GIGA_MAC_VER_27:
3487                 ops->write      = r8168dp_1_mdio_write;
3488                 ops->read       = r8168dp_1_mdio_read;
3489                 break;
3490         case RTL_GIGA_MAC_VER_28:
3491         case RTL_GIGA_MAC_VER_31:
3492                 ops->write      = r8168dp_2_mdio_write;
3493                 ops->read       = r8168dp_2_mdio_read;
3494                 break;
3495         default:
3496                 ops->write      = r8169_mdio_write;
3497                 ops->read       = r8169_mdio_read;
3498                 break;
3499         }
3500 }
3501
3502 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3503 {
3504         void __iomem *ioaddr = tp->mmio_addr;
3505
3506         switch (tp->mac_version) {
3507         case RTL_GIGA_MAC_VER_29:
3508         case RTL_GIGA_MAC_VER_30:
3509         case RTL_GIGA_MAC_VER_32:
3510         case RTL_GIGA_MAC_VER_33:
3511         case RTL_GIGA_MAC_VER_34:
3512                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3513                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3514                 break;
3515         default:
3516                 break;
3517         }
3518 }
3519
3520 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3521 {
3522         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3523                 return false;
3524
3525         rtl_writephy(tp, 0x1f, 0x0000);
3526         rtl_writephy(tp, MII_BMCR, 0x0000);
3527
3528         rtl_wol_suspend_quirk(tp);
3529
3530         return true;
3531 }
3532
3533 static void r810x_phy_power_down(struct rtl8169_private *tp)
3534 {
3535         rtl_writephy(tp, 0x1f, 0x0000);
3536         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3537 }
3538
3539 static void r810x_phy_power_up(struct rtl8169_private *tp)
3540 {
3541         rtl_writephy(tp, 0x1f, 0x0000);
3542         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3543 }
3544
3545 static void r810x_pll_power_down(struct rtl8169_private *tp)
3546 {
3547         if (rtl_wol_pll_power_down(tp))
3548                 return;
3549
3550         r810x_phy_power_down(tp);
3551 }
3552
3553 static void r810x_pll_power_up(struct rtl8169_private *tp)
3554 {
3555         r810x_phy_power_up(tp);
3556 }
3557
3558 static void r8168_phy_power_up(struct rtl8169_private *tp)
3559 {
3560         rtl_writephy(tp, 0x1f, 0x0000);
3561         switch (tp->mac_version) {
3562         case RTL_GIGA_MAC_VER_11:
3563         case RTL_GIGA_MAC_VER_12:
3564         case RTL_GIGA_MAC_VER_17:
3565         case RTL_GIGA_MAC_VER_18:
3566         case RTL_GIGA_MAC_VER_19:
3567         case RTL_GIGA_MAC_VER_20:
3568         case RTL_GIGA_MAC_VER_21:
3569         case RTL_GIGA_MAC_VER_22:
3570         case RTL_GIGA_MAC_VER_23:
3571         case RTL_GIGA_MAC_VER_24:
3572         case RTL_GIGA_MAC_VER_25:
3573         case RTL_GIGA_MAC_VER_26:
3574         case RTL_GIGA_MAC_VER_27:
3575         case RTL_GIGA_MAC_VER_28:
3576         case RTL_GIGA_MAC_VER_31:
3577                 rtl_writephy(tp, 0x0e, 0x0000);
3578                 break;
3579         default:
3580                 break;
3581         }
3582         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3583 }
3584
3585 static void r8168_phy_power_down(struct rtl8169_private *tp)
3586 {
3587         rtl_writephy(tp, 0x1f, 0x0000);
3588         switch (tp->mac_version) {
3589         case RTL_GIGA_MAC_VER_32:
3590         case RTL_GIGA_MAC_VER_33:
3591                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3592                 break;
3593
3594         case RTL_GIGA_MAC_VER_11:
3595         case RTL_GIGA_MAC_VER_12:
3596         case RTL_GIGA_MAC_VER_17:
3597         case RTL_GIGA_MAC_VER_18:
3598         case RTL_GIGA_MAC_VER_19:
3599         case RTL_GIGA_MAC_VER_20:
3600         case RTL_GIGA_MAC_VER_21:
3601         case RTL_GIGA_MAC_VER_22:
3602         case RTL_GIGA_MAC_VER_23:
3603         case RTL_GIGA_MAC_VER_24:
3604         case RTL_GIGA_MAC_VER_25:
3605         case RTL_GIGA_MAC_VER_26:
3606         case RTL_GIGA_MAC_VER_27:
3607         case RTL_GIGA_MAC_VER_28:
3608         case RTL_GIGA_MAC_VER_31:
3609                 rtl_writephy(tp, 0x0e, 0x0200);
3610         default:
3611                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3612                 break;
3613         }
3614 }
3615
3616 static void r8168_pll_power_down(struct rtl8169_private *tp)
3617 {
3618         void __iomem *ioaddr = tp->mmio_addr;
3619
3620         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3621              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3622              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3623             r8168dp_check_dash(tp)) {
3624                 return;
3625         }
3626
3627         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3628              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3629             (RTL_R16(CPlusCmd) & ASF)) {
3630                 return;
3631         }
3632
3633         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3634             tp->mac_version == RTL_GIGA_MAC_VER_33)
3635                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3636
3637         if (rtl_wol_pll_power_down(tp))
3638                 return;
3639
3640         r8168_phy_power_down(tp);
3641
3642         switch (tp->mac_version) {
3643         case RTL_GIGA_MAC_VER_25:
3644         case RTL_GIGA_MAC_VER_26:
3645         case RTL_GIGA_MAC_VER_27:
3646         case RTL_GIGA_MAC_VER_28:
3647         case RTL_GIGA_MAC_VER_31:
3648         case RTL_GIGA_MAC_VER_32:
3649         case RTL_GIGA_MAC_VER_33:
3650                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3651                 break;
3652         }
3653 }
3654
3655 static void r8168_pll_power_up(struct rtl8169_private *tp)
3656 {
3657         void __iomem *ioaddr = tp->mmio_addr;
3658
3659         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3660              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3661              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3662             r8168dp_check_dash(tp)) {
3663                 return;
3664         }
3665
3666         switch (tp->mac_version) {
3667         case RTL_GIGA_MAC_VER_25:
3668         case RTL_GIGA_MAC_VER_26:
3669         case RTL_GIGA_MAC_VER_27:
3670         case RTL_GIGA_MAC_VER_28:
3671         case RTL_GIGA_MAC_VER_31:
3672         case RTL_GIGA_MAC_VER_32:
3673         case RTL_GIGA_MAC_VER_33:
3674                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3675                 break;
3676         }
3677
3678         r8168_phy_power_up(tp);
3679 }
3680
3681 static void rtl_generic_op(struct rtl8169_private *tp,
3682                            void (*op)(struct rtl8169_private *))
3683 {
3684         if (op)
3685                 op(tp);
3686 }
3687
3688 static void rtl_pll_power_down(struct rtl8169_private *tp)
3689 {
3690         rtl_generic_op(tp, tp->pll_power_ops.down);
3691 }
3692
3693 static void rtl_pll_power_up(struct rtl8169_private *tp)
3694 {
3695         rtl_generic_op(tp, tp->pll_power_ops.up);
3696 }
3697
3698 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3699 {
3700         struct pll_power_ops *ops = &tp->pll_power_ops;
3701
3702         switch (tp->mac_version) {
3703         case RTL_GIGA_MAC_VER_07:
3704         case RTL_GIGA_MAC_VER_08:
3705         case RTL_GIGA_MAC_VER_09:
3706         case RTL_GIGA_MAC_VER_10:
3707         case RTL_GIGA_MAC_VER_16:
3708         case RTL_GIGA_MAC_VER_29:
3709         case RTL_GIGA_MAC_VER_30:
3710                 ops->down       = r810x_pll_power_down;
3711                 ops->up         = r810x_pll_power_up;
3712                 break;
3713
3714         case RTL_GIGA_MAC_VER_11:
3715         case RTL_GIGA_MAC_VER_12:
3716         case RTL_GIGA_MAC_VER_17:
3717         case RTL_GIGA_MAC_VER_18:
3718         case RTL_GIGA_MAC_VER_19:
3719         case RTL_GIGA_MAC_VER_20:
3720         case RTL_GIGA_MAC_VER_21:
3721         case RTL_GIGA_MAC_VER_22:
3722         case RTL_GIGA_MAC_VER_23:
3723         case RTL_GIGA_MAC_VER_24:
3724         case RTL_GIGA_MAC_VER_25:
3725         case RTL_GIGA_MAC_VER_26:
3726         case RTL_GIGA_MAC_VER_27:
3727         case RTL_GIGA_MAC_VER_28:
3728         case RTL_GIGA_MAC_VER_31:
3729         case RTL_GIGA_MAC_VER_32:
3730         case RTL_GIGA_MAC_VER_33:
3731         case RTL_GIGA_MAC_VER_34:
3732         case RTL_GIGA_MAC_VER_35:
3733         case RTL_GIGA_MAC_VER_36:
3734                 ops->down       = r8168_pll_power_down;
3735                 ops->up         = r8168_pll_power_up;
3736                 break;
3737
3738         default:
3739                 ops->down       = NULL;
3740                 ops->up         = NULL;
3741                 break;
3742         }
3743 }
3744
3745 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3746 {
3747         void __iomem *ioaddr = tp->mmio_addr;
3748
3749         switch (tp->mac_version) {
3750         case RTL_GIGA_MAC_VER_01:
3751         case RTL_GIGA_MAC_VER_02:
3752         case RTL_GIGA_MAC_VER_03:
3753         case RTL_GIGA_MAC_VER_04:
3754         case RTL_GIGA_MAC_VER_05:
3755         case RTL_GIGA_MAC_VER_06:
3756         case RTL_GIGA_MAC_VER_10:
3757         case RTL_GIGA_MAC_VER_11:
3758         case RTL_GIGA_MAC_VER_12:
3759         case RTL_GIGA_MAC_VER_13:
3760         case RTL_GIGA_MAC_VER_14:
3761         case RTL_GIGA_MAC_VER_15:
3762         case RTL_GIGA_MAC_VER_16:
3763         case RTL_GIGA_MAC_VER_17:
3764                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3765                 break;
3766         case RTL_GIGA_MAC_VER_18:
3767         case RTL_GIGA_MAC_VER_19:
3768         case RTL_GIGA_MAC_VER_20:
3769         case RTL_GIGA_MAC_VER_21:
3770         case RTL_GIGA_MAC_VER_22:
3771         case RTL_GIGA_MAC_VER_23:
3772         case RTL_GIGA_MAC_VER_24:
3773                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3774                 break;
3775         default:
3776                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3777                 break;
3778         }
3779 }
3780
3781 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3782 {
3783         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3784 }
3785
3786 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3787 {
3788         void __iomem *ioaddr = tp->mmio_addr;
3789
3790         RTL_W8(Cfg9346, Cfg9346_Unlock);
3791         rtl_generic_op(tp, tp->jumbo_ops.enable);
3792         RTL_W8(Cfg9346, Cfg9346_Lock);
3793 }
3794
3795 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3796 {
3797         void __iomem *ioaddr = tp->mmio_addr;
3798
3799         RTL_W8(Cfg9346, Cfg9346_Unlock);
3800         rtl_generic_op(tp, tp->jumbo_ops.disable);
3801         RTL_W8(Cfg9346, Cfg9346_Lock);
3802 }
3803
3804 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3805 {
3806         void __iomem *ioaddr = tp->mmio_addr;
3807
3808         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3809         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3810         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3811 }
3812
3813 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3814 {
3815         void __iomem *ioaddr = tp->mmio_addr;
3816
3817         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3818         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3819         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3820 }
3821
3822 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3823 {
3824         void __iomem *ioaddr = tp->mmio_addr;
3825
3826         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3827 }
3828
3829 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3830 {
3831         void __iomem *ioaddr = tp->mmio_addr;
3832
3833         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3834 }
3835
3836 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3837 {
3838         void __iomem *ioaddr = tp->mmio_addr;
3839         struct pci_dev *pdev = tp->pci_dev;
3840
3841         RTL_W8(MaxTxPacketSize, 0x3f);
3842         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3843         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
3844         pci_write_config_byte(pdev, 0x79, 0x20);
3845 }
3846
3847 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3848 {
3849         void __iomem *ioaddr = tp->mmio_addr;
3850         struct pci_dev *pdev = tp->pci_dev;
3851
3852         RTL_W8(MaxTxPacketSize, 0x0c);
3853         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3854         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
3855         pci_write_config_byte(pdev, 0x79, 0x50);
3856 }
3857
3858 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3859 {
3860         rtl_tx_performance_tweak(tp->pci_dev,
3861                 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3862 }
3863
3864 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3865 {
3866         rtl_tx_performance_tweak(tp->pci_dev,
3867                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3868 }
3869
3870 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3871 {
3872         void __iomem *ioaddr = tp->mmio_addr;
3873
3874         r8168b_0_hw_jumbo_enable(tp);
3875
3876         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3877 }
3878
3879 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3880 {
3881         void __iomem *ioaddr = tp->mmio_addr;
3882
3883         r8168b_0_hw_jumbo_disable(tp);
3884
3885         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3886 }
3887
3888 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3889 {
3890         struct jumbo_ops *ops = &tp->jumbo_ops;
3891
3892         switch (tp->mac_version) {
3893         case RTL_GIGA_MAC_VER_11:
3894                 ops->disable    = r8168b_0_hw_jumbo_disable;
3895                 ops->enable     = r8168b_0_hw_jumbo_enable;
3896                 break;
3897         case RTL_GIGA_MAC_VER_12:
3898         case RTL_GIGA_MAC_VER_17:
3899                 ops->disable    = r8168b_1_hw_jumbo_disable;
3900                 ops->enable     = r8168b_1_hw_jumbo_enable;
3901                 break;
3902         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3903         case RTL_GIGA_MAC_VER_19:
3904         case RTL_GIGA_MAC_VER_20:
3905         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3906         case RTL_GIGA_MAC_VER_22:
3907         case RTL_GIGA_MAC_VER_23:
3908         case RTL_GIGA_MAC_VER_24:
3909         case RTL_GIGA_MAC_VER_25:
3910         case RTL_GIGA_MAC_VER_26:
3911                 ops->disable    = r8168c_hw_jumbo_disable;
3912                 ops->enable     = r8168c_hw_jumbo_enable;
3913                 break;
3914         case RTL_GIGA_MAC_VER_27:
3915         case RTL_GIGA_MAC_VER_28:
3916                 ops->disable    = r8168dp_hw_jumbo_disable;
3917                 ops->enable     = r8168dp_hw_jumbo_enable;
3918                 break;
3919         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3920         case RTL_GIGA_MAC_VER_32:
3921         case RTL_GIGA_MAC_VER_33:
3922         case RTL_GIGA_MAC_VER_34:
3923                 ops->disable    = r8168e_hw_jumbo_disable;
3924                 ops->enable     = r8168e_hw_jumbo_enable;
3925                 break;
3926
3927         /*
3928          * No action needed for jumbo frames with 8169.
3929          * No jumbo for 810x at all.
3930          */
3931         default:
3932                 ops->disable    = NULL;
3933                 ops->enable     = NULL;
3934                 break;
3935         }
3936 }
3937
3938 static void rtl_hw_reset(struct rtl8169_private *tp)
3939 {
3940         void __iomem *ioaddr = tp->mmio_addr;
3941         int i;
3942
3943         /* Soft reset the chip. */
3944         RTL_W8(ChipCmd, CmdReset);
3945
3946         /* Check that the chip has finished the reset. */
3947         for (i = 0; i < 100; i++) {
3948                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3949                         break;
3950                 udelay(100);
3951         }
3952 }
3953
3954 static int __devinit
3955 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3956 {
3957         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3958         const unsigned int region = cfg->region;
3959         struct rtl8169_private *tp;
3960         struct mii_if_info *mii;
3961         struct net_device *dev;
3962         void __iomem *ioaddr;
3963         int chipset, i;
3964         int rc;
3965
3966         if (netif_msg_drv(&debug)) {
3967                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3968                        MODULENAME, RTL8169_VERSION);
3969         }
3970
3971         dev = alloc_etherdev(sizeof (*tp));
3972         if (!dev) {
3973                 if (netif_msg_drv(&debug))
3974                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3975                 rc = -ENOMEM;
3976                 goto out;
3977         }
3978
3979         SET_NETDEV_DEV(dev, &pdev->dev);
3980         dev->netdev_ops = &rtl8169_netdev_ops;
3981         tp = netdev_priv(dev);
3982         tp->dev = dev;
3983         tp->pci_dev = pdev;
3984         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3985
3986         mii = &tp->mii;
3987         mii->dev = dev;
3988         mii->mdio_read = rtl_mdio_read;
3989         mii->mdio_write = rtl_mdio_write;
3990         mii->phy_id_mask = 0x1f;
3991         mii->reg_num_mask = 0x1f;
3992         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3993
3994         /* disable ASPM completely as that cause random device stop working
3995          * problems as well as full system hangs for some PCIe devices users */
3996         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3997                                      PCIE_LINK_STATE_CLKPM);
3998
3999         /* enable device (incl. PCI PM wakeup and hotplug setup) */
4000         rc = pci_enable_device(pdev);
4001         if (rc < 0) {
4002                 netif_err(tp, probe, dev, "enable failure\n");
4003                 goto err_out_free_dev_1;
4004         }
4005
4006         if (pci_set_mwi(pdev) < 0)
4007                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
4008
4009         /* make sure PCI base addr 1 is MMIO */
4010         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4011                 netif_err(tp, probe, dev,
4012                           "region #%d not an MMIO resource, aborting\n",
4013                           region);
4014                 rc = -ENODEV;
4015                 goto err_out_mwi_2;
4016         }
4017
4018         /* check for weird/broken PCI region reporting */
4019         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4020                 netif_err(tp, probe, dev,
4021                           "Invalid PCI region size(s), aborting\n");
4022                 rc = -ENODEV;
4023                 goto err_out_mwi_2;
4024         }
4025
4026         rc = pci_request_regions(pdev, MODULENAME);
4027         if (rc < 0) {
4028                 netif_err(tp, probe, dev, "could not request regions\n");
4029                 goto err_out_mwi_2;
4030         }
4031
4032         tp->cp_cmd = RxChkSum;
4033
4034         if ((sizeof(dma_addr_t) > 4) &&
4035             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
4036                 tp->cp_cmd |= PCIDAC;
4037                 dev->features |= NETIF_F_HIGHDMA;
4038         } else {
4039                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4040                 if (rc < 0) {
4041                         netif_err(tp, probe, dev, "DMA configuration failed\n");
4042                         goto err_out_free_res_3;
4043                 }
4044         }
4045
4046         /* ioremap MMIO region */
4047         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4048         if (!ioaddr) {
4049                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
4050                 rc = -EIO;
4051                 goto err_out_free_res_3;
4052         }
4053         tp->mmio_addr = ioaddr;
4054
4055         if (!pci_is_pcie(pdev))
4056                 netif_info(tp, probe, dev, "not PCI Express\n");
4057
4058         /* Identify chip attached to board */
4059         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
4060
4061         rtl_init_rxcfg(tp);
4062
4063         RTL_W16(IntrMask, 0x0000);
4064
4065         rtl_hw_reset(tp);
4066
4067         RTL_W16(IntrStatus, 0xffff);
4068
4069         pci_set_master(pdev);
4070
4071         /*
4072          * Pretend we are using VLANs; This bypasses a nasty bug where
4073          * Interrupts stop flowing on high load on 8110SCd controllers.
4074          */
4075         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4076                 tp->cp_cmd |= RxVlan;
4077
4078         rtl_init_mdio_ops(tp);
4079         rtl_init_pll_power_ops(tp);
4080         rtl_init_jumbo_ops(tp);
4081
4082         rtl8169_print_mac_version(tp);
4083
4084         chipset = tp->mac_version;
4085         tp->txd_version = rtl_chip_infos[chipset].txd_version;
4086
4087         RTL_W8(Cfg9346, Cfg9346_Unlock);
4088         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
4089         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
4090         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
4091                 tp->features |= RTL_FEATURE_WOL;
4092         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
4093                 tp->features |= RTL_FEATURE_WOL;
4094         tp->features |= rtl_try_msi(tp, cfg);
4095         RTL_W8(Cfg9346, Cfg9346_Lock);
4096
4097         if (rtl_tbi_enabled(tp)) {
4098                 tp->set_speed = rtl8169_set_speed_tbi;
4099                 tp->get_settings = rtl8169_gset_tbi;
4100                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
4101                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
4102                 tp->link_ok = rtl8169_tbi_link_ok;
4103                 tp->do_ioctl = rtl_tbi_ioctl;
4104         } else {
4105                 tp->set_speed = rtl8169_set_speed_xmii;
4106                 tp->get_settings = rtl8169_gset_xmii;
4107                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
4108                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
4109                 tp->link_ok = rtl8169_xmii_link_ok;
4110                 tp->do_ioctl = rtl_xmii_ioctl;
4111         }
4112
4113         spin_lock_init(&tp->lock);
4114
4115         /* Get MAC address */
4116         for (i = 0; i < MAC_ADDR_LEN; i++)
4117                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
4118         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4119
4120         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
4121         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
4122         dev->irq = pdev->irq;
4123         dev->base_addr = (unsigned long) ioaddr;
4124
4125         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
4126
4127         /* don't enable SG, IP_CSUM and TSO by default - it might not work
4128          * properly for all devices */
4129         dev->features |= NETIF_F_RXCSUM |
4130                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4131
4132         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4133                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4134         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4135                 NETIF_F_HIGHDMA;
4136
4137         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4138                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
4139                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
4140
4141         tp->intr_mask = 0xffff;
4142         tp->hw_start = cfg->hw_start;
4143         tp->intr_event = cfg->intr_event;
4144         tp->napi_event = cfg->napi_event;
4145
4146         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
4147                 ~(RxBOVF | RxFOVF) : ~0;
4148
4149         init_timer(&tp->timer);
4150         tp->timer.data = (unsigned long) dev;
4151         tp->timer.function = rtl8169_phy_timer;
4152
4153         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
4154
4155         rc = register_netdev(dev);
4156         if (rc < 0)
4157                 goto err_out_msi_4;
4158
4159         pci_set_drvdata(pdev, dev);
4160
4161         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
4162                    rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
4163                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
4164         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
4165                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
4166                            "tx checksumming: %s]\n",
4167                            rtl_chip_infos[chipset].jumbo_max,
4168                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
4169         }
4170
4171         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4172             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4173             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4174                 rtl8168_driver_start(tp);
4175         }
4176
4177         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
4178
4179         if (pci_dev_run_wake(pdev))
4180                 pm_runtime_put_noidle(&pdev->dev);
4181
4182         netif_carrier_off(dev);
4183
4184 out:
4185         return rc;
4186
4187 err_out_msi_4:
4188         rtl_disable_msi(pdev, tp);
4189         iounmap(ioaddr);
4190 err_out_free_res_3:
4191         pci_release_regions(pdev);
4192 err_out_mwi_2:
4193         pci_clear_mwi(pdev);
4194         pci_disable_device(pdev);
4195 err_out_free_dev_1:
4196         free_netdev(dev);
4197         goto out;
4198 }
4199
4200 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
4201 {
4202         struct net_device *dev = pci_get_drvdata(pdev);
4203         struct rtl8169_private *tp = netdev_priv(dev);
4204
4205         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4206             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4207             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4208                 rtl8168_driver_stop(tp);
4209         }
4210
4211         cancel_delayed_work_sync(&tp->task);
4212
4213         unregister_netdev(dev);
4214
4215         rtl_release_firmware(tp);
4216
4217         if (pci_dev_run_wake(pdev))
4218                 pm_runtime_get_noresume(&pdev->dev);
4219
4220         /* restore original MAC address */
4221         rtl_rar_set(tp, dev->perm_addr);
4222
4223         rtl_disable_msi(pdev, tp);
4224         rtl8169_release_board(pdev, dev, tp->mmio_addr);
4225         pci_set_drvdata(pdev, NULL);
4226 }
4227
4228 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4229 {
4230         struct rtl_fw *rtl_fw;
4231         const char *name;
4232         int rc = -ENOMEM;
4233
4234         name = rtl_lookup_firmware_name(tp);
4235         if (!name)
4236                 goto out_no_firmware;
4237
4238         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4239         if (!rtl_fw)
4240                 goto err_warn;
4241
4242         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4243         if (rc < 0)
4244                 goto err_free;
4245
4246         rc = rtl_check_firmware(tp, rtl_fw);
4247         if (rc < 0)
4248                 goto err_release_firmware;
4249
4250         tp->rtl_fw = rtl_fw;
4251 out:
4252         return;
4253
4254 err_release_firmware:
4255         release_firmware(rtl_fw->fw);
4256 err_free:
4257         kfree(rtl_fw);
4258 err_warn:
4259         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4260                    name, rc);
4261 out_no_firmware:
4262         tp->rtl_fw = NULL;
4263         goto out;
4264 }
4265
4266 static void rtl_request_firmware(struct rtl8169_private *tp)
4267 {
4268         if (IS_ERR(tp->rtl_fw))
4269                 rtl_request_uncached_firmware(tp);
4270 }
4271
4272 static int rtl8169_open(struct net_device *dev)
4273 {
4274         struct rtl8169_private *tp = netdev_priv(dev);
4275         void __iomem *ioaddr = tp->mmio_addr;
4276         struct pci_dev *pdev = tp->pci_dev;
4277         int retval = -ENOMEM;
4278
4279         pm_runtime_get_sync(&pdev->dev);
4280
4281         /*
4282          * Rx and Tx desscriptors needs 256 bytes alignment.
4283          * dma_alloc_coherent provides more.
4284          */
4285         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4286                                              &tp->TxPhyAddr, GFP_KERNEL);
4287         if (!tp->TxDescArray)
4288                 goto err_pm_runtime_put;
4289
4290         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4291                                              &tp->RxPhyAddr, GFP_KERNEL);
4292         if (!tp->RxDescArray)
4293                 goto err_free_tx_0;
4294
4295         retval = rtl8169_init_ring(dev);
4296         if (retval < 0)
4297                 goto err_free_rx_1;
4298
4299         INIT_DELAYED_WORK(&tp->task, NULL);
4300
4301         smp_mb();
4302
4303         rtl_request_firmware(tp);
4304
4305         retval = request_irq(dev->irq, rtl8169_interrupt,
4306                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
4307                              dev->name, dev);
4308         if (retval < 0)
4309                 goto err_release_fw_2;
4310
4311         napi_enable(&tp->napi);
4312
4313         rtl8169_init_phy(dev, tp);
4314
4315         rtl8169_set_features(dev, dev->features);
4316
4317         rtl_pll_power_up(tp);
4318
4319         rtl_hw_start(dev);
4320
4321         tp->saved_wolopts = 0;
4322         pm_runtime_put_noidle(&pdev->dev);
4323
4324         rtl8169_check_link_status(dev, tp, ioaddr);
4325 out:
4326         return retval;
4327
4328 err_release_fw_2:
4329         rtl_release_firmware(tp);
4330         rtl8169_rx_clear(tp);
4331 err_free_rx_1:
4332         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4333                           tp->RxPhyAddr);
4334         tp->RxDescArray = NULL;
4335 err_free_tx_0:
4336         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4337                           tp->TxPhyAddr);
4338         tp->TxDescArray = NULL;
4339 err_pm_runtime_put:
4340         pm_runtime_put_noidle(&pdev->dev);
4341         goto out;
4342 }
4343
4344 static void rtl_rx_close(struct rtl8169_private *tp)
4345 {
4346         void __iomem *ioaddr = tp->mmio_addr;
4347
4348         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4349 }
4350
4351 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4352 {
4353         void __iomem *ioaddr = tp->mmio_addr;
4354
4355         /* Disable interrupts */
4356         rtl8169_irq_mask_and_ack(tp);
4357
4358         rtl_rx_close(tp);
4359
4360         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4361             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4362             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4363                 while (RTL_R8(TxPoll) & NPQ)
4364                         udelay(20);
4365         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4366                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4367                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
4368                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4369                 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
4370                         udelay(100);
4371         } else {
4372                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4373                 udelay(100);
4374         }
4375
4376         rtl_hw_reset(tp);
4377 }
4378
4379 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4380 {
4381         void __iomem *ioaddr = tp->mmio_addr;
4382
4383         /* Set DMA burst size and Interframe Gap Time */
4384         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4385                 (InterFrameGap << TxInterFrameGapShift));
4386 }
4387
4388 static void rtl_hw_start(struct net_device *dev)
4389 {
4390         struct rtl8169_private *tp = netdev_priv(dev);
4391
4392         tp->hw_start(dev);
4393
4394         netif_start_queue(dev);
4395 }
4396
4397 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4398                                          void __iomem *ioaddr)
4399 {
4400         /*
4401          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4402          * register to be written before TxDescAddrLow to work.
4403          * Switching from MMIO to I/O access fixes the issue as well.
4404          */
4405         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4406         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4407         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4408         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4409 }
4410
4411 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4412 {
4413         u16 cmd;
4414
4415         cmd = RTL_R16(CPlusCmd);
4416         RTL_W16(CPlusCmd, cmd);
4417         return cmd;
4418 }
4419
4420 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4421 {
4422         /* Low hurts. Let's disable the filtering. */
4423         RTL_W16(RxMaxSize, rx_buf_sz + 1);
4424 }
4425
4426 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4427 {
4428         static const struct rtl_cfg2_info {
4429                 u32 mac_version;
4430                 u32 clk;
4431                 u32 val;
4432         } cfg2_info [] = {
4433                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4434                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4435                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4436                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4437         };
4438         const struct rtl_cfg2_info *p = cfg2_info;
4439         unsigned int i;
4440         u32 clk;
4441
4442         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4443         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4444                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4445                         RTL_W32(0x7c, p->val);
4446                         break;
4447                 }
4448         }
4449 }
4450
4451 static void rtl_hw_start_8169(struct net_device *dev)
4452 {
4453         struct rtl8169_private *tp = netdev_priv(dev);
4454         void __iomem *ioaddr = tp->mmio_addr;
4455         struct pci_dev *pdev = tp->pci_dev;
4456
4457         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4458                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4459                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4460         }
4461
4462         RTL_W8(Cfg9346, Cfg9346_Unlock);
4463         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4464             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4465             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4466             tp->mac_version == RTL_GIGA_MAC_VER_04)
4467                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4468
4469         rtl_init_rxcfg(tp);
4470
4471         RTL_W8(EarlyTxThres, NoEarlyTx);
4472
4473         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4474
4475         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4476             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4477             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4478             tp->mac_version == RTL_GIGA_MAC_VER_04)
4479                 rtl_set_rx_tx_config_registers(tp);
4480
4481         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4482
4483         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4484             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4485                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4486                         "Bit-3 and bit-14 MUST be 1\n");
4487                 tp->cp_cmd |= (1 << 14);
4488         }
4489
4490         RTL_W16(CPlusCmd, tp->cp_cmd);
4491
4492         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4493
4494         /*
4495          * Undocumented corner. Supposedly:
4496          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4497          */
4498         RTL_W16(IntrMitigate, 0x0000);
4499
4500         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4501
4502         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4503             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4504             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4505             tp->mac_version != RTL_GIGA_MAC_VER_04) {
4506                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4507                 rtl_set_rx_tx_config_registers(tp);
4508         }
4509
4510         RTL_W8(Cfg9346, Cfg9346_Lock);
4511
4512         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4513         RTL_R8(IntrMask);
4514
4515         RTL_W32(RxMissed, 0);
4516
4517         rtl_set_rx_mode(dev);
4518
4519         /* no early-rx interrupts */
4520         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4521
4522         /* Enable all known interrupts by setting the interrupt mask. */
4523         RTL_W16(IntrMask, tp->intr_event);
4524 }
4525
4526 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4527 {
4528         u32 csi;
4529
4530         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4531         rtl_csi_write(ioaddr, 0x070c, csi | bits);
4532 }
4533
4534 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4535 {
4536         rtl_csi_access_enable(ioaddr, 0x17000000);
4537 }
4538
4539 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4540 {
4541         rtl_csi_access_enable(ioaddr, 0x27000000);
4542 }
4543
4544 struct ephy_info {
4545         unsigned int offset;
4546         u16 mask;
4547         u16 bits;
4548 };
4549
4550 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4551 {
4552         u16 w;
4553
4554         while (len-- > 0) {
4555                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4556                 rtl_ephy_write(ioaddr, e->offset, w);
4557                 e++;
4558         }
4559 }
4560
4561 static void rtl_disable_clock_request(struct pci_dev *pdev)
4562 {
4563         int cap = pci_pcie_cap(pdev);
4564
4565         if (cap) {
4566                 u16 ctl;
4567
4568                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4569                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4570                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4571         }
4572 }
4573
4574 static void rtl_enable_clock_request(struct pci_dev *pdev)
4575 {
4576         int cap = pci_pcie_cap(pdev);
4577
4578         if (cap) {
4579                 u16 ctl;
4580
4581                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4582                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4583                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4584         }
4585 }
4586
4587 #define R8168_CPCMD_QUIRK_MASK (\
4588         EnableBist | \
4589         Mac_dbgo_oe | \
4590         Force_half_dup | \
4591         Force_rxflow_en | \
4592         Force_txflow_en | \
4593         Cxpl_dbg_sel | \
4594         ASF | \
4595         PktCntrDisable | \
4596         Mac_dbgo_sel)
4597
4598 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4599 {
4600         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4601
4602         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4603
4604         rtl_tx_performance_tweak(pdev,
4605                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4606 }
4607
4608 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4609 {
4610         rtl_hw_start_8168bb(ioaddr, pdev);
4611
4612         RTL_W8(MaxTxPacketSize, TxPacketMax);
4613
4614         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4615 }
4616
4617 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4618 {
4619         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4620
4621         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4622
4623         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4624
4625         rtl_disable_clock_request(pdev);
4626
4627         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4628 }
4629
4630 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4631 {
4632         static const struct ephy_info e_info_8168cp[] = {
4633                 { 0x01, 0,      0x0001 },
4634                 { 0x02, 0x0800, 0x1000 },
4635                 { 0x03, 0,      0x0042 },
4636                 { 0x06, 0x0080, 0x0000 },
4637                 { 0x07, 0,      0x2000 }
4638         };
4639
4640         rtl_csi_access_enable_2(ioaddr);
4641
4642         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4643
4644         __rtl_hw_start_8168cp(ioaddr, pdev);
4645 }
4646
4647 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4648 {
4649         rtl_csi_access_enable_2(ioaddr);
4650
4651         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4652
4653         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4654
4655         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4656 }
4657
4658 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4659 {
4660         rtl_csi_access_enable_2(ioaddr);
4661
4662         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4663
4664         /* Magic. */
4665         RTL_W8(DBG_REG, 0x20);
4666
4667         RTL_W8(MaxTxPacketSize, TxPacketMax);
4668
4669         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4670
4671         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4672 }
4673
4674 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4675 {
4676         static const struct ephy_info e_info_8168c_1[] = {
4677                 { 0x02, 0x0800, 0x1000 },
4678                 { 0x03, 0,      0x0002 },
4679                 { 0x06, 0x0080, 0x0000 }
4680         };
4681
4682         rtl_csi_access_enable_2(ioaddr);
4683
4684         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4685
4686         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4687
4688         __rtl_hw_start_8168cp(ioaddr, pdev);
4689 }
4690
4691 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4692 {
4693         static const struct ephy_info e_info_8168c_2[] = {
4694                 { 0x01, 0,      0x0001 },
4695                 { 0x03, 0x0400, 0x0220 }
4696         };
4697
4698         rtl_csi_access_enable_2(ioaddr);
4699
4700         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4701
4702         __rtl_hw_start_8168cp(ioaddr, pdev);
4703 }
4704
4705 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4706 {
4707         rtl_hw_start_8168c_2(ioaddr, pdev);
4708 }
4709
4710 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4711 {
4712         rtl_csi_access_enable_2(ioaddr);
4713
4714         __rtl_hw_start_8168cp(ioaddr, pdev);
4715 }
4716
4717 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4718 {
4719         rtl_csi_access_enable_2(ioaddr);
4720
4721         rtl_disable_clock_request(pdev);
4722
4723         RTL_W8(MaxTxPacketSize, TxPacketMax);
4724
4725         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4726
4727         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4728 }
4729
4730 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4731 {
4732         rtl_csi_access_enable_1(ioaddr);
4733
4734         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4735
4736         RTL_W8(MaxTxPacketSize, TxPacketMax);
4737
4738         rtl_disable_clock_request(pdev);
4739 }
4740
4741 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4742 {
4743         static const struct ephy_info e_info_8168d_4[] = {
4744                 { 0x0b, ~0,     0x48 },
4745                 { 0x19, 0x20,   0x50 },
4746                 { 0x0c, ~0,     0x20 }
4747         };
4748         int i;
4749
4750         rtl_csi_access_enable_1(ioaddr);
4751
4752         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4753
4754         RTL_W8(MaxTxPacketSize, TxPacketMax);
4755
4756         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4757                 const struct ephy_info *e = e_info_8168d_4 + i;
4758                 u16 w;
4759
4760                 w = rtl_ephy_read(ioaddr, e->offset);
4761                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4762         }
4763
4764         rtl_enable_clock_request(pdev);
4765 }
4766
4767 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4768 {
4769         static const struct ephy_info e_info_8168e_1[] = {
4770                 { 0x00, 0x0200, 0x0100 },
4771                 { 0x00, 0x0000, 0x0004 },
4772                 { 0x06, 0x0002, 0x0001 },
4773                 { 0x06, 0x0000, 0x0030 },
4774                 { 0x07, 0x0000, 0x2000 },
4775                 { 0x00, 0x0000, 0x0020 },
4776                 { 0x03, 0x5800, 0x2000 },
4777                 { 0x03, 0x0000, 0x0001 },
4778                 { 0x01, 0x0800, 0x1000 },
4779                 { 0x07, 0x0000, 0x4000 },
4780                 { 0x1e, 0x0000, 0x2000 },
4781                 { 0x19, 0xffff, 0xfe6c },
4782                 { 0x0a, 0x0000, 0x0040 }
4783         };
4784
4785         rtl_csi_access_enable_2(ioaddr);
4786
4787         rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4788
4789         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4790
4791         RTL_W8(MaxTxPacketSize, TxPacketMax);
4792
4793         rtl_disable_clock_request(pdev);
4794
4795         /* Reset tx FIFO pointer */
4796         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4797         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4798
4799         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4800 }
4801
4802 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4803 {
4804         static const struct ephy_info e_info_8168e_2[] = {
4805                 { 0x09, 0x0000, 0x0080 },
4806                 { 0x19, 0x0000, 0x0224 }
4807         };
4808
4809         rtl_csi_access_enable_1(ioaddr);
4810
4811         rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4812
4813         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4814
4815         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4816         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4817         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4818         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4819         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4820         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4821         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4822         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4823                      ERIAR_EXGMAC);
4824
4825         RTL_W8(MaxTxPacketSize, EarlySize);
4826
4827         rtl_disable_clock_request(pdev);
4828
4829         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4830         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4831
4832         /* Adjust EEE LED frequency */
4833         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4834
4835         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4836         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4837         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4838 }
4839
4840 static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
4841 {
4842         static const struct ephy_info e_info_8168f_1[] = {
4843                 { 0x06, 0x00c0, 0x0020 },
4844                 { 0x08, 0x0001, 0x0002 },
4845                 { 0x09, 0x0000, 0x0080 },
4846                 { 0x19, 0x0000, 0x0224 }
4847         };
4848
4849         rtl_csi_access_enable_1(ioaddr);
4850
4851         rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4852
4853         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4854
4855         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4856         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4857         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4858         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4859         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4860         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4861         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4862         rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4863         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4864         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4865         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4866                      ERIAR_EXGMAC);
4867
4868         RTL_W8(MaxTxPacketSize, EarlySize);
4869
4870         rtl_disable_clock_request(pdev);
4871
4872         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4873         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4874
4875         /* Adjust EEE LED frequency */
4876         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4877
4878         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4879         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4880         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4881 }
4882
4883 static void rtl_hw_start_8168(struct net_device *dev)
4884 {
4885         struct rtl8169_private *tp = netdev_priv(dev);
4886         void __iomem *ioaddr = tp->mmio_addr;
4887         struct pci_dev *pdev = tp->pci_dev;
4888
4889         RTL_W8(Cfg9346, Cfg9346_Unlock);
4890
4891         RTL_W8(MaxTxPacketSize, TxPacketMax);
4892
4893         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4894
4895         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4896
4897         RTL_W16(CPlusCmd, tp->cp_cmd);
4898
4899         RTL_W16(IntrMitigate, 0x5151);
4900
4901         /* Work around for RxFIFO overflow. */
4902         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
4903                 tp->intr_event |= RxFIFOOver | PCSTimeout;
4904                 tp->intr_event &= ~RxOverflow;
4905         }
4906
4907         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4908
4909         rtl_set_rx_mode(dev);
4910
4911         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4912                 (InterFrameGap << TxInterFrameGapShift));
4913
4914         RTL_R8(IntrMask);
4915
4916         switch (tp->mac_version) {
4917         case RTL_GIGA_MAC_VER_11:
4918                 rtl_hw_start_8168bb(ioaddr, pdev);
4919                 break;
4920
4921         case RTL_GIGA_MAC_VER_12:
4922         case RTL_GIGA_MAC_VER_17:
4923                 rtl_hw_start_8168bef(ioaddr, pdev);
4924                 break;
4925
4926         case RTL_GIGA_MAC_VER_18:
4927                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4928                 break;
4929
4930         case RTL_GIGA_MAC_VER_19:
4931                 rtl_hw_start_8168c_1(ioaddr, pdev);
4932                 break;
4933
4934         case RTL_GIGA_MAC_VER_20:
4935                 rtl_hw_start_8168c_2(ioaddr, pdev);
4936                 break;
4937
4938         case RTL_GIGA_MAC_VER_21:
4939                 rtl_hw_start_8168c_3(ioaddr, pdev);
4940                 break;
4941
4942         case RTL_GIGA_MAC_VER_22:
4943                 rtl_hw_start_8168c_4(ioaddr, pdev);
4944                 break;
4945
4946         case RTL_GIGA_MAC_VER_23:
4947                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4948                 break;
4949
4950         case RTL_GIGA_MAC_VER_24:
4951                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4952                 break;
4953
4954         case RTL_GIGA_MAC_VER_25:
4955         case RTL_GIGA_MAC_VER_26:
4956         case RTL_GIGA_MAC_VER_27:
4957                 rtl_hw_start_8168d(ioaddr, pdev);
4958                 break;
4959
4960         case RTL_GIGA_MAC_VER_28:
4961                 rtl_hw_start_8168d_4(ioaddr, pdev);
4962                 break;
4963
4964         case RTL_GIGA_MAC_VER_31:
4965                 rtl_hw_start_8168dp(ioaddr, pdev);
4966                 break;
4967
4968         case RTL_GIGA_MAC_VER_32:
4969         case RTL_GIGA_MAC_VER_33:
4970                 rtl_hw_start_8168e_1(ioaddr, pdev);
4971                 break;
4972         case RTL_GIGA_MAC_VER_34:
4973                 rtl_hw_start_8168e_2(ioaddr, pdev);
4974                 break;
4975
4976         case RTL_GIGA_MAC_VER_35:
4977         case RTL_GIGA_MAC_VER_36:
4978                 rtl_hw_start_8168f_1(ioaddr, pdev);
4979                 break;
4980
4981         default:
4982                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4983                         dev->name, tp->mac_version);
4984                 break;
4985         }
4986
4987         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4988
4989         RTL_W8(Cfg9346, Cfg9346_Lock);
4990
4991         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4992
4993         RTL_W16(IntrMask, tp->intr_event);
4994 }
4995
4996 #define R810X_CPCMD_QUIRK_MASK (\
4997         EnableBist | \
4998         Mac_dbgo_oe | \
4999         Force_half_dup | \
5000         Force_rxflow_en | \
5001         Force_txflow_en | \
5002         Cxpl_dbg_sel | \
5003         ASF | \
5004         PktCntrDisable | \
5005         Mac_dbgo_sel)
5006
5007 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
5008 {
5009         static const struct ephy_info e_info_8102e_1[] = {
5010                 { 0x01, 0, 0x6e65 },
5011                 { 0x02, 0, 0x091f },
5012                 { 0x03, 0, 0xc2f9 },
5013                 { 0x06, 0, 0xafb5 },
5014                 { 0x07, 0, 0x0e00 },
5015                 { 0x19, 0, 0xec80 },
5016                 { 0x01, 0, 0x2e65 },
5017                 { 0x01, 0, 0x6e65 }
5018         };
5019         u8 cfg1;
5020
5021         rtl_csi_access_enable_2(ioaddr);
5022
5023         RTL_W8(DBG_REG, FIX_NAK_1);
5024
5025         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5026
5027         RTL_W8(Config1,
5028                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5029         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5030
5031         cfg1 = RTL_R8(Config1);
5032         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5033                 RTL_W8(Config1, cfg1 & ~LEDS0);
5034
5035         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5036 }
5037
5038 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
5039 {
5040         rtl_csi_access_enable_2(ioaddr);
5041
5042         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5043
5044         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5045         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5046 }
5047
5048 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
5049 {
5050         rtl_hw_start_8102e_2(ioaddr, pdev);
5051
5052         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
5053 }
5054
5055 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
5056 {
5057         static const struct ephy_info e_info_8105e_1[] = {
5058                 { 0x07, 0, 0x4000 },
5059                 { 0x19, 0, 0x0200 },
5060                 { 0x19, 0, 0x0020 },
5061                 { 0x1e, 0, 0x2000 },
5062                 { 0x03, 0, 0x0001 },
5063                 { 0x19, 0, 0x0100 },
5064                 { 0x19, 0, 0x0004 },
5065                 { 0x0a, 0, 0x0020 }
5066         };
5067
5068         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5069         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5070
5071         /* Disable Early Tally Counter */
5072         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5073
5074         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5075         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5076
5077         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5078 }
5079
5080 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
5081 {
5082         rtl_hw_start_8105e_1(ioaddr, pdev);
5083         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
5084 }
5085
5086 static void rtl_hw_start_8101(struct net_device *dev)
5087 {
5088         struct rtl8169_private *tp = netdev_priv(dev);
5089         void __iomem *ioaddr = tp->mmio_addr;
5090         struct pci_dev *pdev = tp->pci_dev;
5091
5092         if (tp->mac_version >= RTL_GIGA_MAC_VER_30) {
5093                 tp->intr_event &= ~RxFIFOOver;
5094                 tp->napi_event &= ~RxFIFOOver;
5095         }
5096
5097         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5098             tp->mac_version == RTL_GIGA_MAC_VER_16) {
5099                 int cap = pci_pcie_cap(pdev);
5100
5101                 if (cap) {
5102                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
5103                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
5104                 }
5105         }
5106
5107         RTL_W8(Cfg9346, Cfg9346_Unlock);
5108
5109         switch (tp->mac_version) {
5110         case RTL_GIGA_MAC_VER_07:
5111                 rtl_hw_start_8102e_1(ioaddr, pdev);
5112                 break;
5113
5114         case RTL_GIGA_MAC_VER_08:
5115                 rtl_hw_start_8102e_3(ioaddr, pdev);
5116                 break;
5117
5118         case RTL_GIGA_MAC_VER_09:
5119                 rtl_hw_start_8102e_2(ioaddr, pdev);
5120                 break;
5121
5122         case RTL_GIGA_MAC_VER_29:
5123                 rtl_hw_start_8105e_1(ioaddr, pdev);
5124                 break;
5125         case RTL_GIGA_MAC_VER_30:
5126                 rtl_hw_start_8105e_2(ioaddr, pdev);
5127                 break;
5128         }
5129
5130         RTL_W8(Cfg9346, Cfg9346_Lock);
5131
5132         RTL_W8(MaxTxPacketSize, TxPacketMax);
5133
5134         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5135
5136         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
5137         RTL_W16(CPlusCmd, tp->cp_cmd);
5138
5139         RTL_W16(IntrMitigate, 0x0000);
5140
5141         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5142
5143         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5144         rtl_set_rx_tx_config_registers(tp);
5145
5146         RTL_R8(IntrMask);
5147
5148         rtl_set_rx_mode(dev);
5149
5150         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5151
5152         RTL_W16(IntrMask, tp->intr_event);
5153 }
5154
5155 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5156 {
5157         struct rtl8169_private *tp = netdev_priv(dev);
5158
5159         if (new_mtu < ETH_ZLEN ||
5160             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
5161                 return -EINVAL;
5162
5163         if (new_mtu > ETH_DATA_LEN)
5164                 rtl_hw_jumbo_enable(tp);
5165         else
5166                 rtl_hw_jumbo_disable(tp);
5167
5168         dev->mtu = new_mtu;
5169         netdev_update_features(dev);
5170
5171         return 0;
5172 }
5173
5174 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5175 {
5176         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5177         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5178 }
5179
5180 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5181                                      void **data_buff, struct RxDesc *desc)
5182 {
5183         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
5184                          DMA_FROM_DEVICE);
5185
5186         kfree(*data_buff);
5187         *data_buff = NULL;
5188         rtl8169_make_unusable_by_asic(desc);
5189 }
5190
5191 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5192 {
5193         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5194
5195         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5196 }
5197
5198 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5199                                        u32 rx_buf_sz)
5200 {
5201         desc->addr = cpu_to_le64(mapping);
5202         wmb();
5203         rtl8169_mark_to_asic(desc, rx_buf_sz);
5204 }
5205
5206 static inline void *rtl8169_align(void *data)
5207 {
5208         return (void *)ALIGN((long)data, 16);
5209 }
5210
5211 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5212                                              struct RxDesc *desc)
5213 {
5214         void *data;
5215         dma_addr_t mapping;
5216         struct device *d = &tp->pci_dev->dev;
5217         struct net_device *dev = tp->dev;
5218         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
5219
5220         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5221         if (!data)
5222                 return NULL;
5223
5224         if (rtl8169_align(data) != data) {
5225                 kfree(data);
5226                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5227                 if (!data)
5228                         return NULL;
5229         }
5230
5231         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
5232                                  DMA_FROM_DEVICE);
5233         if (unlikely(dma_mapping_error(d, mapping))) {
5234                 if (net_ratelimit())
5235                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5236                 goto err_out;
5237         }
5238
5239         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
5240         return data;
5241
5242 err_out:
5243         kfree(data);
5244         return NULL;
5245 }
5246
5247 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5248 {
5249         unsigned int i;
5250
5251         for (i = 0; i < NUM_RX_DESC; i++) {
5252                 if (tp->Rx_databuff[i]) {
5253                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5254                                             tp->RxDescArray + i);
5255                 }
5256         }
5257 }
5258
5259 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5260 {
5261         desc->opts1 |= cpu_to_le32(RingEnd);
5262 }
5263
5264 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5265 {
5266         unsigned int i;
5267
5268         for (i = 0; i < NUM_RX_DESC; i++) {
5269                 void *data;
5270
5271                 if (tp->Rx_databuff[i])
5272                         continue;
5273
5274                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5275                 if (!data) {
5276                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5277                         goto err_out;
5278                 }
5279                 tp->Rx_databuff[i] = data;
5280         }
5281
5282         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5283         return 0;
5284
5285 err_out:
5286         rtl8169_rx_clear(tp);
5287         return -ENOMEM;
5288 }
5289
5290 static int rtl8169_init_ring(struct net_device *dev)
5291 {
5292         struct rtl8169_private *tp = netdev_priv(dev);
5293
5294         rtl8169_init_ring_indexes(tp);
5295
5296         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5297         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5298
5299         return rtl8169_rx_fill(tp);
5300 }
5301
5302 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5303                                  struct TxDesc *desc)
5304 {
5305         unsigned int len = tx_skb->len;
5306
5307         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5308
5309         desc->opts1 = 0x00;
5310         desc->opts2 = 0x00;
5311         desc->addr = 0x00;
5312         tx_skb->len = 0;
5313 }
5314
5315 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5316                                    unsigned int n)
5317 {
5318         unsigned int i;
5319
5320         for (i = 0; i < n; i++) {
5321                 unsigned int entry = (start + i) % NUM_TX_DESC;
5322                 struct ring_info *tx_skb = tp->tx_skb + entry;
5323                 unsigned int len = tx_skb->len;
5324
5325                 if (len) {
5326                         struct sk_buff *skb = tx_skb->skb;
5327
5328                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5329                                              tp->TxDescArray + entry);
5330                         if (skb) {
5331                                 tp->dev->stats.tx_dropped++;
5332                                 dev_kfree_skb(skb);
5333                                 tx_skb->skb = NULL;
5334                         }
5335                 }
5336         }
5337 }
5338
5339 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5340 {
5341         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5342         tp->cur_tx = tp->dirty_tx = 0;
5343 }
5344
5345 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
5346 {
5347         struct rtl8169_private *tp = netdev_priv(dev);
5348
5349         PREPARE_DELAYED_WORK(&tp->task, task);
5350         schedule_delayed_work(&tp->task, 4);
5351 }
5352
5353 static void rtl8169_wait_for_quiescence(struct net_device *dev)
5354 {
5355         struct rtl8169_private *tp = netdev_priv(dev);
5356         void __iomem *ioaddr = tp->mmio_addr;
5357
5358         synchronize_irq(dev->irq);
5359
5360         /* Wait for any pending NAPI task to complete */
5361         napi_disable(&tp->napi);
5362
5363         rtl8169_irq_mask_and_ack(tp);
5364
5365         tp->intr_mask = 0xffff;
5366         RTL_W16(IntrMask, tp->intr_event);
5367         napi_enable(&tp->napi);
5368 }
5369
5370 static void rtl8169_reinit_task(struct work_struct *work)
5371 {
5372         struct rtl8169_private *tp =
5373                 container_of(work, struct rtl8169_private, task.work);
5374         struct net_device *dev = tp->dev;
5375         int ret;
5376
5377         rtnl_lock();
5378
5379         if (!netif_running(dev))
5380                 goto out_unlock;
5381
5382         rtl8169_wait_for_quiescence(dev);
5383         rtl8169_close(dev);
5384
5385         ret = rtl8169_open(dev);
5386         if (unlikely(ret < 0)) {
5387                 if (net_ratelimit())
5388                         netif_err(tp, drv, dev,
5389                                   "reinit failure (status = %d). Rescheduling\n",
5390                                   ret);
5391                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
5392         }
5393
5394 out_unlock:
5395         rtnl_unlock();
5396 }
5397
5398 static void rtl8169_reset_task(struct work_struct *work)
5399 {
5400         struct rtl8169_private *tp =
5401                 container_of(work, struct rtl8169_private, task.work);
5402         struct net_device *dev = tp->dev;
5403         int i;
5404
5405         rtnl_lock();
5406
5407         if (!netif_running(dev))
5408                 goto out_unlock;
5409
5410         rtl8169_hw_reset(tp);
5411
5412         rtl8169_wait_for_quiescence(dev);
5413
5414         for (i = 0; i < NUM_RX_DESC; i++)
5415                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5416
5417         rtl8169_tx_clear(tp);
5418         rtl8169_init_ring_indexes(tp);
5419
5420         rtl_hw_start(dev);
5421         netif_wake_queue(dev);
5422         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5423
5424 out_unlock:
5425         rtnl_unlock();
5426 }
5427
5428 static void rtl8169_tx_timeout(struct net_device *dev)
5429 {
5430         rtl8169_schedule_work(dev, rtl8169_reset_task);
5431 }
5432
5433 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5434                               u32 *opts)
5435 {
5436         struct skb_shared_info *info = skb_shinfo(skb);
5437         unsigned int cur_frag, entry;
5438         struct TxDesc * uninitialized_var(txd);
5439         struct device *d = &tp->pci_dev->dev;
5440
5441         entry = tp->cur_tx;
5442         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5443                 const skb_frag_t *frag = info->frags + cur_frag;
5444                 dma_addr_t mapping;
5445                 u32 status, len;
5446                 void *addr;
5447
5448                 entry = (entry + 1) % NUM_TX_DESC;
5449
5450                 txd = tp->TxDescArray + entry;
5451                 len = skb_frag_size(frag);
5452                 addr = skb_frag_address(frag);
5453                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5454                 if (unlikely(dma_mapping_error(d, mapping))) {
5455                         if (net_ratelimit())
5456                                 netif_err(tp, drv, tp->dev,
5457                                           "Failed to map TX fragments DMA!\n");
5458                         goto err_out;
5459                 }
5460
5461                 /* Anti gcc 2.95.3 bugware (sic) */
5462                 status = opts[0] | len |
5463                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5464
5465                 txd->opts1 = cpu_to_le32(status);
5466                 txd->opts2 = cpu_to_le32(opts[1]);
5467                 txd->addr = cpu_to_le64(mapping);
5468
5469                 tp->tx_skb[entry].len = len;
5470         }
5471
5472         if (cur_frag) {
5473                 tp->tx_skb[entry].skb = skb;
5474                 txd->opts1 |= cpu_to_le32(LastFrag);
5475         }
5476
5477         return cur_frag;
5478
5479 err_out:
5480         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5481         return -EIO;
5482 }
5483
5484 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5485                                     struct sk_buff *skb, u32 *opts)
5486 {
5487         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5488         u32 mss = skb_shinfo(skb)->gso_size;
5489         int offset = info->opts_offset;
5490
5491         if (mss) {
5492                 opts[0] |= TD_LSO;
5493                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5494         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5495                 const struct iphdr *ip = ip_hdr(skb);
5496
5497                 if (ip->protocol == IPPROTO_TCP)
5498                         opts[offset] |= info->checksum.tcp;
5499                 else if (ip->protocol == IPPROTO_UDP)
5500                         opts[offset] |= info->checksum.udp;
5501                 else
5502                         WARN_ON_ONCE(1);
5503         }
5504 }
5505
5506 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5507                                       struct net_device *dev)
5508 {
5509         struct rtl8169_private *tp = netdev_priv(dev);
5510         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5511         struct TxDesc *txd = tp->TxDescArray + entry;
5512         void __iomem *ioaddr = tp->mmio_addr;
5513         struct device *d = &tp->pci_dev->dev;
5514         dma_addr_t mapping;
5515         u32 status, len;
5516         u32 opts[2];
5517         int frags;
5518
5519         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
5520                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5521                 goto err_stop_0;
5522         }
5523
5524         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5525                 goto err_stop_0;
5526
5527         len = skb_headlen(skb);
5528         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5529         if (unlikely(dma_mapping_error(d, mapping))) {
5530                 if (net_ratelimit())
5531                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5532                 goto err_dma_0;
5533         }
5534
5535         tp->tx_skb[entry].len = len;
5536         txd->addr = cpu_to_le64(mapping);
5537
5538         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5539         opts[0] = DescOwn;
5540
5541         rtl8169_tso_csum(tp, skb, opts);
5542
5543         frags = rtl8169_xmit_frags(tp, skb, opts);
5544         if (frags < 0)
5545                 goto err_dma_1;
5546         else if (frags)
5547                 opts[0] |= FirstFrag;
5548         else {
5549                 opts[0] |= FirstFrag | LastFrag;
5550                 tp->tx_skb[entry].skb = skb;
5551         }
5552
5553         txd->opts2 = cpu_to_le32(opts[1]);
5554
5555         wmb();
5556
5557         /* Anti gcc 2.95.3 bugware (sic) */
5558         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5559         txd->opts1 = cpu_to_le32(status);
5560
5561         tp->cur_tx += frags + 1;
5562
5563         wmb();
5564
5565         RTL_W8(TxPoll, NPQ);
5566
5567         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5568                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5569                  * not miss a ring update when it notices a stopped queue.
5570                  */
5571                 smp_wmb();
5572                 netif_stop_queue(dev);
5573                 /* Sync with rtl_tx:
5574                  * - publish queue status and cur_tx ring index (write barrier)
5575                  * - refresh dirty_tx ring index (read barrier).
5576                  * May the current thread have a pessimistic view of the ring
5577                  * status and forget to wake up queue, a racing rtl_tx thread
5578                  * can't.
5579                  */
5580                 smp_mb();
5581                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
5582                         netif_wake_queue(dev);
5583         }
5584
5585         return NETDEV_TX_OK;
5586
5587 err_dma_1:
5588         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5589 err_dma_0:
5590         dev_kfree_skb(skb);
5591         dev->stats.tx_dropped++;
5592         return NETDEV_TX_OK;
5593
5594 err_stop_0:
5595         netif_stop_queue(dev);
5596         dev->stats.tx_dropped++;
5597         return NETDEV_TX_BUSY;
5598 }
5599
5600 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5601 {
5602         struct rtl8169_private *tp = netdev_priv(dev);
5603         struct pci_dev *pdev = tp->pci_dev;
5604         u16 pci_status, pci_cmd;
5605
5606         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5607         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5608
5609         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5610                   pci_cmd, pci_status);
5611
5612         /*
5613          * The recovery sequence below admits a very elaborated explanation:
5614          * - it seems to work;
5615          * - I did not see what else could be done;
5616          * - it makes iop3xx happy.
5617          *
5618          * Feel free to adjust to your needs.
5619          */
5620         if (pdev->broken_parity_status)
5621                 pci_cmd &= ~PCI_COMMAND_PARITY;
5622         else
5623                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5624
5625         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5626
5627         pci_write_config_word(pdev, PCI_STATUS,
5628                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5629                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5630                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5631
5632         /* The infamous DAC f*ckup only happens at boot time */
5633         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5634                 void __iomem *ioaddr = tp->mmio_addr;
5635
5636                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5637                 tp->cp_cmd &= ~PCIDAC;
5638                 RTL_W16(CPlusCmd, tp->cp_cmd);
5639                 dev->features &= ~NETIF_F_HIGHDMA;
5640         }
5641
5642         rtl8169_hw_reset(tp);
5643
5644         rtl8169_schedule_work(dev, rtl8169_reinit_task);
5645 }
5646
5647 static void rtl8169_tx_interrupt(struct net_device *dev,
5648                                  struct rtl8169_private *tp,
5649                                  void __iomem *ioaddr)
5650 {
5651         unsigned int dirty_tx, tx_left;
5652
5653         dirty_tx = tp->dirty_tx;
5654         smp_rmb();
5655         tx_left = tp->cur_tx - dirty_tx;
5656
5657         while (tx_left > 0) {
5658                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5659                 struct ring_info *tx_skb = tp->tx_skb + entry;
5660                 u32 status;
5661
5662                 rmb();
5663                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5664                 if (status & DescOwn)
5665                         break;
5666
5667                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5668                                      tp->TxDescArray + entry);
5669                 if (status & LastFrag) {
5670                         dev->stats.tx_packets++;
5671                         dev->stats.tx_bytes += tx_skb->skb->len;
5672                         dev_kfree_skb(tx_skb->skb);
5673                         tx_skb->skb = NULL;
5674                 }
5675                 dirty_tx++;
5676                 tx_left--;
5677         }
5678
5679         if (tp->dirty_tx != dirty_tx) {
5680                 tp->dirty_tx = dirty_tx;
5681                 /* Sync with rtl8169_start_xmit:
5682                  * - publish dirty_tx ring index (write barrier)
5683                  * - refresh cur_tx ring index and queue status (read barrier)
5684                  * May the current thread miss the stopped queue condition,
5685                  * a racing xmit thread can only have a right view of the
5686                  * ring status.
5687                  */
5688                 smp_mb();
5689                 if (netif_queue_stopped(dev) &&
5690                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5691                         netif_wake_queue(dev);
5692                 }
5693                 /*
5694                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5695                  * too close. Let's kick an extra TxPoll request when a burst
5696                  * of start_xmit activity is detected (if it is not detected,
5697                  * it is slow enough). -- FR
5698                  */
5699                 if (tp->cur_tx != dirty_tx)
5700                         RTL_W8(TxPoll, NPQ);
5701         }
5702 }
5703
5704 static inline int rtl8169_fragmented_frame(u32 status)
5705 {
5706         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5707 }
5708
5709 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5710 {
5711         u32 status = opts1 & RxProtoMask;
5712
5713         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5714             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5715                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5716         else
5717                 skb_checksum_none_assert(skb);
5718 }
5719
5720 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5721                                            struct rtl8169_private *tp,
5722                                            int pkt_size,
5723                                            dma_addr_t addr)
5724 {
5725         struct sk_buff *skb;
5726         struct device *d = &tp->pci_dev->dev;
5727
5728         data = rtl8169_align(data);
5729         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5730         prefetch(data);
5731         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5732         if (skb)
5733                 memcpy(skb->data, data, pkt_size);
5734         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5735
5736         return skb;
5737 }
5738
5739 static int rtl8169_rx_interrupt(struct net_device *dev,
5740                                 struct rtl8169_private *tp,
5741                                 void __iomem *ioaddr, u32 budget)
5742 {
5743         unsigned int cur_rx, rx_left;
5744         unsigned int count;
5745
5746         cur_rx = tp->cur_rx;
5747         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5748         rx_left = min(rx_left, budget);
5749
5750         for (; rx_left > 0; rx_left--, cur_rx++) {
5751                 unsigned int entry = cur_rx % NUM_RX_DESC;
5752                 struct RxDesc *desc = tp->RxDescArray + entry;
5753                 u32 status;
5754
5755                 rmb();
5756                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5757
5758                 if (status & DescOwn)
5759                         break;
5760                 if (unlikely(status & RxRES)) {
5761                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5762                                    status);
5763                         dev->stats.rx_errors++;
5764                         if (status & (RxRWT | RxRUNT))
5765                                 dev->stats.rx_length_errors++;
5766                         if (status & RxCRC)
5767                                 dev->stats.rx_crc_errors++;
5768                         if (status & RxFOVF) {
5769                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
5770                                 dev->stats.rx_fifo_errors++;
5771                         }
5772                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5773                 } else {
5774                         struct sk_buff *skb;
5775                         dma_addr_t addr = le64_to_cpu(desc->addr);
5776                         int pkt_size = (status & 0x00003fff) - 4;
5777
5778                         /*
5779                          * The driver does not support incoming fragmented
5780                          * frames. They are seen as a symptom of over-mtu
5781                          * sized frames.
5782                          */
5783                         if (unlikely(rtl8169_fragmented_frame(status))) {
5784                                 dev->stats.rx_dropped++;
5785                                 dev->stats.rx_length_errors++;
5786                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
5787                                 continue;
5788                         }
5789
5790                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5791                                                   tp, pkt_size, addr);
5792                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5793                         if (!skb) {
5794                                 dev->stats.rx_dropped++;
5795                                 continue;
5796                         }
5797
5798                         rtl8169_rx_csum(skb, status);
5799                         skb_put(skb, pkt_size);
5800                         skb->protocol = eth_type_trans(skb, dev);
5801
5802                         rtl8169_rx_vlan_tag(desc, skb);
5803
5804                         napi_gro_receive(&tp->napi, skb);
5805
5806                         dev->stats.rx_bytes += pkt_size;
5807                         dev->stats.rx_packets++;
5808                 }
5809
5810                 /* Work around for AMD plateform. */
5811                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5812                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5813                         desc->opts2 = 0;
5814                         cur_rx++;
5815                 }
5816         }
5817
5818         count = cur_rx - tp->cur_rx;
5819         tp->cur_rx = cur_rx;
5820
5821         tp->dirty_rx += count;
5822
5823         return count;
5824 }
5825
5826 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5827 {
5828         struct net_device *dev = dev_instance;
5829         struct rtl8169_private *tp = netdev_priv(dev);
5830         void __iomem *ioaddr = tp->mmio_addr;
5831         int handled = 0;
5832         int status;
5833
5834         /* loop handling interrupts until we have no new ones or
5835          * we hit a invalid/hotplug case.
5836          */
5837         status = RTL_R16(IntrStatus);
5838         while (status && status != 0xffff) {
5839                 status &= tp->intr_event;
5840                 if (!status)
5841                         break;
5842
5843                 handled = 1;
5844
5845                 /* Handle all of the error cases first. These will reset
5846                  * the chip, so just exit the loop.
5847                  */
5848                 if (unlikely(!netif_running(dev))) {
5849                         rtl8169_hw_reset(tp);
5850                         break;
5851                 }
5852
5853                 if (unlikely(status & RxFIFOOver)) {
5854                         switch (tp->mac_version) {
5855                         /* Work around for rx fifo overflow */
5856                         case RTL_GIGA_MAC_VER_11:
5857                                 netif_stop_queue(dev);
5858                                 rtl8169_tx_timeout(dev);
5859                                 goto done;
5860                         default:
5861                                 break;
5862                         }
5863                 }
5864
5865                 if (unlikely(status & SYSErr)) {
5866                         rtl8169_pcierr_interrupt(dev);
5867                         break;
5868                 }
5869
5870                 if (status & LinkChg)
5871                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
5872
5873                 /* We need to see the lastest version of tp->intr_mask to
5874                  * avoid ignoring an MSI interrupt and having to wait for
5875                  * another event which may never come.
5876                  */
5877                 smp_rmb();
5878                 if (status & tp->intr_mask & tp->napi_event) {
5879                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5880                         tp->intr_mask = ~tp->napi_event;
5881
5882                         if (likely(napi_schedule_prep(&tp->napi)))
5883                                 __napi_schedule(&tp->napi);
5884                         else
5885                                 netif_info(tp, intr, dev,
5886                                            "interrupt %04x in poll\n", status);
5887                 }
5888
5889                 /* We only get a new MSI interrupt when all active irq
5890                  * sources on the chip have been acknowledged. So, ack
5891                  * everything we've seen and check if new sources have become
5892                  * active to avoid blocking all interrupts from the chip.
5893                  */
5894                 RTL_W16(IntrStatus,
5895                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
5896                 status = RTL_R16(IntrStatus);
5897         }
5898 done:
5899         return IRQ_RETVAL(handled);
5900 }
5901
5902 static int rtl8169_poll(struct napi_struct *napi, int budget)
5903 {
5904         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5905         struct net_device *dev = tp->dev;
5906         void __iomem *ioaddr = tp->mmio_addr;
5907         int work_done;
5908
5909         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5910         rtl8169_tx_interrupt(dev, tp, ioaddr);
5911
5912         if (work_done < budget) {
5913                 napi_complete(napi);
5914
5915                 /* We need for force the visibility of tp->intr_mask
5916                  * for other CPUs, as we can loose an MSI interrupt
5917                  * and potentially wait for a retransmit timeout if we don't.
5918                  * The posted write to IntrMask is safe, as it will
5919                  * eventually make it to the chip and we won't loose anything
5920                  * until it does.
5921                  */
5922                 tp->intr_mask = 0xffff;
5923                 wmb();
5924                 RTL_W16(IntrMask, tp->intr_event);
5925         }
5926
5927         return work_done;
5928 }
5929
5930 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5931 {
5932         struct rtl8169_private *tp = netdev_priv(dev);
5933
5934         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5935                 return;
5936
5937         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5938         RTL_W32(RxMissed, 0);
5939 }
5940
5941 static void rtl8169_down(struct net_device *dev)
5942 {
5943         struct rtl8169_private *tp = netdev_priv(dev);
5944         void __iomem *ioaddr = tp->mmio_addr;
5945
5946         del_timer_sync(&tp->timer);
5947
5948         netif_stop_queue(dev);
5949
5950         napi_disable(&tp->napi);
5951
5952         spin_lock_irq(&tp->lock);
5953
5954         rtl8169_hw_reset(tp);
5955         /*
5956          * At this point device interrupts can not be enabled in any function,
5957          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5958          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5959          */
5960         rtl8169_rx_missed(dev, ioaddr);
5961
5962         spin_unlock_irq(&tp->lock);
5963
5964         synchronize_irq(dev->irq);
5965
5966         /* Give a racing hard_start_xmit a few cycles to complete. */
5967         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
5968
5969         rtl8169_tx_clear(tp);
5970
5971         rtl8169_rx_clear(tp);
5972
5973         rtl_pll_power_down(tp);
5974 }
5975
5976 static int rtl8169_close(struct net_device *dev)
5977 {
5978         struct rtl8169_private *tp = netdev_priv(dev);
5979         struct pci_dev *pdev = tp->pci_dev;
5980
5981         pm_runtime_get_sync(&pdev->dev);
5982
5983         /* Update counters before going down */
5984         rtl8169_update_counters(dev);
5985
5986         rtl8169_down(dev);
5987
5988         free_irq(dev->irq, dev);
5989
5990         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5991                           tp->RxPhyAddr);
5992         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5993                           tp->TxPhyAddr);
5994         tp->TxDescArray = NULL;
5995         tp->RxDescArray = NULL;
5996
5997         pm_runtime_put_sync(&pdev->dev);
5998
5999         return 0;
6000 }
6001
6002 static void rtl_set_rx_mode(struct net_device *dev)
6003 {
6004         struct rtl8169_private *tp = netdev_priv(dev);
6005         void __iomem *ioaddr = tp->mmio_addr;
6006         unsigned long flags;
6007         u32 mc_filter[2];       /* Multicast hash filter */
6008         int rx_mode;
6009         u32 tmp = 0;
6010
6011         if (dev->flags & IFF_PROMISC) {
6012                 /* Unconditionally log net taps. */
6013                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
6014                 rx_mode =
6015                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
6016                     AcceptAllPhys;
6017                 mc_filter[1] = mc_filter[0] = 0xffffffff;
6018         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
6019                    (dev->flags & IFF_ALLMULTI)) {
6020                 /* Too many to filter perfectly -- accept all multicasts. */
6021                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
6022                 mc_filter[1] = mc_filter[0] = 0xffffffff;
6023         } else {
6024                 struct netdev_hw_addr *ha;
6025
6026                 rx_mode = AcceptBroadcast | AcceptMyPhys;
6027                 mc_filter[1] = mc_filter[0] = 0;
6028                 netdev_for_each_mc_addr(ha, dev) {
6029                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
6030                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
6031                         rx_mode |= AcceptMulticast;
6032                 }
6033         }
6034
6035         spin_lock_irqsave(&tp->lock, flags);
6036
6037         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
6038
6039         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
6040                 u32 data = mc_filter[0];
6041
6042                 mc_filter[0] = swab32(mc_filter[1]);
6043                 mc_filter[1] = swab32(data);
6044         }
6045
6046         RTL_W32(MAR0 + 4, mc_filter[1]);
6047         RTL_W32(MAR0 + 0, mc_filter[0]);
6048
6049         RTL_W32(RxConfig, tmp);
6050
6051         spin_unlock_irqrestore(&tp->lock, flags);
6052 }
6053
6054 /**
6055  *  rtl8169_get_stats - Get rtl8169 read/write statistics
6056  *  @dev: The Ethernet Device to get statistics for
6057  *
6058  *  Get TX/RX statistics for rtl8169
6059  */
6060 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
6061 {
6062         struct rtl8169_private *tp = netdev_priv(dev);
6063         void __iomem *ioaddr = tp->mmio_addr;
6064         unsigned long flags;
6065
6066         if (netif_running(dev)) {
6067                 spin_lock_irqsave(&tp->lock, flags);
6068                 rtl8169_rx_missed(dev, ioaddr);
6069                 spin_unlock_irqrestore(&tp->lock, flags);
6070         }
6071
6072         return &dev->stats;
6073 }
6074
6075 static void rtl8169_net_suspend(struct net_device *dev)
6076 {
6077         struct rtl8169_private *tp = netdev_priv(dev);
6078
6079         if (!netif_running(dev))
6080                 return;
6081
6082         rtl_pll_power_down(tp);
6083
6084         netif_device_detach(dev);
6085         netif_stop_queue(dev);
6086 }
6087
6088 #ifdef CONFIG_PM
6089
6090 static int rtl8169_suspend(struct device *device)
6091 {
6092         struct pci_dev *pdev = to_pci_dev(device);
6093         struct net_device *dev = pci_get_drvdata(pdev);
6094
6095         rtl8169_net_suspend(dev);
6096
6097         return 0;
6098 }
6099
6100 static void __rtl8169_resume(struct net_device *dev)
6101 {
6102         struct rtl8169_private *tp = netdev_priv(dev);
6103
6104         netif_device_attach(dev);
6105
6106         rtl_pll_power_up(tp);
6107
6108         rtl8169_schedule_work(dev, rtl8169_reset_task);
6109 }
6110
6111 static int rtl8169_resume(struct device *device)
6112 {
6113         struct pci_dev *pdev = to_pci_dev(device);
6114         struct net_device *dev = pci_get_drvdata(pdev);
6115         struct rtl8169_private *tp = netdev_priv(dev);
6116
6117         rtl8169_init_phy(dev, tp);
6118
6119         if (netif_running(dev))
6120                 __rtl8169_resume(dev);
6121
6122         return 0;
6123 }
6124
6125 static int rtl8169_runtime_suspend(struct device *device)
6126 {
6127         struct pci_dev *pdev = to_pci_dev(device);
6128         struct net_device *dev = pci_get_drvdata(pdev);
6129         struct rtl8169_private *tp = netdev_priv(dev);
6130
6131         if (!tp->TxDescArray)
6132                 return 0;
6133
6134         spin_lock_irq(&tp->lock);
6135         tp->saved_wolopts = __rtl8169_get_wol(tp);
6136         __rtl8169_set_wol(tp, WAKE_ANY);
6137         spin_unlock_irq(&tp->lock);
6138
6139         rtl8169_net_suspend(dev);
6140
6141         return 0;
6142 }
6143
6144 static int rtl8169_runtime_resume(struct device *device)
6145 {
6146         struct pci_dev *pdev = to_pci_dev(device);
6147         struct net_device *dev = pci_get_drvdata(pdev);
6148         struct rtl8169_private *tp = netdev_priv(dev);
6149
6150         if (!tp->TxDescArray)
6151                 return 0;
6152
6153         spin_lock_irq(&tp->lock);
6154         __rtl8169_set_wol(tp, tp->saved_wolopts);
6155         tp->saved_wolopts = 0;
6156         spin_unlock_irq(&tp->lock);
6157
6158         rtl8169_init_phy(dev, tp);
6159
6160         __rtl8169_resume(dev);
6161
6162         return 0;
6163 }
6164
6165 static int rtl8169_runtime_idle(struct device *device)
6166 {
6167         struct pci_dev *pdev = to_pci_dev(device);
6168         struct net_device *dev = pci_get_drvdata(pdev);
6169         struct rtl8169_private *tp = netdev_priv(dev);
6170
6171         return tp->TxDescArray ? -EBUSY : 0;
6172 }
6173
6174 static const struct dev_pm_ops rtl8169_pm_ops = {
6175         .suspend                = rtl8169_suspend,
6176         .resume                 = rtl8169_resume,
6177         .freeze                 = rtl8169_suspend,
6178         .thaw                   = rtl8169_resume,
6179         .poweroff               = rtl8169_suspend,
6180         .restore                = rtl8169_resume,
6181         .runtime_suspend        = rtl8169_runtime_suspend,
6182         .runtime_resume         = rtl8169_runtime_resume,
6183         .runtime_idle           = rtl8169_runtime_idle,
6184 };
6185
6186 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6187
6188 #else /* !CONFIG_PM */
6189
6190 #define RTL8169_PM_OPS  NULL
6191
6192 #endif /* !CONFIG_PM */
6193
6194 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6195 {
6196         void __iomem *ioaddr = tp->mmio_addr;
6197
6198         /* WoL fails with 8168b when the receiver is disabled. */
6199         switch (tp->mac_version) {
6200         case RTL_GIGA_MAC_VER_11:
6201         case RTL_GIGA_MAC_VER_12:
6202         case RTL_GIGA_MAC_VER_17:
6203                 pci_clear_master(tp->pci_dev);
6204
6205                 RTL_W8(ChipCmd, CmdRxEnb);
6206                 /* PCI commit */
6207                 RTL_R8(ChipCmd);
6208                 break;
6209         default:
6210                 break;
6211         }
6212 }
6213
6214 static void rtl_shutdown(struct pci_dev *pdev)
6215 {
6216         struct net_device *dev = pci_get_drvdata(pdev);
6217         struct rtl8169_private *tp = netdev_priv(dev);
6218         struct device *d = &pdev->dev;
6219
6220         pm_runtime_get_sync(d);
6221
6222         rtl8169_net_suspend(dev);
6223
6224         /* Restore original MAC address */
6225         rtl_rar_set(tp, dev->perm_addr);
6226
6227         spin_lock_irq(&tp->lock);
6228
6229         rtl8169_hw_reset(tp);
6230
6231         spin_unlock_irq(&tp->lock);
6232
6233         if (system_state == SYSTEM_POWER_OFF) {
6234                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6235                         rtl_wol_suspend_quirk(tp);
6236                         rtl_wol_shutdown_quirk(tp);
6237                 }
6238
6239                 pci_wake_from_d3(pdev, true);
6240                 pci_set_power_state(pdev, PCI_D3hot);
6241         }
6242
6243         pm_runtime_put_noidle(d);
6244 }
6245
6246 static struct pci_driver rtl8169_pci_driver = {
6247         .name           = MODULENAME,
6248         .id_table       = rtl8169_pci_tbl,
6249         .probe          = rtl8169_init_one,
6250         .remove         = __devexit_p(rtl8169_remove_one),
6251         .shutdown       = rtl_shutdown,
6252         .driver.pm      = RTL8169_PM_OPS,
6253 };
6254
6255 static int __init rtl8169_init_module(void)
6256 {
6257         return pci_register_driver(&rtl8169_pci_driver);
6258 }
6259
6260 static void __exit rtl8169_cleanup_module(void)
6261 {
6262         pci_unregister_driver(&rtl8169_pci_driver);
6263 }
6264
6265 module_init(rtl8169_init_module);
6266 module_exit(rtl8169_cleanup_module);