2 * RDC R6040 Fast Ethernet MAC support
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7 * Florian Fainelli <florian@openwrt.org>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/string.h>
29 #include <linux/timer.h>
30 #include <linux/errno.h>
31 #include <linux/ioport.h>
32 #include <linux/interrupt.h>
33 #include <linux/pci.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/mii.h>
40 #include <linux/ethtool.h>
41 #include <linux/crc32.h>
42 #include <linux/spinlock.h>
43 #include <linux/bitops.h>
45 #include <linux/irq.h>
46 #include <linux/uaccess.h>
47 #include <linux/phy.h>
49 #include <asm/processor.h>
51 #define DRV_NAME "r6040"
52 #define DRV_VERSION "0.28"
53 #define DRV_RELDATE "07Oct2011"
55 /* Time in jiffies before concluding the transmitter is hung. */
56 #define TX_TIMEOUT (6000 * HZ / 1000)
58 /* RDC MAC I/O Size */
59 #define R6040_IO_SIZE 256
65 #define MCR0 0x00 /* Control register 0 */
66 #define MCR0_RCVEN 0x0002 /* Receive enable */
67 #define MCR0_PROMISC 0x0020 /* Promiscuous mode */
68 #define MCR0_HASH_EN 0x0100 /* Enable multicast hash table function */
69 #define MCR0_XMTEN 0x1000 /* Transmission enable */
70 #define MCR0_FD 0x8000 /* Full/Half duplex */
71 #define MCR1 0x04 /* Control register 1 */
72 #define MAC_RST 0x0001 /* Reset the MAC */
73 #define MBCR 0x08 /* Bus control */
74 #define MT_ICR 0x0C /* TX interrupt control */
75 #define MR_ICR 0x10 /* RX interrupt control */
76 #define MTPR 0x14 /* TX poll command register */
77 #define MR_BSR 0x18 /* RX buffer size */
78 #define MR_DCR 0x1A /* RX descriptor control */
79 #define MLSR 0x1C /* Last status */
80 #define MMDIO 0x20 /* MDIO control register */
81 #define MDIO_WRITE 0x4000 /* MDIO write */
82 #define MDIO_READ 0x2000 /* MDIO read */
83 #define MMRD 0x24 /* MDIO read data register */
84 #define MMWD 0x28 /* MDIO write data register */
85 #define MTD_SA0 0x2C /* TX descriptor start address 0 */
86 #define MTD_SA1 0x30 /* TX descriptor start address 1 */
87 #define MRD_SA0 0x34 /* RX descriptor start address 0 */
88 #define MRD_SA1 0x38 /* RX descriptor start address 1 */
89 #define MISR 0x3C /* Status register */
90 #define MIER 0x40 /* INT enable register */
91 #define MSK_INT 0x0000 /* Mask off interrupts */
92 #define RX_FINISH 0x0001 /* RX finished */
93 #define RX_NO_DESC 0x0002 /* No RX descriptor available */
94 #define RX_FIFO_FULL 0x0004 /* RX FIFO full */
95 #define RX_EARLY 0x0008 /* RX early */
96 #define TX_FINISH 0x0010 /* TX finished */
97 #define TX_EARLY 0x0080 /* TX early */
98 #define EVENT_OVRFL 0x0100 /* Event counter overflow */
99 #define LINK_CHANGED 0x0200 /* PHY link changed */
100 #define ME_CISR 0x44 /* Event counter INT status */
101 #define ME_CIER 0x48 /* Event counter INT enable */
102 #define MR_CNT 0x50 /* Successfully received packet counter */
103 #define ME_CNT0 0x52 /* Event counter 0 */
104 #define ME_CNT1 0x54 /* Event counter 1 */
105 #define ME_CNT2 0x56 /* Event counter 2 */
106 #define ME_CNT3 0x58 /* Event counter 3 */
107 #define MT_CNT 0x5A /* Successfully transmit packet counter */
108 #define ME_CNT4 0x5C /* Event counter 4 */
109 #define MP_CNT 0x5E /* Pause frame counter register */
110 #define MAR0 0x60 /* Hash table 0 */
111 #define MAR1 0x62 /* Hash table 1 */
112 #define MAR2 0x64 /* Hash table 2 */
113 #define MAR3 0x66 /* Hash table 3 */
114 #define MID_0L 0x68 /* Multicast address MID0 Low */
115 #define MID_0M 0x6A /* Multicast address MID0 Medium */
116 #define MID_0H 0x6C /* Multicast address MID0 High */
117 #define MID_1L 0x70 /* MID1 Low */
118 #define MID_1M 0x72 /* MID1 Medium */
119 #define MID_1H 0x74 /* MID1 High */
120 #define MID_2L 0x78 /* MID2 Low */
121 #define MID_2M 0x7A /* MID2 Medium */
122 #define MID_2H 0x7C /* MID2 High */
123 #define MID_3L 0x80 /* MID3 Low */
124 #define MID_3M 0x82 /* MID3 Medium */
125 #define MID_3H 0x84 /* MID3 High */
126 #define PHY_CC 0x88 /* PHY status change configuration register */
127 #define PHY_ST 0x8A /* PHY status register */
128 #define MAC_SM 0xAC /* MAC status machine */
129 #define MAC_ID 0xBE /* Identifier register */
131 #define TX_DCNT 0x80 /* TX descriptor count */
132 #define RX_DCNT 0x80 /* RX descriptor count */
133 #define MAX_BUF_SIZE 0x600
134 #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
135 #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
136 #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
137 #define MCAST_MAX 3 /* Max number multicast addresses to filter */
139 /* Descriptor status */
140 #define DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */
141 #define DSC_RX_OK 0x4000 /* RX was successful */
142 #define DSC_RX_ERR 0x0800 /* RX PHY error */
143 #define DSC_RX_ERR_DRI 0x0400 /* RX dribble packet */
144 #define DSC_RX_ERR_BUF 0x0200 /* RX length exceeds buffer size */
145 #define DSC_RX_ERR_LONG 0x0100 /* RX length > maximum packet length */
146 #define DSC_RX_ERR_RUNT 0x0080 /* RX packet length < 64 byte */
147 #define DSC_RX_ERR_CRC 0x0040 /* RX CRC error */
148 #define DSC_RX_BCAST 0x0020 /* RX broadcast (no error) */
149 #define DSC_RX_MCAST 0x0010 /* RX multicast (no error) */
150 #define DSC_RX_MCH_HIT 0x0008 /* RX multicast hit in hash table (no error) */
151 #define DSC_RX_MIDH_HIT 0x0004 /* RX MID table hit (no error) */
152 #define DSC_RX_IDX_MID_MASK 3 /* RX mask for the index of matched MIDx */
154 MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
155 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
156 "Florian Fainelli <florian@openwrt.org>");
157 MODULE_LICENSE("GPL");
158 MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
159 MODULE_VERSION(DRV_VERSION " " DRV_RELDATE);
161 /* RX and TX interrupts that we handle */
162 #define RX_INTS (RX_FIFO_FULL | RX_NO_DESC | RX_FINISH)
163 #define TX_INTS (TX_FINISH)
164 #define INT_MASK (RX_INTS | TX_INTS)
166 struct r6040_descriptor {
167 u16 status, len; /* 0-3 */
168 __le32 buf; /* 4-7 */
169 __le32 ndesc; /* 8-B */
171 char *vbufp; /* 10-13 */
172 struct r6040_descriptor *vndescp; /* 14-17 */
173 struct sk_buff *skb_ptr; /* 18-1B */
174 u32 rev2; /* 1C-1F */
175 } __attribute__((aligned(32)));
177 struct r6040_private {
178 spinlock_t lock; /* driver lock */
179 struct pci_dev *pdev;
180 struct r6040_descriptor *rx_insert_ptr;
181 struct r6040_descriptor *rx_remove_ptr;
182 struct r6040_descriptor *tx_insert_ptr;
183 struct r6040_descriptor *tx_remove_ptr;
184 struct r6040_descriptor *rx_ring;
185 struct r6040_descriptor *tx_ring;
186 dma_addr_t rx_ring_dma;
187 dma_addr_t tx_ring_dma;
190 struct net_device *dev;
191 struct mii_bus *mii_bus;
192 struct napi_struct napi;
194 struct phy_device *phydev;
199 static char version[] __devinitdata = DRV_NAME
200 ": RDC R6040 NAPI net driver,"
201 "version "DRV_VERSION " (" DRV_RELDATE ")";
203 /* Read a word data from PHY Chip */
204 static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg)
209 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
210 /* Wait for the read bit to be cleared */
212 cmd = ioread16(ioaddr + MMDIO);
213 if (!(cmd & MDIO_READ))
217 return ioread16(ioaddr + MMRD);
220 /* Write a word data from PHY Chip */
221 static void r6040_phy_write(void __iomem *ioaddr,
222 int phy_addr, int reg, u16 val)
227 iowrite16(val, ioaddr + MMWD);
228 /* Write the command to the MDIO bus */
229 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
230 /* Wait for the write bit to be cleared */
232 cmd = ioread16(ioaddr + MMDIO);
233 if (!(cmd & MDIO_WRITE))
238 static int r6040_mdiobus_read(struct mii_bus *bus, int phy_addr, int reg)
240 struct net_device *dev = bus->priv;
241 struct r6040_private *lp = netdev_priv(dev);
242 void __iomem *ioaddr = lp->base;
244 return r6040_phy_read(ioaddr, phy_addr, reg);
247 static int r6040_mdiobus_write(struct mii_bus *bus, int phy_addr,
250 struct net_device *dev = bus->priv;
251 struct r6040_private *lp = netdev_priv(dev);
252 void __iomem *ioaddr = lp->base;
254 r6040_phy_write(ioaddr, phy_addr, reg, value);
259 static int r6040_mdiobus_reset(struct mii_bus *bus)
264 static void r6040_free_txbufs(struct net_device *dev)
266 struct r6040_private *lp = netdev_priv(dev);
269 for (i = 0; i < TX_DCNT; i++) {
270 if (lp->tx_insert_ptr->skb_ptr) {
271 pci_unmap_single(lp->pdev,
272 le32_to_cpu(lp->tx_insert_ptr->buf),
273 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
274 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
275 lp->tx_insert_ptr->skb_ptr = NULL;
277 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
281 static void r6040_free_rxbufs(struct net_device *dev)
283 struct r6040_private *lp = netdev_priv(dev);
286 for (i = 0; i < RX_DCNT; i++) {
287 if (lp->rx_insert_ptr->skb_ptr) {
288 pci_unmap_single(lp->pdev,
289 le32_to_cpu(lp->rx_insert_ptr->buf),
290 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
291 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
292 lp->rx_insert_ptr->skb_ptr = NULL;
294 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
298 static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
299 dma_addr_t desc_dma, int size)
301 struct r6040_descriptor *desc = desc_ring;
302 dma_addr_t mapping = desc_dma;
305 mapping += sizeof(*desc);
306 desc->ndesc = cpu_to_le32(mapping);
307 desc->vndescp = desc + 1;
311 desc->ndesc = cpu_to_le32(desc_dma);
312 desc->vndescp = desc_ring;
315 static void r6040_init_txbufs(struct net_device *dev)
317 struct r6040_private *lp = netdev_priv(dev);
319 lp->tx_free_desc = TX_DCNT;
321 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
322 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
325 static int r6040_alloc_rxbufs(struct net_device *dev)
327 struct r6040_private *lp = netdev_priv(dev);
328 struct r6040_descriptor *desc;
332 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
333 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
335 /* Allocate skbs for the rx descriptors */
338 skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
340 netdev_err(dev, "failed to alloc skb for rx\n");
345 desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
347 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
348 desc->status = DSC_OWNER_MAC;
349 desc = desc->vndescp;
350 } while (desc != lp->rx_ring);
355 /* Deallocate all previously allocated skbs */
356 r6040_free_rxbufs(dev);
360 static void r6040_init_mac_regs(struct net_device *dev)
362 struct r6040_private *lp = netdev_priv(dev);
363 void __iomem *ioaddr = lp->base;
367 /* Mask Off Interrupt */
368 iowrite16(MSK_INT, ioaddr + MIER);
371 iowrite16(MAC_RST, ioaddr + MCR1);
373 cmd = ioread16(ioaddr + MCR1);
377 /* Reset internal state machine */
378 iowrite16(2, ioaddr + MAC_SM);
379 iowrite16(0, ioaddr + MAC_SM);
382 /* MAC Bus Control Register */
383 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
385 /* Buffer Size Register */
386 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
388 /* Write TX ring start address */
389 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
390 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
392 /* Write RX ring start address */
393 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
394 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
396 /* Set interrupt waiting time and packet numbers */
397 iowrite16(0, ioaddr + MT_ICR);
398 iowrite16(0, ioaddr + MR_ICR);
400 /* Enable interrupts */
401 iowrite16(INT_MASK, ioaddr + MIER);
403 /* Enable TX and RX */
404 iowrite16(lp->mcr0 | MCR0_RCVEN, ioaddr);
406 /* Let TX poll the descriptors
407 * we may got called by r6040_tx_timeout which has left
408 * some unsent tx buffers */
409 iowrite16(0x01, ioaddr + MTPR);
412 static void r6040_tx_timeout(struct net_device *dev)
414 struct r6040_private *priv = netdev_priv(dev);
415 void __iomem *ioaddr = priv->base;
417 netdev_warn(dev, "transmit timed out, int enable %4.4x "
419 ioread16(ioaddr + MIER),
420 ioread16(ioaddr + MISR));
422 dev->stats.tx_errors++;
424 /* Reset MAC and re-init all registers */
425 r6040_init_mac_regs(dev);
428 static struct net_device_stats *r6040_get_stats(struct net_device *dev)
430 struct r6040_private *priv = netdev_priv(dev);
431 void __iomem *ioaddr = priv->base;
434 spin_lock_irqsave(&priv->lock, flags);
435 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
436 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
437 spin_unlock_irqrestore(&priv->lock, flags);
442 /* Stop RDC MAC and Free the allocated resource */
443 static void r6040_down(struct net_device *dev)
445 struct r6040_private *lp = netdev_priv(dev);
446 void __iomem *ioaddr = lp->base;
452 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
453 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
455 cmd = ioread16(ioaddr + MCR1);
460 /* Restore MAC Address to MIDx */
461 adrp = (u16 *) dev->dev_addr;
462 iowrite16(adrp[0], ioaddr + MID_0L);
463 iowrite16(adrp[1], ioaddr + MID_0M);
464 iowrite16(adrp[2], ioaddr + MID_0H);
466 phy_stop(lp->phydev);
469 static int r6040_close(struct net_device *dev)
471 struct r6040_private *lp = netdev_priv(dev);
472 struct pci_dev *pdev = lp->pdev;
474 spin_lock_irq(&lp->lock);
475 napi_disable(&lp->napi);
476 netif_stop_queue(dev);
479 free_irq(dev->irq, dev);
482 r6040_free_rxbufs(dev);
485 r6040_free_txbufs(dev);
487 spin_unlock_irq(&lp->lock);
489 /* Free Descriptor memory */
491 pci_free_consistent(pdev,
492 RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
497 pci_free_consistent(pdev,
498 TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
505 static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
507 struct r6040_private *lp = netdev_priv(dev);
512 return phy_mii_ioctl(lp->phydev, rq, cmd);
515 static int r6040_rx(struct net_device *dev, int limit)
517 struct r6040_private *priv = netdev_priv(dev);
518 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
519 struct sk_buff *skb_ptr, *new_skb;
523 /* Limit not reached and the descriptor belongs to the CPU */
524 while (count < limit && !(descptr->status & DSC_OWNER_MAC)) {
525 /* Read the descriptor status */
526 err = descptr->status;
527 /* Global error status set */
528 if (err & DSC_RX_ERR) {
530 if (err & DSC_RX_ERR_DRI)
531 dev->stats.rx_frame_errors++;
532 /* Buffer length exceeded */
533 if (err & DSC_RX_ERR_BUF)
534 dev->stats.rx_length_errors++;
535 /* Packet too long */
536 if (err & DSC_RX_ERR_LONG)
537 dev->stats.rx_length_errors++;
538 /* Packet < 64 bytes */
539 if (err & DSC_RX_ERR_RUNT)
540 dev->stats.rx_length_errors++;
542 if (err & DSC_RX_ERR_CRC) {
543 spin_lock(&priv->lock);
544 dev->stats.rx_crc_errors++;
545 spin_unlock(&priv->lock);
550 /* Packet successfully received */
551 new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
553 dev->stats.rx_dropped++;
556 skb_ptr = descptr->skb_ptr;
557 skb_ptr->dev = priv->dev;
559 /* Do not count the CRC */
560 skb_put(skb_ptr, descptr->len - 4);
561 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
562 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
563 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
565 /* Send to upper layer */
566 netif_receive_skb(skb_ptr);
567 dev->stats.rx_packets++;
568 dev->stats.rx_bytes += descptr->len - 4;
570 /* put new skb into descriptor */
571 descptr->skb_ptr = new_skb;
572 descptr->buf = cpu_to_le32(pci_map_single(priv->pdev,
573 descptr->skb_ptr->data,
574 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
577 /* put the descriptor back to the MAC */
578 descptr->status = DSC_OWNER_MAC;
579 descptr = descptr->vndescp;
582 priv->rx_remove_ptr = descptr;
587 static void r6040_tx(struct net_device *dev)
589 struct r6040_private *priv = netdev_priv(dev);
590 struct r6040_descriptor *descptr;
591 void __iomem *ioaddr = priv->base;
592 struct sk_buff *skb_ptr;
595 spin_lock(&priv->lock);
596 descptr = priv->tx_remove_ptr;
597 while (priv->tx_free_desc < TX_DCNT) {
598 /* Check for errors */
599 err = ioread16(ioaddr + MLSR);
602 dev->stats.rx_fifo_errors++;
603 if (err & (0x2000 | 0x4000))
604 dev->stats.tx_carrier_errors++;
606 if (descptr->status & DSC_OWNER_MAC)
607 break; /* Not complete */
608 skb_ptr = descptr->skb_ptr;
609 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
610 skb_ptr->len, PCI_DMA_TODEVICE);
612 dev_kfree_skb_irq(skb_ptr);
613 descptr->skb_ptr = NULL;
614 /* To next descriptor */
615 descptr = descptr->vndescp;
616 priv->tx_free_desc++;
618 priv->tx_remove_ptr = descptr;
620 if (priv->tx_free_desc)
621 netif_wake_queue(dev);
622 spin_unlock(&priv->lock);
625 static int r6040_poll(struct napi_struct *napi, int budget)
627 struct r6040_private *priv =
628 container_of(napi, struct r6040_private, napi);
629 struct net_device *dev = priv->dev;
630 void __iomem *ioaddr = priv->base;
633 work_done = r6040_rx(dev, budget);
635 if (work_done < budget) {
637 /* Enable RX interrupt */
638 iowrite16(ioread16(ioaddr + MIER) | RX_INTS, ioaddr + MIER);
643 /* The RDC interrupt handler. */
644 static irqreturn_t r6040_interrupt(int irq, void *dev_id)
646 struct net_device *dev = dev_id;
647 struct r6040_private *lp = netdev_priv(dev);
648 void __iomem *ioaddr = lp->base;
652 misr = ioread16(ioaddr + MIER);
653 /* Mask off RDC MAC interrupt */
654 iowrite16(MSK_INT, ioaddr + MIER);
655 /* Read MISR status and clear */
656 status = ioread16(ioaddr + MISR);
658 if (status == 0x0000 || status == 0xffff) {
659 /* Restore RDC MAC interrupt */
660 iowrite16(misr, ioaddr + MIER);
664 /* RX interrupt request */
665 if (status & RX_INTS) {
666 if (status & RX_NO_DESC) {
667 /* RX descriptor unavailable */
668 dev->stats.rx_dropped++;
669 dev->stats.rx_missed_errors++;
671 if (status & RX_FIFO_FULL)
672 dev->stats.rx_fifo_errors++;
674 if (likely(napi_schedule_prep(&lp->napi))) {
675 /* Mask off RX interrupt */
677 __napi_schedule(&lp->napi);
681 /* TX interrupt request */
682 if (status & TX_INTS)
685 /* Restore RDC MAC interrupt */
686 iowrite16(misr, ioaddr + MIER);
691 #ifdef CONFIG_NET_POLL_CONTROLLER
692 static void r6040_poll_controller(struct net_device *dev)
694 disable_irq(dev->irq);
695 r6040_interrupt(dev->irq, dev);
696 enable_irq(dev->irq);
701 static int r6040_up(struct net_device *dev)
703 struct r6040_private *lp = netdev_priv(dev);
704 void __iomem *ioaddr = lp->base;
707 /* Initialise and alloc RX/TX buffers */
708 r6040_init_txbufs(dev);
709 ret = r6040_alloc_rxbufs(dev);
713 /* improve performance (by RDC guys) */
714 r6040_phy_write(ioaddr, 30, 17,
715 (r6040_phy_read(ioaddr, 30, 17) | 0x4000));
716 r6040_phy_write(ioaddr, 30, 17,
717 ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000));
718 r6040_phy_write(ioaddr, 0, 19, 0x0000);
719 r6040_phy_write(ioaddr, 0, 30, 0x01F0);
721 /* Initialize all MAC registers */
722 r6040_init_mac_regs(dev);
724 phy_start(lp->phydev);
730 /* Read/set MAC address routines */
731 static void r6040_mac_address(struct net_device *dev)
733 struct r6040_private *lp = netdev_priv(dev);
734 void __iomem *ioaddr = lp->base;
737 /* MAC operation register */
738 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset MAC */
739 iowrite16(2, ioaddr + MAC_SM); /* Reset internal state machine */
740 iowrite16(0, ioaddr + MAC_SM);
743 /* Restore MAC Address */
744 adrp = (u16 *) dev->dev_addr;
745 iowrite16(adrp[0], ioaddr + MID_0L);
746 iowrite16(adrp[1], ioaddr + MID_0M);
747 iowrite16(adrp[2], ioaddr + MID_0H);
749 /* Store MAC Address in perm_addr */
750 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
753 static int r6040_open(struct net_device *dev)
755 struct r6040_private *lp = netdev_priv(dev);
758 /* Request IRQ and Register interrupt handler */
759 ret = request_irq(dev->irq, r6040_interrupt,
760 IRQF_SHARED, dev->name, dev);
764 /* Set MAC address */
765 r6040_mac_address(dev);
767 /* Allocate Descriptor memory */
769 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
776 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
779 goto err_free_rx_ring;
784 goto err_free_tx_ring;
786 napi_enable(&lp->napi);
787 netif_start_queue(dev);
792 pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring,
795 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
798 free_irq(dev->irq, dev);
803 static netdev_tx_t r6040_start_xmit(struct sk_buff *skb,
804 struct net_device *dev)
806 struct r6040_private *lp = netdev_priv(dev);
807 struct r6040_descriptor *descptr;
808 void __iomem *ioaddr = lp->base;
811 /* Critical Section */
812 spin_lock_irqsave(&lp->lock, flags);
814 /* TX resource check */
815 if (!lp->tx_free_desc) {
816 spin_unlock_irqrestore(&lp->lock, flags);
817 netif_stop_queue(dev);
818 netdev_err(dev, ": no tx descriptor\n");
819 return NETDEV_TX_BUSY;
822 /* Statistic Counter */
823 dev->stats.tx_packets++;
824 dev->stats.tx_bytes += skb->len;
825 /* Set TX descriptor & Transmit it */
827 descptr = lp->tx_insert_ptr;
831 descptr->len = skb->len;
833 descptr->skb_ptr = skb;
834 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
835 skb->data, skb->len, PCI_DMA_TODEVICE));
836 descptr->status = DSC_OWNER_MAC;
838 skb_tx_timestamp(skb);
840 /* Trigger the MAC to check the TX descriptor */
841 iowrite16(0x01, ioaddr + MTPR);
842 lp->tx_insert_ptr = descptr->vndescp;
844 /* If no tx resource, stop */
845 if (!lp->tx_free_desc)
846 netif_stop_queue(dev);
848 spin_unlock_irqrestore(&lp->lock, flags);
853 static void r6040_multicast_list(struct net_device *dev)
855 struct r6040_private *lp = netdev_priv(dev);
856 void __iomem *ioaddr = lp->base;
858 struct netdev_hw_addr *ha;
861 u16 hash_table[4] = { 0 };
863 spin_lock_irqsave(&lp->lock, flags);
865 /* Keep our MAC Address */
866 adrp = (u16 *)dev->dev_addr;
867 iowrite16(adrp[0], ioaddr + MID_0L);
868 iowrite16(adrp[1], ioaddr + MID_0M);
869 iowrite16(adrp[2], ioaddr + MID_0H);
871 /* Clear AMCP & PROM bits */
872 lp->mcr0 = ioread16(ioaddr + MCR0) & ~(MCR0_PROMISC | MCR0_HASH_EN);
874 /* Promiscuous mode */
875 if (dev->flags & IFF_PROMISC)
876 lp->mcr0 |= MCR0_PROMISC;
878 /* Enable multicast hash table function to
879 * receive all multicast packets. */
880 else if (dev->flags & IFF_ALLMULTI) {
881 lp->mcr0 |= MCR0_HASH_EN;
883 for (i = 0; i < MCAST_MAX ; i++) {
884 iowrite16(0, ioaddr + MID_1L + 8 * i);
885 iowrite16(0, ioaddr + MID_1M + 8 * i);
886 iowrite16(0, ioaddr + MID_1H + 8 * i);
889 for (i = 0; i < 4; i++)
890 hash_table[i] = 0xffff;
892 /* Use internal multicast address registers if the number of
893 * multicast addresses is not greater than MCAST_MAX. */
894 else if (netdev_mc_count(dev) <= MCAST_MAX) {
896 netdev_for_each_mc_addr(ha, dev) {
897 u16 *adrp = (u16 *) ha->addr;
898 iowrite16(adrp[0], ioaddr + MID_1L + 8 * i);
899 iowrite16(adrp[1], ioaddr + MID_1M + 8 * i);
900 iowrite16(adrp[2], ioaddr + MID_1H + 8 * i);
903 while (i < MCAST_MAX) {
904 iowrite16(0, ioaddr + MID_1L + 8 * i);
905 iowrite16(0, ioaddr + MID_1M + 8 * i);
906 iowrite16(0, ioaddr + MID_1H + 8 * i);
910 /* Otherwise, Enable multicast hash table function. */
914 lp->mcr0 |= MCR0_HASH_EN;
916 for (i = 0; i < MCAST_MAX ; i++) {
917 iowrite16(0, ioaddr + MID_1L + 8 * i);
918 iowrite16(0, ioaddr + MID_1M + 8 * i);
919 iowrite16(0, ioaddr + MID_1H + 8 * i);
922 /* Build multicast hash table */
923 netdev_for_each_mc_addr(ha, dev) {
924 u8 *addrs = ha->addr;
926 crc = ether_crc(ETH_ALEN, addrs);
928 hash_table[crc >> 4] |= 1 << (crc & 0xf);
932 iowrite16(lp->mcr0, ioaddr + MCR0);
934 /* Fill the MAC hash tables with their values */
935 if (lp->mcr0 & MCR0_HASH_EN) {
936 iowrite16(hash_table[0], ioaddr + MAR0);
937 iowrite16(hash_table[1], ioaddr + MAR1);
938 iowrite16(hash_table[2], ioaddr + MAR2);
939 iowrite16(hash_table[3], ioaddr + MAR3);
942 spin_unlock_irqrestore(&lp->lock, flags);
945 static void netdev_get_drvinfo(struct net_device *dev,
946 struct ethtool_drvinfo *info)
948 struct r6040_private *rp = netdev_priv(dev);
950 strcpy(info->driver, DRV_NAME);
951 strcpy(info->version, DRV_VERSION);
952 strcpy(info->bus_info, pci_name(rp->pdev));
955 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
957 struct r6040_private *rp = netdev_priv(dev);
959 return phy_ethtool_gset(rp->phydev, cmd);
962 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
964 struct r6040_private *rp = netdev_priv(dev);
966 return phy_ethtool_sset(rp->phydev, cmd);
969 static const struct ethtool_ops netdev_ethtool_ops = {
970 .get_drvinfo = netdev_get_drvinfo,
971 .get_settings = netdev_get_settings,
972 .set_settings = netdev_set_settings,
973 .get_link = ethtool_op_get_link,
976 static const struct net_device_ops r6040_netdev_ops = {
977 .ndo_open = r6040_open,
978 .ndo_stop = r6040_close,
979 .ndo_start_xmit = r6040_start_xmit,
980 .ndo_get_stats = r6040_get_stats,
981 .ndo_set_rx_mode = r6040_multicast_list,
982 .ndo_change_mtu = eth_change_mtu,
983 .ndo_validate_addr = eth_validate_addr,
984 .ndo_set_mac_address = eth_mac_addr,
985 .ndo_do_ioctl = r6040_ioctl,
986 .ndo_tx_timeout = r6040_tx_timeout,
987 #ifdef CONFIG_NET_POLL_CONTROLLER
988 .ndo_poll_controller = r6040_poll_controller,
992 static void r6040_adjust_link(struct net_device *dev)
994 struct r6040_private *lp = netdev_priv(dev);
995 struct phy_device *phydev = lp->phydev;
996 int status_changed = 0;
997 void __iomem *ioaddr = lp->base;
1001 if (lp->old_link != phydev->link) {
1003 lp->old_link = phydev->link;
1006 /* reflect duplex change */
1007 if (phydev->link && (lp->old_duplex != phydev->duplex)) {
1008 lp->mcr0 |= (phydev->duplex == DUPLEX_FULL ? MCR0_FD : 0);
1009 iowrite16(lp->mcr0, ioaddr);
1012 lp->old_duplex = phydev->duplex;
1015 if (status_changed) {
1016 pr_info("%s: link %s", dev->name, phydev->link ?
1019 pr_cont(" - %d/%s", phydev->speed,
1020 DUPLEX_FULL == phydev->duplex ? "full" : "half");
1025 static int r6040_mii_probe(struct net_device *dev)
1027 struct r6040_private *lp = netdev_priv(dev);
1028 struct phy_device *phydev = NULL;
1030 phydev = phy_find_first(lp->mii_bus);
1032 dev_err(&lp->pdev->dev, "no PHY found\n");
1036 phydev = phy_connect(dev, dev_name(&phydev->dev), &r6040_adjust_link,
1037 0, PHY_INTERFACE_MODE_MII);
1039 if (IS_ERR(phydev)) {
1040 dev_err(&lp->pdev->dev, "could not attach to PHY\n");
1041 return PTR_ERR(phydev);
1044 /* mask with MAC supported features */
1045 phydev->supported &= (SUPPORTED_10baseT_Half
1046 | SUPPORTED_10baseT_Full
1047 | SUPPORTED_100baseT_Half
1048 | SUPPORTED_100baseT_Full
1053 phydev->advertising = phydev->supported;
1054 lp->phydev = phydev;
1056 lp->old_duplex = -1;
1058 dev_info(&lp->pdev->dev, "attached PHY driver [%s] "
1059 "(mii_bus:phy_addr=%s)\n",
1060 phydev->drv->name, dev_name(&phydev->dev));
1065 static int __devinit r6040_init_one(struct pci_dev *pdev,
1066 const struct pci_device_id *ent)
1068 struct net_device *dev;
1069 struct r6040_private *lp;
1070 void __iomem *ioaddr;
1071 int err, io_size = R6040_IO_SIZE;
1072 static int card_idx = -1;
1077 pr_info("%s\n", version);
1079 err = pci_enable_device(pdev);
1083 /* this should always be supported */
1084 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1086 dev_err(&pdev->dev, "32-bit PCI DMA addresses"
1087 "not supported by the card\n");
1090 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1092 dev_err(&pdev->dev, "32-bit PCI DMA addresses"
1093 "not supported by the card\n");
1098 if (pci_resource_len(pdev, bar) < io_size) {
1099 dev_err(&pdev->dev, "Insufficient PCI resources, aborting\n");
1104 pci_set_master(pdev);
1106 dev = alloc_etherdev(sizeof(struct r6040_private));
1108 dev_err(&pdev->dev, "Failed to allocate etherdev\n");
1112 SET_NETDEV_DEV(dev, &pdev->dev);
1113 lp = netdev_priv(dev);
1115 err = pci_request_regions(pdev, DRV_NAME);
1118 dev_err(&pdev->dev, "Failed to request PCI regions\n");
1119 goto err_out_free_dev;
1122 ioaddr = pci_iomap(pdev, bar, io_size);
1124 dev_err(&pdev->dev, "ioremap failed for device\n");
1126 goto err_out_free_res;
1128 /* If PHY status change register is still set to zero it means the
1129 * bootloader didn't initialize it */
1130 if (ioread16(ioaddr + PHY_CC) == 0)
1131 iowrite16(0x9f07, ioaddr + PHY_CC);
1133 /* Init system & device */
1135 dev->irq = pdev->irq;
1137 spin_lock_init(&lp->lock);
1138 pci_set_drvdata(pdev, dev);
1140 /* Set MAC address */
1143 adrp = (u16 *)dev->dev_addr;
1144 adrp[0] = ioread16(ioaddr + MID_0L);
1145 adrp[1] = ioread16(ioaddr + MID_0M);
1146 adrp[2] = ioread16(ioaddr + MID_0H);
1148 /* Some bootloader/BIOSes do not initialize
1149 * MAC address, warn about that */
1150 if (!(adrp[0] || adrp[1] || adrp[2])) {
1151 netdev_warn(dev, "MAC address not initialized, "
1152 "generating random\n");
1153 random_ether_addr(dev->dev_addr);
1156 /* Link new device into r6040_root_dev */
1160 /* Init RDC private data */
1161 lp->mcr0 = MCR0_XMTEN | MCR0;
1163 /* The RDC-specific entries in the device structure. */
1164 dev->netdev_ops = &r6040_netdev_ops;
1165 dev->ethtool_ops = &netdev_ethtool_ops;
1166 dev->watchdog_timeo = TX_TIMEOUT;
1168 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1170 lp->mii_bus = mdiobus_alloc();
1172 dev_err(&pdev->dev, "mdiobus_alloc() failed\n");
1177 lp->mii_bus->priv = dev;
1178 lp->mii_bus->read = r6040_mdiobus_read;
1179 lp->mii_bus->write = r6040_mdiobus_write;
1180 lp->mii_bus->reset = r6040_mdiobus_reset;
1181 lp->mii_bus->name = "r6040_eth_mii";
1182 snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1183 dev_name(&pdev->dev), card_idx);
1184 lp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1185 if (!lp->mii_bus->irq) {
1186 dev_err(&pdev->dev, "mii_bus irq allocation failed\n");
1191 for (i = 0; i < PHY_MAX_ADDR; i++)
1192 lp->mii_bus->irq[i] = PHY_POLL;
1194 err = mdiobus_register(lp->mii_bus);
1196 dev_err(&pdev->dev, "failed to register MII bus\n");
1197 goto err_out_mdio_irq;
1200 err = r6040_mii_probe(dev);
1202 dev_err(&pdev->dev, "failed to probe MII bus\n");
1203 goto err_out_mdio_unregister;
1206 /* Register net device. After this dev->name assign */
1207 err = register_netdev(dev);
1209 dev_err(&pdev->dev, "Failed to register net device\n");
1210 goto err_out_mdio_unregister;
1214 err_out_mdio_unregister:
1215 mdiobus_unregister(lp->mii_bus);
1217 kfree(lp->mii_bus->irq);
1219 mdiobus_free(lp->mii_bus);
1221 pci_iounmap(pdev, ioaddr);
1223 pci_release_regions(pdev);
1230 static void __devexit r6040_remove_one(struct pci_dev *pdev)
1232 struct net_device *dev = pci_get_drvdata(pdev);
1233 struct r6040_private *lp = netdev_priv(dev);
1235 unregister_netdev(dev);
1236 mdiobus_unregister(lp->mii_bus);
1237 kfree(lp->mii_bus->irq);
1238 mdiobus_free(lp->mii_bus);
1239 pci_release_regions(pdev);
1241 pci_disable_device(pdev);
1242 pci_set_drvdata(pdev, NULL);
1246 static DEFINE_PCI_DEVICE_TABLE(r6040_pci_tbl) = {
1247 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1250 MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1252 static struct pci_driver r6040_driver = {
1254 .id_table = r6040_pci_tbl,
1255 .probe = r6040_init_one,
1256 .remove = __devexit_p(r6040_remove_one),
1260 static int __init r6040_init(void)
1262 return pci_register_driver(&r6040_driver);
1266 static void __exit r6040_cleanup(void)
1268 pci_unregister_driver(&r6040_driver);
1271 module_init(r6040_init);
1272 module_exit(r6040_cleanup);