drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include "qlcnic.h"
   9 #include "qlcnic_hdr.h"
  10
  11 #include <linux/slab.h>
  12 #include <net/ip.h>
  13 #include <linux/bitops.h>
  14
  15 #define MASK(n) ((1ULL<<(n))-1)
  16 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
  17
  18 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
  19
  20 #define CRB_BLK(off)    ((off >> 20) & 0x3f)
  21 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  22 #define CRB_WINDOW_2M   (0x130060)
  23 #define CRB_HI(off)     ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
  24 #define CRB_INDIRECT_2M (0x1e0000UL)
  25
  26 struct qlcnic_ms_reg_ctrl {
  27         u32 ocm_window;
  28         u32 control;
  29         u32 hi;
  30         u32 low;
  31         u32 rd[4];
  32         u32 wd[4];
  33         u64 off;
  34 };
  35
  36 #ifndef readq
  37 static inline u64 readq(void __iomem *addr)
  38 {
  39         return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
  40 }
  41 #endif
  42
  43 #ifndef writeq
  44 static inline void writeq(u64 val, void __iomem *addr)
  45 {
  46         writel(((u32) (val)), (addr));
  47         writel(((u32) (val >> 32)), (addr + 4));
  48 }
  49 #endif
  50
  51 static struct crb_128M_2M_block_map
  52 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
  53     {{{0, 0,         0,         0} } },         /* 0: PCI */
  54     {{{1, 0x0100000, 0x0102000, 0x120000},      /* 1: PCIE */
  55           {1, 0x0110000, 0x0120000, 0x130000},
  56           {1, 0x0120000, 0x0122000, 0x124000},
  57           {1, 0x0130000, 0x0132000, 0x126000},
  58           {1, 0x0140000, 0x0142000, 0x128000},
  59           {1, 0x0150000, 0x0152000, 0x12a000},
  60           {1, 0x0160000, 0x0170000, 0x110000},
  61           {1, 0x0170000, 0x0172000, 0x12e000},
  62           {0, 0x0000000, 0x0000000, 0x000000},
  63           {0, 0x0000000, 0x0000000, 0x000000},
  64           {0, 0x0000000, 0x0000000, 0x000000},
  65           {0, 0x0000000, 0x0000000, 0x000000},
  66           {0, 0x0000000, 0x0000000, 0x000000},
  67           {0, 0x0000000, 0x0000000, 0x000000},
  68           {1, 0x01e0000, 0x01e0800, 0x122000},
  69           {0, 0x0000000, 0x0000000, 0x000000} } },
  70         {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
  71     {{{0, 0,         0,         0} } },     /* 3: */
  72     {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
  73     {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE   */
  74     {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU   */
  75     {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM    */
  76     {{{1, 0x0800000, 0x0802000, 0x170000},  /* 8: SQM0  */
  77       {0, 0x0000000, 0x0000000, 0x000000},
  78       {0, 0x0000000, 0x0000000, 0x000000},
  79       {0, 0x0000000, 0x0000000, 0x000000},
  80       {0, 0x0000000, 0x0000000, 0x000000},
  81       {0, 0x0000000, 0x0000000, 0x000000},
  82       {0, 0x0000000, 0x0000000, 0x000000},
  83       {0, 0x0000000, 0x0000000, 0x000000},
  84       {0, 0x0000000, 0x0000000, 0x000000},
  85       {0, 0x0000000, 0x0000000, 0x000000},
  86       {0, 0x0000000, 0x0000000, 0x000000},
  87       {0, 0x0000000, 0x0000000, 0x000000},
  88       {0, 0x0000000, 0x0000000, 0x000000},
  89       {0, 0x0000000, 0x0000000, 0x000000},
  90       {0, 0x0000000, 0x0000000, 0x000000},
  91       {1, 0x08f0000, 0x08f2000, 0x172000} } },
  92     {{{1, 0x0900000, 0x0902000, 0x174000},      /* 9: SQM1*/
  93       {0, 0x0000000, 0x0000000, 0x000000},
  94       {0, 0x0000000, 0x0000000, 0x000000},
  95       {0, 0x0000000, 0x0000000, 0x000000},
  96       {0, 0x0000000, 0x0000000, 0x000000},
  97       {0, 0x0000000, 0x0000000, 0x000000},
  98       {0, 0x0000000, 0x0000000, 0x000000},
  99       {0, 0x0000000, 0x0000000, 0x000000},
 100       {0, 0x0000000, 0x0000000, 0x000000},
 101       {0, 0x0000000, 0x0000000, 0x000000},
 102       {0, 0x0000000, 0x0000000, 0x000000},
 103       {0, 0x0000000, 0x0000000, 0x000000},
 104       {0, 0x0000000, 0x0000000, 0x000000},
 105       {0, 0x0000000, 0x0000000, 0x000000},
 106       {0, 0x0000000, 0x0000000, 0x000000},
 107       {1, 0x09f0000, 0x09f2000, 0x176000} } },
 108     {{{0, 0x0a00000, 0x0a02000, 0x178000},      /* 10: SQM2*/
 109       {0, 0x0000000, 0x0000000, 0x000000},
 110       {0, 0x0000000, 0x0000000, 0x000000},
 111       {0, 0x0000000, 0x0000000, 0x000000},
 112       {0, 0x0000000, 0x0000000, 0x000000},
 113       {0, 0x0000000, 0x0000000, 0x000000},
 114       {0, 0x0000000, 0x0000000, 0x000000},
 115       {0, 0x0000000, 0x0000000, 0x000000},
 116       {0, 0x0000000, 0x0000000, 0x000000},
 117       {0, 0x0000000, 0x0000000, 0x000000},
 118       {0, 0x0000000, 0x0000000, 0x000000},
 119       {0, 0x0000000, 0x0000000, 0x000000},
 120       {0, 0x0000000, 0x0000000, 0x000000},
 121       {0, 0x0000000, 0x0000000, 0x000000},
 122       {0, 0x0000000, 0x0000000, 0x000000},
 123       {1, 0x0af0000, 0x0af2000, 0x17a000} } },
 124     {{{0, 0x0b00000, 0x0b02000, 0x17c000},      /* 11: SQM3*/
 125       {0, 0x0000000, 0x0000000, 0x000000},
 126       {0, 0x0000000, 0x0000000, 0x000000},
 127       {0, 0x0000000, 0x0000000, 0x000000},
 128       {0, 0x0000000, 0x0000000, 0x000000},
 129       {0, 0x0000000, 0x0000000, 0x000000},
 130       {0, 0x0000000, 0x0000000, 0x000000},
 131       {0, 0x0000000, 0x0000000, 0x000000},
 132       {0, 0x0000000, 0x0000000, 0x000000},
 133       {0, 0x0000000, 0x0000000, 0x000000},
 134       {0, 0x0000000, 0x0000000, 0x000000},
 135       {0, 0x0000000, 0x0000000, 0x000000},
 136       {0, 0x0000000, 0x0000000, 0x000000},
 137       {0, 0x0000000, 0x0000000, 0x000000},
 138       {0, 0x0000000, 0x0000000, 0x000000},
 139       {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
 140         {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
 141         {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
 142         {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
 143         {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
 144         {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
 145         {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
 146         {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
 147         {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
 148         {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
 149         {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
 150         {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
 151         {{{0, 0,         0,         0} } },     /* 23: */
 152         {{{0, 0,         0,         0} } },     /* 24: */
 153         {{{0, 0,         0,         0} } },     /* 25: */
 154         {{{0, 0,         0,         0} } },     /* 26: */
 155         {{{0, 0,         0,         0} } },     /* 27: */
 156         {{{0, 0,         0,         0} } },     /* 28: */
 157         {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
 158     {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
 159     {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
 160         {{{0} } },                              /* 32: PCI */
 161         {{{1, 0x2100000, 0x2102000, 0x120000},  /* 33: PCIE */
 162           {1, 0x2110000, 0x2120000, 0x130000},
 163           {1, 0x2120000, 0x2122000, 0x124000},
 164           {1, 0x2130000, 0x2132000, 0x126000},
 165           {1, 0x2140000, 0x2142000, 0x128000},
 166           {1, 0x2150000, 0x2152000, 0x12a000},
 167           {1, 0x2160000, 0x2170000, 0x110000},
 168           {1, 0x2170000, 0x2172000, 0x12e000},
 169           {0, 0x0000000, 0x0000000, 0x000000},
 170           {0, 0x0000000, 0x0000000, 0x000000},
 171           {0, 0x0000000, 0x0000000, 0x000000},
 172           {0, 0x0000000, 0x0000000, 0x000000},
 173           {0, 0x0000000, 0x0000000, 0x000000},
 174           {0, 0x0000000, 0x0000000, 0x000000},
 175           {0, 0x0000000, 0x0000000, 0x000000},
 176           {0, 0x0000000, 0x0000000, 0x000000} } },
 177         {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
 178         {{{0} } },                              /* 35: */
 179         {{{0} } },                              /* 36: */
 180         {{{0} } },                              /* 37: */
 181         {{{0} } },                              /* 38: */
 182         {{{0} } },                              /* 39: */
 183         {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
 184         {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
 185         {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
 186         {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
 187         {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
 188         {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
 189         {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
 190         {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
 191         {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
 192         {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
 193         {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
 194         {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
 195         {{{0} } },                              /* 52: */
 196         {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
 197         {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
 198         {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
 199         {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
 200         {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
 201         {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
 202         {{{0} } },                              /* 59: I2C0 */
 203         {{{0} } },                              /* 60: I2C1 */
 204         {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
 205         {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
 206         {{{1, 0x3f00000, 0x3f01000, 0x168000} } }       /* 63: P2NR0 */
 207 };
 208
 209 /*
 210  * top 12 bits of crb internal address (hub, agent)
 211  */
 212 static const unsigned crb_hub_agt[64] = {
 213         0,
 214         QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
 215         QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
 216         QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
 217         0,
 218         QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
 219         QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
 220         QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
 221         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
 222         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
 223         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
 224         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
 225         QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
 226         QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
 227         QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
 228         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
 229         QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
 230         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
 231         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
 232         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
 233         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
 234         QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
 235         QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
 236         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
 237         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
 238         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
 239         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
 240         0,
 241         QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
 242         QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
 243         0,
 244         QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
 245         0,
 246         QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
 247         QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
 248         0,
 249         0,
 250         0,
 251         0,
 252         0,
 253         QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
 254         0,
 255         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
 256         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
 257         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
 258         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
 259         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
 260         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
 261         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
 262         QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
 263         QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
 264         QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
 265         0,
 266         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
 267         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
 268         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
 269         QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
 270         0,
 271         QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
 272         QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
 273         QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
 274         0,
 275         QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
 276         0,
 277 };
 278
 279 static const u32 msi_tgt_status[8] = {
 280         ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1,
 281         ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3,
 282         ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5,
 283         ISR_INT_TARGET_STATUS_F6, ISR_INT_TARGET_STATUS_F7
 284 };
 285
 286 /*  PCI Windowing for DDR regions.  */
 287
 288 #define QLCNIC_PCIE_SEM_TIMEOUT 10000
 289
 290 static void qlcnic_read_window_reg(u32 addr, void __iomem *bar0, u32 *data)
 291 {
 292         u32 dest;
 293         void __iomem *val;
 294
 295         dest = addr & 0xFFFF0000;
 296         val = bar0 + QLCNIC_FW_DUMP_REG1;
 297         writel(dest, val);
 298         readl(val);
 299         val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
 300         *data = readl(val);
 301 }
 302
 303 static void qlcnic_write_window_reg(u32 addr, void __iomem *bar0, u32 data)
 304 {
 305         u32 dest;
 306         void __iomem *val;
 307
 308         dest = addr & 0xFFFF0000;
 309         val = bar0 + QLCNIC_FW_DUMP_REG1;
 310         writel(dest, val);
 311         readl(val);
 312         val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
 313         writel(data, val);
 314         readl(val);
 315 }
 316
 317 int
 318 qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
 319 {
 320         int timeout = 0;
 321         int err = 0;
 322         u32 done = 0;
 323
 324         while (!done) {
 325                 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)),
 326                                &err);
 327                 if (done == 1)
 328                         break;
 329                 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) {
 330                         dev_err(&adapter->pdev->dev,
 331                                 "Failed to acquire sem=%d lock; holdby=%d\n",
 332                                 sem,
 333                                 id_reg ? QLCRD32(adapter, id_reg, &err) : -1);
 334                         return -EIO;
 335                 }
 336                 msleep(1);
 337         }
 338
 339         if (id_reg)
 340                 QLCWR32(adapter, id_reg, adapter->portnum);
 341
 342         return 0;
 343 }
 344
 345 void
 346 qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
 347 {
 348         int err = 0;
 349
 350         QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)), &err);
 351 }
 352
 353 int qlcnic_ind_rd(struct qlcnic_adapter *adapter, u32 addr)
 354 {
 355         int err = 0;
 356         u32 data;
 357
 358         if (qlcnic_82xx_check(adapter))
 359                 qlcnic_read_window_reg(addr, adapter->ahw->pci_base0, &data);
 360         else {
 361                 data = QLCRD32(adapter, addr, &err);
 362                 if (err == -EIO)
 363                         return err;
 364         }
 365         return data;
 366 }
 367
 368 void qlcnic_ind_wr(struct qlcnic_adapter *adapter, u32 addr, u32 data)
 369 {
 370         if (qlcnic_82xx_check(adapter))
 371                 qlcnic_write_window_reg(addr, adapter->ahw->pci_base0, data);
 372         else
 373                 qlcnic_83xx_wrt_reg_indirect(adapter, addr, data);
 374 }
 375
 376 static int
 377 qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
 378                 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
 379 {
 380         u32 i, producer;
 381         struct qlcnic_cmd_buffer *pbuf;
 382         struct cmd_desc_type0 *cmd_desc;
 383         struct qlcnic_host_tx_ring *tx_ring;
 384
 385         i = 0;
 386
 387         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 388                 return -EIO;
 389
 390         tx_ring = &adapter->tx_ring[0];
 391         __netif_tx_lock_bh(tx_ring->txq);
 392
 393         producer = tx_ring->producer;
 394
 395         if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
 396                 netif_tx_stop_queue(tx_ring->txq);
 397                 smp_mb();
 398                 if (qlcnic_tx_avail(tx_ring) > nr_desc) {
 399                         if (qlcnic_tx_avail(tx_ring) > TX_STOP_THRESH)
 400                                 netif_tx_wake_queue(tx_ring->txq);
 401                 } else {
 402                         adapter->stats.xmit_off++;
 403                         __netif_tx_unlock_bh(tx_ring->txq);
 404                         return -EBUSY;
 405                 }
 406         }
 407
 408         do {
 409                 cmd_desc = &cmd_desc_arr[i];
 410
 411                 pbuf = &tx_ring->cmd_buf_arr[producer];
 412                 pbuf->skb = NULL;
 413                 pbuf->frag_count = 0;
 414
 415                 memcpy(&tx_ring->desc_head[producer],
 416                        cmd_desc, sizeof(struct cmd_desc_type0));
 417
 418                 producer = get_next_index(producer, tx_ring->num_desc);
 419                 i++;
 420
 421         } while (i != nr_desc);
 422
 423         tx_ring->producer = producer;
 424
 425         qlcnic_update_cmd_producer(tx_ring);
 426
 427         __netif_tx_unlock_bh(tx_ring->txq);
 428
 429         return 0;
 430 }
 431
 432 int qlcnic_82xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
 433                                    u16 vlan_id, u8 op)
 434 {
 435         struct qlcnic_nic_req req;
 436         struct qlcnic_mac_req *mac_req;
 437         struct qlcnic_vlan_req *vlan_req;
 438         u64 word;
 439
 440         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 441         req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
 442
 443         word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
 444         req.req_hdr = cpu_to_le64(word);
 445
 446         mac_req = (struct qlcnic_mac_req *)&req.words[0];
 447         mac_req->op = op;
 448         memcpy(mac_req->mac_addr, addr, ETH_ALEN);
 449
 450         vlan_req = (struct qlcnic_vlan_req *)&req.words[1];
 451         vlan_req->vlan_id = cpu_to_le16(vlan_id);
 452
 453         return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 454 }
 455
 456 int qlcnic_nic_del_mac(struct qlcnic_adapter *adapter, const u8 *addr)
 457 {
 458         struct list_head *head;
 459         struct qlcnic_mac_list_s *cur;
 460         int err = -EINVAL;
 461
 462         /* Delete MAC from the existing list */
 463         list_for_each(head, &adapter->mac_list) {
 464                 cur = list_entry(head, struct qlcnic_mac_list_s, list);
 465                 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
 466                         err = qlcnic_sre_macaddr_change(adapter, cur->mac_addr,
 467                                                         0, QLCNIC_MAC_DEL);
 468                         if (err)
 469                                 return err;
 470                         list_del(&cur->list);
 471                         kfree(cur);
 472                         return err;
 473                 }
 474         }
 475         return err;
 476 }
 477
 478 int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, const u8 *addr, u16 vlan)
 479 {
 480         struct list_head *head;
 481         struct qlcnic_mac_list_s *cur;
 482
 483         /* look up if already exists */
 484         list_for_each(head, &adapter->mac_list) {
 485                 cur = list_entry(head, struct qlcnic_mac_list_s, list);
 486                 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
 487                         return 0;
 488         }
 489
 490         cur = kzalloc(sizeof(struct qlcnic_mac_list_s), GFP_ATOMIC);
 491         if (cur == NULL)
 492                 return -ENOMEM;
 493
 494         memcpy(cur->mac_addr, addr, ETH_ALEN);
 495
 496         if (qlcnic_sre_macaddr_change(adapter,
 497                                 cur->mac_addr, vlan, QLCNIC_MAC_ADD)) {
 498                 kfree(cur);
 499                 return -EIO;
 500         }
 501
 502         list_add_tail(&cur->list, &adapter->mac_list);
 503         return 0;
 504 }
 505
 506 void __qlcnic_set_multi(struct net_device *netdev, u16 vlan)
 507 {
 508         struct qlcnic_adapter *adapter = netdev_priv(netdev);
 509         struct qlcnic_hardware_context *ahw = adapter->ahw;
 510         struct netdev_hw_addr *ha;
 511         static const u8 bcast_addr[ETH_ALEN] = {
 512                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
 513         };
 514         u32 mode = VPORT_MISS_MODE_DROP;
 515
 516         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 517                 return;
 518
 519         if (!qlcnic_sriov_vf_check(adapter))
 520                 qlcnic_nic_add_mac(adapter, adapter->mac_addr, vlan);
 521         qlcnic_nic_add_mac(adapter, bcast_addr, vlan);
 522
 523         if (netdev->flags & IFF_PROMISC) {
 524                 if (!(adapter->flags & QLCNIC_PROMISC_DISABLED))
 525                         mode = VPORT_MISS_MODE_ACCEPT_ALL;
 526         } else if ((netdev->flags & IFF_ALLMULTI) ||
 527                    (netdev_mc_count(netdev) > ahw->max_mc_count)) {
 528                 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
 529         } else if (!netdev_mc_empty(netdev) &&
 530                    !qlcnic_sriov_vf_check(adapter)) {
 531                 netdev_for_each_mc_addr(ha, netdev)
 532                         qlcnic_nic_add_mac(adapter, ha->addr, vlan);
 533         }
 534
 535         if (qlcnic_sriov_vf_check(adapter))
 536                 qlcnic_vf_add_mc_list(netdev, vlan);
 537
 538         /* configure unicast MAC address, if there is not sufficient space
 539          * to store all the unicast addresses then enable promiscuous mode
 540          */
 541         if (netdev_uc_count(netdev) > ahw->max_uc_count) {
 542                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
 543         } else if (!netdev_uc_empty(netdev)) {
 544                 netdev_for_each_uc_addr(ha, netdev)
 545                         qlcnic_nic_add_mac(adapter, ha->addr, vlan);
 546         }
 547
 548         if (!qlcnic_sriov_vf_check(adapter)) {
 549                 if (mode == VPORT_MISS_MODE_ACCEPT_ALL &&
 550                     !adapter->fdb_mac_learn) {
 551                         qlcnic_alloc_lb_filters_mem(adapter);
 552                         adapter->drv_mac_learn = true;
 553                 } else {
 554                         adapter->drv_mac_learn = false;
 555                 }
 556         }
 557
 558         qlcnic_nic_set_promisc(adapter, mode);
 559 }
 560
 561 void qlcnic_set_multi(struct net_device *netdev)
 562 {
 563         struct qlcnic_adapter *adapter = netdev_priv(netdev);
 564         struct netdev_hw_addr *ha;
 565         struct qlcnic_mac_list_s *cur;
 566
 567         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 568                 return;
 569         if (qlcnic_sriov_vf_check(adapter)) {
 570                 if (!netdev_mc_empty(netdev)) {
 571                         netdev_for_each_mc_addr(ha, netdev) {
 572                                 cur = kzalloc(sizeof(struct qlcnic_mac_list_s),
 573                                               GFP_ATOMIC);
 574                                 if (cur == NULL)
 575                                         break;
 576                                 memcpy(cur->mac_addr,
 577                                        ha->addr, ETH_ALEN);
 578                                 list_add_tail(&cur->list, &adapter->vf_mc_list);
 579                         }
 580                 }
 581                 qlcnic_sriov_vf_schedule_multi(adapter->netdev);
 582                 return;
 583         }
 584         __qlcnic_set_multi(netdev, 0);
 585 }
 586
 587 int qlcnic_82xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
 588 {
 589         struct qlcnic_nic_req req;
 590         u64 word;
 591
 592         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 593
 594         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 595
 596         word = QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE |
 597                         ((u64)adapter->portnum << 16);
 598         req.req_hdr = cpu_to_le64(word);
 599
 600         req.words[0] = cpu_to_le64(mode);
 601
 602         return qlcnic_send_cmd_descs(adapter,
 603                                 (struct cmd_desc_type0 *)&req, 1);
 604 }
 605
 606 void qlcnic_82xx_free_mac_list(struct qlcnic_adapter *adapter)
 607 {
 608         struct qlcnic_mac_list_s *cur;
 609         struct list_head *head = &adapter->mac_list;
 610
 611         while (!list_empty(head)) {
 612                 cur = list_entry(head->next, struct qlcnic_mac_list_s, list);
 613                 qlcnic_sre_macaddr_change(adapter,
 614                                 cur->mac_addr, 0, QLCNIC_MAC_DEL);
 615                 list_del(&cur->list);
 616                 kfree(cur);
 617         }
 618 }
 619
 620 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter)
 621 {
 622         struct qlcnic_filter *tmp_fil;
 623         struct hlist_node *n;
 624         struct hlist_head *head;
 625         int i;
 626         unsigned long time;
 627         u8 cmd;
 628
 629         for (i = 0; i < adapter->fhash.fbucket_size; i++) {
 630                 head = &(adapter->fhash.fhead[i]);
 631                 hlist_for_each_entry_safe(tmp_fil, n, head, fnode) {
 632                         cmd =  tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
 633                                                   QLCNIC_MAC_DEL;
 634                         time = tmp_fil->ftime;
 635                         if (jiffies > (QLCNIC_FILTER_AGE * HZ + time)) {
 636                                 qlcnic_sre_macaddr_change(adapter,
 637                                                           tmp_fil->faddr,
 638                                                           tmp_fil->vlan_id,
 639                                                           cmd);
 640                                 spin_lock_bh(&adapter->mac_learn_lock);
 641                                 adapter->fhash.fnum--;
 642                                 hlist_del(&tmp_fil->fnode);
 643                                 spin_unlock_bh(&adapter->mac_learn_lock);
 644                                 kfree(tmp_fil);
 645                         }
 646                 }
 647         }
 648         for (i = 0; i < adapter->rx_fhash.fbucket_size; i++) {
 649                 head = &(adapter->rx_fhash.fhead[i]);
 650
 651                 hlist_for_each_entry_safe(tmp_fil, n, head, fnode)
 652                 {
 653                         time = tmp_fil->ftime;
 654                         if (jiffies > (QLCNIC_FILTER_AGE * HZ + time)) {
 655                                 spin_lock_bh(&adapter->rx_mac_learn_lock);
 656                                 adapter->rx_fhash.fnum--;
 657                                 hlist_del(&tmp_fil->fnode);
 658                                 spin_unlock_bh(&adapter->rx_mac_learn_lock);
 659                                 kfree(tmp_fil);
 660                         }
 661                 }
 662         }
 663 }
 664
 665 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter)
 666 {
 667         struct qlcnic_filter *tmp_fil;
 668         struct hlist_node *n;
 669         struct hlist_head *head;
 670         int i;
 671         u8 cmd;
 672
 673         for (i = 0; i < adapter->fhash.fbucket_size; i++) {
 674                 head = &(adapter->fhash.fhead[i]);
 675                 hlist_for_each_entry_safe(tmp_fil, n, head, fnode) {
 676                         cmd =  tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
 677                                                   QLCNIC_MAC_DEL;
 678                         qlcnic_sre_macaddr_change(adapter,
 679                                                   tmp_fil->faddr,
 680                                                   tmp_fil->vlan_id,
 681                                                   cmd);
 682                         spin_lock_bh(&adapter->mac_learn_lock);
 683                         adapter->fhash.fnum--;
 684                         hlist_del(&tmp_fil->fnode);
 685                         spin_unlock_bh(&adapter->mac_learn_lock);
 686                         kfree(tmp_fil);
 687                 }
 688         }
 689 }
 690
 691 static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u8 flag)
 692 {
 693         struct qlcnic_nic_req req;
 694         int rv;
 695
 696         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 697
 698         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 699         req.req_hdr = cpu_to_le64(QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
 700                 ((u64) adapter->portnum << 16) | ((u64) 0x1 << 32));
 701
 702         req.words[0] = cpu_to_le64(flag);
 703
 704         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 705         if (rv != 0)
 706                 dev_err(&adapter->pdev->dev, "%sting loopback mode failed\n",
 707                                 flag ? "Set" : "Reset");
 708         return rv;
 709 }
 710
 711 int qlcnic_82xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
 712 {
 713         if (qlcnic_set_fw_loopback(adapter, mode))
 714                 return -EIO;
 715
 716         if (qlcnic_nic_set_promisc(adapter,
 717                                    VPORT_MISS_MODE_ACCEPT_ALL)) {
 718                 qlcnic_set_fw_loopback(adapter, 0);
 719                 return -EIO;
 720         }
 721
 722         msleep(1000);
 723         return 0;
 724 }
 725
 726 int qlcnic_82xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
 727 {
 728         struct net_device *netdev = adapter->netdev;
 729
 730         mode = VPORT_MISS_MODE_DROP;
 731         qlcnic_set_fw_loopback(adapter, 0);
 732
 733         if (netdev->flags & IFF_PROMISC)
 734                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
 735         else if (netdev->flags & IFF_ALLMULTI)
 736                 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
 737
 738         qlcnic_nic_set_promisc(adapter, mode);
 739         msleep(1000);
 740         return 0;
 741 }
 742
 743 int qlcnic_82xx_read_phys_port_id(struct qlcnic_adapter *adapter)
 744 {
 745         u8 mac[ETH_ALEN];
 746         int ret;
 747
 748         ret = qlcnic_get_mac_address(adapter, mac,
 749                                      adapter->ahw->physical_port);
 750         if (ret)
 751                 return ret;
 752
 753         memcpy(adapter->ahw->phys_port_id, mac, ETH_ALEN);
 754         adapter->flags |= QLCNIC_HAS_PHYS_PORT_ID;
 755
 756         return 0;
 757 }
 758
 759 /*
 760  * Send the interrupt coalescing parameter set by ethtool to the card.
 761  */
 762 void qlcnic_82xx_config_intr_coalesce(struct qlcnic_adapter *adapter)
 763 {
 764         struct qlcnic_nic_req req;
 765         int rv;
 766
 767         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 768
 769         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 770
 771         req.req_hdr = cpu_to_le64(QLCNIC_CONFIG_INTR_COALESCE |
 772                 ((u64) adapter->portnum << 16));
 773
 774         req.words[0] = cpu_to_le64(((u64) adapter->ahw->coal.flag) << 32);
 775         req.words[2] = cpu_to_le64(adapter->ahw->coal.rx_packets |
 776                         ((u64) adapter->ahw->coal.rx_time_us) << 16);
 777         req.words[5] = cpu_to_le64(adapter->ahw->coal.timer_out |
 778                         ((u64) adapter->ahw->coal.type) << 32 |
 779                         ((u64) adapter->ahw->coal.sts_ring_mask) << 40);
 780         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 781         if (rv != 0)
 782                 dev_err(&adapter->netdev->dev,
 783                         "Could not send interrupt coalescing parameters\n");
 784 }
 785
 786 #define QLCNIC_ENABLE_IPV4_LRO          1
 787 #define QLCNIC_ENABLE_IPV6_LRO          2
 788
 789 int qlcnic_82xx_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
 790 {
 791         struct qlcnic_nic_req req;
 792         u64 word;
 793         int rv;
 794
 795         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 796                 return 0;
 797
 798         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 799
 800         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 801
 802         word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
 803         req.req_hdr = cpu_to_le64(word);
 804
 805         word = 0;
 806         if (enable) {
 807                 word = QLCNIC_ENABLE_IPV4_LRO;
 808                 if (adapter->ahw->extra_capability[0] &
 809                     QLCNIC_FW_CAP2_HW_LRO_IPV6)
 810                         word |= QLCNIC_ENABLE_IPV6_LRO;
 811         }
 812
 813         req.words[0] = cpu_to_le64(word);
 814
 815         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 816         if (rv != 0)
 817                 dev_err(&adapter->netdev->dev,
 818                         "Could not send configure hw lro request\n");
 819
 820         return rv;
 821 }
 822
 823 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable)
 824 {
 825         struct qlcnic_nic_req req;
 826         u64 word;
 827         int rv;
 828
 829         if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
 830                 return 0;
 831
 832         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 833
 834         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 835
 836         word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
 837                 ((u64)adapter->portnum << 16);
 838         req.req_hdr = cpu_to_le64(word);
 839
 840         req.words[0] = cpu_to_le64(enable);
 841
 842         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 843         if (rv != 0)
 844                 dev_err(&adapter->netdev->dev,
 845                         "Could not send configure bridge mode request\n");
 846
 847         adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
 848
 849         return rv;
 850 }
 851
 852
 853 #define QLCNIC_RSS_HASHTYPE_IP_TCP      0x3
 854 #define QLCNIC_ENABLE_TYPE_C_RSS        BIT_10
 855 #define QLCNIC_RSS_FEATURE_FLAG (1ULL << 63)
 856 #define QLCNIC_RSS_IND_TABLE_MASK       0x7ULL
 857
 858 int qlcnic_82xx_config_rss(struct qlcnic_adapter *adapter, int enable)
 859 {
 860         struct qlcnic_nic_req req;
 861         u64 word;
 862         int i, rv;
 863
 864         static const u64 key[] = {
 865                 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
 866                 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
 867                 0x255b0ec26d5a56daULL
 868         };
 869
 870         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 871         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 872
 873         word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
 874         req.req_hdr = cpu_to_le64(word);
 875
 876         /*
 877          * RSS request:
 878          * bits 3-0: hash_method
 879          *      5-4: hash_type_ipv4
 880          *      7-6: hash_type_ipv6
 881          *        8: enable
 882          *        9: use indirection table
 883          *       10: type-c rss
 884          *       11: udp rss
 885          *    47-12: reserved
 886          *    62-48: indirection table mask
 887          *       63: feature flag
 888          */
 889         word =  ((u64)(QLCNIC_RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
 890                 ((u64)(QLCNIC_RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
 891                 ((u64)(enable & 0x1) << 8) |
 892                 ((u64)QLCNIC_RSS_IND_TABLE_MASK << 48) |
 893                 (u64)QLCNIC_ENABLE_TYPE_C_RSS |
 894                 (u64)QLCNIC_RSS_FEATURE_FLAG;
 895
 896         req.words[0] = cpu_to_le64(word);
 897         for (i = 0; i < 5; i++)
 898                 req.words[i+1] = cpu_to_le64(key[i]);
 899
 900         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 901         if (rv != 0)
 902                 dev_err(&adapter->netdev->dev, "could not configure RSS\n");
 903
 904         return rv;
 905 }
 906
 907 void qlcnic_82xx_config_ipaddr(struct qlcnic_adapter *adapter,
 908                                __be32 ip, int cmd)
 909 {
 910         struct qlcnic_nic_req req;
 911         struct qlcnic_ipaddr *ipa;
 912         u64 word;
 913         int rv;
 914
 915         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 916         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 917
 918         word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
 919         req.req_hdr = cpu_to_le64(word);
 920
 921         req.words[0] = cpu_to_le64(cmd);
 922         ipa = (struct qlcnic_ipaddr *)&req.words[1];
 923         ipa->ipv4 = ip;
 924
 925         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 926         if (rv != 0)
 927                 dev_err(&adapter->netdev->dev,
 928                                 "could not notify %s IP 0x%x reuqest\n",
 929                                 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
 930 }
 931
 932 int qlcnic_82xx_linkevent_request(struct qlcnic_adapter *adapter, int enable)
 933 {
 934         struct qlcnic_nic_req req;
 935         u64 word;
 936         int rv;
 937         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 938         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 939
 940         word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
 941         req.req_hdr = cpu_to_le64(word);
 942         req.words[0] = cpu_to_le64(enable | (enable << 8));
 943         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 944         if (rv != 0)
 945                 dev_err(&adapter->netdev->dev,
 946                                 "could not configure link notification\n");
 947
 948         return rv;
 949 }
 950
 951 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
 952 {
 953         struct qlcnic_nic_req req;
 954         u64 word;
 955         int rv;
 956
 957         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 958                 return 0;
 959
 960         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 961         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 962
 963         word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
 964                 ((u64)adapter->portnum << 16) |
 965                 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
 966
 967         req.req_hdr = cpu_to_le64(word);
 968
 969         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 970         if (rv != 0)
 971                 dev_err(&adapter->netdev->dev,
 972                                  "could not cleanup lro flows\n");
 973
 974         return rv;
 975 }
 976
 977 /*
 978  * qlcnic_change_mtu - Change the Maximum Transfer Unit
 979  * @returns 0 on success, negative on failure
 980  */
 981
 982 int qlcnic_change_mtu(struct net_device *netdev, int mtu)
 983 {
 984         struct qlcnic_adapter *adapter = netdev_priv(netdev);
 985         int rc = 0;
 986
 987         if (mtu < P3P_MIN_MTU || mtu > P3P_MAX_MTU) {
 988                 dev_err(&adapter->netdev->dev, "%d bytes < mtu < %d bytes"
 989                         " not supported\n", P3P_MAX_MTU, P3P_MIN_MTU);
 990                 return -EINVAL;
 991         }
 992
 993         rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
 994
 995         if (!rc)
 996                 netdev->mtu = mtu;
 997
 998         return rc;
 999 }
1000
1001 static netdev_features_t qlcnic_process_flags(struct qlcnic_adapter *adapter,
1002                                               netdev_features_t features)
1003 {
1004         u32 offload_flags = adapter->offload_flags;
1005
1006         if (offload_flags & BIT_0) {
1007                 features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM |
1008                             NETIF_F_IPV6_CSUM;
1009                 adapter->rx_csum = 1;
1010                 if (QLCNIC_IS_TSO_CAPABLE(adapter)) {
1011                         if (!(offload_flags & BIT_1))
1012                                 features &= ~NETIF_F_TSO;
1013                         else
1014                                 features |= NETIF_F_TSO;
1015
1016                         if (!(offload_flags & BIT_2))
1017                                 features &= ~NETIF_F_TSO6;
1018                         else
1019                                 features |= NETIF_F_TSO6;
1020                 }
1021         } else {
1022                 features &= ~(NETIF_F_RXCSUM |
1023                               NETIF_F_IP_CSUM |
1024                               NETIF_F_IPV6_CSUM);
1025
1026                 if (QLCNIC_IS_TSO_CAPABLE(adapter))
1027                         features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
1028                 adapter->rx_csum = 0;
1029         }
1030
1031         return features;
1032 }
1033
1034 netdev_features_t qlcnic_fix_features(struct net_device *netdev,
1035         netdev_features_t features)
1036 {
1037         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1038         netdev_features_t changed;
1039
1040         if (qlcnic_82xx_check(adapter) &&
1041             (adapter->flags & QLCNIC_ESWITCH_ENABLED)) {
1042                 if (adapter->flags & QLCNIC_APP_CHANGED_FLAGS) {
1043                         features = qlcnic_process_flags(adapter, features);
1044                 } else {
1045                         changed = features ^ netdev->features;
1046                         features ^= changed & (NETIF_F_RXCSUM |
1047                                                NETIF_F_IP_CSUM |
1048                                                NETIF_F_IPV6_CSUM |
1049                                                NETIF_F_TSO |
1050                                                NETIF_F_TSO6);
1051                 }
1052         }
1053
1054         if (!(features & NETIF_F_RXCSUM))
1055                 features &= ~NETIF_F_LRO;
1056
1057         return features;
1058 }
1059
1060
1061 int qlcnic_set_features(struct net_device *netdev, netdev_features_t features)
1062 {
1063         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1064         netdev_features_t changed = netdev->features ^ features;
1065         int hw_lro = (features & NETIF_F_LRO) ? QLCNIC_LRO_ENABLED : 0;
1066
1067         if (!(changed & NETIF_F_LRO))
1068                 return 0;
1069
1070         netdev->features ^= NETIF_F_LRO;
1071
1072         if (qlcnic_config_hw_lro(adapter, hw_lro))
1073                 return -EIO;
1074
1075         if (!hw_lro && qlcnic_82xx_check(adapter)) {
1076                 if (qlcnic_send_lro_cleanup(adapter))
1077                         return -EIO;
1078         }
1079
1080         return 0;
1081 }
1082
1083 /*
1084  * Changes the CRB window to the specified window.
1085  */
1086  /* Returns < 0 if off is not valid,
1087  *       1 if window access is needed. 'off' is set to offset from
1088  *         CRB space in 128M pci map
1089  *       0 if no window access is needed. 'off' is set to 2M addr
1090  * In: 'off' is offset from base in 128M pci map
1091  */
1092 static int qlcnic_pci_get_crb_addr_2M(struct qlcnic_hardware_context *ahw,
1093                                       ulong off, void __iomem **addr)
1094 {
1095         const struct crb_128M_2M_sub_block_map *m;
1096
1097         if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
1098                 return -EINVAL;
1099
1100         off -= QLCNIC_PCI_CRBSPACE;
1101
1102         /*
1103          * Try direct map
1104          */
1105         m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
1106
1107         if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
1108                 *addr = ahw->pci_base0 + m->start_2M +
1109                         (off - m->start_128M);
1110                 return 0;
1111         }
1112
1113         /*
1114          * Not in direct map, use crb window
1115          */
1116         *addr = ahw->pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
1117         return 1;
1118 }
1119
1120 /*
1121  * In: 'off' is offset from CRB space in 128M pci map
1122  * Out: 'off' is 2M pci map addr
1123  * side effect: lock crb window
1124  */
1125 static int
1126 qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
1127 {
1128         u32 window;
1129         void __iomem *addr = adapter->ahw->pci_base0 + CRB_WINDOW_2M;
1130
1131         off -= QLCNIC_PCI_CRBSPACE;
1132
1133         window = CRB_HI(off);
1134         if (window == 0) {
1135                 dev_err(&adapter->pdev->dev, "Invalid offset 0x%lx\n", off);
1136                 return -EIO;
1137         }
1138
1139         writel(window, addr);
1140         if (readl(addr) != window) {
1141                 if (printk_ratelimit())
1142                         dev_warn(&adapter->pdev->dev,
1143                                 "failed to set CRB window to %d off 0x%lx\n",
1144                                 window, off);
1145                 return -EIO;
1146         }
1147         return 0;
1148 }
1149
1150 int qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off,
1151                                u32 data)
1152 {
1153         unsigned long flags;
1154         int rv;
1155         void __iomem *addr = NULL;
1156
1157         rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr);
1158
1159         if (rv == 0) {
1160                 writel(data, addr);
1161                 return 0;
1162         }
1163
1164         if (rv > 0) {
1165                 /* indirect access */
1166                 write_lock_irqsave(&adapter->ahw->crb_lock, flags);
1167                 crb_win_lock(adapter);
1168                 rv = qlcnic_pci_set_crbwindow_2M(adapter, off);
1169                 if (!rv)
1170                         writel(data, addr);
1171                 crb_win_unlock(adapter);
1172                 write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
1173                 return rv;
1174         }
1175
1176         dev_err(&adapter->pdev->dev,
1177                         "%s: invalid offset: 0x%016lx\n", __func__, off);
1178         dump_stack();
1179         return -EIO;
1180 }
1181
1182 int qlcnic_82xx_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off,
1183                               int *err)
1184 {
1185         unsigned long flags;
1186         int rv;
1187         u32 data = -1;
1188         void __iomem *addr = NULL;
1189
1190         rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr);
1191
1192         if (rv == 0)
1193                 return readl(addr);
1194
1195         if (rv > 0) {
1196                 /* indirect access */
1197                 write_lock_irqsave(&adapter->ahw->crb_lock, flags);
1198                 crb_win_lock(adapter);
1199                 if (!qlcnic_pci_set_crbwindow_2M(adapter, off))
1200                         data = readl(addr);
1201                 crb_win_unlock(adapter);
1202                 write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
1203                 return data;
1204         }
1205
1206         dev_err(&adapter->pdev->dev,
1207                         "%s: invalid offset: 0x%016lx\n", __func__, off);
1208         dump_stack();
1209         return -1;
1210 }
1211
1212 void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *ahw,
1213                                 u32 offset)
1214 {
1215         void __iomem *addr = NULL;
1216
1217         WARN_ON(qlcnic_pci_get_crb_addr_2M(ahw, offset, &addr));
1218
1219         return addr;
1220 }
1221
1222 static int qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter,
1223                                         u32 window, u64 off, u64 *data, int op)
1224 {
1225         void __iomem *addr;
1226         u32 start;
1227
1228         mutex_lock(&adapter->ahw->mem_lock);
1229
1230         writel(window, adapter->ahw->ocm_win_crb);
1231         /* read back to flush */
1232         readl(adapter->ahw->ocm_win_crb);
1233         start = QLCNIC_PCI_OCM0_2M + off;
1234
1235         addr = adapter->ahw->pci_base0 + start;
1236
1237         if (op == 0)    /* read */
1238                 *data = readq(addr);
1239         else            /* write */
1240                 writeq(*data, addr);
1241
1242         /* Set window to 0 */
1243         writel(0, adapter->ahw->ocm_win_crb);
1244         readl(adapter->ahw->ocm_win_crb);
1245
1246         mutex_unlock(&adapter->ahw->mem_lock);
1247         return 0;
1248 }
1249
1250 void
1251 qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
1252 {
1253         void __iomem *addr = adapter->ahw->pci_base0 +
1254                 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
1255
1256         mutex_lock(&adapter->ahw->mem_lock);
1257         *data = readq(addr);
1258         mutex_unlock(&adapter->ahw->mem_lock);
1259 }
1260
1261 void
1262 qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
1263 {
1264         void __iomem *addr = adapter->ahw->pci_base0 +
1265                 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
1266
1267         mutex_lock(&adapter->ahw->mem_lock);
1268         writeq(data, addr);
1269         mutex_unlock(&adapter->ahw->mem_lock);
1270 }
1271
1272
1273
1274 /* Set MS memory control data for different adapters */
1275 static void qlcnic_set_ms_controls(struct qlcnic_adapter *adapter, u64 off,
1276                                    struct qlcnic_ms_reg_ctrl *ms)
1277 {
1278         ms->control = QLCNIC_MS_CTRL;
1279         ms->low = QLCNIC_MS_ADDR_LO;
1280         ms->hi = QLCNIC_MS_ADDR_HI;
1281         if (off & 0xf) {
1282                 ms->wd[0] = QLCNIC_MS_WRTDATA_LO;
1283                 ms->rd[0] = QLCNIC_MS_RDDATA_LO;
1284                 ms->wd[1] = QLCNIC_MS_WRTDATA_HI;
1285                 ms->rd[1] = QLCNIC_MS_RDDATA_HI;
1286                 ms->wd[2] = QLCNIC_MS_WRTDATA_ULO;
1287                 ms->wd[3] = QLCNIC_MS_WRTDATA_UHI;
1288                 ms->rd[2] = QLCNIC_MS_RDDATA_ULO;
1289                 ms->rd[3] = QLCNIC_MS_RDDATA_UHI;
1290         } else {
1291                 ms->wd[0] = QLCNIC_MS_WRTDATA_ULO;
1292                 ms->rd[0] = QLCNIC_MS_RDDATA_ULO;
1293                 ms->wd[1] = QLCNIC_MS_WRTDATA_UHI;
1294                 ms->rd[1] = QLCNIC_MS_RDDATA_UHI;
1295                 ms->wd[2] = QLCNIC_MS_WRTDATA_LO;
1296                 ms->wd[3] = QLCNIC_MS_WRTDATA_HI;
1297                 ms->rd[2] = QLCNIC_MS_RDDATA_LO;
1298                 ms->rd[3] = QLCNIC_MS_RDDATA_HI;
1299         }
1300
1301         ms->ocm_window = OCM_WIN_P3P(off);
1302         ms->off = GET_MEM_OFFS_2M(off);
1303 }
1304
1305 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
1306 {
1307         int j, ret = 0;
1308         u32 temp, off8;
1309         struct qlcnic_ms_reg_ctrl ms;
1310
1311         /* Only 64-bit aligned access */
1312         if (off & 7)
1313                 return -EIO;
1314
1315         memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl));
1316         if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1317                             QLCNIC_ADDR_QDR_NET_MAX) ||
1318               ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET,
1319                             QLCNIC_ADDR_DDR_NET_MAX)))
1320                 return -EIO;
1321
1322         qlcnic_set_ms_controls(adapter, off, &ms);
1323
1324         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
1325                 return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window,
1326                                                     ms.off, &data, 1);
1327
1328         off8 = off & ~0xf;
1329
1330         mutex_lock(&adapter->ahw->mem_lock);
1331
1332         qlcnic_ind_wr(adapter, ms.low, off8);
1333         qlcnic_ind_wr(adapter, ms.hi, 0);
1334
1335         qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE);
1336         qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE);
1337
1338         for (j = 0; j < MAX_CTL_CHECK; j++) {
1339                 temp = qlcnic_ind_rd(adapter, ms.control);
1340                 if ((temp & TA_CTL_BUSY) == 0)
1341                         break;
1342         }
1343
1344         if (j >= MAX_CTL_CHECK) {
1345                 ret = -EIO;
1346                 goto done;
1347         }
1348
1349         /* This is the modify part of read-modify-write */
1350         qlcnic_ind_wr(adapter, ms.wd[0], qlcnic_ind_rd(adapter, ms.rd[0]));
1351         qlcnic_ind_wr(adapter, ms.wd[1], qlcnic_ind_rd(adapter, ms.rd[1]));
1352         /* This is the write part of read-modify-write */
1353         qlcnic_ind_wr(adapter, ms.wd[2], data & 0xffffffff);
1354         qlcnic_ind_wr(adapter, ms.wd[3], (data >> 32) & 0xffffffff);
1355
1356         qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_ENABLE);
1357         qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_START);
1358
1359         for (j = 0; j < MAX_CTL_CHECK; j++) {
1360                 temp = qlcnic_ind_rd(adapter, ms.control);
1361                 if ((temp & TA_CTL_BUSY) == 0)
1362                         break;
1363         }
1364
1365         if (j >= MAX_CTL_CHECK) {
1366                 if (printk_ratelimit())
1367                         dev_err(&adapter->pdev->dev,
1368                                         "failed to write through agent\n");
1369                 ret = -EIO;
1370         } else
1371                 ret = 0;
1372
1373 done:
1374         mutex_unlock(&adapter->ahw->mem_lock);
1375
1376         return ret;
1377 }
1378
1379 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
1380 {
1381         int j, ret;
1382         u32 temp, off8;
1383         u64 val;
1384         struct qlcnic_ms_reg_ctrl ms;
1385
1386         /* Only 64-bit aligned access */
1387         if (off & 7)
1388                 return -EIO;
1389         if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1390                             QLCNIC_ADDR_QDR_NET_MAX) ||
1391               ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET,
1392                             QLCNIC_ADDR_DDR_NET_MAX)))
1393                 return -EIO;
1394
1395         memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl));
1396         qlcnic_set_ms_controls(adapter, off, &ms);
1397
1398         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
1399                 return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window,
1400                                                     ms.off, data, 0);
1401
1402         mutex_lock(&adapter->ahw->mem_lock);
1403
1404         off8 = off & ~0xf;
1405
1406         qlcnic_ind_wr(adapter, ms.low, off8);
1407         qlcnic_ind_wr(adapter, ms.hi, 0);
1408
1409         qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE);
1410         qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE);
1411
1412         for (j = 0; j < MAX_CTL_CHECK; j++) {
1413                 temp = qlcnic_ind_rd(adapter, ms.control);
1414                 if ((temp & TA_CTL_BUSY) == 0)
1415                         break;
1416         }
1417
1418         if (j >= MAX_CTL_CHECK) {
1419                 if (printk_ratelimit())
1420                         dev_err(&adapter->pdev->dev,
1421                                         "failed to read through agent\n");
1422                 ret = -EIO;
1423         } else {
1424
1425                 temp = qlcnic_ind_rd(adapter, ms.rd[3]);
1426                 val = (u64)temp << 32;
1427                 val |= qlcnic_ind_rd(adapter, ms.rd[2]);
1428                 *data = val;
1429                 ret = 0;
1430         }
1431
1432         mutex_unlock(&adapter->ahw->mem_lock);
1433
1434         return ret;
1435 }
1436
1437 int qlcnic_82xx_get_board_info(struct qlcnic_adapter *adapter)
1438 {
1439         int offset, board_type, magic, err = 0;
1440         struct pci_dev *pdev = adapter->pdev;
1441
1442         offset = QLCNIC_FW_MAGIC_OFFSET;
1443         if (qlcnic_rom_fast_read(adapter, offset, &magic))
1444                 return -EIO;
1445
1446         if (magic != QLCNIC_BDINFO_MAGIC) {
1447                 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1448                         magic);
1449                 return -EIO;
1450         }
1451
1452         offset = QLCNIC_BRDTYPE_OFFSET;
1453         if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1454                 return -EIO;
1455
1456         adapter->ahw->board_type = board_type;
1457
1458         if (board_type == QLCNIC_BRDTYPE_P3P_4_GB_MM) {
1459                 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I, &err);
1460                 if (err == -EIO)
1461                         return err;
1462                 if ((gpio & 0x8000) == 0)
1463                         board_type = QLCNIC_BRDTYPE_P3P_10G_TP;
1464         }
1465
1466         switch (board_type) {
1467         case QLCNIC_BRDTYPE_P3P_HMEZ:
1468         case QLCNIC_BRDTYPE_P3P_XG_LOM:
1469         case QLCNIC_BRDTYPE_P3P_10G_CX4:
1470         case QLCNIC_BRDTYPE_P3P_10G_CX4_LP:
1471         case QLCNIC_BRDTYPE_P3P_IMEZ:
1472         case QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS:
1473         case QLCNIC_BRDTYPE_P3P_10G_SFP_CT:
1474         case QLCNIC_BRDTYPE_P3P_10G_SFP_QT:
1475         case QLCNIC_BRDTYPE_P3P_10G_XFP:
1476         case QLCNIC_BRDTYPE_P3P_10000_BASE_T:
1477                 adapter->ahw->port_type = QLCNIC_XGBE;
1478                 break;
1479         case QLCNIC_BRDTYPE_P3P_REF_QG:
1480         case QLCNIC_BRDTYPE_P3P_4_GB:
1481         case QLCNIC_BRDTYPE_P3P_4_GB_MM:
1482                 adapter->ahw->port_type = QLCNIC_GBE;
1483                 break;
1484         case QLCNIC_BRDTYPE_P3P_10G_TP:
1485                 adapter->ahw->port_type = (adapter->portnum < 2) ?
1486                         QLCNIC_XGBE : QLCNIC_GBE;
1487                 break;
1488         default:
1489                 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1490                 adapter->ahw->port_type = QLCNIC_XGBE;
1491                 break;
1492         }
1493
1494         return 0;
1495 }
1496
1497 int
1498 qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1499 {
1500         u32 wol_cfg;
1501         int err = 0;
1502
1503         wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV, &err);
1504         if (wol_cfg & (1UL << adapter->portnum)) {
1505                 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG, &err);
1506                 if (err == -EIO)
1507                         return err;
1508                 if (wol_cfg & (1 << adapter->portnum))
1509                         return 1;
1510         }
1511
1512         return 0;
1513 }
1514
1515 int qlcnic_82xx_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
1516 {
1517         struct qlcnic_nic_req   req;
1518         int rv;
1519         u64 word;
1520
1521         memset(&req, 0, sizeof(struct qlcnic_nic_req));
1522         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1523
1524         word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1525         req.req_hdr = cpu_to_le64(word);
1526
1527         req.words[0] = cpu_to_le64(((u64)rate << 32) | adapter->portnum);
1528         req.words[1] = cpu_to_le64(state);
1529
1530         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1531         if (rv)
1532                 dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1533
1534         return rv;
1535 }
1536
1537 int qlcnic_get_beacon_state(struct qlcnic_adapter *adapter, u8 *h_state)
1538 {
1539         struct qlcnic_cmd_args cmd;
1540         int err;
1541
1542         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LED_STATUS);
1543         if (!err) {
1544                 err = qlcnic_issue_cmd(adapter, &cmd);
1545                 if (!err)
1546                         *h_state = cmd.rsp.arg[1];
1547         }
1548         qlcnic_free_mbx_args(&cmd);
1549         return err;
1550 }
1551
1552 void qlcnic_82xx_get_func_no(struct qlcnic_adapter *adapter)
1553 {
1554         void __iomem *msix_base_addr;
1555         u32 func;
1556         u32 msix_base;
1557
1558         pci_read_config_dword(adapter->pdev, QLCNIC_MSIX_TABLE_OFFSET, &func);
1559         msix_base_addr = adapter->ahw->pci_base0 + QLCNIC_MSIX_BASE;
1560         msix_base = readl(msix_base_addr);
1561         func = (func - msix_base) / QLCNIC_MSIX_TBL_PGSIZE;
1562         adapter->ahw->pci_func = func;
1563 }
1564
1565 void qlcnic_82xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
1566                           loff_t offset, size_t size)
1567 {
1568         int err = 0;
1569         u32 data;
1570         u64 qmdata;
1571
1572         if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) {
1573                 qlcnic_pci_camqm_read_2M(adapter, offset, &qmdata);
1574                 memcpy(buf, &qmdata, size);
1575         } else {
1576                 data = QLCRD32(adapter, offset, &err);
1577                 memcpy(buf, &data, size);
1578         }
1579 }
1580
1581 void qlcnic_82xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
1582                            loff_t offset, size_t size)
1583 {
1584         u32 data;
1585         u64 qmdata;
1586
1587         if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) {
1588                 memcpy(&qmdata, buf, size);
1589                 qlcnic_pci_camqm_write_2M(adapter, offset, qmdata);
1590         } else {
1591                 memcpy(&data, buf, size);
1592                 QLCWR32(adapter, offset, data);
1593         }
1594 }
1595
1596 int qlcnic_82xx_api_lock(struct qlcnic_adapter *adapter)
1597 {
1598         return qlcnic_pcie_sem_lock(adapter, 5, 0);
1599 }
1600
1601 void qlcnic_82xx_api_unlock(struct qlcnic_adapter *adapter)
1602 {
1603         qlcnic_pcie_sem_unlock(adapter, 5);
1604 }
1605
1606 int qlcnic_82xx_shutdown(struct pci_dev *pdev)
1607 {
1608         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
1609         struct net_device *netdev = adapter->netdev;
1610         int retval;
1611
1612         netif_device_detach(netdev);
1613
1614         qlcnic_cancel_idc_work(adapter);
1615
1616         if (netif_running(netdev))
1617                 qlcnic_down(adapter, netdev);
1618
1619         qlcnic_clr_all_drv_state(adapter, 0);
1620
1621         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1622
1623         retval = pci_save_state(pdev);
1624         if (retval)
1625                 return retval;
1626
1627         if (qlcnic_wol_supported(adapter)) {
1628                 pci_enable_wake(pdev, PCI_D3cold, 1);
1629                 pci_enable_wake(pdev, PCI_D3hot, 1);
1630         }
1631
1632         return 0;
1633 }
1634
1635 int qlcnic_82xx_resume(struct qlcnic_adapter *adapter)
1636 {
1637         struct net_device *netdev = adapter->netdev;
1638         int err;
1639
1640         err = qlcnic_start_firmware(adapter);
1641         if (err) {
1642                 dev_err(&adapter->pdev->dev, "failed to start firmware\n");
1643                 return err;
1644         }
1645
1646         if (netif_running(netdev)) {
1647                 err = qlcnic_up(adapter, netdev);
1648                 if (!err)
1649                         qlcnic_restore_indev_addr(netdev, NETDEV_UP);
1650         }
1651
1652         netif_device_attach(netdev);
1653         qlcnic_schedule_work(adapter, qlcnic_fw_poll_work, FW_POLL_DELAY);
1654         return err;
1655 }