drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include "qlcnic.h"
   9 #include "qlcnic_sriov.h"
  10 #include <linux/if_vlan.h>
  11 #include <linux/ipv6.h>
  12 #include <linux/ethtool.h>
  13 #include <linux/interrupt.h>
  14
  15 #define QLCNIC_MAX_TX_QUEUES            1
  16 #define RSS_HASHTYPE_IP_TCP             0x3
  17
  18 /* status descriptor mailbox data
  19  * @phy_addr_{low|high}: physical address of buffer
  20  * @sds_ring_size: buffer size
  21  * @intrpt_id: interrupt id
  22  * @intrpt_val: source of interrupt
  23  */
  24 struct qlcnic_sds_mbx {
  25         u32     phy_addr_low;
  26         u32     phy_addr_high;
  27         u32     rsvd1[4];
  28 #if defined(__LITTLE_ENDIAN)
  29         u16     sds_ring_size;
  30         u16     rsvd2;
  31         u16     rsvd3[2];
  32         u16     intrpt_id;
  33         u8      intrpt_val;
  34         u8      rsvd4;
  35 #elif defined(__BIG_ENDIAN)
  36         u16     rsvd2;
  37         u16     sds_ring_size;
  38         u16     rsvd3[2];
  39         u8      rsvd4;
  40         u8      intrpt_val;
  41         u16     intrpt_id;
  42 #endif
  43         u32     rsvd5;
  44 } __packed;
  45
  46 /* receive descriptor buffer data
  47  * phy_addr_reg_{low|high}: physical address of regular buffer
  48  * phy_addr_jmb_{low|high}: physical address of jumbo buffer
  49  * reg_ring_sz: size of regular buffer
  50  * reg_ring_len: no. of entries in regular buffer
  51  * jmb_ring_len: no. of entries in jumbo buffer
  52  * jmb_ring_sz: size of jumbo buffer
  53  */
  54 struct qlcnic_rds_mbx {
  55         u32     phy_addr_reg_low;
  56         u32     phy_addr_reg_high;
  57         u32     phy_addr_jmb_low;
  58         u32     phy_addr_jmb_high;
  59 #if defined(__LITTLE_ENDIAN)
  60         u16     reg_ring_sz;
  61         u16     reg_ring_len;
  62         u16     jmb_ring_sz;
  63         u16     jmb_ring_len;
  64 #elif defined(__BIG_ENDIAN)
  65         u16     reg_ring_len;
  66         u16     reg_ring_sz;
  67         u16     jmb_ring_len;
  68         u16     jmb_ring_sz;
  69 #endif
  70 } __packed;
  71
  72 /* host producers for regular and jumbo rings */
  73 struct __host_producer_mbx {
  74         u32     reg_buf;
  75         u32     jmb_buf;
  76 } __packed;
  77
  78 /* Receive context mailbox data outbox registers
  79  * @state: state of the context
  80  * @vport_id: virtual port id
  81  * @context_id: receive context id
  82  * @num_pci_func: number of pci functions of the port
  83  * @phy_port: physical port id
  84  */
  85 struct qlcnic_rcv_mbx_out {
  86 #if defined(__LITTLE_ENDIAN)
  87         u8      rcv_num;
  88         u8      sts_num;
  89         u16     ctx_id;
  90         u8      state;
  91         u8      num_pci_func;
  92         u8      phy_port;
  93         u8      vport_id;
  94 #elif defined(__BIG_ENDIAN)
  95         u16     ctx_id;
  96         u8      sts_num;
  97         u8      rcv_num;
  98         u8      vport_id;
  99         u8      phy_port;
 100         u8      num_pci_func;
 101         u8      state;
 102 #endif
 103         u32     host_csmr[QLCNIC_MAX_RING_SETS];
 104         struct __host_producer_mbx host_prod[QLCNIC_MAX_RING_SETS];
 105 } __packed;
 106
 107 struct qlcnic_add_rings_mbx_out {
 108 #if defined(__LITTLE_ENDIAN)
 109         u8      rcv_num;
 110         u8      sts_num;
 111         u16     ctx_id;
 112 #elif defined(__BIG_ENDIAN)
 113         u16     ctx_id;
 114         u8      sts_num;
 115         u8      rcv_num;
 116 #endif
 117         u32  host_csmr[QLCNIC_MAX_RING_SETS];
 118         struct __host_producer_mbx host_prod[QLCNIC_MAX_RING_SETS];
 119 } __packed;
 120
 121 /* Transmit context mailbox inbox registers
 122  * @phys_addr_{low|high}: DMA address of the transmit buffer
 123  * @cnsmr_index_{low|high}: host consumer index
 124  * @size: legth of transmit buffer ring
 125  * @intr_id: interrput id
 126  * @src: src of interrupt
 127  */
 128 struct qlcnic_tx_mbx {
 129         u32     phys_addr_low;
 130         u32     phys_addr_high;
 131         u32     cnsmr_index_low;
 132         u32     cnsmr_index_high;
 133 #if defined(__LITTLE_ENDIAN)
 134         u16     size;
 135         u16     intr_id;
 136         u8      src;
 137         u8      rsvd[3];
 138 #elif defined(__BIG_ENDIAN)
 139         u16     intr_id;
 140         u16     size;
 141         u8      rsvd[3];
 142         u8      src;
 143 #endif
 144 } __packed;
 145
 146 /* Transmit context mailbox outbox registers
 147  * @host_prod: host producer index
 148  * @ctx_id: transmit context id
 149  * @state: state of the transmit context
 150  */
 151
 152 struct qlcnic_tx_mbx_out {
 153         u32     host_prod;
 154 #if defined(__LITTLE_ENDIAN)
 155         u16     ctx_id;
 156         u8      state;
 157         u8      rsvd;
 158 #elif defined(__BIG_ENDIAN)
 159         u8      rsvd;
 160         u8      state;
 161         u16     ctx_id;
 162 #endif
 163 } __packed;
 164
 165 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
 166         {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1},
 167         {QLCNIC_CMD_CONFIG_INTRPT, 18, 34},
 168         {QLCNIC_CMD_CREATE_RX_CTX, 136, 27},
 169         {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
 170         {QLCNIC_CMD_CREATE_TX_CTX, 54, 18},
 171         {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
 172         {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1},
 173         {QLCNIC_CMD_INTRPT_TEST, 22, 12},
 174         {QLCNIC_CMD_SET_MTU, 3, 1},
 175         {QLCNIC_CMD_READ_PHY, 4, 2},
 176         {QLCNIC_CMD_WRITE_PHY, 5, 1},
 177         {QLCNIC_CMD_READ_HW_REG, 4, 1},
 178         {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
 179         {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
 180         {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
 181         {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
 182         {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
 183         {QLCNIC_CMD_GET_PCI_INFO, 1, 66},
 184         {QLCNIC_CMD_GET_NIC_INFO, 2, 19},
 185         {QLCNIC_CMD_SET_NIC_INFO, 32, 1},
 186         {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
 187         {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
 188         {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
 189         {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
 190         {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
 191         {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
 192         {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
 193         {QLCNIC_CMD_CONFIG_PORT, 4, 1},
 194         {QLCNIC_CMD_TEMP_SIZE, 1, 4},
 195         {QLCNIC_CMD_GET_TEMP_HDR, 5, 5},
 196         {QLCNIC_CMD_GET_LINK_EVENT, 2, 1},
 197         {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3},
 198         {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1},
 199         {QLCNIC_CMD_CONFIGURE_RSS, 14, 1},
 200         {QLCNIC_CMD_CONFIGURE_LED, 2, 1},
 201         {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1},
 202         {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1},
 203         {QLCNIC_CMD_GET_STATISTICS, 2, 80},
 204         {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1},
 205         {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2},
 206         {QLCNIC_CMD_GET_LINK_STATUS, 2, 4},
 207         {QLCNIC_CMD_IDC_ACK, 5, 1},
 208         {QLCNIC_CMD_INIT_NIC_FUNC, 2, 1},
 209         {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1},
 210         {QLCNIC_CMD_SET_LED_CONFIG, 5, 1},
 211         {QLCNIC_CMD_GET_LED_CONFIG, 1, 5},
 212         {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26},
 213         {QLCNIC_CMD_CONFIG_VPORT, 4, 4},
 214 };
 215
 216 const u32 qlcnic_83xx_ext_reg_tbl[] = {
 217         0x38CC,         /* Global Reset */
 218         0x38F0,         /* Wildcard */
 219         0x38FC,         /* Informant */
 220         0x3038,         /* Host MBX ctrl */
 221         0x303C,         /* FW MBX ctrl */
 222         0x355C,         /* BOOT LOADER ADDRESS REG */
 223         0x3560,         /* BOOT LOADER SIZE REG */
 224         0x3564,         /* FW IMAGE ADDR REG */
 225         0x1000,         /* MBX intr enable */
 226         0x1200,         /* Default Intr mask */
 227         0x1204,         /* Default Interrupt ID */
 228         0x3780,         /* QLC_83XX_IDC_MAJ_VERSION */
 229         0x3784,         /* QLC_83XX_IDC_DEV_STATE */
 230         0x3788,         /* QLC_83XX_IDC_DRV_PRESENCE */
 231         0x378C,         /* QLC_83XX_IDC_DRV_ACK */
 232         0x3790,         /* QLC_83XX_IDC_CTRL */
 233         0x3794,         /* QLC_83XX_IDC_DRV_AUDIT */
 234         0x3798,         /* QLC_83XX_IDC_MIN_VERSION */
 235         0x379C,         /* QLC_83XX_RECOVER_DRV_LOCK */
 236         0x37A0,         /* QLC_83XX_IDC_PF_0 */
 237         0x37A4,         /* QLC_83XX_IDC_PF_1 */
 238         0x37A8,         /* QLC_83XX_IDC_PF_2 */
 239         0x37AC,         /* QLC_83XX_IDC_PF_3 */
 240         0x37B0,         /* QLC_83XX_IDC_PF_4 */
 241         0x37B4,         /* QLC_83XX_IDC_PF_5 */
 242         0x37B8,         /* QLC_83XX_IDC_PF_6 */
 243         0x37BC,         /* QLC_83XX_IDC_PF_7 */
 244         0x37C0,         /* QLC_83XX_IDC_PF_8 */
 245         0x37C4,         /* QLC_83XX_IDC_PF_9 */
 246         0x37C8,         /* QLC_83XX_IDC_PF_10 */
 247         0x37CC,         /* QLC_83XX_IDC_PF_11 */
 248         0x37D0,         /* QLC_83XX_IDC_PF_12 */
 249         0x37D4,         /* QLC_83XX_IDC_PF_13 */
 250         0x37D8,         /* QLC_83XX_IDC_PF_14 */
 251         0x37DC,         /* QLC_83XX_IDC_PF_15 */
 252         0x37E0,         /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
 253         0x37E4,         /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
 254         0x37F0,         /* QLC_83XX_DRV_OP_MODE */
 255         0x37F4,         /* QLC_83XX_VNIC_STATE */
 256         0x3868,         /* QLC_83XX_DRV_LOCK */
 257         0x386C,         /* QLC_83XX_DRV_UNLOCK */
 258         0x3504,         /* QLC_83XX_DRV_LOCK_ID */
 259         0x34A4,         /* QLC_83XX_ASIC_TEMP */
 260 };
 261
 262 const u32 qlcnic_83xx_reg_tbl[] = {
 263         0x34A8,         /* PEG_HALT_STAT1 */
 264         0x34AC,         /* PEG_HALT_STAT2 */
 265         0x34B0,         /* FW_HEARTBEAT */
 266         0x3500,         /* FLASH LOCK_ID */
 267         0x3528,         /* FW_CAPABILITIES */
 268         0x3538,         /* Driver active, DRV_REG0 */
 269         0x3540,         /* Device state, DRV_REG1 */
 270         0x3544,         /* Driver state, DRV_REG2 */
 271         0x3548,         /* Driver scratch, DRV_REG3 */
 272         0x354C,         /* Device partiton info, DRV_REG4 */
 273         0x3524,         /* Driver IDC ver, DRV_REG5 */
 274         0x3550,         /* FW_VER_MAJOR */
 275         0x3554,         /* FW_VER_MINOR */
 276         0x3558,         /* FW_VER_SUB */
 277         0x359C,         /* NPAR STATE */
 278         0x35FC,         /* FW_IMG_VALID */
 279         0x3650,         /* CMD_PEG_STATE */
 280         0x373C,         /* RCV_PEG_STATE */
 281         0x37B4,         /* ASIC TEMP */
 282         0x356C,         /* FW API */
 283         0x3570,         /* DRV OP MODE */
 284         0x3850,         /* FLASH LOCK */
 285         0x3854,         /* FLASH UNLOCK */
 286 };
 287
 288 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = {
 289         .read_crb                       = qlcnic_83xx_read_crb,
 290         .write_crb                      = qlcnic_83xx_write_crb,
 291         .read_reg                       = qlcnic_83xx_rd_reg_indirect,
 292         .write_reg                      = qlcnic_83xx_wrt_reg_indirect,
 293         .get_mac_address                = qlcnic_83xx_get_mac_address,
 294         .setup_intr                     = qlcnic_83xx_setup_intr,
 295         .alloc_mbx_args                 = qlcnic_83xx_alloc_mbx_args,
 296         .mbx_cmd                        = qlcnic_83xx_mbx_op,
 297         .get_func_no                    = qlcnic_83xx_get_func_no,
 298         .api_lock                       = qlcnic_83xx_cam_lock,
 299         .api_unlock                     = qlcnic_83xx_cam_unlock,
 300         .add_sysfs                      = qlcnic_83xx_add_sysfs,
 301         .remove_sysfs                   = qlcnic_83xx_remove_sysfs,
 302         .process_lb_rcv_ring_diag       = qlcnic_83xx_process_rcv_ring_diag,
 303         .create_rx_ctx                  = qlcnic_83xx_create_rx_ctx,
 304         .create_tx_ctx                  = qlcnic_83xx_create_tx_ctx,
 305         .setup_link_event               = qlcnic_83xx_setup_link_event,
 306         .get_nic_info                   = qlcnic_83xx_get_nic_info,
 307         .get_pci_info                   = qlcnic_83xx_get_pci_info,
 308         .set_nic_info                   = qlcnic_83xx_set_nic_info,
 309         .change_macvlan                 = qlcnic_83xx_sre_macaddr_change,
 310         .napi_enable                    = qlcnic_83xx_napi_enable,
 311         .napi_disable                   = qlcnic_83xx_napi_disable,
 312         .config_intr_coal               = qlcnic_83xx_config_intr_coal,
 313         .config_rss                     = qlcnic_83xx_config_rss,
 314         .config_hw_lro                  = qlcnic_83xx_config_hw_lro,
 315         .config_promisc_mode            = qlcnic_83xx_nic_set_promisc,
 316         .change_l2_filter               = qlcnic_83xx_change_l2_filter,
 317         .get_board_info                 = qlcnic_83xx_get_port_info,
 318 };
 319
 320 static struct qlcnic_nic_template qlcnic_83xx_ops = {
 321         .config_bridged_mode    = qlcnic_config_bridged_mode,
 322         .config_led             = qlcnic_config_led,
 323         .request_reset          = qlcnic_83xx_idc_request_reset,
 324         .cancel_idc_work        = qlcnic_83xx_idc_exit,
 325         .napi_add               = qlcnic_83xx_napi_add,
 326         .napi_del               = qlcnic_83xx_napi_del,
 327         .config_ipaddr          = qlcnic_83xx_config_ipaddr,
 328         .clear_legacy_intr      = qlcnic_83xx_clear_legacy_intr,
 329 };
 330
 331 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw)
 332 {
 333         ahw->hw_ops             = &qlcnic_83xx_hw_ops;
 334         ahw->reg_tbl            = (u32 *)qlcnic_83xx_reg_tbl;
 335         ahw->ext_reg_tbl        = (u32 *)qlcnic_83xx_ext_reg_tbl;
 336 }
 337
 338 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter)
 339 {
 340         u32 fw_major, fw_minor, fw_build;
 341         struct pci_dev *pdev = adapter->pdev;
 342
 343         fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
 344         fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
 345         fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
 346         adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build);
 347
 348         dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n",
 349                  QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build);
 350
 351         return adapter->fw_version;
 352 }
 353
 354 static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr)
 355 {
 356         void __iomem *base;
 357         u32 val;
 358
 359         base = adapter->ahw->pci_base0 +
 360                QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func);
 361         writel(addr, base);
 362         val = readl(base);
 363         if (val != addr)
 364                 return -EIO;
 365
 366         return 0;
 367 }
 368
 369 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr)
 370 {
 371         int ret;
 372         struct qlcnic_hardware_context *ahw = adapter->ahw;
 373
 374         ret = __qlcnic_set_win_base(adapter, (u32) addr);
 375         if (!ret) {
 376                 return QLCRDX(ahw, QLCNIC_WILDCARD);
 377         } else {
 378                 dev_err(&adapter->pdev->dev,
 379                         "%s failed, addr = 0x%x\n", __func__, (int)addr);
 380                 return -EIO;
 381         }
 382 }
 383
 384 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
 385                                  u32 data)
 386 {
 387         int err;
 388         struct qlcnic_hardware_context *ahw = adapter->ahw;
 389
 390         err = __qlcnic_set_win_base(adapter, (u32) addr);
 391         if (!err) {
 392                 QLCWRX(ahw, QLCNIC_WILDCARD, data);
 393                 return 0;
 394         } else {
 395                 dev_err(&adapter->pdev->dev,
 396                         "%s failed, addr = 0x%x data = 0x%x\n",
 397                         __func__, (int)addr, data);
 398                 return err;
 399         }
 400 }
 401
 402 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter, u8 num_intr)
 403 {
 404         int err, i, num_msix;
 405         struct qlcnic_hardware_context *ahw = adapter->ahw;
 406
 407         if (!num_intr)
 408                 num_intr = QLCNIC_DEF_NUM_STS_DESC_RINGS;
 409         num_msix = rounddown_pow_of_two(min_t(int, num_online_cpus(),
 410                                               num_intr));
 411         /* account for AEN interrupt MSI-X based interrupts */
 412         num_msix += 1;
 413
 414         if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
 415                 num_msix += adapter->max_drv_tx_rings;
 416
 417         err = qlcnic_enable_msix(adapter, num_msix);
 418         if (err == -ENOMEM)
 419                 return err;
 420         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 421                 num_msix = adapter->ahw->num_msix;
 422         else {
 423                 if (qlcnic_sriov_vf_check(adapter))
 424                         return -EINVAL;
 425                 num_msix = 1;
 426         }
 427         /* setup interrupt mapping table for fw */
 428         ahw->intr_tbl = vzalloc(num_msix *
 429                                 sizeof(struct qlcnic_intrpt_config));
 430         if (!ahw->intr_tbl)
 431                 return -ENOMEM;
 432         if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
 433                 /* MSI-X enablement failed, use legacy interrupt */
 434                 adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR;
 435                 adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK;
 436                 adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR;
 437                 adapter->msix_entries[0].vector = adapter->pdev->irq;
 438                 dev_info(&adapter->pdev->dev, "using legacy interrupt\n");
 439         }
 440
 441         for (i = 0; i < num_msix; i++) {
 442                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
 443                         ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX;
 444                 else
 445                         ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX;
 446                 ahw->intr_tbl[i].id = i;
 447                 ahw->intr_tbl[i].src = 0;
 448         }
 449         return 0;
 450 }
 451
 452 inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter)
 453 {
 454         writel(0, adapter->tgt_mask_reg);
 455 }
 456
 457 /* Enable MSI-x and INT-x interrupts */
 458 void qlcnic_83xx_enable_intr(struct qlcnic_adapter *adapter,
 459                              struct qlcnic_host_sds_ring *sds_ring)
 460 {
 461         writel(0, sds_ring->crb_intr_mask);
 462 }
 463
 464 /* Disable MSI-x and INT-x interrupts */
 465 void qlcnic_83xx_disable_intr(struct qlcnic_adapter *adapter,
 466                               struct qlcnic_host_sds_ring *sds_ring)
 467 {
 468         writel(1, sds_ring->crb_intr_mask);
 469 }
 470
 471 inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
 472                                                     *adapter)
 473 {
 474         u32 mask;
 475
 476         /* Mailbox in MSI-x mode and Legacy Interrupt share the same
 477          * source register. We could be here before contexts are created
 478          * and sds_ring->crb_intr_mask has not been initialized, calculate
 479          * BAR offset for Interrupt Source Register
 480          */
 481         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
 482         writel(0, adapter->ahw->pci_base0 + mask);
 483 }
 484
 485 inline void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter)
 486 {
 487         u32 mask;
 488
 489         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
 490         writel(1, adapter->ahw->pci_base0 + mask);
 491 }
 492
 493 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter,
 494                                      struct qlcnic_cmd_args *cmd)
 495 {
 496         int i;
 497         for (i = 0; i < cmd->rsp.num; i++)
 498                 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i));
 499 }
 500
 501 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
 502 {
 503         u32 intr_val;
 504         struct qlcnic_hardware_context *ahw = adapter->ahw;
 505         int retries = 0;
 506
 507         intr_val = readl(adapter->tgt_status_reg);
 508
 509         if (!QLC_83XX_VALID_INTX_BIT31(intr_val))
 510                 return IRQ_NONE;
 511
 512         if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) {
 513                 adapter->stats.spurious_intr++;
 514                 return IRQ_NONE;
 515         }
 516         /* The barrier is required to ensure writes to the registers */
 517         wmb();
 518
 519         /* clear the interrupt trigger control register */
 520         writel(0, adapter->isr_int_vec);
 521         intr_val = readl(adapter->isr_int_vec);
 522         do {
 523                 intr_val = readl(adapter->tgt_status_reg);
 524                 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func)
 525                         break;
 526                 retries++;
 527         } while (QLC_83XX_VALID_INTX_BIT30(intr_val) &&
 528                  (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY));
 529
 530         return IRQ_HANDLED;
 531 }
 532
 533 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter)
 534 {
 535         u32 resp, event;
 536         unsigned long flags;
 537
 538         spin_lock_irqsave(&adapter->ahw->mbx_lock, flags);
 539
 540         resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
 541         if (!(resp & QLCNIC_SET_OWNER))
 542                 goto out;
 543
 544         event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
 545         if (event &  QLCNIC_MBX_ASYNC_EVENT)
 546                 qlcnic_83xx_process_aen(adapter);
 547 out:
 548         qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 549         spin_unlock_irqrestore(&adapter->ahw->mbx_lock, flags);
 550 }
 551
 552 irqreturn_t qlcnic_83xx_intr(int irq, void *data)
 553 {
 554         struct qlcnic_adapter *adapter = data;
 555         struct qlcnic_host_sds_ring *sds_ring;
 556         struct qlcnic_hardware_context *ahw = adapter->ahw;
 557
 558         if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE)
 559                 return IRQ_NONE;
 560
 561         qlcnic_83xx_poll_process_aen(adapter);
 562
 563         if (ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
 564                 ahw->diag_cnt++;
 565                 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 566                 return IRQ_HANDLED;
 567         }
 568
 569         if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
 570                 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 571         } else {
 572                 sds_ring = &adapter->recv_ctx->sds_rings[0];
 573                 napi_schedule(&sds_ring->napi);
 574         }
 575
 576         return IRQ_HANDLED;
 577 }
 578
 579 irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data)
 580 {
 581         struct qlcnic_host_sds_ring *sds_ring = data;
 582         struct qlcnic_adapter *adapter = sds_ring->adapter;
 583
 584         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 585                 goto done;
 586
 587         if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE)
 588                 return IRQ_NONE;
 589
 590 done:
 591         adapter->ahw->diag_cnt++;
 592         qlcnic_83xx_enable_intr(adapter, sds_ring);
 593
 594         return IRQ_HANDLED;
 595 }
 596
 597 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter)
 598 {
 599         u32 val = 0, num_msix = adapter->ahw->num_msix - 1;
 600
 601         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 602                 num_msix = adapter->ahw->num_msix - 1;
 603         else
 604                 num_msix = 0;
 605
 606         QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
 607
 608         qlcnic_83xx_disable_mbx_intr(adapter);
 609
 610         msleep(20);
 611         synchronize_irq(adapter->msix_entries[num_msix].vector);
 612         free_irq(adapter->msix_entries[num_msix].vector, adapter);
 613 }
 614
 615 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter)
 616 {
 617         irq_handler_t handler;
 618         u32 val;
 619         char name[32];
 620         int err = 0;
 621         unsigned long flags = 0;
 622
 623         if (!(adapter->flags & QLCNIC_MSI_ENABLED) &&
 624             !(adapter->flags & QLCNIC_MSIX_ENABLED))
 625                 flags |= IRQF_SHARED;
 626
 627         if (adapter->flags & QLCNIC_MSIX_ENABLED) {
 628                 handler = qlcnic_83xx_handle_aen;
 629                 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector;
 630                 snprintf(name, (IFNAMSIZ + 4),
 631                          "%s[%s]", "qlcnic", "aen");
 632                 err = request_irq(val, handler, flags, name, adapter);
 633                 if (err) {
 634                         dev_err(&adapter->pdev->dev,
 635                                 "failed to register MBX interrupt\n");
 636                         return err;
 637                 }
 638         } else {
 639                 handler = qlcnic_83xx_intr;
 640                 val = adapter->msix_entries[0].vector;
 641                 err = request_irq(val, handler, flags, "qlcnic", adapter);
 642                 if (err) {
 643                         dev_err(&adapter->pdev->dev,
 644                                 "failed to register INTx interrupt\n");
 645                         return err;
 646                 }
 647                 qlcnic_83xx_clear_legacy_intr_mask(adapter);
 648         }
 649
 650         /* Enable mailbox interrupt */
 651         qlcnic_83xx_enable_mbx_intrpt(adapter);
 652
 653         return err;
 654 }
 655
 656 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter)
 657 {
 658         u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT);
 659         adapter->ahw->pci_func = (val >> 24) & 0xff;
 660 }
 661
 662 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter)
 663 {
 664         void __iomem *addr;
 665         u32 val, limit = 0;
 666
 667         struct qlcnic_hardware_context *ahw = adapter->ahw;
 668
 669         addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func);
 670         do {
 671                 val = readl(addr);
 672                 if (val) {
 673                         /* write the function number to register */
 674                         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
 675                                             ahw->pci_func);
 676                         return 0;
 677                 }
 678                 usleep_range(1000, 2000);
 679         } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT);
 680
 681         return -EIO;
 682 }
 683
 684 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter)
 685 {
 686         void __iomem *addr;
 687         u32 val;
 688         struct qlcnic_hardware_context *ahw = adapter->ahw;
 689
 690         addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func);
 691         val = readl(addr);
 692 }
 693
 694 void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
 695                           loff_t offset, size_t size)
 696 {
 697         int ret;
 698         u32 data;
 699
 700         if (qlcnic_api_lock(adapter)) {
 701                 dev_err(&adapter->pdev->dev,
 702                         "%s: failed to acquire lock. addr offset 0x%x\n",
 703                         __func__, (u32)offset);
 704                 return;
 705         }
 706
 707         ret = qlcnic_83xx_rd_reg_indirect(adapter, (u32) offset);
 708         qlcnic_api_unlock(adapter);
 709
 710         if (ret == -EIO) {
 711                 dev_err(&adapter->pdev->dev,
 712                         "%s: failed. addr offset 0x%x\n",
 713                         __func__, (u32)offset);
 714                 return;
 715         }
 716         data = ret;
 717         memcpy(buf, &data, size);
 718 }
 719
 720 void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
 721                            loff_t offset, size_t size)
 722 {
 723         u32 data;
 724
 725         memcpy(&data, buf, size);
 726         qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data);
 727 }
 728
 729 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
 730 {
 731         int status;
 732
 733         status = qlcnic_83xx_get_port_config(adapter);
 734         if (status) {
 735                 dev_err(&adapter->pdev->dev,
 736                         "Get Port Info failed\n");
 737         } else {
 738                 if (QLC_83XX_SFP_10G_CAPABLE(adapter->ahw->port_config))
 739                         adapter->ahw->port_type = QLCNIC_XGBE;
 740                 else
 741                         adapter->ahw->port_type = QLCNIC_GBE;
 742
 743                 if (QLC_83XX_AUTONEG(adapter->ahw->port_config))
 744                         adapter->ahw->link_autoneg = AUTONEG_ENABLE;
 745         }
 746         return status;
 747 }
 748
 749 void qlcnic_83xx_enable_mbx_intrpt(struct qlcnic_adapter *adapter)
 750 {
 751         u32 val;
 752
 753         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 754                 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8);
 755         else
 756                 val = BIT_2;
 757
 758         QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
 759         qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 760 }
 761
 762 void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter,
 763                           const struct pci_device_id *ent)
 764 {
 765         u32 op_mode, priv_level;
 766         struct qlcnic_hardware_context *ahw = adapter->ahw;
 767
 768         ahw->fw_hal_version = 2;
 769         qlcnic_get_func_no(adapter);
 770
 771         if (qlcnic_sriov_vf_check(adapter)) {
 772                 qlcnic_sriov_vf_set_ops(adapter);
 773                 return;
 774         }
 775
 776         /* Determine function privilege level */
 777         op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
 778         if (op_mode == QLC_83XX_DEFAULT_OPMODE)
 779                 priv_level = QLCNIC_MGMT_FUNC;
 780         else
 781                 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode,
 782                                                          ahw->pci_func);
 783
 784         if (priv_level == QLCNIC_NON_PRIV_FUNC) {
 785                 ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
 786                 dev_info(&adapter->pdev->dev,
 787                          "HAL Version: %d Non Privileged function\n",
 788                          ahw->fw_hal_version);
 789                 adapter->nic_ops = &qlcnic_vf_ops;
 790         } else {
 791                 if (pci_find_ext_capability(adapter->pdev,
 792                                             PCI_EXT_CAP_ID_SRIOV))
 793                         set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state);
 794                 adapter->nic_ops = &qlcnic_83xx_ops;
 795         }
 796 }
 797
 798 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
 799                                         u32 data[]);
 800 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
 801                                             u32 data[]);
 802
 803 static void qlcnic_dump_mbx(struct qlcnic_adapter *adapter,
 804                             struct qlcnic_cmd_args *cmd)
 805 {
 806         int i;
 807
 808         dev_info(&adapter->pdev->dev,
 809                  "Host MBX regs(%d)\n", cmd->req.num);
 810         for (i = 0; i < cmd->req.num; i++) {
 811                 if (i && !(i % 8))
 812                         pr_info("\n");
 813                 pr_info("%08x ", cmd->req.arg[i]);
 814         }
 815         pr_info("\n");
 816         dev_info(&adapter->pdev->dev,
 817                  "FW MBX regs(%d)\n", cmd->rsp.num);
 818         for (i = 0; i < cmd->rsp.num; i++) {
 819                 if (i && !(i % 8))
 820                         pr_info("\n");
 821                 pr_info("%08x ", cmd->rsp.arg[i]);
 822         }
 823         pr_info("\n");
 824 }
 825
 826 /* Mailbox response for mac rcode */
 827 static u32 qlcnic_83xx_mac_rcode(struct qlcnic_adapter *adapter)
 828 {
 829         u32 fw_data;
 830         u8 mac_cmd_rcode;
 831
 832         fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2));
 833         mac_cmd_rcode = (u8)fw_data;
 834         if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE ||
 835             mac_cmd_rcode == QLC_83XX_MAC_PRESENT ||
 836             mac_cmd_rcode == QLC_83XX_MAC_ABSENT)
 837                 return QLCNIC_RCODE_SUCCESS;
 838         return 1;
 839 }
 840
 841 static u32 qlcnic_83xx_mbx_poll(struct qlcnic_adapter *adapter)
 842 {
 843         u32 data;
 844         unsigned long wait_time = 0;
 845         struct qlcnic_hardware_context *ahw = adapter->ahw;
 846         /* wait for mailbox completion */
 847         do {
 848                 data = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
 849                 if (++wait_time > QLCNIC_MBX_TIMEOUT) {
 850                         data = QLCNIC_RCODE_TIMEOUT;
 851                         break;
 852                 }
 853                 mdelay(1);
 854         } while (!data);
 855         return data;
 856 }
 857
 858 int qlcnic_83xx_mbx_op(struct qlcnic_adapter *adapter,
 859                        struct qlcnic_cmd_args *cmd)
 860 {
 861         int i;
 862         u16 opcode;
 863         u8 mbx_err_code;
 864         unsigned long flags;
 865         u32 rsp, mbx_val, fw_data, rsp_num, mbx_cmd;
 866         struct qlcnic_hardware_context *ahw = adapter->ahw;
 867
 868         opcode = LSW(cmd->req.arg[0]);
 869         if (!test_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status)) {
 870                 dev_info(&adapter->pdev->dev,
 871                          "Mailbox cmd attempted, 0x%x\n", opcode);
 872                 dev_info(&adapter->pdev->dev, "Mailbox detached\n");
 873                 return 0;
 874         }
 875
 876         spin_lock_irqsave(&adapter->ahw->mbx_lock, flags);
 877         mbx_val = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
 878
 879         if (mbx_val) {
 880                 QLCDB(adapter, DRV,
 881                       "Mailbox cmd attempted, 0x%x\n", opcode);
 882                 QLCDB(adapter, DRV,
 883                       "Mailbox not available, 0x%x, collect FW dump\n",
 884                       mbx_val);
 885                 cmd->rsp.arg[0] = QLCNIC_RCODE_TIMEOUT;
 886                 spin_unlock_irqrestore(&adapter->ahw->mbx_lock, flags);
 887                 return cmd->rsp.arg[0];
 888         }
 889
 890         /* Fill in mailbox registers */
 891         mbx_cmd = cmd->req.arg[0];
 892         writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
 893         for (i = 1; i < cmd->req.num; i++)
 894                 writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i));
 895
 896         /* Signal FW about the impending command */
 897         QLCWRX(ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER);
 898 poll:
 899         rsp = qlcnic_83xx_mbx_poll(adapter);
 900         if (rsp != QLCNIC_RCODE_TIMEOUT) {
 901                 /* Get the FW response data */
 902                 fw_data = readl(QLCNIC_MBX_FW(ahw, 0));
 903                 if (fw_data &  QLCNIC_MBX_ASYNC_EVENT) {
 904                         qlcnic_83xx_process_aen(adapter);
 905                         mbx_val = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
 906                         if (mbx_val)
 907                                 goto poll;
 908                 }
 909                 mbx_err_code = QLCNIC_MBX_STATUS(fw_data);
 910                 rsp_num = QLCNIC_MBX_NUM_REGS(fw_data);
 911                 opcode = QLCNIC_MBX_RSP(fw_data);
 912                 qlcnic_83xx_get_mbx_data(adapter, cmd);
 913
 914                 switch (mbx_err_code) {
 915                 case QLCNIC_MBX_RSP_OK:
 916                 case QLCNIC_MBX_PORT_RSP_OK:
 917                         rsp = QLCNIC_RCODE_SUCCESS;
 918                         break;
 919                 default:
 920                         if (opcode == QLCNIC_CMD_CONFIG_MAC_VLAN) {
 921                                 rsp = qlcnic_83xx_mac_rcode(adapter);
 922                                 if (!rsp)
 923                                         goto out;
 924                         }
 925                         dev_err(&adapter->pdev->dev,
 926                                 "MBX command 0x%x failed with err:0x%x\n",
 927                                 opcode, mbx_err_code);
 928                         rsp = mbx_err_code;
 929                         qlcnic_dump_mbx(adapter, cmd);
 930                         break;
 931                 }
 932                 goto out;
 933         }
 934
 935         dev_err(&adapter->pdev->dev, "MBX command 0x%x timed out\n",
 936                 QLCNIC_MBX_RSP(mbx_cmd));
 937         rsp = QLCNIC_RCODE_TIMEOUT;
 938 out:
 939         /* clear fw mbx control register */
 940         QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
 941         spin_unlock_irqrestore(&adapter->ahw->mbx_lock, flags);
 942         return rsp;
 943 }
 944
 945 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
 946                                struct qlcnic_adapter *adapter, u32 type)
 947 {
 948         int i, size;
 949         u32 temp;
 950         const struct qlcnic_mailbox_metadata *mbx_tbl;
 951
 952         mbx_tbl = qlcnic_83xx_mbx_tbl;
 953         size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl);
 954         for (i = 0; i < size; i++) {
 955                 if (type == mbx_tbl[i].cmd) {
 956                         mbx->req.num = mbx_tbl[i].in_args;
 957                         mbx->rsp.num = mbx_tbl[i].out_args;
 958                         mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
 959                                                GFP_ATOMIC);
 960                         if (!mbx->req.arg)
 961                                 return -ENOMEM;
 962                         mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
 963                                                GFP_ATOMIC);
 964                         if (!mbx->rsp.arg) {
 965                                 kfree(mbx->req.arg);
 966                                 mbx->req.arg = NULL;
 967                                 return -ENOMEM;
 968                         }
 969                         memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
 970                         memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
 971                         temp = adapter->ahw->fw_hal_version << 29;
 972                         mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp);
 973                         break;
 974                 }
 975         }
 976         return 0;
 977 }
 978
 979 void qlcnic_83xx_idc_aen_work(struct work_struct *work)
 980 {
 981         struct qlcnic_adapter *adapter;
 982         struct qlcnic_cmd_args cmd;
 983         int i, err = 0;
 984
 985         adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work);
 986         qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK);
 987
 988         for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++)
 989                 cmd.req.arg[i] = adapter->ahw->mbox_aen[i];
 990
 991         err = qlcnic_issue_cmd(adapter, &cmd);
 992         if (err)
 993                 dev_info(&adapter->pdev->dev,
 994                          "%s: Mailbox IDC ACK failed.\n", __func__);
 995         qlcnic_free_mbx_args(&cmd);
 996 }
 997
 998 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
 999                                             u32 data[])
1000 {
1001         dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n",
1002                 QLCNIC_MBX_RSP(data[0]));
1003         clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status);
1004         return;
1005 }
1006
1007 void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
1008 {
1009         u32 event[QLC_83XX_MBX_AEN_CNT];
1010         int i;
1011         struct qlcnic_hardware_context *ahw = adapter->ahw;
1012
1013         for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
1014                 event[i] = readl(QLCNIC_MBX_FW(ahw, i));
1015
1016         switch (QLCNIC_MBX_RSP(event[0])) {
1017
1018         case QLCNIC_MBX_LINK_EVENT:
1019                 qlcnic_83xx_handle_link_aen(adapter, event);
1020                 break;
1021         case QLCNIC_MBX_COMP_EVENT:
1022                 qlcnic_83xx_handle_idc_comp_aen(adapter, event);
1023                 break;
1024         case QLCNIC_MBX_REQUEST_EVENT:
1025                 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
1026                         adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]);
1027                 queue_delayed_work(adapter->qlcnic_wq,
1028                                    &adapter->idc_aen_work, 0);
1029                 break;
1030         case QLCNIC_MBX_TIME_EXTEND_EVENT:
1031                 break;
1032         case QLCNIC_MBX_SFP_INSERT_EVENT:
1033                 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n",
1034                          QLCNIC_MBX_RSP(event[0]));
1035                 break;
1036         case QLCNIC_MBX_SFP_REMOVE_EVENT:
1037                 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n",
1038                          QLCNIC_MBX_RSP(event[0]));
1039                 break;
1040         default:
1041                 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n",
1042                         QLCNIC_MBX_RSP(event[0]));
1043                 break;
1044         }
1045
1046         QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
1047 }
1048
1049 static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter)
1050 {
1051         int index, i, err, sds_mbx_size;
1052         u32 *buf, intrpt_id, intr_mask;
1053         u16 context_id;
1054         u8 num_sds;
1055         struct qlcnic_cmd_args cmd;
1056         struct qlcnic_host_sds_ring *sds;
1057         struct qlcnic_sds_mbx sds_mbx;
1058         struct qlcnic_add_rings_mbx_out *mbx_out;
1059         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1060         struct qlcnic_hardware_context *ahw = adapter->ahw;
1061
1062         sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1063         context_id = recv_ctx->context_id;
1064         num_sds = (adapter->max_sds_rings - QLCNIC_MAX_RING_SETS);
1065         ahw->hw_ops->alloc_mbx_args(&cmd, adapter,
1066                                     QLCNIC_CMD_ADD_RCV_RINGS);
1067         cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16);
1068
1069         /* set up status rings, mbx 2-81 */
1070         index = 2;
1071         for (i = 8; i < adapter->max_sds_rings; i++) {
1072                 memset(&sds_mbx, 0, sds_mbx_size);
1073                 sds = &recv_ctx->sds_rings[i];
1074                 sds->consumer = 0;
1075                 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1076                 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1077                 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1078                 sds_mbx.sds_ring_size = sds->num_desc;
1079
1080                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1081                         intrpt_id = ahw->intr_tbl[i].id;
1082                 else
1083                         intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1084
1085                 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1086                         sds_mbx.intrpt_id = intrpt_id;
1087                 else
1088                         sds_mbx.intrpt_id = 0xffff;
1089                 sds_mbx.intrpt_val = 0;
1090                 buf = &cmd.req.arg[index];
1091                 memcpy(buf, &sds_mbx, sds_mbx_size);
1092                 index += sds_mbx_size / sizeof(u32);
1093         }
1094
1095         /* send the mailbox command */
1096         err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1097         if (err) {
1098                 dev_err(&adapter->pdev->dev,
1099                         "Failed to add rings %d\n", err);
1100                 goto out;
1101         }
1102
1103         mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1];
1104         index = 0;
1105         /* status descriptor ring */
1106         for (i = 8; i < adapter->max_sds_rings; i++) {
1107                 sds = &recv_ctx->sds_rings[i];
1108                 sds->crb_sts_consumer = ahw->pci_base0 +
1109                                         mbx_out->host_csmr[index];
1110                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1111                         intr_mask = ahw->intr_tbl[i].src;
1112                 else
1113                         intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1114
1115                 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1116                 index++;
1117         }
1118 out:
1119         qlcnic_free_mbx_args(&cmd);
1120         return err;
1121 }
1122
1123 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter)
1124 {
1125         int i, err, index, sds_mbx_size, rds_mbx_size;
1126         u8 num_sds, num_rds;
1127         u32 *buf, intrpt_id, intr_mask, cap = 0;
1128         struct qlcnic_host_sds_ring *sds;
1129         struct qlcnic_host_rds_ring *rds;
1130         struct qlcnic_sds_mbx sds_mbx;
1131         struct qlcnic_rds_mbx rds_mbx;
1132         struct qlcnic_cmd_args cmd;
1133         struct qlcnic_rcv_mbx_out *mbx_out;
1134         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1135         struct qlcnic_hardware_context *ahw = adapter->ahw;
1136         num_rds = adapter->max_rds_rings;
1137
1138         if (adapter->max_sds_rings <= QLCNIC_MAX_RING_SETS)
1139                 num_sds = adapter->max_sds_rings;
1140         else
1141                 num_sds = QLCNIC_MAX_RING_SETS;
1142
1143         sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1144         rds_mbx_size = sizeof(struct qlcnic_rds_mbx);
1145         cap = QLCNIC_CAP0_LEGACY_CONTEXT;
1146
1147         if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP)
1148                 cap |= QLC_83XX_FW_CAP_LRO_MSS;
1149
1150         /* set mailbox hdr and capabilities */
1151         qlcnic_alloc_mbx_args(&cmd, adapter,
1152                               QLCNIC_CMD_CREATE_RX_CTX);
1153         cmd.req.arg[1] = cap;
1154         cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) |
1155                          (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16);
1156         /* set up status rings, mbx 8-57/87 */
1157         index = QLC_83XX_HOST_SDS_MBX_IDX;
1158         for (i = 0; i < num_sds; i++) {
1159                 memset(&sds_mbx, 0, sds_mbx_size);
1160                 sds = &recv_ctx->sds_rings[i];
1161                 sds->consumer = 0;
1162                 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1163                 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1164                 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1165                 sds_mbx.sds_ring_size = sds->num_desc;
1166                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1167                         intrpt_id = ahw->intr_tbl[i].id;
1168                 else
1169                         intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1170                 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1171                         sds_mbx.intrpt_id = intrpt_id;
1172                 else
1173                         sds_mbx.intrpt_id = 0xffff;
1174                 sds_mbx.intrpt_val = 0;
1175                 buf = &cmd.req.arg[index];
1176                 memcpy(buf, &sds_mbx, sds_mbx_size);
1177                 index += sds_mbx_size / sizeof(u32);
1178         }
1179         /* set up receive rings, mbx 88-111/135 */
1180         index = QLCNIC_HOST_RDS_MBX_IDX;
1181         rds = &recv_ctx->rds_rings[0];
1182         rds->producer = 0;
1183         memset(&rds_mbx, 0, rds_mbx_size);
1184         rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr);
1185         rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr);
1186         rds_mbx.reg_ring_sz = rds->dma_size;
1187         rds_mbx.reg_ring_len = rds->num_desc;
1188         /* Jumbo ring */
1189         rds = &recv_ctx->rds_rings[1];
1190         rds->producer = 0;
1191         rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr);
1192         rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr);
1193         rds_mbx.jmb_ring_sz = rds->dma_size;
1194         rds_mbx.jmb_ring_len = rds->num_desc;
1195         buf = &cmd.req.arg[index];
1196         memcpy(buf, &rds_mbx, rds_mbx_size);
1197
1198         /* send the mailbox command */
1199         err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1200         if (err) {
1201                 dev_err(&adapter->pdev->dev,
1202                         "Failed to create Rx ctx in firmware%d\n", err);
1203                 goto out;
1204         }
1205         mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1];
1206         recv_ctx->context_id = mbx_out->ctx_id;
1207         recv_ctx->state = mbx_out->state;
1208         recv_ctx->virt_port = mbx_out->vport_id;
1209         dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n",
1210                  recv_ctx->context_id, recv_ctx->state);
1211         /* Receive descriptor ring */
1212         /* Standard ring */
1213         rds = &recv_ctx->rds_rings[0];
1214         rds->crb_rcv_producer = ahw->pci_base0 +
1215                                 mbx_out->host_prod[0].reg_buf;
1216         /* Jumbo ring */
1217         rds = &recv_ctx->rds_rings[1];
1218         rds->crb_rcv_producer = ahw->pci_base0 +
1219                                 mbx_out->host_prod[0].jmb_buf;
1220         /* status descriptor ring */
1221         for (i = 0; i < num_sds; i++) {
1222                 sds = &recv_ctx->sds_rings[i];
1223                 sds->crb_sts_consumer = ahw->pci_base0 +
1224                                         mbx_out->host_csmr[i];
1225                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1226                         intr_mask = ahw->intr_tbl[i].src;
1227                 else
1228                         intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1229                 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1230         }
1231
1232         if (adapter->max_sds_rings > QLCNIC_MAX_RING_SETS)
1233                 err = qlcnic_83xx_add_rings(adapter);
1234 out:
1235         qlcnic_free_mbx_args(&cmd);
1236         return err;
1237 }
1238
1239 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter,
1240                               struct qlcnic_host_tx_ring *tx, int ring)
1241 {
1242         int err;
1243         u16 msix_id;
1244         u32 *buf, intr_mask;
1245         struct qlcnic_cmd_args cmd;
1246         struct qlcnic_tx_mbx mbx;
1247         struct qlcnic_tx_mbx_out *mbx_out;
1248         struct qlcnic_hardware_context *ahw = adapter->ahw;
1249         u32 msix_vector;
1250
1251         /* Reset host resources */
1252         tx->producer = 0;
1253         tx->sw_consumer = 0;
1254         *(tx->hw_consumer) = 0;
1255
1256         memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx));
1257
1258         /* setup mailbox inbox registerss */
1259         mbx.phys_addr_low = LSD(tx->phys_addr);
1260         mbx.phys_addr_high = MSD(tx->phys_addr);
1261         mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr);
1262         mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr);
1263         mbx.size = tx->num_desc;
1264         if (adapter->flags & QLCNIC_MSIX_ENABLED) {
1265                 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
1266                         msix_vector = adapter->max_sds_rings + ring;
1267                 else
1268                         msix_vector = adapter->max_sds_rings - 1;
1269                 msix_id = ahw->intr_tbl[msix_vector].id;
1270         } else {
1271                 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1272         }
1273
1274         if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1275                 mbx.intr_id = msix_id;
1276         else
1277                 mbx.intr_id = 0xffff;
1278         mbx.src = 0;
1279
1280         qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
1281         cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT;
1282         cmd.req.arg[5] = QLCNIC_MAX_TX_QUEUES;
1283         buf = &cmd.req.arg[6];
1284         memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx));
1285         /* send the mailbox command*/
1286         err = qlcnic_issue_cmd(adapter, &cmd);
1287         if (err) {
1288                 dev_err(&adapter->pdev->dev,
1289                         "Failed to create Tx ctx in firmware 0x%x\n", err);
1290                 goto out;
1291         }
1292         mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2];
1293         tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod;
1294         tx->ctx_id = mbx_out->ctx_id;
1295         if ((adapter->flags & QLCNIC_MSIX_ENABLED) &&
1296             !(adapter->flags & QLCNIC_TX_INTR_SHARED)) {
1297                 intr_mask = ahw->intr_tbl[adapter->max_sds_rings + ring].src;
1298                 tx->crb_intr_mask = ahw->pci_base0 + intr_mask;
1299         }
1300         dev_info(&adapter->pdev->dev, "Tx Context[0x%x] Created, state:0x%x\n",
1301                  tx->ctx_id, mbx_out->state);
1302 out:
1303         qlcnic_free_mbx_args(&cmd);
1304         return err;
1305 }
1306
1307 static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test)
1308 {
1309         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1310         struct qlcnic_host_sds_ring *sds_ring;
1311         struct qlcnic_host_rds_ring *rds_ring;
1312         u8 ring;
1313         int ret;
1314
1315         netif_device_detach(netdev);
1316
1317         if (netif_running(netdev))
1318                 __qlcnic_down(adapter, netdev);
1319
1320         qlcnic_detach(adapter);
1321
1322         adapter->max_sds_rings = 1;
1323         adapter->ahw->diag_test = test;
1324         adapter->ahw->linkup = 0;
1325
1326         ret = qlcnic_attach(adapter);
1327         if (ret) {
1328                 netif_device_attach(netdev);
1329                 return ret;
1330         }
1331
1332         ret = qlcnic_fw_create_ctx(adapter);
1333         if (ret) {
1334                 qlcnic_detach(adapter);
1335                 netif_device_attach(netdev);
1336                 return ret;
1337         }
1338
1339         for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1340                 rds_ring = &adapter->recv_ctx->rds_rings[ring];
1341                 qlcnic_post_rx_buffers(adapter, rds_ring, ring);
1342         }
1343
1344         if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1345                 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
1346                         sds_ring = &adapter->recv_ctx->sds_rings[ring];
1347                         qlcnic_83xx_enable_intr(adapter, sds_ring);
1348                 }
1349         }
1350
1351         if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1352                 /* disable and free mailbox interrupt */
1353                 qlcnic_83xx_free_mbx_intr(adapter);
1354                 adapter->ahw->loopback_state = 0;
1355                 adapter->ahw->hw_ops->setup_link_event(adapter, 1);
1356         }
1357
1358         set_bit(__QLCNIC_DEV_UP, &adapter->state);
1359         return 0;
1360 }
1361
1362 static void qlcnic_83xx_diag_free_res(struct net_device *netdev,
1363                                         int max_sds_rings)
1364 {
1365         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1366         struct qlcnic_host_sds_ring *sds_ring;
1367         int ring, err;
1368
1369         clear_bit(__QLCNIC_DEV_UP, &adapter->state);
1370         if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1371                 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
1372                         sds_ring = &adapter->recv_ctx->sds_rings[ring];
1373                         qlcnic_83xx_disable_intr(adapter, sds_ring);
1374                 }
1375         }
1376
1377         qlcnic_fw_destroy_ctx(adapter);
1378         qlcnic_detach(adapter);
1379
1380         if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1381                 err = qlcnic_83xx_setup_mbx_intr(adapter);
1382                 if (err) {
1383                         dev_err(&adapter->pdev->dev,
1384                                 "%s: failed to setup mbx interrupt\n",
1385                                 __func__);
1386                         goto out;
1387                 }
1388         }
1389         adapter->ahw->diag_test = 0;
1390         adapter->max_sds_rings = max_sds_rings;
1391
1392         if (qlcnic_attach(adapter))
1393                 goto out;
1394
1395         if (netif_running(netdev))
1396                 __qlcnic_up(adapter, netdev);
1397 out:
1398         netif_device_attach(netdev);
1399 }
1400
1401 int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state,
1402                            u32 beacon)
1403 {
1404         struct qlcnic_cmd_args cmd;
1405         u32 mbx_in;
1406         int i, status = 0;
1407
1408         if (state) {
1409                 /* Get LED configuration */
1410                 qlcnic_alloc_mbx_args(&cmd, adapter,
1411                                       QLCNIC_CMD_GET_LED_CONFIG);
1412                 status = qlcnic_issue_cmd(adapter, &cmd);
1413                 if (status) {
1414                         dev_err(&adapter->pdev->dev,
1415                                 "Get led config failed.\n");
1416                         goto mbx_err;
1417                 } else {
1418                         for (i = 0; i < 4; i++)
1419                                 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1];
1420                 }
1421                 qlcnic_free_mbx_args(&cmd);
1422                 /* Set LED Configuration */
1423                 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) |
1424                           LSW(QLC_83XX_LED_CONFIG);
1425                 qlcnic_alloc_mbx_args(&cmd, adapter,
1426                                       QLCNIC_CMD_SET_LED_CONFIG);
1427                 cmd.req.arg[1] = mbx_in;
1428                 cmd.req.arg[2] = mbx_in;
1429                 cmd.req.arg[3] = mbx_in;
1430                 if (beacon)
1431                         cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON;
1432                 status = qlcnic_issue_cmd(adapter, &cmd);
1433                 if (status) {
1434                         dev_err(&adapter->pdev->dev,
1435                                 "Set led config failed.\n");
1436                 }
1437 mbx_err:
1438                 qlcnic_free_mbx_args(&cmd);
1439                 return status;
1440
1441         } else {
1442                 /* Restoring default LED configuration */
1443                 qlcnic_alloc_mbx_args(&cmd, adapter,
1444                                       QLCNIC_CMD_SET_LED_CONFIG);
1445                 cmd.req.arg[1] = adapter->ahw->mbox_reg[0];
1446                 cmd.req.arg[2] = adapter->ahw->mbox_reg[1];
1447                 cmd.req.arg[3] = adapter->ahw->mbox_reg[2];
1448                 if (beacon)
1449                         cmd.req.arg[4] = adapter->ahw->mbox_reg[3];
1450                 status = qlcnic_issue_cmd(adapter, &cmd);
1451                 if (status)
1452                         dev_err(&adapter->pdev->dev,
1453                                 "Restoring led config failed.\n");
1454                 qlcnic_free_mbx_args(&cmd);
1455                 return status;
1456         }
1457 }
1458
1459 int  qlcnic_83xx_set_led(struct net_device *netdev,
1460                          enum ethtool_phys_id_state state)
1461 {
1462         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1463         int err = -EIO, active = 1;
1464
1465         if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1466                 netdev_warn(netdev,
1467                             "LED test is not supported in non-privileged mode\n");
1468                 return -EOPNOTSUPP;
1469         }
1470
1471         switch (state) {
1472         case ETHTOOL_ID_ACTIVE:
1473                 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state))
1474                         return -EBUSY;
1475
1476                 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1477                         break;
1478
1479                 err = qlcnic_83xx_config_led(adapter, active, 0);
1480                 if (err)
1481                         netdev_err(netdev, "Failed to set LED blink state\n");
1482                 break;
1483         case ETHTOOL_ID_INACTIVE:
1484                 active = 0;
1485
1486                 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1487                         break;
1488
1489                 err = qlcnic_83xx_config_led(adapter, active, 0);
1490                 if (err)
1491                         netdev_err(netdev, "Failed to reset LED blink state\n");
1492                 break;
1493
1494         default:
1495                 return -EINVAL;
1496         }
1497
1498         if (!active || err)
1499                 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state);
1500
1501         return err;
1502 }
1503
1504 void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter *adapter,
1505                                        int enable)
1506 {
1507         struct qlcnic_cmd_args cmd;
1508         int status;
1509
1510         if (qlcnic_sriov_vf_check(adapter))
1511                 return;
1512
1513         if (enable) {
1514                 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INIT_NIC_FUNC);
1515                 cmd.req.arg[1] = BIT_0 | BIT_31;
1516         } else {
1517                 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_STOP_NIC_FUNC);
1518                 cmd.req.arg[1] = BIT_0 | BIT_31;
1519         }
1520         status = qlcnic_issue_cmd(adapter, &cmd);
1521         if (status)
1522                 dev_err(&adapter->pdev->dev,
1523                         "Failed to %s in NIC IDC function event.\n",
1524                         (enable ? "register" : "unregister"));
1525
1526         qlcnic_free_mbx_args(&cmd);
1527 }
1528
1529 int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter)
1530 {
1531         struct qlcnic_cmd_args cmd;
1532         int err;
1533
1534         qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG);
1535         cmd.req.arg[1] = adapter->ahw->port_config;
1536         err = qlcnic_issue_cmd(adapter, &cmd);
1537         if (err)
1538                 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n");
1539         qlcnic_free_mbx_args(&cmd);
1540         return err;
1541 }
1542
1543 int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter)
1544 {
1545         struct qlcnic_cmd_args cmd;
1546         int err;
1547
1548         qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG);
1549         err = qlcnic_issue_cmd(adapter, &cmd);
1550         if (err)
1551                 dev_info(&adapter->pdev->dev, "Get Port config failed\n");
1552         else
1553                 adapter->ahw->port_config = cmd.rsp.arg[1];
1554         qlcnic_free_mbx_args(&cmd);
1555         return err;
1556 }
1557
1558 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable)
1559 {
1560         int err;
1561         u32 temp;
1562         struct qlcnic_cmd_args cmd;
1563
1564         qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT);
1565         temp = adapter->recv_ctx->context_id << 16;
1566         cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp;
1567         err = qlcnic_issue_cmd(adapter, &cmd);
1568         if (err)
1569                 dev_info(&adapter->pdev->dev,
1570                          "Setup linkevent mailbox failed\n");
1571         qlcnic_free_mbx_args(&cmd);
1572         return err;
1573 }
1574
1575 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
1576 {
1577         int err;
1578         u32 temp;
1579         struct qlcnic_cmd_args cmd;
1580
1581         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1582                 return -EIO;
1583
1584         qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_MAC_RX_MODE);
1585         temp = adapter->recv_ctx->context_id << 16;
1586         cmd.req.arg[1] = (mode ? 1 : 0) | temp;
1587         err = qlcnic_issue_cmd(adapter, &cmd);
1588         if (err)
1589                 dev_info(&adapter->pdev->dev,
1590                          "Promiscous mode config failed\n");
1591         qlcnic_free_mbx_args(&cmd);
1592
1593         return err;
1594 }
1595
1596 int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode)
1597 {
1598         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1599         struct qlcnic_hardware_context *ahw = adapter->ahw;
1600         int ret = 0, loop = 0, max_sds_rings = adapter->max_sds_rings;
1601
1602         QLCDB(adapter, DRV, "%s loopback test in progress\n",
1603               mode == QLCNIC_ILB_MODE ? "internal" : "external");
1604         if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1605                 dev_warn(&adapter->pdev->dev,
1606                          "Loopback test not supported for non privilege function\n");
1607                 return ret;
1608         }
1609
1610         if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1611                 return -EBUSY;
1612
1613         ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST);
1614         if (ret)
1615                 goto fail_diag_alloc;
1616
1617         ret = qlcnic_83xx_set_lb_mode(adapter, mode);
1618         if (ret)
1619                 goto free_diag_res;
1620
1621         /* Poll for link up event before running traffic */
1622         do {
1623                 msleep(500);
1624                 qlcnic_83xx_process_aen(adapter);
1625                 if (loop++ > QLCNIC_ILB_MAX_RCV_LOOP) {
1626                         dev_info(&adapter->pdev->dev,
1627                                  "Firmware didn't sent link up event to loopback request\n");
1628                         ret = -QLCNIC_FW_NOT_RESPOND;
1629                         qlcnic_83xx_clear_lb_mode(adapter, mode);
1630                         goto free_diag_res;
1631                 }
1632         } while ((adapter->ahw->linkup && ahw->has_link_events) != 1);
1633
1634         ret = qlcnic_do_lb_test(adapter, mode);
1635
1636         qlcnic_83xx_clear_lb_mode(adapter, mode);
1637
1638 free_diag_res:
1639         qlcnic_83xx_diag_free_res(netdev, max_sds_rings);
1640
1641 fail_diag_alloc:
1642         adapter->max_sds_rings = max_sds_rings;
1643         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1644         return ret;
1645 }
1646
1647 int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1648 {
1649         struct qlcnic_hardware_context *ahw = adapter->ahw;
1650         int status = 0, loop = 0;
1651         u32 config;
1652
1653         status = qlcnic_83xx_get_port_config(adapter);
1654         if (status)
1655                 return status;
1656
1657         config = ahw->port_config;
1658         set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1659
1660         if (mode == QLCNIC_ILB_MODE)
1661                 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS;
1662         if (mode == QLCNIC_ELB_MODE)
1663                 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT;
1664
1665         status = qlcnic_83xx_set_port_config(adapter);
1666         if (status) {
1667                 dev_err(&adapter->pdev->dev,
1668                         "Failed to Set Loopback Mode = 0x%x.\n",
1669                         ahw->port_config);
1670                 ahw->port_config = config;
1671                 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1672                 return status;
1673         }
1674
1675         /* Wait for Link and IDC Completion AEN */
1676         do {
1677                 msleep(300);
1678                 qlcnic_83xx_process_aen(adapter);
1679                 if (loop++ > QLCNIC_ILB_MAX_RCV_LOOP) {
1680                         dev_err(&adapter->pdev->dev,
1681                                 "FW did not generate IDC completion AEN\n");
1682                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1683                         qlcnic_83xx_clear_lb_mode(adapter, mode);
1684                         return -EIO;
1685                 }
1686         } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1687
1688         qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1689                                   QLCNIC_MAC_ADD);
1690         return status;
1691 }
1692
1693 int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1694 {
1695         struct qlcnic_hardware_context *ahw = adapter->ahw;
1696         int status = 0, loop = 0;
1697         u32 config = ahw->port_config;
1698
1699         set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1700         if (mode == QLCNIC_ILB_MODE)
1701                 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS;
1702         if (mode == QLCNIC_ELB_MODE)
1703                 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT;
1704
1705         status = qlcnic_83xx_set_port_config(adapter);
1706         if (status) {
1707                 dev_err(&adapter->pdev->dev,
1708                         "Failed to Clear Loopback Mode = 0x%x.\n",
1709                         ahw->port_config);
1710                 ahw->port_config = config;
1711                 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1712                 return status;
1713         }
1714
1715         /* Wait for Link and IDC Completion AEN */
1716         do {
1717                 msleep(300);
1718                 qlcnic_83xx_process_aen(adapter);
1719                 if (loop++ > QLCNIC_ILB_MAX_RCV_LOOP) {
1720                         dev_err(&adapter->pdev->dev,
1721                                 "Firmware didn't sent IDC completion AEN\n");
1722                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1723                         return -EIO;
1724                 }
1725         } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1726
1727         qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1728                                   QLCNIC_MAC_DEL);
1729         return status;
1730 }
1731
1732 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip,
1733                                int mode)
1734 {
1735         int err;
1736         u32 temp, temp_ip;
1737         struct qlcnic_cmd_args cmd;
1738
1739         qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_IP_ADDR);
1740         if (mode == QLCNIC_IP_UP) {
1741                 temp = adapter->recv_ctx->context_id << 16;
1742                 cmd.req.arg[1] = 1 | temp;
1743         } else {
1744                 temp = adapter->recv_ctx->context_id << 16;
1745                 cmd.req.arg[1] = 2 | temp;
1746         }
1747
1748         /*
1749          * Adapter needs IP address in network byte order.
1750          * But hardware mailbox registers go through writel(), hence IP address
1751          * gets swapped on big endian architecture.
1752          * To negate swapping of writel() on big endian architecture
1753          * use swab32(value).
1754          */
1755
1756         temp_ip = swab32(ntohl(ip));
1757         memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32));
1758         err = qlcnic_issue_cmd(adapter, &cmd);
1759         if (err != QLCNIC_RCODE_SUCCESS)
1760                 dev_err(&adapter->netdev->dev,
1761                         "could not notify %s IP 0x%x request\n",
1762                         (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
1763         qlcnic_free_mbx_args(&cmd);
1764 }
1765
1766 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode)
1767 {
1768         int err;
1769         u32 temp, arg1;
1770         struct qlcnic_cmd_args cmd;
1771         int lro_bit_mask;
1772
1773         lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0);
1774
1775         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1776                 return 0;
1777
1778         qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO);
1779         temp = adapter->recv_ctx->context_id << 16;
1780         arg1 = lro_bit_mask | temp;
1781         cmd.req.arg[1] = arg1;
1782
1783         err = qlcnic_issue_cmd(adapter, &cmd);
1784         if (err)
1785                 dev_info(&adapter->pdev->dev, "LRO config failed\n");
1786         qlcnic_free_mbx_args(&cmd);
1787
1788         return err;
1789 }
1790
1791 int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable)
1792 {
1793         int err;
1794         u32 word;
1795         struct qlcnic_cmd_args cmd;
1796         const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
1797                             0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
1798                             0x255b0ec26d5a56daULL };
1799
1800         qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS);
1801
1802         /*
1803          * RSS request:
1804          * bits 3-0: Rsvd
1805          *      5-4: hash_type_ipv4
1806          *      7-6: hash_type_ipv6
1807          *        8: enable
1808          *        9: use indirection table
1809          *    16-31: indirection table mask
1810          */
1811         word =  ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
1812                 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
1813                 ((u32)(enable & 0x1) << 8) |
1814                 ((0x7ULL) << 16);
1815         cmd.req.arg[1] = (adapter->recv_ctx->context_id);
1816         cmd.req.arg[2] = word;
1817         memcpy(&cmd.req.arg[4], key, sizeof(key));
1818
1819         err = qlcnic_issue_cmd(adapter, &cmd);
1820
1821         if (err)
1822                 dev_info(&adapter->pdev->dev, "RSS config failed\n");
1823         qlcnic_free_mbx_args(&cmd);
1824
1825         return err;
1826
1827 }
1828
1829 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
1830                                    __le16 vlan_id, u8 op)
1831 {
1832         int err;
1833         u32 *buf;
1834         struct qlcnic_cmd_args cmd;
1835         struct qlcnic_macvlan_mbx mv;
1836
1837         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1838                 return -EIO;
1839
1840         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN);
1841         if (err)
1842                 return err;
1843         cmd.req.arg[1] = op | (1 << 8) |
1844                         (adapter->recv_ctx->context_id << 16);
1845
1846         mv.vlan = le16_to_cpu(vlan_id);
1847         mv.mac_addr0 = addr[0];
1848         mv.mac_addr1 = addr[1];
1849         mv.mac_addr2 = addr[2];
1850         mv.mac_addr3 = addr[3];
1851         mv.mac_addr4 = addr[4];
1852         mv.mac_addr5 = addr[5];
1853         buf = &cmd.req.arg[2];
1854         memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx));
1855         err = qlcnic_issue_cmd(adapter, &cmd);
1856         if (err)
1857                 dev_err(&adapter->pdev->dev,
1858                         "MAC-VLAN %s to CAM failed, err=%d.\n",
1859                         ((op == 1) ? "add " : "delete "), err);
1860         qlcnic_free_mbx_args(&cmd);
1861         return err;
1862 }
1863
1864 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr,
1865                                   __le16 vlan_id)
1866 {
1867         u8 mac[ETH_ALEN];
1868         memcpy(&mac, addr, ETH_ALEN);
1869         qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD);
1870 }
1871
1872 void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac,
1873                                u8 type, struct qlcnic_cmd_args *cmd)
1874 {
1875         switch (type) {
1876         case QLCNIC_SET_STATION_MAC:
1877         case QLCNIC_SET_FAC_DEF_MAC:
1878                 memcpy(&cmd->req.arg[2], mac, sizeof(u32));
1879                 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16));
1880                 break;
1881         }
1882         cmd->req.arg[1] = type;
1883 }
1884
1885 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac)
1886 {
1887         int err, i;
1888         struct qlcnic_cmd_args cmd;
1889         u32 mac_low, mac_high;
1890
1891         qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
1892         qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd);
1893         err = qlcnic_issue_cmd(adapter, &cmd);
1894
1895         if (err == QLCNIC_RCODE_SUCCESS) {
1896                 mac_low = cmd.rsp.arg[1];
1897                 mac_high = cmd.rsp.arg[2];
1898
1899                 for (i = 0; i < 2; i++)
1900                         mac[i] = (u8) (mac_high >> ((1 - i) * 8));
1901                 for (i = 2; i < 6; i++)
1902                         mac[i] = (u8) (mac_low >> ((5 - i) * 8));
1903         } else {
1904                 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n",
1905                         err);
1906                 err = -EIO;
1907         }
1908         qlcnic_free_mbx_args(&cmd);
1909         return err;
1910 }
1911
1912 void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter)
1913 {
1914         int err;
1915         u32 temp;
1916         struct qlcnic_cmd_args cmd;
1917         struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
1918
1919         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1920                 return;
1921
1922         qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
1923         cmd.req.arg[1] = 1 | (adapter->recv_ctx->context_id << 16);
1924         cmd.req.arg[3] = coal->flag;
1925         temp = coal->rx_time_us << 16;
1926         cmd.req.arg[2] = coal->rx_packets | temp;
1927         err = qlcnic_issue_cmd(adapter, &cmd);
1928         if (err != QLCNIC_RCODE_SUCCESS)
1929                 dev_info(&adapter->pdev->dev,
1930                          "Failed to send interrupt coalescence parameters\n");
1931         qlcnic_free_mbx_args(&cmd);
1932 }
1933
1934 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
1935                                         u32 data[])
1936 {
1937         u8 link_status, duplex;
1938         /* link speed */
1939         link_status = LSB(data[3]) & 1;
1940         adapter->ahw->link_speed = MSW(data[2]);
1941         adapter->ahw->link_autoneg = MSB(MSW(data[3]));
1942         adapter->ahw->module_type = MSB(LSW(data[3]));
1943         duplex = LSB(MSW(data[3]));
1944         if (duplex)
1945                 adapter->ahw->link_duplex = DUPLEX_FULL;
1946         else
1947                 adapter->ahw->link_duplex = DUPLEX_HALF;
1948         adapter->ahw->has_link_events = 1;
1949         qlcnic_advert_link_change(adapter, link_status);
1950 }
1951
1952 irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data)
1953 {
1954         struct qlcnic_adapter *adapter = data;
1955         unsigned long flags;
1956         u32 mask, resp, event;
1957
1958         spin_lock_irqsave(&adapter->ahw->mbx_lock, flags);
1959         resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
1960         if (!(resp & QLCNIC_SET_OWNER))
1961                 goto out;
1962
1963         event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
1964         if (event &  QLCNIC_MBX_ASYNC_EVENT)
1965                 qlcnic_83xx_process_aen(adapter);
1966 out:
1967         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
1968         writel(0, adapter->ahw->pci_base0 + mask);
1969         spin_unlock_irqrestore(&adapter->ahw->mbx_lock, flags);
1970
1971         return IRQ_HANDLED;
1972 }
1973
1974 int qlcnic_enable_eswitch(struct qlcnic_adapter *adapter, u8 port, u8 enable)
1975 {
1976         int err = -EIO;
1977         struct qlcnic_cmd_args cmd;
1978
1979         if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
1980                 dev_err(&adapter->pdev->dev,
1981                         "%s: Error, invoked by non management func\n",
1982                         __func__);
1983                 return err;
1984         }
1985
1986         qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_TOGGLE_ESWITCH);
1987         cmd.req.arg[1] = (port & 0xf) | BIT_4;
1988         err = qlcnic_issue_cmd(adapter, &cmd);
1989
1990         if (err != QLCNIC_RCODE_SUCCESS) {
1991                 dev_err(&adapter->pdev->dev, "Failed to enable eswitch%d\n",
1992                         err);
1993                 err = -EIO;
1994         }
1995         qlcnic_free_mbx_args(&cmd);
1996
1997         return err;
1998
1999 }
2000
2001 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter,
2002                              struct qlcnic_info *nic)
2003 {
2004         int i, err = -EIO;
2005         struct qlcnic_cmd_args cmd;
2006
2007         if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2008                 dev_err(&adapter->pdev->dev,
2009                         "%s: Error, invoked by non management func\n",
2010                         __func__);
2011                 return err;
2012         }
2013
2014         qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
2015         cmd.req.arg[1] = (nic->pci_func << 16);
2016         cmd.req.arg[2] = 0x1 << 16;
2017         cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16);
2018         cmd.req.arg[4] = nic->capabilities;
2019         cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16);
2020         cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16);
2021         cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16);
2022         for (i = 8; i < 32; i++)
2023                 cmd.req.arg[i] = 0;
2024
2025         err = qlcnic_issue_cmd(adapter, &cmd);
2026
2027         if (err != QLCNIC_RCODE_SUCCESS) {
2028                 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n",
2029                         err);
2030                 err = -EIO;
2031         }
2032
2033         qlcnic_free_mbx_args(&cmd);
2034
2035         return err;
2036 }
2037
2038 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter,
2039                              struct qlcnic_info *npar_info, u8 func_id)
2040 {
2041         int err;
2042         u32 temp;
2043         u8 op = 0;
2044         struct qlcnic_cmd_args cmd;
2045
2046         qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
2047         if (func_id != adapter->ahw->pci_func) {
2048                 temp = func_id << 16;
2049                 cmd.req.arg[1] = op | BIT_31 | temp;
2050         } else {
2051                 cmd.req.arg[1] = adapter->ahw->pci_func << 16;
2052         }
2053         err = qlcnic_issue_cmd(adapter, &cmd);
2054         if (err) {
2055                 dev_info(&adapter->pdev->dev,
2056                          "Failed to get nic info %d\n", err);
2057                 goto out;
2058         }
2059
2060         npar_info->op_type = cmd.rsp.arg[1];
2061         npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF;
2062         npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16;
2063         npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF;
2064         npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16;
2065         npar_info->capabilities = cmd.rsp.arg[4];
2066         npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF;
2067         npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16;
2068         npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF;
2069         npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16;
2070         npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF;
2071         npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16;
2072         if (cmd.rsp.arg[8] & 0x1)
2073                 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1;
2074         if (cmd.rsp.arg[8] & 0x10000) {
2075                 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17;
2076                 npar_info->max_linkspeed_reg_offset = temp;
2077         }
2078
2079 out:
2080         qlcnic_free_mbx_args(&cmd);
2081         return err;
2082 }
2083
2084 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter,
2085                              struct qlcnic_pci_info *pci_info)
2086 {
2087         int i, err = 0, j = 0;
2088         u32 temp;
2089         struct qlcnic_cmd_args cmd;
2090
2091         qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
2092         err = qlcnic_issue_cmd(adapter, &cmd);
2093
2094         adapter->ahw->act_pci_func = 0;
2095         if (err == QLCNIC_RCODE_SUCCESS) {
2096                 pci_info->func_count = cmd.rsp.arg[1] & 0xFF;
2097                 dev_info(&adapter->pdev->dev,
2098                          "%s: total functions = %d\n",
2099                          __func__, pci_info->func_count);
2100                 for (i = 2, j = 0; j < QLCNIC_MAX_PCI_FUNC; j++, pci_info++) {
2101                         pci_info->id = cmd.rsp.arg[i] & 0xFFFF;
2102                         pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2103                         i++;
2104                         pci_info->type = cmd.rsp.arg[i] & 0xFFFF;
2105                         if (pci_info->type == QLCNIC_TYPE_NIC)
2106                                 adapter->ahw->act_pci_func++;
2107                         temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2108                         pci_info->default_port = temp;
2109                         i++;
2110                         pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF;
2111                         temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2112                         pci_info->tx_max_bw = temp;
2113                         i = i + 2;
2114                         memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2);
2115                         i++;
2116                         memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2);
2117                         i = i + 3;
2118
2119                         dev_info(&adapter->pdev->dev, "%s:\n"
2120                                  "\tid = %d active = %d type = %d\n"
2121                                  "\tport = %d min bw = %d max bw = %d\n"
2122                                  "\tmac_addr =  %pM\n", __func__,
2123                                  pci_info->id, pci_info->active, pci_info->type,
2124                                  pci_info->default_port, pci_info->tx_min_bw,
2125                                  pci_info->tx_max_bw, pci_info->mac);
2126                 }
2127         } else {
2128                 dev_err(&adapter->pdev->dev, "Failed to get PCI Info%d\n",
2129                         err);
2130                 err = -EIO;
2131         }
2132
2133         qlcnic_free_mbx_args(&cmd);
2134
2135         return err;
2136 }
2137
2138 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type)
2139 {
2140         int i, index, err;
2141         u8 max_ints;
2142         u32 val, temp, type;
2143         struct qlcnic_cmd_args cmd;
2144
2145         max_ints = adapter->ahw->num_msix - 1;
2146         qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT);
2147         cmd.req.arg[1] = max_ints;
2148         for (i = 0, index = 2; i < max_ints; i++) {
2149                 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
2150                 val = type | (adapter->ahw->intr_tbl[i].type << 4);
2151                 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
2152                         val |= (adapter->ahw->intr_tbl[i].id << 16);
2153                 cmd.req.arg[index++] = val;
2154         }
2155         err = qlcnic_issue_cmd(adapter, &cmd);
2156         if (err) {
2157                 dev_err(&adapter->pdev->dev,
2158                         "Failed to configure interrupts 0x%x\n", err);
2159                 goto out;
2160         }
2161
2162         max_ints = cmd.rsp.arg[1];
2163         for (i = 0, index = 2; i < max_ints; i++, index += 2) {
2164                 val = cmd.rsp.arg[index];
2165                 if (LSB(val)) {
2166                         dev_info(&adapter->pdev->dev,
2167                                  "Can't configure interrupt %d\n",
2168                                  adapter->ahw->intr_tbl[i].id);
2169                         continue;
2170                 }
2171                 if (op_type) {
2172                         adapter->ahw->intr_tbl[i].id = MSW(val);
2173                         adapter->ahw->intr_tbl[i].enabled = 1;
2174                         temp = cmd.rsp.arg[index + 1];
2175                         adapter->ahw->intr_tbl[i].src = temp;
2176                 } else {
2177                         adapter->ahw->intr_tbl[i].id = i;
2178                         adapter->ahw->intr_tbl[i].enabled = 0;
2179                         adapter->ahw->intr_tbl[i].src = 0;
2180                 }
2181         }
2182 out:
2183         qlcnic_free_mbx_args(&cmd);
2184         return err;
2185 }
2186
2187 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter)
2188 {
2189         int id, timeout = 0;
2190         u32 status = 0;
2191
2192         while (status == 0) {
2193                 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
2194                 if (status)
2195                         break;
2196
2197                 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) {
2198                         id = QLC_SHARED_REG_RD32(adapter,
2199                                                  QLCNIC_FLASH_LOCK_OWNER);
2200                         dev_err(&adapter->pdev->dev,
2201                                 "%s: failed, lock held by %d\n", __func__, id);
2202                         return -EIO;
2203                 }
2204                 usleep_range(1000, 2000);
2205         }
2206
2207         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum);
2208         return 0;
2209 }
2210
2211 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter)
2212 {
2213         QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
2214         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF);
2215 }
2216
2217 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter,
2218                                       u32 flash_addr, u8 *p_data,
2219                                       int count)
2220 {
2221         int i, ret;
2222         u32 word, range, flash_offset, addr = flash_addr;
2223         ulong indirect_add, direct_window;
2224
2225         flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1);
2226         if (addr & 0x3) {
2227                 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2228                 return -EIO;
2229         }
2230
2231         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW,
2232                                      (addr));
2233
2234         range = flash_offset + (count * sizeof(u32));
2235         /* Check if data is spread across multiple sectors */
2236         if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2237
2238                 /* Multi sector read */
2239                 for (i = 0; i < count; i++) {
2240                         indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2241                         ret = qlcnic_83xx_rd_reg_indirect(adapter,
2242                                                           indirect_add);
2243                         if (ret == -EIO)
2244                                 return -EIO;
2245
2246                         word = ret;
2247                         *(u32 *)p_data  = word;
2248                         p_data = p_data + 4;
2249                         addr = addr + 4;
2250                         flash_offset = flash_offset + 4;
2251
2252                         if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2253                                 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW;
2254                                 /* This write is needed once for each sector */
2255                                 qlcnic_83xx_wrt_reg_indirect(adapter,
2256                                                              direct_window,
2257                                                              (addr));
2258                                 flash_offset = 0;
2259                         }
2260                 }
2261         } else {
2262                 /* Single sector read */
2263                 for (i = 0; i < count; i++) {
2264                         indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2265                         ret = qlcnic_83xx_rd_reg_indirect(adapter,
2266                                                           indirect_add);
2267                         if (ret == -EIO)
2268                                 return -EIO;
2269
2270                         word = ret;
2271                         *(u32 *)p_data  = word;
2272                         p_data = p_data + 4;
2273                         addr = addr + 4;
2274                 }
2275         }
2276
2277         return 0;
2278 }
2279
2280 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter)
2281 {
2282         u32 status;
2283         int retries = QLC_83XX_FLASH_READ_RETRY_COUNT;
2284
2285         do {
2286                 status = qlcnic_83xx_rd_reg_indirect(adapter,
2287                                                      QLC_83XX_FLASH_STATUS);
2288                 if ((status & QLC_83XX_FLASH_STATUS_READY) ==
2289                     QLC_83XX_FLASH_STATUS_READY)
2290                         break;
2291
2292                 msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY);
2293         } while (--retries);
2294
2295         if (!retries)
2296                 return -EIO;
2297
2298         return 0;
2299 }
2300
2301 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter)
2302 {
2303         int ret;
2304         u32 cmd;
2305         cmd = adapter->ahw->fdt.write_statusreg_cmd;
2306         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2307                                      (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd));
2308         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2309                                      adapter->ahw->fdt.write_enable_bits);
2310         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2311                                      QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2312         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2313         if (ret)
2314                 return -EIO;
2315
2316         return 0;
2317 }
2318
2319 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter)
2320 {
2321         int ret;
2322
2323         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2324                                      (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG |
2325                                      adapter->ahw->fdt.write_statusreg_cmd));
2326         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2327                                      adapter->ahw->fdt.write_disable_bits);
2328         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2329                                      QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2330         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2331         if (ret)
2332                 return -EIO;
2333
2334         return 0;
2335 }
2336
2337 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter)
2338 {
2339         int ret, mfg_id;
2340
2341         if (qlcnic_83xx_lock_flash(adapter))
2342                 return -EIO;
2343
2344         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2345                                      QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL);
2346         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2347                                      QLC_83XX_FLASH_READ_CTRL);
2348         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2349         if (ret) {
2350                 qlcnic_83xx_unlock_flash(adapter);
2351                 return -EIO;
2352         }
2353
2354         mfg_id = qlcnic_83xx_rd_reg_indirect(adapter, QLC_83XX_FLASH_RDDATA);
2355         if (mfg_id == -EIO)
2356                 return -EIO;
2357
2358         adapter->flash_mfg_id = (mfg_id & 0xFF);
2359         qlcnic_83xx_unlock_flash(adapter);
2360
2361         return 0;
2362 }
2363
2364 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter)
2365 {
2366         int count, fdt_size, ret = 0;
2367
2368         fdt_size = sizeof(struct qlcnic_fdt);
2369         count = fdt_size / sizeof(u32);
2370
2371         if (qlcnic_83xx_lock_flash(adapter))
2372                 return -EIO;
2373
2374         memset(&adapter->ahw->fdt, 0, fdt_size);
2375         ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION,
2376                                                 (u8 *)&adapter->ahw->fdt,
2377                                                 count);
2378
2379         qlcnic_83xx_unlock_flash(adapter);
2380         return ret;
2381 }
2382
2383 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter,
2384                                    u32 sector_start_addr)
2385 {
2386         u32 reversed_addr, addr1, addr2, cmd;
2387         int ret = -EIO;
2388
2389         if (qlcnic_83xx_lock_flash(adapter) != 0)
2390                 return -EIO;
2391
2392         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2393                 ret = qlcnic_83xx_enable_flash_write(adapter);
2394                 if (ret) {
2395                         qlcnic_83xx_unlock_flash(adapter);
2396                         dev_err(&adapter->pdev->dev,
2397                                 "%s failed at %d\n",
2398                                 __func__, __LINE__);
2399                         return ret;
2400                 }
2401         }
2402
2403         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2404         if (ret) {
2405                 qlcnic_83xx_unlock_flash(adapter);
2406                 dev_err(&adapter->pdev->dev,
2407                         "%s: failed at %d\n", __func__, __LINE__);
2408                 return -EIO;
2409         }
2410
2411         addr1 = (sector_start_addr & 0xFF) << 16;
2412         addr2 = (sector_start_addr & 0xFF0000) >> 16;
2413         reversed_addr = addr1 | addr2;
2414
2415         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2416                                      reversed_addr);
2417         cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd;
2418         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id)
2419                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd);
2420         else
2421                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2422                                              QLC_83XX_FLASH_OEM_ERASE_SIG);
2423         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2424                                      QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2425
2426         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2427         if (ret) {
2428                 qlcnic_83xx_unlock_flash(adapter);
2429                 dev_err(&adapter->pdev->dev,
2430                         "%s: failed at %d\n", __func__, __LINE__);
2431                 return -EIO;
2432         }
2433
2434         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2435                 ret = qlcnic_83xx_disable_flash_write(adapter);
2436                 if (ret) {
2437                         qlcnic_83xx_unlock_flash(adapter);
2438                         dev_err(&adapter->pdev->dev,
2439                                 "%s: failed at %d\n", __func__, __LINE__);
2440                         return ret;
2441                 }
2442         }
2443
2444         qlcnic_83xx_unlock_flash(adapter);
2445
2446         return 0;
2447 }
2448
2449 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr,
2450                               u32 *p_data)
2451 {
2452         int ret = -EIO;
2453         u32 addr1 = 0x00800000 | (addr >> 2);
2454
2455         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1);
2456         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data);
2457         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2458                                      QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2459         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2460         if (ret) {
2461                 dev_err(&adapter->pdev->dev,
2462                         "%s: failed at %d\n", __func__, __LINE__);
2463                 return -EIO;
2464         }
2465
2466         return 0;
2467 }
2468
2469 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr,
2470                                  u32 *p_data, int count)
2471 {
2472         u32 temp;
2473         int ret = -EIO;
2474
2475         if ((count < QLC_83XX_FLASH_WRITE_MIN) ||
2476             (count > QLC_83XX_FLASH_WRITE_MAX)) {
2477                 dev_err(&adapter->pdev->dev,
2478                         "%s: Invalid word count\n", __func__);
2479                 return -EIO;
2480         }
2481
2482         temp = qlcnic_83xx_rd_reg_indirect(adapter,
2483                                            QLC_83XX_FLASH_SPI_CONTROL);
2484         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL,
2485                                      (temp | QLC_83XX_FLASH_SPI_CTRL));
2486         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2487                                      QLC_83XX_FLASH_ADDR_TEMP_VAL);
2488
2489         /* First DWORD write */
2490         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2491         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2492                                      QLC_83XX_FLASH_FIRST_MS_PATTERN);
2493         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2494         if (ret) {
2495                 dev_err(&adapter->pdev->dev,
2496                         "%s: failed at %d\n", __func__, __LINE__);
2497                 return -EIO;
2498         }
2499
2500         count--;
2501         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2502                                      QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL);
2503         /* Second to N-1 DWORD writes */
2504         while (count != 1) {
2505                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2506                                              *p_data++);
2507                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2508                                              QLC_83XX_FLASH_SECOND_MS_PATTERN);
2509                 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2510                 if (ret) {
2511                         dev_err(&adapter->pdev->dev,
2512                                 "%s: failed at %d\n", __func__, __LINE__);
2513                         return -EIO;
2514                 }
2515                 count--;
2516         }
2517
2518         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2519                                      QLC_83XX_FLASH_ADDR_TEMP_VAL |
2520                                      (addr >> 2));
2521         /* Last DWORD write */
2522         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2523         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2524                                      QLC_83XX_FLASH_LAST_MS_PATTERN);
2525         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2526         if (ret) {
2527                 dev_err(&adapter->pdev->dev,
2528                         "%s: failed at %d\n", __func__, __LINE__);
2529                 return -EIO;
2530         }
2531
2532         ret = qlcnic_83xx_rd_reg_indirect(adapter, QLC_83XX_FLASH_SPI_STATUS);
2533         if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) {
2534                 dev_err(&adapter->pdev->dev, "%s: failed at %d\n",
2535                         __func__, __LINE__);
2536                 /* Operation failed, clear error bit */
2537                 temp = qlcnic_83xx_rd_reg_indirect(adapter,
2538                                                    QLC_83XX_FLASH_SPI_CONTROL);
2539                 qlcnic_83xx_wrt_reg_indirect(adapter,
2540                                              QLC_83XX_FLASH_SPI_CONTROL,
2541                                              (temp | QLC_83XX_FLASH_SPI_CTRL));
2542         }
2543
2544         return 0;
2545 }
2546
2547 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter)
2548 {
2549         u32 val, id;
2550
2551         val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2552
2553         /* Check if recovery need to be performed by the calling function */
2554         if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) {
2555                 val = val & ~0x3F;
2556                 val = val | ((adapter->portnum << 2) |
2557                              QLC_83XX_NEED_DRV_LOCK_RECOVERY);
2558                 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2559                 dev_info(&adapter->pdev->dev,
2560                          "%s: lock recovery initiated\n", __func__);
2561                 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY);
2562                 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2563                 id = ((val >> 2) & 0xF);
2564                 if (id == adapter->portnum) {
2565                         val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK;
2566                         val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS;
2567                         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2568                         /* Force release the lock */
2569                         QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2570                         /* Clear recovery bits */
2571                         val = val & ~0x3F;
2572                         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2573                         dev_info(&adapter->pdev->dev,
2574                                  "%s: lock recovery completed\n", __func__);
2575                 } else {
2576                         dev_info(&adapter->pdev->dev,
2577                                  "%s: func %d to resume lock recovery process\n",
2578                                  __func__, id);
2579                 }
2580         } else {
2581                 dev_info(&adapter->pdev->dev,
2582                          "%s: lock recovery initiated by other functions\n",
2583                          __func__);
2584         }
2585 }
2586
2587 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter)
2588 {
2589         u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0;
2590         int max_attempt = 0;
2591
2592         while (status == 0) {
2593                 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK);
2594                 if (status)
2595                         break;
2596
2597                 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY);
2598                 i++;
2599
2600                 if (i == 1)
2601                         temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2602
2603                 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) {
2604                         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2605                         if (val == temp) {
2606                                 id = val & 0xFF;
2607                                 dev_info(&adapter->pdev->dev,
2608                                          "%s: lock to be recovered from %d\n",
2609                                          __func__, id);
2610                                 qlcnic_83xx_recover_driver_lock(adapter);
2611                                 i = 0;
2612                                 max_attempt++;
2613                         } else {
2614                                 dev_err(&adapter->pdev->dev,
2615                                         "%s: failed to get lock\n", __func__);
2616                                 return -EIO;
2617                         }
2618                 }
2619
2620                 /* Force exit from while loop after few attempts */
2621                 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) {
2622                         dev_err(&adapter->pdev->dev,
2623                                 "%s: failed to get lock\n", __func__);
2624                         return -EIO;
2625                 }
2626         }
2627
2628         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2629         lock_alive_counter = val >> 8;
2630         lock_alive_counter++;
2631         val = lock_alive_counter << 8 | adapter->portnum;
2632         QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2633
2634         return 0;
2635 }
2636
2637 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter)
2638 {
2639         u32 val, lock_alive_counter, id;
2640
2641         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2642         id = val & 0xFF;
2643         lock_alive_counter = val >> 8;
2644
2645         if (id != adapter->portnum)
2646                 dev_err(&adapter->pdev->dev,
2647                         "%s:Warning func %d is unlocking lock owned by %d\n",
2648                         __func__, adapter->portnum, id);
2649
2650         val = (lock_alive_counter << 8) | 0xFF;
2651         QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2652         QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2653 }
2654
2655 int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr,
2656                                 u32 *data, u32 count)
2657 {
2658         int i, j, ret = 0;
2659         u32 temp;
2660
2661         /* Check alignment */
2662         if (addr & 0xF)
2663                 return -EIO;
2664
2665         mutex_lock(&adapter->ahw->mem_lock);
2666         qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_HI, 0);
2667
2668         for (i = 0; i < count; i++, addr += 16) {
2669                 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET,
2670                                      QLCNIC_ADDR_QDR_NET_MAX)) ||
2671                       (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET,
2672                                      QLCNIC_ADDR_DDR_NET_MAX)))) {
2673                         mutex_unlock(&adapter->ahw->mem_lock);
2674                         return -EIO;
2675                 }
2676
2677                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_LO, addr);
2678                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_LO,
2679                                              *data++);
2680                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_HI,
2681                                              *data++);
2682                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_ULO,
2683                                              *data++);
2684                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_UHI,
2685                                              *data++);
2686                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2687                                              QLCNIC_TA_WRITE_ENABLE);
2688                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2689                                              QLCNIC_TA_WRITE_START);
2690
2691                 for (j = 0; j < MAX_CTL_CHECK; j++) {
2692                         temp = qlcnic_83xx_rd_reg_indirect(adapter,
2693                                                            QLCNIC_MS_CTRL);
2694                         if ((temp & TA_CTL_BUSY) == 0)
2695                                 break;
2696                 }
2697
2698                 /* Status check failure */
2699                 if (j >= MAX_CTL_CHECK) {
2700                         printk_ratelimited(KERN_WARNING
2701                                            "MS memory write failed\n");
2702                         mutex_unlock(&adapter->ahw->mem_lock);
2703                         return -EIO;
2704                 }
2705         }
2706
2707         mutex_unlock(&adapter->ahw->mem_lock);
2708
2709         return ret;
2710 }
2711
2712 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr,
2713                              u8 *p_data, int count)
2714 {
2715         int i, ret;
2716         u32 word, addr = flash_addr;
2717         ulong  indirect_addr;
2718
2719         if (qlcnic_83xx_lock_flash(adapter) != 0)
2720                 return -EIO;
2721
2722         if (addr & 0x3) {
2723                 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2724                 qlcnic_83xx_unlock_flash(adapter);
2725                 return -EIO;
2726         }
2727
2728         for (i = 0; i < count; i++) {
2729                 if (qlcnic_83xx_wrt_reg_indirect(adapter,
2730                                                  QLC_83XX_FLASH_DIRECT_WINDOW,
2731                                                  (addr))) {
2732                         qlcnic_83xx_unlock_flash(adapter);
2733                         return -EIO;
2734                 }
2735
2736                 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr);
2737                 ret = qlcnic_83xx_rd_reg_indirect(adapter,
2738                                                   indirect_addr);
2739                 if (ret == -EIO)
2740                         return -EIO;
2741                 word = ret;
2742                 *(u32 *)p_data  = word;
2743                 p_data = p_data + 4;
2744                 addr = addr + 4;
2745         }
2746
2747         qlcnic_83xx_unlock_flash(adapter);
2748
2749         return 0;
2750 }
2751
2752 int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter)
2753 {
2754         int err;
2755         u32 config = 0, state;
2756         struct qlcnic_cmd_args cmd;
2757         struct qlcnic_hardware_context *ahw = adapter->ahw;
2758
2759         state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(ahw->pci_func));
2760         if (!QLC_83xx_FUNC_VAL(state, ahw->pci_func)) {
2761                 dev_info(&adapter->pdev->dev, "link state down\n");
2762                 return config;
2763         }
2764         qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
2765         err = qlcnic_issue_cmd(adapter, &cmd);
2766         if (err) {
2767                 dev_info(&adapter->pdev->dev,
2768                          "Get Link Status Command failed: 0x%x\n", err);
2769                 goto out;
2770         } else {
2771                 config = cmd.rsp.arg[1];
2772                 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) {
2773                 case QLC_83XX_10M_LINK:
2774                         ahw->link_speed = SPEED_10;
2775                         break;
2776                 case QLC_83XX_100M_LINK:
2777                         ahw->link_speed = SPEED_100;
2778                         break;
2779                 case QLC_83XX_1G_LINK:
2780                         ahw->link_speed = SPEED_1000;
2781                         break;
2782                 case QLC_83XX_10G_LINK:
2783                         ahw->link_speed = SPEED_10000;
2784                         break;
2785                 default:
2786                         ahw->link_speed = 0;
2787                         break;
2788                 }
2789                 config = cmd.rsp.arg[3];
2790                 if (config & 1)
2791                         err = 1;
2792         }
2793 out:
2794         qlcnic_free_mbx_args(&cmd);
2795         return config;
2796 }
2797
2798 int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter)
2799 {
2800         u32 config = 0;
2801         int status = 0;
2802         struct qlcnic_hardware_context *ahw = adapter->ahw;
2803
2804         /* Get port configuration info */
2805         status = qlcnic_83xx_get_port_info(adapter);
2806         /* Get Link Status related info */
2807         config = qlcnic_83xx_test_link(adapter);
2808         ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config);
2809         /* hard code until there is a way to get it from flash */
2810         ahw->board_type = QLCNIC_BRDTYPE_83XX_10G;
2811         return status;
2812 }
2813
2814 int qlcnic_83xx_set_settings(struct qlcnic_adapter *adapter,
2815                              struct ethtool_cmd *ecmd)
2816 {
2817         int status = 0;
2818         u32 config = adapter->ahw->port_config;
2819
2820         if (ecmd->autoneg)
2821                 adapter->ahw->port_config |= BIT_15;
2822
2823         switch (ethtool_cmd_speed(ecmd)) {
2824         case SPEED_10:
2825                 adapter->ahw->port_config |= BIT_8;
2826                 break;
2827         case SPEED_100:
2828                 adapter->ahw->port_config |= BIT_9;
2829                 break;
2830         case SPEED_1000:
2831                 adapter->ahw->port_config |= BIT_10;
2832                 break;
2833         case SPEED_10000:
2834                 adapter->ahw->port_config |= BIT_11;
2835                 break;
2836         default:
2837                 return -EINVAL;
2838         }
2839
2840         status = qlcnic_83xx_set_port_config(adapter);
2841         if (status) {
2842                 dev_info(&adapter->pdev->dev,
2843                          "Faild to Set Link Speed and autoneg.\n");
2844                 adapter->ahw->port_config = config;
2845         }
2846         return status;
2847 }
2848
2849 static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd,
2850                                           u64 *data, int index)
2851 {
2852         u32 low, hi;
2853         u64 val;
2854
2855         low = cmd->rsp.arg[index];
2856         hi = cmd->rsp.arg[index + 1];
2857         val = (((u64) low) | (((u64) hi) << 32));
2858         *data++ = val;
2859         return data;
2860 }
2861
2862 static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter,
2863                                    struct qlcnic_cmd_args *cmd, u64 *data,
2864                                    int type, int *ret)
2865 {
2866         int err, k, total_regs;
2867
2868         *ret = 0;
2869         err = qlcnic_issue_cmd(adapter, cmd);
2870         if (err != QLCNIC_RCODE_SUCCESS) {
2871                 dev_info(&adapter->pdev->dev,
2872                          "Error in get statistics mailbox command\n");
2873                 *ret = -EIO;
2874                 return data;
2875         }
2876         total_regs = cmd->rsp.num;
2877         switch (type) {
2878         case QLC_83XX_STAT_MAC:
2879                 /* fill in MAC tx counters */
2880                 for (k = 2; k < 28; k += 2)
2881                         data = qlcnic_83xx_copy_stats(cmd, data, k);
2882                 /* skip 24 bytes of reserved area */
2883                 /* fill in MAC rx counters */
2884                 for (k += 6; k < 60; k += 2)
2885                         data = qlcnic_83xx_copy_stats(cmd, data, k);
2886                 /* skip 24 bytes of reserved area */
2887                 /* fill in MAC rx frame stats */
2888                 for (k += 6; k < 80; k += 2)
2889                         data = qlcnic_83xx_copy_stats(cmd, data, k);
2890                 break;
2891         case QLC_83XX_STAT_RX:
2892                 for (k = 2; k < 8; k += 2)
2893                         data = qlcnic_83xx_copy_stats(cmd, data, k);
2894                 /* skip 8 bytes of reserved data */
2895                 for (k += 2; k < 24; k += 2)
2896                         data = qlcnic_83xx_copy_stats(cmd, data, k);
2897                 /* skip 8 bytes containing RE1FBQ error data */
2898                 for (k += 2; k < total_regs; k += 2)
2899                         data = qlcnic_83xx_copy_stats(cmd, data, k);
2900                 break;
2901         case QLC_83XX_STAT_TX:
2902                 for (k = 2; k < 10; k += 2)
2903                         data = qlcnic_83xx_copy_stats(cmd, data, k);
2904                 /* skip 8 bytes of reserved data */
2905                 for (k += 2; k < total_regs; k += 2)
2906                         data = qlcnic_83xx_copy_stats(cmd, data, k);
2907                 break;
2908         default:
2909                 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n");
2910                 *ret = -EIO;
2911         }
2912         return data;
2913 }
2914
2915 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data)
2916 {
2917         struct qlcnic_cmd_args cmd;
2918         int ret = 0;
2919
2920         qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS);
2921         /* Get Tx stats */
2922         cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16);
2923         cmd.rsp.num = QLC_83XX_TX_STAT_REGS;
2924         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
2925                                       QLC_83XX_STAT_TX, &ret);
2926         if (ret) {
2927                 dev_info(&adapter->pdev->dev, "Error getting MAC stats\n");
2928                 goto out;
2929         }
2930         /* Get MAC stats */
2931         cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16);
2932         cmd.rsp.num = QLC_83XX_MAC_STAT_REGS;
2933         memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
2934         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
2935                                       QLC_83XX_STAT_MAC, &ret);
2936         if (ret) {
2937                 dev_info(&adapter->pdev->dev,
2938                          "Error getting Rx stats\n");
2939                 goto out;
2940         }
2941         /* Get Rx stats */
2942         cmd.req.arg[1] = adapter->recv_ctx->context_id << 16;
2943         cmd.rsp.num = QLC_83XX_RX_STAT_REGS;
2944         memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
2945         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
2946                                       QLC_83XX_STAT_RX, &ret);
2947         if (ret)
2948                 dev_info(&adapter->pdev->dev,
2949                          "Error getting Tx stats\n");
2950 out:
2951         qlcnic_free_mbx_args(&cmd);
2952 }
2953
2954 int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter)
2955 {
2956         u32 major, minor, sub;
2957
2958         major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
2959         minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
2960         sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
2961
2962         if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) {
2963                 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n",
2964                          __func__);
2965                 return 1;
2966         }
2967         return 0;
2968 }
2969
2970 int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter)
2971 {
2972         return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) *
2973                 sizeof(adapter->ahw->ext_reg_tbl)) +
2974                 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) +
2975                 sizeof(adapter->ahw->reg_tbl));
2976 }
2977
2978 int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff)
2979 {
2980         int i, j = 0;
2981
2982         for (i = QLCNIC_DEV_INFO_SIZE + 1;
2983              j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++)
2984                 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j);
2985
2986         for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++)
2987                 regs_buff[i++] = QLCRDX(adapter->ahw, j);
2988         return i;
2989 }
2990
2991 int qlcnic_83xx_interrupt_test(struct net_device *netdev)
2992 {
2993         struct qlcnic_adapter *adapter = netdev_priv(netdev);
2994         struct qlcnic_hardware_context *ahw = adapter->ahw;
2995         struct qlcnic_cmd_args cmd;
2996         u32 data;
2997         u16 intrpt_id, id;
2998         u8 val;
2999         int ret, max_sds_rings = adapter->max_sds_rings;
3000
3001         if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
3002                 return -EIO;
3003
3004         ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST);
3005         if (ret)
3006                 goto fail_diag_irq;
3007
3008         ahw->diag_cnt = 0;
3009         qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST);
3010
3011         if (adapter->flags & QLCNIC_MSIX_ENABLED)
3012                 intrpt_id = ahw->intr_tbl[0].id;
3013         else
3014                 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
3015
3016         cmd.req.arg[1] = 1;
3017         cmd.req.arg[2] = intrpt_id;
3018         cmd.req.arg[3] = BIT_0;
3019
3020         ret = qlcnic_issue_cmd(adapter, &cmd);
3021         data = cmd.rsp.arg[2];
3022         id = LSW(data);
3023         val = LSB(MSW(data));
3024         if (id != intrpt_id)
3025                 dev_info(&adapter->pdev->dev,
3026                          "Interrupt generated: 0x%x, requested:0x%x\n",
3027                          id, intrpt_id);
3028         if (val)
3029                 dev_err(&adapter->pdev->dev,
3030                          "Interrupt test error: 0x%x\n", val);
3031         if (ret)
3032                 goto done;
3033
3034         msleep(20);
3035         ret = !ahw->diag_cnt;
3036
3037 done:
3038         qlcnic_free_mbx_args(&cmd);
3039         qlcnic_83xx_diag_free_res(netdev, max_sds_rings);
3040
3041 fail_diag_irq:
3042         adapter->max_sds_rings = max_sds_rings;
3043         clear_bit(__QLCNIC_RESETTING, &adapter->state);
3044         return ret;
3045 }
3046
3047 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter,
3048                                 struct ethtool_pauseparam *pause)
3049 {
3050         struct qlcnic_hardware_context *ahw = adapter->ahw;
3051         int status = 0;
3052         u32 config;
3053
3054         status = qlcnic_83xx_get_port_config(adapter);
3055         if (status) {
3056                 dev_err(&adapter->pdev->dev,
3057                         "%s: Get Pause Config failed\n", __func__);
3058                 return;
3059         }
3060         config = ahw->port_config;
3061         if (config & QLC_83XX_CFG_STD_PAUSE) {
3062                 if (config & QLC_83XX_CFG_STD_TX_PAUSE)
3063                         pause->tx_pause = 1;
3064                 if (config & QLC_83XX_CFG_STD_RX_PAUSE)
3065                         pause->rx_pause = 1;
3066         }
3067
3068         if (QLC_83XX_AUTONEG(config))
3069                 pause->autoneg = 1;
3070 }
3071
3072 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter,
3073                                struct ethtool_pauseparam *pause)
3074 {
3075         struct qlcnic_hardware_context *ahw = adapter->ahw;
3076         int status = 0;
3077         u32 config;
3078
3079         status = qlcnic_83xx_get_port_config(adapter);
3080         if (status) {
3081                 dev_err(&adapter->pdev->dev,
3082                         "%s: Get Pause Config failed.\n", __func__);
3083                 return status;
3084         }
3085         config = ahw->port_config;
3086
3087         if (ahw->port_type == QLCNIC_GBE) {
3088                 if (pause->autoneg)
3089                         ahw->port_config |= QLC_83XX_ENABLE_AUTONEG;
3090                 if (!pause->autoneg)
3091                         ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG;
3092         } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) {
3093                 return -EOPNOTSUPP;
3094         }
3095
3096         if (!(config & QLC_83XX_CFG_STD_PAUSE))
3097                 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE;
3098
3099         if (pause->rx_pause && pause->tx_pause) {
3100                 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE;
3101         } else if (pause->rx_pause && !pause->tx_pause) {
3102                 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE;
3103                 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE;
3104         } else if (pause->tx_pause && !pause->rx_pause) {
3105                 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE;
3106                 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE;
3107         } else if (!pause->rx_pause && !pause->tx_pause) {
3108                 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_RX_PAUSE;
3109         }
3110         status = qlcnic_83xx_set_port_config(adapter);
3111         if (status) {
3112                 dev_err(&adapter->pdev->dev,
3113                         "%s: Set Pause Config failed.\n", __func__);
3114                 ahw->port_config = config;
3115         }
3116         return status;
3117 }
3118
3119 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter)
3120 {
3121         int ret;
3122
3123         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
3124                                      QLC_83XX_FLASH_OEM_READ_SIG);
3125         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
3126                                      QLC_83XX_FLASH_READ_CTRL);
3127         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
3128         if (ret)
3129                 return -EIO;
3130
3131         ret = qlcnic_83xx_rd_reg_indirect(adapter, QLC_83XX_FLASH_RDDATA);
3132         return ret & 0xFF;
3133 }
3134
3135 int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter)
3136 {
3137         int status;
3138
3139         status = qlcnic_83xx_read_flash_status_reg(adapter);
3140         if (status == -EIO) {
3141                 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n",
3142                          __func__);
3143                 return 1;
3144         }
3145         return 0;
3146 }