2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/mutex.h>
41 #include <linux/radix-tree.h>
42 #include <linux/timer.h>
43 #include <linux/semaphore.h>
44 #include <linux/workqueue.h>
46 #include <linux/mlx4/device.h>
47 #include <linux/mlx4/driver.h>
48 #include <linux/mlx4/doorbell.h>
49 #include <linux/mlx4/cmd.h>
51 #define DRV_NAME "mlx4_core"
52 #define PFX DRV_NAME ": "
53 #define DRV_VERSION "1.1"
54 #define DRV_RELDATE "Dec, 2011"
57 MLX4_HCR_BASE = 0x80680,
58 MLX4_HCR_SIZE = 0x0001c,
59 MLX4_CLR_INT_SIZE = 0x00008,
60 MLX4_SLAVE_COMM_BASE = 0x0,
61 MLX4_COMM_PAGESIZE = 0x1000
65 MLX4_MAX_MGM_ENTRY_SIZE = 0x1000,
66 MLX4_MAX_QP_PER_MGM = 4 * (MLX4_MAX_MGM_ENTRY_SIZE / 16 - 2),
67 MLX4_MTT_ENTRY_PER_SEG = 8,
71 MLX4_NUM_PDS = 1 << 15
75 MLX4_CMPT_TYPE_QP = 0,
76 MLX4_CMPT_TYPE_SRQ = 1,
77 MLX4_CMPT_TYPE_CQ = 2,
78 MLX4_CMPT_TYPE_EQ = 3,
84 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
93 #define MLX4_COMM_TIME 10000
99 MLX4_COMM_CMD_VHCR_EN,
100 MLX4_COMM_CMD_VHCR_POST,
101 MLX4_COMM_CMD_FLR = 254
104 /*The flag indicates that the slave should delay the RESET cmd*/
105 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
106 /*indicates how many retries will be done if we are in the middle of FLR*/
107 #define NUM_OF_RESET_RETRIES 10
108 #define SLEEP_TIME_IN_RESET (2 * 1000)
120 MLX4_NUM_OF_RESOURCE_TYPE
123 enum mlx4_alloc_mode {
125 RES_OP_RESERVE_AND_MAP,
131 *Virtual HCR structures.
132 * mlx4_vhcr is the sw representation, in machine endianess
134 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
135 * to FW to go through communication channel.
136 * It is big endian, and has the same structure as the physical HCR
137 * used by command interface
150 struct mlx4_vhcr_cmd {
161 struct mlx4_cmd_info {
166 bool encode_slave_id;
167 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
168 struct mlx4_cmd_mailbox *inbox);
169 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
170 struct mlx4_cmd_mailbox *inbox,
171 struct mlx4_cmd_mailbox *outbox,
172 struct mlx4_cmd_info *cmd);
175 #ifdef CONFIG_MLX4_DEBUG
176 extern int mlx4_debug_level;
177 #else /* CONFIG_MLX4_DEBUG */
178 #define mlx4_debug_level (0)
179 #endif /* CONFIG_MLX4_DEBUG */
181 #define mlx4_dbg(mdev, format, arg...) \
183 if (mlx4_debug_level) \
184 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
187 #define mlx4_err(mdev, format, arg...) \
188 dev_err(&mdev->pdev->dev, format, ##arg)
189 #define mlx4_info(mdev, format, arg...) \
190 dev_info(&mdev->pdev->dev, format, ##arg)
191 #define mlx4_warn(mdev, format, arg...) \
192 dev_warn(&mdev->pdev->dev, format, ##arg)
194 extern int mlx4_log_num_mgm_entry_size;
195 extern int log_mtts_per_seg;
197 #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
198 #define ALL_SLAVES 0xff
208 unsigned long *table;
212 unsigned long **bits;
213 unsigned int *num_free;
220 struct mlx4_icm_table {
228 struct mlx4_icm **icm;
232 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
234 struct mlx4_mpt_entry {
248 __be32 first_byte_offset;
252 * Must be packed because start is 64 bits but only aligned to 32 bits.
254 struct mlx4_eq_context {
268 __be32 mtt_base_addr_l;
270 __be32 consumer_index;
271 __be32 producer_index;
275 struct mlx4_cq_context {
279 __be32 logsize_usrpage;
287 __be32 mtt_base_addr_l;
288 __be32 last_notified_index;
289 __be32 solicit_producer_index;
290 __be32 consumer_index;
291 __be32 producer_index;
296 struct mlx4_srq_context {
297 __be32 state_logsize_srqn;
301 __be32 pg_offset_cqn;
306 __be32 mtt_base_addr_l;
308 __be16 limit_watermark;
349 } __packed port_change;
351 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
353 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
354 } __packed comm_channel_arm;
359 } __packed mac_update;
365 } __packed flr_event;
367 __be16 current_temperature;
368 __be16 warning_threshold;
377 struct mlx4_dev *dev;
378 void __iomem *doorbell;
384 struct mlx4_buf_list *page_list;
388 struct mlx4_slave_eqe {
394 struct mlx4_slave_event_eq_info {
399 struct mlx4_profile {
413 struct mlx4_icm *fw_icm;
414 struct mlx4_icm *aux_icm;
428 MLX4_MCAST_CONFIG = 0,
429 MLX4_MCAST_DISABLE = 1,
430 MLX4_MCAST_ENABLE = 2,
433 #define VLAN_FLTR_SIZE 128
435 struct mlx4_vlan_fltr {
436 __be32 entry[VLAN_FLTR_SIZE];
439 struct mlx4_mcast_entry {
440 struct list_head list;
444 struct mlx4_promisc_qp {
445 struct list_head list;
449 struct mlx4_steer_index {
450 struct list_head list;
452 struct list_head duplicates;
455 #define MLX4_EVENT_TYPES_NUM 64
457 struct mlx4_slave_state {
464 u16 mtu[MLX4_MAX_PORTS + 1];
465 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
466 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
467 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
468 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
469 /* event type to eq number lookup */
470 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
474 /*initialized via the kzalloc*/
475 u8 is_slave_going_down;
481 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
484 struct mlx4_resource_tracker {
486 /* tree for each resources */
487 struct radix_tree_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
488 /* num_of_slave's lists, one per slave */
489 struct slave_list *slave_list;
492 #define SLAVE_EVENT_EQ_SIZE 128
493 struct mlx4_slave_event_eq {
497 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
500 struct mlx4_master_qp0_state {
501 int proxy_qp0_active;
506 struct mlx4_mfunc_master_ctx {
507 struct mlx4_slave_state *slave_state;
508 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
509 int init_port_ref[MLX4_MAX_PORTS + 1];
510 u16 max_mtu[MLX4_MAX_PORTS + 1];
511 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
512 struct mlx4_resource_tracker res_tracker;
513 struct workqueue_struct *comm_wq;
514 struct work_struct comm_work;
515 struct work_struct slave_event_work;
516 struct work_struct slave_flr_event_work;
517 spinlock_t slave_state_lock;
518 __be32 comm_arm_bit_vector[4];
519 struct mlx4_eqe cmd_eqe;
520 struct mlx4_slave_event_eq slave_eq;
521 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
525 struct mlx4_comm __iomem *comm;
526 struct mlx4_vhcr_cmd *vhcr;
529 struct mlx4_mfunc_master_ctx master;
533 struct pci_pool *pool;
535 struct mutex hcr_mutex;
536 struct semaphore poll_sem;
537 struct semaphore event_sem;
538 struct semaphore slave_sem;
540 spinlock_t context_lock;
542 struct mlx4_cmd_context *context;
549 struct mlx4_uar_table {
550 struct mlx4_bitmap bitmap;
553 struct mlx4_mr_table {
554 struct mlx4_bitmap mpt_bitmap;
555 struct mlx4_buddy mtt_buddy;
558 struct mlx4_icm_table mtt_table;
559 struct mlx4_icm_table dmpt_table;
562 struct mlx4_cq_table {
563 struct mlx4_bitmap bitmap;
565 struct radix_tree_root tree;
566 struct mlx4_icm_table table;
567 struct mlx4_icm_table cmpt_table;
570 struct mlx4_eq_table {
571 struct mlx4_bitmap bitmap;
573 void __iomem *clr_int;
574 void __iomem **uar_map;
577 struct mlx4_icm_table table;
578 struct mlx4_icm_table cmpt_table;
583 struct mlx4_srq_table {
584 struct mlx4_bitmap bitmap;
586 struct radix_tree_root tree;
587 struct mlx4_icm_table table;
588 struct mlx4_icm_table cmpt_table;
591 struct mlx4_qp_table {
592 struct mlx4_bitmap bitmap;
596 struct mlx4_icm_table qp_table;
597 struct mlx4_icm_table auxc_table;
598 struct mlx4_icm_table altc_table;
599 struct mlx4_icm_table rdmarc_table;
600 struct mlx4_icm_table cmpt_table;
603 struct mlx4_mcg_table {
605 struct mlx4_bitmap bitmap;
606 struct mlx4_icm_table table;
609 struct mlx4_catas_err {
611 struct timer_list timer;
612 struct list_head list;
615 #define MLX4_MAX_MAC_NUM 128
616 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
618 struct mlx4_mac_table {
619 __be64 entries[MLX4_MAX_MAC_NUM];
620 int refs[MLX4_MAX_MAC_NUM];
626 #define MLX4_MAX_VLAN_NUM 128
627 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
629 struct mlx4_vlan_table {
630 __be32 entries[MLX4_MAX_VLAN_NUM];
631 int refs[MLX4_MAX_VLAN_NUM];
637 #define SET_PORT_GEN_ALL_VALID 0x7
638 #define SET_PORT_PROMISC_SHIFT 31
639 #define SET_PORT_MC_PROMISC_SHIFT 30
642 MCAST_DIRECT_ONLY = 0,
648 struct mlx4_set_port_general_context {
661 struct mlx4_set_port_rqp_calc_context {
679 struct mlx4_mac_entry {
683 struct mlx4_port_info {
684 struct mlx4_dev *dev;
687 struct device_attribute port_attr;
688 enum mlx4_port_type tmp_type;
689 char dev_mtu_name[16];
690 struct device_attribute port_mtu_attr;
691 struct mlx4_mac_table mac_table;
692 struct radix_tree_root mac_tree;
693 struct mlx4_vlan_table vlan_table;
698 struct mlx4_dev *dev;
699 u8 do_sense_port[MLX4_MAX_PORTS + 1];
700 u8 sense_allowed[MLX4_MAX_PORTS + 1];
701 struct delayed_work sense_poll;
704 struct mlx4_msix_ctl {
706 spinlock_t pool_lock;
710 struct list_head promisc_qps[MLX4_NUM_STEERS];
711 struct list_head steer_entries[MLX4_NUM_STEERS];
712 struct list_head high_prios;
718 struct list_head dev_list;
719 struct list_head ctx_list;
722 struct list_head pgdir_list;
723 struct mutex pgdir_mutex;
727 struct mlx4_mfunc mfunc;
729 struct mlx4_bitmap pd_bitmap;
730 struct mlx4_bitmap xrcd_bitmap;
731 struct mlx4_uar_table uar_table;
732 struct mlx4_mr_table mr_table;
733 struct mlx4_cq_table cq_table;
734 struct mlx4_eq_table eq_table;
735 struct mlx4_srq_table srq_table;
736 struct mlx4_qp_table qp_table;
737 struct mlx4_mcg_table mcg_table;
738 struct mlx4_bitmap counters_bitmap;
740 struct mlx4_catas_err catas_err;
742 void __iomem *clr_base;
744 struct mlx4_uar driver_uar;
746 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
747 struct mlx4_sense sense;
748 struct mutex port_mutex;
749 struct mlx4_msix_ctl msix_ctl;
750 struct mlx4_steer *steer;
751 struct list_head bf_list;
752 struct mutex bf_mutex;
753 struct io_mapping *bf_mapping;
757 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
759 return container_of(dev, struct mlx4_priv, dev);
762 #define MLX4_SENSE_RANGE (HZ * 3)
764 extern struct workqueue_struct *mlx4_wq;
766 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
767 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
768 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
769 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
770 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
771 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
772 u32 reserved_bot, u32 resetrved_top);
773 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
775 int mlx4_reset(struct mlx4_dev *dev);
777 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
778 void mlx4_free_eq_table(struct mlx4_dev *dev);
780 int mlx4_init_pd_table(struct mlx4_dev *dev);
781 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
782 int mlx4_init_uar_table(struct mlx4_dev *dev);
783 int mlx4_init_mr_table(struct mlx4_dev *dev);
784 int mlx4_init_eq_table(struct mlx4_dev *dev);
785 int mlx4_init_cq_table(struct mlx4_dev *dev);
786 int mlx4_init_qp_table(struct mlx4_dev *dev);
787 int mlx4_init_srq_table(struct mlx4_dev *dev);
788 int mlx4_init_mcg_table(struct mlx4_dev *dev);
790 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
791 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
792 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
793 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
794 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
795 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
796 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
797 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
798 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
799 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
800 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
801 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
802 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
803 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
804 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
805 int __mlx4_mr_reserve(struct mlx4_dev *dev);
806 void __mlx4_mr_release(struct mlx4_dev *dev, u32 index);
807 int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index);
808 void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index);
809 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
810 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
812 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
813 struct mlx4_vhcr *vhcr,
814 struct mlx4_cmd_mailbox *inbox,
815 struct mlx4_cmd_mailbox *outbox,
816 struct mlx4_cmd_info *cmd);
817 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
818 struct mlx4_vhcr *vhcr,
819 struct mlx4_cmd_mailbox *inbox,
820 struct mlx4_cmd_mailbox *outbox,
821 struct mlx4_cmd_info *cmd);
822 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
823 struct mlx4_vhcr *vhcr,
824 struct mlx4_cmd_mailbox *inbox,
825 struct mlx4_cmd_mailbox *outbox,
826 struct mlx4_cmd_info *cmd);
827 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
828 struct mlx4_vhcr *vhcr,
829 struct mlx4_cmd_mailbox *inbox,
830 struct mlx4_cmd_mailbox *outbox,
831 struct mlx4_cmd_info *cmd);
832 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
833 struct mlx4_vhcr *vhcr,
834 struct mlx4_cmd_mailbox *inbox,
835 struct mlx4_cmd_mailbox *outbox,
836 struct mlx4_cmd_info *cmd);
837 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
838 struct mlx4_vhcr *vhcr,
839 struct mlx4_cmd_mailbox *inbox,
840 struct mlx4_cmd_mailbox *outbox,
841 struct mlx4_cmd_info *cmd);
842 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
843 struct mlx4_vhcr *vhcr,
844 struct mlx4_cmd_mailbox *inbox,
845 struct mlx4_cmd_mailbox *outbox,
846 struct mlx4_cmd_info *cmd);
847 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
849 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
850 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
851 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
852 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
853 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
854 int start_index, int npages, u64 *page_list);
856 void mlx4_start_catas_poll(struct mlx4_dev *dev);
857 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
858 void mlx4_catas_init(void);
859 int mlx4_restart_one(struct pci_dev *pdev);
860 int mlx4_register_device(struct mlx4_dev *dev);
861 void mlx4_unregister_device(struct mlx4_dev *dev);
862 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, int port);
865 struct mlx4_init_hca_param;
867 u64 mlx4_make_profile(struct mlx4_dev *dev,
868 struct mlx4_profile *request,
869 struct mlx4_dev_cap *dev_cap,
870 struct mlx4_init_hca_param *init_hca);
871 void mlx4_master_comm_channel(struct work_struct *work);
872 void mlx4_gen_slave_eqe(struct work_struct *work);
873 void mlx4_master_handle_slave_flr(struct work_struct *work);
875 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
876 struct mlx4_vhcr *vhcr,
877 struct mlx4_cmd_mailbox *inbox,
878 struct mlx4_cmd_mailbox *outbox,
879 struct mlx4_cmd_info *cmd);
880 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
881 struct mlx4_vhcr *vhcr,
882 struct mlx4_cmd_mailbox *inbox,
883 struct mlx4_cmd_mailbox *outbox,
884 struct mlx4_cmd_info *cmd);
885 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
886 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
887 struct mlx4_cmd_mailbox *outbox,
888 struct mlx4_cmd_info *cmd);
889 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
890 struct mlx4_vhcr *vhcr,
891 struct mlx4_cmd_mailbox *inbox,
892 struct mlx4_cmd_mailbox *outbox,
893 struct mlx4_cmd_info *cmd);
894 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
895 struct mlx4_vhcr *vhcr,
896 struct mlx4_cmd_mailbox *inbox,
897 struct mlx4_cmd_mailbox *outbox,
898 struct mlx4_cmd_info *cmd);
899 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
900 struct mlx4_vhcr *vhcr,
901 struct mlx4_cmd_mailbox *inbox,
902 struct mlx4_cmd_mailbox *outbox,
903 struct mlx4_cmd_info *cmd);
904 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
905 struct mlx4_vhcr *vhcr,
906 struct mlx4_cmd_mailbox *inbox,
907 struct mlx4_cmd_mailbox *outbox,
908 struct mlx4_cmd_info *cmd);
909 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
910 struct mlx4_vhcr *vhcr,
911 struct mlx4_cmd_mailbox *inbox,
912 struct mlx4_cmd_mailbox *outbox,
913 struct mlx4_cmd_info *cmd);
914 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
915 struct mlx4_vhcr *vhcr,
916 struct mlx4_cmd_mailbox *inbox,
917 struct mlx4_cmd_mailbox *outbox,
918 struct mlx4_cmd_info *cmd);
919 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
920 struct mlx4_vhcr *vhcr,
921 struct mlx4_cmd_mailbox *inbox,
922 struct mlx4_cmd_mailbox *outbox,
923 struct mlx4_cmd_info *cmd);
924 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
925 struct mlx4_vhcr *vhcr,
926 struct mlx4_cmd_mailbox *inbox,
927 struct mlx4_cmd_mailbox *outbox,
928 struct mlx4_cmd_info *cmd);
929 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
930 struct mlx4_vhcr *vhcr,
931 struct mlx4_cmd_mailbox *inbox,
932 struct mlx4_cmd_mailbox *outbox,
933 struct mlx4_cmd_info *cmd);
934 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
935 struct mlx4_vhcr *vhcr,
936 struct mlx4_cmd_mailbox *inbox,
937 struct mlx4_cmd_mailbox *outbox,
938 struct mlx4_cmd_info *cmd);
939 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
940 struct mlx4_vhcr *vhcr,
941 struct mlx4_cmd_mailbox *inbox,
942 struct mlx4_cmd_mailbox *outbox,
943 struct mlx4_cmd_info *cmd);
944 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
945 struct mlx4_vhcr *vhcr,
946 struct mlx4_cmd_mailbox *inbox,
947 struct mlx4_cmd_mailbox *outbox,
948 struct mlx4_cmd_info *cmd);
949 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
950 struct mlx4_vhcr *vhcr,
951 struct mlx4_cmd_mailbox *inbox,
952 struct mlx4_cmd_mailbox *outbox,
953 struct mlx4_cmd_info *cmd);
954 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
955 struct mlx4_vhcr *vhcr,
956 struct mlx4_cmd_mailbox *inbox,
957 struct mlx4_cmd_mailbox *outbox,
958 struct mlx4_cmd_info *cmd);
959 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
960 struct mlx4_vhcr *vhcr,
961 struct mlx4_cmd_mailbox *inbox,
962 struct mlx4_cmd_mailbox *outbox,
963 struct mlx4_cmd_info *cmd);
965 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
967 int mlx4_cmd_init(struct mlx4_dev *dev);
968 void mlx4_cmd_cleanup(struct mlx4_dev *dev);
969 int mlx4_multi_func_init(struct mlx4_dev *dev);
970 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
971 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
972 int mlx4_cmd_use_events(struct mlx4_dev *dev);
973 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
975 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
976 unsigned long timeout);
978 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
979 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
981 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
983 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
985 void mlx4_handle_catas_err(struct mlx4_dev *dev);
987 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
988 enum mlx4_port_type *type);
989 void mlx4_do_sense_ports(struct mlx4_dev *dev,
990 enum mlx4_port_type *stype,
991 enum mlx4_port_type *defaults);
992 void mlx4_start_sense(struct mlx4_dev *dev);
993 void mlx4_stop_sense(struct mlx4_dev *dev);
994 void mlx4_sense_init(struct mlx4_dev *dev);
995 int mlx4_check_port_params(struct mlx4_dev *dev,
996 enum mlx4_port_type *port_type);
997 int mlx4_change_port_types(struct mlx4_dev *dev,
998 enum mlx4_port_type *port_types);
1000 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1001 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1003 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port);
1004 /* resource tracker functions*/
1005 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1006 enum mlx4_resource resource_type,
1007 int resource_id, int *slave);
1008 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1009 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1011 void mlx4_free_resource_tracker(struct mlx4_dev *dev);
1013 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1014 struct mlx4_vhcr *vhcr,
1015 struct mlx4_cmd_mailbox *inbox,
1016 struct mlx4_cmd_mailbox *outbox,
1017 struct mlx4_cmd_info *cmd);
1018 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1019 struct mlx4_vhcr *vhcr,
1020 struct mlx4_cmd_mailbox *inbox,
1021 struct mlx4_cmd_mailbox *outbox,
1022 struct mlx4_cmd_info *cmd);
1023 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1024 struct mlx4_vhcr *vhcr,
1025 struct mlx4_cmd_mailbox *inbox,
1026 struct mlx4_cmd_mailbox *outbox,
1027 struct mlx4_cmd_info *cmd);
1028 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1029 struct mlx4_vhcr *vhcr,
1030 struct mlx4_cmd_mailbox *inbox,
1031 struct mlx4_cmd_mailbox *outbox,
1032 struct mlx4_cmd_info *cmd);
1033 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1034 int mlx4_check_ext_port_caps(struct mlx4_dev *dev, u8 port);
1037 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1038 struct mlx4_vhcr *vhcr,
1039 struct mlx4_cmd_mailbox *inbox,
1040 struct mlx4_cmd_mailbox *outbox,
1041 struct mlx4_cmd_info *cmd);
1043 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1044 struct mlx4_vhcr *vhcr,
1045 struct mlx4_cmd_mailbox *inbox,
1046 struct mlx4_cmd_mailbox *outbox,
1047 struct mlx4_cmd_info *cmd);
1048 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1049 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1050 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1051 int block_mcast_loopback, enum mlx4_protocol prot,
1052 enum mlx4_steer_type steer);
1053 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1054 struct mlx4_vhcr *vhcr,
1055 struct mlx4_cmd_mailbox *inbox,
1056 struct mlx4_cmd_mailbox *outbox,
1057 struct mlx4_cmd_info *cmd);
1058 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1059 struct mlx4_vhcr *vhcr,
1060 struct mlx4_cmd_mailbox *inbox,
1061 struct mlx4_cmd_mailbox *outbox,
1062 struct mlx4_cmd_info *cmd);
1063 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1064 int port, void *buf);
1065 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1066 struct mlx4_cmd_mailbox *outbox);
1067 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1068 struct mlx4_vhcr *vhcr,
1069 struct mlx4_cmd_mailbox *inbox,
1070 struct mlx4_cmd_mailbox *outbox,
1071 struct mlx4_cmd_info *cmd);
1072 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1073 struct mlx4_vhcr *vhcr,
1074 struct mlx4_cmd_mailbox *inbox,
1075 struct mlx4_cmd_mailbox *outbox,
1076 struct mlx4_cmd_info *cmd);
1077 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1078 struct mlx4_vhcr *vhcr,
1079 struct mlx4_cmd_mailbox *inbox,
1080 struct mlx4_cmd_mailbox *outbox,
1081 struct mlx4_cmd_info *cmd);
1083 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1084 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1086 static inline void set_param_l(u64 *arg, u32 val)
1088 *((u32 *)arg) = val;
1091 static inline void set_param_h(u64 *arg, u32 val)
1093 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1096 static inline u32 get_param_l(u64 *arg)
1098 return (u32) (*arg & 0xffffffff);
1101 static inline u32 get_param_h(u64 *arg)
1103 return (u32)(*arg >> 32);
1106 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1108 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1111 #define NOT_MASKED_PD_BITS 17