drivers/net/ethernet/mellanox/mlx4/main.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  */
  35
  36 #include <linux/module.h>
  37 #include <linux/init.h>
  38 #include <linux/errno.h>
  39 #include <linux/pci.h>
  40 #include <linux/dma-mapping.h>
  41 #include <linux/slab.h>
  42 #include <linux/io-mapping.h>
  43
  44 #include <linux/mlx4/device.h>
  45 #include <linux/mlx4/doorbell.h>
  46
  47 #include "mlx4.h"
  48 #include "fw.h"
  49 #include "icm.h"
  50
  51 MODULE_AUTHOR("Roland Dreier");
  52 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
  53 MODULE_LICENSE("Dual BSD/GPL");
  54 MODULE_VERSION(DRV_VERSION);
  55
  56 struct workqueue_struct *mlx4_wq;
  57
  58 #ifdef CONFIG_MLX4_DEBUG
  59
  60 int mlx4_debug_level = 0;
  61 module_param_named(debug_level, mlx4_debug_level, int, 0644);
  62 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  63
  64 #endif /* CONFIG_MLX4_DEBUG */
  65
  66 #ifdef CONFIG_PCI_MSI
  67
  68 static int msi_x = 1;
  69 module_param(msi_x, int, 0444);
  70 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  71
  72 #else /* CONFIG_PCI_MSI */
  73
  74 #define msi_x (0)
  75
  76 #endif /* CONFIG_PCI_MSI */
  77
  78 static char mlx4_version[] __devinitdata =
  79         DRV_NAME ": Mellanox ConnectX core driver v"
  80         DRV_VERSION " (" DRV_RELDATE ")\n";
  81
  82 static struct mlx4_profile default_profile = {
  83         .num_qp         = 1 << 17,
  84         .num_srq        = 1 << 16,
  85         .rdmarc_per_qp  = 1 << 4,
  86         .num_cq         = 1 << 16,
  87         .num_mcg        = 1 << 13,
  88         .num_mpt        = 1 << 17,
  89         .num_mtt        = 1 << 20,
  90 };
  91
  92 static int log_num_mac = 2;
  93 module_param_named(log_num_mac, log_num_mac, int, 0444);
  94 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
  95
  96 static int log_num_vlan;
  97 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
  98 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
  99 /* Log2 max number of VLANs per ETH port (0-7) */
 100 #define MLX4_LOG_NUM_VLANS 7
 101
 102 static int use_prio;
 103 module_param_named(use_prio, use_prio, bool, 0444);
 104 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
 105                   "(0/1, default 0)");
 106
 107 static int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
 108 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
 109 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
 110
 111 int mlx4_check_port_params(struct mlx4_dev *dev,
 112                            enum mlx4_port_type *port_type)
 113 {
 114         int i;
 115
 116         for (i = 0; i < dev->caps.num_ports - 1; i++) {
 117                 if (port_type[i] != port_type[i + 1]) {
 118                         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
 119                                 mlx4_err(dev, "Only same port types supported "
 120                                          "on this HCA, aborting.\n");
 121                                 return -EINVAL;
 122                         }
 123                         if (port_type[i] == MLX4_PORT_TYPE_ETH &&
 124                             port_type[i + 1] == MLX4_PORT_TYPE_IB)
 125                                 return -EINVAL;
 126                 }
 127         }
 128
 129         for (i = 0; i < dev->caps.num_ports; i++) {
 130                 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
 131                         mlx4_err(dev, "Requested port type for port %d is not "
 132                                       "supported on this HCA\n", i + 1);
 133                         return -EINVAL;
 134                 }
 135         }
 136         return 0;
 137 }
 138
 139 static void mlx4_set_port_mask(struct mlx4_dev *dev)
 140 {
 141         int i;
 142
 143         dev->caps.port_mask = 0;
 144         for (i = 1; i <= dev->caps.num_ports; ++i)
 145                 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_IB)
 146                         dev->caps.port_mask |= 1 << (i - 1);
 147 }
 148
 149 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
 150 {
 151         int err;
 152         int i;
 153
 154         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
 155         if (err) {
 156                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
 157                 return err;
 158         }
 159
 160         if (dev_cap->min_page_sz > PAGE_SIZE) {
 161                 mlx4_err(dev, "HCA minimum page size of %d bigger than "
 162                          "kernel PAGE_SIZE of %ld, aborting.\n",
 163                          dev_cap->min_page_sz, PAGE_SIZE);
 164                 return -ENODEV;
 165         }
 166         if (dev_cap->num_ports > MLX4_MAX_PORTS) {
 167                 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
 168                          "aborting.\n",
 169                          dev_cap->num_ports, MLX4_MAX_PORTS);
 170                 return -ENODEV;
 171         }
 172
 173         if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
 174                 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
 175                          "PCI resource 2 size of 0x%llx, aborting.\n",
 176                          dev_cap->uar_size,
 177                          (unsigned long long) pci_resource_len(dev->pdev, 2));
 178                 return -ENODEV;
 179         }
 180
 181         dev->caps.num_ports          = dev_cap->num_ports;
 182         for (i = 1; i <= dev->caps.num_ports; ++i) {
 183                 dev->caps.vl_cap[i]         = dev_cap->max_vl[i];
 184                 dev->caps.ib_mtu_cap[i]     = dev_cap->ib_mtu[i];
 185                 dev->caps.gid_table_len[i]  = dev_cap->max_gids[i];
 186                 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
 187                 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
 188                 dev->caps.eth_mtu_cap[i]    = dev_cap->eth_mtu[i];
 189                 dev->caps.def_mac[i]        = dev_cap->def_mac[i];
 190                 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
 191                 dev->caps.trans_type[i]     = dev_cap->trans_type[i];
 192                 dev->caps.vendor_oui[i]     = dev_cap->vendor_oui[i];
 193                 dev->caps.wavelength[i]     = dev_cap->wavelength[i];
 194                 dev->caps.trans_code[i]     = dev_cap->trans_code[i];
 195         }
 196
 197         dev->caps.num_uars           = dev_cap->uar_size / PAGE_SIZE;
 198         dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
 199         dev->caps.bf_reg_size        = dev_cap->bf_reg_size;
 200         dev->caps.bf_regs_per_page   = dev_cap->bf_regs_per_page;
 201         dev->caps.max_sq_sg          = dev_cap->max_sq_sg;
 202         dev->caps.max_rq_sg          = dev_cap->max_rq_sg;
 203         dev->caps.max_wqes           = dev_cap->max_qp_sz;
 204         dev->caps.max_qp_init_rdma   = dev_cap->max_requester_per_qp;
 205         dev->caps.max_srq_wqes       = dev_cap->max_srq_sz;
 206         dev->caps.max_srq_sge        = dev_cap->max_rq_sg - 1;
 207         dev->caps.reserved_srqs      = dev_cap->reserved_srqs;
 208         dev->caps.max_sq_desc_sz     = dev_cap->max_sq_desc_sz;
 209         dev->caps.max_rq_desc_sz     = dev_cap->max_rq_desc_sz;
 210         dev->caps.num_qp_per_mgm     = MLX4_QP_PER_MGM;
 211         /*
 212          * Subtract 1 from the limit because we need to allocate a
 213          * spare CQE so the HCA HW can tell the difference between an
 214          * empty CQ and a full CQ.
 215          */
 216         dev->caps.max_cqes           = dev_cap->max_cq_sz - 1;
 217         dev->caps.reserved_cqs       = dev_cap->reserved_cqs;
 218         dev->caps.reserved_eqs       = dev_cap->reserved_eqs;
 219         dev->caps.mtts_per_seg       = 1 << log_mtts_per_seg;
 220         dev->caps.reserved_mtts      = DIV_ROUND_UP(dev_cap->reserved_mtts,
 221                                                     dev->caps.mtts_per_seg);
 222         dev->caps.reserved_mrws      = dev_cap->reserved_mrws;
 223         dev->caps.reserved_uars      = dev_cap->reserved_uars;
 224         dev->caps.reserved_pds       = dev_cap->reserved_pds;
 225         dev->caps.reserved_xrcds     = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
 226                                         dev_cap->reserved_xrcds : 0;
 227         dev->caps.max_xrcds          = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
 228                                         dev_cap->max_xrcds : 0;
 229         dev->caps.mtt_entry_sz       = dev->caps.mtts_per_seg * dev_cap->mtt_entry_sz;
 230         dev->caps.max_msg_sz         = dev_cap->max_msg_sz;
 231         dev->caps.page_size_cap      = ~(u32) (dev_cap->min_page_sz - 1);
 232         dev->caps.flags              = dev_cap->flags;
 233         dev->caps.bmme_flags         = dev_cap->bmme_flags;
 234         dev->caps.reserved_lkey      = dev_cap->reserved_lkey;
 235         dev->caps.stat_rate_support  = dev_cap->stat_rate_support;
 236         dev->caps.max_gso_sz         = dev_cap->max_gso_sz;
 237         dev->caps.wol_port[1]          = dev_cap->wol_port[1];
 238         dev->caps.wol_port[2]          = dev_cap->wol_port[2];
 239
 240         dev->caps.log_num_macs  = log_num_mac;
 241         dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
 242         dev->caps.log_num_prios = use_prio ? 3 : 0;
 243
 244         for (i = 1; i <= dev->caps.num_ports; ++i) {
 245                 if (dev->caps.supported_type[i] != MLX4_PORT_TYPE_ETH)
 246                         dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
 247                 else
 248                         dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
 249                 dev->caps.possible_type[i] = dev->caps.port_type[i];
 250                 mlx4_priv(dev)->sense.sense_allowed[i] =
 251                         dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO;
 252
 253                 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
 254                         dev->caps.log_num_macs = dev_cap->log_max_macs[i];
 255                         mlx4_warn(dev, "Requested number of MACs is too much "
 256                                   "for port %d, reducing to %d.\n",
 257                                   i, 1 << dev->caps.log_num_macs);
 258                 }
 259                 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
 260                         dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
 261                         mlx4_warn(dev, "Requested number of VLANs is too much "
 262                                   "for port %d, reducing to %d.\n",
 263                                   i, 1 << dev->caps.log_num_vlans);
 264                 }
 265         }
 266
 267         mlx4_set_port_mask(dev);
 268
 269         dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
 270
 271         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
 272         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
 273                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
 274                 (1 << dev->caps.log_num_macs) *
 275                 (1 << dev->caps.log_num_vlans) *
 276                 (1 << dev->caps.log_num_prios) *
 277                 dev->caps.num_ports;
 278         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
 279
 280         dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
 281                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
 282                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
 283                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
 284
 285         return 0;
 286 }
 287
 288 /*
 289  * Change the port configuration of the device.
 290  * Every user of this function must hold the port mutex.
 291  */
 292 int mlx4_change_port_types(struct mlx4_dev *dev,
 293                            enum mlx4_port_type *port_types)
 294 {
 295         int err = 0;
 296         int change = 0;
 297         int port;
 298
 299         for (port = 0; port <  dev->caps.num_ports; port++) {
 300                 /* Change the port type only if the new type is different
 301                  * from the current, and not set to Auto */
 302                 if (port_types[port] != dev->caps.port_type[port + 1]) {
 303                         change = 1;
 304                         dev->caps.port_type[port + 1] = port_types[port];
 305                 }
 306         }
 307         if (change) {
 308                 mlx4_unregister_device(dev);
 309                 for (port = 1; port <= dev->caps.num_ports; port++) {
 310                         mlx4_CLOSE_PORT(dev, port);
 311                         err = mlx4_SET_PORT(dev, port);
 312                         if (err) {
 313                                 mlx4_err(dev, "Failed to set port %d, "
 314                                               "aborting\n", port);
 315                                 goto out;
 316                         }
 317                 }
 318                 mlx4_set_port_mask(dev);
 319                 err = mlx4_register_device(dev);
 320         }
 321
 322 out:
 323         return err;
 324 }
 325
 326 static ssize_t show_port_type(struct device *dev,
 327                               struct device_attribute *attr,
 328                               char *buf)
 329 {
 330         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
 331                                                    port_attr);
 332         struct mlx4_dev *mdev = info->dev;
 333         char type[8];
 334
 335         sprintf(type, "%s",
 336                 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
 337                 "ib" : "eth");
 338         if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
 339                 sprintf(buf, "auto (%s)\n", type);
 340         else
 341                 sprintf(buf, "%s\n", type);
 342
 343         return strlen(buf);
 344 }
 345
 346 static ssize_t set_port_type(struct device *dev,
 347                              struct device_attribute *attr,
 348                              const char *buf, size_t count)
 349 {
 350         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
 351                                                    port_attr);
 352         struct mlx4_dev *mdev = info->dev;
 353         struct mlx4_priv *priv = mlx4_priv(mdev);
 354         enum mlx4_port_type types[MLX4_MAX_PORTS];
 355         enum mlx4_port_type new_types[MLX4_MAX_PORTS];
 356         int i;
 357         int err = 0;
 358
 359         if (!strcmp(buf, "ib\n"))
 360                 info->tmp_type = MLX4_PORT_TYPE_IB;
 361         else if (!strcmp(buf, "eth\n"))
 362                 info->tmp_type = MLX4_PORT_TYPE_ETH;
 363         else if (!strcmp(buf, "auto\n"))
 364                 info->tmp_type = MLX4_PORT_TYPE_AUTO;
 365         else {
 366                 mlx4_err(mdev, "%s is not supported port type\n", buf);
 367                 return -EINVAL;
 368         }
 369
 370         mlx4_stop_sense(mdev);
 371         mutex_lock(&priv->port_mutex);
 372         /* Possible type is always the one that was delivered */
 373         mdev->caps.possible_type[info->port] = info->tmp_type;
 374
 375         for (i = 0; i < mdev->caps.num_ports; i++) {
 376                 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
 377                                         mdev->caps.possible_type[i+1];
 378                 if (types[i] == MLX4_PORT_TYPE_AUTO)
 379                         types[i] = mdev->caps.port_type[i+1];
 380         }
 381
 382         if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
 383                 for (i = 1; i <= mdev->caps.num_ports; i++) {
 384                         if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
 385                                 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
 386                                 err = -EINVAL;
 387                         }
 388                 }
 389         }
 390         if (err) {
 391                 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
 392                                "Set only 'eth' or 'ib' for both ports "
 393                                "(should be the same)\n");
 394                 goto out;
 395         }
 396
 397         mlx4_do_sense_ports(mdev, new_types, types);
 398
 399         err = mlx4_check_port_params(mdev, new_types);
 400         if (err)
 401                 goto out;
 402
 403         /* We are about to apply the changes after the configuration
 404          * was verified, no need to remember the temporary types
 405          * any more */
 406         for (i = 0; i < mdev->caps.num_ports; i++)
 407                 priv->port[i + 1].tmp_type = 0;
 408
 409         err = mlx4_change_port_types(mdev, new_types);
 410
 411 out:
 412         mlx4_start_sense(mdev);
 413         mutex_unlock(&priv->port_mutex);
 414         return err ? err : count;
 415 }
 416
 417 static int mlx4_load_fw(struct mlx4_dev *dev)
 418 {
 419         struct mlx4_priv *priv = mlx4_priv(dev);
 420         int err;
 421
 422         priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
 423                                          GFP_HIGHUSER | __GFP_NOWARN, 0);
 424         if (!priv->fw.fw_icm) {
 425                 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
 426                 return -ENOMEM;
 427         }
 428
 429         err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
 430         if (err) {
 431                 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
 432                 goto err_free;
 433         }
 434
 435         err = mlx4_RUN_FW(dev);
 436         if (err) {
 437                 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
 438                 goto err_unmap_fa;
 439         }
 440
 441         return 0;
 442
 443 err_unmap_fa:
 444         mlx4_UNMAP_FA(dev);
 445
 446 err_free:
 447         mlx4_free_icm(dev, priv->fw.fw_icm, 0);
 448         return err;
 449 }
 450
 451 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
 452                                 int cmpt_entry_sz)
 453 {
 454         struct mlx4_priv *priv = mlx4_priv(dev);
 455         int err;
 456
 457         err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
 458                                   cmpt_base +
 459                                   ((u64) (MLX4_CMPT_TYPE_QP *
 460                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
 461                                   cmpt_entry_sz, dev->caps.num_qps,
 462                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
 463                                   0, 0);
 464         if (err)
 465                 goto err;
 466
 467         err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
 468                                   cmpt_base +
 469                                   ((u64) (MLX4_CMPT_TYPE_SRQ *
 470                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
 471                                   cmpt_entry_sz, dev->caps.num_srqs,
 472                                   dev->caps.reserved_srqs, 0, 0);
 473         if (err)
 474                 goto err_qp;
 475
 476         err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
 477                                   cmpt_base +
 478                                   ((u64) (MLX4_CMPT_TYPE_CQ *
 479                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
 480                                   cmpt_entry_sz, dev->caps.num_cqs,
 481                                   dev->caps.reserved_cqs, 0, 0);
 482         if (err)
 483                 goto err_srq;
 484
 485         err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
 486                                   cmpt_base +
 487                                   ((u64) (MLX4_CMPT_TYPE_EQ *
 488                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
 489                                   cmpt_entry_sz,
 490                                   dev->caps.num_eqs, dev->caps.num_eqs, 0, 0);
 491         if (err)
 492                 goto err_cq;
 493
 494         return 0;
 495
 496 err_cq:
 497         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
 498
 499 err_srq:
 500         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
 501
 502 err_qp:
 503         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
 504
 505 err:
 506         return err;
 507 }
 508
 509 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
 510                          struct mlx4_init_hca_param *init_hca, u64 icm_size)
 511 {
 512         struct mlx4_priv *priv = mlx4_priv(dev);
 513         u64 aux_pages;
 514         int err;
 515
 516         err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
 517         if (err) {
 518                 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
 519                 return err;
 520         }
 521
 522         mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
 523                  (unsigned long long) icm_size >> 10,
 524                  (unsigned long long) aux_pages << 2);
 525
 526         priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
 527                                           GFP_HIGHUSER | __GFP_NOWARN, 0);
 528         if (!priv->fw.aux_icm) {
 529                 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
 530                 return -ENOMEM;
 531         }
 532
 533         err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
 534         if (err) {
 535                 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
 536                 goto err_free_aux;
 537         }
 538
 539         err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
 540         if (err) {
 541                 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
 542                 goto err_unmap_aux;
 543         }
 544
 545         err = mlx4_init_icm_table(dev, &priv->eq_table.table,
 546                                   init_hca->eqc_base, dev_cap->eqc_entry_sz,
 547                                   dev->caps.num_eqs, dev->caps.num_eqs,
 548                                   0, 0);
 549         if (err) {
 550                 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
 551                 goto err_unmap_cmpt;
 552         }
 553
 554         /*
 555          * Reserved MTT entries must be aligned up to a cacheline
 556          * boundary, since the FW will write to them, while the driver
 557          * writes to all other MTT entries. (The variable
 558          * dev->caps.mtt_entry_sz below is really the MTT segment
 559          * size, not the raw entry size)
 560          */
 561         dev->caps.reserved_mtts =
 562                 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
 563                       dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
 564
 565         err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
 566                                   init_hca->mtt_base,
 567                                   dev->caps.mtt_entry_sz,
 568                                   dev->caps.num_mtt_segs,
 569                                   dev->caps.reserved_mtts, 1, 0);
 570         if (err) {
 571                 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
 572                 goto err_unmap_eq;
 573         }
 574
 575         err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
 576                                   init_hca->dmpt_base,
 577                                   dev_cap->dmpt_entry_sz,
 578                                   dev->caps.num_mpts,
 579                                   dev->caps.reserved_mrws, 1, 1);
 580         if (err) {
 581                 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
 582                 goto err_unmap_mtt;
 583         }
 584
 585         err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
 586                                   init_hca->qpc_base,
 587                                   dev_cap->qpc_entry_sz,
 588                                   dev->caps.num_qps,
 589                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
 590                                   0, 0);
 591         if (err) {
 592                 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
 593                 goto err_unmap_dmpt;
 594         }
 595
 596         err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
 597                                   init_hca->auxc_base,
 598                                   dev_cap->aux_entry_sz,
 599                                   dev->caps.num_qps,
 600                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
 601                                   0, 0);
 602         if (err) {
 603                 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
 604                 goto err_unmap_qp;
 605         }
 606
 607         err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
 608                                   init_hca->altc_base,
 609                                   dev_cap->altc_entry_sz,
 610                                   dev->caps.num_qps,
 611                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
 612                                   0, 0);
 613         if (err) {
 614                 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
 615                 goto err_unmap_auxc;
 616         }
 617
 618         err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
 619                                   init_hca->rdmarc_base,
 620                                   dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
 621                                   dev->caps.num_qps,
 622                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
 623                                   0, 0);
 624         if (err) {
 625                 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
 626                 goto err_unmap_altc;
 627         }
 628
 629         err = mlx4_init_icm_table(dev, &priv->cq_table.table,
 630                                   init_hca->cqc_base,
 631                                   dev_cap->cqc_entry_sz,
 632                                   dev->caps.num_cqs,
 633                                   dev->caps.reserved_cqs, 0, 0);
 634         if (err) {
 635                 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
 636                 goto err_unmap_rdmarc;
 637         }
 638
 639         err = mlx4_init_icm_table(dev, &priv->srq_table.table,
 640                                   init_hca->srqc_base,
 641                                   dev_cap->srq_entry_sz,
 642                                   dev->caps.num_srqs,
 643                                   dev->caps.reserved_srqs, 0, 0);
 644         if (err) {
 645                 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
 646                 goto err_unmap_cq;
 647         }
 648
 649         /*
 650          * It's not strictly required, but for simplicity just map the
 651          * whole multicast group table now.  The table isn't very big
 652          * and it's a lot easier than trying to track ref counts.
 653          */
 654         err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
 655                                   init_hca->mc_base, MLX4_MGM_ENTRY_SIZE,
 656                                   dev->caps.num_mgms + dev->caps.num_amgms,
 657                                   dev->caps.num_mgms + dev->caps.num_amgms,
 658                                   0, 0);
 659         if (err) {
 660                 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
 661                 goto err_unmap_srq;
 662         }
 663
 664         return 0;
 665
 666 err_unmap_srq:
 667         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
 668
 669 err_unmap_cq:
 670         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
 671
 672 err_unmap_rdmarc:
 673         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
 674
 675 err_unmap_altc:
 676         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
 677
 678 err_unmap_auxc:
 679         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
 680
 681 err_unmap_qp:
 682         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
 683
 684 err_unmap_dmpt:
 685         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
 686
 687 err_unmap_mtt:
 688         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
 689
 690 err_unmap_eq:
 691         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
 692
 693 err_unmap_cmpt:
 694         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
 695         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
 696         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
 697         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
 698
 699 err_unmap_aux:
 700         mlx4_UNMAP_ICM_AUX(dev);
 701
 702 err_free_aux:
 703         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
 704
 705         return err;
 706 }
 707
 708 static void mlx4_free_icms(struct mlx4_dev *dev)
 709 {
 710         struct mlx4_priv *priv = mlx4_priv(dev);
 711
 712         mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
 713         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
 714         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
 715         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
 716         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
 717         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
 718         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
 719         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
 720         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
 721         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
 722         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
 723         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
 724         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
 725         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
 726
 727         mlx4_UNMAP_ICM_AUX(dev);
 728         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
 729 }
 730
 731 static int map_bf_area(struct mlx4_dev *dev)
 732 {
 733         struct mlx4_priv *priv = mlx4_priv(dev);
 734         resource_size_t bf_start;
 735         resource_size_t bf_len;
 736         int err = 0;
 737
 738         bf_start = pci_resource_start(dev->pdev, 2) + (dev->caps.num_uars << PAGE_SHIFT);
 739         bf_len = pci_resource_len(dev->pdev, 2) - (dev->caps.num_uars << PAGE_SHIFT);
 740         priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
 741         if (!priv->bf_mapping)
 742                 err = -ENOMEM;
 743
 744         return err;
 745 }
 746
 747 static void unmap_bf_area(struct mlx4_dev *dev)
 748 {
 749         if (mlx4_priv(dev)->bf_mapping)
 750                 io_mapping_free(mlx4_priv(dev)->bf_mapping);
 751 }
 752
 753 static void mlx4_close_hca(struct mlx4_dev *dev)
 754 {
 755         unmap_bf_area(dev);
 756         mlx4_CLOSE_HCA(dev, 0);
 757         mlx4_free_icms(dev);
 758         mlx4_UNMAP_FA(dev);
 759         mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
 760 }
 761
 762 static int mlx4_init_hca(struct mlx4_dev *dev)
 763 {
 764         struct mlx4_priv          *priv = mlx4_priv(dev);
 765         struct mlx4_adapter        adapter;
 766         struct mlx4_dev_cap        dev_cap;
 767         struct mlx4_mod_stat_cfg   mlx4_cfg;
 768         struct mlx4_profile        profile;
 769         struct mlx4_init_hca_param init_hca;
 770         u64 icm_size;
 771         int err;
 772
 773         err = mlx4_QUERY_FW(dev);
 774         if (err) {
 775                 if (err == -EACCES)
 776                         mlx4_info(dev, "non-primary physical function, skipping.\n");
 777                 else
 778                         mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
 779                 return err;
 780         }
 781
 782         err = mlx4_load_fw(dev);
 783         if (err) {
 784                 mlx4_err(dev, "Failed to start FW, aborting.\n");
 785                 return err;
 786         }
 787
 788         mlx4_cfg.log_pg_sz_m = 1;
 789         mlx4_cfg.log_pg_sz = 0;
 790         err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
 791         if (err)
 792                 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
 793
 794         err = mlx4_dev_cap(dev, &dev_cap);
 795         if (err) {
 796                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
 797                 goto err_stop_fw;
 798         }
 799
 800         profile = default_profile;
 801
 802         icm_size = mlx4_make_profile(dev, &profile, &dev_cap, &init_hca);
 803         if ((long long) icm_size < 0) {
 804                 err = icm_size;
 805                 goto err_stop_fw;
 806         }
 807
 808         if (map_bf_area(dev))
 809                 mlx4_dbg(dev, "Failed to map blue flame area\n");
 810
 811         init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
 812
 813         err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
 814         if (err)
 815                 goto err_stop_fw;
 816
 817         err = mlx4_INIT_HCA(dev, &init_hca);
 818         if (err) {
 819                 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
 820                 goto err_free_icm;
 821         }
 822
 823         err = mlx4_QUERY_ADAPTER(dev, &adapter);
 824         if (err) {
 825                 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
 826                 goto err_close;
 827         }
 828
 829         priv->eq_table.inta_pin = adapter.inta_pin;
 830         memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
 831
 832         return 0;
 833
 834 err_close:
 835         mlx4_CLOSE_HCA(dev, 0);
 836
 837 err_free_icm:
 838         mlx4_free_icms(dev);
 839
 840 err_stop_fw:
 841         unmap_bf_area(dev);
 842         mlx4_UNMAP_FA(dev);
 843         mlx4_free_icm(dev, priv->fw.fw_icm, 0);
 844
 845         return err;
 846 }
 847
 848 static int mlx4_init_counters_table(struct mlx4_dev *dev)
 849 {
 850         struct mlx4_priv *priv = mlx4_priv(dev);
 851         int nent;
 852
 853         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
 854                 return -ENOENT;
 855
 856         nent = dev->caps.max_counters;
 857         return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
 858 }
 859
 860 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
 861 {
 862         mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
 863 }
 864
 865 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
 866 {
 867         struct mlx4_priv *priv = mlx4_priv(dev);
 868
 869         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
 870                 return -ENOENT;
 871
 872         *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
 873         if (*idx == -1)
 874                 return -ENOMEM;
 875
 876         return 0;
 877 }
 878 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
 879
 880 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
 881 {
 882         mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx);
 883         return;
 884 }
 885 EXPORT_SYMBOL_GPL(mlx4_counter_free);
 886
 887 static int mlx4_setup_hca(struct mlx4_dev *dev)
 888 {
 889         struct mlx4_priv *priv = mlx4_priv(dev);
 890         int err;
 891         int port;
 892         __be32 ib_port_default_caps;
 893
 894         err = mlx4_init_uar_table(dev);
 895         if (err) {
 896                 mlx4_err(dev, "Failed to initialize "
 897                          "user access region table, aborting.\n");
 898                 return err;
 899         }
 900
 901         err = mlx4_uar_alloc(dev, &priv->driver_uar);
 902         if (err) {
 903                 mlx4_err(dev, "Failed to allocate driver access region, "
 904                          "aborting.\n");
 905                 goto err_uar_table_free;
 906         }
 907
 908         priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
 909         if (!priv->kar) {
 910                 mlx4_err(dev, "Couldn't map kernel access region, "
 911                          "aborting.\n");
 912                 err = -ENOMEM;
 913                 goto err_uar_free;
 914         }
 915
 916         err = mlx4_init_pd_table(dev);
 917         if (err) {
 918                 mlx4_err(dev, "Failed to initialize "
 919                          "protection domain table, aborting.\n");
 920                 goto err_kar_unmap;
 921         }
 922
 923         err = mlx4_init_xrcd_table(dev);
 924         if (err) {
 925                 mlx4_err(dev, "Failed to initialize "
 926                          "reliable connection domain table, aborting.\n");
 927                 goto err_pd_table_free;
 928         }
 929
 930         err = mlx4_init_mr_table(dev);
 931         if (err) {
 932                 mlx4_err(dev, "Failed to initialize "
 933                          "memory region table, aborting.\n");
 934                 goto err_xrcd_table_free;
 935         }
 936
 937         err = mlx4_init_eq_table(dev);
 938         if (err) {
 939                 mlx4_err(dev, "Failed to initialize "
 940                          "event queue table, aborting.\n");
 941                 goto err_mr_table_free;
 942         }
 943
 944         err = mlx4_cmd_use_events(dev);
 945         if (err) {
 946                 mlx4_err(dev, "Failed to switch to event-driven "
 947                          "firmware commands, aborting.\n");
 948                 goto err_eq_table_free;
 949         }
 950
 951         err = mlx4_NOP(dev);
 952         if (err) {
 953                 if (dev->flags & MLX4_FLAG_MSI_X) {
 954                         mlx4_warn(dev, "NOP command failed to generate MSI-X "
 955                                   "interrupt IRQ %d).\n",
 956                                   priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
 957                         mlx4_warn(dev, "Trying again without MSI-X.\n");
 958                 } else {
 959                         mlx4_err(dev, "NOP command failed to generate interrupt "
 960                                  "(IRQ %d), aborting.\n",
 961                                  priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
 962                         mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
 963                 }
 964
 965                 goto err_cmd_poll;
 966         }
 967
 968         mlx4_dbg(dev, "NOP command IRQ test passed\n");
 969
 970         err = mlx4_init_cq_table(dev);
 971         if (err) {
 972                 mlx4_err(dev, "Failed to initialize "
 973                          "completion queue table, aborting.\n");
 974                 goto err_cmd_poll;
 975         }
 976
 977         err = mlx4_init_srq_table(dev);
 978         if (err) {
 979                 mlx4_err(dev, "Failed to initialize "
 980                          "shared receive queue table, aborting.\n");
 981                 goto err_cq_table_free;
 982         }
 983
 984         err = mlx4_init_qp_table(dev);
 985         if (err) {
 986                 mlx4_err(dev, "Failed to initialize "
 987                          "queue pair table, aborting.\n");
 988                 goto err_srq_table_free;
 989         }
 990
 991         err = mlx4_init_mcg_table(dev);
 992         if (err) {
 993                 mlx4_err(dev, "Failed to initialize "
 994                          "multicast group table, aborting.\n");
 995                 goto err_qp_table_free;
 996         }
 997
 998         err = mlx4_init_counters_table(dev);
 999         if (err && err != -ENOENT) {
1000                 mlx4_err(dev, "Failed to initialize counters table, aborting.\n");
1001                 goto err_counters_table_free;
1002         }
1003
1004         for (port = 1; port <= dev->caps.num_ports; port++) {
1005                 enum mlx4_port_type port_type = 0;
1006                 mlx4_SENSE_PORT(dev, port, &port_type);
1007                 if (port_type)
1008                         dev->caps.port_type[port] = port_type;
1009                 ib_port_default_caps = 0;
1010                 err = mlx4_get_port_ib_caps(dev, port, &ib_port_default_caps);
1011                 if (err)
1012                         mlx4_warn(dev, "failed to get port %d default "
1013                                   "ib capabilities (%d). Continuing with "
1014                                   "caps = 0\n", port, err);
1015                 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1016
1017                 err = mlx4_check_ext_port_caps(dev, port);
1018                 if (err)
1019                         mlx4_warn(dev, "failed to get port %d extended "
1020                                   "port capabilities support info (%d)."
1021                                   " Assuming not supported\n", port, err);
1022
1023                 err = mlx4_SET_PORT(dev, port);
1024                 if (err) {
1025                         mlx4_err(dev, "Failed to set port %d, aborting\n",
1026                                 port);
1027                         goto err_mcg_table_free;
1028                 }
1029         }
1030         mlx4_set_port_mask(dev);
1031
1032         return 0;
1033
1034 err_mcg_table_free:
1035         mlx4_cleanup_mcg_table(dev);
1036
1037 err_counters_table_free:
1038         mlx4_cleanup_counters_table(dev);
1039
1040 err_qp_table_free:
1041         mlx4_cleanup_qp_table(dev);
1042
1043 err_srq_table_free:
1044         mlx4_cleanup_srq_table(dev);
1045
1046 err_cq_table_free:
1047         mlx4_cleanup_cq_table(dev);
1048
1049 err_cmd_poll:
1050         mlx4_cmd_use_polling(dev);
1051
1052 err_eq_table_free:
1053         mlx4_cleanup_eq_table(dev);
1054
1055 err_mr_table_free:
1056         mlx4_cleanup_mr_table(dev);
1057
1058 err_xrcd_table_free:
1059         mlx4_cleanup_xrcd_table(dev);
1060
1061 err_pd_table_free:
1062         mlx4_cleanup_pd_table(dev);
1063
1064 err_kar_unmap:
1065         iounmap(priv->kar);
1066
1067 err_uar_free:
1068         mlx4_uar_free(dev, &priv->driver_uar);
1069
1070 err_uar_table_free:
1071         mlx4_cleanup_uar_table(dev);
1072         return err;
1073 }
1074
1075 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
1076 {
1077         struct mlx4_priv *priv = mlx4_priv(dev);
1078         struct msix_entry *entries;
1079         int nreq = min_t(int, dev->caps.num_ports *
1080                          min_t(int, num_online_cpus() + 1, MAX_MSIX_P_PORT)
1081                                 + MSIX_LEGACY_SZ, MAX_MSIX);
1082         int err;
1083         int i;
1084
1085         if (msi_x) {
1086                 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
1087                              nreq);
1088                 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
1089                 if (!entries)
1090                         goto no_msi;
1091
1092                 for (i = 0; i < nreq; ++i)
1093                         entries[i].entry = i;
1094
1095         retry:
1096                 err = pci_enable_msix(dev->pdev, entries, nreq);
1097                 if (err) {
1098                         /* Try again if at least 2 vectors are available */
1099                         if (err > 1) {
1100                                 mlx4_info(dev, "Requested %d vectors, "
1101                                           "but only %d MSI-X vectors available, "
1102                                           "trying again\n", nreq, err);
1103                                 nreq = err;
1104                                 goto retry;
1105                         }
1106                         kfree(entries);
1107                         goto no_msi;
1108                 }
1109
1110                 if (nreq <
1111                     MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) {
1112                         /*Working in legacy mode , all EQ's shared*/
1113                         dev->caps.comp_pool           = 0;
1114                         dev->caps.num_comp_vectors = nreq - 1;
1115                 } else {
1116                         dev->caps.comp_pool           = nreq - MSIX_LEGACY_SZ;
1117                         dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
1118                 }
1119                 for (i = 0; i < nreq; ++i)
1120                         priv->eq_table.eq[i].irq = entries[i].vector;
1121
1122                 dev->flags |= MLX4_FLAG_MSI_X;
1123
1124                 kfree(entries);
1125                 return;
1126         }
1127
1128 no_msi:
1129         dev->caps.num_comp_vectors = 1;
1130         dev->caps.comp_pool        = 0;
1131
1132         for (i = 0; i < 2; ++i)
1133                 priv->eq_table.eq[i].irq = dev->pdev->irq;
1134 }
1135
1136 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
1137 {
1138         struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
1139         int err = 0;
1140
1141         info->dev = dev;
1142         info->port = port;
1143         mlx4_init_mac_table(dev, &info->mac_table);
1144         mlx4_init_vlan_table(dev, &info->vlan_table);
1145         info->base_qpn = dev->caps.reserved_qps_base[MLX4_QP_REGION_ETH_ADDR] +
1146                         (port - 1) * (1 << log_num_mac);
1147
1148         sprintf(info->dev_name, "mlx4_port%d", port);
1149         info->port_attr.attr.name = info->dev_name;
1150         info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
1151         info->port_attr.show      = show_port_type;
1152         info->port_attr.store     = set_port_type;
1153         sysfs_attr_init(&info->port_attr.attr);
1154
1155         err = device_create_file(&dev->pdev->dev, &info->port_attr);
1156         if (err) {
1157                 mlx4_err(dev, "Failed to create file for port %d\n", port);
1158                 info->port = -1;
1159         }
1160
1161         return err;
1162 }
1163
1164 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
1165 {
1166         if (info->port < 0)
1167                 return;
1168
1169         device_remove_file(&info->dev->pdev->dev, &info->port_attr);
1170 }
1171
1172 static int mlx4_init_steering(struct mlx4_dev *dev)
1173 {
1174         struct mlx4_priv *priv = mlx4_priv(dev);
1175         int num_entries = dev->caps.num_ports;
1176         int i, j;
1177
1178         priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
1179         if (!priv->steer)
1180                 return -ENOMEM;
1181
1182         for (i = 0; i < num_entries; i++) {
1183                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1184                         INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
1185                         INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
1186                 }
1187                 INIT_LIST_HEAD(&priv->steer[i].high_prios);
1188         }
1189         return 0;
1190 }
1191
1192 static void mlx4_clear_steering(struct mlx4_dev *dev)
1193 {
1194         struct mlx4_priv *priv = mlx4_priv(dev);
1195         struct mlx4_steer_index *entry, *tmp_entry;
1196         struct mlx4_promisc_qp *pqp, *tmp_pqp;
1197         int num_entries = dev->caps.num_ports;
1198         int i, j;
1199
1200         for (i = 0; i < num_entries; i++) {
1201                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1202                         list_for_each_entry_safe(pqp, tmp_pqp,
1203                                                  &priv->steer[i].promisc_qps[j],
1204                                                  list) {
1205                                 list_del(&pqp->list);
1206                                 kfree(pqp);
1207                         }
1208                         list_for_each_entry_safe(entry, tmp_entry,
1209                                                  &priv->steer[i].steer_entries[j],
1210                                                  list) {
1211                                 list_del(&entry->list);
1212                                 list_for_each_entry_safe(pqp, tmp_pqp,
1213                                                          &entry->duplicates,
1214                                                          list) {
1215                                         list_del(&pqp->list);
1216                                         kfree(pqp);
1217                                 }
1218                                 kfree(entry);
1219                         }
1220                 }
1221         }
1222         kfree(priv->steer);
1223 }
1224
1225 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data)
1226 {
1227         struct mlx4_priv *priv;
1228         struct mlx4_dev *dev;
1229         int err;
1230         int port;
1231
1232         pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
1233
1234         err = pci_enable_device(pdev);
1235         if (err) {
1236                 dev_err(&pdev->dev, "Cannot enable PCI device, "
1237                         "aborting.\n");
1238                 return err;
1239         }
1240
1241         /*
1242          * Check for BARs.  We expect 0: 1MB
1243          */
1244         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
1245             pci_resource_len(pdev, 0) != 1 << 20) {
1246                 dev_err(&pdev->dev, "Missing DCS, aborting.\n");
1247                 err = -ENODEV;
1248                 goto err_disable_pdev;
1249         }
1250         if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
1251                 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
1252                 err = -ENODEV;
1253                 goto err_disable_pdev;
1254         }
1255
1256         err = pci_request_regions(pdev, DRV_NAME);
1257         if (err) {
1258                 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
1259                 goto err_disable_pdev;
1260         }
1261
1262         pci_set_master(pdev);
1263
1264         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1265         if (err) {
1266                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
1267                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1268                 if (err) {
1269                         dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
1270                         goto err_release_regions;
1271                 }
1272         }
1273         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1274         if (err) {
1275                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
1276                          "consistent PCI DMA mask.\n");
1277                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1278                 if (err) {
1279                         dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
1280                                 "aborting.\n");
1281                         goto err_release_regions;
1282                 }
1283         }
1284
1285         /* Allow large DMA segments, up to the firmware limit of 1 GB */
1286         dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
1287
1288         dev       = pci_get_drvdata(pdev);
1289         priv      = mlx4_priv(dev);
1290         dev->pdev = pdev;
1291         INIT_LIST_HEAD(&priv->ctx_list);
1292         spin_lock_init(&priv->ctx_lock);
1293
1294         mutex_init(&priv->port_mutex);
1295
1296         INIT_LIST_HEAD(&priv->pgdir_list);
1297         mutex_init(&priv->pgdir_mutex);
1298
1299         INIT_LIST_HEAD(&priv->bf_list);
1300         mutex_init(&priv->bf_mutex);
1301
1302         dev->rev_id = pdev->revision;
1303
1304         /*
1305          * Now reset the HCA before we touch the PCI capabilities or
1306          * attempt a firmware command, since a boot ROM may have left
1307          * the HCA in an undefined state.
1308          */
1309         err = mlx4_reset(dev);
1310         if (err) {
1311                 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
1312                 goto err_free_dev;
1313         }
1314
1315         if (mlx4_cmd_init(dev)) {
1316                 mlx4_err(dev, "Failed to init command interface, aborting.\n");
1317                 goto err_free_dev;
1318         }
1319
1320         err = mlx4_init_hca(dev);
1321         if (err)
1322                 goto err_cmd;
1323
1324         err = mlx4_alloc_eq_table(dev);
1325         if (err)
1326                 goto err_close;
1327
1328         priv->msix_ctl.pool_bm = 0;
1329         spin_lock_init(&priv->msix_ctl.pool_lock);
1330
1331         mlx4_enable_msi_x(dev);
1332
1333         err = mlx4_init_steering(dev);
1334         if (err)
1335                 goto err_free_eq;
1336
1337         err = mlx4_setup_hca(dev);
1338         if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X)) {
1339                 dev->flags &= ~MLX4_FLAG_MSI_X;
1340                 pci_disable_msix(pdev);
1341                 err = mlx4_setup_hca(dev);
1342         }
1343
1344         if (err)
1345                 goto err_steer;
1346
1347         for (port = 1; port <= dev->caps.num_ports; port++) {
1348                 err = mlx4_init_port_info(dev, port);
1349                 if (err)
1350                         goto err_port;
1351         }
1352
1353         err = mlx4_register_device(dev);
1354         if (err)
1355                 goto err_port;
1356
1357         mlx4_sense_init(dev);
1358         mlx4_start_sense(dev);
1359
1360         priv->removed = 0;
1361
1362         return 0;
1363
1364 err_port:
1365         for (--port; port >= 1; --port)
1366                 mlx4_cleanup_port_info(&priv->port[port]);
1367
1368         mlx4_cleanup_counters_table(dev);
1369         mlx4_cleanup_mcg_table(dev);
1370         mlx4_cleanup_qp_table(dev);
1371         mlx4_cleanup_srq_table(dev);
1372         mlx4_cleanup_cq_table(dev);
1373         mlx4_cmd_use_polling(dev);
1374         mlx4_cleanup_eq_table(dev);
1375         mlx4_cleanup_mr_table(dev);
1376         mlx4_cleanup_xrcd_table(dev);
1377         mlx4_cleanup_pd_table(dev);
1378         mlx4_cleanup_uar_table(dev);
1379
1380 err_steer:
1381         mlx4_clear_steering(dev);
1382
1383 err_free_eq:
1384         mlx4_free_eq_table(dev);
1385
1386 err_close:
1387         if (dev->flags & MLX4_FLAG_MSI_X)
1388                 pci_disable_msix(pdev);
1389
1390         mlx4_close_hca(dev);
1391
1392 err_cmd:
1393         mlx4_cmd_cleanup(dev);
1394
1395 err_free_dev:
1396         kfree(priv);
1397
1398 err_release_regions:
1399         pci_release_regions(pdev);
1400
1401 err_disable_pdev:
1402         pci_disable_device(pdev);
1403         pci_set_drvdata(pdev, NULL);
1404         return err;
1405 }
1406
1407 static int __devinit mlx4_init_one(struct pci_dev *pdev,
1408                                    const struct pci_device_id *id)
1409 {
1410         struct mlx4_priv *priv;
1411         struct mlx4_dev *dev;
1412
1413         printk_once(KERN_INFO "%s", mlx4_version);
1414
1415         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1416         if (!priv)
1417                 return -ENOMEM;
1418
1419         dev       = &priv->dev;
1420         pci_set_drvdata(pdev, dev);
1421         priv->pci_dev_data = id->driver_data;
1422
1423         return __mlx4_init_one(pdev, id->driver_data);
1424 }
1425
1426 static void __mlx4_remove_one(struct pci_dev *pdev)
1427 {
1428         struct mlx4_dev  *dev  = pci_get_drvdata(pdev);
1429         struct mlx4_priv *priv = mlx4_priv(dev);
1430         int               pci_dev_data;
1431         int p;
1432
1433         if (priv->removed)
1434                 return;
1435
1436         pci_dev_data = priv->pci_dev_data;
1437
1438         mlx4_stop_sense(dev);
1439         mlx4_unregister_device(dev);
1440
1441         for (p = 1; p <= dev->caps.num_ports; p++) {
1442                 mlx4_cleanup_port_info(&priv->port[p]);
1443                 mlx4_CLOSE_PORT(dev, p);
1444         }
1445
1446         mlx4_cleanup_counters_table(dev);
1447         mlx4_cleanup_mcg_table(dev);
1448         mlx4_cleanup_qp_table(dev);
1449         mlx4_cleanup_srq_table(dev);
1450         mlx4_cleanup_cq_table(dev);
1451         mlx4_cmd_use_polling(dev);
1452         mlx4_cleanup_eq_table(dev);
1453         mlx4_cleanup_mr_table(dev);
1454         mlx4_cleanup_xrcd_table(dev);
1455         mlx4_cleanup_pd_table(dev);
1456
1457         iounmap(priv->kar);
1458         mlx4_uar_free(dev, &priv->driver_uar);
1459         mlx4_cleanup_uar_table(dev);
1460         mlx4_clear_steering(dev);
1461         mlx4_free_eq_table(dev);
1462         mlx4_close_hca(dev);
1463         mlx4_cmd_cleanup(dev);
1464
1465         if (dev->flags & MLX4_FLAG_MSI_X)
1466                 pci_disable_msix(pdev);
1467
1468         pci_release_regions(pdev);
1469         pci_disable_device(pdev);
1470         memset(priv, 0, sizeof(*priv));
1471         priv->pci_dev_data = pci_dev_data;
1472         priv->removed = 1;
1473 }
1474
1475 static void mlx4_remove_one(struct pci_dev *pdev)
1476 {
1477         struct mlx4_dev  *dev  = pci_get_drvdata(pdev);
1478         struct mlx4_priv *priv = mlx4_priv(dev);
1479
1480         __mlx4_remove_one(pdev);
1481         kfree(priv);
1482         pci_set_drvdata(pdev, NULL);
1483 }
1484
1485 int mlx4_restart_one(struct pci_dev *pdev)
1486 {
1487         struct mlx4_dev  *dev  = pci_get_drvdata(pdev);
1488         struct mlx4_priv *priv = mlx4_priv(dev);
1489         int               pci_dev_data;
1490
1491         pci_dev_data = priv->pci_dev_data;
1492         __mlx4_remove_one(pdev);
1493         return __mlx4_init_one(pdev, pci_dev_data);
1494 }
1495
1496 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
1497         { PCI_VDEVICE(MELLANOX, 0x6340) }, /* MT25408 "Hermon" SDR */
1498         { PCI_VDEVICE(MELLANOX, 0x634a) }, /* MT25408 "Hermon" DDR */
1499         { PCI_VDEVICE(MELLANOX, 0x6354) }, /* MT25408 "Hermon" QDR */
1500         { PCI_VDEVICE(MELLANOX, 0x6732) }, /* MT25408 "Hermon" DDR PCIe gen2 */
1501         { PCI_VDEVICE(MELLANOX, 0x673c) }, /* MT25408 "Hermon" QDR PCIe gen2 */
1502         { PCI_VDEVICE(MELLANOX, 0x6368) }, /* MT25408 "Hermon" EN 10GigE */
1503         { PCI_VDEVICE(MELLANOX, 0x6750) }, /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
1504         { PCI_VDEVICE(MELLANOX, 0x6372) }, /* MT25458 ConnectX EN 10GBASE-T 10GigE */
1505         { PCI_VDEVICE(MELLANOX, 0x675a) }, /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
1506         { PCI_VDEVICE(MELLANOX, 0x6764) }, /* MT26468 ConnectX EN 10GigE PCIe gen2*/
1507         { PCI_VDEVICE(MELLANOX, 0x6746) }, /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
1508         { PCI_VDEVICE(MELLANOX, 0x676e) }, /* MT26478 ConnectX2 40GigE PCIe gen2 */
1509         { PCI_VDEVICE(MELLANOX, 0x1002) }, /* MT25400 Family [ConnectX-2 Virtual Function] */
1510         { PCI_VDEVICE(MELLANOX, 0x1003) }, /* MT27500 Family [ConnectX-3] */
1511         { PCI_VDEVICE(MELLANOX, 0x1004) }, /* MT27500 Family [ConnectX-3 Virtual Function] */
1512         { PCI_VDEVICE(MELLANOX, 0x1005) }, /* MT27510 Family */
1513         { PCI_VDEVICE(MELLANOX, 0x1006) }, /* MT27511 Family */
1514         { PCI_VDEVICE(MELLANOX, 0x1007) }, /* MT27520 Family */
1515         { PCI_VDEVICE(MELLANOX, 0x1008) }, /* MT27521 Family */
1516         { PCI_VDEVICE(MELLANOX, 0x1009) }, /* MT27530 Family */
1517         { PCI_VDEVICE(MELLANOX, 0x100a) }, /* MT27531 Family */
1518         { PCI_VDEVICE(MELLANOX, 0x100b) }, /* MT27540 Family */
1519         { PCI_VDEVICE(MELLANOX, 0x100c) }, /* MT27541 Family */
1520         { PCI_VDEVICE(MELLANOX, 0x100d) }, /* MT27550 Family */
1521         { PCI_VDEVICE(MELLANOX, 0x100e) }, /* MT27551 Family */
1522         { PCI_VDEVICE(MELLANOX, 0x100f) }, /* MT27560 Family */
1523         { PCI_VDEVICE(MELLANOX, 0x1010) }, /* MT27561 Family */
1524         { 0, }
1525 };
1526
1527 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
1528
1529 static struct pci_driver mlx4_driver = {
1530         .name           = DRV_NAME,
1531         .id_table       = mlx4_pci_table,
1532         .probe          = mlx4_init_one,
1533         .remove         = __devexit_p(mlx4_remove_one)
1534 };
1535
1536 static int __init mlx4_verify_params(void)
1537 {
1538         if ((log_num_mac < 0) || (log_num_mac > 7)) {
1539                 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
1540                 return -1;
1541         }
1542
1543         if (log_num_vlan != 0)
1544                 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
1545                            MLX4_LOG_NUM_VLANS);
1546
1547         if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
1548                 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
1549                 return -1;
1550         }
1551
1552         return 0;
1553 }
1554
1555 static int __init mlx4_init(void)
1556 {
1557         int ret;
1558
1559         if (mlx4_verify_params())
1560                 return -EINVAL;
1561
1562         mlx4_catas_init();
1563
1564         mlx4_wq = create_singlethread_workqueue("mlx4");
1565         if (!mlx4_wq)
1566                 return -ENOMEM;
1567
1568         ret = pci_register_driver(&mlx4_driver);
1569         return ret < 0 ? ret : 0;
1570 }
1571
1572 static void __exit mlx4_cleanup(void)
1573 {
1574         pci_unregister_driver(&mlx4_driver);
1575         destroy_workqueue(mlx4_wq);
1576 }
1577
1578 module_init(mlx4_init);
1579 module_exit(mlx4_cleanup);