2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/errno.h>
39 #include <linux/pci.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/slab.h>
42 #include <linux/io-mapping.h>
43 #include <linux/delay.h>
44 #include <linux/netdevice.h>
46 #include <linux/mlx4/device.h>
47 #include <linux/mlx4/doorbell.h>
53 MODULE_AUTHOR("Roland Dreier");
54 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55 MODULE_LICENSE("Dual BSD/GPL");
56 MODULE_VERSION(DRV_VERSION);
58 struct workqueue_struct *mlx4_wq;
60 #ifdef CONFIG_MLX4_DEBUG
62 int mlx4_debug_level = 0;
63 module_param_named(debug_level, mlx4_debug_level, int, 0644);
64 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
66 #endif /* CONFIG_MLX4_DEBUG */
71 module_param(msi_x, int, 0444);
72 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
74 #else /* CONFIG_PCI_MSI */
78 #endif /* CONFIG_PCI_MSI */
81 module_param(num_vfs, int, 0444);
82 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0");
85 module_param(probe_vf, int, 0644);
86 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)");
88 int mlx4_log_num_mgm_entry_size = 10;
89 module_param_named(log_num_mgm_entry_size,
90 mlx4_log_num_mgm_entry_size, int, 0444);
91 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
92 " of qp per mcg, for example:"
93 " 10 gives 248.range: 9<="
94 " log_num_mgm_entry_size <= 12."
95 " Not in use with device managed"
98 static bool enable_64b_cqe_eqe;
99 module_param(enable_64b_cqe_eqe, bool, 0444);
100 MODULE_PARM_DESC(enable_64b_cqe_eqe,
101 "Enable 64 byte CQEs/EQEs when the the FW supports this");
103 #define HCA_GLOBAL_CAP_MASK 0
105 #define PF_CONTEXT_BEHAVIOUR_MASK MLX4_FUNC_CAP_64B_EQE_CQE
107 static char mlx4_version[] =
108 DRV_NAME ": Mellanox ConnectX core driver v"
109 DRV_VERSION " (" DRV_RELDATE ")\n";
111 static struct mlx4_profile default_profile = {
114 .rdmarc_per_qp = 1 << 4,
118 .num_mtt = 1 << 20, /* It is really num mtt segements */
121 static int log_num_mac = 7;
122 module_param_named(log_num_mac, log_num_mac, int, 0444);
123 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
125 static int log_num_vlan;
126 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
127 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
128 /* Log2 max number of VLANs per ETH port (0-7) */
129 #define MLX4_LOG_NUM_VLANS 7
131 static bool use_prio;
132 module_param_named(use_prio, use_prio, bool, 0444);
133 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
136 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
137 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
138 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
140 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
141 static int arr_argc = 2;
142 module_param_array(port_type_array, int, &arr_argc, 0444);
143 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
144 "1 for IB, 2 for Ethernet");
146 struct mlx4_port_config {
147 struct list_head list;
148 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
149 struct pci_dev *pdev;
152 int mlx4_check_port_params(struct mlx4_dev *dev,
153 enum mlx4_port_type *port_type)
157 for (i = 0; i < dev->caps.num_ports - 1; i++) {
158 if (port_type[i] != port_type[i + 1]) {
159 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
160 mlx4_err(dev, "Only same port types supported "
161 "on this HCA, aborting.\n");
167 for (i = 0; i < dev->caps.num_ports; i++) {
168 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
169 mlx4_err(dev, "Requested port type for port %d is not "
170 "supported on this HCA\n", i + 1);
177 static void mlx4_set_port_mask(struct mlx4_dev *dev)
181 for (i = 1; i <= dev->caps.num_ports; ++i)
182 dev->caps.port_mask[i] = dev->caps.port_type[i];
185 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
190 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
192 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
196 if (dev_cap->min_page_sz > PAGE_SIZE) {
197 mlx4_err(dev, "HCA minimum page size of %d bigger than "
198 "kernel PAGE_SIZE of %ld, aborting.\n",
199 dev_cap->min_page_sz, PAGE_SIZE);
202 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
203 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
205 dev_cap->num_ports, MLX4_MAX_PORTS);
209 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
210 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
211 "PCI resource 2 size of 0x%llx, aborting.\n",
213 (unsigned long long) pci_resource_len(dev->pdev, 2));
217 dev->caps.num_ports = dev_cap->num_ports;
218 dev->phys_caps.num_phys_eqs = MLX4_MAX_EQ_NUM;
219 for (i = 1; i <= dev->caps.num_ports; ++i) {
220 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
221 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
222 dev->phys_caps.gid_phys_table_len[i] = dev_cap->max_gids[i];
223 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i];
224 /* set gid and pkey table operating lengths by default
225 * to non-sriov values */
226 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
227 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
228 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
229 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
230 dev->caps.def_mac[i] = dev_cap->def_mac[i];
231 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
232 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
233 dev->caps.default_sense[i] = dev_cap->default_sense[i];
234 dev->caps.trans_type[i] = dev_cap->trans_type[i];
235 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
236 dev->caps.wavelength[i] = dev_cap->wavelength[i];
237 dev->caps.trans_code[i] = dev_cap->trans_code[i];
240 dev->caps.uar_page_size = PAGE_SIZE;
241 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
242 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
243 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
244 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
245 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
246 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
247 dev->caps.max_wqes = dev_cap->max_qp_sz;
248 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
249 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
250 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
251 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
252 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
253 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
255 * Subtract 1 from the limit because we need to allocate a
256 * spare CQE so the HCA HW can tell the difference between an
257 * empty CQ and a full CQ.
259 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
260 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
261 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
262 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
263 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
265 /* The first 128 UARs are used for EQ doorbells */
266 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
267 dev->caps.reserved_pds = dev_cap->reserved_pds;
268 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
269 dev_cap->reserved_xrcds : 0;
270 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
271 dev_cap->max_xrcds : 0;
272 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
274 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
275 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
276 dev->caps.flags = dev_cap->flags;
277 dev->caps.flags2 = dev_cap->flags2;
278 dev->caps.bmme_flags = dev_cap->bmme_flags;
279 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
280 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
281 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
282 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
284 if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) {
285 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
286 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
287 dev->caps.fs_log_max_ucast_qp_range_size =
288 dev_cap->fs_log_max_ucast_qp_range_size;
290 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
291 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) {
292 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
294 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
296 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
297 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
298 mlx4_warn(dev, "Must have UC_STEER and MC_STEER flags "
299 "set to use B0 steering. Falling back to A0 steering mode.\n");
301 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
303 mlx4_dbg(dev, "Steering mode is: %s\n",
304 mlx4_steering_mode_str(dev->caps.steering_mode));
306 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
307 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
308 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
309 /* Don't do sense port on multifunction devices (for now at least) */
310 if (mlx4_is_mfunc(dev))
311 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
313 dev->caps.log_num_macs = log_num_mac;
314 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
315 dev->caps.log_num_prios = use_prio ? 3 : 0;
317 for (i = 1; i <= dev->caps.num_ports; ++i) {
318 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
319 if (dev->caps.supported_type[i]) {
320 /* if only ETH is supported - assign ETH */
321 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
322 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
323 /* if only IB is supported, assign IB */
324 else if (dev->caps.supported_type[i] ==
326 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
328 /* if IB and ETH are supported, we set the port
329 * type according to user selection of port type;
330 * if user selected none, take the FW hint */
331 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
332 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
333 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
335 dev->caps.port_type[i] = port_type_array[i - 1];
339 * Link sensing is allowed on the port if 3 conditions are true:
340 * 1. Both protocols are supported on the port.
341 * 2. Different types are supported on the port
342 * 3. FW declared that it supports link sensing
344 mlx4_priv(dev)->sense.sense_allowed[i] =
345 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
346 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
347 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
350 * If "default_sense" bit is set, we move the port to "AUTO" mode
351 * and perform sense_port FW command to try and set the correct
352 * port type from beginning
354 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
355 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
356 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
357 mlx4_SENSE_PORT(dev, i, &sensed_port);
358 if (sensed_port != MLX4_PORT_TYPE_NONE)
359 dev->caps.port_type[i] = sensed_port;
361 dev->caps.possible_type[i] = dev->caps.port_type[i];
364 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
365 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
366 mlx4_warn(dev, "Requested number of MACs is too much "
367 "for port %d, reducing to %d.\n",
368 i, 1 << dev->caps.log_num_macs);
370 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
371 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
372 mlx4_warn(dev, "Requested number of VLANs is too much "
373 "for port %d, reducing to %d.\n",
374 i, 1 << dev->caps.log_num_vlans);
378 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
380 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
381 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
382 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
383 (1 << dev->caps.log_num_macs) *
384 (1 << dev->caps.log_num_vlans) *
385 (1 << dev->caps.log_num_prios) *
387 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
389 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
390 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
391 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
392 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
394 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
396 if (!enable_64b_cqe_eqe) {
398 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
399 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
400 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
401 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
405 if ((dev_cap->flags &
406 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
408 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
412 /*The function checks if there are live vf, return the num of them*/
413 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
415 struct mlx4_priv *priv = mlx4_priv(dev);
416 struct mlx4_slave_state *s_state;
420 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
421 s_state = &priv->mfunc.master.slave_state[i];
422 if (s_state->active && s_state->last_cmd !=
423 MLX4_COMM_CMD_RESET) {
424 mlx4_warn(dev, "%s: slave: %d is still active\n",
432 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
434 u32 qk = MLX4_RESERVED_QKEY_BASE;
436 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
437 qpn < dev->phys_caps.base_proxy_sqpn)
440 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
442 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
444 qk += qpn - dev->phys_caps.base_proxy_sqpn;
448 EXPORT_SYMBOL(mlx4_get_parav_qkey);
450 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
452 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
454 if (!mlx4_is_master(dev))
457 priv->virt2phys_pkey[slave][port - 1][i] = val;
459 EXPORT_SYMBOL(mlx4_sync_pkey_table);
461 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
463 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
465 if (!mlx4_is_master(dev))
468 priv->slave_node_guids[slave] = guid;
470 EXPORT_SYMBOL(mlx4_put_slave_node_guid);
472 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
474 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
476 if (!mlx4_is_master(dev))
479 return priv->slave_node_guids[slave];
481 EXPORT_SYMBOL(mlx4_get_slave_node_guid);
483 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
485 struct mlx4_priv *priv = mlx4_priv(dev);
486 struct mlx4_slave_state *s_slave;
488 if (!mlx4_is_master(dev))
491 s_slave = &priv->mfunc.master.slave_state[slave];
492 return !!s_slave->active;
494 EXPORT_SYMBOL(mlx4_is_slave_active);
496 static int mlx4_slave_cap(struct mlx4_dev *dev)
500 struct mlx4_dev_cap dev_cap;
501 struct mlx4_func_cap func_cap;
502 struct mlx4_init_hca_param hca_param;
505 memset(&hca_param, 0, sizeof(hca_param));
506 err = mlx4_QUERY_HCA(dev, &hca_param);
508 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n");
512 /*fail if the hca has an unknown capability */
513 if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) !=
514 HCA_GLOBAL_CAP_MASK) {
515 mlx4_err(dev, "Unknown hca global capabilities\n");
519 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
521 memset(&dev_cap, 0, sizeof(dev_cap));
522 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
523 err = mlx4_dev_cap(dev, &dev_cap);
525 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
529 err = mlx4_QUERY_FW(dev);
531 mlx4_err(dev, "QUERY_FW command failed: could not get FW version.\n");
533 page_size = ~dev->caps.page_size_cap + 1;
534 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
535 if (page_size > PAGE_SIZE) {
536 mlx4_err(dev, "HCA minimum page size of %d bigger than "
537 "kernel PAGE_SIZE of %ld, aborting.\n",
538 page_size, PAGE_SIZE);
542 /* slave gets uar page size from QUERY_HCA fw command */
543 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
545 /* TODO: relax this assumption */
546 if (dev->caps.uar_page_size != PAGE_SIZE) {
547 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
548 dev->caps.uar_page_size, PAGE_SIZE);
552 memset(&func_cap, 0, sizeof(func_cap));
553 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
555 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d).\n",
560 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
561 PF_CONTEXT_BEHAVIOUR_MASK) {
562 mlx4_err(dev, "Unknown pf context behaviour\n");
566 dev->caps.num_ports = func_cap.num_ports;
567 dev->caps.num_qps = func_cap.qp_quota;
568 dev->caps.num_srqs = func_cap.srq_quota;
569 dev->caps.num_cqs = func_cap.cq_quota;
570 dev->caps.num_eqs = func_cap.max_eq;
571 dev->caps.reserved_eqs = func_cap.reserved_eq;
572 dev->caps.num_mpts = func_cap.mpt_quota;
573 dev->caps.num_mtts = func_cap.mtt_quota;
574 dev->caps.num_pds = MLX4_NUM_PDS;
575 dev->caps.num_mgms = 0;
576 dev->caps.num_amgms = 0;
578 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
579 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
580 "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS);
584 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
585 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
586 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
587 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
589 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
590 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy) {
595 for (i = 1; i <= dev->caps.num_ports; ++i) {
596 err = mlx4_QUERY_FUNC_CAP(dev, (u32) i, &func_cap);
598 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for"
599 " port %d, aborting (%d).\n", i, err);
602 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
603 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
604 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
605 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
606 dev->caps.port_mask[i] = dev->caps.port_type[i];
607 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
608 &dev->caps.gid_table_len[i],
609 &dev->caps.pkey_table_len[i]))
613 if (dev->caps.uar_page_size * (dev->caps.num_uars -
614 dev->caps.reserved_uars) >
615 pci_resource_len(dev->pdev, 2)) {
616 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than "
617 "PCI resource 2 size of 0x%llx, aborting.\n",
618 dev->caps.uar_page_size * dev->caps.num_uars,
619 (unsigned long long) pci_resource_len(dev->pdev, 2));
623 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
624 dev->caps.eqe_size = 64;
625 dev->caps.eqe_factor = 1;
627 dev->caps.eqe_size = 32;
628 dev->caps.eqe_factor = 0;
631 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
632 dev->caps.cqe_size = 64;
633 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
635 dev->caps.cqe_size = 32;
641 kfree(dev->caps.qp0_tunnel);
642 kfree(dev->caps.qp0_proxy);
643 kfree(dev->caps.qp1_tunnel);
644 kfree(dev->caps.qp1_proxy);
645 dev->caps.qp0_tunnel = dev->caps.qp0_proxy =
646 dev->caps.qp1_tunnel = dev->caps.qp1_proxy = NULL;
652 * Change the port configuration of the device.
653 * Every user of this function must hold the port mutex.
655 int mlx4_change_port_types(struct mlx4_dev *dev,
656 enum mlx4_port_type *port_types)
662 for (port = 0; port < dev->caps.num_ports; port++) {
663 /* Change the port type only if the new type is different
664 * from the current, and not set to Auto */
665 if (port_types[port] != dev->caps.port_type[port + 1])
669 mlx4_unregister_device(dev);
670 for (port = 1; port <= dev->caps.num_ports; port++) {
671 mlx4_CLOSE_PORT(dev, port);
672 dev->caps.port_type[port] = port_types[port - 1];
673 err = mlx4_SET_PORT(dev, port, -1);
675 mlx4_err(dev, "Failed to set port %d, "
680 mlx4_set_port_mask(dev);
681 err = mlx4_register_device(dev);
688 static ssize_t show_port_type(struct device *dev,
689 struct device_attribute *attr,
692 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
694 struct mlx4_dev *mdev = info->dev;
698 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
700 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
701 sprintf(buf, "auto (%s)\n", type);
703 sprintf(buf, "%s\n", type);
708 static ssize_t set_port_type(struct device *dev,
709 struct device_attribute *attr,
710 const char *buf, size_t count)
712 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
714 struct mlx4_dev *mdev = info->dev;
715 struct mlx4_priv *priv = mlx4_priv(mdev);
716 enum mlx4_port_type types[MLX4_MAX_PORTS];
717 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
721 if (!strcmp(buf, "ib\n"))
722 info->tmp_type = MLX4_PORT_TYPE_IB;
723 else if (!strcmp(buf, "eth\n"))
724 info->tmp_type = MLX4_PORT_TYPE_ETH;
725 else if (!strcmp(buf, "auto\n"))
726 info->tmp_type = MLX4_PORT_TYPE_AUTO;
728 mlx4_err(mdev, "%s is not supported port type\n", buf);
732 mlx4_stop_sense(mdev);
733 mutex_lock(&priv->port_mutex);
734 /* Possible type is always the one that was delivered */
735 mdev->caps.possible_type[info->port] = info->tmp_type;
737 for (i = 0; i < mdev->caps.num_ports; i++) {
738 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
739 mdev->caps.possible_type[i+1];
740 if (types[i] == MLX4_PORT_TYPE_AUTO)
741 types[i] = mdev->caps.port_type[i+1];
744 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
745 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
746 for (i = 1; i <= mdev->caps.num_ports; i++) {
747 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
748 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
754 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
755 "Set only 'eth' or 'ib' for both ports "
756 "(should be the same)\n");
760 mlx4_do_sense_ports(mdev, new_types, types);
762 err = mlx4_check_port_params(mdev, new_types);
766 /* We are about to apply the changes after the configuration
767 * was verified, no need to remember the temporary types
769 for (i = 0; i < mdev->caps.num_ports; i++)
770 priv->port[i + 1].tmp_type = 0;
772 err = mlx4_change_port_types(mdev, new_types);
775 mlx4_start_sense(mdev);
776 mutex_unlock(&priv->port_mutex);
777 return err ? err : count;
788 static inline int int_to_ibta_mtu(int mtu)
791 case 256: return IB_MTU_256;
792 case 512: return IB_MTU_512;
793 case 1024: return IB_MTU_1024;
794 case 2048: return IB_MTU_2048;
795 case 4096: return IB_MTU_4096;
800 static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
803 case IB_MTU_256: return 256;
804 case IB_MTU_512: return 512;
805 case IB_MTU_1024: return 1024;
806 case IB_MTU_2048: return 2048;
807 case IB_MTU_4096: return 4096;
812 static ssize_t show_port_ib_mtu(struct device *dev,
813 struct device_attribute *attr,
816 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
818 struct mlx4_dev *mdev = info->dev;
820 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
821 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
824 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
828 static ssize_t set_port_ib_mtu(struct device *dev,
829 struct device_attribute *attr,
830 const char *buf, size_t count)
832 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
834 struct mlx4_dev *mdev = info->dev;
835 struct mlx4_priv *priv = mlx4_priv(mdev);
836 int err, port, mtu, ibta_mtu = -1;
838 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
839 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
843 err = sscanf(buf, "%d", &mtu);
845 ibta_mtu = int_to_ibta_mtu(mtu);
847 if (err <= 0 || ibta_mtu < 0) {
848 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
852 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
854 mlx4_stop_sense(mdev);
855 mutex_lock(&priv->port_mutex);
856 mlx4_unregister_device(mdev);
857 for (port = 1; port <= mdev->caps.num_ports; port++) {
858 mlx4_CLOSE_PORT(mdev, port);
859 err = mlx4_SET_PORT(mdev, port, -1);
861 mlx4_err(mdev, "Failed to set port %d, "
866 err = mlx4_register_device(mdev);
868 mutex_unlock(&priv->port_mutex);
869 mlx4_start_sense(mdev);
870 return err ? err : count;
873 static int mlx4_load_fw(struct mlx4_dev *dev)
875 struct mlx4_priv *priv = mlx4_priv(dev);
878 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
879 GFP_HIGHUSER | __GFP_NOWARN, 0);
880 if (!priv->fw.fw_icm) {
881 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
885 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
887 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
891 err = mlx4_RUN_FW(dev);
893 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
903 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
907 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
910 struct mlx4_priv *priv = mlx4_priv(dev);
914 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
916 ((u64) (MLX4_CMPT_TYPE_QP *
917 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
918 cmpt_entry_sz, dev->caps.num_qps,
919 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
924 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
926 ((u64) (MLX4_CMPT_TYPE_SRQ *
927 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
928 cmpt_entry_sz, dev->caps.num_srqs,
929 dev->caps.reserved_srqs, 0, 0);
933 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
935 ((u64) (MLX4_CMPT_TYPE_CQ *
936 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
937 cmpt_entry_sz, dev->caps.num_cqs,
938 dev->caps.reserved_cqs, 0, 0);
942 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
944 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
946 ((u64) (MLX4_CMPT_TYPE_EQ *
947 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
948 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
955 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
958 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
961 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
967 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
968 struct mlx4_init_hca_param *init_hca, u64 icm_size)
970 struct mlx4_priv *priv = mlx4_priv(dev);
975 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
977 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
981 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
982 (unsigned long long) icm_size >> 10,
983 (unsigned long long) aux_pages << 2);
985 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
986 GFP_HIGHUSER | __GFP_NOWARN, 0);
987 if (!priv->fw.aux_icm) {
988 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
992 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
994 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
998 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1000 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
1005 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1007 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1008 init_hca->eqc_base, dev_cap->eqc_entry_sz,
1009 num_eqs, num_eqs, 0, 0);
1011 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
1012 goto err_unmap_cmpt;
1016 * Reserved MTT entries must be aligned up to a cacheline
1017 * boundary, since the FW will write to them, while the driver
1018 * writes to all other MTT entries. (The variable
1019 * dev->caps.mtt_entry_sz below is really the MTT segment
1020 * size, not the raw entry size)
1022 dev->caps.reserved_mtts =
1023 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1024 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1026 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1028 dev->caps.mtt_entry_sz,
1030 dev->caps.reserved_mtts, 1, 0);
1032 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
1036 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1037 init_hca->dmpt_base,
1038 dev_cap->dmpt_entry_sz,
1040 dev->caps.reserved_mrws, 1, 1);
1042 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
1046 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1048 dev_cap->qpc_entry_sz,
1050 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1053 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
1054 goto err_unmap_dmpt;
1057 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1058 init_hca->auxc_base,
1059 dev_cap->aux_entry_sz,
1061 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1064 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
1068 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1069 init_hca->altc_base,
1070 dev_cap->altc_entry_sz,
1072 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1075 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
1076 goto err_unmap_auxc;
1079 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1080 init_hca->rdmarc_base,
1081 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1083 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1086 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1087 goto err_unmap_altc;
1090 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1092 dev_cap->cqc_entry_sz,
1094 dev->caps.reserved_cqs, 0, 0);
1096 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
1097 goto err_unmap_rdmarc;
1100 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1101 init_hca->srqc_base,
1102 dev_cap->srq_entry_sz,
1104 dev->caps.reserved_srqs, 0, 0);
1106 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
1111 * For flow steering device managed mode it is required to use
1112 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1113 * required, but for simplicity just map the whole multicast
1114 * group table now. The table isn't very big and it's a lot
1115 * easier than trying to track ref counts.
1117 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
1119 mlx4_get_mgm_entry_size(dev),
1120 dev->caps.num_mgms + dev->caps.num_amgms,
1121 dev->caps.num_mgms + dev->caps.num_amgms,
1124 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
1131 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1134 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1137 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1140 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1143 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1146 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1149 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1152 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1155 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1158 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1159 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1160 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1161 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1164 mlx4_UNMAP_ICM_AUX(dev);
1167 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1172 static void mlx4_free_icms(struct mlx4_dev *dev)
1174 struct mlx4_priv *priv = mlx4_priv(dev);
1176 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1177 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1178 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1179 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1180 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1181 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1182 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1183 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1184 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1185 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1186 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1187 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1188 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1189 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1191 mlx4_UNMAP_ICM_AUX(dev);
1192 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1195 static void mlx4_slave_exit(struct mlx4_dev *dev)
1197 struct mlx4_priv *priv = mlx4_priv(dev);
1199 mutex_lock(&priv->cmd.slave_cmd_mutex);
1200 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1201 mlx4_warn(dev, "Failed to close slave function.\n");
1202 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1205 static int map_bf_area(struct mlx4_dev *dev)
1207 struct mlx4_priv *priv = mlx4_priv(dev);
1208 resource_size_t bf_start;
1209 resource_size_t bf_len;
1212 if (!dev->caps.bf_reg_size)
1215 bf_start = pci_resource_start(dev->pdev, 2) +
1216 (dev->caps.num_uars << PAGE_SHIFT);
1217 bf_len = pci_resource_len(dev->pdev, 2) -
1218 (dev->caps.num_uars << PAGE_SHIFT);
1219 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1220 if (!priv->bf_mapping)
1226 static void unmap_bf_area(struct mlx4_dev *dev)
1228 if (mlx4_priv(dev)->bf_mapping)
1229 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1232 static void mlx4_close_hca(struct mlx4_dev *dev)
1235 if (mlx4_is_slave(dev))
1236 mlx4_slave_exit(dev);
1238 mlx4_CLOSE_HCA(dev, 0);
1239 mlx4_free_icms(dev);
1241 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1245 static int mlx4_init_slave(struct mlx4_dev *dev)
1247 struct mlx4_priv *priv = mlx4_priv(dev);
1248 u64 dma = (u64) priv->mfunc.vhcr_dma;
1249 int num_of_reset_retries = NUM_OF_RESET_RETRIES;
1250 int ret_from_reset = 0;
1252 u32 cmd_channel_ver;
1254 mutex_lock(&priv->cmd.slave_cmd_mutex);
1255 priv->cmd.max_cmds = 1;
1256 mlx4_warn(dev, "Sending reset\n");
1257 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1259 /* if we are in the middle of flr the slave will try
1260 * NUM_OF_RESET_RETRIES times before leaving.*/
1261 if (ret_from_reset) {
1262 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1263 msleep(SLEEP_TIME_IN_RESET);
1264 while (ret_from_reset && num_of_reset_retries) {
1265 mlx4_warn(dev, "slave is currently in the"
1266 "middle of FLR. retrying..."
1268 (NUM_OF_RESET_RETRIES -
1269 num_of_reset_retries + 1));
1271 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET,
1273 num_of_reset_retries = num_of_reset_retries - 1;
1279 /* check the driver version - the slave I/F revision
1280 * must match the master's */
1281 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1282 cmd_channel_ver = mlx4_comm_get_version();
1284 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1285 MLX4_COMM_GET_IF_REV(slave_read)) {
1286 mlx4_err(dev, "slave driver version is not supported"
1287 " by the master\n");
1291 mlx4_warn(dev, "Sending vhcr0\n");
1292 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1295 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1298 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1301 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1304 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1308 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
1309 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1313 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1317 for (i = 1; i <= dev->caps.num_ports; i++) {
1318 dev->caps.gid_table_len[i] = 1;
1319 dev->caps.pkey_table_len[i] =
1320 dev->phys_caps.pkey_phys_table_len[i] - 1;
1324 static int mlx4_init_hca(struct mlx4_dev *dev)
1326 struct mlx4_priv *priv = mlx4_priv(dev);
1327 struct mlx4_adapter adapter;
1328 struct mlx4_dev_cap dev_cap;
1329 struct mlx4_mod_stat_cfg mlx4_cfg;
1330 struct mlx4_profile profile;
1331 struct mlx4_init_hca_param init_hca;
1335 if (!mlx4_is_slave(dev)) {
1336 err = mlx4_QUERY_FW(dev);
1339 mlx4_info(dev, "non-primary physical function, skipping.\n");
1341 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
1345 err = mlx4_load_fw(dev);
1347 mlx4_err(dev, "Failed to start FW, aborting.\n");
1351 mlx4_cfg.log_pg_sz_m = 1;
1352 mlx4_cfg.log_pg_sz = 0;
1353 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1355 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
1357 err = mlx4_dev_cap(dev, &dev_cap);
1359 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
1363 if (mlx4_is_master(dev))
1364 mlx4_parav_master_pf_caps(dev);
1366 priv->fs_hash_mode = MLX4_FS_L2_HASH;
1368 switch (priv->fs_hash_mode) {
1369 case MLX4_FS_L2_HASH:
1370 init_hca.fs_hash_enable_bits = 0;
1373 case MLX4_FS_L2_L3_L4_HASH:
1374 /* Enable flow steering with
1375 * udp unicast and tcp unicast
1377 init_hca.fs_hash_enable_bits =
1378 MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN;
1382 profile = default_profile;
1383 if (dev->caps.steering_mode ==
1384 MLX4_STEERING_MODE_DEVICE_MANAGED)
1385 profile.num_mcg = MLX4_FS_NUM_MCG;
1387 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1389 if ((long long) icm_size < 0) {
1394 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
1396 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1397 init_hca.uar_page_sz = PAGE_SHIFT - 12;
1399 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1403 err = mlx4_INIT_HCA(dev, &init_hca);
1405 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
1409 err = mlx4_init_slave(dev);
1411 mlx4_err(dev, "Failed to initialize slave\n");
1415 err = mlx4_slave_cap(dev);
1417 mlx4_err(dev, "Failed to obtain slave caps\n");
1422 if (map_bf_area(dev))
1423 mlx4_dbg(dev, "Failed to map blue flame area\n");
1425 /*Only the master set the ports, all the rest got it from it.*/
1426 if (!mlx4_is_slave(dev))
1427 mlx4_set_port_mask(dev);
1429 err = mlx4_QUERY_ADAPTER(dev, &adapter);
1431 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
1435 priv->eq_table.inta_pin = adapter.inta_pin;
1436 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
1444 if (mlx4_is_slave(dev))
1445 mlx4_slave_exit(dev);
1447 mlx4_CLOSE_HCA(dev, 0);
1450 if (!mlx4_is_slave(dev))
1451 mlx4_free_icms(dev);
1454 if (!mlx4_is_slave(dev)) {
1456 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1461 static int mlx4_init_counters_table(struct mlx4_dev *dev)
1463 struct mlx4_priv *priv = mlx4_priv(dev);
1466 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1469 nent = dev->caps.max_counters;
1470 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
1473 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
1475 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
1478 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1480 struct mlx4_priv *priv = mlx4_priv(dev);
1482 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1485 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
1492 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1497 if (mlx4_is_mfunc(dev)) {
1498 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
1499 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
1500 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1502 *idx = get_param_l(&out_param);
1506 return __mlx4_counter_alloc(dev, idx);
1508 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
1510 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1512 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx);
1516 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1520 if (mlx4_is_mfunc(dev)) {
1521 set_param_l(&in_param, idx);
1522 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
1523 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
1527 __mlx4_counter_free(dev, idx);
1529 EXPORT_SYMBOL_GPL(mlx4_counter_free);
1531 static int mlx4_setup_hca(struct mlx4_dev *dev)
1533 struct mlx4_priv *priv = mlx4_priv(dev);
1536 __be32 ib_port_default_caps;
1538 err = mlx4_init_uar_table(dev);
1540 mlx4_err(dev, "Failed to initialize "
1541 "user access region table, aborting.\n");
1545 err = mlx4_uar_alloc(dev, &priv->driver_uar);
1547 mlx4_err(dev, "Failed to allocate driver access region, "
1549 goto err_uar_table_free;
1552 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
1554 mlx4_err(dev, "Couldn't map kernel access region, "
1560 err = mlx4_init_pd_table(dev);
1562 mlx4_err(dev, "Failed to initialize "
1563 "protection domain table, aborting.\n");
1567 err = mlx4_init_xrcd_table(dev);
1569 mlx4_err(dev, "Failed to initialize "
1570 "reliable connection domain table, aborting.\n");
1571 goto err_pd_table_free;
1574 err = mlx4_init_mr_table(dev);
1576 mlx4_err(dev, "Failed to initialize "
1577 "memory region table, aborting.\n");
1578 goto err_xrcd_table_free;
1581 err = mlx4_init_eq_table(dev);
1583 mlx4_err(dev, "Failed to initialize "
1584 "event queue table, aborting.\n");
1585 goto err_mr_table_free;
1588 err = mlx4_cmd_use_events(dev);
1590 mlx4_err(dev, "Failed to switch to event-driven "
1591 "firmware commands, aborting.\n");
1592 goto err_eq_table_free;
1595 err = mlx4_NOP(dev);
1597 if (dev->flags & MLX4_FLAG_MSI_X) {
1598 mlx4_warn(dev, "NOP command failed to generate MSI-X "
1599 "interrupt IRQ %d).\n",
1600 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1601 mlx4_warn(dev, "Trying again without MSI-X.\n");
1603 mlx4_err(dev, "NOP command failed to generate interrupt "
1604 "(IRQ %d), aborting.\n",
1605 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1606 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
1612 mlx4_dbg(dev, "NOP command IRQ test passed\n");
1614 err = mlx4_init_cq_table(dev);
1616 mlx4_err(dev, "Failed to initialize "
1617 "completion queue table, aborting.\n");
1621 err = mlx4_init_srq_table(dev);
1623 mlx4_err(dev, "Failed to initialize "
1624 "shared receive queue table, aborting.\n");
1625 goto err_cq_table_free;
1628 err = mlx4_init_qp_table(dev);
1630 mlx4_err(dev, "Failed to initialize "
1631 "queue pair table, aborting.\n");
1632 goto err_srq_table_free;
1635 if (!mlx4_is_slave(dev)) {
1636 err = mlx4_init_mcg_table(dev);
1638 mlx4_err(dev, "Failed to initialize "
1639 "multicast group table, aborting.\n");
1640 goto err_qp_table_free;
1644 err = mlx4_init_counters_table(dev);
1645 if (err && err != -ENOENT) {
1646 mlx4_err(dev, "Failed to initialize counters table, aborting.\n");
1647 goto err_mcg_table_free;
1650 if (!mlx4_is_slave(dev)) {
1651 for (port = 1; port <= dev->caps.num_ports; port++) {
1652 ib_port_default_caps = 0;
1653 err = mlx4_get_port_ib_caps(dev, port,
1654 &ib_port_default_caps);
1656 mlx4_warn(dev, "failed to get port %d default "
1657 "ib capabilities (%d). Continuing "
1658 "with caps = 0\n", port, err);
1659 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1661 /* initialize per-slave default ib port capabilities */
1662 if (mlx4_is_master(dev)) {
1664 for (i = 0; i < dev->num_slaves; i++) {
1665 if (i == mlx4_master_func_num(dev))
1667 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1668 ib_port_default_caps;
1672 if (mlx4_is_mfunc(dev))
1673 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
1675 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
1677 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
1678 dev->caps.pkey_table_len[port] : -1);
1680 mlx4_err(dev, "Failed to set port %d, aborting\n",
1682 goto err_counters_table_free;
1689 err_counters_table_free:
1690 mlx4_cleanup_counters_table(dev);
1693 mlx4_cleanup_mcg_table(dev);
1696 mlx4_cleanup_qp_table(dev);
1699 mlx4_cleanup_srq_table(dev);
1702 mlx4_cleanup_cq_table(dev);
1705 mlx4_cmd_use_polling(dev);
1708 mlx4_cleanup_eq_table(dev);
1711 mlx4_cleanup_mr_table(dev);
1713 err_xrcd_table_free:
1714 mlx4_cleanup_xrcd_table(dev);
1717 mlx4_cleanup_pd_table(dev);
1723 mlx4_uar_free(dev, &priv->driver_uar);
1726 mlx4_cleanup_uar_table(dev);
1730 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
1732 struct mlx4_priv *priv = mlx4_priv(dev);
1733 struct msix_entry *entries;
1734 int nreq = min_t(int, dev->caps.num_ports *
1735 min_t(int, netif_get_num_default_rss_queues() + 1,
1736 MAX_MSIX_P_PORT) + MSIX_LEGACY_SZ, MAX_MSIX);
1741 /* In multifunction mode each function gets 2 msi-X vectors
1742 * one for data path completions anf the other for asynch events
1743 * or command completions */
1744 if (mlx4_is_mfunc(dev)) {
1747 nreq = min_t(int, dev->caps.num_eqs -
1748 dev->caps.reserved_eqs, nreq);
1751 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
1755 for (i = 0; i < nreq; ++i)
1756 entries[i].entry = i;
1759 err = pci_enable_msix(dev->pdev, entries, nreq);
1761 /* Try again if at least 2 vectors are available */
1763 mlx4_info(dev, "Requested %d vectors, "
1764 "but only %d MSI-X vectors available, "
1765 "trying again\n", nreq, err);
1774 MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) {
1775 /*Working in legacy mode , all EQ's shared*/
1776 dev->caps.comp_pool = 0;
1777 dev->caps.num_comp_vectors = nreq - 1;
1779 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
1780 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
1782 for (i = 0; i < nreq; ++i)
1783 priv->eq_table.eq[i].irq = entries[i].vector;
1785 dev->flags |= MLX4_FLAG_MSI_X;
1792 dev->caps.num_comp_vectors = 1;
1793 dev->caps.comp_pool = 0;
1795 for (i = 0; i < 2; ++i)
1796 priv->eq_table.eq[i].irq = dev->pdev->irq;
1799 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
1801 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
1806 if (!mlx4_is_slave(dev)) {
1807 INIT_RADIX_TREE(&info->mac_tree, GFP_KERNEL);
1808 mlx4_init_mac_table(dev, &info->mac_table);
1809 mlx4_init_vlan_table(dev, &info->vlan_table);
1811 dev->caps.reserved_qps_base[MLX4_QP_REGION_ETH_ADDR] +
1812 (port - 1) * (1 << log_num_mac);
1815 sprintf(info->dev_name, "mlx4_port%d", port);
1816 info->port_attr.attr.name = info->dev_name;
1817 if (mlx4_is_mfunc(dev))
1818 info->port_attr.attr.mode = S_IRUGO;
1820 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
1821 info->port_attr.store = set_port_type;
1823 info->port_attr.show = show_port_type;
1824 sysfs_attr_init(&info->port_attr.attr);
1826 err = device_create_file(&dev->pdev->dev, &info->port_attr);
1828 mlx4_err(dev, "Failed to create file for port %d\n", port);
1832 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
1833 info->port_mtu_attr.attr.name = info->dev_mtu_name;
1834 if (mlx4_is_mfunc(dev))
1835 info->port_mtu_attr.attr.mode = S_IRUGO;
1837 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
1838 info->port_mtu_attr.store = set_port_ib_mtu;
1840 info->port_mtu_attr.show = show_port_ib_mtu;
1841 sysfs_attr_init(&info->port_mtu_attr.attr);
1843 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
1845 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
1846 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
1853 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
1858 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
1859 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
1862 static int mlx4_init_steering(struct mlx4_dev *dev)
1864 struct mlx4_priv *priv = mlx4_priv(dev);
1865 int num_entries = dev->caps.num_ports;
1868 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
1872 for (i = 0; i < num_entries; i++)
1873 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1874 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
1875 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
1880 static void mlx4_clear_steering(struct mlx4_dev *dev)
1882 struct mlx4_priv *priv = mlx4_priv(dev);
1883 struct mlx4_steer_index *entry, *tmp_entry;
1884 struct mlx4_promisc_qp *pqp, *tmp_pqp;
1885 int num_entries = dev->caps.num_ports;
1888 for (i = 0; i < num_entries; i++) {
1889 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1890 list_for_each_entry_safe(pqp, tmp_pqp,
1891 &priv->steer[i].promisc_qps[j],
1893 list_del(&pqp->list);
1896 list_for_each_entry_safe(entry, tmp_entry,
1897 &priv->steer[i].steer_entries[j],
1899 list_del(&entry->list);
1900 list_for_each_entry_safe(pqp, tmp_pqp,
1903 list_del(&pqp->list);
1913 static int extended_func_num(struct pci_dev *pdev)
1915 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
1918 #define MLX4_OWNER_BASE 0x8069c
1919 #define MLX4_OWNER_SIZE 4
1921 static int mlx4_get_ownership(struct mlx4_dev *dev)
1923 void __iomem *owner;
1926 if (pci_channel_offline(dev->pdev))
1929 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
1932 mlx4_err(dev, "Failed to obtain ownership bit\n");
1941 static void mlx4_free_ownership(struct mlx4_dev *dev)
1943 void __iomem *owner;
1945 if (pci_channel_offline(dev->pdev))
1948 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
1951 mlx4_err(dev, "Failed to obtain ownership bit\n");
1959 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data)
1961 struct mlx4_priv *priv;
1962 struct mlx4_dev *dev;
1966 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
1968 err = pci_enable_device(pdev);
1970 dev_err(&pdev->dev, "Cannot enable PCI device, "
1974 if (num_vfs > MLX4_MAX_NUM_VF) {
1975 printk(KERN_ERR "There are more VF's (%d) than allowed(%d)\n",
1976 num_vfs, MLX4_MAX_NUM_VF);
1982 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
1983 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1984 dev_err(&pdev->dev, "Missing DCS, aborting."
1985 "(driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
1986 pci_dev_data, pci_resource_flags(pdev, 0));
1988 goto err_disable_pdev;
1990 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
1991 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
1993 goto err_disable_pdev;
1996 err = pci_request_regions(pdev, DRV_NAME);
1998 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
1999 goto err_disable_pdev;
2002 pci_set_master(pdev);
2004 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
2006 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
2007 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2009 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
2010 goto err_release_regions;
2013 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
2015 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
2016 "consistent PCI DMA mask.\n");
2017 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2019 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
2021 goto err_release_regions;
2025 /* Allow large DMA segments, up to the firmware limit of 1 GB */
2026 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
2028 priv = kzalloc(sizeof *priv, GFP_KERNEL);
2030 dev_err(&pdev->dev, "Device struct alloc failed, "
2033 goto err_release_regions;
2038 INIT_LIST_HEAD(&priv->ctx_list);
2039 spin_lock_init(&priv->ctx_lock);
2041 mutex_init(&priv->port_mutex);
2043 INIT_LIST_HEAD(&priv->pgdir_list);
2044 mutex_init(&priv->pgdir_mutex);
2046 INIT_LIST_HEAD(&priv->bf_list);
2047 mutex_init(&priv->bf_mutex);
2049 dev->rev_id = pdev->revision;
2050 /* Detect if this device is a virtual function */
2051 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
2052 /* When acting as pf, we normally skip vfs unless explicitly
2053 * requested to probe them. */
2054 if (num_vfs && extended_func_num(pdev) > probe_vf) {
2055 mlx4_warn(dev, "Skipping virtual function:%d\n",
2056 extended_func_num(pdev));
2060 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
2061 dev->flags |= MLX4_FLAG_SLAVE;
2063 /* We reset the device and enable SRIOV only for physical
2064 * devices. Try to claim ownership on the device;
2065 * if already taken, skip -- do not allow multiple PFs */
2066 err = mlx4_get_ownership(dev);
2071 mlx4_warn(dev, "Multiple PFs not yet supported."
2079 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", num_vfs);
2080 err = pci_enable_sriov(pdev, num_vfs);
2082 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d).\n",
2086 mlx4_warn(dev, "Running in master mode\n");
2087 dev->flags |= MLX4_FLAG_SRIOV |
2089 dev->num_vfs = num_vfs;
2094 * Now reset the HCA before we touch the PCI capabilities or
2095 * attempt a firmware command, since a boot ROM may have left
2096 * the HCA in an undefined state.
2098 err = mlx4_reset(dev);
2100 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
2106 err = mlx4_cmd_init(dev);
2108 mlx4_err(dev, "Failed to init command interface, aborting.\n");
2112 /* In slave functions, the communication channel must be initialized
2113 * before posting commands. Also, init num_slaves before calling
2115 if (mlx4_is_mfunc(dev)) {
2116 if (mlx4_is_master(dev))
2117 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
2119 dev->num_slaves = 0;
2120 if (mlx4_multi_func_init(dev)) {
2121 mlx4_err(dev, "Failed to init slave mfunc"
2122 " interface, aborting.\n");
2128 err = mlx4_init_hca(dev);
2130 if (err == -EACCES) {
2131 /* Not primary Physical function
2132 * Running in slave mode */
2133 mlx4_cmd_cleanup(dev);
2134 dev->flags |= MLX4_FLAG_SLAVE;
2135 dev->flags &= ~MLX4_FLAG_MASTER;
2141 /* In master functions, the communication channel must be initialized
2142 * after obtaining its address from fw */
2143 if (mlx4_is_master(dev)) {
2144 if (mlx4_multi_func_init(dev)) {
2145 mlx4_err(dev, "Failed to init master mfunc"
2146 "interface, aborting.\n");
2151 err = mlx4_alloc_eq_table(dev);
2153 goto err_master_mfunc;
2155 priv->msix_ctl.pool_bm = 0;
2156 mutex_init(&priv->msix_ctl.pool_lock);
2158 mlx4_enable_msi_x(dev);
2159 if ((mlx4_is_mfunc(dev)) &&
2160 !(dev->flags & MLX4_FLAG_MSI_X)) {
2161 mlx4_err(dev, "INTx is not supported in multi-function mode."
2166 if (!mlx4_is_slave(dev)) {
2167 err = mlx4_init_steering(dev);
2172 err = mlx4_setup_hca(dev);
2173 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
2174 !mlx4_is_mfunc(dev)) {
2175 dev->flags &= ~MLX4_FLAG_MSI_X;
2176 dev->caps.num_comp_vectors = 1;
2177 dev->caps.comp_pool = 0;
2178 pci_disable_msix(pdev);
2179 err = mlx4_setup_hca(dev);
2185 for (port = 1; port <= dev->caps.num_ports; port++) {
2186 err = mlx4_init_port_info(dev, port);
2191 err = mlx4_register_device(dev);
2195 mlx4_sense_init(dev);
2196 mlx4_start_sense(dev);
2198 priv->pci_dev_data = pci_dev_data;
2199 pci_set_drvdata(pdev, dev);
2204 for (--port; port >= 1; --port)
2205 mlx4_cleanup_port_info(&priv->port[port]);
2207 mlx4_cleanup_counters_table(dev);
2208 mlx4_cleanup_mcg_table(dev);
2209 mlx4_cleanup_qp_table(dev);
2210 mlx4_cleanup_srq_table(dev);
2211 mlx4_cleanup_cq_table(dev);
2212 mlx4_cmd_use_polling(dev);
2213 mlx4_cleanup_eq_table(dev);
2214 mlx4_cleanup_mr_table(dev);
2215 mlx4_cleanup_xrcd_table(dev);
2216 mlx4_cleanup_pd_table(dev);
2217 mlx4_cleanup_uar_table(dev);
2220 if (!mlx4_is_slave(dev))
2221 mlx4_clear_steering(dev);
2224 mlx4_free_eq_table(dev);
2227 if (mlx4_is_master(dev))
2228 mlx4_multi_func_cleanup(dev);
2231 if (dev->flags & MLX4_FLAG_MSI_X)
2232 pci_disable_msix(pdev);
2234 mlx4_close_hca(dev);
2237 if (mlx4_is_slave(dev))
2238 mlx4_multi_func_cleanup(dev);
2241 mlx4_cmd_cleanup(dev);
2244 if (dev->flags & MLX4_FLAG_SRIOV)
2245 pci_disable_sriov(pdev);
2248 if (!mlx4_is_slave(dev))
2249 mlx4_free_ownership(dev);
2254 err_release_regions:
2255 pci_release_regions(pdev);
2258 pci_disable_device(pdev);
2259 pci_set_drvdata(pdev, NULL);
2263 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
2265 printk_once(KERN_INFO "%s", mlx4_version);
2267 return __mlx4_init_one(pdev, id->driver_data);
2270 static void mlx4_remove_one(struct pci_dev *pdev)
2272 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2273 struct mlx4_priv *priv = mlx4_priv(dev);
2277 /* in SRIOV it is not allowed to unload the pf's
2278 * driver while there are alive vf's */
2279 if (mlx4_is_master(dev)) {
2280 if (mlx4_how_many_lives_vf(dev))
2281 printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n");
2283 mlx4_stop_sense(dev);
2284 mlx4_unregister_device(dev);
2286 for (p = 1; p <= dev->caps.num_ports; p++) {
2287 mlx4_cleanup_port_info(&priv->port[p]);
2288 mlx4_CLOSE_PORT(dev, p);
2291 if (mlx4_is_master(dev))
2292 mlx4_free_resource_tracker(dev,
2293 RES_TR_FREE_SLAVES_ONLY);
2295 mlx4_cleanup_counters_table(dev);
2296 mlx4_cleanup_mcg_table(dev);
2297 mlx4_cleanup_qp_table(dev);
2298 mlx4_cleanup_srq_table(dev);
2299 mlx4_cleanup_cq_table(dev);
2300 mlx4_cmd_use_polling(dev);
2301 mlx4_cleanup_eq_table(dev);
2302 mlx4_cleanup_mr_table(dev);
2303 mlx4_cleanup_xrcd_table(dev);
2304 mlx4_cleanup_pd_table(dev);
2306 if (mlx4_is_master(dev))
2307 mlx4_free_resource_tracker(dev,
2308 RES_TR_FREE_STRUCTS_ONLY);
2311 mlx4_uar_free(dev, &priv->driver_uar);
2312 mlx4_cleanup_uar_table(dev);
2313 if (!mlx4_is_slave(dev))
2314 mlx4_clear_steering(dev);
2315 mlx4_free_eq_table(dev);
2316 if (mlx4_is_master(dev))
2317 mlx4_multi_func_cleanup(dev);
2318 mlx4_close_hca(dev);
2319 if (mlx4_is_slave(dev))
2320 mlx4_multi_func_cleanup(dev);
2321 mlx4_cmd_cleanup(dev);
2323 if (dev->flags & MLX4_FLAG_MSI_X)
2324 pci_disable_msix(pdev);
2325 if (dev->flags & MLX4_FLAG_SRIOV) {
2326 mlx4_warn(dev, "Disabling SR-IOV\n");
2327 pci_disable_sriov(pdev);
2330 if (!mlx4_is_slave(dev))
2331 mlx4_free_ownership(dev);
2333 kfree(dev->caps.qp0_tunnel);
2334 kfree(dev->caps.qp0_proxy);
2335 kfree(dev->caps.qp1_tunnel);
2336 kfree(dev->caps.qp1_proxy);
2339 pci_release_regions(pdev);
2340 pci_disable_device(pdev);
2341 pci_set_drvdata(pdev, NULL);
2345 int mlx4_restart_one(struct pci_dev *pdev)
2347 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2348 struct mlx4_priv *priv = mlx4_priv(dev);
2351 pci_dev_data = priv->pci_dev_data;
2352 mlx4_remove_one(pdev);
2353 return __mlx4_init_one(pdev, pci_dev_data);
2356 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
2357 /* MT25408 "Hermon" SDR */
2358 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2359 /* MT25408 "Hermon" DDR */
2360 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2361 /* MT25408 "Hermon" QDR */
2362 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2363 /* MT25408 "Hermon" DDR PCIe gen2 */
2364 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2365 /* MT25408 "Hermon" QDR PCIe gen2 */
2366 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2367 /* MT25408 "Hermon" EN 10GigE */
2368 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2369 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
2370 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2371 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
2372 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2373 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
2374 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2375 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
2376 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2377 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
2378 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2379 /* MT26478 ConnectX2 40GigE PCIe gen2 */
2380 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2381 /* MT25400 Family [ConnectX-2 Virtual Function] */
2382 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
2383 /* MT27500 Family [ConnectX-3] */
2384 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
2385 /* MT27500 Family [ConnectX-3 Virtual Function] */
2386 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
2387 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
2388 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
2389 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
2390 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
2391 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
2392 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
2393 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
2394 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
2395 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
2396 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
2397 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
2398 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
2402 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
2404 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
2405 pci_channel_state_t state)
2407 mlx4_remove_one(pdev);
2409 return state == pci_channel_io_perm_failure ?
2410 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
2413 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
2415 int ret = __mlx4_init_one(pdev, 0);
2417 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
2420 static const struct pci_error_handlers mlx4_err_handler = {
2421 .error_detected = mlx4_pci_err_detected,
2422 .slot_reset = mlx4_pci_slot_reset,
2425 static struct pci_driver mlx4_driver = {
2427 .id_table = mlx4_pci_table,
2428 .probe = mlx4_init_one,
2429 .remove = mlx4_remove_one,
2430 .err_handler = &mlx4_err_handler,
2433 static int __init mlx4_verify_params(void)
2435 if ((log_num_mac < 0) || (log_num_mac > 7)) {
2436 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
2440 if (log_num_vlan != 0)
2441 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2442 MLX4_LOG_NUM_VLANS);
2444 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
2445 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
2449 /* Check if module param for ports type has legal combination */
2450 if (port_type_array[0] == false && port_type_array[1] == true) {
2451 printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2452 port_type_array[0] = true;
2458 static int __init mlx4_init(void)
2462 if (mlx4_verify_params())
2467 mlx4_wq = create_singlethread_workqueue("mlx4");
2471 ret = pci_register_driver(&mlx4_driver);
2472 return ret < 0 ? ret : 0;
2475 static void __exit mlx4_cleanup(void)
2477 pci_unregister_driver(&mlx4_driver);
2478 destroy_workqueue(mlx4_wq);
2481 module_init(mlx4_init);
2482 module_exit(mlx4_cleanup);