2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/mlx4/cmd.h>
36 #include <linux/module.h>
37 #include <linux/cache.h>
43 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
44 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
45 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
48 extern void __buggy_use_of_MLX4_GET(void);
49 extern void __buggy_use_of_MLX4_PUT(void);
51 static int enable_qos;
52 module_param(enable_qos, bool, 0444);
53 MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
55 #define MLX4_GET(dest, source, offset) \
57 void *__p = (char *) (source) + (offset); \
58 switch (sizeof (dest)) { \
59 case 1: (dest) = *(u8 *) __p; break; \
60 case 2: (dest) = be16_to_cpup(__p); break; \
61 case 4: (dest) = be32_to_cpup(__p); break; \
62 case 8: (dest) = be64_to_cpup(__p); break; \
63 default: __buggy_use_of_MLX4_GET(); \
67 #define MLX4_PUT(dest, source, offset) \
69 void *__d = ((char *) (dest) + (offset)); \
70 switch (sizeof(source)) { \
71 case 1: *(u8 *) __d = (source); break; \
72 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
73 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
74 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
75 default: __buggy_use_of_MLX4_PUT(); \
79 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
81 static const char *fname[] = {
82 [ 0] = "RC transport",
83 [ 1] = "UC transport",
84 [ 2] = "UD transport",
85 [ 3] = "XRC transport",
86 [ 4] = "reliable multicast",
87 [ 5] = "FCoIB support",
89 [ 7] = "IPoIB checksum offload",
90 [ 8] = "P_Key violation counter",
91 [ 9] = "Q_Key violation counter",
94 [15] = "Big LSO headers",
97 [18] = "Atomic ops support",
98 [19] = "Raw multicast support",
99 [20] = "Address vector port checking support",
100 [21] = "UD multicast support",
101 [24] = "Demand paging support",
102 [25] = "Router support",
103 [30] = "IBoE support",
104 [32] = "Unicast loopback support",
105 [34] = "FCS header control",
106 [38] = "Wake On LAN support",
107 [40] = "UDP RSS support",
108 [41] = "Unicast VEP steering support",
109 [42] = "Multicast VEP steering support",
110 [48] = "Counters support",
114 mlx4_dbg(dev, "DEV_CAP flags:\n");
115 for (i = 0; i < ARRAY_SIZE(fname); ++i)
116 if (fname[i] && (flags & (1LL << i)))
117 mlx4_dbg(dev, " %s\n", fname[i]);
120 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
122 struct mlx4_cmd_mailbox *mailbox;
126 #define MOD_STAT_CFG_IN_SIZE 0x100
128 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
129 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
131 mailbox = mlx4_alloc_cmd_mailbox(dev);
133 return PTR_ERR(mailbox);
134 inbox = mailbox->buf;
136 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
138 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
139 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
141 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
142 MLX4_CMD_TIME_CLASS_A);
144 mlx4_free_cmd_mailbox(dev, mailbox);
148 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
150 struct mlx4_cmd_mailbox *mailbox;
153 u32 field32, flags, ext_flags;
159 #define QUERY_DEV_CAP_OUT_SIZE 0x100
160 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
161 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
162 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
163 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
164 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
165 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
166 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
167 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
168 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
169 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
170 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
171 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
172 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
173 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
174 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
175 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
176 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
177 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
178 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
179 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
180 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
181 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
182 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
183 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
184 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
185 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
186 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
187 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
188 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
189 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
190 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
191 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
192 #define QUERY_DEV_CAP_WOL_OFFSET 0x43
193 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
194 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
195 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
196 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
197 #define QUERY_DEV_CAP_BF_OFFSET 0x4c
198 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
199 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
200 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
201 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
202 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
203 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
204 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
205 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
206 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
207 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
208 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
209 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
210 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
211 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
212 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
213 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
214 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
215 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
216 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
217 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
218 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
219 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
220 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
221 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
222 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
223 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
224 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
225 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
227 mailbox = mlx4_alloc_cmd_mailbox(dev);
229 return PTR_ERR(mailbox);
230 outbox = mailbox->buf;
232 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
233 MLX4_CMD_TIME_CLASS_A);
237 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
238 dev_cap->reserved_qps = 1 << (field & 0xf);
239 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
240 dev_cap->max_qps = 1 << (field & 0x1f);
241 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
242 dev_cap->reserved_srqs = 1 << (field >> 4);
243 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
244 dev_cap->max_srqs = 1 << (field & 0x1f);
245 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
246 dev_cap->max_cq_sz = 1 << field;
247 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
248 dev_cap->reserved_cqs = 1 << (field & 0xf);
249 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
250 dev_cap->max_cqs = 1 << (field & 0x1f);
251 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
252 dev_cap->max_mpts = 1 << (field & 0x3f);
253 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
254 dev_cap->reserved_eqs = field & 0xf;
255 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
256 dev_cap->max_eqs = 1 << (field & 0xf);
257 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
258 dev_cap->reserved_mtts = 1 << (field >> 4);
259 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
260 dev_cap->max_mrw_sz = 1 << field;
261 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
262 dev_cap->reserved_mrws = 1 << (field & 0xf);
263 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
264 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
265 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
266 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
267 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
268 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
269 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
272 dev_cap->max_gso_sz = 0;
274 dev_cap->max_gso_sz = 1 << field;
276 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
277 dev_cap->max_rdma_global = 1 << (field & 0x3f);
278 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
279 dev_cap->local_ca_ack_delay = field & 0x1f;
280 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
281 dev_cap->num_ports = field & 0xf;
282 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
283 dev_cap->max_msg_sz = 1 << (field & 0x1f);
284 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
285 dev_cap->stat_rate_support = stat_rate;
286 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
287 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
288 dev_cap->flags = flags | (u64)ext_flags << 32;
289 MLX4_GET(field, outbox, QUERY_DEV_CAP_WOL_OFFSET);
290 dev_cap->wol_port[1] = !!(field & 0x20);
291 dev_cap->wol_port[2] = !!(field & 0x40);
292 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
293 dev_cap->reserved_uars = field >> 4;
294 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
295 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
296 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
297 dev_cap->min_page_sz = 1 << field;
299 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
301 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
302 dev_cap->bf_reg_size = 1 << (field & 0x1f);
303 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
304 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
306 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
307 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
308 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
310 dev_cap->bf_reg_size = 0;
311 mlx4_dbg(dev, "BlueFlame not available\n");
314 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
315 dev_cap->max_sq_sg = field;
316 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
317 dev_cap->max_sq_desc_sz = size;
319 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
320 dev_cap->max_qp_per_mcg = 1 << field;
321 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
322 dev_cap->reserved_mgms = field & 0xf;
323 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
324 dev_cap->max_mcgs = 1 << field;
325 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
326 dev_cap->reserved_pds = field >> 4;
327 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
328 dev_cap->max_pds = 1 << (field & 0x3f);
329 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
330 dev_cap->reserved_xrcds = field >> 4;
331 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
332 dev_cap->max_xrcds = 1 << (field & 0x1f);
334 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
335 dev_cap->rdmarc_entry_sz = size;
336 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
337 dev_cap->qpc_entry_sz = size;
338 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
339 dev_cap->aux_entry_sz = size;
340 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
341 dev_cap->altc_entry_sz = size;
342 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
343 dev_cap->eqc_entry_sz = size;
344 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
345 dev_cap->cqc_entry_sz = size;
346 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
347 dev_cap->srq_entry_sz = size;
348 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
349 dev_cap->cmpt_entry_sz = size;
350 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
351 dev_cap->mtt_entry_sz = size;
352 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
353 dev_cap->dmpt_entry_sz = size;
355 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
356 dev_cap->max_srq_sz = 1 << field;
357 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
358 dev_cap->max_qp_sz = 1 << field;
359 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
360 dev_cap->resize_srq = field & 1;
361 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
362 dev_cap->max_rq_sg = field;
363 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
364 dev_cap->max_rq_desc_sz = size;
366 MLX4_GET(dev_cap->bmme_flags, outbox,
367 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
368 MLX4_GET(dev_cap->reserved_lkey, outbox,
369 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
370 MLX4_GET(dev_cap->max_icm_sz, outbox,
371 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
372 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
373 MLX4_GET(dev_cap->max_counters, outbox,
374 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
376 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
377 for (i = 1; i <= dev_cap->num_ports; ++i) {
378 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
379 dev_cap->max_vl[i] = field >> 4;
380 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
381 dev_cap->ib_mtu[i] = field >> 4;
382 dev_cap->max_port_width[i] = field & 0xf;
383 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
384 dev_cap->max_gids[i] = 1 << (field & 0xf);
385 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
386 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
389 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
390 #define QUERY_PORT_MTU_OFFSET 0x01
391 #define QUERY_PORT_ETH_MTU_OFFSET 0x02
392 #define QUERY_PORT_WIDTH_OFFSET 0x06
393 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
394 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
395 #define QUERY_PORT_MAX_VL_OFFSET 0x0b
396 #define QUERY_PORT_MAC_OFFSET 0x10
397 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
398 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
399 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20
401 for (i = 1; i <= dev_cap->num_ports; ++i) {
402 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
403 MLX4_CMD_TIME_CLASS_B);
407 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
408 dev_cap->supported_port_types[i] = field & 3;
409 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
410 dev_cap->ib_mtu[i] = field & 0xf;
411 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
412 dev_cap->max_port_width[i] = field & 0xf;
413 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
414 dev_cap->max_gids[i] = 1 << (field >> 4);
415 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
416 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
417 dev_cap->max_vl[i] = field & 0xf;
418 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
419 dev_cap->log_max_macs[i] = field & 0xf;
420 dev_cap->log_max_vlans[i] = field >> 4;
421 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
422 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
423 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
424 dev_cap->trans_type[i] = field32 >> 24;
425 dev_cap->vendor_oui[i] = field32 & 0xffffff;
426 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
427 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
431 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
432 dev_cap->bmme_flags, dev_cap->reserved_lkey);
435 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
436 * we can't use any EQs whose doorbell falls on that page,
437 * even if the EQ itself isn't reserved.
439 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
440 dev_cap->reserved_eqs);
442 mlx4_dbg(dev, "Max ICM size %lld MB\n",
443 (unsigned long long) dev_cap->max_icm_sz >> 20);
444 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
445 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
446 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
447 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
448 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
449 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
450 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
451 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
452 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
453 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
454 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
455 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
456 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
457 dev_cap->max_pds, dev_cap->reserved_mgms);
458 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
459 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
460 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
461 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
462 dev_cap->max_port_width[1]);
463 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
464 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
465 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
466 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
467 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
468 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
470 dump_dev_cap_flags(dev, dev_cap->flags);
473 mlx4_free_cmd_mailbox(dev, mailbox);
477 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
479 struct mlx4_cmd_mailbox *mailbox;
480 struct mlx4_icm_iter iter;
488 mailbox = mlx4_alloc_cmd_mailbox(dev);
490 return PTR_ERR(mailbox);
491 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
492 pages = mailbox->buf;
494 for (mlx4_icm_first(icm, &iter);
495 !mlx4_icm_last(&iter);
496 mlx4_icm_next(&iter)) {
498 * We have to pass pages that are aligned to their
499 * size, so find the least significant 1 in the
500 * address or size and use that as our log2 size.
502 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
503 if (lg < MLX4_ICM_PAGE_SHIFT) {
504 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
506 (unsigned long long) mlx4_icm_addr(&iter),
507 mlx4_icm_size(&iter));
512 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
514 pages[nent * 2] = cpu_to_be64(virt);
518 pages[nent * 2 + 1] =
519 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
520 (lg - MLX4_ICM_PAGE_SHIFT));
521 ts += 1 << (lg - 10);
524 if (++nent == MLX4_MAILBOX_SIZE / 16) {
525 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
526 MLX4_CMD_TIME_CLASS_B);
535 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, MLX4_CMD_TIME_CLASS_B);
540 case MLX4_CMD_MAP_FA:
541 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
543 case MLX4_CMD_MAP_ICM_AUX:
544 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
546 case MLX4_CMD_MAP_ICM:
547 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
548 tc, ts, (unsigned long long) virt - (ts << 10));
553 mlx4_free_cmd_mailbox(dev, mailbox);
557 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
559 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
562 int mlx4_UNMAP_FA(struct mlx4_dev *dev)
564 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, MLX4_CMD_TIME_CLASS_B);
568 int mlx4_RUN_FW(struct mlx4_dev *dev)
570 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, MLX4_CMD_TIME_CLASS_A);
573 int mlx4_QUERY_FW(struct mlx4_dev *dev)
575 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
576 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
577 struct mlx4_cmd_mailbox *mailbox;
584 #define QUERY_FW_OUT_SIZE 0x100
585 #define QUERY_FW_VER_OFFSET 0x00
586 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
587 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
588 #define QUERY_FW_ERR_START_OFFSET 0x30
589 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
590 #define QUERY_FW_ERR_BAR_OFFSET 0x3c
592 #define QUERY_FW_SIZE_OFFSET 0x00
593 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
594 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
596 mailbox = mlx4_alloc_cmd_mailbox(dev);
598 return PTR_ERR(mailbox);
599 outbox = mailbox->buf;
601 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
602 MLX4_CMD_TIME_CLASS_A);
606 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
608 * FW subminor version is at more significant bits than minor
609 * version, so swap here.
611 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
612 ((fw_ver & 0xffff0000ull) >> 16) |
613 ((fw_ver & 0x0000ffffull) << 16);
615 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
616 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
617 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
618 mlx4_err(dev, "Installed FW has unsupported "
619 "command interface revision %d.\n",
621 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
622 (int) (dev->caps.fw_ver >> 32),
623 (int) (dev->caps.fw_ver >> 16) & 0xffff,
624 (int) dev->caps.fw_ver & 0xffff);
625 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
626 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
631 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
632 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
634 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
635 cmd->max_cmds = 1 << lg;
637 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
638 (int) (dev->caps.fw_ver >> 32),
639 (int) (dev->caps.fw_ver >> 16) & 0xffff,
640 (int) dev->caps.fw_ver & 0xffff,
641 cmd_if_rev, cmd->max_cmds);
643 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
644 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
645 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
646 fw->catas_bar = (fw->catas_bar >> 6) * 2;
648 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
649 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
651 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
652 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
653 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
654 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
656 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
659 * Round up number of system pages needed in case
660 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
663 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
664 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
666 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
667 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
670 mlx4_free_cmd_mailbox(dev, mailbox);
674 static void get_board_id(void *vsd, char *board_id)
678 #define VSD_OFFSET_SIG1 0x00
679 #define VSD_OFFSET_SIG2 0xde
680 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
681 #define VSD_OFFSET_TS_BOARD_ID 0x20
683 #define VSD_SIGNATURE_TOPSPIN 0x5ad
685 memset(board_id, 0, MLX4_BOARD_ID_LEN);
687 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
688 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
689 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
692 * The board ID is a string but the firmware byte
693 * swaps each 4-byte word before passing it back to
694 * us. Therefore we need to swab it before printing.
696 for (i = 0; i < 4; ++i)
697 ((u32 *) board_id)[i] =
698 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
702 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
704 struct mlx4_cmd_mailbox *mailbox;
708 #define QUERY_ADAPTER_OUT_SIZE 0x100
709 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
710 #define QUERY_ADAPTER_VSD_OFFSET 0x20
712 mailbox = mlx4_alloc_cmd_mailbox(dev);
714 return PTR_ERR(mailbox);
715 outbox = mailbox->buf;
717 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
718 MLX4_CMD_TIME_CLASS_A);
722 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
724 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
728 mlx4_free_cmd_mailbox(dev, mailbox);
732 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
734 struct mlx4_cmd_mailbox *mailbox;
738 #define INIT_HCA_IN_SIZE 0x200
739 #define INIT_HCA_VERSION_OFFSET 0x000
740 #define INIT_HCA_VERSION 2
741 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
742 #define INIT_HCA_FLAGS_OFFSET 0x014
743 #define INIT_HCA_QPC_OFFSET 0x020
744 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
745 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
746 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
747 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
748 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
749 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
750 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
751 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
752 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
753 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
754 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
755 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
756 #define INIT_HCA_MCAST_OFFSET 0x0c0
757 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
758 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
759 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
760 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
761 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
762 #define INIT_HCA_TPT_OFFSET 0x0f0
763 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
764 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
765 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
766 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
767 #define INIT_HCA_UAR_OFFSET 0x120
768 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
769 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
771 mailbox = mlx4_alloc_cmd_mailbox(dev);
773 return PTR_ERR(mailbox);
774 inbox = mailbox->buf;
776 memset(inbox, 0, INIT_HCA_IN_SIZE);
778 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
780 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
781 (ilog2(cache_line_size()) - 4) << 5;
783 #if defined(__LITTLE_ENDIAN)
784 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
785 #elif defined(__BIG_ENDIAN)
786 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
788 #error Host endianness not defined
790 /* Check port for UD address vector: */
791 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
793 /* Enable IPoIB checksumming if we can: */
794 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
795 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
797 /* Enable QoS support if module parameter set */
799 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
801 /* enable counters */
802 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
803 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
805 /* QPC/EEC/CQC/EQC/RDMARC attributes */
807 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
808 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
809 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
810 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
811 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
812 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
813 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
814 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
815 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
816 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
817 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
818 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
820 /* multicast attributes */
822 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
823 MLX4_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
824 MLX4_PUT(inbox, param->log_mc_hash_sz, INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
825 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
826 MLX4_PUT(inbox, (u8) (1 << 3), INIT_HCA_UC_STEERING_OFFSET);
827 MLX4_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
831 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
832 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
833 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
834 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
838 MLX4_PUT(inbox, (u8) (PAGE_SHIFT - 12), INIT_HCA_UAR_PAGE_SZ_OFFSET);
839 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
841 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000);
844 mlx4_err(dev, "INIT_HCA returns %d\n", err);
846 mlx4_free_cmd_mailbox(dev, mailbox);
850 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
852 struct mlx4_cmd_mailbox *mailbox;
858 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
859 #define INIT_PORT_IN_SIZE 256
860 #define INIT_PORT_FLAGS_OFFSET 0x00
861 #define INIT_PORT_FLAG_SIG (1 << 18)
862 #define INIT_PORT_FLAG_NG (1 << 17)
863 #define INIT_PORT_FLAG_G0 (1 << 16)
864 #define INIT_PORT_VL_SHIFT 4
865 #define INIT_PORT_PORT_WIDTH_SHIFT 8
866 #define INIT_PORT_MTU_OFFSET 0x04
867 #define INIT_PORT_MAX_GID_OFFSET 0x06
868 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
869 #define INIT_PORT_GUID0_OFFSET 0x10
870 #define INIT_PORT_NODE_GUID_OFFSET 0x18
871 #define INIT_PORT_SI_GUID_OFFSET 0x20
873 mailbox = mlx4_alloc_cmd_mailbox(dev);
875 return PTR_ERR(mailbox);
876 inbox = mailbox->buf;
878 memset(inbox, 0, INIT_PORT_IN_SIZE);
881 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
882 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
883 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
885 field = 128 << dev->caps.ib_mtu_cap[port];
886 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
887 field = dev->caps.gid_table_len[port];
888 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
889 field = dev->caps.pkey_table_len[port];
890 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
892 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
893 MLX4_CMD_TIME_CLASS_A);
895 mlx4_free_cmd_mailbox(dev, mailbox);
897 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
898 MLX4_CMD_TIME_CLASS_A);
902 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
904 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
906 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000);
908 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
910 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
912 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000);
915 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
917 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
918 MLX4_CMD_SET_ICM_SIZE,
919 MLX4_CMD_TIME_CLASS_A);
924 * Round up number of system pages needed in case
925 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
927 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
928 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
933 int mlx4_NOP(struct mlx4_dev *dev)
935 /* Input modifier of 0x1f means "finish as soon as possible." */
936 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100);
939 #define MLX4_WOL_SETUP_MODE (5 << 28)
940 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
942 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
944 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
945 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A);
947 EXPORT_SYMBOL_GPL(mlx4_wol_read);
949 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
951 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
953 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
954 MLX4_CMD_TIME_CLASS_A);
956 EXPORT_SYMBOL_GPL(mlx4_wol_write);