1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31 #include <linux/netdevice.h>
34 #include "ixgbe_common.h"
35 #include "ixgbe_phy.h"
37 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
38 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
39 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
40 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
41 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
42 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
44 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
45 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
46 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
49 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
50 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
51 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
52 u16 words, u16 *data);
53 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
54 u16 words, u16 *data);
55 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
57 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
60 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
62 * @hw: pointer to hardware structure
64 * There are several phys that do not support autoneg flow control. This
65 * function check the device id to see if the associated phy supports
66 * autoneg flow control.
68 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
70 bool supported = false;
71 ixgbe_link_speed speed;
74 switch (hw->phy.media_type) {
75 case ixgbe_media_type_fiber_fixed:
76 case ixgbe_media_type_fiber:
77 hw->mac.ops.check_link(hw, &speed, &link_up, false);
78 /* if link is down, assume supported */
80 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
85 case ixgbe_media_type_backplane:
88 case ixgbe_media_type_copper:
89 /* only some copper devices support flow control autoneg */
90 switch (hw->device_id) {
91 case IXGBE_DEV_ID_82599_T3_LOM:
92 case IXGBE_DEV_ID_X540T:
93 case IXGBE_DEV_ID_X540T1:
107 * ixgbe_setup_fc - Set up flow control
108 * @hw: pointer to hardware structure
110 * Called at init time to set up flow control.
112 static s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
115 u32 reg = 0, reg_bp = 0;
117 bool got_lock = false;
120 * Validate the requested mode. Strict IEEE mode does not allow
121 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
123 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
124 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
125 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
130 * 10gig parts do not have a word in the EEPROM to determine the
131 * default flow control setting, so we explicitly set it to full.
133 if (hw->fc.requested_mode == ixgbe_fc_default)
134 hw->fc.requested_mode = ixgbe_fc_full;
137 * Set up the 1G and 10G flow control advertisement registers so the
138 * HW will be able to do fc autoneg once the cable is plugged in. If
139 * we link at 10G, the 1G advertisement is harmless and vice versa.
141 switch (hw->phy.media_type) {
142 case ixgbe_media_type_fiber_fixed:
143 case ixgbe_media_type_fiber:
144 case ixgbe_media_type_backplane:
145 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
146 reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
148 case ixgbe_media_type_copper:
149 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
150 MDIO_MMD_AN, ®_cu);
157 * The possible values of fc.requested_mode are:
158 * 0: Flow control is completely disabled
159 * 1: Rx flow control is enabled (we can receive pause frames,
160 * but not send pause frames).
161 * 2: Tx flow control is enabled (we can send pause frames but
162 * we do not support receiving pause frames).
163 * 3: Both Rx and Tx flow control (symmetric) are enabled.
166 switch (hw->fc.requested_mode) {
168 /* Flow control completely disabled by software override. */
169 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
170 if (hw->phy.media_type == ixgbe_media_type_backplane)
171 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
172 IXGBE_AUTOC_ASM_PAUSE);
173 else if (hw->phy.media_type == ixgbe_media_type_copper)
174 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
176 case ixgbe_fc_tx_pause:
178 * Tx Flow control is enabled, and Rx Flow control is
179 * disabled by software override.
181 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
182 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
183 if (hw->phy.media_type == ixgbe_media_type_backplane) {
184 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
185 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
186 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
187 reg_cu |= IXGBE_TAF_ASM_PAUSE;
188 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
191 case ixgbe_fc_rx_pause:
193 * Rx Flow control is enabled and Tx Flow control is
194 * disabled by software override. Since there really
195 * isn't a way to advertise that we are capable of RX
196 * Pause ONLY, we will advertise that we support both
197 * symmetric and asymmetric Rx PAUSE, as such we fall
198 * through to the fc_full statement. Later, we will
199 * disable the adapter's ability to send PAUSE frames.
202 /* Flow control (both Rx and Tx) is enabled by SW override. */
203 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
204 if (hw->phy.media_type == ixgbe_media_type_backplane)
205 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
206 IXGBE_AUTOC_ASM_PAUSE;
207 else if (hw->phy.media_type == ixgbe_media_type_copper)
208 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
211 hw_dbg(hw, "Flow control param set incorrectly\n");
212 ret_val = IXGBE_ERR_CONFIG;
217 if (hw->mac.type != ixgbe_mac_X540) {
219 * Enable auto-negotiation between the MAC & PHY;
220 * the MAC will advertise clause 37 flow control.
222 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
223 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
225 /* Disable AN timeout */
226 if (hw->fc.strict_ieee)
227 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
229 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
230 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
234 * AUTOC restart handles negotiation of 1G and 10G on backplane
235 * and copper. There is no need to set the PCS1GCTL register.
238 if (hw->phy.media_type == ixgbe_media_type_backplane) {
239 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
240 * LESM is on, likewise reset_pipeline requries the lock as
241 * it also writes AUTOC.
243 if ((hw->mac.type == ixgbe_mac_82599EB) &&
244 ixgbe_verify_lesm_fw_enabled_82599(hw)) {
245 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
246 IXGBE_GSSR_MAC_CSR_SM);
253 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
255 if (hw->mac.type == ixgbe_mac_82599EB)
256 ixgbe_reset_pipeline_82599(hw);
259 hw->mac.ops.release_swfw_sync(hw,
260 IXGBE_GSSR_MAC_CSR_SM);
262 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
263 ixgbe_device_supports_autoneg_fc(hw)) {
264 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
265 MDIO_MMD_AN, reg_cu);
268 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
274 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
275 * @hw: pointer to hardware structure
277 * Starts the hardware by filling the bus info structure and media type, clears
278 * all on chip counters, initializes receive address registers, multicast
279 * table, VLAN filter table, calls routine to set up link and flow control
280 * settings, and leaves transmit and receive units disabled and uninitialized
282 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
286 /* Set the media type */
287 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
289 /* Identify the PHY */
290 hw->phy.ops.identify(hw);
292 /* Clear the VLAN filter table */
293 hw->mac.ops.clear_vfta(hw);
295 /* Clear statistics registers */
296 hw->mac.ops.clear_hw_cntrs(hw);
298 /* Set No Snoop Disable */
299 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
300 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
301 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
302 IXGBE_WRITE_FLUSH(hw);
304 /* Setup flow control */
307 /* Clear adapter stopped flag */
308 hw->adapter_stopped = false;
314 * ixgbe_start_hw_gen2 - Init sequence for common device family
315 * @hw: pointer to hw structure
317 * Performs the init sequence common to the second generation
319 * Devices in the second generation:
323 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
328 /* Clear the rate limiters */
329 for (i = 0; i < hw->mac.max_tx_queues; i++) {
330 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
331 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
333 IXGBE_WRITE_FLUSH(hw);
335 /* Disable relaxed ordering */
336 for (i = 0; i < hw->mac.max_tx_queues; i++) {
337 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
338 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
339 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
342 for (i = 0; i < hw->mac.max_rx_queues; i++) {
343 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
344 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
345 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
346 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
353 * ixgbe_init_hw_generic - Generic hardware initialization
354 * @hw: pointer to hardware structure
356 * Initialize the hardware by resetting the hardware, filling the bus info
357 * structure and media type, clears all on chip counters, initializes receive
358 * address registers, multicast table, VLAN filter table, calls routine to set
359 * up link and flow control settings, and leaves transmit and receive units
360 * disabled and uninitialized
362 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
366 /* Reset the hardware */
367 status = hw->mac.ops.reset_hw(hw);
371 status = hw->mac.ops.start_hw(hw);
378 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
379 * @hw: pointer to hardware structure
381 * Clears all hardware statistics counters by reading them from the hardware
382 * Statistics counters are clear on read.
384 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
388 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
389 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
390 IXGBE_READ_REG(hw, IXGBE_ERRBC);
391 IXGBE_READ_REG(hw, IXGBE_MSPDC);
392 for (i = 0; i < 8; i++)
393 IXGBE_READ_REG(hw, IXGBE_MPC(i));
395 IXGBE_READ_REG(hw, IXGBE_MLFC);
396 IXGBE_READ_REG(hw, IXGBE_MRFC);
397 IXGBE_READ_REG(hw, IXGBE_RLEC);
398 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
399 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
400 if (hw->mac.type >= ixgbe_mac_82599EB) {
401 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
402 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
404 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
405 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
408 for (i = 0; i < 8; i++) {
409 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
410 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
411 if (hw->mac.type >= ixgbe_mac_82599EB) {
412 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
413 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
415 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
416 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
419 if (hw->mac.type >= ixgbe_mac_82599EB)
420 for (i = 0; i < 8; i++)
421 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
422 IXGBE_READ_REG(hw, IXGBE_PRC64);
423 IXGBE_READ_REG(hw, IXGBE_PRC127);
424 IXGBE_READ_REG(hw, IXGBE_PRC255);
425 IXGBE_READ_REG(hw, IXGBE_PRC511);
426 IXGBE_READ_REG(hw, IXGBE_PRC1023);
427 IXGBE_READ_REG(hw, IXGBE_PRC1522);
428 IXGBE_READ_REG(hw, IXGBE_GPRC);
429 IXGBE_READ_REG(hw, IXGBE_BPRC);
430 IXGBE_READ_REG(hw, IXGBE_MPRC);
431 IXGBE_READ_REG(hw, IXGBE_GPTC);
432 IXGBE_READ_REG(hw, IXGBE_GORCL);
433 IXGBE_READ_REG(hw, IXGBE_GORCH);
434 IXGBE_READ_REG(hw, IXGBE_GOTCL);
435 IXGBE_READ_REG(hw, IXGBE_GOTCH);
436 if (hw->mac.type == ixgbe_mac_82598EB)
437 for (i = 0; i < 8; i++)
438 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
439 IXGBE_READ_REG(hw, IXGBE_RUC);
440 IXGBE_READ_REG(hw, IXGBE_RFC);
441 IXGBE_READ_REG(hw, IXGBE_ROC);
442 IXGBE_READ_REG(hw, IXGBE_RJC);
443 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
444 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
445 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
446 IXGBE_READ_REG(hw, IXGBE_TORL);
447 IXGBE_READ_REG(hw, IXGBE_TORH);
448 IXGBE_READ_REG(hw, IXGBE_TPR);
449 IXGBE_READ_REG(hw, IXGBE_TPT);
450 IXGBE_READ_REG(hw, IXGBE_PTC64);
451 IXGBE_READ_REG(hw, IXGBE_PTC127);
452 IXGBE_READ_REG(hw, IXGBE_PTC255);
453 IXGBE_READ_REG(hw, IXGBE_PTC511);
454 IXGBE_READ_REG(hw, IXGBE_PTC1023);
455 IXGBE_READ_REG(hw, IXGBE_PTC1522);
456 IXGBE_READ_REG(hw, IXGBE_MPTC);
457 IXGBE_READ_REG(hw, IXGBE_BPTC);
458 for (i = 0; i < 16; i++) {
459 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
460 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
461 if (hw->mac.type >= ixgbe_mac_82599EB) {
462 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
463 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
464 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
465 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
466 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
468 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
469 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
473 if (hw->mac.type == ixgbe_mac_X540) {
475 hw->phy.ops.identify(hw);
476 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i);
477 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i);
478 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i);
479 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i);
486 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
487 * @hw: pointer to hardware structure
488 * @pba_num: stores the part number string from the EEPROM
489 * @pba_num_size: part number string buffer length
491 * Reads the part number string from the EEPROM.
493 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
502 if (pba_num == NULL) {
503 hw_dbg(hw, "PBA string buffer was null\n");
504 return IXGBE_ERR_INVALID_ARGUMENT;
507 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
509 hw_dbg(hw, "NVM Read Error\n");
513 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
515 hw_dbg(hw, "NVM Read Error\n");
520 * if data is not ptr guard the PBA must be in legacy format which
521 * means pba_ptr is actually our second data word for the PBA number
522 * and we can decode it into an ascii string
524 if (data != IXGBE_PBANUM_PTR_GUARD) {
525 hw_dbg(hw, "NVM PBA number is not stored as string\n");
527 /* we will need 11 characters to store the PBA */
528 if (pba_num_size < 11) {
529 hw_dbg(hw, "PBA string buffer too small\n");
530 return IXGBE_ERR_NO_SPACE;
533 /* extract hex string from data and pba_ptr */
534 pba_num[0] = (data >> 12) & 0xF;
535 pba_num[1] = (data >> 8) & 0xF;
536 pba_num[2] = (data >> 4) & 0xF;
537 pba_num[3] = data & 0xF;
538 pba_num[4] = (pba_ptr >> 12) & 0xF;
539 pba_num[5] = (pba_ptr >> 8) & 0xF;
542 pba_num[8] = (pba_ptr >> 4) & 0xF;
543 pba_num[9] = pba_ptr & 0xF;
545 /* put a null character on the end of our string */
548 /* switch all the data but the '-' to hex char */
549 for (offset = 0; offset < 10; offset++) {
550 if (pba_num[offset] < 0xA)
551 pba_num[offset] += '0';
552 else if (pba_num[offset] < 0x10)
553 pba_num[offset] += 'A' - 0xA;
559 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
561 hw_dbg(hw, "NVM Read Error\n");
565 if (length == 0xFFFF || length == 0) {
566 hw_dbg(hw, "NVM PBA number section invalid length\n");
567 return IXGBE_ERR_PBA_SECTION;
570 /* check if pba_num buffer is big enough */
571 if (pba_num_size < (((u32)length * 2) - 1)) {
572 hw_dbg(hw, "PBA string buffer too small\n");
573 return IXGBE_ERR_NO_SPACE;
576 /* trim pba length from start of string */
580 for (offset = 0; offset < length; offset++) {
581 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
583 hw_dbg(hw, "NVM Read Error\n");
586 pba_num[offset * 2] = (u8)(data >> 8);
587 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
589 pba_num[offset * 2] = '\0';
595 * ixgbe_get_mac_addr_generic - Generic get MAC address
596 * @hw: pointer to hardware structure
597 * @mac_addr: Adapter MAC address
599 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
600 * A reset of the adapter must be performed prior to calling this function
601 * in order for the MAC address to have been loaded from the EEPROM into RAR0
603 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
609 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
610 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
612 for (i = 0; i < 4; i++)
613 mac_addr[i] = (u8)(rar_low >> (i*8));
615 for (i = 0; i < 2; i++)
616 mac_addr[i+4] = (u8)(rar_high >> (i*8));
621 enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status)
623 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
624 case IXGBE_PCI_LINK_WIDTH_1:
625 return ixgbe_bus_width_pcie_x1;
626 case IXGBE_PCI_LINK_WIDTH_2:
627 return ixgbe_bus_width_pcie_x2;
628 case IXGBE_PCI_LINK_WIDTH_4:
629 return ixgbe_bus_width_pcie_x4;
630 case IXGBE_PCI_LINK_WIDTH_8:
631 return ixgbe_bus_width_pcie_x8;
633 return ixgbe_bus_width_unknown;
637 enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status)
639 switch (link_status & IXGBE_PCI_LINK_SPEED) {
640 case IXGBE_PCI_LINK_SPEED_2500:
641 return ixgbe_bus_speed_2500;
642 case IXGBE_PCI_LINK_SPEED_5000:
643 return ixgbe_bus_speed_5000;
644 case IXGBE_PCI_LINK_SPEED_8000:
645 return ixgbe_bus_speed_8000;
647 return ixgbe_bus_speed_unknown;
652 * ixgbe_get_bus_info_generic - Generic set PCI bus info
653 * @hw: pointer to hardware structure
655 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
657 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
659 struct ixgbe_adapter *adapter = hw->back;
660 struct ixgbe_mac_info *mac = &hw->mac;
663 hw->bus.type = ixgbe_bus_type_pci_express;
665 /* Get the negotiated link width and speed from PCI config space */
666 pci_read_config_word(adapter->pdev, IXGBE_PCI_LINK_STATUS,
669 hw->bus.width = ixgbe_convert_bus_width(link_status);
670 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
672 mac->ops.set_lan_id(hw);
678 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
679 * @hw: pointer to the HW structure
681 * Determines the LAN function id by reading memory-mapped registers
682 * and swaps the port value if requested.
684 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
686 struct ixgbe_bus_info *bus = &hw->bus;
689 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
690 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
691 bus->lan_id = bus->func;
693 /* check for a port swap */
694 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
695 if (reg & IXGBE_FACTPS_LFS)
700 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
701 * @hw: pointer to hardware structure
703 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
704 * disables transmit and receive units. The adapter_stopped flag is used by
705 * the shared code and drivers to determine if the adapter is in a stopped
706 * state and should not touch the hardware.
708 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
714 * Set the adapter_stopped flag so other driver functions stop touching
717 hw->adapter_stopped = true;
719 /* Disable the receive unit */
720 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0);
722 /* Clear interrupt mask to stop interrupts from being generated */
723 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
725 /* Clear any pending interrupts, flush previous writes */
726 IXGBE_READ_REG(hw, IXGBE_EICR);
728 /* Disable the transmit unit. Each queue must be disabled. */
729 for (i = 0; i < hw->mac.max_tx_queues; i++)
730 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
732 /* Disable the receive unit by stopping each queue */
733 for (i = 0; i < hw->mac.max_rx_queues; i++) {
734 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
735 reg_val &= ~IXGBE_RXDCTL_ENABLE;
736 reg_val |= IXGBE_RXDCTL_SWFLSH;
737 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
740 /* flush all queues disables */
741 IXGBE_WRITE_FLUSH(hw);
742 usleep_range(1000, 2000);
745 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
746 * access and verify no pending requests
748 return ixgbe_disable_pcie_master(hw);
752 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
753 * @hw: pointer to hardware structure
754 * @index: led number to turn on
756 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
758 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
760 /* To turn on the LED, set mode to ON. */
761 led_reg &= ~IXGBE_LED_MODE_MASK(index);
762 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
763 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
764 IXGBE_WRITE_FLUSH(hw);
770 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
771 * @hw: pointer to hardware structure
772 * @index: led number to turn off
774 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
776 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
778 /* To turn off the LED, set mode to OFF. */
779 led_reg &= ~IXGBE_LED_MODE_MASK(index);
780 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
781 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
782 IXGBE_WRITE_FLUSH(hw);
788 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
789 * @hw: pointer to hardware structure
791 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
792 * ixgbe_hw struct in order to set up EEPROM access.
794 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
796 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
800 if (eeprom->type == ixgbe_eeprom_uninitialized) {
801 eeprom->type = ixgbe_eeprom_none;
802 /* Set default semaphore delay to 10ms which is a well
804 eeprom->semaphore_delay = 10;
805 /* Clear EEPROM page size, it will be initialized as needed */
806 eeprom->word_page_size = 0;
809 * Check for EEPROM present first.
810 * If not present leave as none
812 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
813 if (eec & IXGBE_EEC_PRES) {
814 eeprom->type = ixgbe_eeprom_spi;
817 * SPI EEPROM is assumed here. This code would need to
818 * change if a future EEPROM is not SPI.
820 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
821 IXGBE_EEC_SIZE_SHIFT);
822 eeprom->word_size = 1 << (eeprom_size +
823 IXGBE_EEPROM_WORD_SIZE_SHIFT);
826 if (eec & IXGBE_EEC_ADDR_SIZE)
827 eeprom->address_bits = 16;
829 eeprom->address_bits = 8;
830 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
831 "%d\n", eeprom->type, eeprom->word_size,
832 eeprom->address_bits);
839 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
840 * @hw: pointer to hardware structure
841 * @offset: offset within the EEPROM to write
842 * @words: number of words
843 * @data: 16 bit word(s) to write to EEPROM
845 * Reads 16 bit word(s) from EEPROM through bit-bang method
847 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
848 u16 words, u16 *data)
853 hw->eeprom.ops.init_params(hw);
856 status = IXGBE_ERR_INVALID_ARGUMENT;
860 if (offset + words > hw->eeprom.word_size) {
861 status = IXGBE_ERR_EEPROM;
866 * The EEPROM page size cannot be queried from the chip. We do lazy
867 * initialization. It is worth to do that when we write large buffer.
869 if ((hw->eeprom.word_page_size == 0) &&
870 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
871 ixgbe_detect_eeprom_page_size_generic(hw, offset);
874 * We cannot hold synchronization semaphores for too long
875 * to avoid other entity starvation. However it is more efficient
876 * to read in bursts than synchronizing access for each word.
878 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
879 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
880 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
881 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
893 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
894 * @hw: pointer to hardware structure
895 * @offset: offset within the EEPROM to be written to
896 * @words: number of word(s)
897 * @data: 16 bit word(s) to be written to the EEPROM
899 * If ixgbe_eeprom_update_checksum is not called after this function, the
900 * EEPROM will most likely contain an invalid checksum.
902 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
903 u16 words, u16 *data)
909 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
911 /* Prepare the EEPROM for writing */
912 status = ixgbe_acquire_eeprom(hw);
915 if (ixgbe_ready_eeprom(hw) != 0) {
916 ixgbe_release_eeprom(hw);
917 status = IXGBE_ERR_EEPROM;
922 for (i = 0; i < words; i++) {
923 ixgbe_standby_eeprom(hw);
925 /* Send the WRITE ENABLE command (8 bit opcode ) */
926 ixgbe_shift_out_eeprom_bits(hw,
927 IXGBE_EEPROM_WREN_OPCODE_SPI,
928 IXGBE_EEPROM_OPCODE_BITS);
930 ixgbe_standby_eeprom(hw);
933 * Some SPI eeproms use the 8th address bit embedded
936 if ((hw->eeprom.address_bits == 8) &&
937 ((offset + i) >= 128))
938 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
940 /* Send the Write command (8-bit opcode + addr) */
941 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
942 IXGBE_EEPROM_OPCODE_BITS);
943 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
944 hw->eeprom.address_bits);
946 page_size = hw->eeprom.word_page_size;
948 /* Send the data in burst via SPI*/
951 word = (word >> 8) | (word << 8);
952 ixgbe_shift_out_eeprom_bits(hw, word, 16);
957 /* do not wrap around page */
958 if (((offset + i) & (page_size - 1)) ==
961 } while (++i < words);
963 ixgbe_standby_eeprom(hw);
964 usleep_range(10000, 20000);
966 /* Done with writing - release the EEPROM */
967 ixgbe_release_eeprom(hw);
974 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
975 * @hw: pointer to hardware structure
976 * @offset: offset within the EEPROM to be written to
977 * @data: 16 bit word to be written to the EEPROM
979 * If ixgbe_eeprom_update_checksum is not called after this function, the
980 * EEPROM will most likely contain an invalid checksum.
982 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
986 hw->eeprom.ops.init_params(hw);
988 if (offset >= hw->eeprom.word_size) {
989 status = IXGBE_ERR_EEPROM;
993 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1000 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1001 * @hw: pointer to hardware structure
1002 * @offset: offset within the EEPROM to be read
1003 * @words: number of word(s)
1004 * @data: read 16 bit words(s) from EEPROM
1006 * Reads 16 bit word(s) from EEPROM through bit-bang method
1008 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1009 u16 words, u16 *data)
1014 hw->eeprom.ops.init_params(hw);
1017 status = IXGBE_ERR_INVALID_ARGUMENT;
1021 if (offset + words > hw->eeprom.word_size) {
1022 status = IXGBE_ERR_EEPROM;
1027 * We cannot hold synchronization semaphores for too long
1028 * to avoid other entity starvation. However it is more efficient
1029 * to read in bursts than synchronizing access for each word.
1031 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1032 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1033 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1035 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1047 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1048 * @hw: pointer to hardware structure
1049 * @offset: offset within the EEPROM to be read
1050 * @words: number of word(s)
1051 * @data: read 16 bit word(s) from EEPROM
1053 * Reads 16 bit word(s) from EEPROM through bit-bang method
1055 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1056 u16 words, u16 *data)
1060 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1063 /* Prepare the EEPROM for reading */
1064 status = ixgbe_acquire_eeprom(hw);
1067 if (ixgbe_ready_eeprom(hw) != 0) {
1068 ixgbe_release_eeprom(hw);
1069 status = IXGBE_ERR_EEPROM;
1074 for (i = 0; i < words; i++) {
1075 ixgbe_standby_eeprom(hw);
1077 * Some SPI eeproms use the 8th address bit embedded
1080 if ((hw->eeprom.address_bits == 8) &&
1081 ((offset + i) >= 128))
1082 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1084 /* Send the READ command (opcode + addr) */
1085 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1086 IXGBE_EEPROM_OPCODE_BITS);
1087 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1088 hw->eeprom.address_bits);
1090 /* Read the data. */
1091 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1092 data[i] = (word_in >> 8) | (word_in << 8);
1095 /* End this read operation */
1096 ixgbe_release_eeprom(hw);
1103 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1104 * @hw: pointer to hardware structure
1105 * @offset: offset within the EEPROM to be read
1106 * @data: read 16 bit value from EEPROM
1108 * Reads 16 bit value from EEPROM through bit-bang method
1110 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1115 hw->eeprom.ops.init_params(hw);
1117 if (offset >= hw->eeprom.word_size) {
1118 status = IXGBE_ERR_EEPROM;
1122 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1129 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1130 * @hw: pointer to hardware structure
1131 * @offset: offset of word in the EEPROM to read
1132 * @words: number of word(s)
1133 * @data: 16 bit word(s) from the EEPROM
1135 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1137 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1138 u16 words, u16 *data)
1144 hw->eeprom.ops.init_params(hw);
1147 status = IXGBE_ERR_INVALID_ARGUMENT;
1151 if (offset >= hw->eeprom.word_size) {
1152 status = IXGBE_ERR_EEPROM;
1156 for (i = 0; i < words; i++) {
1157 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1158 IXGBE_EEPROM_RW_REG_START;
1160 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1161 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1164 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1165 IXGBE_EEPROM_RW_REG_DATA);
1167 hw_dbg(hw, "Eeprom read timed out\n");
1176 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1177 * @hw: pointer to hardware structure
1178 * @offset: offset within the EEPROM to be used as a scratch pad
1180 * Discover EEPROM page size by writing marching data at given offset.
1181 * This function is called only when we are writing a new large buffer
1182 * at given offset so the data would be overwritten anyway.
1184 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1187 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1191 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1194 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1195 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1196 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1197 hw->eeprom.word_page_size = 0;
1201 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1206 * When writing in burst more than the actual page size
1207 * EEPROM address wraps around current page.
1209 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1211 hw_dbg(hw, "Detected EEPROM page size = %d words.",
1212 hw->eeprom.word_page_size);
1218 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1219 * @hw: pointer to hardware structure
1220 * @offset: offset of word in the EEPROM to read
1221 * @data: word read from the EEPROM
1223 * Reads a 16 bit word from the EEPROM using the EERD register.
1225 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1227 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1231 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1232 * @hw: pointer to hardware structure
1233 * @offset: offset of word in the EEPROM to write
1234 * @words: number of words
1235 * @data: word(s) write to the EEPROM
1237 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1239 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1240 u16 words, u16 *data)
1246 hw->eeprom.ops.init_params(hw);
1249 status = IXGBE_ERR_INVALID_ARGUMENT;
1253 if (offset >= hw->eeprom.word_size) {
1254 status = IXGBE_ERR_EEPROM;
1258 for (i = 0; i < words; i++) {
1259 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1260 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1261 IXGBE_EEPROM_RW_REG_START;
1263 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1265 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1269 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1271 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1273 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1283 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1284 * @hw: pointer to hardware structure
1285 * @offset: offset of word in the EEPROM to write
1286 * @data: word write to the EEPROM
1288 * Write a 16 bit word to the EEPROM using the EEWR register.
1290 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1292 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1296 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1297 * @hw: pointer to hardware structure
1298 * @ee_reg: EEPROM flag for polling
1300 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1301 * read or write is done respectively.
1303 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1307 s32 status = IXGBE_ERR_EEPROM;
1309 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1310 if (ee_reg == IXGBE_NVM_POLL_READ)
1311 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1313 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1315 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1325 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1326 * @hw: pointer to hardware structure
1328 * Prepares EEPROM for access using bit-bang method. This function should
1329 * be called before issuing a command to the EEPROM.
1331 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1337 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
1338 status = IXGBE_ERR_SWFW_SYNC;
1341 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1343 /* Request EEPROM Access */
1344 eec |= IXGBE_EEC_REQ;
1345 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1347 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1348 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1349 if (eec & IXGBE_EEC_GNT)
1354 /* Release if grant not acquired */
1355 if (!(eec & IXGBE_EEC_GNT)) {
1356 eec &= ~IXGBE_EEC_REQ;
1357 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1358 hw_dbg(hw, "Could not acquire EEPROM grant\n");
1360 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1361 status = IXGBE_ERR_EEPROM;
1364 /* Setup EEPROM for Read/Write */
1366 /* Clear CS and SK */
1367 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1368 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1369 IXGBE_WRITE_FLUSH(hw);
1377 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1378 * @hw: pointer to hardware structure
1380 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1382 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1384 s32 status = IXGBE_ERR_EEPROM;
1389 /* Get SMBI software semaphore between device drivers first */
1390 for (i = 0; i < timeout; i++) {
1392 * If the SMBI bit is 0 when we read it, then the bit will be
1393 * set and we have the semaphore
1395 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1396 if (!(swsm & IXGBE_SWSM_SMBI)) {
1404 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore "
1407 * this release is particularly important because our attempts
1408 * above to get the semaphore may have succeeded, and if there
1409 * was a timeout, we should unconditionally clear the semaphore
1410 * bits to free the driver to make progress
1412 ixgbe_release_eeprom_semaphore(hw);
1417 * If the SMBI bit is 0 when we read it, then the bit will be
1418 * set and we have the semaphore
1420 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1421 if (!(swsm & IXGBE_SWSM_SMBI))
1425 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1427 for (i = 0; i < timeout; i++) {
1428 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1430 /* Set the SW EEPROM semaphore bit to request access */
1431 swsm |= IXGBE_SWSM_SWESMBI;
1432 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1435 * If we set the bit successfully then we got the
1438 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1439 if (swsm & IXGBE_SWSM_SWESMBI)
1446 * Release semaphores and return error if SW EEPROM semaphore
1447 * was not granted because we don't have access to the EEPROM
1450 hw_dbg(hw, "SWESMBI Software EEPROM semaphore "
1452 ixgbe_release_eeprom_semaphore(hw);
1453 status = IXGBE_ERR_EEPROM;
1456 hw_dbg(hw, "Software semaphore SMBI between device drivers "
1464 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1465 * @hw: pointer to hardware structure
1467 * This function clears hardware semaphore bits.
1469 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1473 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1475 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1476 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1477 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1478 IXGBE_WRITE_FLUSH(hw);
1482 * ixgbe_ready_eeprom - Polls for EEPROM ready
1483 * @hw: pointer to hardware structure
1485 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1492 * Read "Status Register" repeatedly until the LSB is cleared. The
1493 * EEPROM will signal that the command has been completed by clearing
1494 * bit 0 of the internal status register. If it's not cleared within
1495 * 5 milliseconds, then error out.
1497 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1498 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1499 IXGBE_EEPROM_OPCODE_BITS);
1500 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1501 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1505 ixgbe_standby_eeprom(hw);
1509 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1510 * devices (and only 0-5mSec on 5V devices)
1512 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1513 hw_dbg(hw, "SPI EEPROM Status error\n");
1514 status = IXGBE_ERR_EEPROM;
1521 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1522 * @hw: pointer to hardware structure
1524 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1528 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1530 /* Toggle CS to flush commands */
1531 eec |= IXGBE_EEC_CS;
1532 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1533 IXGBE_WRITE_FLUSH(hw);
1535 eec &= ~IXGBE_EEC_CS;
1536 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1537 IXGBE_WRITE_FLUSH(hw);
1542 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1543 * @hw: pointer to hardware structure
1544 * @data: data to send to the EEPROM
1545 * @count: number of bits to shift out
1547 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1554 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1557 * Mask is used to shift "count" bits of "data" out to the EEPROM
1558 * one bit at a time. Determine the starting bit based on count
1560 mask = 0x01 << (count - 1);
1562 for (i = 0; i < count; i++) {
1564 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1565 * "1", and then raising and then lowering the clock (the SK
1566 * bit controls the clock input to the EEPROM). A "0" is
1567 * shifted out to the EEPROM by setting "DI" to "0" and then
1568 * raising and then lowering the clock.
1571 eec |= IXGBE_EEC_DI;
1573 eec &= ~IXGBE_EEC_DI;
1575 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1576 IXGBE_WRITE_FLUSH(hw);
1580 ixgbe_raise_eeprom_clk(hw, &eec);
1581 ixgbe_lower_eeprom_clk(hw, &eec);
1584 * Shift mask to signify next bit of data to shift in to the
1590 /* We leave the "DI" bit set to "0" when we leave this routine. */
1591 eec &= ~IXGBE_EEC_DI;
1592 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1593 IXGBE_WRITE_FLUSH(hw);
1597 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1598 * @hw: pointer to hardware structure
1600 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1607 * In order to read a register from the EEPROM, we need to shift
1608 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1609 * the clock input to the EEPROM (setting the SK bit), and then reading
1610 * the value of the "DO" bit. During this "shifting in" process the
1611 * "DI" bit should always be clear.
1613 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1615 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1617 for (i = 0; i < count; i++) {
1619 ixgbe_raise_eeprom_clk(hw, &eec);
1621 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1623 eec &= ~(IXGBE_EEC_DI);
1624 if (eec & IXGBE_EEC_DO)
1627 ixgbe_lower_eeprom_clk(hw, &eec);
1634 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1635 * @hw: pointer to hardware structure
1636 * @eec: EEC register's current value
1638 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1641 * Raise the clock input to the EEPROM
1642 * (setting the SK bit), then delay
1644 *eec = *eec | IXGBE_EEC_SK;
1645 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1646 IXGBE_WRITE_FLUSH(hw);
1651 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1652 * @hw: pointer to hardware structure
1653 * @eecd: EECD's current value
1655 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1658 * Lower the clock input to the EEPROM (clearing the SK bit), then
1661 *eec = *eec & ~IXGBE_EEC_SK;
1662 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1663 IXGBE_WRITE_FLUSH(hw);
1668 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1669 * @hw: pointer to hardware structure
1671 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1675 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1677 eec |= IXGBE_EEC_CS; /* Pull CS high */
1678 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1680 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1681 IXGBE_WRITE_FLUSH(hw);
1685 /* Stop requesting EEPROM access */
1686 eec &= ~IXGBE_EEC_REQ;
1687 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1689 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1692 * Delay before attempt to obtain semaphore again to allow FW
1693 * access. semaphore_delay is in ms we need us for usleep_range
1695 usleep_range(hw->eeprom.semaphore_delay * 1000,
1696 hw->eeprom.semaphore_delay * 2000);
1700 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
1701 * @hw: pointer to hardware structure
1703 u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
1712 /* Include 0x0-0x3F in the checksum */
1713 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
1714 if (hw->eeprom.ops.read(hw, i, &word) != 0) {
1715 hw_dbg(hw, "EEPROM read failed\n");
1721 /* Include all data from pointers except for the fw pointer */
1722 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
1723 hw->eeprom.ops.read(hw, i, &pointer);
1725 /* Make sure the pointer seems valid */
1726 if (pointer != 0xFFFF && pointer != 0) {
1727 hw->eeprom.ops.read(hw, pointer, &length);
1729 if (length != 0xFFFF && length != 0) {
1730 for (j = pointer+1; j <= pointer+length; j++) {
1731 hw->eeprom.ops.read(hw, j, &word);
1738 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1744 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
1745 * @hw: pointer to hardware structure
1746 * @checksum_val: calculated checksum
1748 * Performs checksum calculation and validates the EEPROM checksum. If the
1749 * caller does not need checksum_val, the value can be NULL.
1751 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1756 u16 read_checksum = 0;
1759 * Read the first word from the EEPROM. If this times out or fails, do
1760 * not continue or we could be in for a very long wait while every
1763 status = hw->eeprom.ops.read(hw, 0, &checksum);
1766 checksum = hw->eeprom.ops.calc_checksum(hw);
1768 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
1771 * Verify read checksum from EEPROM is the same as
1772 * calculated checksum
1774 if (read_checksum != checksum)
1775 status = IXGBE_ERR_EEPROM_CHECKSUM;
1777 /* If the user cares, return the calculated checksum */
1779 *checksum_val = checksum;
1781 hw_dbg(hw, "EEPROM read failed\n");
1788 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1789 * @hw: pointer to hardware structure
1791 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1797 * Read the first word from the EEPROM. If this times out or fails, do
1798 * not continue or we could be in for a very long wait while every
1801 status = hw->eeprom.ops.read(hw, 0, &checksum);
1804 checksum = hw->eeprom.ops.calc_checksum(hw);
1805 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1808 hw_dbg(hw, "EEPROM read failed\n");
1815 * ixgbe_set_rar_generic - Set Rx address register
1816 * @hw: pointer to hardware structure
1817 * @index: Receive address register to write
1818 * @addr: Address to put into receive address register
1819 * @vmdq: VMDq "set" or "pool" index
1820 * @enable_addr: set flag that address is active
1822 * Puts an ethernet address into a receive address register.
1824 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1827 u32 rar_low, rar_high;
1828 u32 rar_entries = hw->mac.num_rar_entries;
1830 /* Make sure we are using a valid rar index range */
1831 if (index >= rar_entries) {
1832 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1833 return IXGBE_ERR_INVALID_ARGUMENT;
1836 /* setup VMDq pool selection before this RAR gets enabled */
1837 hw->mac.ops.set_vmdq(hw, index, vmdq);
1840 * HW expects these in little endian so we reverse the byte
1841 * order from network order (big endian) to little endian
1843 rar_low = ((u32)addr[0] |
1844 ((u32)addr[1] << 8) |
1845 ((u32)addr[2] << 16) |
1846 ((u32)addr[3] << 24));
1848 * Some parts put the VMDq setting in the extra RAH bits,
1849 * so save everything except the lower 16 bits that hold part
1850 * of the address and the address valid bit.
1852 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1853 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1854 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
1856 if (enable_addr != 0)
1857 rar_high |= IXGBE_RAH_AV;
1859 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1860 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1866 * ixgbe_clear_rar_generic - Remove Rx address register
1867 * @hw: pointer to hardware structure
1868 * @index: Receive address register to write
1870 * Clears an ethernet address from a receive address register.
1872 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1875 u32 rar_entries = hw->mac.num_rar_entries;
1877 /* Make sure we are using a valid rar index range */
1878 if (index >= rar_entries) {
1879 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1880 return IXGBE_ERR_INVALID_ARGUMENT;
1884 * Some parts put the VMDq setting in the extra RAH bits,
1885 * so save everything except the lower 16 bits that hold part
1886 * of the address and the address valid bit.
1888 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1889 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1891 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1892 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1894 /* clear VMDq pool/queue selection for this RAR */
1895 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
1901 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
1902 * @hw: pointer to hardware structure
1904 * Places the MAC address in receive address register 0 and clears the rest
1905 * of the receive address registers. Clears the multicast table. Assumes
1906 * the receiver is in reset when the routine is called.
1908 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
1911 u32 rar_entries = hw->mac.num_rar_entries;
1914 * If the current mac address is valid, assume it is a software override
1915 * to the permanent address.
1916 * Otherwise, use the permanent address from the eeprom.
1918 if (!is_valid_ether_addr(hw->mac.addr)) {
1919 /* Get the MAC address from the RAR0 for later reference */
1920 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
1922 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
1924 /* Setup the receive address. */
1925 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
1926 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
1928 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1930 /* clear VMDq pool/queue selection for RAR 0 */
1931 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
1933 hw->addr_ctrl.overflow_promisc = 0;
1935 hw->addr_ctrl.rar_used_count = 1;
1937 /* Zero out the other receive addresses. */
1938 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
1939 for (i = 1; i < rar_entries; i++) {
1940 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1941 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1945 hw->addr_ctrl.mta_in_use = 0;
1946 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1948 hw_dbg(hw, " Clearing MTA\n");
1949 for (i = 0; i < hw->mac.mcft_size; i++)
1950 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1952 if (hw->mac.ops.init_uta_tables)
1953 hw->mac.ops.init_uta_tables(hw);
1959 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1960 * @hw: pointer to hardware structure
1961 * @mc_addr: the multicast address
1963 * Extracts the 12 bits, from a multicast address, to determine which
1964 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1965 * incoming rx multicast addresses, to determine the bit-vector to check in
1966 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
1967 * by the MO field of the MCSTCTRL. The MO field is set during initialization
1968 * to mc_filter_type.
1970 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1974 switch (hw->mac.mc_filter_type) {
1975 case 0: /* use bits [47:36] of the address */
1976 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1978 case 1: /* use bits [46:35] of the address */
1979 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1981 case 2: /* use bits [45:34] of the address */
1982 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1984 case 3: /* use bits [43:32] of the address */
1985 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1987 default: /* Invalid mc_filter_type */
1988 hw_dbg(hw, "MC filter type param set incorrectly\n");
1992 /* vector can only be 12-bits or boundary will be exceeded */
1998 * ixgbe_set_mta - Set bit-vector in multicast table
1999 * @hw: pointer to hardware structure
2000 * @hash_value: Multicast address hash value
2002 * Sets the bit-vector in the multicast table.
2004 static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2010 hw->addr_ctrl.mta_in_use++;
2012 vector = ixgbe_mta_vector(hw, mc_addr);
2013 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
2016 * The MTA is a register array of 128 32-bit registers. It is treated
2017 * like an array of 4096 bits. We want to set bit
2018 * BitArray[vector_value]. So we figure out what register the bit is
2019 * in, read it, OR in the new bit, then write back the new value. The
2020 * register is determined by the upper 7 bits of the vector value and
2021 * the bit within that register are determined by the lower 5 bits of
2024 vector_reg = (vector >> 5) & 0x7F;
2025 vector_bit = vector & 0x1F;
2026 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2030 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2031 * @hw: pointer to hardware structure
2032 * @netdev: pointer to net device structure
2034 * The given list replaces any existing list. Clears the MC addrs from receive
2035 * address registers and the multicast table. Uses unused receive address
2036 * registers for the first multicast addresses, and hashes the rest into the
2039 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
2040 struct net_device *netdev)
2042 struct netdev_hw_addr *ha;
2046 * Set the new number of MC addresses that we are being requested to
2049 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
2050 hw->addr_ctrl.mta_in_use = 0;
2052 /* Clear mta_shadow */
2053 hw_dbg(hw, " Clearing MTA\n");
2054 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2056 /* Update mta shadow */
2057 netdev_for_each_mc_addr(ha, netdev) {
2058 hw_dbg(hw, " Adding the multicast addresses:\n");
2059 ixgbe_set_mta(hw, ha->addr);
2063 for (i = 0; i < hw->mac.mcft_size; i++)
2064 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2065 hw->mac.mta_shadow[i]);
2067 if (hw->addr_ctrl.mta_in_use > 0)
2068 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2069 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2071 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
2076 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2077 * @hw: pointer to hardware structure
2079 * Enables multicast address in RAR and the use of the multicast hash table.
2081 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2083 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2085 if (a->mta_in_use > 0)
2086 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2087 hw->mac.mc_filter_type);
2093 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2094 * @hw: pointer to hardware structure
2096 * Disables multicast address in RAR and the use of the multicast hash table.
2098 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2100 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2102 if (a->mta_in_use > 0)
2103 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2109 * ixgbe_fc_enable_generic - Enable flow control
2110 * @hw: pointer to hardware structure
2112 * Enable flow control according to the current settings.
2114 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2117 u32 mflcn_reg, fccfg_reg;
2123 * Validate the water mark configuration for packet buffer 0. Zero
2124 * water marks indicate that the packet buffer was not configured
2125 * and the watermarks for packet buffer 0 should always be configured.
2127 if (!hw->fc.low_water ||
2128 !hw->fc.high_water[0] ||
2129 !hw->fc.pause_time) {
2130 hw_dbg(hw, "Invalid water mark configuration\n");
2131 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2135 /* Negotiate the fc mode to use */
2136 ixgbe_fc_autoneg(hw);
2138 /* Disable any previous flow control settings */
2139 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2140 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2142 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2143 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2146 * The possible values of fc.current_mode are:
2147 * 0: Flow control is completely disabled
2148 * 1: Rx flow control is enabled (we can receive pause frames,
2149 * but not send pause frames).
2150 * 2: Tx flow control is enabled (we can send pause frames but
2151 * we do not support receiving pause frames).
2152 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2155 switch (hw->fc.current_mode) {
2158 * Flow control is disabled by software override or autoneg.
2159 * The code below will actually disable it in the HW.
2162 case ixgbe_fc_rx_pause:
2164 * Rx Flow control is enabled and Tx Flow control is
2165 * disabled by software override. Since there really
2166 * isn't a way to advertise that we are capable of RX
2167 * Pause ONLY, we will advertise that we support both
2168 * symmetric and asymmetric Rx PAUSE. Later, we will
2169 * disable the adapter's ability to send PAUSE frames.
2171 mflcn_reg |= IXGBE_MFLCN_RFCE;
2173 case ixgbe_fc_tx_pause:
2175 * Tx Flow control is enabled, and Rx Flow control is
2176 * disabled by software override.
2178 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2181 /* Flow control (both Rx and Tx) is enabled by SW override. */
2182 mflcn_reg |= IXGBE_MFLCN_RFCE;
2183 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2186 hw_dbg(hw, "Flow control param set incorrectly\n");
2187 ret_val = IXGBE_ERR_CONFIG;
2192 /* Set 802.3x based flow control settings. */
2193 mflcn_reg |= IXGBE_MFLCN_DPF;
2194 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2195 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2197 fcrtl = (hw->fc.low_water << 10) | IXGBE_FCRTL_XONE;
2199 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2200 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
2201 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2202 hw->fc.high_water[i]) {
2203 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2204 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2206 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2208 * In order to prevent Tx hangs when the internal Tx
2209 * switch is enabled we must set the high water mark
2210 * to the maximum FCRTH value. This allows the Tx
2211 * switch to function even under heavy Rx workloads.
2213 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
2216 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2219 /* Configure pause time (2 TCs per register) */
2220 reg = hw->fc.pause_time * 0x00010001;
2221 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
2222 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2224 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2231 * ixgbe_negotiate_fc - Negotiate flow control
2232 * @hw: pointer to hardware structure
2233 * @adv_reg: flow control advertised settings
2234 * @lp_reg: link partner's flow control settings
2235 * @adv_sym: symmetric pause bit in advertisement
2236 * @adv_asm: asymmetric pause bit in advertisement
2237 * @lp_sym: symmetric pause bit in link partner advertisement
2238 * @lp_asm: asymmetric pause bit in link partner advertisement
2240 * Find the intersection between advertised settings and link partner's
2241 * advertised settings
2243 static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2244 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2246 if ((!(adv_reg)) || (!(lp_reg)))
2247 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2249 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2251 * Now we need to check if the user selected Rx ONLY
2252 * of pause frames. In this case, we had to advertise
2253 * FULL flow control because we could not advertise RX
2254 * ONLY. Hence, we must now check to see if we need to
2255 * turn OFF the TRANSMISSION of PAUSE frames.
2257 if (hw->fc.requested_mode == ixgbe_fc_full) {
2258 hw->fc.current_mode = ixgbe_fc_full;
2259 hw_dbg(hw, "Flow Control = FULL.\n");
2261 hw->fc.current_mode = ixgbe_fc_rx_pause;
2262 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n");
2264 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2265 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2266 hw->fc.current_mode = ixgbe_fc_tx_pause;
2267 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
2268 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2269 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2270 hw->fc.current_mode = ixgbe_fc_rx_pause;
2271 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
2273 hw->fc.current_mode = ixgbe_fc_none;
2274 hw_dbg(hw, "Flow Control = NONE.\n");
2280 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2281 * @hw: pointer to hardware structure
2283 * Enable flow control according on 1 gig fiber.
2285 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2287 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2288 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2291 * On multispeed fiber at 1g, bail out if
2292 * - link is up but AN did not complete, or if
2293 * - link is up and AN completed but timed out
2296 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2297 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2298 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
2301 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2302 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2304 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2305 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2306 IXGBE_PCS1GANA_ASM_PAUSE,
2307 IXGBE_PCS1GANA_SYM_PAUSE,
2308 IXGBE_PCS1GANA_ASM_PAUSE);
2315 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2316 * @hw: pointer to hardware structure
2318 * Enable flow control according to IEEE clause 37.
2320 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2322 u32 links2, anlp1_reg, autoc_reg, links;
2323 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2326 * On backplane, bail out if
2327 * - backplane autoneg was not completed, or if
2328 * - we are 82599 and link partner is not AN enabled
2330 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2331 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
2334 if (hw->mac.type == ixgbe_mac_82599EB) {
2335 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2336 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
2340 * Read the 10g AN autoc and LP ability registers and resolve
2341 * local flow control settings accordingly
2343 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2344 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2346 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2347 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2348 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2355 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2356 * @hw: pointer to hardware structure
2358 * Enable flow control according to IEEE clause 37.
2360 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2362 u16 technology_ability_reg = 0;
2363 u16 lp_technology_ability_reg = 0;
2365 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
2367 &technology_ability_reg);
2368 hw->phy.ops.read_reg(hw, MDIO_AN_LPA,
2370 &lp_technology_ability_reg);
2372 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2373 (u32)lp_technology_ability_reg,
2374 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2375 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2379 * ixgbe_fc_autoneg - Configure flow control
2380 * @hw: pointer to hardware structure
2382 * Compares our advertised flow control capabilities to those advertised by
2383 * our link partner, and determines the proper flow control mode to use.
2385 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
2387 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2388 ixgbe_link_speed speed;
2392 * AN should have completed when the cable was plugged in.
2393 * Look for reasons to bail out. Bail out if:
2394 * - FC autoneg is disabled, or if
2397 * Since we're being called from an LSC, link is already known to be up.
2398 * So use link_up_wait_to_complete=false.
2400 if (hw->fc.disable_fc_autoneg)
2403 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2407 switch (hw->phy.media_type) {
2408 /* Autoneg flow control on fiber adapters */
2409 case ixgbe_media_type_fiber_fixed:
2410 case ixgbe_media_type_fiber:
2411 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2412 ret_val = ixgbe_fc_autoneg_fiber(hw);
2415 /* Autoneg flow control on backplane adapters */
2416 case ixgbe_media_type_backplane:
2417 ret_val = ixgbe_fc_autoneg_backplane(hw);
2420 /* Autoneg flow control on copper adapters */
2421 case ixgbe_media_type_copper:
2422 if (ixgbe_device_supports_autoneg_fc(hw))
2423 ret_val = ixgbe_fc_autoneg_copper(hw);
2432 hw->fc.fc_was_autonegged = true;
2434 hw->fc.fc_was_autonegged = false;
2435 hw->fc.current_mode = hw->fc.requested_mode;
2440 * ixgbe_disable_pcie_master - Disable PCI-express master access
2441 * @hw: pointer to hardware structure
2443 * Disables PCI-Express master access and verifies there are no pending
2444 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2445 * bit hasn't caused the master requests to be disabled, else 0
2446 * is returned signifying master requests disabled.
2448 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2450 struct ixgbe_adapter *adapter = hw->back;
2455 /* Always set this bit to ensure any future transactions are blocked */
2456 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
2458 /* Exit if master requests are blocked */
2459 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2462 /* Poll for master request bit to clear */
2463 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2465 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2470 * Two consecutive resets are required via CTRL.RST per datasheet
2471 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2472 * of this need. The first reset prevents new master requests from
2473 * being issued by our device. We then must wait 1usec or more for any
2474 * remaining completions from the PCIe bus to trickle in, and then reset
2475 * again to clear out any effects they may have had on our device.
2477 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
2478 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2481 * Before proceeding, make sure that the PCIe block does not have
2482 * transactions pending.
2484 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2486 pci_read_config_word(adapter->pdev, IXGBE_PCI_DEVICE_STATUS,
2488 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
2492 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
2493 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
2500 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
2501 * @hw: pointer to hardware structure
2502 * @mask: Mask to specify which semaphore to acquire
2504 * Acquires the SWFW semaphore through the GSSR register for the specified
2505 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2507 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2511 u32 fwmask = mask << 5;
2515 for (i = 0; i < timeout; i++) {
2517 * SW NVM semaphore bit is used for access to all
2518 * SW_FW_SYNC bits (not just NVM)
2520 if (ixgbe_get_eeprom_semaphore(hw))
2521 return IXGBE_ERR_SWFW_SYNC;
2523 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2524 if (!(gssr & (fwmask | swmask))) {
2526 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2527 ixgbe_release_eeprom_semaphore(hw);
2530 /* Resource is currently in use by FW or SW */
2531 ixgbe_release_eeprom_semaphore(hw);
2532 usleep_range(5000, 10000);
2536 /* If time expired clear the bits holding the lock and retry */
2537 if (gssr & (fwmask | swmask))
2538 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
2540 usleep_range(5000, 10000);
2541 return IXGBE_ERR_SWFW_SYNC;
2545 * ixgbe_release_swfw_sync - Release SWFW semaphore
2546 * @hw: pointer to hardware structure
2547 * @mask: Mask to specify which semaphore to release
2549 * Releases the SWFW semaphore through the GSSR register for the specified
2550 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2552 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2557 ixgbe_get_eeprom_semaphore(hw);
2559 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2561 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2563 ixgbe_release_eeprom_semaphore(hw);
2567 * ixgbe_disable_rx_buff_generic - Stops the receive data path
2568 * @hw: pointer to hardware structure
2570 * Stops the receive data path and waits for the HW to internally
2571 * empty the Rx security block.
2573 s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw)
2575 #define IXGBE_MAX_SECRX_POLL 40
2579 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2580 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2581 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2582 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2583 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2584 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2587 /* Use interrupt-safe sleep just in case */
2591 /* For informational purposes only */
2592 if (i >= IXGBE_MAX_SECRX_POLL)
2593 hw_dbg(hw, "Rx unit being enabled before security "
2594 "path fully disabled. Continuing with init.\n");
2601 * ixgbe_enable_rx_buff - Enables the receive data path
2602 * @hw: pointer to hardware structure
2604 * Enables the receive data path
2606 s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw)
2610 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2611 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2612 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2613 IXGBE_WRITE_FLUSH(hw);
2619 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2620 * @hw: pointer to hardware structure
2621 * @regval: register value to write to RXCTRL
2623 * Enables the Rx DMA unit
2625 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2627 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2633 * ixgbe_blink_led_start_generic - Blink LED based on index.
2634 * @hw: pointer to hardware structure
2635 * @index: led number to blink
2637 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2639 ixgbe_link_speed speed = 0;
2640 bool link_up = false;
2641 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2642 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2646 * Link must be up to auto-blink the LEDs;
2647 * Force it if link is down.
2649 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2652 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
2655 bool got_lock = false;
2657 if ((hw->mac.type == ixgbe_mac_82599EB) &&
2658 ixgbe_verify_lesm_fw_enabled_82599(hw)) {
2659 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
2660 IXGBE_GSSR_MAC_CSR_SM);
2666 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2667 autoc_reg |= IXGBE_AUTOC_FLU;
2668 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2669 IXGBE_WRITE_FLUSH(hw);
2672 hw->mac.ops.release_swfw_sync(hw,
2673 IXGBE_GSSR_MAC_CSR_SM);
2674 usleep_range(10000, 20000);
2677 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2678 led_reg |= IXGBE_LED_BLINK(index);
2679 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2680 IXGBE_WRITE_FLUSH(hw);
2687 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2688 * @hw: pointer to hardware structure
2689 * @index: led number to stop blinking
2691 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2693 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2694 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2696 bool got_lock = false;
2698 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
2701 if ((hw->mac.type == ixgbe_mac_82599EB) &&
2702 ixgbe_verify_lesm_fw_enabled_82599(hw)) {
2703 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
2704 IXGBE_GSSR_MAC_CSR_SM);
2711 autoc_reg &= ~IXGBE_AUTOC_FLU;
2712 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2713 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2715 if (hw->mac.type == ixgbe_mac_82599EB)
2716 ixgbe_reset_pipeline_82599(hw);
2719 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
2721 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2722 led_reg &= ~IXGBE_LED_BLINK(index);
2723 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2724 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2725 IXGBE_WRITE_FLUSH(hw);
2732 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2733 * @hw: pointer to hardware structure
2734 * @san_mac_offset: SAN MAC address offset
2736 * This function will read the EEPROM location for the SAN MAC address
2737 * pointer, and returns the value at that location. This is used in both
2738 * get and set mac_addr routines.
2740 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
2741 u16 *san_mac_offset)
2746 * First read the EEPROM pointer to see if the MAC addresses are
2749 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
2752 hw_err(hw, "eeprom read at offset %d failed\n",
2753 IXGBE_SAN_MAC_ADDR_PTR);
2759 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2760 * @hw: pointer to hardware structure
2761 * @san_mac_addr: SAN MAC address
2763 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2764 * per-port, so set_lan_id() must be called before reading the addresses.
2765 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2766 * upon for non-SFP connections, so we must call it here.
2768 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2770 u16 san_mac_data, san_mac_offset;
2775 * First read the EEPROM pointer to see if the MAC addresses are
2776 * available. If they're not, no point in calling set_lan_id() here.
2778 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2779 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
2781 goto san_mac_addr_clr;
2783 /* make sure we know which port we need to program */
2784 hw->mac.ops.set_lan_id(hw);
2785 /* apply the port offset to the address offset */
2786 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2787 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2788 for (i = 0; i < 3; i++) {
2789 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
2792 hw_err(hw, "eeprom read at offset %d failed\n",
2794 goto san_mac_addr_clr;
2796 san_mac_addr[i * 2] = (u8)(san_mac_data);
2797 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2803 /* No addresses available in this EEPROM. It's not necessarily an
2804 * error though, so just wipe the local address and return.
2806 for (i = 0; i < 6; i++)
2807 san_mac_addr[i] = 0xFF;
2812 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2813 * @hw: pointer to hardware structure
2815 * Read PCIe configuration space, and get the MSI-X vector count from
2816 * the capabilities table.
2818 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
2820 struct ixgbe_adapter *adapter = hw->back;
2825 switch (hw->mac.type) {
2826 case ixgbe_mac_82598EB:
2827 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
2828 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
2830 case ixgbe_mac_82599EB:
2831 case ixgbe_mac_X540:
2832 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
2833 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
2839 pci_read_config_word(adapter->pdev, pcie_offset, &msix_count);
2840 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2842 /* MSI-X count is zero-based in HW */
2845 if (msix_count > max_msix_count)
2846 msix_count = max_msix_count;
2852 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2853 * @hw: pointer to hardware struct
2854 * @rar: receive address register index to disassociate
2855 * @vmdq: VMDq pool index to remove from the rar
2857 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2859 u32 mpsar_lo, mpsar_hi;
2860 u32 rar_entries = hw->mac.num_rar_entries;
2862 /* Make sure we are using a valid rar index range */
2863 if (rar >= rar_entries) {
2864 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2865 return IXGBE_ERR_INVALID_ARGUMENT;
2868 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2869 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2871 if (!mpsar_lo && !mpsar_hi)
2874 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2876 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2880 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2883 } else if (vmdq < 32) {
2884 mpsar_lo &= ~(1 << vmdq);
2885 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
2887 mpsar_hi &= ~(1 << (vmdq - 32));
2888 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
2891 /* was that the last pool using this rar? */
2892 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
2893 hw->mac.ops.clear_rar(hw, rar);
2899 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2900 * @hw: pointer to hardware struct
2901 * @rar: receive address register index to associate with a VMDq index
2902 * @vmdq: VMDq pool index
2904 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2907 u32 rar_entries = hw->mac.num_rar_entries;
2909 /* Make sure we are using a valid rar index range */
2910 if (rar >= rar_entries) {
2911 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2912 return IXGBE_ERR_INVALID_ARGUMENT;
2916 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2918 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2920 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2921 mpsar |= 1 << (vmdq - 32);
2922 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
2928 * This function should only be involved in the IOV mode.
2929 * In IOV mode, Default pool is next pool after the number of
2930 * VFs advertized and not 0.
2931 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
2933 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
2934 * @hw: pointer to hardware struct
2935 * @vmdq: VMDq pool index
2937 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
2939 u32 rar = hw->mac.san_mac_rar_index;
2942 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
2943 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2945 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2946 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
2953 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
2954 * @hw: pointer to hardware structure
2956 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
2960 for (i = 0; i < 128; i++)
2961 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2967 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
2968 * @hw: pointer to hardware structure
2969 * @vlan: VLAN id to write to VLAN filter
2971 * return the VLVF index where this VLAN id should be placed
2974 static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
2977 u32 first_empty_slot = 0;
2980 /* short cut the special case */
2985 * Search for the vlan id in the VLVF entries. Save off the first empty
2986 * slot found along the way
2988 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
2989 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
2990 if (!bits && !(first_empty_slot))
2991 first_empty_slot = regindex;
2992 else if ((bits & 0x0FFF) == vlan)
2997 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
2998 * in the VLVF. Else use the first empty VLVF register for this
3001 if (regindex >= IXGBE_VLVF_ENTRIES) {
3002 if (first_empty_slot)
3003 regindex = first_empty_slot;
3005 hw_dbg(hw, "No space in VLVF.\n");
3006 regindex = IXGBE_ERR_NO_SPACE;
3014 * ixgbe_set_vfta_generic - Set VLAN filter table
3015 * @hw: pointer to hardware structure
3016 * @vlan: VLAN id to write to VLAN filter
3017 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3018 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3020 * Turn on/off specified VLAN in the VLAN filter table.
3022 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3031 bool vfta_changed = false;
3034 return IXGBE_ERR_PARAM;
3037 * this is a 2 part operation - first the VFTA, then the
3038 * VLVF and VLVFB if VT Mode is set
3039 * We don't write the VFTA until we know the VLVF part succeeded.
3043 * The VFTA is a bitstring made up of 128 32-bit registers
3044 * that enable the particular VLAN id, much like the MTA:
3045 * bits[11-5]: which register
3046 * bits[4-0]: which bit in the register
3048 regindex = (vlan >> 5) & 0x7F;
3049 bitindex = vlan & 0x1F;
3050 targetbit = (1 << bitindex);
3051 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3054 if (!(vfta & targetbit)) {
3056 vfta_changed = true;
3059 if ((vfta & targetbit)) {
3061 vfta_changed = true;
3068 * make sure the vlan is in VLVF
3069 * set the vind bit in the matching VLVFB
3071 * clear the pool bit and possibly the vind
3073 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3074 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3077 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3082 /* set the pool bit */
3084 bits = IXGBE_READ_REG(hw,
3085 IXGBE_VLVFB(vlvf_index*2));
3086 bits |= (1 << vind);
3088 IXGBE_VLVFB(vlvf_index*2),
3091 bits = IXGBE_READ_REG(hw,
3092 IXGBE_VLVFB((vlvf_index*2)+1));
3093 bits |= (1 << (vind-32));
3095 IXGBE_VLVFB((vlvf_index*2)+1),
3099 /* clear the pool bit */
3101 bits = IXGBE_READ_REG(hw,
3102 IXGBE_VLVFB(vlvf_index*2));
3103 bits &= ~(1 << vind);
3105 IXGBE_VLVFB(vlvf_index*2),
3107 bits |= IXGBE_READ_REG(hw,
3108 IXGBE_VLVFB((vlvf_index*2)+1));
3110 bits = IXGBE_READ_REG(hw,
3111 IXGBE_VLVFB((vlvf_index*2)+1));
3112 bits &= ~(1 << (vind-32));
3114 IXGBE_VLVFB((vlvf_index*2)+1),
3116 bits |= IXGBE_READ_REG(hw,
3117 IXGBE_VLVFB(vlvf_index*2));
3122 * If there are still bits set in the VLVFB registers
3123 * for the VLAN ID indicated we need to see if the
3124 * caller is requesting that we clear the VFTA entry bit.
3125 * If the caller has requested that we clear the VFTA
3126 * entry bit but there are still pools/VFs using this VLAN
3127 * ID entry then ignore the request. We're not worried
3128 * about the case where we're turning the VFTA VLAN ID
3129 * entry bit on, only when requested to turn it off as
3130 * there may be multiple pools and/or VFs using the
3131 * VLAN ID entry. In that case we cannot clear the
3132 * VFTA bit until all pools/VFs using that VLAN ID have also
3133 * been cleared. This will be indicated by "bits" being
3137 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3138 (IXGBE_VLVF_VIEN | vlan));
3140 /* someone wants to clear the vfta entry
3141 * but some pools/VFs are still using it.
3143 vfta_changed = false;
3147 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3151 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3157 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3158 * @hw: pointer to hardware structure
3160 * Clears the VLAN filer table, and the VMDq index associated with the filter
3162 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3166 for (offset = 0; offset < hw->mac.vft_size; offset++)
3167 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3169 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3170 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
3171 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
3172 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
3179 * ixgbe_check_mac_link_generic - Determine link and speed status
3180 * @hw: pointer to hardware structure
3181 * @speed: pointer to link speed
3182 * @link_up: true when link is up
3183 * @link_up_wait_to_complete: bool used to wait for link up or not
3185 * Reads the links register to determine if link is up and the current speed
3187 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3188 bool *link_up, bool link_up_wait_to_complete)
3190 u32 links_reg, links_orig;
3193 /* clear the old state */
3194 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
3196 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3198 if (links_orig != links_reg) {
3199 hw_dbg(hw, "LINKS changed from %08X to %08X\n",
3200 links_orig, links_reg);
3203 if (link_up_wait_to_complete) {
3204 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
3205 if (links_reg & IXGBE_LINKS_UP) {
3212 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3215 if (links_reg & IXGBE_LINKS_UP)
3221 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3222 IXGBE_LINKS_SPEED_10G_82599)
3223 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3224 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3225 IXGBE_LINKS_SPEED_1G_82599)
3226 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3227 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3228 IXGBE_LINKS_SPEED_100_82599)
3229 *speed = IXGBE_LINK_SPEED_100_FULL;
3231 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3237 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
3239 * @hw: pointer to hardware structure
3240 * @wwnn_prefix: the alternative WWNN prefix
3241 * @wwpn_prefix: the alternative WWPN prefix
3243 * This function will read the EEPROM from the alternative SAN MAC address
3244 * block to check the support for the alternative WWNN/WWPN prefix support.
3246 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
3250 u16 alt_san_mac_blk_offset;
3252 /* clear output first */
3253 *wwnn_prefix = 0xFFFF;
3254 *wwpn_prefix = 0xFFFF;
3256 /* check if alternative SAN MAC is supported */
3257 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
3258 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
3259 goto wwn_prefix_err;
3261 if ((alt_san_mac_blk_offset == 0) ||
3262 (alt_san_mac_blk_offset == 0xFFFF))
3263 goto wwn_prefix_out;
3265 /* check capability in alternative san mac address block */
3266 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
3267 if (hw->eeprom.ops.read(hw, offset, &caps))
3268 goto wwn_prefix_err;
3269 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
3270 goto wwn_prefix_out;
3272 /* get the corresponding prefix for WWNN/WWPN */
3273 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
3274 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix))
3275 hw_err(hw, "eeprom read at offset %d failed\n", offset);
3277 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
3278 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
3279 goto wwn_prefix_err;
3285 hw_err(hw, "eeprom read at offset %d failed\n", offset);
3290 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3291 * @hw: pointer to hardware structure
3292 * @enable: enable or disable switch for anti-spoofing
3293 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
3296 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
3299 int pf_target_reg = pf >> 3;
3300 int pf_target_shift = pf % 8;
3303 if (hw->mac.type == ixgbe_mac_82598EB)
3307 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
3310 * PFVFSPOOF register array is size 8 with 8 bits assigned to
3311 * MAC anti-spoof enables in each register array element.
3313 for (j = 0; j < pf_target_reg; j++)
3314 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3317 * The PF should be allowed to spoof so that it can support
3318 * emulation mode NICs. Do not set the bits assigned to the PF
3320 pfvfspoof &= (1 << pf_target_shift) - 1;
3321 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3324 * Remaining pools belong to the PF so they do not need to have
3325 * anti-spoofing enabled.
3327 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
3328 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
3332 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3333 * @hw: pointer to hardware structure
3334 * @enable: enable or disable switch for VLAN anti-spoofing
3335 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3338 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3340 int vf_target_reg = vf >> 3;
3341 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
3344 if (hw->mac.type == ixgbe_mac_82598EB)
3347 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3349 pfvfspoof |= (1 << vf_target_shift);
3351 pfvfspoof &= ~(1 << vf_target_shift);
3352 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3356 * ixgbe_get_device_caps_generic - Get additional device capabilities
3357 * @hw: pointer to hardware structure
3358 * @device_caps: the EEPROM word with the extra device capabilities
3360 * This function will read the EEPROM location for the device capabilities,
3361 * and return the word through device_caps.
3363 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
3365 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
3371 * ixgbe_set_rxpba_generic - Initialize RX packet buffer
3372 * @hw: pointer to hardware structure
3373 * @num_pb: number of packet buffers to allocate
3374 * @headroom: reserve n KB of headroom
3375 * @strategy: packet buffer allocation strategy
3377 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw,
3382 u32 pbsize = hw->mac.rx_pb_size;
3384 u32 rxpktsize, txpktsize, txpbthresh;
3386 /* Reserve headroom */
3392 /* Divide remaining packet buffer space amongst the number
3393 * of packet buffers requested using supplied strategy.
3396 case (PBA_STRATEGY_WEIGHTED):
3397 /* pba_80_48 strategy weight first half of packet buffer with
3398 * 5/8 of the packet buffer space.
3400 rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8));
3401 pbsize -= rxpktsize * (num_pb / 2);
3402 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
3403 for (; i < (num_pb / 2); i++)
3404 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3405 /* Fall through to configure remaining packet buffers */
3406 case (PBA_STRATEGY_EQUAL):
3407 /* Divide the remaining Rx packet buffer evenly among the TCs */
3408 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
3409 for (; i < num_pb; i++)
3410 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3417 * Setup Tx packet buffer and threshold equally for all TCs
3418 * TXPBTHRESH register is set in K so divide by 1024 and subtract
3419 * 10 since the largest packet we support is just over 9K.
3421 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
3422 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
3423 for (i = 0; i < num_pb; i++) {
3424 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3425 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3428 /* Clear unused TCs, if any, to zero buffer size*/
3429 for (; i < IXGBE_MAX_PB; i++) {
3430 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3431 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3432 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3437 * ixgbe_calculate_checksum - Calculate checksum for buffer
3438 * @buffer: pointer to EEPROM
3439 * @length: size of EEPROM to calculate a checksum for
3441 * Calculates the checksum for some buffer on a specified length. The
3442 * checksum calculated is returned.
3444 static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
3452 for (i = 0; i < length; i++)
3455 return (u8) (0 - sum);
3459 * ixgbe_host_interface_command - Issue command to manageability block
3460 * @hw: pointer to the HW structure
3461 * @buffer: contains the command to write and where the return status will
3463 * @length: length of buffer, must be multiple of 4 bytes
3465 * Communicates with the manageability block. On success return 0
3466 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
3468 static s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
3472 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
3473 u8 buf_len, dword_len;
3477 if (length == 0 || length & 0x3 ||
3478 length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
3479 hw_dbg(hw, "Buffer length failure.\n");
3480 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3484 /* Check that the host interface is enabled. */
3485 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3486 if ((hicr & IXGBE_HICR_EN) == 0) {
3487 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n");
3488 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3492 /* Calculate length in DWORDs */
3493 dword_len = length >> 2;
3496 * The device driver writes the relevant command block
3497 * into the ram area.
3499 for (i = 0; i < dword_len; i++)
3500 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3501 i, cpu_to_le32(buffer[i]));
3503 /* Setting this bit tells the ARC that a new command is pending. */
3504 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
3506 for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
3507 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3508 if (!(hicr & IXGBE_HICR_C))
3510 usleep_range(1000, 2000);
3513 /* Check command successful completion. */
3514 if (i == IXGBE_HI_COMMAND_TIMEOUT ||
3515 (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
3516 hw_dbg(hw, "Command has failed with no status valid.\n");
3517 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3521 /* Calculate length in DWORDs */
3522 dword_len = hdr_size >> 2;
3524 /* first pull in the header so we know the buffer length */
3525 for (bi = 0; bi < dword_len; bi++) {
3526 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3527 le32_to_cpus(&buffer[bi]);
3530 /* If there is any thing in data position pull it in */
3531 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
3535 if (length < (buf_len + hdr_size)) {
3536 hw_dbg(hw, "Buffer not large enough for reply message.\n");
3537 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3541 /* Calculate length in DWORDs, add 3 for odd lengths */
3542 dword_len = (buf_len + 3) >> 2;
3544 /* Pull in the rest of the buffer (bi is where we left off)*/
3545 for (; bi <= dword_len; bi++) {
3546 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3547 le32_to_cpus(&buffer[bi]);
3555 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
3556 * @hw: pointer to the HW structure
3557 * @maj: driver version major number
3558 * @min: driver version minor number
3559 * @build: driver version build number
3560 * @sub: driver version sub build number
3562 * Sends driver version number to firmware through the manageability
3563 * block. On success return 0
3564 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
3565 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
3567 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
3570 struct ixgbe_hic_drv_info fw_cmd;
3574 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM) != 0) {
3575 ret_val = IXGBE_ERR_SWFW_SYNC;
3579 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
3580 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
3581 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
3582 fw_cmd.port_num = (u8)hw->bus.func;
3583 fw_cmd.ver_maj = maj;
3584 fw_cmd.ver_min = min;
3585 fw_cmd.ver_build = build;
3586 fw_cmd.ver_sub = sub;
3587 fw_cmd.hdr.checksum = 0;
3588 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
3589 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
3593 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
3594 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3599 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
3600 FW_CEM_RESP_STATUS_SUCCESS)
3603 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3608 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
3614 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
3615 * @hw: pointer to the hardware structure
3617 * The 82599 and x540 MACs can experience issues if TX work is still pending
3618 * when a reset occurs. This function prevents this by flushing the PCIe
3619 * buffers on the system.
3621 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
3623 u32 gcr_ext, hlreg0;
3626 * If double reset is not requested then all transactions should
3627 * already be clear and as such there is no work to do
3629 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
3633 * Set loopback enable to prevent any transmits from being sent
3634 * should the link come up. This assumes that the RXCTRL.RXEN bit
3635 * has already been cleared.
3637 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3638 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
3640 /* initiate cleaning flow for buffers in the PCIe transaction layer */
3641 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3642 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
3643 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
3645 /* Flush all writes and allow 20usec for all transactions to clear */
3646 IXGBE_WRITE_FLUSH(hw);
3649 /* restore previous register values */
3650 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3651 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3654 static const u8 ixgbe_emc_temp_data[4] = {
3655 IXGBE_EMC_INTERNAL_DATA,
3656 IXGBE_EMC_DIODE1_DATA,
3657 IXGBE_EMC_DIODE2_DATA,
3658 IXGBE_EMC_DIODE3_DATA
3660 static const u8 ixgbe_emc_therm_limit[4] = {
3661 IXGBE_EMC_INTERNAL_THERM_LIMIT,
3662 IXGBE_EMC_DIODE1_THERM_LIMIT,
3663 IXGBE_EMC_DIODE2_THERM_LIMIT,
3664 IXGBE_EMC_DIODE3_THERM_LIMIT
3668 * ixgbe_get_ets_data - Extracts the ETS bit data
3669 * @hw: pointer to hardware structure
3670 * @ets_cfg: extected ETS data
3671 * @ets_offset: offset of ETS data
3673 * Returns error code.
3675 static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg,
3680 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset);
3684 if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF)) {
3685 status = IXGBE_NOT_IMPLEMENTED;
3689 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg);
3693 if ((*ets_cfg & IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED) {
3694 status = IXGBE_NOT_IMPLEMENTED;
3703 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
3704 * @hw: pointer to hardware structure
3706 * Returns the thermal sensor data structure
3708 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
3716 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3718 /* Only support thermal sensors attached to physical port 0 */
3719 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
3720 status = IXGBE_NOT_IMPLEMENTED;
3724 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3728 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3729 if (num_sensors > IXGBE_MAX_SENSORS)
3730 num_sensors = IXGBE_MAX_SENSORS;
3732 for (i = 0; i < num_sensors; i++) {
3736 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
3741 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3742 IXGBE_ETS_DATA_INDEX_SHIFT);
3743 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3744 IXGBE_ETS_DATA_LOC_SHIFT);
3746 if (sensor_location != 0) {
3747 status = hw->phy.ops.read_i2c_byte(hw,
3748 ixgbe_emc_temp_data[sensor_index],
3749 IXGBE_I2C_THERMAL_SENSOR_ADDR,
3750 &data->sensor[i].temp);
3760 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
3761 * @hw: pointer to hardware structure
3763 * Inits the thermal sensor thresholds according to the NVM map
3764 * and save off the threshold and location values into mac.thermal_sensor_data
3766 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
3772 u8 low_thresh_delta;
3776 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3778 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
3780 /* Only support thermal sensors attached to physical port 0 */
3781 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
3782 status = IXGBE_NOT_IMPLEMENTED;
3786 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3790 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
3791 IXGBE_ETS_LTHRES_DELTA_SHIFT);
3792 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3793 if (num_sensors > IXGBE_MAX_SENSORS)
3794 num_sensors = IXGBE_MAX_SENSORS;
3796 for (i = 0; i < num_sensors; i++) {
3800 if (hw->eeprom.ops.read(hw, ets_offset + 1 + i, &ets_sensor)) {
3801 hw_err(hw, "eeprom read at offset %d failed\n",
3802 ets_offset + 1 + i);
3805 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3806 IXGBE_ETS_DATA_INDEX_SHIFT);
3807 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3808 IXGBE_ETS_DATA_LOC_SHIFT);
3809 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
3811 hw->phy.ops.write_i2c_byte(hw,
3812 ixgbe_emc_therm_limit[sensor_index],
3813 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
3815 if (sensor_location == 0)
3818 data->sensor[i].location = sensor_location;
3819 data->sensor[i].caution_thresh = therm_limit;
3820 data->sensor[i].max_op_thresh = therm_limit - low_thresh_delta;