drivers/net/ethernet/intel/igb/igb_main.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  29
  30 #include <linux/module.h>
  31 #include <linux/types.h>
  32 #include <linux/init.h>
  33 #include <linux/bitops.h>
  34 #include <linux/vmalloc.h>
  35 #include <linux/pagemap.h>
  36 #include <linux/netdevice.h>
  37 #include <linux/ipv6.h>
  38 #include <linux/slab.h>
  39 #include <net/checksum.h>
  40 #include <net/ip6_checksum.h>
  41 #include <linux/net_tstamp.h>
  42 #include <linux/mii.h>
  43 #include <linux/ethtool.h>
  44 #include <linux/if.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/pci.h>
  47 #include <linux/pci-aspm.h>
  48 #include <linux/delay.h>
  49 #include <linux/interrupt.h>
  50 #include <linux/ip.h>
  51 #include <linux/tcp.h>
  52 #include <linux/sctp.h>
  53 #include <linux/if_ether.h>
  54 #include <linux/aer.h>
  55 #include <linux/prefetch.h>
  56 #include <linux/pm_runtime.h>
  57 #ifdef CONFIG_IGB_DCA
  58 #include <linux/dca.h>
  59 #endif
  60 #include <linux/i2c.h>
  61 #include "igb.h"
  62
  63 #define MAJ 4
  64 #define MIN 1
  65 #define BUILD 2
  66 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
  67 __stringify(BUILD) "-k"
  68 char igb_driver_name[] = "igb";
  69 char igb_driver_version[] = DRV_VERSION;
  70 static const char igb_driver_string[] =
  71                                 "Intel(R) Gigabit Ethernet Network Driver";
  72 static const char igb_copyright[] =
  73                                 "Copyright (c) 2007-2013 Intel Corporation.";
  74
  75 static const struct e1000_info *igb_info_tbl[] = {
  76         [board_82575] = &e1000_82575_info,
  77 };
  78
  79 static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
  80         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
  81         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
  82         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
  83         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
  84         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
  85         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
  86         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
  87         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
  88         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
  89         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
  90         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
  91         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
  92         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
  93         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
  94         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
  95         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
  96         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
  97         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
  98         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
  99         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
 100         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
 101         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
 102         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
 103         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
 104         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
 105         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
 106         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
 107         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
 108         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
 109         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
 110         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
 111         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
 112         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
 113         /* required last entry */
 114         {0, }
 115 };
 116
 117 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
 118
 119 void igb_reset(struct igb_adapter *);
 120 static int igb_setup_all_tx_resources(struct igb_adapter *);
 121 static int igb_setup_all_rx_resources(struct igb_adapter *);
 122 static void igb_free_all_tx_resources(struct igb_adapter *);
 123 static void igb_free_all_rx_resources(struct igb_adapter *);
 124 static void igb_setup_mrqc(struct igb_adapter *);
 125 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
 126 static void igb_remove(struct pci_dev *pdev);
 127 static int igb_sw_init(struct igb_adapter *);
 128 static int igb_open(struct net_device *);
 129 static int igb_close(struct net_device *);
 130 static void igb_configure(struct igb_adapter *);
 131 static void igb_configure_tx(struct igb_adapter *);
 132 static void igb_configure_rx(struct igb_adapter *);
 133 static void igb_clean_all_tx_rings(struct igb_adapter *);
 134 static void igb_clean_all_rx_rings(struct igb_adapter *);
 135 static void igb_clean_tx_ring(struct igb_ring *);
 136 static void igb_clean_rx_ring(struct igb_ring *);
 137 static void igb_set_rx_mode(struct net_device *);
 138 static void igb_update_phy_info(unsigned long);
 139 static void igb_watchdog(unsigned long);
 140 static void igb_watchdog_task(struct work_struct *);
 141 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
 142 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
 143                                                  struct rtnl_link_stats64 *stats);
 144 static int igb_change_mtu(struct net_device *, int);
 145 static int igb_set_mac(struct net_device *, void *);
 146 static void igb_set_uta(struct igb_adapter *adapter);
 147 static irqreturn_t igb_intr(int irq, void *);
 148 static irqreturn_t igb_intr_msi(int irq, void *);
 149 static irqreturn_t igb_msix_other(int irq, void *);
 150 static irqreturn_t igb_msix_ring(int irq, void *);
 151 #ifdef CONFIG_IGB_DCA
 152 static void igb_update_dca(struct igb_q_vector *);
 153 static void igb_setup_dca(struct igb_adapter *);
 154 #endif /* CONFIG_IGB_DCA */
 155 static int igb_poll(struct napi_struct *, int);
 156 static bool igb_clean_tx_irq(struct igb_q_vector *);
 157 static bool igb_clean_rx_irq(struct igb_q_vector *, int);
 158 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
 159 static void igb_tx_timeout(struct net_device *);
 160 static void igb_reset_task(struct work_struct *);
 161 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
 162 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
 163 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
 164 static void igb_restore_vlan(struct igb_adapter *);
 165 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
 166 static void igb_ping_all_vfs(struct igb_adapter *);
 167 static void igb_msg_task(struct igb_adapter *);
 168 static void igb_vmm_control(struct igb_adapter *);
 169 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
 170 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
 171 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
 172 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
 173                                int vf, u16 vlan, u8 qos);
 174 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
 175 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
 176                                    bool setting);
 177 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
 178                                  struct ifla_vf_info *ivi);
 179 static void igb_check_vf_rate_limit(struct igb_adapter *);
 180
 181 #ifdef CONFIG_PCI_IOV
 182 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
 183 static bool igb_vfs_are_assigned(struct igb_adapter *adapter);
 184 #endif
 185
 186 #ifdef CONFIG_PM
 187 #ifdef CONFIG_PM_SLEEP
 188 static int igb_suspend(struct device *);
 189 #endif
 190 static int igb_resume(struct device *);
 191 #ifdef CONFIG_PM_RUNTIME
 192 static int igb_runtime_suspend(struct device *dev);
 193 static int igb_runtime_resume(struct device *dev);
 194 static int igb_runtime_idle(struct device *dev);
 195 #endif
 196 static const struct dev_pm_ops igb_pm_ops = {
 197         SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
 198         SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
 199                         igb_runtime_idle)
 200 };
 201 #endif
 202 static void igb_shutdown(struct pci_dev *);
 203 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
 204 #ifdef CONFIG_IGB_DCA
 205 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
 206 static struct notifier_block dca_notifier = {
 207         .notifier_call  = igb_notify_dca,
 208         .next           = NULL,
 209         .priority       = 0
 210 };
 211 #endif
 212 #ifdef CONFIG_NET_POLL_CONTROLLER
 213 /* for netdump / net console */
 214 static void igb_netpoll(struct net_device *);
 215 #endif
 216 #ifdef CONFIG_PCI_IOV
 217 static unsigned int max_vfs = 0;
 218 module_param(max_vfs, uint, 0);
 219 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
 220                  "per physical function");
 221 #endif /* CONFIG_PCI_IOV */
 222
 223 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
 224                      pci_channel_state_t);
 225 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
 226 static void igb_io_resume(struct pci_dev *);
 227
 228 static const struct pci_error_handlers igb_err_handler = {
 229         .error_detected = igb_io_error_detected,
 230         .slot_reset = igb_io_slot_reset,
 231         .resume = igb_io_resume,
 232 };
 233
 234 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
 235
 236 static struct pci_driver igb_driver = {
 237         .name     = igb_driver_name,
 238         .id_table = igb_pci_tbl,
 239         .probe    = igb_probe,
 240         .remove   = igb_remove,
 241 #ifdef CONFIG_PM
 242         .driver.pm = &igb_pm_ops,
 243 #endif
 244         .shutdown = igb_shutdown,
 245         .sriov_configure = igb_pci_sriov_configure,
 246         .err_handler = &igb_err_handler
 247 };
 248
 249 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
 250 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
 251 MODULE_LICENSE("GPL");
 252 MODULE_VERSION(DRV_VERSION);
 253
 254 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
 255 static int debug = -1;
 256 module_param(debug, int, 0);
 257 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
 258
 259 struct igb_reg_info {
 260         u32 ofs;
 261         char *name;
 262 };
 263
 264 static const struct igb_reg_info igb_reg_info_tbl[] = {
 265
 266         /* General Registers */
 267         {E1000_CTRL, "CTRL"},
 268         {E1000_STATUS, "STATUS"},
 269         {E1000_CTRL_EXT, "CTRL_EXT"},
 270
 271         /* Interrupt Registers */
 272         {E1000_ICR, "ICR"},
 273
 274         /* RX Registers */
 275         {E1000_RCTL, "RCTL"},
 276         {E1000_RDLEN(0), "RDLEN"},
 277         {E1000_RDH(0), "RDH"},
 278         {E1000_RDT(0), "RDT"},
 279         {E1000_RXDCTL(0), "RXDCTL"},
 280         {E1000_RDBAL(0), "RDBAL"},
 281         {E1000_RDBAH(0), "RDBAH"},
 282
 283         /* TX Registers */
 284         {E1000_TCTL, "TCTL"},
 285         {E1000_TDBAL(0), "TDBAL"},
 286         {E1000_TDBAH(0), "TDBAH"},
 287         {E1000_TDLEN(0), "TDLEN"},
 288         {E1000_TDH(0), "TDH"},
 289         {E1000_TDT(0), "TDT"},
 290         {E1000_TXDCTL(0), "TXDCTL"},
 291         {E1000_TDFH, "TDFH"},
 292         {E1000_TDFT, "TDFT"},
 293         {E1000_TDFHS, "TDFHS"},
 294         {E1000_TDFPC, "TDFPC"},
 295
 296         /* List Terminator */
 297         {}
 298 };
 299
 300 /* igb_regdump - register printout routine */
 301 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
 302 {
 303         int n = 0;
 304         char rname[16];
 305         u32 regs[8];
 306
 307         switch (reginfo->ofs) {
 308         case E1000_RDLEN(0):
 309                 for (n = 0; n < 4; n++)
 310                         regs[n] = rd32(E1000_RDLEN(n));
 311                 break;
 312         case E1000_RDH(0):
 313                 for (n = 0; n < 4; n++)
 314                         regs[n] = rd32(E1000_RDH(n));
 315                 break;
 316         case E1000_RDT(0):
 317                 for (n = 0; n < 4; n++)
 318                         regs[n] = rd32(E1000_RDT(n));
 319                 break;
 320         case E1000_RXDCTL(0):
 321                 for (n = 0; n < 4; n++)
 322                         regs[n] = rd32(E1000_RXDCTL(n));
 323                 break;
 324         case E1000_RDBAL(0):
 325                 for (n = 0; n < 4; n++)
 326                         regs[n] = rd32(E1000_RDBAL(n));
 327                 break;
 328         case E1000_RDBAH(0):
 329                 for (n = 0; n < 4; n++)
 330                         regs[n] = rd32(E1000_RDBAH(n));
 331                 break;
 332         case E1000_TDBAL(0):
 333                 for (n = 0; n < 4; n++)
 334                         regs[n] = rd32(E1000_RDBAL(n));
 335                 break;
 336         case E1000_TDBAH(0):
 337                 for (n = 0; n < 4; n++)
 338                         regs[n] = rd32(E1000_TDBAH(n));
 339                 break;
 340         case E1000_TDLEN(0):
 341                 for (n = 0; n < 4; n++)
 342                         regs[n] = rd32(E1000_TDLEN(n));
 343                 break;
 344         case E1000_TDH(0):
 345                 for (n = 0; n < 4; n++)
 346                         regs[n] = rd32(E1000_TDH(n));
 347                 break;
 348         case E1000_TDT(0):
 349                 for (n = 0; n < 4; n++)
 350                         regs[n] = rd32(E1000_TDT(n));
 351                 break;
 352         case E1000_TXDCTL(0):
 353                 for (n = 0; n < 4; n++)
 354                         regs[n] = rd32(E1000_TXDCTL(n));
 355                 break;
 356         default:
 357                 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
 358                 return;
 359         }
 360
 361         snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
 362         pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
 363                 regs[2], regs[3]);
 364 }
 365
 366 /* igb_dump - Print registers, Tx-rings and Rx-rings */
 367 static void igb_dump(struct igb_adapter *adapter)
 368 {
 369         struct net_device *netdev = adapter->netdev;
 370         struct e1000_hw *hw = &adapter->hw;
 371         struct igb_reg_info *reginfo;
 372         struct igb_ring *tx_ring;
 373         union e1000_adv_tx_desc *tx_desc;
 374         struct my_u0 { u64 a; u64 b; } *u0;
 375         struct igb_ring *rx_ring;
 376         union e1000_adv_rx_desc *rx_desc;
 377         u32 staterr;
 378         u16 i, n;
 379
 380         if (!netif_msg_hw(adapter))
 381                 return;
 382
 383         /* Print netdevice Info */
 384         if (netdev) {
 385                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 386                 pr_info("Device Name     state            trans_start      "
 387                         "last_rx\n");
 388                 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
 389                         netdev->state, netdev->trans_start, netdev->last_rx);
 390         }
 391
 392         /* Print Registers */
 393         dev_info(&adapter->pdev->dev, "Register Dump\n");
 394         pr_info(" Register Name   Value\n");
 395         for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
 396              reginfo->name; reginfo++) {
 397                 igb_regdump(hw, reginfo);
 398         }
 399
 400         /* Print TX Ring Summary */
 401         if (!netdev || !netif_running(netdev))
 402                 goto exit;
 403
 404         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 405         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 406         for (n = 0; n < adapter->num_tx_queues; n++) {
 407                 struct igb_tx_buffer *buffer_info;
 408                 tx_ring = adapter->tx_ring[n];
 409                 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 410                 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
 411                         n, tx_ring->next_to_use, tx_ring->next_to_clean,
 412                         (u64)dma_unmap_addr(buffer_info, dma),
 413                         dma_unmap_len(buffer_info, len),
 414                         buffer_info->next_to_watch,
 415                         (u64)buffer_info->time_stamp);
 416         }
 417
 418         /* Print TX Rings */
 419         if (!netif_msg_tx_done(adapter))
 420                 goto rx_ring_summary;
 421
 422         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 423
 424         /* Transmit Descriptor Formats
 425          *
 426          * Advanced Transmit Descriptor
 427          *   +--------------------------------------------------------------+
 428          * 0 |         Buffer Address [63:0]                                |
 429          *   +--------------------------------------------------------------+
 430          * 8 | PAYLEN  | PORTS  |CC|IDX | STA | DCMD  |DTYP|MAC|RSV| DTALEN |
 431          *   +--------------------------------------------------------------+
 432          *   63      46 45    40 39 38 36 35 32 31   24             15       0
 433          */
 434
 435         for (n = 0; n < adapter->num_tx_queues; n++) {
 436                 tx_ring = adapter->tx_ring[n];
 437                 pr_info("------------------------------------\n");
 438                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 439                 pr_info("------------------------------------\n");
 440                 pr_info("T [desc]     [address 63:0  ] [PlPOCIStDDM Ln] "
 441                         "[bi->dma       ] leng  ntw timestamp        "
 442                         "bi->skb\n");
 443
 444                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 445                         const char *next_desc;
 446                         struct igb_tx_buffer *buffer_info;
 447                         tx_desc = IGB_TX_DESC(tx_ring, i);
 448                         buffer_info = &tx_ring->tx_buffer_info[i];
 449                         u0 = (struct my_u0 *)tx_desc;
 450                         if (i == tx_ring->next_to_use &&
 451                             i == tx_ring->next_to_clean)
 452                                 next_desc = " NTC/U";
 453                         else if (i == tx_ring->next_to_use)
 454                                 next_desc = " NTU";
 455                         else if (i == tx_ring->next_to_clean)
 456                                 next_desc = " NTC";
 457                         else
 458                                 next_desc = "";
 459
 460                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 461                                 " %04X  %p %016llX %p%s\n", i,
 462                                 le64_to_cpu(u0->a),
 463                                 le64_to_cpu(u0->b),
 464                                 (u64)dma_unmap_addr(buffer_info, dma),
 465                                 dma_unmap_len(buffer_info, len),
 466                                 buffer_info->next_to_watch,
 467                                 (u64)buffer_info->time_stamp,
 468                                 buffer_info->skb, next_desc);
 469
 470                         if (netif_msg_pktdata(adapter) && buffer_info->skb)
 471                                 print_hex_dump(KERN_INFO, "",
 472                                         DUMP_PREFIX_ADDRESS,
 473                                         16, 1, buffer_info->skb->data,
 474                                         dma_unmap_len(buffer_info, len),
 475                                         true);
 476                 }
 477         }
 478
 479         /* Print RX Rings Summary */
 480 rx_ring_summary:
 481         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 482         pr_info("Queue [NTU] [NTC]\n");
 483         for (n = 0; n < adapter->num_rx_queues; n++) {
 484                 rx_ring = adapter->rx_ring[n];
 485                 pr_info(" %5d %5X %5X\n",
 486                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 487         }
 488
 489         /* Print RX Rings */
 490         if (!netif_msg_rx_status(adapter))
 491                 goto exit;
 492
 493         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 494
 495         /* Advanced Receive Descriptor (Read) Format
 496          *    63                                           1        0
 497          *    +-----------------------------------------------------+
 498          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 499          *    +----------------------------------------------+------+
 500          *  8 |       Header Buffer Address [63:1]           |  DD  |
 501          *    +-----------------------------------------------------+
 502          *
 503          *
 504          * Advanced Receive Descriptor (Write-Back) Format
 505          *
 506          *   63       48 47    32 31  30      21 20 17 16   4 3     0
 507          *   +------------------------------------------------------+
 508          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 509          *   | Checksum   Ident  |   |           |    | Type | Type |
 510          *   +------------------------------------------------------+
 511          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 512          *   +------------------------------------------------------+
 513          *   63       48 47    32 31            20 19               0
 514          */
 515
 516         for (n = 0; n < adapter->num_rx_queues; n++) {
 517                 rx_ring = adapter->rx_ring[n];
 518                 pr_info("------------------------------------\n");
 519                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 520                 pr_info("------------------------------------\n");
 521                 pr_info("R  [desc]      [ PktBuf     A0] [  HeadBuf   DD] "
 522                         "[bi->dma       ] [bi->skb] <-- Adv Rx Read format\n");
 523                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] [vl er S cks ln] -----"
 524                         "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
 525
 526                 for (i = 0; i < rx_ring->count; i++) {
 527                         const char *next_desc;
 528                         struct igb_rx_buffer *buffer_info;
 529                         buffer_info = &rx_ring->rx_buffer_info[i];
 530                         rx_desc = IGB_RX_DESC(rx_ring, i);
 531                         u0 = (struct my_u0 *)rx_desc;
 532                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 533
 534                         if (i == rx_ring->next_to_use)
 535                                 next_desc = " NTU";
 536                         else if (i == rx_ring->next_to_clean)
 537                                 next_desc = " NTC";
 538                         else
 539                                 next_desc = "";
 540
 541                         if (staterr & E1000_RXD_STAT_DD) {
 542                                 /* Descriptor Done */
 543                                 pr_info("%s[0x%03X]     %016llX %016llX ---------------- %s\n",
 544                                         "RWB", i,
 545                                         le64_to_cpu(u0->a),
 546                                         le64_to_cpu(u0->b),
 547                                         next_desc);
 548                         } else {
 549                                 pr_info("%s[0x%03X]     %016llX %016llX %016llX %s\n",
 550                                         "R  ", i,
 551                                         le64_to_cpu(u0->a),
 552                                         le64_to_cpu(u0->b),
 553                                         (u64)buffer_info->dma,
 554                                         next_desc);
 555
 556                                 if (netif_msg_pktdata(adapter) &&
 557                                     buffer_info->dma && buffer_info->page) {
 558                                         print_hex_dump(KERN_INFO, "",
 559                                           DUMP_PREFIX_ADDRESS,
 560                                           16, 1,
 561                                           page_address(buffer_info->page) +
 562                                                       buffer_info->page_offset,
 563                                           IGB_RX_BUFSZ, true);
 564                                 }
 565                         }
 566                 }
 567         }
 568
 569 exit:
 570         return;
 571 }
 572
 573 /**
 574  *  igb_get_i2c_data - Reads the I2C SDA data bit
 575  *  @hw: pointer to hardware structure
 576  *  @i2cctl: Current value of I2CCTL register
 577  *
 578  *  Returns the I2C data bit value
 579  **/
 580 static int igb_get_i2c_data(void *data)
 581 {
 582         struct igb_adapter *adapter = (struct igb_adapter *)data;
 583         struct e1000_hw *hw = &adapter->hw;
 584         s32 i2cctl = rd32(E1000_I2CPARAMS);
 585
 586         return ((i2cctl & E1000_I2C_DATA_IN) != 0);
 587 }
 588
 589 /**
 590  *  igb_set_i2c_data - Sets the I2C data bit
 591  *  @data: pointer to hardware structure
 592  *  @state: I2C data value (0 or 1) to set
 593  *
 594  *  Sets the I2C data bit
 595  **/
 596 static void igb_set_i2c_data(void *data, int state)
 597 {
 598         struct igb_adapter *adapter = (struct igb_adapter *)data;
 599         struct e1000_hw *hw = &adapter->hw;
 600         s32 i2cctl = rd32(E1000_I2CPARAMS);
 601
 602         if (state)
 603                 i2cctl |= E1000_I2C_DATA_OUT;
 604         else
 605                 i2cctl &= ~E1000_I2C_DATA_OUT;
 606
 607         i2cctl &= ~E1000_I2C_DATA_OE_N;
 608         i2cctl |= E1000_I2C_CLK_OE_N;
 609         wr32(E1000_I2CPARAMS, i2cctl);
 610         wrfl();
 611
 612 }
 613
 614 /**
 615  *  igb_set_i2c_clk - Sets the I2C SCL clock
 616  *  @data: pointer to hardware structure
 617  *  @state: state to set clock
 618  *
 619  *  Sets the I2C clock line to state
 620  **/
 621 static void igb_set_i2c_clk(void *data, int state)
 622 {
 623         struct igb_adapter *adapter = (struct igb_adapter *)data;
 624         struct e1000_hw *hw = &adapter->hw;
 625         s32 i2cctl = rd32(E1000_I2CPARAMS);
 626
 627         if (state) {
 628                 i2cctl |= E1000_I2C_CLK_OUT;
 629                 i2cctl &= ~E1000_I2C_CLK_OE_N;
 630         } else {
 631                 i2cctl &= ~E1000_I2C_CLK_OUT;
 632                 i2cctl &= ~E1000_I2C_CLK_OE_N;
 633         }
 634         wr32(E1000_I2CPARAMS, i2cctl);
 635         wrfl();
 636 }
 637
 638 /**
 639  *  igb_get_i2c_clk - Gets the I2C SCL clock state
 640  *  @data: pointer to hardware structure
 641  *
 642  *  Gets the I2C clock state
 643  **/
 644 static int igb_get_i2c_clk(void *data)
 645 {
 646         struct igb_adapter *adapter = (struct igb_adapter *)data;
 647         struct e1000_hw *hw = &adapter->hw;
 648         s32 i2cctl = rd32(E1000_I2CPARAMS);
 649
 650         return ((i2cctl & E1000_I2C_CLK_IN) != 0);
 651 }
 652
 653 static const struct i2c_algo_bit_data igb_i2c_algo = {
 654         .setsda         = igb_set_i2c_data,
 655         .setscl         = igb_set_i2c_clk,
 656         .getsda         = igb_get_i2c_data,
 657         .getscl         = igb_get_i2c_clk,
 658         .udelay         = 5,
 659         .timeout        = 20,
 660 };
 661
 662 /**
 663  *  igb_get_hw_dev - return device
 664  *  @hw: pointer to hardware structure
 665  *
 666  *  used by hardware layer to print debugging information
 667  **/
 668 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
 669 {
 670         struct igb_adapter *adapter = hw->back;
 671         return adapter->netdev;
 672 }
 673
 674 /**
 675  *  igb_init_module - Driver Registration Routine
 676  *
 677  *  igb_init_module is the first routine called when the driver is
 678  *  loaded. All it does is register with the PCI subsystem.
 679  **/
 680 static int __init igb_init_module(void)
 681 {
 682         int ret;
 683         pr_info("%s - version %s\n",
 684                igb_driver_string, igb_driver_version);
 685
 686         pr_info("%s\n", igb_copyright);
 687
 688 #ifdef CONFIG_IGB_DCA
 689         dca_register_notify(&dca_notifier);
 690 #endif
 691         ret = pci_register_driver(&igb_driver);
 692         return ret;
 693 }
 694
 695 module_init(igb_init_module);
 696
 697 /**
 698  *  igb_exit_module - Driver Exit Cleanup Routine
 699  *
 700  *  igb_exit_module is called just before the driver is removed
 701  *  from memory.
 702  **/
 703 static void __exit igb_exit_module(void)
 704 {
 705 #ifdef CONFIG_IGB_DCA
 706         dca_unregister_notify(&dca_notifier);
 707 #endif
 708         pci_unregister_driver(&igb_driver);
 709 }
 710
 711 module_exit(igb_exit_module);
 712
 713 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
 714 /**
 715  *  igb_cache_ring_register - Descriptor ring to register mapping
 716  *  @adapter: board private structure to initialize
 717  *
 718  *  Once we know the feature-set enabled for the device, we'll cache
 719  *  the register offset the descriptor ring is assigned to.
 720  **/
 721 static void igb_cache_ring_register(struct igb_adapter *adapter)
 722 {
 723         int i = 0, j = 0;
 724         u32 rbase_offset = adapter->vfs_allocated_count;
 725
 726         switch (adapter->hw.mac.type) {
 727         case e1000_82576:
 728                 /* The queues are allocated for virtualization such that VF 0
 729                  * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
 730                  * In order to avoid collision we start at the first free queue
 731                  * and continue consuming queues in the same sequence
 732                  */
 733                 if (adapter->vfs_allocated_count) {
 734                         for (; i < adapter->rss_queues; i++)
 735                                 adapter->rx_ring[i]->reg_idx = rbase_offset +
 736                                                                Q_IDX_82576(i);
 737                 }
 738         case e1000_82575:
 739         case e1000_82580:
 740         case e1000_i350:
 741         case e1000_i354:
 742         case e1000_i210:
 743         case e1000_i211:
 744         default:
 745                 for (; i < adapter->num_rx_queues; i++)
 746                         adapter->rx_ring[i]->reg_idx = rbase_offset + i;
 747                 for (; j < adapter->num_tx_queues; j++)
 748                         adapter->tx_ring[j]->reg_idx = rbase_offset + j;
 749                 break;
 750         }
 751 }
 752
 753 /**
 754  *  igb_write_ivar - configure ivar for given MSI-X vector
 755  *  @hw: pointer to the HW structure
 756  *  @msix_vector: vector number we are allocating to a given ring
 757  *  @index: row index of IVAR register to write within IVAR table
 758  *  @offset: column offset of in IVAR, should be multiple of 8
 759  *
 760  *  This function is intended to handle the writing of the IVAR register
 761  *  for adapters 82576 and newer.  The IVAR table consists of 2 columns,
 762  *  each containing an cause allocation for an Rx and Tx ring, and a
 763  *  variable number of rows depending on the number of queues supported.
 764  **/
 765 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
 766                            int index, int offset)
 767 {
 768         u32 ivar = array_rd32(E1000_IVAR0, index);
 769
 770         /* clear any bits that are currently set */
 771         ivar &= ~((u32)0xFF << offset);
 772
 773         /* write vector and valid bit */
 774         ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
 775
 776         array_wr32(E1000_IVAR0, index, ivar);
 777 }
 778
 779 #define IGB_N0_QUEUE -1
 780 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
 781 {
 782         struct igb_adapter *adapter = q_vector->adapter;
 783         struct e1000_hw *hw = &adapter->hw;
 784         int rx_queue = IGB_N0_QUEUE;
 785         int tx_queue = IGB_N0_QUEUE;
 786         u32 msixbm = 0;
 787
 788         if (q_vector->rx.ring)
 789                 rx_queue = q_vector->rx.ring->reg_idx;
 790         if (q_vector->tx.ring)
 791                 tx_queue = q_vector->tx.ring->reg_idx;
 792
 793         switch (hw->mac.type) {
 794         case e1000_82575:
 795                 /* The 82575 assigns vectors using a bitmask, which matches the
 796                  * bitmask for the EICR/EIMS/EIMC registers.  To assign one
 797                  * or more queues to a vector, we write the appropriate bits
 798                  * into the MSIXBM register for that vector.
 799                  */
 800                 if (rx_queue > IGB_N0_QUEUE)
 801                         msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
 802                 if (tx_queue > IGB_N0_QUEUE)
 803                         msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
 804                 if (!adapter->msix_entries && msix_vector == 0)
 805                         msixbm |= E1000_EIMS_OTHER;
 806                 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
 807                 q_vector->eims_value = msixbm;
 808                 break;
 809         case e1000_82576:
 810                 /* 82576 uses a table that essentially consists of 2 columns
 811                  * with 8 rows.  The ordering is column-major so we use the
 812                  * lower 3 bits as the row index, and the 4th bit as the
 813                  * column offset.
 814                  */
 815                 if (rx_queue > IGB_N0_QUEUE)
 816                         igb_write_ivar(hw, msix_vector,
 817                                        rx_queue & 0x7,
 818                                        (rx_queue & 0x8) << 1);
 819                 if (tx_queue > IGB_N0_QUEUE)
 820                         igb_write_ivar(hw, msix_vector,
 821                                        tx_queue & 0x7,
 822                                        ((tx_queue & 0x8) << 1) + 8);
 823                 q_vector->eims_value = 1 << msix_vector;
 824                 break;
 825         case e1000_82580:
 826         case e1000_i350:
 827         case e1000_i354:
 828         case e1000_i210:
 829         case e1000_i211:
 830                 /* On 82580 and newer adapters the scheme is similar to 82576
 831                  * however instead of ordering column-major we have things
 832                  * ordered row-major.  So we traverse the table by using
 833                  * bit 0 as the column offset, and the remaining bits as the
 834                  * row index.
 835                  */
 836                 if (rx_queue > IGB_N0_QUEUE)
 837                         igb_write_ivar(hw, msix_vector,
 838                                        rx_queue >> 1,
 839                                        (rx_queue & 0x1) << 4);
 840                 if (tx_queue > IGB_N0_QUEUE)
 841                         igb_write_ivar(hw, msix_vector,
 842                                        tx_queue >> 1,
 843                                        ((tx_queue & 0x1) << 4) + 8);
 844                 q_vector->eims_value = 1 << msix_vector;
 845                 break;
 846         default:
 847                 BUG();
 848                 break;
 849         }
 850
 851         /* add q_vector eims value to global eims_enable_mask */
 852         adapter->eims_enable_mask |= q_vector->eims_value;
 853
 854         /* configure q_vector to set itr on first interrupt */
 855         q_vector->set_itr = 1;
 856 }
 857
 858 /**
 859  *  igb_configure_msix - Configure MSI-X hardware
 860  *  @adapter: board private structure to initialize
 861  *
 862  *  igb_configure_msix sets up the hardware to properly
 863  *  generate MSI-X interrupts.
 864  **/
 865 static void igb_configure_msix(struct igb_adapter *adapter)
 866 {
 867         u32 tmp;
 868         int i, vector = 0;
 869         struct e1000_hw *hw = &adapter->hw;
 870
 871         adapter->eims_enable_mask = 0;
 872
 873         /* set vector for other causes, i.e. link changes */
 874         switch (hw->mac.type) {
 875         case e1000_82575:
 876                 tmp = rd32(E1000_CTRL_EXT);
 877                 /* enable MSI-X PBA support*/
 878                 tmp |= E1000_CTRL_EXT_PBA_CLR;
 879
 880                 /* Auto-Mask interrupts upon ICR read. */
 881                 tmp |= E1000_CTRL_EXT_EIAME;
 882                 tmp |= E1000_CTRL_EXT_IRCA;
 883
 884                 wr32(E1000_CTRL_EXT, tmp);
 885
 886                 /* enable msix_other interrupt */
 887                 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
 888                 adapter->eims_other = E1000_EIMS_OTHER;
 889
 890                 break;
 891
 892         case e1000_82576:
 893         case e1000_82580:
 894         case e1000_i350:
 895         case e1000_i354:
 896         case e1000_i210:
 897         case e1000_i211:
 898                 /* Turn on MSI-X capability first, or our settings
 899                  * won't stick.  And it will take days to debug.
 900                  */
 901                 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
 902                      E1000_GPIE_PBA | E1000_GPIE_EIAME |
 903                      E1000_GPIE_NSICR);
 904
 905                 /* enable msix_other interrupt */
 906                 adapter->eims_other = 1 << vector;
 907                 tmp = (vector++ | E1000_IVAR_VALID) << 8;
 908
 909                 wr32(E1000_IVAR_MISC, tmp);
 910                 break;
 911         default:
 912                 /* do nothing, since nothing else supports MSI-X */
 913                 break;
 914         } /* switch (hw->mac.type) */
 915
 916         adapter->eims_enable_mask |= adapter->eims_other;
 917
 918         for (i = 0; i < adapter->num_q_vectors; i++)
 919                 igb_assign_vector(adapter->q_vector[i], vector++);
 920
 921         wrfl();
 922 }
 923
 924 /**
 925  *  igb_request_msix - Initialize MSI-X interrupts
 926  *  @adapter: board private structure to initialize
 927  *
 928  *  igb_request_msix allocates MSI-X vectors and requests interrupts from the
 929  *  kernel.
 930  **/
 931 static int igb_request_msix(struct igb_adapter *adapter)
 932 {
 933         struct net_device *netdev = adapter->netdev;
 934         struct e1000_hw *hw = &adapter->hw;
 935         int i, err = 0, vector = 0, free_vector = 0;
 936
 937         err = request_irq(adapter->msix_entries[vector].vector,
 938                           igb_msix_other, 0, netdev->name, adapter);
 939         if (err)
 940                 goto err_out;
 941
 942         for (i = 0; i < adapter->num_q_vectors; i++) {
 943                 struct igb_q_vector *q_vector = adapter->q_vector[i];
 944
 945                 vector++;
 946
 947                 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
 948
 949                 if (q_vector->rx.ring && q_vector->tx.ring)
 950                         sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
 951                                 q_vector->rx.ring->queue_index);
 952                 else if (q_vector->tx.ring)
 953                         sprintf(q_vector->name, "%s-tx-%u", netdev->name,
 954                                 q_vector->tx.ring->queue_index);
 955                 else if (q_vector->rx.ring)
 956                         sprintf(q_vector->name, "%s-rx-%u", netdev->name,
 957                                 q_vector->rx.ring->queue_index);
 958                 else
 959                         sprintf(q_vector->name, "%s-unused", netdev->name);
 960
 961                 err = request_irq(adapter->msix_entries[vector].vector,
 962                                   igb_msix_ring, 0, q_vector->name,
 963                                   q_vector);
 964                 if (err)
 965                         goto err_free;
 966         }
 967
 968         igb_configure_msix(adapter);
 969         return 0;
 970
 971 err_free:
 972         /* free already assigned IRQs */
 973         free_irq(adapter->msix_entries[free_vector++].vector, adapter);
 974
 975         vector--;
 976         for (i = 0; i < vector; i++) {
 977                 free_irq(adapter->msix_entries[free_vector++].vector,
 978                          adapter->q_vector[i]);
 979         }
 980 err_out:
 981         return err;
 982 }
 983
 984 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
 985 {
 986         if (adapter->msix_entries) {
 987                 pci_disable_msix(adapter->pdev);
 988                 kfree(adapter->msix_entries);
 989                 adapter->msix_entries = NULL;
 990         } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
 991                 pci_disable_msi(adapter->pdev);
 992         }
 993 }
 994
 995 /**
 996  *  igb_free_q_vector - Free memory allocated for specific interrupt vector
 997  *  @adapter: board private structure to initialize
 998  *  @v_idx: Index of vector to be freed
 999  *
1000  *  This function frees the memory allocated to the q_vector.  In addition if
1001  *  NAPI is enabled it will delete any references to the NAPI struct prior
1002  *  to freeing the q_vector.
1003  **/
1004 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1005 {
1006         struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1007
1008         if (q_vector->tx.ring)
1009                 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1010
1011         if (q_vector->rx.ring)
1012                 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1013
1014         adapter->q_vector[v_idx] = NULL;
1015         netif_napi_del(&q_vector->napi);
1016
1017         /* ixgbe_get_stats64() might access the rings on this vector,
1018          * we must wait a grace period before freeing it.
1019          */
1020         kfree_rcu(q_vector, rcu);
1021 }
1022
1023 /**
1024  *  igb_free_q_vectors - Free memory allocated for interrupt vectors
1025  *  @adapter: board private structure to initialize
1026  *
1027  *  This function frees the memory allocated to the q_vectors.  In addition if
1028  *  NAPI is enabled it will delete any references to the NAPI struct prior
1029  *  to freeing the q_vector.
1030  **/
1031 static void igb_free_q_vectors(struct igb_adapter *adapter)
1032 {
1033         int v_idx = adapter->num_q_vectors;
1034
1035         adapter->num_tx_queues = 0;
1036         adapter->num_rx_queues = 0;
1037         adapter->num_q_vectors = 0;
1038
1039         while (v_idx--)
1040                 igb_free_q_vector(adapter, v_idx);
1041 }
1042
1043 /**
1044  *  igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1045  *  @adapter: board private structure to initialize
1046  *
1047  *  This function resets the device so that it has 0 Rx queues, Tx queues, and
1048  *  MSI-X interrupts allocated.
1049  */
1050 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1051 {
1052         igb_free_q_vectors(adapter);
1053         igb_reset_interrupt_capability(adapter);
1054 }
1055
1056 /**
1057  *  igb_set_interrupt_capability - set MSI or MSI-X if supported
1058  *  @adapter: board private structure to initialize
1059  *  @msix: boolean value of MSIX capability
1060  *
1061  *  Attempt to configure interrupts using the best available
1062  *  capabilities of the hardware and kernel.
1063  **/
1064 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1065 {
1066         int err;
1067         int numvecs, i;
1068
1069         if (!msix)
1070                 goto msi_only;
1071
1072         /* Number of supported queues. */
1073         adapter->num_rx_queues = adapter->rss_queues;
1074         if (adapter->vfs_allocated_count)
1075                 adapter->num_tx_queues = 1;
1076         else
1077                 adapter->num_tx_queues = adapter->rss_queues;
1078
1079         /* start with one vector for every Rx queue */
1080         numvecs = adapter->num_rx_queues;
1081
1082         /* if Tx handler is separate add 1 for every Tx queue */
1083         if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1084                 numvecs += adapter->num_tx_queues;
1085
1086         /* store the number of vectors reserved for queues */
1087         adapter->num_q_vectors = numvecs;
1088
1089         /* add 1 vector for link status interrupts */
1090         numvecs++;
1091         adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1092                                         GFP_KERNEL);
1093
1094         if (!adapter->msix_entries)
1095                 goto msi_only;
1096
1097         for (i = 0; i < numvecs; i++)
1098                 adapter->msix_entries[i].entry = i;
1099
1100         err = pci_enable_msix(adapter->pdev,
1101                               adapter->msix_entries,
1102                               numvecs);
1103         if (err == 0)
1104                 return;
1105
1106         igb_reset_interrupt_capability(adapter);
1107
1108         /* If we can't do MSI-X, try MSI */
1109 msi_only:
1110 #ifdef CONFIG_PCI_IOV
1111         /* disable SR-IOV for non MSI-X configurations */
1112         if (adapter->vf_data) {
1113                 struct e1000_hw *hw = &adapter->hw;
1114                 /* disable iov and allow time for transactions to clear */
1115                 pci_disable_sriov(adapter->pdev);
1116                 msleep(500);
1117
1118                 kfree(adapter->vf_data);
1119                 adapter->vf_data = NULL;
1120                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1121                 wrfl();
1122                 msleep(100);
1123                 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1124         }
1125 #endif
1126         adapter->vfs_allocated_count = 0;
1127         adapter->rss_queues = 1;
1128         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1129         adapter->num_rx_queues = 1;
1130         adapter->num_tx_queues = 1;
1131         adapter->num_q_vectors = 1;
1132         if (!pci_enable_msi(adapter->pdev))
1133                 adapter->flags |= IGB_FLAG_HAS_MSI;
1134 }
1135
1136 static void igb_add_ring(struct igb_ring *ring,
1137                          struct igb_ring_container *head)
1138 {
1139         head->ring = ring;
1140         head->count++;
1141 }
1142
1143 /**
1144  *  igb_alloc_q_vector - Allocate memory for a single interrupt vector
1145  *  @adapter: board private structure to initialize
1146  *  @v_count: q_vectors allocated on adapter, used for ring interleaving
1147  *  @v_idx: index of vector in adapter struct
1148  *  @txr_count: total number of Tx rings to allocate
1149  *  @txr_idx: index of first Tx ring to allocate
1150  *  @rxr_count: total number of Rx rings to allocate
1151  *  @rxr_idx: index of first Rx ring to allocate
1152  *
1153  *  We allocate one q_vector.  If allocation fails we return -ENOMEM.
1154  **/
1155 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1156                               int v_count, int v_idx,
1157                               int txr_count, int txr_idx,
1158                               int rxr_count, int rxr_idx)
1159 {
1160         struct igb_q_vector *q_vector;
1161         struct igb_ring *ring;
1162         int ring_count, size;
1163
1164         /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1165         if (txr_count > 1 || rxr_count > 1)
1166                 return -ENOMEM;
1167
1168         ring_count = txr_count + rxr_count;
1169         size = sizeof(struct igb_q_vector) +
1170                (sizeof(struct igb_ring) * ring_count);
1171
1172         /* allocate q_vector and rings */
1173         q_vector = kzalloc(size, GFP_KERNEL);
1174         if (!q_vector)
1175                 return -ENOMEM;
1176
1177         /* initialize NAPI */
1178         netif_napi_add(adapter->netdev, &q_vector->napi,
1179                        igb_poll, 64);
1180
1181         /* tie q_vector and adapter together */
1182         adapter->q_vector[v_idx] = q_vector;
1183         q_vector->adapter = adapter;
1184
1185         /* initialize work limits */
1186         q_vector->tx.work_limit = adapter->tx_work_limit;
1187
1188         /* initialize ITR configuration */
1189         q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1190         q_vector->itr_val = IGB_START_ITR;
1191
1192         /* initialize pointer to rings */
1193         ring = q_vector->ring;
1194
1195         /* intialize ITR */
1196         if (rxr_count) {
1197                 /* rx or rx/tx vector */
1198                 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1199                         q_vector->itr_val = adapter->rx_itr_setting;
1200         } else {
1201                 /* tx only vector */
1202                 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1203                         q_vector->itr_val = adapter->tx_itr_setting;
1204         }
1205
1206         if (txr_count) {
1207                 /* assign generic ring traits */
1208                 ring->dev = &adapter->pdev->dev;
1209                 ring->netdev = adapter->netdev;
1210
1211                 /* configure backlink on ring */
1212                 ring->q_vector = q_vector;
1213
1214                 /* update q_vector Tx values */
1215                 igb_add_ring(ring, &q_vector->tx);
1216
1217                 /* For 82575, context index must be unique per ring. */
1218                 if (adapter->hw.mac.type == e1000_82575)
1219                         set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1220
1221                 /* apply Tx specific ring traits */
1222                 ring->count = adapter->tx_ring_count;
1223                 ring->queue_index = txr_idx;
1224
1225                 /* assign ring to adapter */
1226                 adapter->tx_ring[txr_idx] = ring;
1227
1228                 /* push pointer to next ring */
1229                 ring++;
1230         }
1231
1232         if (rxr_count) {
1233                 /* assign generic ring traits */
1234                 ring->dev = &adapter->pdev->dev;
1235                 ring->netdev = adapter->netdev;
1236
1237                 /* configure backlink on ring */
1238                 ring->q_vector = q_vector;
1239
1240                 /* update q_vector Rx values */
1241                 igb_add_ring(ring, &q_vector->rx);
1242
1243                 /* set flag indicating ring supports SCTP checksum offload */
1244                 if (adapter->hw.mac.type >= e1000_82576)
1245                         set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1246
1247                 /*
1248                  * On i350, i354, i210, and i211, loopback VLAN packets
1249                  * have the tag byte-swapped.
1250                  */
1251                 if (adapter->hw.mac.type >= e1000_i350)
1252                         set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1253
1254                 /* apply Rx specific ring traits */
1255                 ring->count = adapter->rx_ring_count;
1256                 ring->queue_index = rxr_idx;
1257
1258                 /* assign ring to adapter */
1259                 adapter->rx_ring[rxr_idx] = ring;
1260         }
1261
1262         return 0;
1263 }
1264
1265
1266 /**
1267  *  igb_alloc_q_vectors - Allocate memory for interrupt vectors
1268  *  @adapter: board private structure to initialize
1269  *
1270  *  We allocate one q_vector per queue interrupt.  If allocation fails we
1271  *  return -ENOMEM.
1272  **/
1273 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1274 {
1275         int q_vectors = adapter->num_q_vectors;
1276         int rxr_remaining = adapter->num_rx_queues;
1277         int txr_remaining = adapter->num_tx_queues;
1278         int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1279         int err;
1280
1281         if (q_vectors >= (rxr_remaining + txr_remaining)) {
1282                 for (; rxr_remaining; v_idx++) {
1283                         err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1284                                                  0, 0, 1, rxr_idx);
1285
1286                         if (err)
1287                                 goto err_out;
1288
1289                         /* update counts and index */
1290                         rxr_remaining--;
1291                         rxr_idx++;
1292                 }
1293         }
1294
1295         for (; v_idx < q_vectors; v_idx++) {
1296                 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1297                 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1298                 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1299                                          tqpv, txr_idx, rqpv, rxr_idx);
1300
1301                 if (err)
1302                         goto err_out;
1303
1304                 /* update counts and index */
1305                 rxr_remaining -= rqpv;
1306                 txr_remaining -= tqpv;
1307                 rxr_idx++;
1308                 txr_idx++;
1309         }
1310
1311         return 0;
1312
1313 err_out:
1314         adapter->num_tx_queues = 0;
1315         adapter->num_rx_queues = 0;
1316         adapter->num_q_vectors = 0;
1317
1318         while (v_idx--)
1319                 igb_free_q_vector(adapter, v_idx);
1320
1321         return -ENOMEM;
1322 }
1323
1324 /**
1325  *  igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1326  *  @adapter: board private structure to initialize
1327  *  @msix: boolean value of MSIX capability
1328  *
1329  *  This function initializes the interrupts and allocates all of the queues.
1330  **/
1331 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1332 {
1333         struct pci_dev *pdev = adapter->pdev;
1334         int err;
1335
1336         igb_set_interrupt_capability(adapter, msix);
1337
1338         err = igb_alloc_q_vectors(adapter);
1339         if (err) {
1340                 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1341                 goto err_alloc_q_vectors;
1342         }
1343
1344         igb_cache_ring_register(adapter);
1345
1346         return 0;
1347
1348 err_alloc_q_vectors:
1349         igb_reset_interrupt_capability(adapter);
1350         return err;
1351 }
1352
1353 /**
1354  *  igb_request_irq - initialize interrupts
1355  *  @adapter: board private structure to initialize
1356  *
1357  *  Attempts to configure interrupts using the best available
1358  *  capabilities of the hardware and kernel.
1359  **/
1360 static int igb_request_irq(struct igb_adapter *adapter)
1361 {
1362         struct net_device *netdev = adapter->netdev;
1363         struct pci_dev *pdev = adapter->pdev;
1364         int err = 0;
1365
1366         if (adapter->msix_entries) {
1367                 err = igb_request_msix(adapter);
1368                 if (!err)
1369                         goto request_done;
1370                 /* fall back to MSI */
1371                 igb_free_all_tx_resources(adapter);
1372                 igb_free_all_rx_resources(adapter);
1373
1374                 igb_clear_interrupt_scheme(adapter);
1375                 err = igb_init_interrupt_scheme(adapter, false);
1376                 if (err)
1377                         goto request_done;
1378
1379                 igb_setup_all_tx_resources(adapter);
1380                 igb_setup_all_rx_resources(adapter);
1381                 igb_configure(adapter);
1382         }
1383
1384         igb_assign_vector(adapter->q_vector[0], 0);
1385
1386         if (adapter->flags & IGB_FLAG_HAS_MSI) {
1387                 err = request_irq(pdev->irq, igb_intr_msi, 0,
1388                                   netdev->name, adapter);
1389                 if (!err)
1390                         goto request_done;
1391
1392                 /* fall back to legacy interrupts */
1393                 igb_reset_interrupt_capability(adapter);
1394                 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1395         }
1396
1397         err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1398                           netdev->name, adapter);
1399
1400         if (err)
1401                 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1402                         err);
1403
1404 request_done:
1405         return err;
1406 }
1407
1408 static void igb_free_irq(struct igb_adapter *adapter)
1409 {
1410         if (adapter->msix_entries) {
1411                 int vector = 0, i;
1412
1413                 free_irq(adapter->msix_entries[vector++].vector, adapter);
1414
1415                 for (i = 0; i < adapter->num_q_vectors; i++)
1416                         free_irq(adapter->msix_entries[vector++].vector,
1417                                  adapter->q_vector[i]);
1418         } else {
1419                 free_irq(adapter->pdev->irq, adapter);
1420         }
1421 }
1422
1423 /**
1424  *  igb_irq_disable - Mask off interrupt generation on the NIC
1425  *  @adapter: board private structure
1426  **/
1427 static void igb_irq_disable(struct igb_adapter *adapter)
1428 {
1429         struct e1000_hw *hw = &adapter->hw;
1430
1431         /* we need to be careful when disabling interrupts.  The VFs are also
1432          * mapped into these registers and so clearing the bits can cause
1433          * issues on the VF drivers so we only need to clear what we set
1434          */
1435         if (adapter->msix_entries) {
1436                 u32 regval = rd32(E1000_EIAM);
1437                 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1438                 wr32(E1000_EIMC, adapter->eims_enable_mask);
1439                 regval = rd32(E1000_EIAC);
1440                 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1441         }
1442
1443         wr32(E1000_IAM, 0);
1444         wr32(E1000_IMC, ~0);
1445         wrfl();
1446         if (adapter->msix_entries) {
1447                 int i;
1448                 for (i = 0; i < adapter->num_q_vectors; i++)
1449                         synchronize_irq(adapter->msix_entries[i].vector);
1450         } else {
1451                 synchronize_irq(adapter->pdev->irq);
1452         }
1453 }
1454
1455 /**
1456  *  igb_irq_enable - Enable default interrupt generation settings
1457  *  @adapter: board private structure
1458  **/
1459 static void igb_irq_enable(struct igb_adapter *adapter)
1460 {
1461         struct e1000_hw *hw = &adapter->hw;
1462
1463         if (adapter->msix_entries) {
1464                 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1465                 u32 regval = rd32(E1000_EIAC);
1466                 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1467                 regval = rd32(E1000_EIAM);
1468                 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1469                 wr32(E1000_EIMS, adapter->eims_enable_mask);
1470                 if (adapter->vfs_allocated_count) {
1471                         wr32(E1000_MBVFIMR, 0xFF);
1472                         ims |= E1000_IMS_VMMB;
1473                 }
1474                 wr32(E1000_IMS, ims);
1475         } else {
1476                 wr32(E1000_IMS, IMS_ENABLE_MASK |
1477                                 E1000_IMS_DRSTA);
1478                 wr32(E1000_IAM, IMS_ENABLE_MASK |
1479                                 E1000_IMS_DRSTA);
1480         }
1481 }
1482
1483 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1484 {
1485         struct e1000_hw *hw = &adapter->hw;
1486         u16 vid = adapter->hw.mng_cookie.vlan_id;
1487         u16 old_vid = adapter->mng_vlan_id;
1488
1489         if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1490                 /* add VID to filter table */
1491                 igb_vfta_set(hw, vid, true);
1492                 adapter->mng_vlan_id = vid;
1493         } else {
1494                 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1495         }
1496
1497         if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1498             (vid != old_vid) &&
1499             !test_bit(old_vid, adapter->active_vlans)) {
1500                 /* remove VID from filter table */
1501                 igb_vfta_set(hw, old_vid, false);
1502         }
1503 }
1504
1505 /**
1506  *  igb_release_hw_control - release control of the h/w to f/w
1507  *  @adapter: address of board private structure
1508  *
1509  *  igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1510  *  For ASF and Pass Through versions of f/w this means that the
1511  *  driver is no longer loaded.
1512  **/
1513 static void igb_release_hw_control(struct igb_adapter *adapter)
1514 {
1515         struct e1000_hw *hw = &adapter->hw;
1516         u32 ctrl_ext;
1517
1518         /* Let firmware take over control of h/w */
1519         ctrl_ext = rd32(E1000_CTRL_EXT);
1520         wr32(E1000_CTRL_EXT,
1521                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1522 }
1523
1524 /**
1525  *  igb_get_hw_control - get control of the h/w from f/w
1526  *  @adapter: address of board private structure
1527  *
1528  *  igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1529  *  For ASF and Pass Through versions of f/w this means that
1530  *  the driver is loaded.
1531  **/
1532 static void igb_get_hw_control(struct igb_adapter *adapter)
1533 {
1534         struct e1000_hw *hw = &adapter->hw;
1535         u32 ctrl_ext;
1536
1537         /* Let firmware know the driver has taken over */
1538         ctrl_ext = rd32(E1000_CTRL_EXT);
1539         wr32(E1000_CTRL_EXT,
1540                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1541 }
1542
1543 /**
1544  *  igb_configure - configure the hardware for RX and TX
1545  *  @adapter: private board structure
1546  **/
1547 static void igb_configure(struct igb_adapter *adapter)
1548 {
1549         struct net_device *netdev = adapter->netdev;
1550         int i;
1551
1552         igb_get_hw_control(adapter);
1553         igb_set_rx_mode(netdev);
1554
1555         igb_restore_vlan(adapter);
1556
1557         igb_setup_tctl(adapter);
1558         igb_setup_mrqc(adapter);
1559         igb_setup_rctl(adapter);
1560
1561         igb_configure_tx(adapter);
1562         igb_configure_rx(adapter);
1563
1564         igb_rx_fifo_flush_82575(&adapter->hw);
1565
1566         /* call igb_desc_unused which always leaves
1567          * at least 1 descriptor unused to make sure
1568          * next_to_use != next_to_clean
1569          */
1570         for (i = 0; i < adapter->num_rx_queues; i++) {
1571                 struct igb_ring *ring = adapter->rx_ring[i];
1572                 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1573         }
1574 }
1575
1576 /**
1577  *  igb_power_up_link - Power up the phy/serdes link
1578  *  @adapter: address of board private structure
1579  **/
1580 void igb_power_up_link(struct igb_adapter *adapter)
1581 {
1582         igb_reset_phy(&adapter->hw);
1583
1584         if (adapter->hw.phy.media_type == e1000_media_type_copper)
1585                 igb_power_up_phy_copper(&adapter->hw);
1586         else
1587                 igb_power_up_serdes_link_82575(&adapter->hw);
1588 }
1589
1590 /**
1591  *  igb_power_down_link - Power down the phy/serdes link
1592  *  @adapter: address of board private structure
1593  */
1594 static void igb_power_down_link(struct igb_adapter *adapter)
1595 {
1596         if (adapter->hw.phy.media_type == e1000_media_type_copper)
1597                 igb_power_down_phy_copper_82575(&adapter->hw);
1598         else
1599                 igb_shutdown_serdes_link_82575(&adapter->hw);
1600 }
1601
1602 /**
1603  *  igb_up - Open the interface and prepare it to handle traffic
1604  *  @adapter: board private structure
1605  **/
1606 int igb_up(struct igb_adapter *adapter)
1607 {
1608         struct e1000_hw *hw = &adapter->hw;
1609         int i;
1610
1611         /* hardware has been reset, we need to reload some things */
1612         igb_configure(adapter);
1613
1614         clear_bit(__IGB_DOWN, &adapter->state);
1615
1616         for (i = 0; i < adapter->num_q_vectors; i++)
1617                 napi_enable(&(adapter->q_vector[i]->napi));
1618
1619         if (adapter->msix_entries)
1620                 igb_configure_msix(adapter);
1621         else
1622                 igb_assign_vector(adapter->q_vector[0], 0);
1623
1624         /* Clear any pending interrupts. */
1625         rd32(E1000_ICR);
1626         igb_irq_enable(adapter);
1627
1628         /* notify VFs that reset has been completed */
1629         if (adapter->vfs_allocated_count) {
1630                 u32 reg_data = rd32(E1000_CTRL_EXT);
1631                 reg_data |= E1000_CTRL_EXT_PFRSTD;
1632                 wr32(E1000_CTRL_EXT, reg_data);
1633         }
1634
1635         netif_tx_start_all_queues(adapter->netdev);
1636
1637         /* start the watchdog. */
1638         hw->mac.get_link_status = 1;
1639         schedule_work(&adapter->watchdog_task);
1640
1641         return 0;
1642 }
1643
1644 void igb_down(struct igb_adapter *adapter)
1645 {
1646         struct net_device *netdev = adapter->netdev;
1647         struct e1000_hw *hw = &adapter->hw;
1648         u32 tctl, rctl;
1649         int i;
1650
1651         /* signal that we're down so the interrupt handler does not
1652          * reschedule our watchdog timer
1653          */
1654         set_bit(__IGB_DOWN, &adapter->state);
1655
1656         /* disable receives in the hardware */
1657         rctl = rd32(E1000_RCTL);
1658         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1659         /* flush and sleep below */
1660
1661         netif_tx_stop_all_queues(netdev);
1662
1663         /* disable transmits in the hardware */
1664         tctl = rd32(E1000_TCTL);
1665         tctl &= ~E1000_TCTL_EN;
1666         wr32(E1000_TCTL, tctl);
1667         /* flush both disables and wait for them to finish */
1668         wrfl();
1669         msleep(10);
1670
1671         for (i = 0; i < adapter->num_q_vectors; i++)
1672                 napi_disable(&(adapter->q_vector[i]->napi));
1673
1674         igb_irq_disable(adapter);
1675
1676         del_timer_sync(&adapter->watchdog_timer);
1677         del_timer_sync(&adapter->phy_info_timer);
1678
1679         netif_carrier_off(netdev);
1680
1681         /* record the stats before reset*/
1682         spin_lock(&adapter->stats64_lock);
1683         igb_update_stats(adapter, &adapter->stats64);
1684         spin_unlock(&adapter->stats64_lock);
1685
1686         adapter->link_speed = 0;
1687         adapter->link_duplex = 0;
1688
1689         if (!pci_channel_offline(adapter->pdev))
1690                 igb_reset(adapter);
1691         igb_clean_all_tx_rings(adapter);
1692         igb_clean_all_rx_rings(adapter);
1693 #ifdef CONFIG_IGB_DCA
1694
1695         /* since we reset the hardware DCA settings were cleared */
1696         igb_setup_dca(adapter);
1697 #endif
1698 }
1699
1700 void igb_reinit_locked(struct igb_adapter *adapter)
1701 {
1702         WARN_ON(in_interrupt());
1703         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1704                 msleep(1);
1705         igb_down(adapter);
1706         igb_up(adapter);
1707         clear_bit(__IGB_RESETTING, &adapter->state);
1708 }
1709
1710 void igb_reset(struct igb_adapter *adapter)
1711 {
1712         struct pci_dev *pdev = adapter->pdev;
1713         struct e1000_hw *hw = &adapter->hw;
1714         struct e1000_mac_info *mac = &hw->mac;
1715         struct e1000_fc_info *fc = &hw->fc;
1716         u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
1717
1718         /* Repartition Pba for greater than 9k mtu
1719          * To take effect CTRL.RST is required.
1720          */
1721         switch (mac->type) {
1722         case e1000_i350:
1723         case e1000_i354:
1724         case e1000_82580:
1725                 pba = rd32(E1000_RXPBS);
1726                 pba = igb_rxpbs_adjust_82580(pba);
1727                 break;
1728         case e1000_82576:
1729                 pba = rd32(E1000_RXPBS);
1730                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1731                 break;
1732         case e1000_82575:
1733         case e1000_i210:
1734         case e1000_i211:
1735         default:
1736                 pba = E1000_PBA_34K;
1737                 break;
1738         }
1739
1740         if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1741             (mac->type < e1000_82576)) {
1742                 /* adjust PBA for jumbo frames */
1743                 wr32(E1000_PBA, pba);
1744
1745                 /* To maintain wire speed transmits, the Tx FIFO should be
1746                  * large enough to accommodate two full transmit packets,
1747                  * rounded up to the next 1KB and expressed in KB.  Likewise,
1748                  * the Rx FIFO should be large enough to accommodate at least
1749                  * one full receive packet and is similarly rounded up and
1750                  * expressed in KB.
1751                  */
1752                 pba = rd32(E1000_PBA);
1753                 /* upper 16 bits has Tx packet buffer allocation size in KB */
1754                 tx_space = pba >> 16;
1755                 /* lower 16 bits has Rx packet buffer allocation size in KB */
1756                 pba &= 0xffff;
1757                 /* the Tx fifo also stores 16 bytes of information about the Tx
1758                  * but don't include ethernet FCS because hardware appends it
1759                  */
1760                 min_tx_space = (adapter->max_frame_size +
1761                                 sizeof(union e1000_adv_tx_desc) -
1762                                 ETH_FCS_LEN) * 2;
1763                 min_tx_space = ALIGN(min_tx_space, 1024);
1764                 min_tx_space >>= 10;
1765                 /* software strips receive CRC, so leave room for it */
1766                 min_rx_space = adapter->max_frame_size;
1767                 min_rx_space = ALIGN(min_rx_space, 1024);
1768                 min_rx_space >>= 10;
1769
1770                 /* If current Tx allocation is less than the min Tx FIFO size,
1771                  * and the min Tx FIFO size is less than the current Rx FIFO
1772                  * allocation, take space away from current Rx allocation
1773                  */
1774                 if (tx_space < min_tx_space &&
1775                     ((min_tx_space - tx_space) < pba)) {
1776                         pba = pba - (min_tx_space - tx_space);
1777
1778                         /* if short on Rx space, Rx wins and must trump Tx
1779                          * adjustment
1780                          */
1781                         if (pba < min_rx_space)
1782                                 pba = min_rx_space;
1783                 }
1784                 wr32(E1000_PBA, pba);
1785         }
1786
1787         /* flow control settings */
1788         /* The high water mark must be low enough to fit one full frame
1789          * (or the size used for early receive) above it in the Rx FIFO.
1790          * Set it to the lower of:
1791          * - 90% of the Rx FIFO size, or
1792          * - the full Rx FIFO size minus one full frame
1793          */
1794         hwm = min(((pba << 10) * 9 / 10),
1795                         ((pba << 10) - 2 * adapter->max_frame_size));
1796
1797         fc->high_water = hwm & 0xFFFFFFF0;      /* 16-byte granularity */
1798         fc->low_water = fc->high_water - 16;
1799         fc->pause_time = 0xFFFF;
1800         fc->send_xon = 1;
1801         fc->current_mode = fc->requested_mode;
1802
1803         /* disable receive for all VFs and wait one second */
1804         if (adapter->vfs_allocated_count) {
1805                 int i;
1806                 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1807                         adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
1808
1809                 /* ping all the active vfs to let them know we are going down */
1810                 igb_ping_all_vfs(adapter);
1811
1812                 /* disable transmits and receives */
1813                 wr32(E1000_VFRE, 0);
1814                 wr32(E1000_VFTE, 0);
1815         }
1816
1817         /* Allow time for pending master requests to run */
1818         hw->mac.ops.reset_hw(hw);
1819         wr32(E1000_WUC, 0);
1820
1821         if (hw->mac.ops.init_hw(hw))
1822                 dev_err(&pdev->dev, "Hardware Error\n");
1823
1824         /* Flow control settings reset on hardware reset, so guarantee flow
1825          * control is off when forcing speed.
1826          */
1827         if (!hw->mac.autoneg)
1828                 igb_force_mac_fc(hw);
1829
1830         igb_init_dmac(adapter, pba);
1831 #ifdef CONFIG_IGB_HWMON
1832         /* Re-initialize the thermal sensor on i350 devices. */
1833         if (!test_bit(__IGB_DOWN, &adapter->state)) {
1834                 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1835                         /* If present, re-initialize the external thermal sensor
1836                          * interface.
1837                          */
1838                         if (adapter->ets)
1839                                 mac->ops.init_thermal_sensor_thresh(hw);
1840                 }
1841         }
1842 #endif
1843         if (!netif_running(adapter->netdev))
1844                 igb_power_down_link(adapter);
1845
1846         igb_update_mng_vlan(adapter);
1847
1848         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1849         wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1850
1851         /* Re-enable PTP, where applicable. */
1852         igb_ptp_reset(adapter);
1853
1854         igb_get_phy_info(hw);
1855 }
1856
1857 static netdev_features_t igb_fix_features(struct net_device *netdev,
1858         netdev_features_t features)
1859 {
1860         /* Since there is no support for separate Rx/Tx vlan accel
1861          * enable/disable make sure Tx flag is always in same state as Rx.
1862          */
1863         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1864                 features |= NETIF_F_HW_VLAN_CTAG_TX;
1865         else
1866                 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
1867
1868         return features;
1869 }
1870
1871 static int igb_set_features(struct net_device *netdev,
1872         netdev_features_t features)
1873 {
1874         netdev_features_t changed = netdev->features ^ features;
1875         struct igb_adapter *adapter = netdev_priv(netdev);
1876
1877         if (changed & NETIF_F_HW_VLAN_CTAG_RX)
1878                 igb_vlan_mode(netdev, features);
1879
1880         if (!(changed & NETIF_F_RXALL))
1881                 return 0;
1882
1883         netdev->features = features;
1884
1885         if (netif_running(netdev))
1886                 igb_reinit_locked(adapter);
1887         else
1888                 igb_reset(adapter);
1889
1890         return 0;
1891 }
1892
1893 static const struct net_device_ops igb_netdev_ops = {
1894         .ndo_open               = igb_open,
1895         .ndo_stop               = igb_close,
1896         .ndo_start_xmit         = igb_xmit_frame,
1897         .ndo_get_stats64        = igb_get_stats64,
1898         .ndo_set_rx_mode        = igb_set_rx_mode,
1899         .ndo_set_mac_address    = igb_set_mac,
1900         .ndo_change_mtu         = igb_change_mtu,
1901         .ndo_do_ioctl           = igb_ioctl,
1902         .ndo_tx_timeout         = igb_tx_timeout,
1903         .ndo_validate_addr      = eth_validate_addr,
1904         .ndo_vlan_rx_add_vid    = igb_vlan_rx_add_vid,
1905         .ndo_vlan_rx_kill_vid   = igb_vlan_rx_kill_vid,
1906         .ndo_set_vf_mac         = igb_ndo_set_vf_mac,
1907         .ndo_set_vf_vlan        = igb_ndo_set_vf_vlan,
1908         .ndo_set_vf_tx_rate     = igb_ndo_set_vf_bw,
1909         .ndo_set_vf_spoofchk    = igb_ndo_set_vf_spoofchk,
1910         .ndo_get_vf_config      = igb_ndo_get_vf_config,
1911 #ifdef CONFIG_NET_POLL_CONTROLLER
1912         .ndo_poll_controller    = igb_netpoll,
1913 #endif
1914         .ndo_fix_features       = igb_fix_features,
1915         .ndo_set_features       = igb_set_features,
1916 };
1917
1918 /**
1919  * igb_set_fw_version - Configure version string for ethtool
1920  * @adapter: adapter struct
1921  **/
1922 void igb_set_fw_version(struct igb_adapter *adapter)
1923 {
1924         struct e1000_hw *hw = &adapter->hw;
1925         struct e1000_fw_version fw;
1926
1927         igb_get_fw_version(hw, &fw);
1928
1929         switch (hw->mac.type) {
1930         case e1000_i211:
1931                 snprintf(adapter->fw_version, sizeof(adapter->fw_version),
1932                          "%2d.%2d-%d",
1933                          fw.invm_major, fw.invm_minor, fw.invm_img_type);
1934                 break;
1935
1936         default:
1937                 /* if option is rom valid, display its version too */
1938                 if (fw.or_valid) {
1939                         snprintf(adapter->fw_version,
1940                                  sizeof(adapter->fw_version),
1941                                  "%d.%d, 0x%08x, %d.%d.%d",
1942                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
1943                                  fw.or_major, fw.or_build, fw.or_patch);
1944                 /* no option rom */
1945                 } else {
1946                         snprintf(adapter->fw_version,
1947                                  sizeof(adapter->fw_version),
1948                                  "%d.%d, 0x%08x",
1949                                  fw.eep_major, fw.eep_minor, fw.etrack_id);
1950                 }
1951                 break;
1952         }
1953         return;
1954 }
1955
1956 /**
1957  *  igb_init_i2c - Init I2C interface
1958  *  @adapter: pointer to adapter structure
1959  **/
1960 static s32 igb_init_i2c(struct igb_adapter *adapter)
1961 {
1962         s32 status = E1000_SUCCESS;
1963
1964         /* I2C interface supported on i350 devices */
1965         if (adapter->hw.mac.type != e1000_i350)
1966                 return E1000_SUCCESS;
1967
1968         /* Initialize the i2c bus which is controlled by the registers.
1969          * This bus will use the i2c_algo_bit structue that implements
1970          * the protocol through toggling of the 4 bits in the register.
1971          */
1972         adapter->i2c_adap.owner = THIS_MODULE;
1973         adapter->i2c_algo = igb_i2c_algo;
1974         adapter->i2c_algo.data = adapter;
1975         adapter->i2c_adap.algo_data = &adapter->i2c_algo;
1976         adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
1977         strlcpy(adapter->i2c_adap.name, "igb BB",
1978                 sizeof(adapter->i2c_adap.name));
1979         status = i2c_bit_add_bus(&adapter->i2c_adap);
1980         return status;
1981 }
1982
1983 /**
1984  *  igb_probe - Device Initialization Routine
1985  *  @pdev: PCI device information struct
1986  *  @ent: entry in igb_pci_tbl
1987  *
1988  *  Returns 0 on success, negative on failure
1989  *
1990  *  igb_probe initializes an adapter identified by a pci_dev structure.
1991  *  The OS initialization, configuring of the adapter private structure,
1992  *  and a hardware reset occur.
1993  **/
1994 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1995 {
1996         struct net_device *netdev;
1997         struct igb_adapter *adapter;
1998         struct e1000_hw *hw;
1999         u16 eeprom_data = 0;
2000         s32 ret_val;
2001         static int global_quad_port_a; /* global quad port a indication */
2002         const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2003         unsigned long mmio_start, mmio_len;
2004         int err, pci_using_dac;
2005         u8 part_str[E1000_PBANUM_LENGTH];
2006
2007         /* Catch broken hardware that put the wrong VF device ID in
2008          * the PCIe SR-IOV capability.
2009          */
2010         if (pdev->is_virtfn) {
2011                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
2012                         pci_name(pdev), pdev->vendor, pdev->device);
2013                 return -EINVAL;
2014         }
2015
2016         err = pci_enable_device_mem(pdev);
2017         if (err)
2018                 return err;
2019
2020         pci_using_dac = 0;
2021         err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
2022         if (!err) {
2023                 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
2024                 if (!err)
2025                         pci_using_dac = 1;
2026         } else {
2027                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
2028                 if (err) {
2029                         err = dma_set_coherent_mask(&pdev->dev,
2030                                                     DMA_BIT_MASK(32));
2031                         if (err) {
2032                                 dev_err(&pdev->dev,
2033                                         "No usable DMA configuration, aborting\n");
2034                                 goto err_dma;
2035                         }
2036                 }
2037         }
2038
2039         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
2040                                            IORESOURCE_MEM),
2041                                            igb_driver_name);
2042         if (err)
2043                 goto err_pci_reg;
2044
2045         pci_enable_pcie_error_reporting(pdev);
2046
2047         pci_set_master(pdev);
2048         pci_save_state(pdev);
2049
2050         err = -ENOMEM;
2051         netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
2052                                    IGB_MAX_TX_QUEUES);
2053         if (!netdev)
2054                 goto err_alloc_etherdev;
2055
2056         SET_NETDEV_DEV(netdev, &pdev->dev);
2057
2058         pci_set_drvdata(pdev, netdev);
2059         adapter = netdev_priv(netdev);
2060         adapter->netdev = netdev;
2061         adapter->pdev = pdev;
2062         hw = &adapter->hw;
2063         hw->back = adapter;
2064         adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
2065
2066         mmio_start = pci_resource_start(pdev, 0);
2067         mmio_len = pci_resource_len(pdev, 0);
2068
2069         err = -EIO;
2070         hw->hw_addr = ioremap(mmio_start, mmio_len);
2071         if (!hw->hw_addr)
2072                 goto err_ioremap;
2073
2074         netdev->netdev_ops = &igb_netdev_ops;
2075         igb_set_ethtool_ops(netdev);
2076         netdev->watchdog_timeo = 5 * HZ;
2077
2078         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2079
2080         netdev->mem_start = mmio_start;
2081         netdev->mem_end = mmio_start + mmio_len;
2082
2083         /* PCI config space info */
2084         hw->vendor_id = pdev->vendor;
2085         hw->device_id = pdev->device;
2086         hw->revision_id = pdev->revision;
2087         hw->subsystem_vendor_id = pdev->subsystem_vendor;
2088         hw->subsystem_device_id = pdev->subsystem_device;
2089
2090         /* Copy the default MAC, PHY and NVM function pointers */
2091         memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2092         memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2093         memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2094         /* Initialize skew-specific constants */
2095         err = ei->get_invariants(hw);
2096         if (err)
2097                 goto err_sw_init;
2098
2099         /* setup the private structure */
2100         err = igb_sw_init(adapter);
2101         if (err)
2102                 goto err_sw_init;
2103
2104         igb_get_bus_info_pcie(hw);
2105
2106         hw->phy.autoneg_wait_to_complete = false;
2107
2108         /* Copper options */
2109         if (hw->phy.media_type == e1000_media_type_copper) {
2110                 hw->phy.mdix = AUTO_ALL_MODES;
2111                 hw->phy.disable_polarity_correction = false;
2112                 hw->phy.ms_type = e1000_ms_hw_default;
2113         }
2114
2115         if (igb_check_reset_block(hw))
2116                 dev_info(&pdev->dev,
2117                         "PHY reset is blocked due to SOL/IDER session.\n");
2118
2119         /* features is initialized to 0 in allocation, it might have bits
2120          * set by igb_sw_init so we should use an or instead of an
2121          * assignment.
2122          */
2123         netdev->features |= NETIF_F_SG |
2124                             NETIF_F_IP_CSUM |
2125                             NETIF_F_IPV6_CSUM |
2126                             NETIF_F_TSO |
2127                             NETIF_F_TSO6 |
2128                             NETIF_F_RXHASH |
2129                             NETIF_F_RXCSUM |
2130                             NETIF_F_HW_VLAN_CTAG_RX |
2131                             NETIF_F_HW_VLAN_CTAG_TX;
2132
2133         /* copy netdev features into list of user selectable features */
2134         netdev->hw_features |= netdev->features;
2135         netdev->hw_features |= NETIF_F_RXALL;
2136
2137         /* set this bit last since it cannot be part of hw_features */
2138         netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2139
2140         netdev->vlan_features |= NETIF_F_TSO |
2141                                  NETIF_F_TSO6 |
2142                                  NETIF_F_IP_CSUM |
2143                                  NETIF_F_IPV6_CSUM |
2144                                  NETIF_F_SG;
2145
2146         netdev->priv_flags |= IFF_SUPP_NOFCS;
2147
2148         if (pci_using_dac) {
2149                 netdev->features |= NETIF_F_HIGHDMA;
2150                 netdev->vlan_features |= NETIF_F_HIGHDMA;
2151         }
2152
2153         if (hw->mac.type >= e1000_82576) {
2154                 netdev->hw_features |= NETIF_F_SCTP_CSUM;
2155                 netdev->features |= NETIF_F_SCTP_CSUM;
2156         }
2157
2158         netdev->priv_flags |= IFF_UNICAST_FLT;
2159
2160         adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
2161
2162         /* before reading the NVM, reset the controller to put the device in a
2163          * known good starting state
2164          */
2165         hw->mac.ops.reset_hw(hw);
2166
2167         /* make sure the NVM is good , i211 parts have special NVM that
2168          * doesn't contain a checksum
2169          */
2170         if (hw->mac.type != e1000_i211) {
2171                 if (hw->nvm.ops.validate(hw) < 0) {
2172                         dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2173                         err = -EIO;
2174                         goto err_eeprom;
2175                 }
2176         }
2177
2178         /* copy the MAC address out of the NVM */
2179         if (hw->mac.ops.read_mac_addr(hw))
2180                 dev_err(&pdev->dev, "NVM Read Error\n");
2181
2182         memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2183
2184         if (!is_valid_ether_addr(netdev->dev_addr)) {
2185                 dev_err(&pdev->dev, "Invalid MAC Address\n");
2186                 err = -EIO;
2187                 goto err_eeprom;
2188         }
2189
2190         /* get firmware version for ethtool -i */
2191         igb_set_fw_version(adapter);
2192
2193         setup_timer(&adapter->watchdog_timer, igb_watchdog,
2194                     (unsigned long) adapter);
2195         setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
2196                     (unsigned long) adapter);
2197
2198         INIT_WORK(&adapter->reset_task, igb_reset_task);
2199         INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2200
2201         /* Initialize link properties that are user-changeable */
2202         adapter->fc_autoneg = true;
2203         hw->mac.autoneg = true;
2204         hw->phy.autoneg_advertised = 0x2f;
2205
2206         hw->fc.requested_mode = e1000_fc_default;
2207         hw->fc.current_mode = e1000_fc_default;
2208
2209         igb_validate_mdi_setting(hw);
2210
2211         /* By default, support wake on port A */
2212         if (hw->bus.func == 0)
2213                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2214
2215         /* Check the NVM for wake support on non-port A ports */
2216         if (hw->mac.type >= e1000_82580)
2217                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2218                                  NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2219                                  &eeprom_data);
2220         else if (hw->bus.func == 1)
2221                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2222
2223         if (eeprom_data & IGB_EEPROM_APME)
2224                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2225
2226         /* now that we have the eeprom settings, apply the special cases where
2227          * the eeprom may be wrong or the board simply won't support wake on
2228          * lan on a particular port
2229          */
2230         switch (pdev->device) {
2231         case E1000_DEV_ID_82575GB_QUAD_COPPER:
2232                 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2233                 break;
2234         case E1000_DEV_ID_82575EB_FIBER_SERDES:
2235         case E1000_DEV_ID_82576_FIBER:
2236         case E1000_DEV_ID_82576_SERDES:
2237                 /* Wake events only supported on port A for dual fiber
2238                  * regardless of eeprom setting
2239                  */
2240                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2241                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2242                 break;
2243         case E1000_DEV_ID_82576_QUAD_COPPER:
2244         case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2245                 /* if quad port adapter, disable WoL on all but port A */
2246                 if (global_quad_port_a != 0)
2247                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2248                 else
2249                         adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2250                 /* Reset for multiple quad port adapters */
2251                 if (++global_quad_port_a == 4)
2252                         global_quad_port_a = 0;
2253                 break;
2254         default:
2255                 /* If the device can't wake, don't set software support */
2256                 if (!device_can_wakeup(&adapter->pdev->dev))
2257                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2258         }
2259
2260         /* initialize the wol settings based on the eeprom settings */
2261         if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2262                 adapter->wol |= E1000_WUFC_MAG;
2263
2264         /* Some vendors want WoL disabled by default, but still supported */
2265         if ((hw->mac.type == e1000_i350) &&
2266             (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2267                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2268                 adapter->wol = 0;
2269         }
2270
2271         device_set_wakeup_enable(&adapter->pdev->dev,
2272                                  adapter->flags & IGB_FLAG_WOL_SUPPORTED);
2273
2274         /* reset the hardware with the new settings */
2275         igb_reset(adapter);
2276
2277         /* Init the I2C interface */
2278         err = igb_init_i2c(adapter);
2279         if (err) {
2280                 dev_err(&pdev->dev, "failed to init i2c interface\n");
2281                 goto err_eeprom;
2282         }
2283
2284         /* let the f/w know that the h/w is now under the control of the
2285          * driver. */
2286         igb_get_hw_control(adapter);
2287
2288         strcpy(netdev->name, "eth%d");
2289         err = register_netdev(netdev);
2290         if (err)
2291                 goto err_register;
2292
2293         /* carrier off reporting is important to ethtool even BEFORE open */
2294         netif_carrier_off(netdev);
2295
2296 #ifdef CONFIG_IGB_DCA
2297         if (dca_add_requester(&pdev->dev) == 0) {
2298                 adapter->flags |= IGB_FLAG_DCA_ENABLED;
2299                 dev_info(&pdev->dev, "DCA enabled\n");
2300                 igb_setup_dca(adapter);
2301         }
2302
2303 #endif
2304 #ifdef CONFIG_IGB_HWMON
2305         /* Initialize the thermal sensor on i350 devices. */
2306         if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2307                 u16 ets_word;
2308
2309                 /* Read the NVM to determine if this i350 device supports an
2310                  * external thermal sensor.
2311                  */
2312                 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2313                 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2314                         adapter->ets = true;
2315                 else
2316                         adapter->ets = false;
2317                 if (igb_sysfs_init(adapter))
2318                         dev_err(&pdev->dev,
2319                                 "failed to allocate sysfs resources\n");
2320         } else {
2321                 adapter->ets = false;
2322         }
2323 #endif
2324         /* do hw tstamp init after resetting */
2325         igb_ptp_init(adapter);
2326
2327         dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2328         /* print bus type/speed/width info, not applicable to i354 */
2329         if (hw->mac.type != e1000_i354) {
2330                 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2331                          netdev->name,
2332                          ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2333                           (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2334                            "unknown"),
2335                          ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2336                           "Width x4" :
2337                           (hw->bus.width == e1000_bus_width_pcie_x2) ?
2338                           "Width x2" :
2339                           (hw->bus.width == e1000_bus_width_pcie_x1) ?
2340                           "Width x1" : "unknown"), netdev->dev_addr);
2341         }
2342
2343         ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2344         if (ret_val)
2345                 strcpy(part_str, "Unknown");
2346         dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
2347         dev_info(&pdev->dev,
2348                 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2349                 adapter->msix_entries ? "MSI-X" :
2350                 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2351                 adapter->num_rx_queues, adapter->num_tx_queues);
2352         switch (hw->mac.type) {
2353         case e1000_i350:
2354         case e1000_i210:
2355         case e1000_i211:
2356                 igb_set_eee_i350(hw);
2357                 break;
2358         case e1000_i354:
2359                 if (hw->phy.media_type == e1000_media_type_copper) {
2360                         if ((rd32(E1000_CTRL_EXT) &
2361                             E1000_CTRL_EXT_LINK_MODE_SGMII))
2362                                 igb_set_eee_i354(hw);
2363                 }
2364                 break;
2365         default:
2366                 break;
2367         }
2368
2369         pm_runtime_put_noidle(&pdev->dev);
2370         return 0;
2371
2372 err_register:
2373         igb_release_hw_control(adapter);
2374         memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
2375 err_eeprom:
2376         if (!igb_check_reset_block(hw))
2377                 igb_reset_phy(hw);
2378
2379         if (hw->flash_address)
2380                 iounmap(hw->flash_address);
2381 err_sw_init:
2382         igb_clear_interrupt_scheme(adapter);
2383         iounmap(hw->hw_addr);
2384 err_ioremap:
2385         free_netdev(netdev);
2386 err_alloc_etherdev:
2387         pci_release_selected_regions(pdev,
2388                                      pci_select_bars(pdev, IORESOURCE_MEM));
2389 err_pci_reg:
2390 err_dma:
2391         pci_disable_device(pdev);
2392         return err;
2393 }
2394
2395 #ifdef CONFIG_PCI_IOV
2396 static int  igb_disable_sriov(struct pci_dev *pdev)
2397 {
2398         struct net_device *netdev = pci_get_drvdata(pdev);
2399         struct igb_adapter *adapter = netdev_priv(netdev);
2400         struct e1000_hw *hw = &adapter->hw;
2401
2402         /* reclaim resources allocated to VFs */
2403         if (adapter->vf_data) {
2404                 /* disable iov and allow time for transactions to clear */
2405                 if (igb_vfs_are_assigned(adapter)) {
2406                         dev_warn(&pdev->dev,
2407                                  "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2408                         return -EPERM;
2409                 } else {
2410                         pci_disable_sriov(pdev);
2411                         msleep(500);
2412                 }
2413
2414                 kfree(adapter->vf_data);
2415                 adapter->vf_data = NULL;
2416                 adapter->vfs_allocated_count = 0;
2417                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2418                 wrfl();
2419                 msleep(100);
2420                 dev_info(&pdev->dev, "IOV Disabled\n");
2421
2422                 /* Re-enable DMA Coalescing flag since IOV is turned off */
2423                 adapter->flags |= IGB_FLAG_DMAC;
2424         }
2425
2426         return 0;
2427 }
2428
2429 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2430 {
2431         struct net_device *netdev = pci_get_drvdata(pdev);
2432         struct igb_adapter *adapter = netdev_priv(netdev);
2433         int old_vfs = pci_num_vf(pdev);
2434         int err = 0;
2435         int i;
2436
2437         if (!num_vfs)
2438                 goto out;
2439         else if (old_vfs && old_vfs == num_vfs)
2440                 goto out;
2441         else if (old_vfs && old_vfs != num_vfs)
2442                 err = igb_disable_sriov(pdev);
2443
2444         if (err)
2445                 goto out;
2446
2447         if (num_vfs > 7) {
2448                 err = -EPERM;
2449                 goto out;
2450         }
2451
2452         adapter->vfs_allocated_count = num_vfs;
2453
2454         adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2455                                 sizeof(struct vf_data_storage), GFP_KERNEL);
2456
2457         /* if allocation failed then we do not support SR-IOV */
2458         if (!adapter->vf_data) {
2459                 adapter->vfs_allocated_count = 0;
2460                 dev_err(&pdev->dev,
2461                         "Unable to allocate memory for VF Data Storage\n");
2462                 err = -ENOMEM;
2463                 goto out;
2464         }
2465
2466         err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2467         if (err)
2468                 goto err_out;
2469
2470         dev_info(&pdev->dev, "%d VFs allocated\n",
2471                  adapter->vfs_allocated_count);
2472         for (i = 0; i < adapter->vfs_allocated_count; i++)
2473                 igb_vf_configure(adapter, i);
2474
2475         /* DMA Coalescing is not supported in IOV mode. */
2476         adapter->flags &= ~IGB_FLAG_DMAC;
2477         goto out;
2478
2479 err_out:
2480         kfree(adapter->vf_data);
2481         adapter->vf_data = NULL;
2482         adapter->vfs_allocated_count = 0;
2483 out:
2484         return err;
2485 }
2486
2487 #endif
2488 /**
2489  *  igb_remove_i2c - Cleanup  I2C interface
2490  *  @adapter: pointer to adapter structure
2491  **/
2492 static void igb_remove_i2c(struct igb_adapter *adapter)
2493 {
2494         /* free the adapter bus structure */
2495         i2c_del_adapter(&adapter->i2c_adap);
2496 }
2497
2498 /**
2499  *  igb_remove - Device Removal Routine
2500  *  @pdev: PCI device information struct
2501  *
2502  *  igb_remove is called by the PCI subsystem to alert the driver
2503  *  that it should release a PCI device.  The could be caused by a
2504  *  Hot-Plug event, or because the driver is going to be removed from
2505  *  memory.
2506  **/
2507 static void igb_remove(struct pci_dev *pdev)
2508 {
2509         struct net_device *netdev = pci_get_drvdata(pdev);
2510         struct igb_adapter *adapter = netdev_priv(netdev);
2511         struct e1000_hw *hw = &adapter->hw;
2512
2513         pm_runtime_get_noresume(&pdev->dev);
2514 #ifdef CONFIG_IGB_HWMON
2515         igb_sysfs_exit(adapter);
2516 #endif
2517         igb_remove_i2c(adapter);
2518         igb_ptp_stop(adapter);
2519         /* The watchdog timer may be rescheduled, so explicitly
2520          * disable watchdog from being rescheduled.
2521          */
2522         set_bit(__IGB_DOWN, &adapter->state);
2523         del_timer_sync(&adapter->watchdog_timer);
2524         del_timer_sync(&adapter->phy_info_timer);
2525
2526         cancel_work_sync(&adapter->reset_task);
2527         cancel_work_sync(&adapter->watchdog_task);
2528
2529 #ifdef CONFIG_IGB_DCA
2530         if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
2531                 dev_info(&pdev->dev, "DCA disabled\n");
2532                 dca_remove_requester(&pdev->dev);
2533                 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
2534                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
2535         }
2536 #endif
2537
2538         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
2539          * would have already happened in close and is redundant.
2540          */
2541         igb_release_hw_control(adapter);
2542
2543         unregister_netdev(netdev);
2544
2545         igb_clear_interrupt_scheme(adapter);
2546
2547 #ifdef CONFIG_PCI_IOV
2548         igb_disable_sriov(pdev);
2549 #endif
2550
2551         iounmap(hw->hw_addr);
2552         if (hw->flash_address)
2553                 iounmap(hw->flash_address);
2554         pci_release_selected_regions(pdev,
2555                                      pci_select_bars(pdev, IORESOURCE_MEM));
2556
2557         kfree(adapter->shadow_vfta);
2558         free_netdev(netdev);
2559
2560         pci_disable_pcie_error_reporting(pdev);
2561
2562         pci_disable_device(pdev);
2563 }
2564
2565 /**
2566  *  igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2567  *  @adapter: board private structure to initialize
2568  *
2569  *  This function initializes the vf specific data storage and then attempts to
2570  *  allocate the VFs.  The reason for ordering it this way is because it is much
2571  *  mor expensive time wise to disable SR-IOV than it is to allocate and free
2572  *  the memory for the VFs.
2573  **/
2574 static void igb_probe_vfs(struct igb_adapter *adapter)
2575 {
2576 #ifdef CONFIG_PCI_IOV
2577         struct pci_dev *pdev = adapter->pdev;
2578         struct e1000_hw *hw = &adapter->hw;
2579
2580         /* Virtualization features not supported on i210 family. */
2581         if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2582                 return;
2583
2584         pci_sriov_set_totalvfs(pdev, 7);
2585         igb_enable_sriov(pdev, max_vfs);
2586
2587 #endif /* CONFIG_PCI_IOV */
2588 }
2589
2590 static void igb_init_queue_configuration(struct igb_adapter *adapter)
2591 {
2592         struct e1000_hw *hw = &adapter->hw;
2593         u32 max_rss_queues;
2594
2595         /* Determine the maximum number of RSS queues supported. */
2596         switch (hw->mac.type) {
2597         case e1000_i211:
2598                 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2599                 break;
2600         case e1000_82575:
2601         case e1000_i210:
2602                 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2603                 break;
2604         case e1000_i350:
2605                 /* I350 cannot do RSS and SR-IOV at the same time */
2606                 if (!!adapter->vfs_allocated_count) {
2607                         max_rss_queues = 1;
2608                         break;
2609                 }
2610                 /* fall through */
2611         case e1000_82576:
2612                 if (!!adapter->vfs_allocated_count) {
2613                         max_rss_queues = 2;
2614                         break;
2615                 }
2616                 /* fall through */
2617         case e1000_82580:
2618         case e1000_i354:
2619         default:
2620                 max_rss_queues = IGB_MAX_RX_QUEUES;
2621                 break;
2622         }
2623
2624         adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2625
2626         /* Determine if we need to pair queues. */
2627         switch (hw->mac.type) {
2628         case e1000_82575:
2629         case e1000_i211:
2630                 /* Device supports enough interrupts without queue pairing. */
2631                 break;
2632         case e1000_82576:
2633                 /* If VFs are going to be allocated with RSS queues then we
2634                  * should pair the queues in order to conserve interrupts due
2635                  * to limited supply.
2636                  */
2637                 if ((adapter->rss_queues > 1) &&
2638                     (adapter->vfs_allocated_count > 6))
2639                         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2640                 /* fall through */
2641         case e1000_82580:
2642         case e1000_i350:
2643         case e1000_i354:
2644         case e1000_i210:
2645         default:
2646                 /* If rss_queues > half of max_rss_queues, pair the queues in
2647                  * order to conserve interrupts due to limited supply.
2648                  */
2649                 if (adapter->rss_queues > (max_rss_queues / 2))
2650                         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2651                 break;
2652         }
2653 }
2654
2655 /**
2656  *  igb_sw_init - Initialize general software structures (struct igb_adapter)
2657  *  @adapter: board private structure to initialize
2658  *
2659  *  igb_sw_init initializes the Adapter private data structure.
2660  *  Fields are initialized based on PCI device information and
2661  *  OS network device settings (MTU size).
2662  **/
2663 static int igb_sw_init(struct igb_adapter *adapter)
2664 {
2665         struct e1000_hw *hw = &adapter->hw;
2666         struct net_device *netdev = adapter->netdev;
2667         struct pci_dev *pdev = adapter->pdev;
2668
2669         pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2670
2671         /* set default ring sizes */
2672         adapter->tx_ring_count = IGB_DEFAULT_TXD;
2673         adapter->rx_ring_count = IGB_DEFAULT_RXD;
2674
2675         /* set default ITR values */
2676         adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2677         adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2678
2679         /* set default work limits */
2680         adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2681
2682         adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2683                                   VLAN_HLEN;
2684         adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2685
2686         spin_lock_init(&adapter->stats64_lock);
2687 #ifdef CONFIG_PCI_IOV
2688         switch (hw->mac.type) {
2689         case e1000_82576:
2690         case e1000_i350:
2691                 if (max_vfs > 7) {
2692                         dev_warn(&pdev->dev,
2693                                  "Maximum of 7 VFs per PF, using max\n");
2694                         max_vfs = adapter->vfs_allocated_count = 7;
2695                 } else
2696                         adapter->vfs_allocated_count = max_vfs;
2697                 if (adapter->vfs_allocated_count)
2698                         dev_warn(&pdev->dev,
2699                                  "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2700                 break;
2701         default:
2702                 break;
2703         }
2704 #endif /* CONFIG_PCI_IOV */
2705
2706         igb_init_queue_configuration(adapter);
2707
2708         /* Setup and initialize a copy of the hw vlan table array */
2709         adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2710                                        GFP_ATOMIC);
2711
2712         /* This call may decrease the number of queues */
2713         if (igb_init_interrupt_scheme(adapter, true)) {
2714                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2715                 return -ENOMEM;
2716         }
2717
2718         igb_probe_vfs(adapter);
2719
2720         /* Explicitly disable IRQ since the NIC can be in any state. */
2721         igb_irq_disable(adapter);
2722
2723         if (hw->mac.type >= e1000_i350)
2724                 adapter->flags &= ~IGB_FLAG_DMAC;
2725
2726         set_bit(__IGB_DOWN, &adapter->state);
2727         return 0;
2728 }
2729
2730 /**
2731  *  igb_open - Called when a network interface is made active
2732  *  @netdev: network interface device structure
2733  *
2734  *  Returns 0 on success, negative value on failure
2735  *
2736  *  The open entry point is called when a network interface is made
2737  *  active by the system (IFF_UP).  At this point all resources needed
2738  *  for transmit and receive operations are allocated, the interrupt
2739  *  handler is registered with the OS, the watchdog timer is started,
2740  *  and the stack is notified that the interface is ready.
2741  **/
2742 static int __igb_open(struct net_device *netdev, bool resuming)
2743 {
2744         struct igb_adapter *adapter = netdev_priv(netdev);
2745         struct e1000_hw *hw = &adapter->hw;
2746         struct pci_dev *pdev = adapter->pdev;
2747         int err;
2748         int i;
2749
2750         /* disallow open during test */
2751         if (test_bit(__IGB_TESTING, &adapter->state)) {
2752                 WARN_ON(resuming);
2753                 return -EBUSY;
2754         }
2755
2756         if (!resuming)
2757                 pm_runtime_get_sync(&pdev->dev);
2758
2759         netif_carrier_off(netdev);
2760
2761         /* allocate transmit descriptors */
2762         err = igb_setup_all_tx_resources(adapter);
2763         if (err)
2764                 goto err_setup_tx;
2765
2766         /* allocate receive descriptors */
2767         err = igb_setup_all_rx_resources(adapter);
2768         if (err)
2769                 goto err_setup_rx;
2770
2771         igb_power_up_link(adapter);
2772
2773         /* before we allocate an interrupt, we must be ready to handle it.
2774          * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2775          * as soon as we call pci_request_irq, so we have to setup our
2776          * clean_rx handler before we do so.
2777          */
2778         igb_configure(adapter);
2779
2780         err = igb_request_irq(adapter);
2781         if (err)
2782                 goto err_req_irq;
2783
2784         /* Notify the stack of the actual queue counts. */
2785         err = netif_set_real_num_tx_queues(adapter->netdev,
2786                                            adapter->num_tx_queues);
2787         if (err)
2788                 goto err_set_queues;
2789
2790         err = netif_set_real_num_rx_queues(adapter->netdev,
2791                                            adapter->num_rx_queues);
2792         if (err)
2793                 goto err_set_queues;
2794
2795         /* From here on the code is the same as igb_up() */
2796         clear_bit(__IGB_DOWN, &adapter->state);
2797
2798         for (i = 0; i < adapter->num_q_vectors; i++)
2799                 napi_enable(&(adapter->q_vector[i]->napi));
2800
2801         /* Clear any pending interrupts. */
2802         rd32(E1000_ICR);
2803
2804         igb_irq_enable(adapter);
2805
2806         /* notify VFs that reset has been completed */
2807         if (adapter->vfs_allocated_count) {
2808                 u32 reg_data = rd32(E1000_CTRL_EXT);
2809                 reg_data |= E1000_CTRL_EXT_PFRSTD;
2810                 wr32(E1000_CTRL_EXT, reg_data);
2811         }
2812
2813         netif_tx_start_all_queues(netdev);
2814
2815         if (!resuming)
2816                 pm_runtime_put(&pdev->dev);
2817
2818         /* start the watchdog. */
2819         hw->mac.get_link_status = 1;
2820         schedule_work(&adapter->watchdog_task);
2821
2822         return 0;
2823
2824 err_set_queues:
2825         igb_free_irq(adapter);
2826 err_req_irq:
2827         igb_release_hw_control(adapter);
2828         igb_power_down_link(adapter);
2829         igb_free_all_rx_resources(adapter);
2830 err_setup_rx:
2831         igb_free_all_tx_resources(adapter);
2832 err_setup_tx:
2833         igb_reset(adapter);
2834         if (!resuming)
2835                 pm_runtime_put(&pdev->dev);
2836
2837         return err;
2838 }
2839
2840 static int igb_open(struct net_device *netdev)
2841 {
2842         return __igb_open(netdev, false);
2843 }
2844
2845 /**
2846  *  igb_close - Disables a network interface
2847  *  @netdev: network interface device structure
2848  *
2849  *  Returns 0, this is not allowed to fail
2850  *
2851  *  The close entry point is called when an interface is de-activated
2852  *  by the OS.  The hardware is still under the driver's control, but
2853  *  needs to be disabled.  A global MAC reset is issued to stop the
2854  *  hardware, and all transmit and receive resources are freed.
2855  **/
2856 static int __igb_close(struct net_device *netdev, bool suspending)
2857 {
2858         struct igb_adapter *adapter = netdev_priv(netdev);
2859         struct pci_dev *pdev = adapter->pdev;
2860
2861         WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
2862
2863         if (!suspending)
2864                 pm_runtime_get_sync(&pdev->dev);
2865
2866         igb_down(adapter);
2867         igb_free_irq(adapter);
2868
2869         igb_free_all_tx_resources(adapter);
2870         igb_free_all_rx_resources(adapter);
2871
2872         if (!suspending)
2873                 pm_runtime_put_sync(&pdev->dev);
2874         return 0;
2875 }
2876
2877 static int igb_close(struct net_device *netdev)
2878 {
2879         return __igb_close(netdev, false);
2880 }
2881
2882 /**
2883  *  igb_setup_tx_resources - allocate Tx resources (Descriptors)
2884  *  @tx_ring: tx descriptor ring (for a specific queue) to setup
2885  *
2886  *  Return 0 on success, negative on failure
2887  **/
2888 int igb_setup_tx_resources(struct igb_ring *tx_ring)
2889 {
2890         struct device *dev = tx_ring->dev;
2891         int size;
2892
2893         size = sizeof(struct igb_tx_buffer) * tx_ring->count;
2894
2895         tx_ring->tx_buffer_info = vzalloc(size);
2896         if (!tx_ring->tx_buffer_info)
2897                 goto err;
2898
2899         /* round up to nearest 4K */
2900         tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
2901         tx_ring->size = ALIGN(tx_ring->size, 4096);
2902
2903         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2904                                            &tx_ring->dma, GFP_KERNEL);
2905         if (!tx_ring->desc)
2906                 goto err;
2907
2908         tx_ring->next_to_use = 0;
2909         tx_ring->next_to_clean = 0;
2910
2911         return 0;
2912
2913 err:
2914         vfree(tx_ring->tx_buffer_info);
2915         tx_ring->tx_buffer_info = NULL;
2916         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
2917         return -ENOMEM;
2918 }
2919
2920 /**
2921  *  igb_setup_all_tx_resources - wrapper to allocate Tx resources
2922  *                               (Descriptors) for all queues
2923  *  @adapter: board private structure
2924  *
2925  *  Return 0 on success, negative on failure
2926  **/
2927 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2928 {
2929         struct pci_dev *pdev = adapter->pdev;
2930         int i, err = 0;
2931
2932         for (i = 0; i < adapter->num_tx_queues; i++) {
2933                 err = igb_setup_tx_resources(adapter->tx_ring[i]);
2934                 if (err) {
2935                         dev_err(&pdev->dev,
2936                                 "Allocation for Tx Queue %u failed\n", i);
2937                         for (i--; i >= 0; i--)
2938                                 igb_free_tx_resources(adapter->tx_ring[i]);
2939                         break;
2940                 }
2941         }
2942
2943         return err;
2944 }
2945
2946 /**
2947  *  igb_setup_tctl - configure the transmit control registers
2948  *  @adapter: Board private structure
2949  **/
2950 void igb_setup_tctl(struct igb_adapter *adapter)
2951 {
2952         struct e1000_hw *hw = &adapter->hw;
2953         u32 tctl;
2954
2955         /* disable queue 0 which is enabled by default on 82575 and 82576 */
2956         wr32(E1000_TXDCTL(0), 0);
2957
2958         /* Program the Transmit Control Register */
2959         tctl = rd32(E1000_TCTL);
2960         tctl &= ~E1000_TCTL_CT;
2961         tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2962                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2963
2964         igb_config_collision_dist(hw);
2965
2966         /* Enable transmits */
2967         tctl |= E1000_TCTL_EN;
2968
2969         wr32(E1000_TCTL, tctl);
2970 }
2971
2972 /**
2973  *  igb_configure_tx_ring - Configure transmit ring after Reset
2974  *  @adapter: board private structure
2975  *  @ring: tx ring to configure
2976  *
2977  *  Configure a transmit ring after a reset.
2978  **/
2979 void igb_configure_tx_ring(struct igb_adapter *adapter,
2980                            struct igb_ring *ring)
2981 {
2982         struct e1000_hw *hw = &adapter->hw;
2983         u32 txdctl = 0;
2984         u64 tdba = ring->dma;
2985         int reg_idx = ring->reg_idx;
2986
2987         /* disable the queue */
2988         wr32(E1000_TXDCTL(reg_idx), 0);
2989         wrfl();
2990         mdelay(10);
2991
2992         wr32(E1000_TDLEN(reg_idx),
2993              ring->count * sizeof(union e1000_adv_tx_desc));
2994         wr32(E1000_TDBAL(reg_idx),
2995              tdba & 0x00000000ffffffffULL);
2996         wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2997
2998         ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
2999         wr32(E1000_TDH(reg_idx), 0);
3000         writel(0, ring->tail);
3001
3002         txdctl |= IGB_TX_PTHRESH;
3003         txdctl |= IGB_TX_HTHRESH << 8;
3004         txdctl |= IGB_TX_WTHRESH << 16;
3005
3006         txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3007         wr32(E1000_TXDCTL(reg_idx), txdctl);
3008 }
3009
3010 /**
3011  *  igb_configure_tx - Configure transmit Unit after Reset
3012  *  @adapter: board private structure
3013  *
3014  *  Configure the Tx unit of the MAC after a reset.
3015  **/
3016 static void igb_configure_tx(struct igb_adapter *adapter)
3017 {
3018         int i;
3019
3020         for (i = 0; i < adapter->num_tx_queues; i++)
3021                 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
3022 }
3023
3024 /**
3025  *  igb_setup_rx_resources - allocate Rx resources (Descriptors)
3026  *  @rx_ring: Rx descriptor ring (for a specific queue) to setup
3027  *
3028  *  Returns 0 on success, negative on failure
3029  **/
3030 int igb_setup_rx_resources(struct igb_ring *rx_ring)
3031 {
3032         struct device *dev = rx_ring->dev;
3033         int size;
3034
3035         size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3036
3037         rx_ring->rx_buffer_info = vzalloc(size);
3038         if (!rx_ring->rx_buffer_info)
3039                 goto err;
3040
3041         /* Round up to nearest 4K */
3042         rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
3043         rx_ring->size = ALIGN(rx_ring->size, 4096);
3044
3045         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3046                                            &rx_ring->dma, GFP_KERNEL);
3047         if (!rx_ring->desc)
3048                 goto err;
3049
3050         rx_ring->next_to_alloc = 0;
3051         rx_ring->next_to_clean = 0;
3052         rx_ring->next_to_use = 0;
3053
3054         return 0;
3055
3056 err:
3057         vfree(rx_ring->rx_buffer_info);
3058         rx_ring->rx_buffer_info = NULL;
3059         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
3060         return -ENOMEM;
3061 }
3062
3063 /**
3064  *  igb_setup_all_rx_resources - wrapper to allocate Rx resources
3065  *                               (Descriptors) for all queues
3066  *  @adapter: board private structure
3067  *
3068  *  Return 0 on success, negative on failure
3069  **/
3070 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3071 {
3072         struct pci_dev *pdev = adapter->pdev;
3073         int i, err = 0;
3074
3075         for (i = 0; i < adapter->num_rx_queues; i++) {
3076                 err = igb_setup_rx_resources(adapter->rx_ring[i]);
3077                 if (err) {
3078                         dev_err(&pdev->dev,
3079                                 "Allocation for Rx Queue %u failed\n", i);
3080                         for (i--; i >= 0; i--)
3081                                 igb_free_rx_resources(adapter->rx_ring[i]);
3082                         break;
3083                 }
3084         }
3085
3086         return err;
3087 }
3088
3089 /**
3090  *  igb_setup_mrqc - configure the multiple receive queue control registers
3091  *  @adapter: Board private structure
3092  **/
3093 static void igb_setup_mrqc(struct igb_adapter *adapter)
3094 {
3095         struct e1000_hw *hw = &adapter->hw;
3096         u32 mrqc, rxcsum;
3097         u32 j, num_rx_queues, shift = 0;
3098         static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3099                                         0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3100                                         0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3101                                         0xFA01ACBE };
3102
3103         /* Fill out hash function seeds */
3104         for (j = 0; j < 10; j++)
3105                 wr32(E1000_RSSRK(j), rsskey[j]);
3106
3107         num_rx_queues = adapter->rss_queues;
3108
3109         switch (hw->mac.type) {
3110         case e1000_82575:
3111                 shift = 6;
3112                 break;
3113         case e1000_82576:
3114                 /* 82576 supports 2 RSS queues for SR-IOV */
3115                 if (adapter->vfs_allocated_count) {
3116                         shift = 3;
3117                         num_rx_queues = 2;
3118                 }
3119                 break;
3120         default:
3121                 break;
3122         }
3123
3124         /* Populate the indirection table 4 entries at a time.  To do this
3125          * we are generating the results for n and n+2 and then interleaving
3126          * those with the results with n+1 and n+3.
3127          */
3128         for (j = 0; j < 32; j++) {
3129                 /* first pass generates n and n+2 */
3130                 u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues;
3131                 u32 reta = (base & 0x07800780) >> (7 - shift);
3132
3133                 /* second pass generates n+1 and n+3 */
3134                 base += 0x00010001 * num_rx_queues;
3135                 reta |= (base & 0x07800780) << (1 + shift);
3136
3137                 wr32(E1000_RETA(j), reta);
3138         }
3139
3140         /* Disable raw packet checksumming so that RSS hash is placed in
3141          * descriptor on writeback.  No need to enable TCP/UDP/IP checksum
3142          * offloads as they are enabled by default
3143          */
3144         rxcsum = rd32(E1000_RXCSUM);
3145         rxcsum |= E1000_RXCSUM_PCSD;
3146
3147         if (adapter->hw.mac.type >= e1000_82576)
3148                 /* Enable Receive Checksum Offload for SCTP */
3149                 rxcsum |= E1000_RXCSUM_CRCOFL;
3150
3151         /* Don't need to set TUOFL or IPOFL, they default to 1 */
3152         wr32(E1000_RXCSUM, rxcsum);
3153
3154         /* Generate RSS hash based on packet types, TCP/UDP
3155          * port numbers and/or IPv4/v6 src and dst addresses
3156          */
3157         mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3158                E1000_MRQC_RSS_FIELD_IPV4_TCP |
3159                E1000_MRQC_RSS_FIELD_IPV6 |
3160                E1000_MRQC_RSS_FIELD_IPV6_TCP |
3161                E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
3162
3163         if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3164                 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3165         if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3166                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3167
3168         /* If VMDq is enabled then we set the appropriate mode for that, else
3169          * we default to RSS so that an RSS hash is calculated per packet even
3170          * if we are only using one queue
3171          */
3172         if (adapter->vfs_allocated_count) {
3173                 if (hw->mac.type > e1000_82575) {
3174                         /* Set the default pool for the PF's first queue */
3175                         u32 vtctl = rd32(E1000_VT_CTL);
3176                         vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3177                                    E1000_VT_CTL_DISABLE_DEF_POOL);
3178                         vtctl |= adapter->vfs_allocated_count <<
3179                                 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3180                         wr32(E1000_VT_CTL, vtctl);
3181                 }
3182                 if (adapter->rss_queues > 1)
3183                         mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
3184                 else
3185                         mrqc |= E1000_MRQC_ENABLE_VMDQ;
3186         } else {
3187                 if (hw->mac.type != e1000_i211)
3188                         mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
3189         }
3190         igb_vmm_control(adapter);
3191
3192         wr32(E1000_MRQC, mrqc);
3193 }
3194
3195 /**
3196  *  igb_setup_rctl - configure the receive control registers
3197  *  @adapter: Board private structure
3198  **/
3199 void igb_setup_rctl(struct igb_adapter *adapter)
3200 {
3201         struct e1000_hw *hw = &adapter->hw;
3202         u32 rctl;
3203
3204         rctl = rd32(E1000_RCTL);
3205
3206         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3207         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
3208
3209         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
3210                 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3211
3212         /* enable stripping of CRC. It's unlikely this will break BMC
3213          * redirection as it did with e1000. Newer features require
3214          * that the HW strips the CRC.
3215          */
3216         rctl |= E1000_RCTL_SECRC;
3217
3218         /* disable store bad packets and clear size bits. */
3219         rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
3220
3221         /* enable LPE to prevent packets larger than max_frame_size */
3222         rctl |= E1000_RCTL_LPE;
3223
3224         /* disable queue 0 to prevent tail write w/o re-config */
3225         wr32(E1000_RXDCTL(0), 0);
3226
3227         /* Attention!!!  For SR-IOV PF driver operations you must enable
3228          * queue drop for all VF and PF queues to prevent head of line blocking
3229          * if an un-trusted VF does not provide descriptors to hardware.
3230          */
3231         if (adapter->vfs_allocated_count) {
3232                 /* set all queue drop enable bits */
3233                 wr32(E1000_QDE, ALL_QUEUES);
3234         }
3235
3236         /* This is useful for sniffing bad packets. */
3237         if (adapter->netdev->features & NETIF_F_RXALL) {
3238                 /* UPE and MPE will be handled by normal PROMISC logic
3239                  * in e1000e_set_rx_mode
3240                  */
3241                 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3242                          E1000_RCTL_BAM | /* RX All Bcast Pkts */
3243                          E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3244
3245                 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3246                           E1000_RCTL_DPF | /* Allow filtered pause */
3247                           E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3248                 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3249                  * and that breaks VLANs.
3250                  */
3251         }
3252
3253         wr32(E1000_RCTL, rctl);
3254 }
3255
3256 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3257                                    int vfn)
3258 {
3259         struct e1000_hw *hw = &adapter->hw;
3260         u32 vmolr;
3261
3262         /* if it isn't the PF check to see if VFs are enabled and
3263          * increase the size to support vlan tags
3264          */
3265         if (vfn < adapter->vfs_allocated_count &&
3266             adapter->vf_data[vfn].vlans_enabled)
3267                 size += VLAN_TAG_SIZE;
3268
3269         vmolr = rd32(E1000_VMOLR(vfn));
3270         vmolr &= ~E1000_VMOLR_RLPML_MASK;
3271         vmolr |= size | E1000_VMOLR_LPE;
3272         wr32(E1000_VMOLR(vfn), vmolr);
3273
3274         return 0;
3275 }
3276
3277 /**
3278  *  igb_rlpml_set - set maximum receive packet size
3279  *  @adapter: board private structure
3280  *
3281  *  Configure maximum receivable packet size.
3282  **/
3283 static void igb_rlpml_set(struct igb_adapter *adapter)
3284 {
3285         u32 max_frame_size = adapter->max_frame_size;
3286         struct e1000_hw *hw = &adapter->hw;
3287         u16 pf_id = adapter->vfs_allocated_count;
3288
3289         if (pf_id) {
3290                 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
3291                 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
3292                  * to our max jumbo frame size, in case we need to enable
3293                  * jumbo frames on one of the rings later.
3294                  * This will not pass over-length frames into the default
3295                  * queue because it's gated by the VMOLR.RLPML.
3296                  */
3297                 max_frame_size = MAX_JUMBO_FRAME_SIZE;
3298         }
3299
3300         wr32(E1000_RLPML, max_frame_size);
3301 }
3302
3303 static inline void igb_set_vmolr(struct igb_adapter *adapter,
3304                                  int vfn, bool aupe)
3305 {
3306         struct e1000_hw *hw = &adapter->hw;
3307         u32 vmolr;
3308
3309         /* This register exists only on 82576 and newer so if we are older then
3310          * we should exit and do nothing
3311          */
3312         if (hw->mac.type < e1000_82576)
3313                 return;
3314
3315         vmolr = rd32(E1000_VMOLR(vfn));
3316         vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3317         if (aupe)
3318                 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3319         else
3320                 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
3321
3322         /* clear all bits that might not be set */
3323         vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3324
3325         if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
3326                 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3327         /* for VMDq only allow the VFs and pool 0 to accept broadcast and
3328          * multicast packets
3329          */
3330         if (vfn <= adapter->vfs_allocated_count)
3331                 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3332
3333         wr32(E1000_VMOLR(vfn), vmolr);
3334 }
3335
3336 /**
3337  *  igb_configure_rx_ring - Configure a receive ring after Reset
3338  *  @adapter: board private structure
3339  *  @ring: receive ring to be configured
3340  *
3341  *  Configure the Rx unit of the MAC after a reset.
3342  **/
3343 void igb_configure_rx_ring(struct igb_adapter *adapter,
3344                            struct igb_ring *ring)
3345 {
3346         struct e1000_hw *hw = &adapter->hw;
3347         u64 rdba = ring->dma;
3348         int reg_idx = ring->reg_idx;
3349         u32 srrctl = 0, rxdctl = 0;
3350
3351         /* disable the queue */
3352         wr32(E1000_RXDCTL(reg_idx), 0);
3353
3354         /* Set DMA base address registers */
3355         wr32(E1000_RDBAL(reg_idx),
3356              rdba & 0x00000000ffffffffULL);
3357         wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3358         wr32(E1000_RDLEN(reg_idx),
3359              ring->count * sizeof(union e1000_adv_rx_desc));
3360
3361         /* initialize head and tail */
3362         ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3363         wr32(E1000_RDH(reg_idx), 0);
3364         writel(0, ring->tail);
3365
3366         /* set descriptor configuration */
3367         srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3368         srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3369         srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3370         if (hw->mac.type >= e1000_82580)
3371                 srrctl |= E1000_SRRCTL_TIMESTAMP;
3372         /* Only set Drop Enable if we are supporting multiple queues */
3373         if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3374                 srrctl |= E1000_SRRCTL_DROP_EN;
3375
3376         wr32(E1000_SRRCTL(reg_idx), srrctl);
3377
3378         /* set filtering for VMDQ pools */
3379         igb_set_vmolr(adapter, reg_idx & 0x7, true);
3380
3381         rxdctl |= IGB_RX_PTHRESH;
3382         rxdctl |= IGB_RX_HTHRESH << 8;
3383         rxdctl |= IGB_RX_WTHRESH << 16;
3384
3385         /* enable receive descriptor fetching */
3386         rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3387         wr32(E1000_RXDCTL(reg_idx), rxdctl);
3388 }
3389
3390 /**
3391  *  igb_configure_rx - Configure receive Unit after Reset
3392  *  @adapter: board private structure
3393  *
3394  *  Configure the Rx unit of the MAC after a reset.
3395  **/
3396 static void igb_configure_rx(struct igb_adapter *adapter)
3397 {
3398         int i;
3399
3400         /* set UTA to appropriate mode */
3401         igb_set_uta(adapter);
3402
3403         /* set the correct pool for the PF default MAC address in entry 0 */
3404         igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3405                          adapter->vfs_allocated_count);
3406
3407         /* Setup the HW Rx Head and Tail Descriptor Pointers and
3408          * the Base and Length of the Rx Descriptor Ring
3409          */
3410         for (i = 0; i < adapter->num_rx_queues; i++)
3411                 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
3412 }
3413
3414 /**
3415  *  igb_free_tx_resources - Free Tx Resources per Queue
3416  *  @tx_ring: Tx descriptor ring for a specific queue
3417  *
3418  *  Free all transmit software resources
3419  **/
3420 void igb_free_tx_resources(struct igb_ring *tx_ring)
3421 {
3422         igb_clean_tx_ring(tx_ring);
3423
3424         vfree(tx_ring->tx_buffer_info);
3425         tx_ring->tx_buffer_info = NULL;
3426
3427         /* if not set, then don't free */
3428         if (!tx_ring->desc)
3429                 return;
3430
3431         dma_free_coherent(tx_ring->dev, tx_ring->size,
3432                           tx_ring->desc, tx_ring->dma);
3433
3434         tx_ring->desc = NULL;
3435 }
3436
3437 /**
3438  *  igb_free_all_tx_resources - Free Tx Resources for All Queues
3439  *  @adapter: board private structure
3440  *
3441  *  Free all transmit software resources
3442  **/
3443 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3444 {
3445         int i;
3446
3447         for (i = 0; i < adapter->num_tx_queues; i++)
3448                 igb_free_tx_resources(adapter->tx_ring[i]);
3449 }
3450
3451 void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3452                                     struct igb_tx_buffer *tx_buffer)
3453 {
3454         if (tx_buffer->skb) {
3455                 dev_kfree_skb_any(tx_buffer->skb);
3456                 if (dma_unmap_len(tx_buffer, len))
3457                         dma_unmap_single(ring->dev,
3458                                          dma_unmap_addr(tx_buffer, dma),
3459                                          dma_unmap_len(tx_buffer, len),
3460                                          DMA_TO_DEVICE);
3461         } else if (dma_unmap_len(tx_buffer, len)) {
3462                 dma_unmap_page(ring->dev,
3463                                dma_unmap_addr(tx_buffer, dma),
3464                                dma_unmap_len(tx_buffer, len),
3465                                DMA_TO_DEVICE);
3466         }
3467         tx_buffer->next_to_watch = NULL;
3468         tx_buffer->skb = NULL;
3469         dma_unmap_len_set(tx_buffer, len, 0);
3470         /* buffer_info must be completely set up in the transmit path */
3471 }
3472
3473 /**
3474  *  igb_clean_tx_ring - Free Tx Buffers
3475  *  @tx_ring: ring to be cleaned
3476  **/
3477 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3478 {
3479         struct igb_tx_buffer *buffer_info;
3480         unsigned long size;
3481         u16 i;
3482
3483         if (!tx_ring->tx_buffer_info)
3484                 return;
3485         /* Free all the Tx ring sk_buffs */
3486
3487         for (i = 0; i < tx_ring->count; i++) {
3488                 buffer_info = &tx_ring->tx_buffer_info[i];
3489                 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3490         }
3491
3492         netdev_tx_reset_queue(txring_txq(tx_ring));
3493
3494         size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3495         memset(tx_ring->tx_buffer_info, 0, size);
3496
3497         /* Zero out the descriptor ring */
3498         memset(tx_ring->desc, 0, tx_ring->size);
3499
3500         tx_ring->next_to_use = 0;
3501         tx_ring->next_to_clean = 0;
3502 }
3503
3504 /**
3505  *  igb_clean_all_tx_rings - Free Tx Buffers for all queues
3506  *  @adapter: board private structure
3507  **/
3508 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3509 {
3510         int i;
3511
3512         for (i = 0; i < adapter->num_tx_queues; i++)
3513                 igb_clean_tx_ring(adapter->tx_ring[i]);
3514 }
3515
3516 /**
3517  *  igb_free_rx_resources - Free Rx Resources
3518  *  @rx_ring: ring to clean the resources from
3519  *
3520  *  Free all receive software resources
3521  **/
3522 void igb_free_rx_resources(struct igb_ring *rx_ring)
3523 {
3524         igb_clean_rx_ring(rx_ring);
3525
3526         vfree(rx_ring->rx_buffer_info);
3527         rx_ring->rx_buffer_info = NULL;
3528
3529         /* if not set, then don't free */
3530         if (!rx_ring->desc)
3531                 return;
3532
3533         dma_free_coherent(rx_ring->dev, rx_ring->size,
3534                           rx_ring->desc, rx_ring->dma);
3535
3536         rx_ring->desc = NULL;
3537 }
3538
3539 /**
3540  *  igb_free_all_rx_resources - Free Rx Resources for All Queues
3541  *  @adapter: board private structure
3542  *
3543  *  Free all receive software resources
3544  **/
3545 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3546 {
3547         int i;
3548
3549         for (i = 0; i < adapter->num_rx_queues; i++)
3550                 igb_free_rx_resources(adapter->rx_ring[i]);
3551 }
3552
3553 /**
3554  *  igb_clean_rx_ring - Free Rx Buffers per Queue
3555  *  @rx_ring: ring to free buffers from
3556  **/
3557 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3558 {
3559         unsigned long size;
3560         u16 i;
3561
3562         if (rx_ring->skb)
3563                 dev_kfree_skb(rx_ring->skb);
3564         rx_ring->skb = NULL;
3565
3566         if (!rx_ring->rx_buffer_info)
3567                 return;
3568
3569         /* Free all the Rx ring sk_buffs */
3570         for (i = 0; i < rx_ring->count; i++) {
3571                 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
3572
3573                 if (!buffer_info->page)
3574                         continue;
3575
3576                 dma_unmap_page(rx_ring->dev,
3577                                buffer_info->dma,
3578                                PAGE_SIZE,
3579                                DMA_FROM_DEVICE);
3580                 __free_page(buffer_info->page);
3581
3582                 buffer_info->page = NULL;
3583         }
3584
3585         size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3586         memset(rx_ring->rx_buffer_info, 0, size);
3587
3588         /* Zero out the descriptor ring */
3589         memset(rx_ring->desc, 0, rx_ring->size);
3590
3591         rx_ring->next_to_alloc = 0;
3592         rx_ring->next_to_clean = 0;
3593         rx_ring->next_to_use = 0;
3594 }
3595
3596 /**
3597  *  igb_clean_all_rx_rings - Free Rx Buffers for all queues
3598  *  @adapter: board private structure
3599  **/
3600 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3601 {
3602         int i;
3603
3604         for (i = 0; i < adapter->num_rx_queues; i++)
3605                 igb_clean_rx_ring(adapter->rx_ring[i]);
3606 }
3607
3608 /**
3609  *  igb_set_mac - Change the Ethernet Address of the NIC
3610  *  @netdev: network interface device structure
3611  *  @p: pointer to an address structure
3612  *
3613  *  Returns 0 on success, negative on failure
3614  **/
3615 static int igb_set_mac(struct net_device *netdev, void *p)
3616 {
3617         struct igb_adapter *adapter = netdev_priv(netdev);
3618         struct e1000_hw *hw = &adapter->hw;
3619         struct sockaddr *addr = p;
3620
3621         if (!is_valid_ether_addr(addr->sa_data))
3622                 return -EADDRNOTAVAIL;
3623
3624         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3625         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3626
3627         /* set the correct pool for the new PF MAC address in entry 0 */
3628         igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3629                          adapter->vfs_allocated_count);
3630
3631         return 0;
3632 }
3633
3634 /**
3635  *  igb_write_mc_addr_list - write multicast addresses to MTA
3636  *  @netdev: network interface device structure
3637  *
3638  *  Writes multicast address list to the MTA hash table.
3639  *  Returns: -ENOMEM on failure
3640  *           0 on no addresses written
3641  *           X on writing X addresses to MTA
3642  **/
3643 static int igb_write_mc_addr_list(struct net_device *netdev)
3644 {
3645         struct igb_adapter *adapter = netdev_priv(netdev);
3646         struct e1000_hw *hw = &adapter->hw;
3647         struct netdev_hw_addr *ha;
3648         u8  *mta_list;
3649         int i;
3650
3651         if (netdev_mc_empty(netdev)) {
3652                 /* nothing to program, so clear mc list */
3653                 igb_update_mc_addr_list(hw, NULL, 0);
3654                 igb_restore_vf_multicasts(adapter);
3655                 return 0;
3656         }
3657
3658         mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
3659         if (!mta_list)
3660                 return -ENOMEM;
3661
3662         /* The shared function expects a packed array of only addresses. */
3663         i = 0;
3664         netdev_for_each_mc_addr(ha, netdev)
3665                 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3666
3667         igb_update_mc_addr_list(hw, mta_list, i);
3668         kfree(mta_list);
3669
3670         return netdev_mc_count(netdev);
3671 }
3672
3673 /**
3674  *  igb_write_uc_addr_list - write unicast addresses to RAR table
3675  *  @netdev: network interface device structure
3676  *
3677  *  Writes unicast address list to the RAR table.
3678  *  Returns: -ENOMEM on failure/insufficient address space
3679  *           0 on no addresses written
3680  *           X on writing X addresses to the RAR table
3681  **/
3682 static int igb_write_uc_addr_list(struct net_device *netdev)
3683 {
3684         struct igb_adapter *adapter = netdev_priv(netdev);
3685         struct e1000_hw *hw = &adapter->hw;
3686         unsigned int vfn = adapter->vfs_allocated_count;
3687         unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3688         int count = 0;
3689
3690         /* return ENOMEM indicating insufficient memory for addresses */
3691         if (netdev_uc_count(netdev) > rar_entries)
3692                 return -ENOMEM;
3693
3694         if (!netdev_uc_empty(netdev) && rar_entries) {
3695                 struct netdev_hw_addr *ha;
3696
3697                 netdev_for_each_uc_addr(ha, netdev) {
3698                         if (!rar_entries)
3699                                 break;
3700                         igb_rar_set_qsel(adapter, ha->addr,
3701                                          rar_entries--,
3702                                          vfn);
3703                         count++;
3704                 }
3705         }
3706         /* write the addresses in reverse order to avoid write combining */
3707         for (; rar_entries > 0 ; rar_entries--) {
3708                 wr32(E1000_RAH(rar_entries), 0);
3709                 wr32(E1000_RAL(rar_entries), 0);
3710         }
3711         wrfl();
3712
3713         return count;
3714 }
3715
3716 /**
3717  *  igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3718  *  @netdev: network interface device structure
3719  *
3720  *  The set_rx_mode entry point is called whenever the unicast or multicast
3721  *  address lists or the network interface flags are updated.  This routine is
3722  *  responsible for configuring the hardware for proper unicast, multicast,
3723  *  promiscuous mode, and all-multi behavior.
3724  **/
3725 static void igb_set_rx_mode(struct net_device *netdev)
3726 {
3727         struct igb_adapter *adapter = netdev_priv(netdev);
3728         struct e1000_hw *hw = &adapter->hw;
3729         unsigned int vfn = adapter->vfs_allocated_count;
3730         u32 rctl, vmolr = 0;
3731         int count;
3732
3733         /* Check for Promiscuous and All Multicast modes */
3734         rctl = rd32(E1000_RCTL);
3735
3736         /* clear the effected bits */
3737         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3738
3739         if (netdev->flags & IFF_PROMISC) {
3740                 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3741                 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3742         } else {
3743                 if (netdev->flags & IFF_ALLMULTI) {
3744                         rctl |= E1000_RCTL_MPE;
3745                         vmolr |= E1000_VMOLR_MPME;
3746                 } else {
3747                         /* Write addresses to the MTA, if the attempt fails
3748                          * then we should just turn on promiscuous mode so
3749                          * that we can at least receive multicast traffic
3750                          */
3751                         count = igb_write_mc_addr_list(netdev);
3752                         if (count < 0) {
3753                                 rctl |= E1000_RCTL_MPE;
3754                                 vmolr |= E1000_VMOLR_MPME;
3755                         } else if (count) {
3756                                 vmolr |= E1000_VMOLR_ROMPE;
3757                         }
3758                 }
3759                 /* Write addresses to available RAR registers, if there is not
3760                  * sufficient space to store all the addresses then enable
3761                  * unicast promiscuous mode
3762                  */
3763                 count = igb_write_uc_addr_list(netdev);
3764                 if (count < 0) {
3765                         rctl |= E1000_RCTL_UPE;
3766                         vmolr |= E1000_VMOLR_ROPE;
3767                 }
3768                 rctl |= E1000_RCTL_VFE;
3769         }
3770         wr32(E1000_RCTL, rctl);
3771
3772         /* In order to support SR-IOV and eventually VMDq it is necessary to set
3773          * the VMOLR to enable the appropriate modes.  Without this workaround
3774          * we will have issues with VLAN tag stripping not being done for frames
3775          * that are only arriving because we are the default pool
3776          */
3777         if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
3778                 return;
3779
3780         vmolr |= rd32(E1000_VMOLR(vfn)) &
3781                  ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3782         wr32(E1000_VMOLR(vfn), vmolr);
3783         igb_restore_vf_multicasts(adapter);
3784 }
3785
3786 static void igb_check_wvbr(struct igb_adapter *adapter)
3787 {
3788         struct e1000_hw *hw = &adapter->hw;
3789         u32 wvbr = 0;
3790
3791         switch (hw->mac.type) {
3792         case e1000_82576:
3793         case e1000_i350:
3794                 if (!(wvbr = rd32(E1000_WVBR)))
3795                         return;
3796                 break;
3797         default:
3798                 break;
3799         }
3800
3801         adapter->wvbr |= wvbr;
3802 }
3803
3804 #define IGB_STAGGERED_QUEUE_OFFSET 8
3805
3806 static void igb_spoof_check(struct igb_adapter *adapter)
3807 {
3808         int j;
3809
3810         if (!adapter->wvbr)
3811                 return;
3812
3813         for(j = 0; j < adapter->vfs_allocated_count; j++) {
3814                 if (adapter->wvbr & (1 << j) ||
3815                     adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3816                         dev_warn(&adapter->pdev->dev,
3817                                 "Spoof event(s) detected on VF %d\n", j);
3818                         adapter->wvbr &=
3819                                 ~((1 << j) |
3820                                   (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3821                 }
3822         }
3823 }
3824
3825 /* Need to wait a few seconds after link up to get diagnostic information from
3826  * the phy
3827  */
3828 static void igb_update_phy_info(unsigned long data)
3829 {
3830         struct igb_adapter *adapter = (struct igb_adapter *) data;
3831         igb_get_phy_info(&adapter->hw);
3832 }
3833
3834 /**
3835  *  igb_has_link - check shared code for link and determine up/down
3836  *  @adapter: pointer to driver private info
3837  **/
3838 bool igb_has_link(struct igb_adapter *adapter)
3839 {
3840         struct e1000_hw *hw = &adapter->hw;
3841         bool link_active = false;
3842         s32 ret_val = 0;
3843
3844         /* get_link_status is set on LSC (link status) interrupt or
3845          * rx sequence error interrupt.  get_link_status will stay
3846          * false until the e1000_check_for_link establishes link
3847          * for copper adapters ONLY
3848          */
3849         switch (hw->phy.media_type) {
3850         case e1000_media_type_copper:
3851                 if (hw->mac.get_link_status) {
3852                         ret_val = hw->mac.ops.check_for_link(hw);
3853                         link_active = !hw->mac.get_link_status;
3854                 } else {
3855                         link_active = true;
3856                 }
3857                 break;
3858         case e1000_media_type_internal_serdes:
3859                 ret_val = hw->mac.ops.check_for_link(hw);
3860                 link_active = hw->mac.serdes_has_link;
3861                 break;
3862         default:
3863         case e1000_media_type_unknown:
3864                 break;
3865         }
3866
3867         return link_active;
3868 }
3869
3870 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3871 {
3872         bool ret = false;
3873         u32 ctrl_ext, thstat;
3874
3875         /* check for thermal sensor event on i350 copper only */
3876         if (hw->mac.type == e1000_i350) {
3877                 thstat = rd32(E1000_THSTAT);
3878                 ctrl_ext = rd32(E1000_CTRL_EXT);
3879
3880                 if ((hw->phy.media_type == e1000_media_type_copper) &&
3881                     !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
3882                         ret = !!(thstat & event);
3883         }
3884
3885         return ret;
3886 }
3887
3888 /**
3889  *  igb_watchdog - Timer Call-back
3890  *  @data: pointer to adapter cast into an unsigned long
3891  **/
3892 static void igb_watchdog(unsigned long data)
3893 {
3894         struct igb_adapter *adapter = (struct igb_adapter *)data;
3895         /* Do the rest outside of interrupt context */
3896         schedule_work(&adapter->watchdog_task);
3897 }
3898
3899 static void igb_watchdog_task(struct work_struct *work)
3900 {
3901         struct igb_adapter *adapter = container_of(work,
3902                                                    struct igb_adapter,
3903                                                    watchdog_task);
3904         struct e1000_hw *hw = &adapter->hw;
3905         struct net_device *netdev = adapter->netdev;
3906         u32 link;
3907         int i;
3908
3909         link = igb_has_link(adapter);
3910         if (link) {
3911                 /* Cancel scheduled suspend requests. */
3912                 pm_runtime_resume(netdev->dev.parent);
3913
3914                 if (!netif_carrier_ok(netdev)) {
3915                         u32 ctrl;
3916                         hw->mac.ops.get_speed_and_duplex(hw,
3917                                                          &adapter->link_speed,
3918                                                          &adapter->link_duplex);
3919
3920                         ctrl = rd32(E1000_CTRL);
3921                         /* Links status message must follow this format */
3922                         printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3923                                "Duplex, Flow Control: %s\n",
3924                                netdev->name,
3925                                adapter->link_speed,
3926                                adapter->link_duplex == FULL_DUPLEX ?
3927                                "Full" : "Half",
3928                                (ctrl & E1000_CTRL_TFCE) &&
3929                                (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3930                                (ctrl & E1000_CTRL_RFCE) ?  "RX" :
3931                                (ctrl & E1000_CTRL_TFCE) ?  "TX" : "None");
3932
3933                         /* check for thermal sensor event */
3934                         if (igb_thermal_sensor_event(hw,
3935                             E1000_THSTAT_LINK_THROTTLE)) {
3936                                 netdev_info(netdev, "The network adapter link "
3937                                             "speed was downshifted because it "
3938                                             "overheated\n");
3939                         }
3940
3941                         /* adjust timeout factor according to speed/duplex */
3942                         adapter->tx_timeout_factor = 1;
3943                         switch (adapter->link_speed) {
3944                         case SPEED_10:
3945                                 adapter->tx_timeout_factor = 14;
3946                                 break;
3947                         case SPEED_100:
3948                                 /* maybe add some timeout factor ? */
3949                                 break;
3950                         }
3951
3952                         netif_carrier_on(netdev);
3953
3954                         igb_ping_all_vfs(adapter);
3955                         igb_check_vf_rate_limit(adapter);
3956
3957                         /* link state has changed, schedule phy info update */
3958                         if (!test_bit(__IGB_DOWN, &adapter->state))
3959                                 mod_timer(&adapter->phy_info_timer,
3960                                           round_jiffies(jiffies + 2 * HZ));
3961                 }
3962         } else {
3963                 if (netif_carrier_ok(netdev)) {
3964                         adapter->link_speed = 0;
3965                         adapter->link_duplex = 0;
3966
3967                         /* check for thermal sensor event */
3968                         if (igb_thermal_sensor_event(hw,
3969                             E1000_THSTAT_PWR_DOWN)) {
3970                                 netdev_err(netdev, "The network adapter was "
3971                                            "stopped because it overheated\n");
3972                         }
3973
3974                         /* Links status message must follow this format */
3975                         printk(KERN_INFO "igb: %s NIC Link is Down\n",
3976                                netdev->name);
3977                         netif_carrier_off(netdev);
3978
3979                         igb_ping_all_vfs(adapter);
3980
3981                         /* link state has changed, schedule phy info update */
3982                         if (!test_bit(__IGB_DOWN, &adapter->state))
3983                                 mod_timer(&adapter->phy_info_timer,
3984                                           round_jiffies(jiffies + 2 * HZ));
3985
3986                         pm_schedule_suspend(netdev->dev.parent,
3987                                             MSEC_PER_SEC * 5);
3988                 }
3989         }
3990
3991         spin_lock(&adapter->stats64_lock);
3992         igb_update_stats(adapter, &adapter->stats64);
3993         spin_unlock(&adapter->stats64_lock);
3994
3995         for (i = 0; i < adapter->num_tx_queues; i++) {
3996                 struct igb_ring *tx_ring = adapter->tx_ring[i];
3997                 if (!netif_carrier_ok(netdev)) {
3998                         /* We've lost link, so the controller stops DMA,
3999                          * but we've got queued Tx work that's never going
4000                          * to get done, so reset controller to flush Tx.
4001                          * (Do the reset outside of interrupt context).
4002                          */
4003                         if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4004                                 adapter->tx_timeout_count++;
4005                                 schedule_work(&adapter->reset_task);
4006                                 /* return immediately since reset is imminent */
4007                                 return;
4008                         }
4009                 }
4010
4011                 /* Force detection of hung controller every watchdog period */
4012                 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
4013         }
4014
4015         /* Cause software interrupt to ensure Rx ring is cleaned */
4016         if (adapter->msix_entries) {
4017                 u32 eics = 0;
4018                 for (i = 0; i < adapter->num_q_vectors; i++)
4019                         eics |= adapter->q_vector[i]->eims_value;
4020                 wr32(E1000_EICS, eics);
4021         } else {
4022                 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4023         }
4024
4025         igb_spoof_check(adapter);
4026         igb_ptp_rx_hang(adapter);
4027
4028         /* Reset the timer */
4029         if (!test_bit(__IGB_DOWN, &adapter->state))
4030                 mod_timer(&adapter->watchdog_timer,
4031                           round_jiffies(jiffies + 2 * HZ));
4032 }
4033
4034 enum latency_range {
4035         lowest_latency = 0,
4036         low_latency = 1,
4037         bulk_latency = 2,
4038         latency_invalid = 255
4039 };
4040
4041 /**
4042  *  igb_update_ring_itr - update the dynamic ITR value based on packet size
4043  *  @q_vector: pointer to q_vector
4044  *
4045  *  Stores a new ITR value based on strictly on packet size.  This
4046  *  algorithm is less sophisticated than that used in igb_update_itr,
4047  *  due to the difficulty of synchronizing statistics across multiple
4048  *  receive rings.  The divisors and thresholds used by this function
4049  *  were determined based on theoretical maximum wire speed and testing
4050  *  data, in order to minimize response time while increasing bulk
4051  *  throughput.
4052  *  This functionality is controlled by the InterruptThrottleRate module
4053  *  parameter (see igb_param.c)
4054  *  NOTE:  This function is called only when operating in a multiqueue
4055  *         receive environment.
4056  **/
4057 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
4058 {
4059         int new_val = q_vector->itr_val;
4060         int avg_wire_size = 0;
4061         struct igb_adapter *adapter = q_vector->adapter;
4062         unsigned int packets;
4063
4064         /* For non-gigabit speeds, just fix the interrupt rate at 4000
4065          * ints/sec - ITR timer value of 120 ticks.
4066          */
4067         if (adapter->link_speed != SPEED_1000) {
4068                 new_val = IGB_4K_ITR;
4069                 goto set_itr_val;
4070         }
4071
4072         packets = q_vector->rx.total_packets;
4073         if (packets)
4074                 avg_wire_size = q_vector->rx.total_bytes / packets;
4075
4076         packets = q_vector->tx.total_packets;
4077         if (packets)
4078                 avg_wire_size = max_t(u32, avg_wire_size,
4079                                       q_vector->tx.total_bytes / packets);
4080
4081         /* if avg_wire_size isn't set no work was done */
4082         if (!avg_wire_size)
4083                 goto clear_counts;
4084
4085         /* Add 24 bytes to size to account for CRC, preamble, and gap */
4086         avg_wire_size += 24;
4087
4088         /* Don't starve jumbo frames */
4089         avg_wire_size = min(avg_wire_size, 3000);
4090
4091         /* Give a little boost to mid-size frames */
4092         if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4093                 new_val = avg_wire_size / 3;
4094         else
4095                 new_val = avg_wire_size / 2;
4096
4097         /* conservative mode (itr 3) eliminates the lowest_latency setting */
4098         if (new_val < IGB_20K_ITR &&
4099             ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4100              (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4101                 new_val = IGB_20K_ITR;
4102
4103 set_itr_val:
4104         if (new_val != q_vector->itr_val) {
4105                 q_vector->itr_val = new_val;
4106                 q_vector->set_itr = 1;
4107         }
4108 clear_counts:
4109         q_vector->rx.total_bytes = 0;
4110         q_vector->rx.total_packets = 0;
4111         q_vector->tx.total_bytes = 0;
4112         q_vector->tx.total_packets = 0;
4113 }
4114
4115 /**
4116  *  igb_update_itr - update the dynamic ITR value based on statistics
4117  *  @q_vector: pointer to q_vector
4118  *  @ring_container: ring info to update the itr for
4119  *
4120  *  Stores a new ITR value based on packets and byte
4121  *  counts during the last interrupt.  The advantage of per interrupt
4122  *  computation is faster updates and more accurate ITR for the current
4123  *  traffic pattern.  Constants in this function were computed
4124  *  based on theoretical maximum wire speed and thresholds were set based
4125  *  on testing data as well as attempting to minimize response time
4126  *  while increasing bulk throughput.
4127  *  this functionality is controlled by the InterruptThrottleRate module
4128  *  parameter (see igb_param.c)
4129  *  NOTE:  These calculations are only valid when operating in a single-
4130  *         queue environment.
4131  **/
4132 static void igb_update_itr(struct igb_q_vector *q_vector,
4133                            struct igb_ring_container *ring_container)
4134 {
4135         unsigned int packets = ring_container->total_packets;
4136         unsigned int bytes = ring_container->total_bytes;
4137         u8 itrval = ring_container->itr;
4138
4139         /* no packets, exit with status unchanged */
4140         if (packets == 0)
4141                 return;
4142
4143         switch (itrval) {
4144         case lowest_latency:
4145                 /* handle TSO and jumbo frames */
4146                 if (bytes/packets > 8000)
4147                         itrval = bulk_latency;
4148                 else if ((packets < 5) && (bytes > 512))
4149                         itrval = low_latency;
4150                 break;
4151         case low_latency:  /* 50 usec aka 20000 ints/s */
4152                 if (bytes > 10000) {
4153                         /* this if handles the TSO accounting */
4154                         if (bytes/packets > 8000) {
4155                                 itrval = bulk_latency;
4156                         } else if ((packets < 10) || ((bytes/packets) > 1200)) {
4157                                 itrval = bulk_latency;
4158                         } else if ((packets > 35)) {
4159                                 itrval = lowest_latency;
4160                         }
4161                 } else if (bytes/packets > 2000) {
4162                         itrval = bulk_latency;
4163                 } else if (packets <= 2 && bytes < 512) {
4164                         itrval = lowest_latency;
4165                 }
4166                 break;
4167         case bulk_latency: /* 250 usec aka 4000 ints/s */
4168                 if (bytes > 25000) {
4169                         if (packets > 35)
4170                                 itrval = low_latency;
4171                 } else if (bytes < 1500) {
4172                         itrval = low_latency;
4173                 }
4174                 break;
4175         }
4176
4177         /* clear work counters since we have the values we need */
4178         ring_container->total_bytes = 0;
4179         ring_container->total_packets = 0;
4180
4181         /* write updated itr to ring container */
4182         ring_container->itr = itrval;
4183 }
4184
4185 static void igb_set_itr(struct igb_q_vector *q_vector)
4186 {
4187         struct igb_adapter *adapter = q_vector->adapter;
4188         u32 new_itr = q_vector->itr_val;
4189         u8 current_itr = 0;
4190
4191         /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4192         if (adapter->link_speed != SPEED_1000) {
4193                 current_itr = 0;
4194                 new_itr = IGB_4K_ITR;
4195                 goto set_itr_now;
4196         }
4197
4198         igb_update_itr(q_vector, &q_vector->tx);
4199         igb_update_itr(q_vector, &q_vector->rx);
4200
4201         current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
4202
4203         /* conservative mode (itr 3) eliminates the lowest_latency setting */
4204         if (current_itr == lowest_latency &&
4205             ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4206              (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4207                 current_itr = low_latency;
4208
4209         switch (current_itr) {
4210         /* counts and packets in update_itr are dependent on these numbers */
4211         case lowest_latency:
4212                 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
4213                 break;
4214         case low_latency:
4215                 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
4216                 break;
4217         case bulk_latency:
4218                 new_itr = IGB_4K_ITR;  /* 4,000 ints/sec */
4219                 break;
4220         default:
4221                 break;
4222         }
4223
4224 set_itr_now:
4225         if (new_itr != q_vector->itr_val) {
4226                 /* this attempts to bias the interrupt rate towards Bulk
4227                  * by adding intermediate steps when interrupt rate is
4228                  * increasing
4229                  */
4230                 new_itr = new_itr > q_vector->itr_val ?
4231                           max((new_itr * q_vector->itr_val) /
4232                           (new_itr + (q_vector->itr_val >> 2)),
4233                           new_itr) : new_itr;
4234                 /* Don't write the value here; it resets the adapter's
4235                  * internal timer, and causes us to delay far longer than
4236                  * we should between interrupts.  Instead, we write the ITR
4237                  * value at the beginning of the next interrupt so the timing
4238                  * ends up being correct.
4239                  */
4240                 q_vector->itr_val = new_itr;
4241                 q_vector->set_itr = 1;
4242         }
4243 }
4244
4245 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4246                             u32 type_tucmd, u32 mss_l4len_idx)
4247 {
4248         struct e1000_adv_tx_context_desc *context_desc;
4249         u16 i = tx_ring->next_to_use;
4250
4251         context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4252
4253         i++;
4254         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4255
4256         /* set bits to identify this as an advanced context descriptor */
4257         type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4258
4259         /* For 82575, context index must be unique per ring. */
4260         if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4261                 mss_l4len_idx |= tx_ring->reg_idx << 4;
4262
4263         context_desc->vlan_macip_lens   = cpu_to_le32(vlan_macip_lens);
4264         context_desc->seqnum_seed       = 0;
4265         context_desc->type_tucmd_mlhl   = cpu_to_le32(type_tucmd);
4266         context_desc->mss_l4len_idx     = cpu_to_le32(mss_l4len_idx);
4267 }
4268
4269 static int igb_tso(struct igb_ring *tx_ring,
4270                    struct igb_tx_buffer *first,
4271                    u8 *hdr_len)
4272 {
4273         struct sk_buff *skb = first->skb;
4274         u32 vlan_macip_lens, type_tucmd;
4275         u32 mss_l4len_idx, l4len;
4276
4277         if (skb->ip_summed != CHECKSUM_PARTIAL)
4278                 return 0;
4279
4280         if (!skb_is_gso(skb))
4281                 return 0;
4282
4283         if (skb_header_cloned(skb)) {
4284                 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4285                 if (err)
4286                         return err;
4287         }
4288
4289         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4290         type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4291
4292         if (first->protocol == __constant_htons(ETH_P_IP)) {
4293                 struct iphdr *iph = ip_hdr(skb);
4294                 iph->tot_len = 0;
4295                 iph->check = 0;
4296                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4297                                                          iph->daddr, 0,
4298                                                          IPPROTO_TCP,
4299                                                          0);
4300                 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4301                 first->tx_flags |= IGB_TX_FLAGS_TSO |
4302                                    IGB_TX_FLAGS_CSUM |
4303                                    IGB_TX_FLAGS_IPV4;
4304         } else if (skb_is_gso_v6(skb)) {
4305                 ipv6_hdr(skb)->payload_len = 0;
4306                 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4307                                                        &ipv6_hdr(skb)->daddr,
4308                                                        0, IPPROTO_TCP, 0);
4309                 first->tx_flags |= IGB_TX_FLAGS_TSO |
4310                                    IGB_TX_FLAGS_CSUM;
4311         }
4312
4313         /* compute header lengths */
4314         l4len = tcp_hdrlen(skb);
4315         *hdr_len = skb_transport_offset(skb) + l4len;
4316
4317         /* update gso size and bytecount with header size */
4318         first->gso_segs = skb_shinfo(skb)->gso_segs;
4319         first->bytecount += (first->gso_segs - 1) * *hdr_len;
4320
4321         /* MSS L4LEN IDX */
4322         mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4323         mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4324
4325         /* VLAN MACLEN IPLEN */
4326         vlan_macip_lens = skb_network_header_len(skb);
4327         vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4328         vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4329
4330         igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4331
4332         return 1;
4333 }
4334
4335 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
4336 {
4337         struct sk_buff *skb = first->skb;
4338         u32 vlan_macip_lens = 0;
4339         u32 mss_l4len_idx = 0;
4340         u32 type_tucmd = 0;
4341
4342         if (skb->ip_summed != CHECKSUM_PARTIAL) {
4343                 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4344                         return;
4345         } else {
4346                 u8 l4_hdr = 0;
4347                 switch (first->protocol) {
4348                 case __constant_htons(ETH_P_IP):
4349                         vlan_macip_lens |= skb_network_header_len(skb);
4350                         type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4351                         l4_hdr = ip_hdr(skb)->protocol;
4352                         break;
4353                 case __constant_htons(ETH_P_IPV6):
4354                         vlan_macip_lens |= skb_network_header_len(skb);
4355                         l4_hdr = ipv6_hdr(skb)->nexthdr;
4356                         break;
4357                 default:
4358                         if (unlikely(net_ratelimit())) {
4359                                 dev_warn(tx_ring->dev,
4360                                          "partial checksum but proto=%x!\n",
4361                                          first->protocol);
4362                         }
4363                         break;
4364                 }
4365
4366                 switch (l4_hdr) {
4367                 case IPPROTO_TCP:
4368                         type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4369                         mss_l4len_idx = tcp_hdrlen(skb) <<
4370                                         E1000_ADVTXD_L4LEN_SHIFT;
4371                         break;
4372                 case IPPROTO_SCTP:
4373                         type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4374                         mss_l4len_idx = sizeof(struct sctphdr) <<
4375                                         E1000_ADVTXD_L4LEN_SHIFT;
4376                         break;
4377                 case IPPROTO_UDP:
4378                         mss_l4len_idx = sizeof(struct udphdr) <<
4379                                         E1000_ADVTXD_L4LEN_SHIFT;
4380                         break;
4381                 default:
4382                         if (unlikely(net_ratelimit())) {
4383                                 dev_warn(tx_ring->dev,
4384                                          "partial checksum but l4 proto=%x!\n",
4385                                          l4_hdr);
4386                         }
4387                         break;
4388                 }
4389
4390                 /* update TX checksum flag */
4391                 first->tx_flags |= IGB_TX_FLAGS_CSUM;
4392         }
4393
4394         vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4395         vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4396
4397         igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4398 }
4399
4400 #define IGB_SET_FLAG(_input, _flag, _result) \
4401         ((_flag <= _result) ? \
4402          ((u32)(_input & _flag) * (_result / _flag)) : \
4403          ((u32)(_input & _flag) / (_flag / _result)))
4404
4405 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
4406 {
4407         /* set type for advanced descriptor with frame checksum insertion */
4408         u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4409                        E1000_ADVTXD_DCMD_DEXT |
4410                        E1000_ADVTXD_DCMD_IFCS;
4411
4412         /* set HW vlan bit if vlan is present */
4413         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4414                                  (E1000_ADVTXD_DCMD_VLE));
4415
4416         /* set segmentation bits for TSO */
4417         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4418                                  (E1000_ADVTXD_DCMD_TSE));
4419
4420         /* set timestamp bit if present */
4421         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4422                                  (E1000_ADVTXD_MAC_TSTAMP));
4423
4424         /* insert frame checksum */
4425         cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
4426
4427         return cmd_type;
4428 }
4429
4430 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4431                                  union e1000_adv_tx_desc *tx_desc,
4432                                  u32 tx_flags, unsigned int paylen)
4433 {
4434         u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4435
4436         /* 82575 requires a unique index per ring */
4437         if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4438                 olinfo_status |= tx_ring->reg_idx << 4;
4439
4440         /* insert L4 checksum */
4441         olinfo_status |= IGB_SET_FLAG(tx_flags,
4442                                       IGB_TX_FLAGS_CSUM,
4443                                       (E1000_TXD_POPTS_TXSM << 8));
4444
4445         /* insert IPv4 checksum */
4446         olinfo_status |= IGB_SET_FLAG(tx_flags,
4447                                       IGB_TX_FLAGS_IPV4,
4448                                       (E1000_TXD_POPTS_IXSM << 8));
4449
4450         tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4451 }
4452
4453 static void igb_tx_map(struct igb_ring *tx_ring,
4454                        struct igb_tx_buffer *first,
4455                        const u8 hdr_len)
4456 {
4457         struct sk_buff *skb = first->skb;
4458         struct igb_tx_buffer *tx_buffer;
4459         union e1000_adv_tx_desc *tx_desc;
4460         struct skb_frag_struct *frag;
4461         dma_addr_t dma;
4462         unsigned int data_len, size;
4463         u32 tx_flags = first->tx_flags;
4464         u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
4465         u16 i = tx_ring->next_to_use;
4466
4467         tx_desc = IGB_TX_DESC(tx_ring, i);
4468
4469         igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4470
4471         size = skb_headlen(skb);
4472         data_len = skb->data_len;
4473
4474         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
4475
4476         tx_buffer = first;
4477
4478         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4479                 if (dma_mapping_error(tx_ring->dev, dma))
4480                         goto dma_error;
4481
4482                 /* record length, and DMA address */
4483                 dma_unmap_len_set(tx_buffer, len, size);
4484                 dma_unmap_addr_set(tx_buffer, dma, dma);
4485
4486                 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4487
4488                 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4489                         tx_desc->read.cmd_type_len =
4490                                 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
4491
4492                         i++;
4493                         tx_desc++;
4494                         if (i == tx_ring->count) {
4495                                 tx_desc = IGB_TX_DESC(tx_ring, 0);
4496                                 i = 0;
4497                         }
4498                         tx_desc->read.olinfo_status = 0;
4499
4500                         dma += IGB_MAX_DATA_PER_TXD;
4501                         size -= IGB_MAX_DATA_PER_TXD;
4502
4503                         tx_desc->read.buffer_addr = cpu_to_le64(dma);
4504                 }
4505
4506                 if (likely(!data_len))
4507                         break;
4508
4509                 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
4510
4511                 i++;
4512                 tx_desc++;
4513                 if (i == tx_ring->count) {
4514                         tx_desc = IGB_TX_DESC(tx_ring, 0);
4515                         i = 0;
4516                 }
4517                 tx_desc->read.olinfo_status = 0;
4518
4519                 size = skb_frag_size(frag);
4520                 data_len -= size;
4521
4522                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
4523                                        size, DMA_TO_DEVICE);
4524
4525                 tx_buffer = &tx_ring->tx_buffer_info[i];
4526         }
4527
4528         /* write last descriptor with RS and EOP bits */
4529         cmd_type |= size | IGB_TXD_DCMD;
4530         tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
4531
4532         netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4533
4534         /* set the timestamp */
4535         first->time_stamp = jiffies;
4536
4537         /* Force memory writes to complete before letting h/w know there
4538          * are new descriptors to fetch.  (Only applicable for weak-ordered
4539          * memory model archs, such as IA-64).
4540          *
4541          * We also need this memory barrier to make certain all of the
4542          * status bits have been updated before next_to_watch is written.
4543          */
4544         wmb();
4545
4546         /* set next_to_watch value indicating a packet is present */
4547         first->next_to_watch = tx_desc;
4548
4549         i++;
4550         if (i == tx_ring->count)
4551                 i = 0;
4552
4553         tx_ring->next_to_use = i;
4554
4555         writel(i, tx_ring->tail);
4556
4557         /* we need this if more than one processor can write to our tail
4558          * at a time, it synchronizes IO on IA64/Altix systems
4559          */
4560         mmiowb();
4561
4562         return;
4563
4564 dma_error:
4565         dev_err(tx_ring->dev, "TX DMA map failed\n");
4566
4567         /* clear dma mappings for failed tx_buffer_info map */
4568         for (;;) {
4569                 tx_buffer = &tx_ring->tx_buffer_info[i];
4570                 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4571                 if (tx_buffer == first)
4572                         break;
4573                 if (i == 0)
4574                         i = tx_ring->count;
4575                 i--;
4576         }
4577
4578         tx_ring->next_to_use = i;
4579 }
4580
4581 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4582 {
4583         struct net_device *netdev = tx_ring->netdev;
4584
4585         netif_stop_subqueue(netdev, tx_ring->queue_index);
4586
4587         /* Herbert's original patch had:
4588          *  smp_mb__after_netif_stop_queue();
4589          * but since that doesn't exist yet, just open code it.
4590          */
4591         smp_mb();
4592
4593         /* We need to check again in a case another CPU has just
4594          * made room available.
4595          */
4596         if (igb_desc_unused(tx_ring) < size)
4597                 return -EBUSY;
4598
4599         /* A reprieve! */
4600         netif_wake_subqueue(netdev, tx_ring->queue_index);
4601
4602         u64_stats_update_begin(&tx_ring->tx_syncp2);
4603         tx_ring->tx_stats.restart_queue2++;
4604         u64_stats_update_end(&tx_ring->tx_syncp2);
4605
4606         return 0;
4607 }
4608
4609 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4610 {
4611         if (igb_desc_unused(tx_ring) >= size)
4612                 return 0;
4613         return __igb_maybe_stop_tx(tx_ring, size);
4614 }
4615
4616 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4617                                 struct igb_ring *tx_ring)
4618 {
4619         struct igb_tx_buffer *first;
4620         int tso;
4621         u32 tx_flags = 0;
4622         u16 count = TXD_USE_COUNT(skb_headlen(skb));
4623         __be16 protocol = vlan_get_protocol(skb);
4624         u8 hdr_len = 0;
4625
4626         /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4627          *       + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
4628          *       + 2 desc gap to keep tail from touching head,
4629          *       + 1 desc for context descriptor,
4630          * otherwise try next time
4631          */
4632         if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
4633                 unsigned short f;
4634                 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4635                         count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4636         } else {
4637                 count += skb_shinfo(skb)->nr_frags;
4638         }
4639
4640         if (igb_maybe_stop_tx(tx_ring, count + 3)) {
4641                 /* this is a hard error */
4642                 return NETDEV_TX_BUSY;
4643         }
4644
4645         /* record the location of the first descriptor for this packet */
4646         first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4647         first->skb = skb;
4648         first->bytecount = skb->len;
4649         first->gso_segs = 1;
4650
4651         skb_tx_timestamp(skb);
4652
4653         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4654                 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
4655
4656                 if (!(adapter->ptp_tx_skb)) {
4657                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4658                         tx_flags |= IGB_TX_FLAGS_TSTAMP;
4659
4660                         adapter->ptp_tx_skb = skb_get(skb);
4661                         adapter->ptp_tx_start = jiffies;
4662                         if (adapter->hw.mac.type == e1000_82576)
4663                                 schedule_work(&adapter->ptp_tx_work);
4664                 }
4665         }
4666
4667         if (vlan_tx_tag_present(skb)) {
4668                 tx_flags |= IGB_TX_FLAGS_VLAN;
4669                 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4670         }
4671
4672         /* record initial flags and protocol */
4673         first->tx_flags = tx_flags;
4674         first->protocol = protocol;
4675
4676         tso = igb_tso(tx_ring, first, &hdr_len);
4677         if (tso < 0)
4678                 goto out_drop;
4679         else if (!tso)
4680                 igb_tx_csum(tx_ring, first);
4681
4682         igb_tx_map(tx_ring, first, hdr_len);
4683
4684         /* Make sure there is space in the ring for the next send. */
4685         igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
4686
4687         return NETDEV_TX_OK;
4688
4689 out_drop:
4690         igb_unmap_and_free_tx_resource(tx_ring, first);
4691
4692         return NETDEV_TX_OK;
4693 }
4694
4695 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4696                                                     struct sk_buff *skb)
4697 {
4698         unsigned int r_idx = skb->queue_mapping;
4699
4700         if (r_idx >= adapter->num_tx_queues)
4701                 r_idx = r_idx % adapter->num_tx_queues;
4702
4703         return adapter->tx_ring[r_idx];
4704 }
4705
4706 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4707                                   struct net_device *netdev)
4708 {
4709         struct igb_adapter *adapter = netdev_priv(netdev);
4710
4711         if (test_bit(__IGB_DOWN, &adapter->state)) {
4712                 dev_kfree_skb_any(skb);
4713                 return NETDEV_TX_OK;
4714         }
4715
4716         if (skb->len <= 0) {
4717                 dev_kfree_skb_any(skb);
4718                 return NETDEV_TX_OK;
4719         }
4720
4721         /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
4722          * in order to meet this minimum size requirement.
4723          */
4724         if (unlikely(skb->len < 17)) {
4725                 if (skb_pad(skb, 17 - skb->len))
4726                         return NETDEV_TX_OK;
4727                 skb->len = 17;
4728                 skb_set_tail_pointer(skb, 17);
4729         }
4730
4731         return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
4732 }
4733
4734 /**
4735  *  igb_tx_timeout - Respond to a Tx Hang
4736  *  @netdev: network interface device structure
4737  **/
4738 static void igb_tx_timeout(struct net_device *netdev)
4739 {
4740         struct igb_adapter *adapter = netdev_priv(netdev);
4741         struct e1000_hw *hw = &adapter->hw;
4742
4743         /* Do the reset outside of interrupt context */
4744         adapter->tx_timeout_count++;
4745
4746         if (hw->mac.type >= e1000_82580)
4747                 hw->dev_spec._82575.global_device_reset = true;
4748
4749         schedule_work(&adapter->reset_task);
4750         wr32(E1000_EICS,
4751              (adapter->eims_enable_mask & ~adapter->eims_other));
4752 }
4753
4754 static void igb_reset_task(struct work_struct *work)
4755 {
4756         struct igb_adapter *adapter;
4757         adapter = container_of(work, struct igb_adapter, reset_task);
4758
4759         igb_dump(adapter);
4760         netdev_err(adapter->netdev, "Reset adapter\n");
4761         igb_reinit_locked(adapter);
4762 }
4763
4764 /**
4765  *  igb_get_stats64 - Get System Network Statistics
4766  *  @netdev: network interface device structure
4767  *  @stats: rtnl_link_stats64 pointer
4768  **/
4769 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4770                                                 struct rtnl_link_stats64 *stats)
4771 {
4772         struct igb_adapter *adapter = netdev_priv(netdev);
4773
4774         spin_lock(&adapter->stats64_lock);
4775         igb_update_stats(adapter, &adapter->stats64);
4776         memcpy(stats, &adapter->stats64, sizeof(*stats));
4777         spin_unlock(&adapter->stats64_lock);
4778
4779         return stats;
4780 }
4781
4782 /**
4783  *  igb_change_mtu - Change the Maximum Transfer Unit
4784  *  @netdev: network interface device structure
4785  *  @new_mtu: new value for maximum frame size
4786  *
4787  *  Returns 0 on success, negative on failure
4788  **/
4789 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4790 {
4791         struct igb_adapter *adapter = netdev_priv(netdev);
4792         struct pci_dev *pdev = adapter->pdev;
4793         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
4794
4795         if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
4796                 dev_err(&pdev->dev, "Invalid MTU setting\n");
4797                 return -EINVAL;
4798         }
4799
4800 #define MAX_STD_JUMBO_FRAME_SIZE 9238
4801         if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
4802                 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
4803                 return -EINVAL;
4804         }
4805
4806         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4807                 msleep(1);
4808
4809         /* igb_down has a dependency on max_frame_size */
4810         adapter->max_frame_size = max_frame;
4811
4812         if (netif_running(netdev))
4813                 igb_down(adapter);
4814
4815         dev_info(&pdev->dev, "changing MTU from %d to %d\n",
4816                  netdev->mtu, new_mtu);
4817         netdev->mtu = new_mtu;
4818
4819         if (netif_running(netdev))
4820                 igb_up(adapter);
4821         else
4822                 igb_reset(adapter);
4823
4824         clear_bit(__IGB_RESETTING, &adapter->state);
4825
4826         return 0;
4827 }
4828
4829 /**
4830  *  igb_update_stats - Update the board statistics counters
4831  *  @adapter: board private structure
4832  **/
4833 void igb_update_stats(struct igb_adapter *adapter,
4834                       struct rtnl_link_stats64 *net_stats)
4835 {
4836         struct e1000_hw *hw = &adapter->hw;
4837         struct pci_dev *pdev = adapter->pdev;
4838         u32 reg, mpc;
4839         u16 phy_tmp;
4840         int i;
4841         u64 bytes, packets;
4842         unsigned int start;
4843         u64 _bytes, _packets;
4844
4845 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4846
4847         /* Prevent stats update while adapter is being reset, or if the pci
4848          * connection is down.
4849          */
4850         if (adapter->link_speed == 0)
4851                 return;
4852         if (pci_channel_offline(pdev))
4853                 return;
4854
4855         bytes = 0;
4856         packets = 0;
4857         for (i = 0; i < adapter->num_rx_queues; i++) {
4858                 u32 rqdpc = rd32(E1000_RQDPC(i));
4859                 struct igb_ring *ring = adapter->rx_ring[i];
4860
4861                 if (rqdpc) {
4862                         ring->rx_stats.drops += rqdpc;
4863                         net_stats->rx_fifo_errors += rqdpc;
4864                 }
4865
4866                 do {
4867                         start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4868                         _bytes = ring->rx_stats.bytes;
4869                         _packets = ring->rx_stats.packets;
4870                 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4871                 bytes += _bytes;
4872                 packets += _packets;
4873         }
4874
4875         net_stats->rx_bytes = bytes;
4876         net_stats->rx_packets = packets;
4877
4878         bytes = 0;
4879         packets = 0;
4880         for (i = 0; i < adapter->num_tx_queues; i++) {
4881                 struct igb_ring *ring = adapter->tx_ring[i];
4882                 do {
4883                         start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4884                         _bytes = ring->tx_stats.bytes;
4885                         _packets = ring->tx_stats.packets;
4886                 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4887                 bytes += _bytes;
4888                 packets += _packets;
4889         }
4890         net_stats->tx_bytes = bytes;
4891         net_stats->tx_packets = packets;
4892
4893         /* read stats registers */
4894         adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4895         adapter->stats.gprc += rd32(E1000_GPRC);
4896         adapter->stats.gorc += rd32(E1000_GORCL);
4897         rd32(E1000_GORCH); /* clear GORCL */
4898         adapter->stats.bprc += rd32(E1000_BPRC);
4899         adapter->stats.mprc += rd32(E1000_MPRC);
4900         adapter->stats.roc += rd32(E1000_ROC);
4901
4902         adapter->stats.prc64 += rd32(E1000_PRC64);
4903         adapter->stats.prc127 += rd32(E1000_PRC127);
4904         adapter->stats.prc255 += rd32(E1000_PRC255);
4905         adapter->stats.prc511 += rd32(E1000_PRC511);
4906         adapter->stats.prc1023 += rd32(E1000_PRC1023);
4907         adapter->stats.prc1522 += rd32(E1000_PRC1522);
4908         adapter->stats.symerrs += rd32(E1000_SYMERRS);
4909         adapter->stats.sec += rd32(E1000_SEC);
4910
4911         mpc = rd32(E1000_MPC);
4912         adapter->stats.mpc += mpc;
4913         net_stats->rx_fifo_errors += mpc;
4914         adapter->stats.scc += rd32(E1000_SCC);
4915         adapter->stats.ecol += rd32(E1000_ECOL);
4916         adapter->stats.mcc += rd32(E1000_MCC);
4917         adapter->stats.latecol += rd32(E1000_LATECOL);
4918         adapter->stats.dc += rd32(E1000_DC);
4919         adapter->stats.rlec += rd32(E1000_RLEC);
4920         adapter->stats.xonrxc += rd32(E1000_XONRXC);
4921         adapter->stats.xontxc += rd32(E1000_XONTXC);
4922         adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4923         adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4924         adapter->stats.fcruc += rd32(E1000_FCRUC);
4925         adapter->stats.gptc += rd32(E1000_GPTC);
4926         adapter->stats.gotc += rd32(E1000_GOTCL);
4927         rd32(E1000_GOTCH); /* clear GOTCL */
4928         adapter->stats.rnbc += rd32(E1000_RNBC);
4929         adapter->stats.ruc += rd32(E1000_RUC);
4930         adapter->stats.rfc += rd32(E1000_RFC);
4931         adapter->stats.rjc += rd32(E1000_RJC);
4932         adapter->stats.tor += rd32(E1000_TORH);
4933         adapter->stats.tot += rd32(E1000_TOTH);
4934         adapter->stats.tpr += rd32(E1000_TPR);
4935
4936         adapter->stats.ptc64 += rd32(E1000_PTC64);
4937         adapter->stats.ptc127 += rd32(E1000_PTC127);
4938         adapter->stats.ptc255 += rd32(E1000_PTC255);
4939         adapter->stats.ptc511 += rd32(E1000_PTC511);
4940         adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4941         adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4942
4943         adapter->stats.mptc += rd32(E1000_MPTC);
4944         adapter->stats.bptc += rd32(E1000_BPTC);
4945
4946         adapter->stats.tpt += rd32(E1000_TPT);
4947         adapter->stats.colc += rd32(E1000_COLC);
4948
4949         adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
4950         /* read internal phy specific stats */
4951         reg = rd32(E1000_CTRL_EXT);
4952         if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4953                 adapter->stats.rxerrc += rd32(E1000_RXERRC);
4954
4955                 /* this stat has invalid values on i210/i211 */
4956                 if ((hw->mac.type != e1000_i210) &&
4957                     (hw->mac.type != e1000_i211))
4958                         adapter->stats.tncrs += rd32(E1000_TNCRS);
4959         }
4960
4961         adapter->stats.tsctc += rd32(E1000_TSCTC);
4962         adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4963
4964         adapter->stats.iac += rd32(E1000_IAC);
4965         adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4966         adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4967         adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4968         adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4969         adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4970         adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4971         adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4972         adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4973
4974         /* Fill out the OS statistics structure */
4975         net_stats->multicast = adapter->stats.mprc;
4976         net_stats->collisions = adapter->stats.colc;
4977
4978         /* Rx Errors */
4979
4980         /* RLEC on some newer hardware can be incorrect so build
4981          * our own version based on RUC and ROC
4982          */
4983         net_stats->rx_errors = adapter->stats.rxerrc +
4984                 adapter->stats.crcerrs + adapter->stats.algnerrc +
4985                 adapter->stats.ruc + adapter->stats.roc +
4986                 adapter->stats.cexterr;
4987         net_stats->rx_length_errors = adapter->stats.ruc +
4988                                       adapter->stats.roc;
4989         net_stats->rx_crc_errors = adapter->stats.crcerrs;
4990         net_stats->rx_frame_errors = adapter->stats.algnerrc;
4991         net_stats->rx_missed_errors = adapter->stats.mpc;
4992
4993         /* Tx Errors */
4994         net_stats->tx_errors = adapter->stats.ecol +
4995                                adapter->stats.latecol;
4996         net_stats->tx_aborted_errors = adapter->stats.ecol;
4997         net_stats->tx_window_errors = adapter->stats.latecol;
4998         net_stats->tx_carrier_errors = adapter->stats.tncrs;
4999
5000         /* Tx Dropped needs to be maintained elsewhere */
5001
5002         /* Phy Stats */
5003         if (hw->phy.media_type == e1000_media_type_copper) {
5004                 if ((adapter->link_speed == SPEED_1000) &&
5005                    (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
5006                         phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
5007                         adapter->phy_stats.idle_errors += phy_tmp;
5008                 }
5009         }
5010
5011         /* Management Stats */
5012         adapter->stats.mgptc += rd32(E1000_MGTPTC);
5013         adapter->stats.mgprc += rd32(E1000_MGTPRC);
5014         adapter->stats.mgpdc += rd32(E1000_MGTPDC);
5015
5016         /* OS2BMC Stats */
5017         reg = rd32(E1000_MANC);
5018         if (reg & E1000_MANC_EN_BMC2OS) {
5019                 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5020                 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5021                 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5022                 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5023         }
5024 }
5025
5026 static irqreturn_t igb_msix_other(int irq, void *data)
5027 {
5028         struct igb_adapter *adapter = data;
5029         struct e1000_hw *hw = &adapter->hw;
5030         u32 icr = rd32(E1000_ICR);
5031         /* reading ICR causes bit 31 of EICR to be cleared */
5032
5033         if (icr & E1000_ICR_DRSTA)
5034                 schedule_work(&adapter->reset_task);
5035
5036         if (icr & E1000_ICR_DOUTSYNC) {
5037                 /* HW is reporting DMA is out of sync */
5038                 adapter->stats.doosync++;
5039                 /* The DMA Out of Sync is also indication of a spoof event
5040                  * in IOV mode. Check the Wrong VM Behavior register to
5041                  * see if it is really a spoof event.
5042                  */
5043                 igb_check_wvbr(adapter);
5044         }
5045
5046         /* Check for a mailbox event */
5047         if (icr & E1000_ICR_VMMB)
5048                 igb_msg_task(adapter);
5049
5050         if (icr & E1000_ICR_LSC) {
5051                 hw->mac.get_link_status = 1;
5052                 /* guard against interrupt when we're going down */
5053                 if (!test_bit(__IGB_DOWN, &adapter->state))
5054                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
5055         }
5056
5057         if (icr & E1000_ICR_TS) {
5058                 u32 tsicr = rd32(E1000_TSICR);
5059
5060                 if (tsicr & E1000_TSICR_TXTS) {
5061                         /* acknowledge the interrupt */
5062                         wr32(E1000_TSICR, E1000_TSICR_TXTS);
5063                         /* retrieve hardware timestamp */
5064                         schedule_work(&adapter->ptp_tx_work);
5065                 }
5066         }
5067
5068         wr32(E1000_EIMS, adapter->eims_other);
5069
5070         return IRQ_HANDLED;
5071 }
5072
5073 static void igb_write_itr(struct igb_q_vector *q_vector)
5074 {
5075         struct igb_adapter *adapter = q_vector->adapter;
5076         u32 itr_val = q_vector->itr_val & 0x7FFC;
5077
5078         if (!q_vector->set_itr)
5079                 return;
5080
5081         if (!itr_val)
5082                 itr_val = 0x4;
5083
5084         if (adapter->hw.mac.type == e1000_82575)
5085                 itr_val |= itr_val << 16;
5086         else
5087                 itr_val |= E1000_EITR_CNT_IGNR;
5088
5089         writel(itr_val, q_vector->itr_register);
5090         q_vector->set_itr = 0;
5091 }
5092
5093 static irqreturn_t igb_msix_ring(int irq, void *data)
5094 {
5095         struct igb_q_vector *q_vector = data;
5096
5097         /* Write the ITR value calculated from the previous interrupt. */
5098         igb_write_itr(q_vector);
5099
5100         napi_schedule(&q_vector->napi);
5101
5102         return IRQ_HANDLED;
5103 }
5104
5105 #ifdef CONFIG_IGB_DCA
5106 static void igb_update_tx_dca(struct igb_adapter *adapter,
5107                               struct igb_ring *tx_ring,
5108                               int cpu)
5109 {
5110         struct e1000_hw *hw = &adapter->hw;
5111         u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5112
5113         if (hw->mac.type != e1000_82575)
5114                 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5115
5116         /* We can enable relaxed ordering for reads, but not writes when
5117          * DCA is enabled.  This is due to a known issue in some chipsets
5118          * which will cause the DCA tag to be cleared.
5119          */
5120         txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5121                   E1000_DCA_TXCTRL_DATA_RRO_EN |
5122                   E1000_DCA_TXCTRL_DESC_DCA_EN;
5123
5124         wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5125 }
5126
5127 static void igb_update_rx_dca(struct igb_adapter *adapter,
5128                               struct igb_ring *rx_ring,
5129                               int cpu)
5130 {
5131         struct e1000_hw *hw = &adapter->hw;
5132         u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5133
5134         if (hw->mac.type != e1000_82575)
5135                 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5136
5137         /* We can enable relaxed ordering for reads, but not writes when
5138          * DCA is enabled.  This is due to a known issue in some chipsets
5139          * which will cause the DCA tag to be cleared.
5140          */
5141         rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5142                   E1000_DCA_RXCTRL_DESC_DCA_EN;
5143
5144         wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5145 }
5146
5147 static void igb_update_dca(struct igb_q_vector *q_vector)
5148 {
5149         struct igb_adapter *adapter = q_vector->adapter;
5150         int cpu = get_cpu();
5151
5152         if (q_vector->cpu == cpu)
5153                 goto out_no_update;
5154
5155         if (q_vector->tx.ring)
5156                 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5157
5158         if (q_vector->rx.ring)
5159                 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5160
5161         q_vector->cpu = cpu;
5162 out_no_update:
5163         put_cpu();
5164 }
5165
5166 static void igb_setup_dca(struct igb_adapter *adapter)
5167 {
5168         struct e1000_hw *hw = &adapter->hw;
5169         int i;
5170
5171         if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
5172                 return;
5173
5174         /* Always use CB2 mode, difference is masked in the CB driver. */
5175         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5176
5177         for (i = 0; i < adapter->num_q_vectors; i++) {
5178                 adapter->q_vector[i]->cpu = -1;
5179                 igb_update_dca(adapter->q_vector[i]);
5180         }
5181 }
5182
5183 static int __igb_notify_dca(struct device *dev, void *data)
5184 {
5185         struct net_device *netdev = dev_get_drvdata(dev);
5186         struct igb_adapter *adapter = netdev_priv(netdev);
5187         struct pci_dev *pdev = adapter->pdev;
5188         struct e1000_hw *hw = &adapter->hw;
5189         unsigned long event = *(unsigned long *)data;
5190
5191         switch (event) {
5192         case DCA_PROVIDER_ADD:
5193                 /* if already enabled, don't do it again */
5194                 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
5195                         break;
5196                 if (dca_add_requester(dev) == 0) {
5197                         adapter->flags |= IGB_FLAG_DCA_ENABLED;
5198                         dev_info(&pdev->dev, "DCA enabled\n");
5199                         igb_setup_dca(adapter);
5200                         break;
5201                 }
5202                 /* Fall Through since DCA is disabled. */
5203         case DCA_PROVIDER_REMOVE:
5204                 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
5205                         /* without this a class_device is left
5206                          * hanging around in the sysfs model
5207                          */
5208                         dca_remove_requester(dev);
5209                         dev_info(&pdev->dev, "DCA disabled\n");
5210                         adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
5211                         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
5212                 }
5213                 break;
5214         }
5215
5216         return 0;
5217 }
5218
5219 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
5220                           void *p)
5221 {
5222         int ret_val;
5223
5224         ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
5225                                          __igb_notify_dca);
5226
5227         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5228 }
5229 #endif /* CONFIG_IGB_DCA */
5230
5231 #ifdef CONFIG_PCI_IOV
5232 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5233 {
5234         unsigned char mac_addr[ETH_ALEN];
5235
5236         eth_zero_addr(mac_addr);
5237         igb_set_vf_mac(adapter, vf, mac_addr);
5238
5239         /* By default spoof check is enabled for all VFs */
5240         adapter->vf_data[vf].spoofchk_enabled = true;
5241
5242         return 0;
5243 }
5244
5245 static bool igb_vfs_are_assigned(struct igb_adapter *adapter)
5246 {
5247         struct pci_dev *pdev = adapter->pdev;
5248         struct pci_dev *vfdev;
5249         int dev_id;
5250
5251         switch (adapter->hw.mac.type) {
5252         case e1000_82576:
5253                 dev_id = IGB_82576_VF_DEV_ID;
5254                 break;
5255         case e1000_i350:
5256                 dev_id = IGB_I350_VF_DEV_ID;
5257                 break;
5258         default:
5259                 return false;
5260         }
5261
5262         /* loop through all the VFs to see if we own any that are assigned */
5263         vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, NULL);
5264         while (vfdev) {
5265                 /* if we don't own it we don't care */
5266                 if (vfdev->is_virtfn && vfdev->physfn == pdev) {
5267                         /* if it is assigned we cannot release it */
5268                         if (vfdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED)
5269                                 return true;
5270                 }
5271
5272                 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, vfdev);
5273         }
5274
5275         return false;
5276 }
5277
5278 #endif
5279 static void igb_ping_all_vfs(struct igb_adapter *adapter)
5280 {
5281         struct e1000_hw *hw = &adapter->hw;
5282         u32 ping;
5283         int i;
5284
5285         for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5286                 ping = E1000_PF_CONTROL_MSG;
5287                 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
5288                         ping |= E1000_VT_MSGTYPE_CTS;
5289                 igb_write_mbx(hw, &ping, 1, i);
5290         }
5291 }
5292
5293 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5294 {
5295         struct e1000_hw *hw = &adapter->hw;
5296         u32 vmolr = rd32(E1000_VMOLR(vf));
5297         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5298
5299         vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
5300                             IGB_VF_FLAG_MULTI_PROMISC);
5301         vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5302
5303         if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5304                 vmolr |= E1000_VMOLR_MPME;
5305                 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
5306                 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5307         } else {
5308                 /* if we have hashes and we are clearing a multicast promisc
5309                  * flag we need to write the hashes to the MTA as this step
5310                  * was previously skipped
5311                  */
5312                 if (vf_data->num_vf_mc_hashes > 30) {
5313                         vmolr |= E1000_VMOLR_MPME;
5314                 } else if (vf_data->num_vf_mc_hashes) {
5315                         int j;
5316                         vmolr |= E1000_VMOLR_ROMPE;
5317                         for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5318                                 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5319                 }
5320         }
5321
5322         wr32(E1000_VMOLR(vf), vmolr);
5323
5324         /* there are flags left unprocessed, likely not supported */
5325         if (*msgbuf & E1000_VT_MSGINFO_MASK)
5326                 return -EINVAL;
5327
5328         return 0;
5329 }
5330
5331 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5332                                   u32 *msgbuf, u32 vf)
5333 {
5334         int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5335         u16 *hash_list = (u16 *)&msgbuf[1];
5336         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5337         int i;
5338
5339         /* salt away the number of multicast addresses assigned
5340          * to this VF for later use to restore when the PF multi cast
5341          * list changes
5342          */
5343         vf_data->num_vf_mc_hashes = n;
5344
5345         /* only up to 30 hash values supported */
5346         if (n > 30)
5347                 n = 30;
5348
5349         /* store the hashes for later use */
5350         for (i = 0; i < n; i++)
5351                 vf_data->vf_mc_hashes[i] = hash_list[i];
5352
5353         /* Flush and reset the mta with the new values */
5354         igb_set_rx_mode(adapter->netdev);
5355
5356         return 0;
5357 }
5358
5359 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5360 {
5361         struct e1000_hw *hw = &adapter->hw;
5362         struct vf_data_storage *vf_data;
5363         int i, j;
5364
5365         for (i = 0; i < adapter->vfs_allocated_count; i++) {
5366                 u32 vmolr = rd32(E1000_VMOLR(i));
5367                 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5368
5369                 vf_data = &adapter->vf_data[i];
5370
5371                 if ((vf_data->num_vf_mc_hashes > 30) ||
5372                     (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5373                         vmolr |= E1000_VMOLR_MPME;
5374                 } else if (vf_data->num_vf_mc_hashes) {
5375                         vmolr |= E1000_VMOLR_ROMPE;
5376                         for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5377                                 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5378                 }
5379                 wr32(E1000_VMOLR(i), vmolr);
5380         }
5381 }
5382
5383 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5384 {
5385         struct e1000_hw *hw = &adapter->hw;
5386         u32 pool_mask, reg, vid;
5387         int i;
5388
5389         pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5390
5391         /* Find the vlan filter for this id */
5392         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5393                 reg = rd32(E1000_VLVF(i));
5394
5395                 /* remove the vf from the pool */
5396                 reg &= ~pool_mask;
5397
5398                 /* if pool is empty then remove entry from vfta */
5399                 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5400                     (reg & E1000_VLVF_VLANID_ENABLE)) {
5401                         reg = 0;
5402                         vid = reg & E1000_VLVF_VLANID_MASK;
5403                         igb_vfta_set(hw, vid, false);
5404                 }
5405
5406                 wr32(E1000_VLVF(i), reg);
5407         }
5408
5409         adapter->vf_data[vf].vlans_enabled = 0;
5410 }
5411
5412 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5413 {
5414         struct e1000_hw *hw = &adapter->hw;
5415         u32 reg, i;
5416
5417         /* The vlvf table only exists on 82576 hardware and newer */
5418         if (hw->mac.type < e1000_82576)
5419                 return -1;
5420
5421         /* we only need to do this if VMDq is enabled */
5422         if (!adapter->vfs_allocated_count)
5423                 return -1;
5424
5425         /* Find the vlan filter for this id */
5426         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5427                 reg = rd32(E1000_VLVF(i));
5428                 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5429                     vid == (reg & E1000_VLVF_VLANID_MASK))
5430                         break;
5431         }
5432
5433         if (add) {
5434                 if (i == E1000_VLVF_ARRAY_SIZE) {
5435                         /* Did not find a matching VLAN ID entry that was
5436                          * enabled.  Search for a free filter entry, i.e.
5437                          * one without the enable bit set
5438                          */
5439                         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5440                                 reg = rd32(E1000_VLVF(i));
5441                                 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5442                                         break;
5443                         }
5444                 }
5445                 if (i < E1000_VLVF_ARRAY_SIZE) {
5446                         /* Found an enabled/available entry */
5447                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5448
5449                         /* if !enabled we need to set this up in vfta */
5450                         if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
5451                                 /* add VID to filter table */
5452                                 igb_vfta_set(hw, vid, true);
5453                                 reg |= E1000_VLVF_VLANID_ENABLE;
5454                         }
5455                         reg &= ~E1000_VLVF_VLANID_MASK;
5456                         reg |= vid;
5457                         wr32(E1000_VLVF(i), reg);
5458
5459                         /* do not modify RLPML for PF devices */
5460                         if (vf >= adapter->vfs_allocated_count)
5461                                 return 0;
5462
5463                         if (!adapter->vf_data[vf].vlans_enabled) {
5464                                 u32 size;
5465                                 reg = rd32(E1000_VMOLR(vf));
5466                                 size = reg & E1000_VMOLR_RLPML_MASK;
5467                                 size += 4;
5468                                 reg &= ~E1000_VMOLR_RLPML_MASK;
5469                                 reg |= size;
5470                                 wr32(E1000_VMOLR(vf), reg);
5471                         }
5472
5473                         adapter->vf_data[vf].vlans_enabled++;
5474                 }
5475         } else {
5476                 if (i < E1000_VLVF_ARRAY_SIZE) {
5477                         /* remove vf from the pool */
5478                         reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5479                         /* if pool is empty then remove entry from vfta */
5480                         if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5481                                 reg = 0;
5482                                 igb_vfta_set(hw, vid, false);
5483                         }
5484                         wr32(E1000_VLVF(i), reg);
5485
5486                         /* do not modify RLPML for PF devices */
5487                         if (vf >= adapter->vfs_allocated_count)
5488                                 return 0;
5489
5490                         adapter->vf_data[vf].vlans_enabled--;
5491                         if (!adapter->vf_data[vf].vlans_enabled) {
5492                                 u32 size;
5493                                 reg = rd32(E1000_VMOLR(vf));
5494                                 size = reg & E1000_VMOLR_RLPML_MASK;
5495                                 size -= 4;
5496                                 reg &= ~E1000_VMOLR_RLPML_MASK;
5497                                 reg |= size;
5498                                 wr32(E1000_VMOLR(vf), reg);
5499                         }
5500                 }
5501         }
5502         return 0;
5503 }
5504
5505 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5506 {
5507         struct e1000_hw *hw = &adapter->hw;
5508
5509         if (vid)
5510                 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5511         else
5512                 wr32(E1000_VMVIR(vf), 0);
5513 }
5514
5515 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5516                                int vf, u16 vlan, u8 qos)
5517 {
5518         int err = 0;
5519         struct igb_adapter *adapter = netdev_priv(netdev);
5520
5521         if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5522                 return -EINVAL;
5523         if (vlan || qos) {
5524                 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5525                 if (err)
5526                         goto out;
5527                 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5528                 igb_set_vmolr(adapter, vf, !vlan);
5529                 adapter->vf_data[vf].pf_vlan = vlan;
5530                 adapter->vf_data[vf].pf_qos = qos;
5531                 dev_info(&adapter->pdev->dev,
5532                          "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5533                 if (test_bit(__IGB_DOWN, &adapter->state)) {
5534                         dev_warn(&adapter->pdev->dev,
5535                                  "The VF VLAN has been set, but the PF device is not up.\n");
5536                         dev_warn(&adapter->pdev->dev,
5537                                  "Bring the PF device up before attempting to use the VF device.\n");
5538                 }
5539         } else {
5540                 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5541                              false, vf);
5542                 igb_set_vmvir(adapter, vlan, vf);
5543                 igb_set_vmolr(adapter, vf, true);
5544                 adapter->vf_data[vf].pf_vlan = 0;
5545                 adapter->vf_data[vf].pf_qos = 0;
5546         }
5547 out:
5548         return err;
5549 }
5550
5551 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5552 {
5553         int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5554         int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5555
5556         return igb_vlvf_set(adapter, vid, add, vf);
5557 }
5558
5559 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
5560 {
5561         /* clear flags - except flag that indicates PF has set the MAC */
5562         adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
5563         adapter->vf_data[vf].last_nack = jiffies;
5564
5565         /* reset offloads to defaults */
5566         igb_set_vmolr(adapter, vf, true);
5567
5568         /* reset vlans for device */
5569         igb_clear_vf_vfta(adapter, vf);
5570         if (adapter->vf_data[vf].pf_vlan)
5571                 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5572                                     adapter->vf_data[vf].pf_vlan,
5573                                     adapter->vf_data[vf].pf_qos);
5574         else
5575                 igb_clear_vf_vfta(adapter, vf);
5576
5577         /* reset multicast table array for vf */
5578         adapter->vf_data[vf].num_vf_mc_hashes = 0;
5579
5580         /* Flush and reset the mta with the new values */
5581         igb_set_rx_mode(adapter->netdev);
5582 }
5583
5584 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5585 {
5586         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5587
5588         /* clear mac address as we were hotplug removed/added */
5589         if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5590                 eth_zero_addr(vf_mac);
5591
5592         /* process remaining reset events */
5593         igb_vf_reset(adapter, vf);
5594 }
5595
5596 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
5597 {
5598         struct e1000_hw *hw = &adapter->hw;
5599         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5600         int rar_entry = hw->mac.rar_entry_count - (vf + 1);
5601         u32 reg, msgbuf[3];
5602         u8 *addr = (u8 *)(&msgbuf[1]);
5603
5604         /* process all the same items cleared in a function level reset */
5605         igb_vf_reset(adapter, vf);
5606
5607         /* set vf mac address */
5608         igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
5609
5610         /* enable transmit and receive for vf */
5611         reg = rd32(E1000_VFTE);
5612         wr32(E1000_VFTE, reg | (1 << vf));
5613         reg = rd32(E1000_VFRE);
5614         wr32(E1000_VFRE, reg | (1 << vf));
5615
5616         adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
5617
5618         /* reply to reset with ack and vf mac address */
5619         msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5620         memcpy(addr, vf_mac, 6);
5621         igb_write_mbx(hw, msgbuf, 3, vf);
5622 }
5623
5624 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5625 {
5626         /* The VF MAC Address is stored in a packed array of bytes
5627          * starting at the second 32 bit word of the msg array
5628          */
5629         unsigned char *addr = (char *)&msg[1];
5630         int err = -1;
5631
5632         if (is_valid_ether_addr(addr))
5633                 err = igb_set_vf_mac(adapter, vf, addr);
5634
5635         return err;
5636 }
5637
5638 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5639 {
5640         struct e1000_hw *hw = &adapter->hw;
5641         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5642         u32 msg = E1000_VT_MSGTYPE_NACK;
5643
5644         /* if device isn't clear to send it shouldn't be reading either */
5645         if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5646             time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
5647                 igb_write_mbx(hw, &msg, 1, vf);
5648                 vf_data->last_nack = jiffies;
5649         }
5650 }
5651
5652 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
5653 {
5654         struct pci_dev *pdev = adapter->pdev;
5655         u32 msgbuf[E1000_VFMAILBOX_SIZE];
5656         struct e1000_hw *hw = &adapter->hw;
5657         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5658         s32 retval;
5659
5660         retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
5661
5662         if (retval) {
5663                 /* if receive failed revoke VF CTS stats and restart init */
5664                 dev_err(&pdev->dev, "Error receiving message from VF\n");
5665                 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5666                 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5667                         return;
5668                 goto out;
5669         }
5670
5671         /* this is a message we already processed, do nothing */
5672         if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
5673                 return;
5674
5675         /* until the vf completes a reset it should not be
5676          * allowed to start any configuration.
5677          */
5678         if (msgbuf[0] == E1000_VF_RESET) {
5679                 igb_vf_reset_msg(adapter, vf);
5680                 return;
5681         }
5682
5683         if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
5684                 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5685                         return;
5686                 retval = -1;
5687                 goto out;
5688         }
5689
5690         switch ((msgbuf[0] & 0xFFFF)) {
5691         case E1000_VF_SET_MAC_ADDR:
5692                 retval = -EINVAL;
5693                 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5694                         retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5695                 else
5696                         dev_warn(&pdev->dev,
5697                                  "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
5698                                  vf);
5699                 break;
5700         case E1000_VF_SET_PROMISC:
5701                 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5702                 break;
5703         case E1000_VF_SET_MULTICAST:
5704                 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5705                 break;
5706         case E1000_VF_SET_LPE:
5707                 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5708                 break;
5709         case E1000_VF_SET_VLAN:
5710                 retval = -1;
5711                 if (vf_data->pf_vlan)
5712                         dev_warn(&pdev->dev,
5713                                  "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
5714                                  vf);
5715                 else
5716                         retval = igb_set_vf_vlan(adapter, msgbuf, vf);
5717                 break;
5718         default:
5719                 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
5720                 retval = -1;
5721                 break;
5722         }
5723
5724         msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5725 out:
5726         /* notify the VF of the results of what it sent us */
5727         if (retval)
5728                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5729         else
5730                 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5731
5732         igb_write_mbx(hw, msgbuf, 1, vf);
5733 }
5734
5735 static void igb_msg_task(struct igb_adapter *adapter)
5736 {
5737         struct e1000_hw *hw = &adapter->hw;
5738         u32 vf;
5739
5740         for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5741                 /* process any reset requests */
5742                 if (!igb_check_for_rst(hw, vf))
5743                         igb_vf_reset_event(adapter, vf);
5744
5745                 /* process any messages pending */
5746                 if (!igb_check_for_msg(hw, vf))
5747                         igb_rcv_msg_from_vf(adapter, vf);
5748
5749                 /* process any acks */
5750                 if (!igb_check_for_ack(hw, vf))
5751                         igb_rcv_ack_from_vf(adapter, vf);
5752         }
5753 }
5754
5755 /**
5756  *  igb_set_uta - Set unicast filter table address
5757  *  @adapter: board private structure
5758  *
5759  *  The unicast table address is a register array of 32-bit registers.
5760  *  The table is meant to be used in a way similar to how the MTA is used
5761  *  however due to certain limitations in the hardware it is necessary to
5762  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5763  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
5764  **/
5765 static void igb_set_uta(struct igb_adapter *adapter)
5766 {
5767         struct e1000_hw *hw = &adapter->hw;
5768         int i;
5769
5770         /* The UTA table only exists on 82576 hardware and newer */
5771         if (hw->mac.type < e1000_82576)
5772                 return;
5773
5774         /* we only need to do this if VMDq is enabled */
5775         if (!adapter->vfs_allocated_count)
5776                 return;
5777
5778         for (i = 0; i < hw->mac.uta_reg_count; i++)
5779                 array_wr32(E1000_UTA, i, ~0);
5780 }
5781
5782 /**
5783  *  igb_intr_msi - Interrupt Handler
5784  *  @irq: interrupt number
5785  *  @data: pointer to a network interface device structure
5786  **/
5787 static irqreturn_t igb_intr_msi(int irq, void *data)
5788 {
5789         struct igb_adapter *adapter = data;
5790         struct igb_q_vector *q_vector = adapter->q_vector[0];
5791         struct e1000_hw *hw = &adapter->hw;
5792         /* read ICR disables interrupts using IAM */
5793         u32 icr = rd32(E1000_ICR);
5794
5795         igb_write_itr(q_vector);
5796
5797         if (icr & E1000_ICR_DRSTA)
5798                 schedule_work(&adapter->reset_task);
5799
5800         if (icr & E1000_ICR_DOUTSYNC) {
5801                 /* HW is reporting DMA is out of sync */
5802                 adapter->stats.doosync++;
5803         }
5804
5805         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5806                 hw->mac.get_link_status = 1;
5807                 if (!test_bit(__IGB_DOWN, &adapter->state))
5808                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
5809         }
5810
5811         if (icr & E1000_ICR_TS) {
5812                 u32 tsicr = rd32(E1000_TSICR);
5813
5814                 if (tsicr & E1000_TSICR_TXTS) {
5815                         /* acknowledge the interrupt */
5816                         wr32(E1000_TSICR, E1000_TSICR_TXTS);
5817                         /* retrieve hardware timestamp */
5818                         schedule_work(&adapter->ptp_tx_work);
5819                 }
5820         }
5821
5822         napi_schedule(&q_vector->napi);
5823
5824         return IRQ_HANDLED;
5825 }
5826
5827 /**
5828  *  igb_intr - Legacy Interrupt Handler
5829  *  @irq: interrupt number
5830  *  @data: pointer to a network interface device structure
5831  **/
5832 static irqreturn_t igb_intr(int irq, void *data)
5833 {
5834         struct igb_adapter *adapter = data;
5835         struct igb_q_vector *q_vector = adapter->q_vector[0];
5836         struct e1000_hw *hw = &adapter->hw;
5837         /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
5838          * need for the IMC write
5839          */
5840         u32 icr = rd32(E1000_ICR);
5841
5842         /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5843          * not set, then the adapter didn't send an interrupt
5844          */
5845         if (!(icr & E1000_ICR_INT_ASSERTED))
5846                 return IRQ_NONE;
5847
5848         igb_write_itr(q_vector);
5849
5850         if (icr & E1000_ICR_DRSTA)
5851                 schedule_work(&adapter->reset_task);
5852
5853         if (icr & E1000_ICR_DOUTSYNC) {
5854                 /* HW is reporting DMA is out of sync */
5855                 adapter->stats.doosync++;
5856         }
5857
5858         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5859                 hw->mac.get_link_status = 1;
5860                 /* guard against interrupt when we're going down */
5861                 if (!test_bit(__IGB_DOWN, &adapter->state))
5862                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
5863         }
5864
5865         if (icr & E1000_ICR_TS) {
5866                 u32 tsicr = rd32(E1000_TSICR);
5867
5868                 if (tsicr & E1000_TSICR_TXTS) {
5869                         /* acknowledge the interrupt */
5870                         wr32(E1000_TSICR, E1000_TSICR_TXTS);
5871                         /* retrieve hardware timestamp */
5872                         schedule_work(&adapter->ptp_tx_work);
5873                 }
5874         }
5875
5876         napi_schedule(&q_vector->napi);
5877
5878         return IRQ_HANDLED;
5879 }
5880
5881 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
5882 {
5883         struct igb_adapter *adapter = q_vector->adapter;
5884         struct e1000_hw *hw = &adapter->hw;
5885
5886         if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5887             (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5888                 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5889                         igb_set_itr(q_vector);
5890                 else
5891                         igb_update_ring_itr(q_vector);
5892         }
5893
5894         if (!test_bit(__IGB_DOWN, &adapter->state)) {
5895                 if (adapter->msix_entries)
5896                         wr32(E1000_EIMS, q_vector->eims_value);
5897                 else
5898                         igb_irq_enable(adapter);
5899         }
5900 }
5901
5902 /**
5903  *  igb_poll - NAPI Rx polling callback
5904  *  @napi: napi polling structure
5905  *  @budget: count of how many packets we should handle
5906  **/
5907 static int igb_poll(struct napi_struct *napi, int budget)
5908 {
5909         struct igb_q_vector *q_vector = container_of(napi,
5910                                                      struct igb_q_vector,
5911                                                      napi);
5912         bool clean_complete = true;
5913
5914 #ifdef CONFIG_IGB_DCA
5915         if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5916                 igb_update_dca(q_vector);
5917 #endif
5918         if (q_vector->tx.ring)
5919                 clean_complete = igb_clean_tx_irq(q_vector);
5920
5921         if (q_vector->rx.ring)
5922                 clean_complete &= igb_clean_rx_irq(q_vector, budget);
5923
5924         /* If all work not completed, return budget and keep polling */
5925         if (!clean_complete)
5926                 return budget;
5927
5928         /* If not enough Rx work done, exit the polling mode */
5929         napi_complete(napi);
5930         igb_ring_irq_enable(q_vector);
5931
5932         return 0;
5933 }
5934
5935 /**
5936  *  igb_clean_tx_irq - Reclaim resources after transmit completes
5937  *  @q_vector: pointer to q_vector containing needed info
5938  *
5939  *  returns true if ring is completely cleaned
5940  **/
5941 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
5942 {
5943         struct igb_adapter *adapter = q_vector->adapter;
5944         struct igb_ring *tx_ring = q_vector->tx.ring;
5945         struct igb_tx_buffer *tx_buffer;
5946         union e1000_adv_tx_desc *tx_desc;
5947         unsigned int total_bytes = 0, total_packets = 0;
5948         unsigned int budget = q_vector->tx.work_limit;
5949         unsigned int i = tx_ring->next_to_clean;
5950
5951         if (test_bit(__IGB_DOWN, &adapter->state))
5952                 return true;
5953
5954         tx_buffer = &tx_ring->tx_buffer_info[i];
5955         tx_desc = IGB_TX_DESC(tx_ring, i);
5956         i -= tx_ring->count;
5957
5958         do {
5959                 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
5960
5961                 /* if next_to_watch is not set then there is no work pending */
5962                 if (!eop_desc)
5963                         break;
5964
5965                 /* prevent any other reads prior to eop_desc */
5966                 read_barrier_depends();
5967
5968                 /* if DD is not set pending work has not been completed */
5969                 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
5970                         break;
5971
5972                 /* clear next_to_watch to prevent false hangs */
5973                 tx_buffer->next_to_watch = NULL;
5974
5975                 /* update the statistics for this packet */
5976                 total_bytes += tx_buffer->bytecount;
5977                 total_packets += tx_buffer->gso_segs;
5978
5979                 /* free the skb */
5980                 dev_kfree_skb_any(tx_buffer->skb);
5981
5982                 /* unmap skb header data */
5983                 dma_unmap_single(tx_ring->dev,
5984                                  dma_unmap_addr(tx_buffer, dma),
5985                                  dma_unmap_len(tx_buffer, len),
5986                                  DMA_TO_DEVICE);
5987
5988                 /* clear tx_buffer data */
5989                 tx_buffer->skb = NULL;
5990                 dma_unmap_len_set(tx_buffer, len, 0);
5991
5992                 /* clear last DMA location and unmap remaining buffers */
5993                 while (tx_desc != eop_desc) {
5994                         tx_buffer++;
5995                         tx_desc++;
5996                         i++;
5997                         if (unlikely(!i)) {
5998                                 i -= tx_ring->count;
5999                                 tx_buffer = tx_ring->tx_buffer_info;
6000                                 tx_desc = IGB_TX_DESC(tx_ring, 0);
6001                         }
6002
6003                         /* unmap any remaining paged data */
6004                         if (dma_unmap_len(tx_buffer, len)) {
6005                                 dma_unmap_page(tx_ring->dev,
6006                                                dma_unmap_addr(tx_buffer, dma),
6007                                                dma_unmap_len(tx_buffer, len),
6008                                                DMA_TO_DEVICE);
6009                                 dma_unmap_len_set(tx_buffer, len, 0);
6010                         }
6011                 }
6012
6013                 /* move us one more past the eop_desc for start of next pkt */
6014                 tx_buffer++;
6015                 tx_desc++;
6016                 i++;
6017                 if (unlikely(!i)) {
6018                         i -= tx_ring->count;
6019                         tx_buffer = tx_ring->tx_buffer_info;
6020                         tx_desc = IGB_TX_DESC(tx_ring, 0);
6021                 }
6022
6023                 /* issue prefetch for next Tx descriptor */
6024                 prefetch(tx_desc);
6025
6026                 /* update budget accounting */
6027                 budget--;
6028         } while (likely(budget));
6029
6030         netdev_tx_completed_queue(txring_txq(tx_ring),
6031                                   total_packets, total_bytes);
6032         i += tx_ring->count;
6033         tx_ring->next_to_clean = i;
6034         u64_stats_update_begin(&tx_ring->tx_syncp);
6035         tx_ring->tx_stats.bytes += total_bytes;
6036         tx_ring->tx_stats.packets += total_packets;
6037         u64_stats_update_end(&tx_ring->tx_syncp);
6038         q_vector->tx.total_bytes += total_bytes;
6039         q_vector->tx.total_packets += total_packets;
6040
6041         if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
6042                 struct e1000_hw *hw = &adapter->hw;
6043
6044                 /* Detect a transmit hang in hardware, this serializes the
6045                  * check with the clearing of time_stamp and movement of i
6046                  */
6047                 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
6048                 if (tx_buffer->next_to_watch &&
6049                     time_after(jiffies, tx_buffer->time_stamp +
6050                                (adapter->tx_timeout_factor * HZ)) &&
6051                     !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
6052
6053                         /* detected Tx unit hang */
6054                         dev_err(tx_ring->dev,
6055                                 "Detected Tx Unit Hang\n"
6056                                 "  Tx Queue             <%d>\n"
6057                                 "  TDH                  <%x>\n"
6058                                 "  TDT                  <%x>\n"
6059                                 "  next_to_use          <%x>\n"
6060                                 "  next_to_clean        <%x>\n"
6061                                 "buffer_info[next_to_clean]\n"
6062                                 "  time_stamp           <%lx>\n"
6063                                 "  next_to_watch        <%p>\n"
6064                                 "  jiffies              <%lx>\n"
6065                                 "  desc.status          <%x>\n",
6066                                 tx_ring->queue_index,
6067                                 rd32(E1000_TDH(tx_ring->reg_idx)),
6068                                 readl(tx_ring->tail),
6069                                 tx_ring->next_to_use,
6070                                 tx_ring->next_to_clean,
6071                                 tx_buffer->time_stamp,
6072                                 tx_buffer->next_to_watch,
6073                                 jiffies,
6074                                 tx_buffer->next_to_watch->wb.status);
6075                         netif_stop_subqueue(tx_ring->netdev,
6076                                             tx_ring->queue_index);
6077
6078                         /* we are about to reset, no point in enabling stuff */
6079                         return true;
6080                 }
6081         }
6082
6083 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
6084         if (unlikely(total_packets &&
6085             netif_carrier_ok(tx_ring->netdev) &&
6086             igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
6087                 /* Make sure that anybody stopping the queue after this
6088                  * sees the new next_to_clean.
6089                  */
6090                 smp_mb();
6091                 if (__netif_subqueue_stopped(tx_ring->netdev,
6092                                              tx_ring->queue_index) &&
6093                     !(test_bit(__IGB_DOWN, &adapter->state))) {
6094                         netif_wake_subqueue(tx_ring->netdev,
6095                                             tx_ring->queue_index);
6096
6097                         u64_stats_update_begin(&tx_ring->tx_syncp);
6098                         tx_ring->tx_stats.restart_queue++;
6099                         u64_stats_update_end(&tx_ring->tx_syncp);
6100                 }
6101         }
6102
6103         return !!budget;
6104 }
6105
6106 /**
6107  *  igb_reuse_rx_page - page flip buffer and store it back on the ring
6108  *  @rx_ring: rx descriptor ring to store buffers on
6109  *  @old_buff: donor buffer to have page reused
6110  *
6111  *  Synchronizes page for reuse by the adapter
6112  **/
6113 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6114                               struct igb_rx_buffer *old_buff)
6115 {
6116         struct igb_rx_buffer *new_buff;
6117         u16 nta = rx_ring->next_to_alloc;
6118
6119         new_buff = &rx_ring->rx_buffer_info[nta];
6120
6121         /* update, and store next to alloc */
6122         nta++;
6123         rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6124
6125         /* transfer page from old buffer to new buffer */
6126         memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
6127
6128         /* sync the buffer for use by the device */
6129         dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6130                                          old_buff->page_offset,
6131                                          IGB_RX_BUFSZ,
6132                                          DMA_FROM_DEVICE);
6133 }
6134
6135 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6136                                   struct page *page,
6137                                   unsigned int truesize)
6138 {
6139         /* avoid re-using remote pages */
6140         if (unlikely(page_to_nid(page) != numa_node_id()))
6141                 return false;
6142
6143 #if (PAGE_SIZE < 8192)
6144         /* if we are only owner of page we can reuse it */
6145         if (unlikely(page_count(page) != 1))
6146                 return false;
6147
6148         /* flip page offset to other buffer */
6149         rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6150
6151         /* since we are the only owner of the page and we need to
6152          * increment it, just set the value to 2 in order to avoid
6153          * an unnecessary locked operation
6154          */
6155         atomic_set(&page->_count, 2);
6156 #else
6157         /* move offset up to the next cache line */
6158         rx_buffer->page_offset += truesize;
6159
6160         if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6161                 return false;
6162
6163         /* bump ref count on page before it is given to the stack */
6164         get_page(page);
6165 #endif
6166
6167         return true;
6168 }
6169
6170 /**
6171  *  igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6172  *  @rx_ring: rx descriptor ring to transact packets on
6173  *  @rx_buffer: buffer containing page to add
6174  *  @rx_desc: descriptor containing length of buffer written by hardware
6175  *  @skb: sk_buff to place the data into
6176  *
6177  *  This function will add the data contained in rx_buffer->page to the skb.
6178  *  This is done either through a direct copy if the data in the buffer is
6179  *  less than the skb header size, otherwise it will just attach the page as
6180  *  a frag to the skb.
6181  *
6182  *  The function will then update the page offset if necessary and return
6183  *  true if the buffer can be reused by the adapter.
6184  **/
6185 static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6186                             struct igb_rx_buffer *rx_buffer,
6187                             union e1000_adv_rx_desc *rx_desc,
6188                             struct sk_buff *skb)
6189 {
6190         struct page *page = rx_buffer->page;
6191         unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
6192 #if (PAGE_SIZE < 8192)
6193         unsigned int truesize = IGB_RX_BUFSZ;
6194 #else
6195         unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6196 #endif
6197
6198         if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6199                 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6200
6201                 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6202                         igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6203                         va += IGB_TS_HDR_LEN;
6204                         size -= IGB_TS_HDR_LEN;
6205                 }
6206
6207                 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6208
6209                 /* we can reuse buffer as-is, just make sure it is local */
6210                 if (likely(page_to_nid(page) == numa_node_id()))
6211                         return true;
6212
6213                 /* this page cannot be reused so discard it */
6214                 put_page(page);
6215                 return false;
6216         }
6217
6218         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
6219                         rx_buffer->page_offset, size, truesize);
6220
6221         return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6222 }
6223
6224 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6225                                            union e1000_adv_rx_desc *rx_desc,
6226                                            struct sk_buff *skb)
6227 {
6228         struct igb_rx_buffer *rx_buffer;
6229         struct page *page;
6230
6231         rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6232
6233         page = rx_buffer->page;
6234         prefetchw(page);
6235
6236         if (likely(!skb)) {
6237                 void *page_addr = page_address(page) +
6238                                   rx_buffer->page_offset;
6239
6240                 /* prefetch first cache line of first page */
6241                 prefetch(page_addr);
6242 #if L1_CACHE_BYTES < 128
6243                 prefetch(page_addr + L1_CACHE_BYTES);
6244 #endif
6245
6246                 /* allocate a skb to store the frags */
6247                 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6248                                                 IGB_RX_HDR_LEN);
6249                 if (unlikely(!skb)) {
6250                         rx_ring->rx_stats.alloc_failed++;
6251                         return NULL;
6252                 }
6253
6254                 /* we will be copying header into skb->data in
6255                  * pskb_may_pull so it is in our interest to prefetch
6256                  * it now to avoid a possible cache miss
6257                  */
6258                 prefetchw(skb->data);
6259         }
6260
6261         /* we are reusing so sync this buffer for CPU use */
6262         dma_sync_single_range_for_cpu(rx_ring->dev,
6263                                       rx_buffer->dma,
6264                                       rx_buffer->page_offset,
6265                                       IGB_RX_BUFSZ,
6266                                       DMA_FROM_DEVICE);
6267
6268         /* pull page into skb */
6269         if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6270                 /* hand second half of page back to the ring */
6271                 igb_reuse_rx_page(rx_ring, rx_buffer);
6272         } else {
6273                 /* we are not reusing the buffer so unmap it */
6274                 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6275                                PAGE_SIZE, DMA_FROM_DEVICE);
6276         }
6277
6278         /* clear contents of rx_buffer */
6279         rx_buffer->page = NULL;
6280
6281         return skb;
6282 }
6283
6284 static inline void igb_rx_checksum(struct igb_ring *ring,
6285                                    union e1000_adv_rx_desc *rx_desc,
6286                                    struct sk_buff *skb)
6287 {
6288         skb_checksum_none_assert(skb);
6289
6290         /* Ignore Checksum bit is set */
6291         if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
6292                 return;
6293
6294         /* Rx checksum disabled via ethtool */
6295         if (!(ring->netdev->features & NETIF_F_RXCSUM))
6296                 return;
6297
6298         /* TCP/UDP checksum error bit is set */
6299         if (igb_test_staterr(rx_desc,
6300                              E1000_RXDEXT_STATERR_TCPE |
6301                              E1000_RXDEXT_STATERR_IPE)) {
6302                 /* work around errata with sctp packets where the TCPE aka
6303                  * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6304                  * packets, (aka let the stack check the crc32c)
6305                  */
6306                 if (!((skb->len == 60) &&
6307                       test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
6308                         u64_stats_update_begin(&ring->rx_syncp);
6309                         ring->rx_stats.csum_err++;
6310                         u64_stats_update_end(&ring->rx_syncp);
6311                 }
6312                 /* let the stack verify checksum errors */
6313                 return;
6314         }
6315         /* It must be a TCP or UDP packet with a valid checksum */
6316         if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6317                                       E1000_RXD_STAT_UDPCS))
6318                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6319
6320         dev_dbg(ring->dev, "cksum success: bits %08X\n",
6321                 le32_to_cpu(rx_desc->wb.upper.status_error));
6322 }
6323
6324 static inline void igb_rx_hash(struct igb_ring *ring,
6325                                union e1000_adv_rx_desc *rx_desc,
6326                                struct sk_buff *skb)
6327 {
6328         if (ring->netdev->features & NETIF_F_RXHASH)
6329                 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6330 }
6331
6332 /**
6333  *  igb_is_non_eop - process handling of non-EOP buffers
6334  *  @rx_ring: Rx ring being processed
6335  *  @rx_desc: Rx descriptor for current buffer
6336  *  @skb: current socket buffer containing buffer in progress
6337  *
6338  *  This function updates next to clean.  If the buffer is an EOP buffer
6339  *  this function exits returning false, otherwise it will place the
6340  *  sk_buff in the next buffer to be chained and return true indicating
6341  *  that this is in fact a non-EOP buffer.
6342  **/
6343 static bool igb_is_non_eop(struct igb_ring *rx_ring,
6344                            union e1000_adv_rx_desc *rx_desc)
6345 {
6346         u32 ntc = rx_ring->next_to_clean + 1;
6347
6348         /* fetch, update, and store next to clean */
6349         ntc = (ntc < rx_ring->count) ? ntc : 0;
6350         rx_ring->next_to_clean = ntc;
6351
6352         prefetch(IGB_RX_DESC(rx_ring, ntc));
6353
6354         if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6355                 return false;
6356
6357         return true;
6358 }
6359
6360 /**
6361  *  igb_get_headlen - determine size of header for LRO/GRO
6362  *  @data: pointer to the start of the headers
6363  *  @max_len: total length of section to find headers in
6364  *
6365  *  This function is meant to determine the length of headers that will
6366  *  be recognized by hardware for LRO, and GRO offloads.  The main
6367  *  motivation of doing this is to only perform one pull for IPv4 TCP
6368  *  packets so that we can do basic things like calculating the gso_size
6369  *  based on the average data per packet.
6370  **/
6371 static unsigned int igb_get_headlen(unsigned char *data,
6372                                     unsigned int max_len)
6373 {
6374         union {
6375                 unsigned char *network;
6376                 /* l2 headers */
6377                 struct ethhdr *eth;
6378                 struct vlan_hdr *vlan;
6379                 /* l3 headers */
6380                 struct iphdr *ipv4;
6381                 struct ipv6hdr *ipv6;
6382         } hdr;
6383         __be16 protocol;
6384         u8 nexthdr = 0; /* default to not TCP */
6385         u8 hlen;
6386
6387         /* this should never happen, but better safe than sorry */
6388         if (max_len < ETH_HLEN)
6389                 return max_len;
6390
6391         /* initialize network frame pointer */
6392         hdr.network = data;
6393
6394         /* set first protocol and move network header forward */
6395         protocol = hdr.eth->h_proto;
6396         hdr.network += ETH_HLEN;
6397
6398         /* handle any vlan tag if present */
6399         if (protocol == __constant_htons(ETH_P_8021Q)) {
6400                 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6401                         return max_len;
6402
6403                 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6404                 hdr.network += VLAN_HLEN;
6405         }
6406
6407         /* handle L3 protocols */
6408         if (protocol == __constant_htons(ETH_P_IP)) {
6409                 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6410                         return max_len;
6411
6412                 /* access ihl as a u8 to avoid unaligned access on ia64 */
6413                 hlen = (hdr.network[0] & 0x0F) << 2;
6414
6415                 /* verify hlen meets minimum size requirements */
6416                 if (hlen < sizeof(struct iphdr))
6417                         return hdr.network - data;
6418
6419                 /* record next protocol if header is present */
6420                 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
6421                         nexthdr = hdr.ipv4->protocol;
6422         } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6423                 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6424                         return max_len;
6425
6426                 /* record next protocol */
6427                 nexthdr = hdr.ipv6->nexthdr;
6428                 hlen = sizeof(struct ipv6hdr);
6429         } else {
6430                 return hdr.network - data;
6431         }
6432
6433         /* relocate pointer to start of L4 header */
6434         hdr.network += hlen;
6435
6436         /* finally sort out TCP */
6437         if (nexthdr == IPPROTO_TCP) {
6438                 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6439                         return max_len;
6440
6441                 /* access doff as a u8 to avoid unaligned access on ia64 */
6442                 hlen = (hdr.network[12] & 0xF0) >> 2;
6443
6444                 /* verify hlen meets minimum size requirements */
6445                 if (hlen < sizeof(struct tcphdr))
6446                         return hdr.network - data;
6447
6448                 hdr.network += hlen;
6449         } else if (nexthdr == IPPROTO_UDP) {
6450                 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6451                         return max_len;
6452
6453                 hdr.network += sizeof(struct udphdr);
6454         }
6455
6456         /* If everything has gone correctly hdr.network should be the
6457          * data section of the packet and will be the end of the header.
6458          * If not then it probably represents the end of the last recognized
6459          * header.
6460          */
6461         if ((hdr.network - data) < max_len)
6462                 return hdr.network - data;
6463         else
6464                 return max_len;
6465 }
6466
6467 /**
6468  *  igb_pull_tail - igb specific version of skb_pull_tail
6469  *  @rx_ring: rx descriptor ring packet is being transacted on
6470  *  @rx_desc: pointer to the EOP Rx descriptor
6471  *  @skb: pointer to current skb being adjusted
6472  *
6473  *  This function is an igb specific version of __pskb_pull_tail.  The
6474  *  main difference between this version and the original function is that
6475  *  this function can make several assumptions about the state of things
6476  *  that allow for significant optimizations versus the standard function.
6477  *  As a result we can do things like drop a frag and maintain an accurate
6478  *  truesize for the skb.
6479  */
6480 static void igb_pull_tail(struct igb_ring *rx_ring,
6481                           union e1000_adv_rx_desc *rx_desc,
6482                           struct sk_buff *skb)
6483 {
6484         struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6485         unsigned char *va;
6486         unsigned int pull_len;
6487
6488         /* it is valid to use page_address instead of kmap since we are
6489          * working with pages allocated out of the lomem pool per
6490          * alloc_page(GFP_ATOMIC)
6491          */
6492         va = skb_frag_address(frag);
6493
6494         if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6495                 /* retrieve timestamp from buffer */
6496                 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6497
6498                 /* update pointers to remove timestamp header */
6499                 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6500                 frag->page_offset += IGB_TS_HDR_LEN;
6501                 skb->data_len -= IGB_TS_HDR_LEN;
6502                 skb->len -= IGB_TS_HDR_LEN;
6503
6504                 /* move va to start of packet data */
6505                 va += IGB_TS_HDR_LEN;
6506         }
6507
6508         /* we need the header to contain the greater of either ETH_HLEN or
6509          * 60 bytes if the skb->len is less than 60 for skb_pad.
6510          */
6511         pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6512
6513         /* align pull length to size of long to optimize memcpy performance */
6514         skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6515
6516         /* update all of the pointers */
6517         skb_frag_size_sub(frag, pull_len);
6518         frag->page_offset += pull_len;
6519         skb->data_len -= pull_len;
6520         skb->tail += pull_len;
6521 }
6522
6523 /**
6524  *  igb_cleanup_headers - Correct corrupted or empty headers
6525  *  @rx_ring: rx descriptor ring packet is being transacted on
6526  *  @rx_desc: pointer to the EOP Rx descriptor
6527  *  @skb: pointer to current skb being fixed
6528  *
6529  *  Address the case where we are pulling data in on pages only
6530  *  and as such no data is present in the skb header.
6531  *
6532  *  In addition if skb is not at least 60 bytes we need to pad it so that
6533  *  it is large enough to qualify as a valid Ethernet frame.
6534  *
6535  *  Returns true if an error was encountered and skb was freed.
6536  **/
6537 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6538                                 union e1000_adv_rx_desc *rx_desc,
6539                                 struct sk_buff *skb)
6540 {
6541         if (unlikely((igb_test_staterr(rx_desc,
6542                                        E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6543                 struct net_device *netdev = rx_ring->netdev;
6544                 if (!(netdev->features & NETIF_F_RXALL)) {
6545                         dev_kfree_skb_any(skb);
6546                         return true;
6547                 }
6548         }
6549
6550         /* place header in linear portion of buffer */
6551         if (skb_is_nonlinear(skb))
6552                 igb_pull_tail(rx_ring, rx_desc, skb);
6553
6554         /* if skb_pad returns an error the skb was freed */
6555         if (unlikely(skb->len < 60)) {
6556                 int pad_len = 60 - skb->len;
6557
6558                 if (skb_pad(skb, pad_len))
6559                         return true;
6560                 __skb_put(skb, pad_len);
6561         }
6562
6563         return false;
6564 }
6565
6566 /**
6567  *  igb_process_skb_fields - Populate skb header fields from Rx descriptor
6568  *  @rx_ring: rx descriptor ring packet is being transacted on
6569  *  @rx_desc: pointer to the EOP Rx descriptor
6570  *  @skb: pointer to current skb being populated
6571  *
6572  *  This function checks the ring, descriptor, and packet information in
6573  *  order to populate the hash, checksum, VLAN, timestamp, protocol, and
6574  *  other fields within the skb.
6575  **/
6576 static void igb_process_skb_fields(struct igb_ring *rx_ring,
6577                                    union e1000_adv_rx_desc *rx_desc,
6578                                    struct sk_buff *skb)
6579 {
6580         struct net_device *dev = rx_ring->netdev;
6581
6582         igb_rx_hash(rx_ring, rx_desc, skb);
6583
6584         igb_rx_checksum(rx_ring, rx_desc, skb);
6585
6586         igb_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
6587
6588         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
6589             igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6590                 u16 vid;
6591                 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6592                     test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6593                         vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6594                 else
6595                         vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6596
6597                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
6598         }
6599
6600         skb_record_rx_queue(skb, rx_ring->queue_index);
6601
6602         skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6603 }
6604
6605 static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
6606 {
6607         struct igb_ring *rx_ring = q_vector->rx.ring;
6608         struct sk_buff *skb = rx_ring->skb;
6609         unsigned int total_bytes = 0, total_packets = 0;
6610         u16 cleaned_count = igb_desc_unused(rx_ring);
6611
6612         do {
6613                 union e1000_adv_rx_desc *rx_desc;
6614
6615                 /* return some buffers to hardware, one at a time is too slow */
6616                 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6617                         igb_alloc_rx_buffers(rx_ring, cleaned_count);
6618                         cleaned_count = 0;
6619                 }
6620
6621                 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
6622
6623                 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6624                         break;
6625
6626                 /* This memory barrier is needed to keep us from reading
6627                  * any other fields out of the rx_desc until we know the
6628                  * RXD_STAT_DD bit is set
6629                  */
6630                 rmb();
6631
6632                 /* retrieve a buffer from the ring */
6633                 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
6634
6635                 /* exit if we failed to retrieve a buffer */
6636                 if (!skb)
6637                         break;
6638
6639                 cleaned_count++;
6640
6641                 /* fetch next buffer in frame if non-eop */
6642                 if (igb_is_non_eop(rx_ring, rx_desc))
6643                         continue;
6644
6645                 /* verify the packet layout is correct */
6646                 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6647                         skb = NULL;
6648                         continue;
6649                 }
6650
6651                 /* probably a little skewed due to removing CRC */
6652                 total_bytes += skb->len;
6653
6654                 /* populate checksum, timestamp, VLAN, and protocol */
6655                 igb_process_skb_fields(rx_ring, rx_desc, skb);
6656
6657                 napi_gro_receive(&q_vector->napi, skb);
6658
6659                 /* reset skb pointer */
6660                 skb = NULL;
6661
6662                 /* update budget accounting */
6663                 total_packets++;
6664         } while (likely(total_packets < budget));
6665
6666         /* place incomplete frames back on ring for completion */
6667         rx_ring->skb = skb;
6668
6669         u64_stats_update_begin(&rx_ring->rx_syncp);
6670         rx_ring->rx_stats.packets += total_packets;
6671         rx_ring->rx_stats.bytes += total_bytes;
6672         u64_stats_update_end(&rx_ring->rx_syncp);
6673         q_vector->rx.total_packets += total_packets;
6674         q_vector->rx.total_bytes += total_bytes;
6675
6676         if (cleaned_count)
6677                 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6678
6679         return (total_packets < budget);
6680 }
6681
6682 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
6683                                   struct igb_rx_buffer *bi)
6684 {
6685         struct page *page = bi->page;
6686         dma_addr_t dma;
6687
6688         /* since we are recycling buffers we should seldom need to alloc */
6689         if (likely(page))
6690                 return true;
6691
6692         /* alloc new page for storage */
6693         page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6694         if (unlikely(!page)) {
6695                 rx_ring->rx_stats.alloc_failed++;
6696                 return false;
6697         }
6698
6699         /* map page for use */
6700         dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
6701
6702         /* if mapping failed free memory back to system since
6703          * there isn't much point in holding memory we can't use
6704          */
6705         if (dma_mapping_error(rx_ring->dev, dma)) {
6706                 __free_page(page);
6707
6708                 rx_ring->rx_stats.alloc_failed++;
6709                 return false;
6710         }
6711
6712         bi->dma = dma;
6713         bi->page = page;
6714         bi->page_offset = 0;
6715
6716         return true;
6717 }
6718
6719 /**
6720  *  igb_alloc_rx_buffers - Replace used receive buffers; packet split
6721  *  @adapter: address of board private structure
6722  **/
6723 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
6724 {
6725         union e1000_adv_rx_desc *rx_desc;
6726         struct igb_rx_buffer *bi;
6727         u16 i = rx_ring->next_to_use;
6728
6729         /* nothing to do */
6730         if (!cleaned_count)
6731                 return;
6732
6733         rx_desc = IGB_RX_DESC(rx_ring, i);
6734         bi = &rx_ring->rx_buffer_info[i];
6735         i -= rx_ring->count;
6736
6737         do {
6738                 if (!igb_alloc_mapped_page(rx_ring, bi))
6739                         break;
6740
6741                 /* Refresh the desc even if buffer_addrs didn't change
6742                  * because each write-back erases this info.
6743                  */
6744                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
6745
6746                 rx_desc++;
6747                 bi++;
6748                 i++;
6749                 if (unlikely(!i)) {
6750                         rx_desc = IGB_RX_DESC(rx_ring, 0);
6751                         bi = rx_ring->rx_buffer_info;
6752                         i -= rx_ring->count;
6753                 }
6754
6755                 /* clear the hdr_addr for the next_to_use descriptor */
6756                 rx_desc->read.hdr_addr = 0;
6757
6758                 cleaned_count--;
6759         } while (cleaned_count);
6760
6761         i += rx_ring->count;
6762
6763         if (rx_ring->next_to_use != i) {
6764                 /* record the next descriptor to use */
6765                 rx_ring->next_to_use = i;
6766
6767                 /* update next to alloc since we have filled the ring */
6768                 rx_ring->next_to_alloc = i;
6769
6770                 /* Force memory writes to complete before letting h/w
6771                  * know there are new descriptors to fetch.  (Only
6772                  * applicable for weak-ordered memory model archs,
6773                  * such as IA-64).
6774                  */
6775                 wmb();
6776                 writel(i, rx_ring->tail);
6777         }
6778 }
6779
6780 /**
6781  * igb_mii_ioctl -
6782  * @netdev:
6783  * @ifreq:
6784  * @cmd:
6785  **/
6786 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6787 {
6788         struct igb_adapter *adapter = netdev_priv(netdev);
6789         struct mii_ioctl_data *data = if_mii(ifr);
6790
6791         if (adapter->hw.phy.media_type != e1000_media_type_copper)
6792                 return -EOPNOTSUPP;
6793
6794         switch (cmd) {
6795         case SIOCGMIIPHY:
6796                 data->phy_id = adapter->hw.phy.addr;
6797                 break;
6798         case SIOCGMIIREG:
6799                 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6800                                      &data->val_out))
6801                         return -EIO;
6802                 break;
6803         case SIOCSMIIREG:
6804         default:
6805                 return -EOPNOTSUPP;
6806         }
6807         return 0;
6808 }
6809
6810 /**
6811  * igb_ioctl -
6812  * @netdev:
6813  * @ifreq:
6814  * @cmd:
6815  **/
6816 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6817 {
6818         switch (cmd) {
6819         case SIOCGMIIPHY:
6820         case SIOCGMIIREG:
6821         case SIOCSMIIREG:
6822                 return igb_mii_ioctl(netdev, ifr, cmd);
6823         case SIOCSHWTSTAMP:
6824                 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
6825         default:
6826                 return -EOPNOTSUPP;
6827         }
6828 }
6829
6830 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6831 {
6832         struct igb_adapter *adapter = hw->back;
6833
6834         if (pcie_capability_read_word(adapter->pdev, reg, value))
6835                 return -E1000_ERR_CONFIG;
6836
6837         return 0;
6838 }
6839
6840 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6841 {
6842         struct igb_adapter *adapter = hw->back;
6843
6844         if (pcie_capability_write_word(adapter->pdev, reg, *value))
6845                 return -E1000_ERR_CONFIG;
6846
6847         return 0;
6848 }
6849
6850 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
6851 {
6852         struct igb_adapter *adapter = netdev_priv(netdev);
6853         struct e1000_hw *hw = &adapter->hw;
6854         u32 ctrl, rctl;
6855         bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
6856
6857         if (enable) {
6858                 /* enable VLAN tag insert/strip */
6859                 ctrl = rd32(E1000_CTRL);
6860                 ctrl |= E1000_CTRL_VME;
6861                 wr32(E1000_CTRL, ctrl);
6862
6863                 /* Disable CFI check */
6864                 rctl = rd32(E1000_RCTL);
6865                 rctl &= ~E1000_RCTL_CFIEN;
6866                 wr32(E1000_RCTL, rctl);
6867         } else {
6868                 /* disable VLAN tag insert/strip */
6869                 ctrl = rd32(E1000_CTRL);
6870                 ctrl &= ~E1000_CTRL_VME;
6871                 wr32(E1000_CTRL, ctrl);
6872         }
6873
6874         igb_rlpml_set(adapter);
6875 }
6876
6877 static int igb_vlan_rx_add_vid(struct net_device *netdev,
6878                                __be16 proto, u16 vid)
6879 {
6880         struct igb_adapter *adapter = netdev_priv(netdev);
6881         struct e1000_hw *hw = &adapter->hw;
6882         int pf_id = adapter->vfs_allocated_count;
6883
6884         /* attempt to add filter to vlvf array */
6885         igb_vlvf_set(adapter, vid, true, pf_id);
6886
6887         /* add the filter since PF can receive vlans w/o entry in vlvf */
6888         igb_vfta_set(hw, vid, true);
6889
6890         set_bit(vid, adapter->active_vlans);
6891
6892         return 0;
6893 }
6894
6895 static int igb_vlan_rx_kill_vid(struct net_device *netdev,
6896                                 __be16 proto, u16 vid)
6897 {
6898         struct igb_adapter *adapter = netdev_priv(netdev);
6899         struct e1000_hw *hw = &adapter->hw;
6900         int pf_id = adapter->vfs_allocated_count;
6901         s32 err;
6902
6903         /* remove vlan from VLVF table array */
6904         err = igb_vlvf_set(adapter, vid, false, pf_id);
6905
6906         /* if vid was not present in VLVF just remove it from table */
6907         if (err)
6908                 igb_vfta_set(hw, vid, false);
6909
6910         clear_bit(vid, adapter->active_vlans);
6911
6912         return 0;
6913 }
6914
6915 static void igb_restore_vlan(struct igb_adapter *adapter)
6916 {
6917         u16 vid;
6918
6919         igb_vlan_mode(adapter->netdev, adapter->netdev->features);
6920
6921         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
6922                 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
6923 }
6924
6925 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
6926 {
6927         struct pci_dev *pdev = adapter->pdev;
6928         struct e1000_mac_info *mac = &adapter->hw.mac;
6929
6930         mac->autoneg = 0;
6931
6932         /* Make sure dplx is at most 1 bit and lsb of speed is not set
6933          * for the switch() below to work
6934          */
6935         if ((spd & 1) || (dplx & ~1))
6936                 goto err_inval;
6937
6938         /* Fiber NIC's only allow 1000 gbps Full duplex
6939          * and 100Mbps Full duplex for 100baseFx sfp
6940          */
6941         if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
6942                 switch (spd + dplx) {
6943                 case SPEED_10 + DUPLEX_HALF:
6944                 case SPEED_10 + DUPLEX_FULL:
6945                 case SPEED_100 + DUPLEX_HALF:
6946                         goto err_inval;
6947                 default:
6948                         break;
6949                 }
6950         }
6951
6952         switch (spd + dplx) {
6953         case SPEED_10 + DUPLEX_HALF:
6954                 mac->forced_speed_duplex = ADVERTISE_10_HALF;
6955                 break;
6956         case SPEED_10 + DUPLEX_FULL:
6957                 mac->forced_speed_duplex = ADVERTISE_10_FULL;
6958                 break;
6959         case SPEED_100 + DUPLEX_HALF:
6960                 mac->forced_speed_duplex = ADVERTISE_100_HALF;
6961                 break;
6962         case SPEED_100 + DUPLEX_FULL:
6963                 mac->forced_speed_duplex = ADVERTISE_100_FULL;
6964                 break;
6965         case SPEED_1000 + DUPLEX_FULL:
6966                 mac->autoneg = 1;
6967                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
6968                 break;
6969         case SPEED_1000 + DUPLEX_HALF: /* not supported */
6970         default:
6971                 goto err_inval;
6972         }
6973
6974         /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
6975         adapter->hw.phy.mdix = AUTO_ALL_MODES;
6976
6977         return 0;
6978
6979 err_inval:
6980         dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
6981         return -EINVAL;
6982 }
6983
6984 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
6985                           bool runtime)
6986 {
6987         struct net_device *netdev = pci_get_drvdata(pdev);
6988         struct igb_adapter *adapter = netdev_priv(netdev);
6989         struct e1000_hw *hw = &adapter->hw;
6990         u32 ctrl, rctl, status;
6991         u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
6992 #ifdef CONFIG_PM
6993         int retval = 0;
6994 #endif
6995
6996         netif_device_detach(netdev);
6997
6998         if (netif_running(netdev))
6999                 __igb_close(netdev, true);
7000
7001         igb_clear_interrupt_scheme(adapter);
7002
7003 #ifdef CONFIG_PM
7004         retval = pci_save_state(pdev);
7005         if (retval)
7006                 return retval;
7007 #endif
7008
7009         status = rd32(E1000_STATUS);
7010         if (status & E1000_STATUS_LU)
7011                 wufc &= ~E1000_WUFC_LNKC;
7012
7013         if (wufc) {
7014                 igb_setup_rctl(adapter);
7015                 igb_set_rx_mode(netdev);
7016
7017                 /* turn on all-multi mode if wake on multicast is enabled */
7018                 if (wufc & E1000_WUFC_MC) {
7019                         rctl = rd32(E1000_RCTL);
7020                         rctl |= E1000_RCTL_MPE;
7021                         wr32(E1000_RCTL, rctl);
7022                 }
7023
7024                 ctrl = rd32(E1000_CTRL);
7025                 /* advertise wake from D3Cold */
7026                 #define E1000_CTRL_ADVD3WUC 0x00100000
7027                 /* phy power management enable */
7028                 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7029                 ctrl |= E1000_CTRL_ADVD3WUC;
7030                 wr32(E1000_CTRL, ctrl);
7031
7032                 /* Allow time for pending master requests to run */
7033                 igb_disable_pcie_master(hw);
7034
7035                 wr32(E1000_WUC, E1000_WUC_PME_EN);
7036                 wr32(E1000_WUFC, wufc);
7037         } else {
7038                 wr32(E1000_WUC, 0);
7039                 wr32(E1000_WUFC, 0);
7040         }
7041
7042         *enable_wake = wufc || adapter->en_mng_pt;
7043         if (!*enable_wake)
7044                 igb_power_down_link(adapter);
7045         else
7046                 igb_power_up_link(adapter);
7047
7048         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
7049          * would have already happened in close and is redundant.
7050          */
7051         igb_release_hw_control(adapter);
7052
7053         pci_disable_device(pdev);
7054
7055         return 0;
7056 }
7057
7058 #ifdef CONFIG_PM
7059 #ifdef CONFIG_PM_SLEEP
7060 static int igb_suspend(struct device *dev)
7061 {
7062         int retval;
7063         bool wake;
7064         struct pci_dev *pdev = to_pci_dev(dev);
7065
7066         retval = __igb_shutdown(pdev, &wake, 0);
7067         if (retval)
7068                 return retval;
7069
7070         if (wake) {
7071                 pci_prepare_to_sleep(pdev);
7072         } else {
7073                 pci_wake_from_d3(pdev, false);
7074                 pci_set_power_state(pdev, PCI_D3hot);
7075         }
7076
7077         return 0;
7078 }
7079 #endif /* CONFIG_PM_SLEEP */
7080
7081 static int igb_resume(struct device *dev)
7082 {
7083         struct pci_dev *pdev = to_pci_dev(dev);
7084         struct net_device *netdev = pci_get_drvdata(pdev);
7085         struct igb_adapter *adapter = netdev_priv(netdev);
7086         struct e1000_hw *hw = &adapter->hw;
7087         u32 err;
7088
7089         pci_set_power_state(pdev, PCI_D0);
7090         pci_restore_state(pdev);
7091         pci_save_state(pdev);
7092
7093         err = pci_enable_device_mem(pdev);
7094         if (err) {
7095                 dev_err(&pdev->dev,
7096                         "igb: Cannot enable PCI device from suspend\n");
7097                 return err;
7098         }
7099         pci_set_master(pdev);
7100
7101         pci_enable_wake(pdev, PCI_D3hot, 0);
7102         pci_enable_wake(pdev, PCI_D3cold, 0);
7103
7104         if (igb_init_interrupt_scheme(adapter, true)) {
7105                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7106                 return -ENOMEM;
7107         }
7108
7109         igb_reset(adapter);
7110
7111         /* let the f/w know that the h/w is now under the control of the
7112          * driver.
7113          */
7114         igb_get_hw_control(adapter);
7115
7116         wr32(E1000_WUS, ~0);
7117
7118         if (netdev->flags & IFF_UP) {
7119                 rtnl_lock();
7120                 err = __igb_open(netdev, true);
7121                 rtnl_unlock();
7122                 if (err)
7123                         return err;
7124         }
7125
7126         netif_device_attach(netdev);
7127         return 0;
7128 }
7129
7130 #ifdef CONFIG_PM_RUNTIME
7131 static int igb_runtime_idle(struct device *dev)
7132 {
7133         struct pci_dev *pdev = to_pci_dev(dev);
7134         struct net_device *netdev = pci_get_drvdata(pdev);
7135         struct igb_adapter *adapter = netdev_priv(netdev);
7136
7137         if (!igb_has_link(adapter))
7138                 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7139
7140         return -EBUSY;
7141 }
7142
7143 static int igb_runtime_suspend(struct device *dev)
7144 {
7145         struct pci_dev *pdev = to_pci_dev(dev);
7146         int retval;
7147         bool wake;
7148
7149         retval = __igb_shutdown(pdev, &wake, 1);
7150         if (retval)
7151                 return retval;
7152
7153         if (wake) {
7154                 pci_prepare_to_sleep(pdev);
7155         } else {
7156                 pci_wake_from_d3(pdev, false);
7157                 pci_set_power_state(pdev, PCI_D3hot);
7158         }
7159
7160         return 0;
7161 }
7162
7163 static int igb_runtime_resume(struct device *dev)
7164 {
7165         return igb_resume(dev);
7166 }
7167 #endif /* CONFIG_PM_RUNTIME */
7168 #endif
7169
7170 static void igb_shutdown(struct pci_dev *pdev)
7171 {
7172         bool wake;
7173
7174         __igb_shutdown(pdev, &wake, 0);
7175
7176         if (system_state == SYSTEM_POWER_OFF) {
7177                 pci_wake_from_d3(pdev, wake);
7178                 pci_set_power_state(pdev, PCI_D3hot);
7179         }
7180 }
7181
7182 #ifdef CONFIG_PCI_IOV
7183 static int igb_sriov_reinit(struct pci_dev *dev)
7184 {
7185         struct net_device *netdev = pci_get_drvdata(dev);
7186         struct igb_adapter *adapter = netdev_priv(netdev);
7187         struct pci_dev *pdev = adapter->pdev;
7188
7189         rtnl_lock();
7190
7191         if (netif_running(netdev))
7192                 igb_close(netdev);
7193
7194         igb_clear_interrupt_scheme(adapter);
7195
7196         igb_init_queue_configuration(adapter);
7197
7198         if (igb_init_interrupt_scheme(adapter, true)) {
7199                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7200                 return -ENOMEM;
7201         }
7202
7203         if (netif_running(netdev))
7204                 igb_open(netdev);
7205
7206         rtnl_unlock();
7207
7208         return 0;
7209 }
7210
7211 static int igb_pci_disable_sriov(struct pci_dev *dev)
7212 {
7213         int err = igb_disable_sriov(dev);
7214
7215         if (!err)
7216                 err = igb_sriov_reinit(dev);
7217
7218         return err;
7219 }
7220
7221 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7222 {
7223         int err = igb_enable_sriov(dev, num_vfs);
7224
7225         if (err)
7226                 goto out;
7227
7228         err = igb_sriov_reinit(dev);
7229         if (!err)
7230                 return num_vfs;
7231
7232 out:
7233         return err;
7234 }
7235
7236 #endif
7237 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7238 {
7239 #ifdef CONFIG_PCI_IOV
7240         if (num_vfs == 0)
7241                 return igb_pci_disable_sriov(dev);
7242         else
7243                 return igb_pci_enable_sriov(dev, num_vfs);
7244 #endif
7245         return 0;
7246 }
7247
7248 #ifdef CONFIG_NET_POLL_CONTROLLER
7249 /* Polling 'interrupt' - used by things like netconsole to send skbs
7250  * without having to re-enable interrupts. It's not called while
7251  * the interrupt routine is executing.
7252  */
7253 static void igb_netpoll(struct net_device *netdev)
7254 {
7255         struct igb_adapter *adapter = netdev_priv(netdev);
7256         struct e1000_hw *hw = &adapter->hw;
7257         struct igb_q_vector *q_vector;
7258         int i;
7259
7260         for (i = 0; i < adapter->num_q_vectors; i++) {
7261                 q_vector = adapter->q_vector[i];
7262                 if (adapter->msix_entries)
7263                         wr32(E1000_EIMC, q_vector->eims_value);
7264                 else
7265                         igb_irq_disable(adapter);
7266                 napi_schedule(&q_vector->napi);
7267         }
7268 }
7269 #endif /* CONFIG_NET_POLL_CONTROLLER */
7270
7271 /**
7272  *  igb_io_error_detected - called when PCI error is detected
7273  *  @pdev: Pointer to PCI device
7274  *  @state: The current pci connection state
7275  *
7276  *  This function is called after a PCI bus error affecting
7277  *  this device has been detected.
7278  **/
7279 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7280                                               pci_channel_state_t state)
7281 {
7282         struct net_device *netdev = pci_get_drvdata(pdev);
7283         struct igb_adapter *adapter = netdev_priv(netdev);
7284
7285         netif_device_detach(netdev);
7286
7287         if (state == pci_channel_io_perm_failure)
7288                 return PCI_ERS_RESULT_DISCONNECT;
7289
7290         if (netif_running(netdev))
7291                 igb_down(adapter);
7292         pci_disable_device(pdev);
7293
7294         /* Request a slot slot reset. */
7295         return PCI_ERS_RESULT_NEED_RESET;
7296 }
7297
7298 /**
7299  *  igb_io_slot_reset - called after the pci bus has been reset.
7300  *  @pdev: Pointer to PCI device
7301  *
7302  *  Restart the card from scratch, as if from a cold-boot. Implementation
7303  *  resembles the first-half of the igb_resume routine.
7304  **/
7305 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7306 {
7307         struct net_device *netdev = pci_get_drvdata(pdev);
7308         struct igb_adapter *adapter = netdev_priv(netdev);
7309         struct e1000_hw *hw = &adapter->hw;
7310         pci_ers_result_t result;
7311         int err;
7312
7313         if (pci_enable_device_mem(pdev)) {
7314                 dev_err(&pdev->dev,
7315                         "Cannot re-enable PCI device after reset.\n");
7316                 result = PCI_ERS_RESULT_DISCONNECT;
7317         } else {
7318                 pci_set_master(pdev);
7319                 pci_restore_state(pdev);
7320                 pci_save_state(pdev);
7321
7322                 pci_enable_wake(pdev, PCI_D3hot, 0);
7323                 pci_enable_wake(pdev, PCI_D3cold, 0);
7324
7325                 igb_reset(adapter);
7326                 wr32(E1000_WUS, ~0);
7327                 result = PCI_ERS_RESULT_RECOVERED;
7328         }
7329
7330         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7331         if (err) {
7332                 dev_err(&pdev->dev,
7333                         "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7334                         err);
7335                 /* non-fatal, continue */
7336         }
7337
7338         return result;
7339 }
7340
7341 /**
7342  *  igb_io_resume - called when traffic can start flowing again.
7343  *  @pdev: Pointer to PCI device
7344  *
7345  *  This callback is called when the error recovery driver tells us that
7346  *  its OK to resume normal operation. Implementation resembles the
7347  *  second-half of the igb_resume routine.
7348  */
7349 static void igb_io_resume(struct pci_dev *pdev)
7350 {
7351         struct net_device *netdev = pci_get_drvdata(pdev);
7352         struct igb_adapter *adapter = netdev_priv(netdev);
7353
7354         if (netif_running(netdev)) {
7355                 if (igb_up(adapter)) {
7356                         dev_err(&pdev->dev, "igb_up failed after reset\n");
7357                         return;
7358                 }
7359         }
7360
7361         netif_device_attach(netdev);
7362
7363         /* let the f/w know that the h/w is now under the control of the
7364          * driver.
7365          */
7366         igb_get_hw_control(adapter);
7367 }
7368
7369 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7370                              u8 qsel)
7371 {
7372         u32 rar_low, rar_high;
7373         struct e1000_hw *hw = &adapter->hw;
7374
7375         /* HW expects these in little endian so we reverse the byte order
7376          * from network order (big endian) to little endian
7377          */
7378         rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7379                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7380         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7381
7382         /* Indicate to hardware the Address is Valid. */
7383         rar_high |= E1000_RAH_AV;
7384
7385         if (hw->mac.type == e1000_82575)
7386                 rar_high |= E1000_RAH_POOL_1 * qsel;
7387         else
7388                 rar_high |= E1000_RAH_POOL_1 << qsel;
7389
7390         wr32(E1000_RAL(index), rar_low);
7391         wrfl();
7392         wr32(E1000_RAH(index), rar_high);
7393         wrfl();
7394 }
7395
7396 static int igb_set_vf_mac(struct igb_adapter *adapter,
7397                           int vf, unsigned char *mac_addr)
7398 {
7399         struct e1000_hw *hw = &adapter->hw;
7400         /* VF MAC addresses start at end of receive addresses and moves
7401          * towards the first, as a result a collision should not be possible
7402          */
7403         int rar_entry = hw->mac.rar_entry_count - (vf + 1);
7404
7405         memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
7406
7407         igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
7408
7409         return 0;
7410 }
7411
7412 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7413 {
7414         struct igb_adapter *adapter = netdev_priv(netdev);
7415         if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7416                 return -EINVAL;
7417         adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7418         dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7419         dev_info(&adapter->pdev->dev,
7420                  "Reload the VF driver to make this change effective.");
7421         if (test_bit(__IGB_DOWN, &adapter->state)) {
7422                 dev_warn(&adapter->pdev->dev,
7423                          "The VF MAC address has been set, but the PF device is not up.\n");
7424                 dev_warn(&adapter->pdev->dev,
7425                          "Bring the PF device up before attempting to use the VF device.\n");
7426         }
7427         return igb_set_vf_mac(adapter, vf, mac);
7428 }
7429
7430 static int igb_link_mbps(int internal_link_speed)
7431 {
7432         switch (internal_link_speed) {
7433         case SPEED_100:
7434                 return 100;
7435         case SPEED_1000:
7436                 return 1000;
7437         default:
7438                 return 0;
7439         }
7440 }
7441
7442 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7443                                   int link_speed)
7444 {
7445         int rf_dec, rf_int;
7446         u32 bcnrc_val;
7447
7448         if (tx_rate != 0) {
7449                 /* Calculate the rate factor values to set */
7450                 rf_int = link_speed / tx_rate;
7451                 rf_dec = (link_speed - (rf_int * tx_rate));
7452                 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7453                          tx_rate;
7454
7455                 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7456                 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7457                               E1000_RTTBCNRC_RF_INT_MASK);
7458                 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7459         } else {
7460                 bcnrc_val = 0;
7461         }
7462
7463         wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
7464         /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7465          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7466          */
7467         wr32(E1000_RTTBCNRM, 0x14);
7468         wr32(E1000_RTTBCNRC, bcnrc_val);
7469 }
7470
7471 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7472 {
7473         int actual_link_speed, i;
7474         bool reset_rate = false;
7475
7476         /* VF TX rate limit was not set or not supported */
7477         if ((adapter->vf_rate_link_speed == 0) ||
7478             (adapter->hw.mac.type != e1000_82576))
7479                 return;
7480
7481         actual_link_speed = igb_link_mbps(adapter->link_speed);
7482         if (actual_link_speed != adapter->vf_rate_link_speed) {
7483                 reset_rate = true;
7484                 adapter->vf_rate_link_speed = 0;
7485                 dev_info(&adapter->pdev->dev,
7486                          "Link speed has been changed. VF Transmit rate is disabled\n");
7487         }
7488
7489         for (i = 0; i < adapter->vfs_allocated_count; i++) {
7490                 if (reset_rate)
7491                         adapter->vf_data[i].tx_rate = 0;
7492
7493                 igb_set_vf_rate_limit(&adapter->hw, i,
7494                                       adapter->vf_data[i].tx_rate,
7495                                       actual_link_speed);
7496         }
7497 }
7498
7499 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7500 {
7501         struct igb_adapter *adapter = netdev_priv(netdev);
7502         struct e1000_hw *hw = &adapter->hw;
7503         int actual_link_speed;
7504
7505         if (hw->mac.type != e1000_82576)
7506                 return -EOPNOTSUPP;
7507
7508         actual_link_speed = igb_link_mbps(adapter->link_speed);
7509         if ((vf >= adapter->vfs_allocated_count) ||
7510             (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7511             (tx_rate < 0) || (tx_rate > actual_link_speed))
7512                 return -EINVAL;
7513
7514         adapter->vf_rate_link_speed = actual_link_speed;
7515         adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7516         igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7517
7518         return 0;
7519 }
7520
7521 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7522                                    bool setting)
7523 {
7524         struct igb_adapter *adapter = netdev_priv(netdev);
7525         struct e1000_hw *hw = &adapter->hw;
7526         u32 reg_val, reg_offset;
7527
7528         if (!adapter->vfs_allocated_count)
7529                 return -EOPNOTSUPP;
7530
7531         if (vf >= adapter->vfs_allocated_count)
7532                 return -EINVAL;
7533
7534         reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7535         reg_val = rd32(reg_offset);
7536         if (setting)
7537                 reg_val |= ((1 << vf) |
7538                             (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7539         else
7540                 reg_val &= ~((1 << vf) |
7541                              (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7542         wr32(reg_offset, reg_val);
7543
7544         adapter->vf_data[vf].spoofchk_enabled = setting;
7545         return E1000_SUCCESS;
7546 }
7547
7548 static int igb_ndo_get_vf_config(struct net_device *netdev,
7549                                  int vf, struct ifla_vf_info *ivi)
7550 {
7551         struct igb_adapter *adapter = netdev_priv(netdev);
7552         if (vf >= adapter->vfs_allocated_count)
7553                 return -EINVAL;
7554         ivi->vf = vf;
7555         memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
7556         ivi->tx_rate = adapter->vf_data[vf].tx_rate;
7557         ivi->vlan = adapter->vf_data[vf].pf_vlan;
7558         ivi->qos = adapter->vf_data[vf].pf_qos;
7559         ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
7560         return 0;
7561 }
7562
7563 static void igb_vmm_control(struct igb_adapter *adapter)
7564 {
7565         struct e1000_hw *hw = &adapter->hw;
7566         u32 reg;
7567
7568         switch (hw->mac.type) {
7569         case e1000_82575:
7570         case e1000_i210:
7571         case e1000_i211:
7572         case e1000_i354:
7573         default:
7574                 /* replication is not supported for 82575 */
7575                 return;
7576         case e1000_82576:
7577                 /* notify HW that the MAC is adding vlan tags */
7578                 reg = rd32(E1000_DTXCTL);
7579                 reg |= E1000_DTXCTL_VLAN_ADDED;
7580                 wr32(E1000_DTXCTL, reg);
7581         case e1000_82580:
7582                 /* enable replication vlan tag stripping */
7583                 reg = rd32(E1000_RPLOLR);
7584                 reg |= E1000_RPLOLR_STRVLAN;
7585                 wr32(E1000_RPLOLR, reg);
7586         case e1000_i350:
7587                 /* none of the above registers are supported by i350 */
7588                 break;
7589         }
7590
7591         if (adapter->vfs_allocated_count) {
7592                 igb_vmdq_set_loopback_pf(hw, true);
7593                 igb_vmdq_set_replication_pf(hw, true);
7594                 igb_vmdq_set_anti_spoofing_pf(hw, true,
7595                                               adapter->vfs_allocated_count);
7596         } else {
7597                 igb_vmdq_set_loopback_pf(hw, false);
7598                 igb_vmdq_set_replication_pf(hw, false);
7599         }
7600 }
7601
7602 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7603 {
7604         struct e1000_hw *hw = &adapter->hw;
7605         u32 dmac_thr;
7606         u16 hwm;
7607
7608         if (hw->mac.type > e1000_82580) {
7609                 if (adapter->flags & IGB_FLAG_DMAC) {
7610                         u32 reg;
7611
7612                         /* force threshold to 0. */
7613                         wr32(E1000_DMCTXTH, 0);
7614
7615                         /* DMA Coalescing high water mark needs to be greater
7616                          * than the Rx threshold. Set hwm to PBA - max frame
7617                          * size in 16B units, capping it at PBA - 6KB.
7618                          */
7619                         hwm = 64 * pba - adapter->max_frame_size / 16;
7620                         if (hwm < 64 * (pba - 6))
7621                                 hwm = 64 * (pba - 6);
7622                         reg = rd32(E1000_FCRTC);
7623                         reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7624                         reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7625                                 & E1000_FCRTC_RTH_COAL_MASK);
7626                         wr32(E1000_FCRTC, reg);
7627
7628                         /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
7629                          * frame size, capping it at PBA - 10KB.
7630                          */
7631                         dmac_thr = pba - adapter->max_frame_size / 512;
7632                         if (dmac_thr < pba - 10)
7633                                 dmac_thr = pba - 10;
7634                         reg = rd32(E1000_DMACR);
7635                         reg &= ~E1000_DMACR_DMACTHR_MASK;
7636                         reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7637                                 & E1000_DMACR_DMACTHR_MASK);
7638
7639                         /* transition to L0x or L1 if available..*/
7640                         reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7641
7642                         /* watchdog timer= +-1000 usec in 32usec intervals */
7643                         reg |= (1000 >> 5);
7644
7645                         /* Disable BMC-to-OS Watchdog Enable */
7646                         if (hw->mac.type != e1000_i354)
7647                                 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7648
7649                         wr32(E1000_DMACR, reg);
7650
7651                         /* no lower threshold to disable
7652                          * coalescing(smart fifb)-UTRESH=0
7653                          */
7654                         wr32(E1000_DMCRTRH, 0);
7655
7656                         reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7657
7658                         wr32(E1000_DMCTLX, reg);
7659
7660                         /* free space in tx packet buffer to wake from
7661                          * DMA coal
7662                          */
7663                         wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7664                              (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7665
7666                         /* make low power state decision controlled
7667                          * by DMA coal
7668                          */
7669                         reg = rd32(E1000_PCIEMISC);
7670                         reg &= ~E1000_PCIEMISC_LX_DECISION;
7671                         wr32(E1000_PCIEMISC, reg);
7672                 } /* endif adapter->dmac is not disabled */
7673         } else if (hw->mac.type == e1000_82580) {
7674                 u32 reg = rd32(E1000_PCIEMISC);
7675                 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7676                 wr32(E1000_DMACR, 0);
7677         }
7678 }
7679
7680 /**
7681  *  igb_read_i2c_byte - Reads 8 bit word over I2C
7682  *  @hw: pointer to hardware structure
7683  *  @byte_offset: byte offset to read
7684  *  @dev_addr: device address
7685  *  @data: value read
7686  *
7687  *  Performs byte read operation over I2C interface at
7688  *  a specified device address.
7689  **/
7690 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
7691                       u8 dev_addr, u8 *data)
7692 {
7693         struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
7694         struct i2c_client *this_client = adapter->i2c_client;
7695         s32 status;
7696         u16 swfw_mask = 0;
7697
7698         if (!this_client)
7699                 return E1000_ERR_I2C;
7700
7701         swfw_mask = E1000_SWFW_PHY0_SM;
7702
7703         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
7704             != E1000_SUCCESS)
7705                 return E1000_ERR_SWFW_SYNC;
7706
7707         status = i2c_smbus_read_byte_data(this_client, byte_offset);
7708         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7709
7710         if (status < 0)
7711                 return E1000_ERR_I2C;
7712         else {
7713                 *data = status;
7714                 return E1000_SUCCESS;
7715         }
7716 }
7717
7718 /**
7719  *  igb_write_i2c_byte - Writes 8 bit word over I2C
7720  *  @hw: pointer to hardware structure
7721  *  @byte_offset: byte offset to write
7722  *  @dev_addr: device address
7723  *  @data: value to write
7724  *
7725  *  Performs byte write operation over I2C interface at
7726  *  a specified device address.
7727  **/
7728 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
7729                        u8 dev_addr, u8 data)
7730 {
7731         struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
7732         struct i2c_client *this_client = adapter->i2c_client;
7733         s32 status;
7734         u16 swfw_mask = E1000_SWFW_PHY0_SM;
7735
7736         if (!this_client)
7737                 return E1000_ERR_I2C;
7738
7739         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)
7740                 return E1000_ERR_SWFW_SYNC;
7741         status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
7742         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7743
7744         if (status)
7745                 return E1000_ERR_I2C;
7746         else
7747                 return E1000_SUCCESS;
7748
7749 }
7750 /* igb_main.c */