drivers/net/ethernet/intel/i40evf/i40e_txrx.c

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
   4  * Copyright(c) 2013 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * The full GNU General Public License is included in this distribution in
  16  * the file called "COPYING".
  17  *
  18  * Contact Information:
  19  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  20  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  21  *
  22  ******************************************************************************/
  23
  24 #include <linux/prefetch.h>
  25
  26 #include "i40evf.h"
  27
  28 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
  29                                 u32 td_tag)
  30 {
  31         return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
  32                            ((u64)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
  33                            ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
  34                            ((u64)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
  35                            ((u64)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
  36 }
  37
  38 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  39
  40 /**
  41  * i40e_unmap_and_free_tx_resource - Release a Tx buffer
  42  * @ring:      the ring that owns the buffer
  43  * @tx_buffer: the buffer to free
  44  **/
  45 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
  46                                             struct i40e_tx_buffer *tx_buffer)
  47 {
  48         if (tx_buffer->skb) {
  49                 dev_kfree_skb_any(tx_buffer->skb);
  50                 if (dma_unmap_len(tx_buffer, len))
  51                         dma_unmap_single(ring->dev,
  52                                          dma_unmap_addr(tx_buffer, dma),
  53                                          dma_unmap_len(tx_buffer, len),
  54                                          DMA_TO_DEVICE);
  55         } else if (dma_unmap_len(tx_buffer, len)) {
  56                 dma_unmap_page(ring->dev,
  57                                dma_unmap_addr(tx_buffer, dma),
  58                                dma_unmap_len(tx_buffer, len),
  59                                DMA_TO_DEVICE);
  60         }
  61         tx_buffer->next_to_watch = NULL;
  62         tx_buffer->skb = NULL;
  63         dma_unmap_len_set(tx_buffer, len, 0);
  64         /* tx_buffer must be completely set up in the transmit path */
  65 }
  66
  67 /**
  68  * i40evf_clean_tx_ring - Free any empty Tx buffers
  69  * @tx_ring: ring to be cleaned
  70  **/
  71 void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
  72 {
  73         unsigned long bi_size;
  74         u16 i;
  75
  76         /* ring already cleared, nothing to do */
  77         if (!tx_ring->tx_bi)
  78                 return;
  79
  80         /* Free all the Tx ring sk_buffs */
  81         for (i = 0; i < tx_ring->count; i++)
  82                 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
  83
  84         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
  85         memset(tx_ring->tx_bi, 0, bi_size);
  86
  87         /* Zero out the descriptor ring */
  88         memset(tx_ring->desc, 0, tx_ring->size);
  89
  90         tx_ring->next_to_use = 0;
  91         tx_ring->next_to_clean = 0;
  92
  93         if (!tx_ring->netdev)
  94                 return;
  95
  96         /* cleanup Tx queue statistics */
  97         netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
  98                                                   tx_ring->queue_index));
  99 }
 100
 101 /**
 102  * i40evf_free_tx_resources - Free Tx resources per queue
 103  * @tx_ring: Tx descriptor ring for a specific queue
 104  *
 105  * Free all transmit software resources
 106  **/
 107 void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
 108 {
 109         i40evf_clean_tx_ring(tx_ring);
 110         kfree(tx_ring->tx_bi);
 111         tx_ring->tx_bi = NULL;
 112
 113         if (tx_ring->desc) {
 114                 dma_free_coherent(tx_ring->dev, tx_ring->size,
 115                                   tx_ring->desc, tx_ring->dma);
 116                 tx_ring->desc = NULL;
 117         }
 118 }
 119
 120 /**
 121  * i40e_get_tx_pending - how many tx descriptors not processed
 122  * @tx_ring: the ring of descriptors
 123  *
 124  * Since there is no access to the ring head register
 125  * in XL710, we need to use our local copies
 126  **/
 127 static u32 i40e_get_tx_pending(struct i40e_ring *ring)
 128 {
 129         u32 ntu = ((ring->next_to_clean <= ring->next_to_use)
 130                         ? ring->next_to_use
 131                         : ring->next_to_use + ring->count);
 132         return ntu - ring->next_to_clean;
 133 }
 134
 135 /**
 136  * i40e_check_tx_hang - Is there a hang in the Tx queue
 137  * @tx_ring: the ring of descriptors
 138  **/
 139 static bool i40e_check_tx_hang(struct i40e_ring *tx_ring)
 140 {
 141         u32 tx_pending = i40e_get_tx_pending(tx_ring);
 142         bool ret = false;
 143
 144         clear_check_for_tx_hang(tx_ring);
 145
 146         /* Check for a hung queue, but be thorough. This verifies
 147          * that a transmit has been completed since the previous
 148          * check AND there is at least one packet pending. The
 149          * ARMED bit is set to indicate a potential hang. The
 150          * bit is cleared if a pause frame is received to remove
 151          * false hang detection due to PFC or 802.3x frames. By
 152          * requiring this to fail twice we avoid races with
 153          * PFC clearing the ARMED bit and conditions where we
 154          * run the check_tx_hang logic with a transmit completion
 155          * pending but without time to complete it yet.
 156          */
 157         if ((tx_ring->tx_stats.tx_done_old == tx_ring->stats.packets) &&
 158             tx_pending) {
 159                 /* make sure it is true for two checks in a row */
 160                 ret = test_and_set_bit(__I40E_HANG_CHECK_ARMED,
 161                                        &tx_ring->state);
 162         } else {
 163                 /* update completed stats and disarm the hang check */
 164                 tx_ring->tx_stats.tx_done_old = tx_ring->stats.packets;
 165                 clear_bit(__I40E_HANG_CHECK_ARMED, &tx_ring->state);
 166         }
 167
 168         return ret;
 169 }
 170
 171 /**
 172  * i40e_clean_tx_irq - Reclaim resources after transmit completes
 173  * @tx_ring:  tx ring to clean
 174  * @budget:   how many cleans we're allowed
 175  *
 176  * Returns true if there's any budget left (e.g. the clean is finished)
 177  **/
 178 static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
 179 {
 180         u16 i = tx_ring->next_to_clean;
 181         struct i40e_tx_buffer *tx_buf;
 182         struct i40e_tx_desc *tx_desc;
 183         unsigned int total_packets = 0;
 184         unsigned int total_bytes = 0;
 185
 186         tx_buf = &tx_ring->tx_bi[i];
 187         tx_desc = I40E_TX_DESC(tx_ring, i);
 188         i -= tx_ring->count;
 189
 190         do {
 191                 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
 192
 193                 /* if next_to_watch is not set then there is no work pending */
 194                 if (!eop_desc)
 195                         break;
 196
 197                 /* prevent any other reads prior to eop_desc */
 198                 read_barrier_depends();
 199
 200                 /* if the descriptor isn't done, no work yet to do */
 201                 if (!(eop_desc->cmd_type_offset_bsz &
 202                       cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
 203                         break;
 204
 205                 /* clear next_to_watch to prevent false hangs */
 206                 tx_buf->next_to_watch = NULL;
 207
 208                 /* update the statistics for this packet */
 209                 total_bytes += tx_buf->bytecount;
 210                 total_packets += tx_buf->gso_segs;
 211
 212                 /* free the skb */
 213                 dev_kfree_skb_any(tx_buf->skb);
 214
 215                 /* unmap skb header data */
 216                 dma_unmap_single(tx_ring->dev,
 217                                  dma_unmap_addr(tx_buf, dma),
 218                                  dma_unmap_len(tx_buf, len),
 219                                  DMA_TO_DEVICE);
 220
 221                 /* clear tx_buffer data */
 222                 tx_buf->skb = NULL;
 223                 dma_unmap_len_set(tx_buf, len, 0);
 224
 225                 /* unmap remaining buffers */
 226                 while (tx_desc != eop_desc) {
 227
 228                         tx_buf++;
 229                         tx_desc++;
 230                         i++;
 231                         if (unlikely(!i)) {
 232                                 i -= tx_ring->count;
 233                                 tx_buf = tx_ring->tx_bi;
 234                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
 235                         }
 236
 237                         /* unmap any remaining paged data */
 238                         if (dma_unmap_len(tx_buf, len)) {
 239                                 dma_unmap_page(tx_ring->dev,
 240                                                dma_unmap_addr(tx_buf, dma),
 241                                                dma_unmap_len(tx_buf, len),
 242                                                DMA_TO_DEVICE);
 243                                 dma_unmap_len_set(tx_buf, len, 0);
 244                         }
 245                 }
 246
 247                 /* move us one more past the eop_desc for start of next pkt */
 248                 tx_buf++;
 249                 tx_desc++;
 250                 i++;
 251                 if (unlikely(!i)) {
 252                         i -= tx_ring->count;
 253                         tx_buf = tx_ring->tx_bi;
 254                         tx_desc = I40E_TX_DESC(tx_ring, 0);
 255                 }
 256
 257                 /* update budget accounting */
 258                 budget--;
 259         } while (likely(budget));
 260
 261         i += tx_ring->count;
 262         tx_ring->next_to_clean = i;
 263         u64_stats_update_begin(&tx_ring->syncp);
 264         tx_ring->stats.bytes += total_bytes;
 265         tx_ring->stats.packets += total_packets;
 266         u64_stats_update_end(&tx_ring->syncp);
 267         tx_ring->q_vector->tx.total_bytes += total_bytes;
 268         tx_ring->q_vector->tx.total_packets += total_packets;
 269
 270         if (check_for_tx_hang(tx_ring) && i40e_check_tx_hang(tx_ring)) {
 271                 /* schedule immediate reset if we believe we hung */
 272                 dev_info(tx_ring->dev, "Detected Tx Unit Hang\n"
 273                          "  VSI                  <%d>\n"
 274                          "  Tx Queue             <%d>\n"
 275                          "  next_to_use          <%x>\n"
 276                          "  next_to_clean        <%x>\n",
 277                          tx_ring->vsi->seid,
 278                          tx_ring->queue_index,
 279                          tx_ring->next_to_use, i);
 280                 dev_info(tx_ring->dev, "tx_bi[next_to_clean]\n"
 281                          "  time_stamp           <%lx>\n"
 282                          "  jiffies              <%lx>\n",
 283                          tx_ring->tx_bi[i].time_stamp, jiffies);
 284
 285                 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
 286
 287                 dev_info(tx_ring->dev,
 288                          "tx hang detected on queue %d, resetting adapter\n",
 289                          tx_ring->queue_index);
 290
 291                 tx_ring->netdev->netdev_ops->ndo_tx_timeout(tx_ring->netdev);
 292
 293                 /* the adapter is about to reset, no point in enabling stuff */
 294                 return true;
 295         }
 296
 297         netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
 298                                                       tx_ring->queue_index),
 299                                   total_packets, total_bytes);
 300
 301 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 302         if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
 303                      (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 304                 /* Make sure that anybody stopping the queue after this
 305                  * sees the new next_to_clean.
 306                  */
 307                 smp_mb();
 308                 if (__netif_subqueue_stopped(tx_ring->netdev,
 309                                              tx_ring->queue_index) &&
 310                    !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
 311                         netif_wake_subqueue(tx_ring->netdev,
 312                                             tx_ring->queue_index);
 313                         ++tx_ring->tx_stats.restart_queue;
 314                 }
 315         }
 316
 317         return budget > 0;
 318 }
 319
 320 /**
 321  * i40e_set_new_dynamic_itr - Find new ITR level
 322  * @rc: structure containing ring performance data
 323  *
 324  * Stores a new ITR value based on packets and byte counts during
 325  * the last interrupt.  The advantage of per interrupt computation
 326  * is faster updates and more accurate ITR for the current traffic
 327  * pattern.  Constants in this function were computed based on
 328  * theoretical maximum wire speed and thresholds were set based on
 329  * testing data as well as attempting to minimize response time
 330  * while increasing bulk throughput.
 331  **/
 332 static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
 333 {
 334         enum i40e_latency_range new_latency_range = rc->latency_range;
 335         u32 new_itr = rc->itr;
 336         int bytes_per_int;
 337
 338         if (rc->total_packets == 0 || !rc->itr)
 339                 return;
 340
 341         /* simple throttlerate management
 342          *   0-10MB/s   lowest (100000 ints/s)
 343          *  10-20MB/s   low    (20000 ints/s)
 344          *  20-1249MB/s bulk   (8000 ints/s)
 345          */
 346         bytes_per_int = rc->total_bytes / rc->itr;
 347         switch (rc->itr) {
 348         case I40E_LOWEST_LATENCY:
 349                 if (bytes_per_int > 10)
 350                         new_latency_range = I40E_LOW_LATENCY;
 351                 break;
 352         case I40E_LOW_LATENCY:
 353                 if (bytes_per_int > 20)
 354                         new_latency_range = I40E_BULK_LATENCY;
 355                 else if (bytes_per_int <= 10)
 356                         new_latency_range = I40E_LOWEST_LATENCY;
 357                 break;
 358         case I40E_BULK_LATENCY:
 359                 if (bytes_per_int <= 20)
 360                         rc->latency_range = I40E_LOW_LATENCY;
 361                 break;
 362         }
 363
 364         switch (new_latency_range) {
 365         case I40E_LOWEST_LATENCY:
 366                 new_itr = I40E_ITR_100K;
 367                 break;
 368         case I40E_LOW_LATENCY:
 369                 new_itr = I40E_ITR_20K;
 370                 break;
 371         case I40E_BULK_LATENCY:
 372                 new_itr = I40E_ITR_8K;
 373                 break;
 374         default:
 375                 break;
 376         }
 377
 378         if (new_itr != rc->itr) {
 379                 /* do an exponential smoothing */
 380                 new_itr = (10 * new_itr * rc->itr) /
 381                           ((9 * new_itr) + rc->itr);
 382                 rc->itr = new_itr & I40E_MAX_ITR;
 383         }
 384
 385         rc->total_bytes = 0;
 386         rc->total_packets = 0;
 387 }
 388
 389 /**
 390  * i40e_update_dynamic_itr - Adjust ITR based on bytes per int
 391  * @q_vector: the vector to adjust
 392  **/
 393 static void i40e_update_dynamic_itr(struct i40e_q_vector *q_vector)
 394 {
 395         u16 vector = q_vector->vsi->base_vector + q_vector->v_idx;
 396         struct i40e_hw *hw = &q_vector->vsi->back->hw;
 397         u32 reg_addr;
 398         u16 old_itr;
 399
 400         reg_addr = I40E_VFINT_ITRN1(I40E_RX_ITR, vector - 1);
 401         old_itr = q_vector->rx.itr;
 402         i40e_set_new_dynamic_itr(&q_vector->rx);
 403         if (old_itr != q_vector->rx.itr)
 404                 wr32(hw, reg_addr, q_vector->rx.itr);
 405
 406         reg_addr = I40E_VFINT_ITRN1(I40E_TX_ITR, vector - 1);
 407         old_itr = q_vector->tx.itr;
 408         i40e_set_new_dynamic_itr(&q_vector->tx);
 409         if (old_itr != q_vector->tx.itr)
 410                 wr32(hw, reg_addr, q_vector->tx.itr);
 411 }
 412
 413 /**
 414  * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
 415  * @tx_ring: the tx ring to set up
 416  *
 417  * Return 0 on success, negative on error
 418  **/
 419 int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
 420 {
 421         struct device *dev = tx_ring->dev;
 422         int bi_size;
 423
 424         if (!dev)
 425                 return -ENOMEM;
 426
 427         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
 428         tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
 429         if (!tx_ring->tx_bi)
 430                 goto err;
 431
 432         /* round up to nearest 4K */
 433         tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
 434         tx_ring->size = ALIGN(tx_ring->size, 4096);
 435         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
 436                                            &tx_ring->dma, GFP_KERNEL);
 437         if (!tx_ring->desc) {
 438                 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
 439                          tx_ring->size);
 440                 goto err;
 441         }
 442
 443         tx_ring->next_to_use = 0;
 444         tx_ring->next_to_clean = 0;
 445         return 0;
 446
 447 err:
 448         kfree(tx_ring->tx_bi);
 449         tx_ring->tx_bi = NULL;
 450         return -ENOMEM;
 451 }
 452
 453 /**
 454  * i40evf_clean_rx_ring - Free Rx buffers
 455  * @rx_ring: ring to be cleaned
 456  **/
 457 void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
 458 {
 459         struct device *dev = rx_ring->dev;
 460         struct i40e_rx_buffer *rx_bi;
 461         unsigned long bi_size;
 462         u16 i;
 463
 464         /* ring already cleared, nothing to do */
 465         if (!rx_ring->rx_bi)
 466                 return;
 467
 468         /* Free all the Rx ring sk_buffs */
 469         for (i = 0; i < rx_ring->count; i++) {
 470                 rx_bi = &rx_ring->rx_bi[i];
 471                 if (rx_bi->dma) {
 472                         dma_unmap_single(dev,
 473                                          rx_bi->dma,
 474                                          rx_ring->rx_buf_len,
 475                                          DMA_FROM_DEVICE);
 476                         rx_bi->dma = 0;
 477                 }
 478                 if (rx_bi->skb) {
 479                         dev_kfree_skb(rx_bi->skb);
 480                         rx_bi->skb = NULL;
 481                 }
 482                 if (rx_bi->page) {
 483                         if (rx_bi->page_dma) {
 484                                 dma_unmap_page(dev,
 485                                                rx_bi->page_dma,
 486                                                PAGE_SIZE / 2,
 487                                                DMA_FROM_DEVICE);
 488                                 rx_bi->page_dma = 0;
 489                         }
 490                         __free_page(rx_bi->page);
 491                         rx_bi->page = NULL;
 492                         rx_bi->page_offset = 0;
 493                 }
 494         }
 495
 496         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 497         memset(rx_ring->rx_bi, 0, bi_size);
 498
 499         /* Zero out the descriptor ring */
 500         memset(rx_ring->desc, 0, rx_ring->size);
 501
 502         rx_ring->next_to_clean = 0;
 503         rx_ring->next_to_use = 0;
 504 }
 505
 506 /**
 507  * i40evf_free_rx_resources - Free Rx resources
 508  * @rx_ring: ring to clean the resources from
 509  *
 510  * Free all receive software resources
 511  **/
 512 void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
 513 {
 514         i40evf_clean_rx_ring(rx_ring);
 515         kfree(rx_ring->rx_bi);
 516         rx_ring->rx_bi = NULL;
 517
 518         if (rx_ring->desc) {
 519                 dma_free_coherent(rx_ring->dev, rx_ring->size,
 520                                   rx_ring->desc, rx_ring->dma);
 521                 rx_ring->desc = NULL;
 522         }
 523 }
 524
 525 /**
 526  * i40evf_setup_rx_descriptors - Allocate Rx descriptors
 527  * @rx_ring: Rx descriptor ring (for a specific queue) to setup
 528  *
 529  * Returns 0 on success, negative on failure
 530  **/
 531 int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
 532 {
 533         struct device *dev = rx_ring->dev;
 534         int bi_size;
 535
 536         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 537         rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
 538         if (!rx_ring->rx_bi)
 539                 goto err;
 540
 541         /* Round up to nearest 4K */
 542         rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
 543                 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
 544                 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
 545         rx_ring->size = ALIGN(rx_ring->size, 4096);
 546         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
 547                                            &rx_ring->dma, GFP_KERNEL);
 548
 549         if (!rx_ring->desc) {
 550                 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
 551                          rx_ring->size);
 552                 goto err;
 553         }
 554
 555         rx_ring->next_to_clean = 0;
 556         rx_ring->next_to_use = 0;
 557
 558         return 0;
 559 err:
 560         kfree(rx_ring->rx_bi);
 561         rx_ring->rx_bi = NULL;
 562         return -ENOMEM;
 563 }
 564
 565 /**
 566  * i40e_release_rx_desc - Store the new tail and head values
 567  * @rx_ring: ring to bump
 568  * @val: new head index
 569  **/
 570 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
 571 {
 572         rx_ring->next_to_use = val;
 573         /* Force memory writes to complete before letting h/w
 574          * know there are new descriptors to fetch.  (Only
 575          * applicable for weak-ordered memory model archs,
 576          * such as IA-64).
 577          */
 578         wmb();
 579         writel(val, rx_ring->tail);
 580 }
 581
 582 /**
 583  * i40evf_alloc_rx_buffers - Replace used receive buffers; packet split
 584  * @rx_ring: ring to place buffers on
 585  * @cleaned_count: number of buffers to replace
 586  **/
 587 void i40evf_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count)
 588 {
 589         u16 i = rx_ring->next_to_use;
 590         union i40e_rx_desc *rx_desc;
 591         struct i40e_rx_buffer *bi;
 592         struct sk_buff *skb;
 593
 594         /* do nothing if no valid netdev defined */
 595         if (!rx_ring->netdev || !cleaned_count)
 596                 return;
 597
 598         while (cleaned_count--) {
 599                 rx_desc = I40E_RX_DESC(rx_ring, i);
 600                 bi = &rx_ring->rx_bi[i];
 601                 skb = bi->skb;
 602
 603                 if (!skb) {
 604                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
 605                                                         rx_ring->rx_buf_len);
 606                         if (!skb) {
 607                                 rx_ring->rx_stats.alloc_buff_failed++;
 608                                 goto no_buffers;
 609                         }
 610                         /* initialize queue mapping */
 611                         skb_record_rx_queue(skb, rx_ring->queue_index);
 612                         bi->skb = skb;
 613                 }
 614
 615                 if (!bi->dma) {
 616                         bi->dma = dma_map_single(rx_ring->dev,
 617                                                  skb->data,
 618                                                  rx_ring->rx_buf_len,
 619                                                  DMA_FROM_DEVICE);
 620                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
 621                                 rx_ring->rx_stats.alloc_buff_failed++;
 622                                 bi->dma = 0;
 623                                 goto no_buffers;
 624                         }
 625                 }
 626
 627                 if (ring_is_ps_enabled(rx_ring)) {
 628                         if (!bi->page) {
 629                                 bi->page = alloc_page(GFP_ATOMIC);
 630                                 if (!bi->page) {
 631                                         rx_ring->rx_stats.alloc_page_failed++;
 632                                         goto no_buffers;
 633                                 }
 634                         }
 635
 636                         if (!bi->page_dma) {
 637                                 /* use a half page if we're re-using */
 638                                 bi->page_offset ^= PAGE_SIZE / 2;
 639                                 bi->page_dma = dma_map_page(rx_ring->dev,
 640                                                             bi->page,
 641                                                             bi->page_offset,
 642                                                             PAGE_SIZE / 2,
 643                                                             DMA_FROM_DEVICE);
 644                                 if (dma_mapping_error(rx_ring->dev,
 645                                                       bi->page_dma)) {
 646                                         rx_ring->rx_stats.alloc_page_failed++;
 647                                         bi->page_dma = 0;
 648                                         goto no_buffers;
 649                                 }
 650                         }
 651
 652                         /* Refresh the desc even if buffer_addrs didn't change
 653                          * because each write-back erases this info.
 654                          */
 655                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 656                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 657                 } else {
 658                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 659                         rx_desc->read.hdr_addr = 0;
 660                 }
 661                 i++;
 662                 if (i == rx_ring->count)
 663                         i = 0;
 664         }
 665
 666 no_buffers:
 667         if (rx_ring->next_to_use != i)
 668                 i40e_release_rx_desc(rx_ring, i);
 669 }
 670
 671 /**
 672  * i40e_receive_skb - Send a completed packet up the stack
 673  * @rx_ring:  rx ring in play
 674  * @skb: packet to send up
 675  * @vlan_tag: vlan tag for packet
 676  **/
 677 static void i40e_receive_skb(struct i40e_ring *rx_ring,
 678                              struct sk_buff *skb, u16 vlan_tag)
 679 {
 680         struct i40e_q_vector *q_vector = rx_ring->q_vector;
 681         struct i40e_vsi *vsi = rx_ring->vsi;
 682         u64 flags = vsi->back->flags;
 683
 684         if (vlan_tag & VLAN_VID_MASK)
 685                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
 686
 687         if (flags & I40E_FLAG_IN_NETPOLL)
 688                 netif_rx(skb);
 689         else
 690                 napi_gro_receive(&q_vector->napi, skb);
 691 }
 692
 693 /**
 694  * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
 695  * @vsi: the VSI we care about
 696  * @skb: skb currently being received and modified
 697  * @rx_status: status value of last descriptor in packet
 698  * @rx_error: error value of last descriptor in packet
 699  * @rx_ptype: ptype value of last descriptor in packet
 700  **/
 701 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
 702                                     struct sk_buff *skb,
 703                                     u32 rx_status,
 704                                     u32 rx_error,
 705                                     u16 rx_ptype)
 706 {
 707         bool ipv4_tunnel, ipv6_tunnel;
 708         __wsum rx_udp_csum;
 709         __sum16 csum;
 710         struct iphdr *iph;
 711
 712         ipv4_tunnel = (rx_ptype > I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
 713                       (rx_ptype < I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
 714         ipv6_tunnel = (rx_ptype > I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
 715                       (rx_ptype < I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
 716
 717         skb->encapsulation = ipv4_tunnel || ipv6_tunnel;
 718         skb->ip_summed = CHECKSUM_NONE;
 719
 720         /* Rx csum enabled and ip headers found? */
 721         if (!(vsi->netdev->features & NETIF_F_RXCSUM &&
 722               rx_status & (1 << I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
 723                 return;
 724
 725         /* likely incorrect csum if alternate IP extention headers found */
 726         if (rx_status & (1 << I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
 727                 return;
 728
 729         /* IP or L4 or outmost IP checksum error */
 730         if (rx_error & ((1 << I40E_RX_DESC_ERROR_IPE_SHIFT) |
 731                         (1 << I40E_RX_DESC_ERROR_L4E_SHIFT) |
 732                         (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT))) {
 733                 vsi->back->hw_csum_rx_error++;
 734                 return;
 735         }
 736
 737         if (ipv4_tunnel &&
 738             !(rx_status & (1 << I40E_RX_DESC_STATUS_UDP_0_SHIFT))) {
 739                 /* If VXLAN traffic has an outer UDPv4 checksum we need to check
 740                  * it in the driver, hardware does not do it for us.
 741                  * Since L3L4P bit was set we assume a valid IHL value (>=5)
 742                  * so the total length of IPv4 header is IHL*4 bytes
 743                  */
 744                 skb->transport_header = skb->mac_header +
 745                                         sizeof(struct ethhdr) +
 746                                         (ip_hdr(skb)->ihl * 4);
 747
 748                 /* Add 4 bytes for VLAN tagged packets */
 749                 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
 750                                           skb->protocol == htons(ETH_P_8021AD))
 751                                           ? VLAN_HLEN : 0;
 752
 753                 rx_udp_csum = udp_csum(skb);
 754                 iph = ip_hdr(skb);
 755                 csum = csum_tcpudp_magic(
 756                                 iph->saddr, iph->daddr,
 757                                 (skb->len - skb_transport_offset(skb)),
 758                                 IPPROTO_UDP, rx_udp_csum);
 759
 760                 if (udp_hdr(skb)->check != csum) {
 761                         vsi->back->hw_csum_rx_error++;
 762                         return;
 763                 }
 764         }
 765
 766         skb->ip_summed = CHECKSUM_UNNECESSARY;
 767 }
 768
 769 /**
 770  * i40e_rx_hash - returns the hash value from the Rx descriptor
 771  * @ring: descriptor ring
 772  * @rx_desc: specific descriptor
 773  **/
 774 static inline u32 i40e_rx_hash(struct i40e_ring *ring,
 775                                union i40e_rx_desc *rx_desc)
 776 {
 777         const __le64 rss_mask =
 778                 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
 779                             I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
 780
 781         if ((ring->netdev->features & NETIF_F_RXHASH) &&
 782             (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask)
 783                 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
 784         else
 785                 return 0;
 786 }
 787
 788 /**
 789  * i40e_clean_rx_irq - Reclaim resources after receive completes
 790  * @rx_ring:  rx ring to clean
 791  * @budget:   how many cleans we're allowed
 792  *
 793  * Returns true if there's any budget left (e.g. the clean is finished)
 794  **/
 795 static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)
 796 {
 797         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 798         u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
 799         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
 800         const int current_node = numa_node_id();
 801         struct i40e_vsi *vsi = rx_ring->vsi;
 802         u16 i = rx_ring->next_to_clean;
 803         union i40e_rx_desc *rx_desc;
 804         u32 rx_error, rx_status;
 805         u64 qword;
 806         u16 rx_ptype;
 807
 808         rx_desc = I40E_RX_DESC(rx_ring, i);
 809         qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
 810         rx_status = (qword & I40E_RXD_QW1_STATUS_MASK)
 811                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 812
 813         while (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
 814                 union i40e_rx_desc *next_rxd;
 815                 struct i40e_rx_buffer *rx_bi;
 816                 struct sk_buff *skb;
 817                 u16 vlan_tag;
 818                 rx_bi = &rx_ring->rx_bi[i];
 819                 skb = rx_bi->skb;
 820                 prefetch(skb->data);
 821
 822                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 823                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 824                 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
 825                                 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
 826                 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
 827                          I40E_RXD_QW1_LENGTH_SPH_SHIFT;
 828
 829                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
 830                            I40E_RXD_QW1_ERROR_SHIFT;
 831                 rx_hbo = rx_error & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
 832                 rx_error &= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
 833
 834                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
 835                            I40E_RXD_QW1_PTYPE_SHIFT;
 836                 rx_bi->skb = NULL;
 837
 838                 /* This memory barrier is needed to keep us from reading
 839                  * any other fields out of the rx_desc until we know the
 840                  * STATUS_DD bit is set
 841                  */
 842                 rmb();
 843
 844                 /* Get the header and possibly the whole packet
 845                  * If this is an skb from previous receive dma will be 0
 846                  */
 847                 if (rx_bi->dma) {
 848                         u16 len;
 849
 850                         if (rx_hbo)
 851                                 len = I40E_RX_HDR_SIZE;
 852                         else if (rx_sph)
 853                                 len = rx_header_len;
 854                         else if (rx_packet_len)
 855                                 len = rx_packet_len;   /* 1buf/no split found */
 856                         else
 857                                 len = rx_header_len;   /* split always mode */
 858
 859                         skb_put(skb, len);
 860                         dma_unmap_single(rx_ring->dev,
 861                                          rx_bi->dma,
 862                                          rx_ring->rx_buf_len,
 863                                          DMA_FROM_DEVICE);
 864                         rx_bi->dma = 0;
 865                 }
 866
 867                 /* Get the rest of the data if this was a header split */
 868                 if (ring_is_ps_enabled(rx_ring) && rx_packet_len) {
 869
 870                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 871                                            rx_bi->page,
 872                                            rx_bi->page_offset,
 873                                            rx_packet_len);
 874
 875                         skb->len += rx_packet_len;
 876                         skb->data_len += rx_packet_len;
 877                         skb->truesize += rx_packet_len;
 878
 879                         if ((page_count(rx_bi->page) == 1) &&
 880                             (page_to_nid(rx_bi->page) == current_node))
 881                                 get_page(rx_bi->page);
 882                         else
 883                                 rx_bi->page = NULL;
 884
 885                         dma_unmap_page(rx_ring->dev,
 886                                        rx_bi->page_dma,
 887                                        PAGE_SIZE / 2,
 888                                        DMA_FROM_DEVICE);
 889                         rx_bi->page_dma = 0;
 890                 }
 891                 I40E_RX_NEXT_DESC_PREFETCH(rx_ring, i, next_rxd);
 892
 893                 if (unlikely(
 894                     !(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
 895                         struct i40e_rx_buffer *next_buffer;
 896
 897                         next_buffer = &rx_ring->rx_bi[i];
 898
 899                         if (ring_is_ps_enabled(rx_ring)) {
 900                                 rx_bi->skb = next_buffer->skb;
 901                                 rx_bi->dma = next_buffer->dma;
 902                                 next_buffer->skb = skb;
 903                                 next_buffer->dma = 0;
 904                         }
 905                         rx_ring->rx_stats.non_eop_descs++;
 906                         goto next_desc;
 907                 }
 908
 909                 /* ERR_MASK will only have valid bits if EOP set */
 910                 if (unlikely(rx_error & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
 911                         dev_kfree_skb_any(skb);
 912                         goto next_desc;
 913                 }
 914
 915                 skb->rxhash = i40e_rx_hash(rx_ring, rx_desc);
 916                 /* probably a little skewed due to removing CRC */
 917                 total_rx_bytes += skb->len;
 918                 total_rx_packets++;
 919
 920                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
 921
 922                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
 923
 924                 vlan_tag = rx_status & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
 925                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
 926                          : 0;
 927                 i40e_receive_skb(rx_ring, skb, vlan_tag);
 928
 929                 rx_ring->netdev->last_rx = jiffies;
 930                 budget--;
 931 next_desc:
 932                 rx_desc->wb.qword1.status_error_len = 0;
 933                 if (!budget)
 934                         break;
 935
 936                 cleaned_count++;
 937                 /* return some buffers to hardware, one at a time is too slow */
 938                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
 939                         i40evf_alloc_rx_buffers(rx_ring, cleaned_count);
 940                         cleaned_count = 0;
 941                 }
 942
 943                 /* use prefetched values */
 944                 rx_desc = next_rxd;
 945                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
 946                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
 947                             I40E_RXD_QW1_STATUS_SHIFT;
 948         }
 949
 950         rx_ring->next_to_clean = i;
 951         u64_stats_update_begin(&rx_ring->syncp);
 952         rx_ring->stats.packets += total_rx_packets;
 953         rx_ring->stats.bytes += total_rx_bytes;
 954         u64_stats_update_end(&rx_ring->syncp);
 955         rx_ring->q_vector->rx.total_packets += total_rx_packets;
 956         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
 957
 958         if (cleaned_count)
 959                 i40evf_alloc_rx_buffers(rx_ring, cleaned_count);
 960
 961         return budget > 0;
 962 }
 963
 964 /**
 965  * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
 966  * @napi: napi struct with our devices info in it
 967  * @budget: amount of work driver is allowed to do this pass, in packets
 968  *
 969  * This function will clean all queues associated with a q_vector.
 970  *
 971  * Returns the amount of work done
 972  **/
 973 int i40evf_napi_poll(struct napi_struct *napi, int budget)
 974 {
 975         struct i40e_q_vector *q_vector =
 976                                container_of(napi, struct i40e_q_vector, napi);
 977         struct i40e_vsi *vsi = q_vector->vsi;
 978         struct i40e_ring *ring;
 979         bool clean_complete = true;
 980         int budget_per_ring;
 981
 982         if (test_bit(__I40E_DOWN, &vsi->state)) {
 983                 napi_complete(napi);
 984                 return 0;
 985         }
 986
 987         /* Since the actual Tx work is minimal, we can give the Tx a larger
 988          * budget and be more aggressive about cleaning up the Tx descriptors.
 989          */
 990         i40e_for_each_ring(ring, q_vector->tx)
 991                 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
 992
 993         /* We attempt to distribute budget to each Rx queue fairly, but don't
 994          * allow the budget to go below 1 because that would exit polling early.
 995          */
 996         budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
 997
 998         i40e_for_each_ring(ring, q_vector->rx)
 999                 clean_complete &= i40e_clean_rx_irq(ring, budget_per_ring);
1000
1001         /* If work not completed, return budget and polling will return */
1002         if (!clean_complete)
1003                 return budget;
1004
1005         /* Work is done so exit the polling mode and re-enable the interrupt */
1006         napi_complete(napi);
1007         if (ITR_IS_DYNAMIC(vsi->rx_itr_setting) ||
1008             ITR_IS_DYNAMIC(vsi->tx_itr_setting))
1009                 i40e_update_dynamic_itr(q_vector);
1010
1011         if (!test_bit(__I40E_DOWN, &vsi->state))
1012                 i40evf_irq_enable_queues(vsi->back, 1 << q_vector->v_idx);
1013
1014         return 0;
1015 }
1016
1017 /**
1018  * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1019  * @skb:     send buffer
1020  * @tx_ring: ring to send buffer on
1021  * @flags:   the tx flags to be set
1022  *
1023  * Checks the skb and set up correspondingly several generic transmit flags
1024  * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1025  *
1026  * Returns error code indicate the frame should be dropped upon error and the
1027  * otherwise  returns 0 to indicate the flags has been set properly.
1028  **/
1029 static int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
1030                                       struct i40e_ring *tx_ring,
1031                                       u32 *flags)
1032 {
1033         __be16 protocol = skb->protocol;
1034         u32  tx_flags = 0;
1035
1036         /* if we have a HW VLAN tag being added, default to the HW one */
1037         if (vlan_tx_tag_present(skb)) {
1038                 tx_flags |= vlan_tx_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1039                 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1040         /* else if it is a SW VLAN, check the next protocol and store the tag */
1041         } else if (protocol == htons(ETH_P_8021Q)) {
1042                 struct vlan_hdr *vhdr, _vhdr;
1043                 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1044                 if (!vhdr)
1045                         return -EINVAL;
1046
1047                 protocol = vhdr->h_vlan_encapsulated_proto;
1048                 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1049                 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1050         }
1051
1052         *flags = tx_flags;
1053         return 0;
1054 }
1055
1056 /**
1057  * i40e_tso - set up the tso context descriptor
1058  * @tx_ring:  ptr to the ring to send
1059  * @skb:      ptr to the skb we're sending
1060  * @tx_flags: the collected send information
1061  * @protocol: the send protocol
1062  * @hdr_len:  ptr to the size of the packet header
1063  * @cd_tunneling: ptr to context descriptor bits
1064  *
1065  * Returns 0 if no TSO can happen, 1 if tso is going, or error
1066  **/
1067 static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
1068                     u32 tx_flags, __be16 protocol, u8 *hdr_len,
1069                     u64 *cd_type_cmd_tso_mss, u32 *cd_tunneling)
1070 {
1071         u32 cd_cmd, cd_tso_len, cd_mss;
1072         struct tcphdr *tcph;
1073         struct iphdr *iph;
1074         u32 l4len;
1075         int err;
1076         struct ipv6hdr *ipv6h;
1077
1078         if (!skb_is_gso(skb))
1079                 return 0;
1080
1081         if (skb_header_cloned(skb)) {
1082                 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1083                 if (err)
1084                         return err;
1085         }
1086
1087         if (protocol == htons(ETH_P_IP)) {
1088                 iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1089                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1090                 iph->tot_len = 0;
1091                 iph->check = 0;
1092                 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1093                                                  0, IPPROTO_TCP, 0);
1094         } else if (skb_is_gso_v6(skb)) {
1095
1096                 ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb)
1097                                            : ipv6_hdr(skb);
1098                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1099                 ipv6h->payload_len = 0;
1100                 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1101                                                0, IPPROTO_TCP, 0);
1102         }
1103
1104         l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1105         *hdr_len = (skb->encapsulation
1106                     ? (skb_inner_transport_header(skb) - skb->data)
1107                     : skb_transport_offset(skb)) + l4len;
1108
1109         /* find the field values */
1110         cd_cmd = I40E_TX_CTX_DESC_TSO;
1111         cd_tso_len = skb->len - *hdr_len;
1112         cd_mss = skb_shinfo(skb)->gso_size;
1113         *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1114                                 ((u64)cd_tso_len <<
1115                                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1116                                 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1117         return 1;
1118 }
1119
1120 /**
1121  * i40e_tx_enable_csum - Enable Tx checksum offloads
1122  * @skb: send buffer
1123  * @tx_flags: Tx flags currently set
1124  * @td_cmd: Tx descriptor command bits to set
1125  * @td_offset: Tx descriptor header offsets to set
1126  * @cd_tunneling: ptr to context desc bits
1127  **/
1128 static void i40e_tx_enable_csum(struct sk_buff *skb, u32 tx_flags,
1129                                 u32 *td_cmd, u32 *td_offset,
1130                                 struct i40e_ring *tx_ring,
1131                                 u32 *cd_tunneling)
1132 {
1133         struct ipv6hdr *this_ipv6_hdr;
1134         unsigned int this_tcp_hdrlen;
1135         struct iphdr *this_ip_hdr;
1136         u32 network_hdr_len;
1137         u8 l4_hdr = 0;
1138
1139         if (skb->encapsulation) {
1140                 network_hdr_len = skb_inner_network_header_len(skb);
1141                 this_ip_hdr = inner_ip_hdr(skb);
1142                 this_ipv6_hdr = inner_ipv6_hdr(skb);
1143                 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1144
1145                 if (tx_flags & I40E_TX_FLAGS_IPV4) {
1146
1147                         if (tx_flags & I40E_TX_FLAGS_TSO) {
1148                                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1149                                 ip_hdr(skb)->check = 0;
1150                         } else {
1151                                 *cd_tunneling |=
1152                                          I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1153                         }
1154                 } else if (tx_flags & I40E_TX_FLAGS_IPV6) {
1155                         if (tx_flags & I40E_TX_FLAGS_TSO) {
1156                                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
1157                                 ip_hdr(skb)->check = 0;
1158                         } else {
1159                                 *cd_tunneling |=
1160                                          I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1161                         }
1162                 }
1163
1164                 /* Now set the ctx descriptor fields */
1165                 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
1166                                         I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
1167                                    I40E_TXD_CTX_UDP_TUNNELING            |
1168                                    ((skb_inner_network_offset(skb) -
1169                                         skb_transport_offset(skb)) >> 1) <<
1170                                    I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1171
1172         } else {
1173                 network_hdr_len = skb_network_header_len(skb);
1174                 this_ip_hdr = ip_hdr(skb);
1175                 this_ipv6_hdr = ipv6_hdr(skb);
1176                 this_tcp_hdrlen = tcp_hdrlen(skb);
1177         }
1178
1179         /* Enable IP checksum offloads */
1180         if (tx_flags & I40E_TX_FLAGS_IPV4) {
1181                 l4_hdr = this_ip_hdr->protocol;
1182                 /* the stack computes the IP header already, the only time we
1183                  * need the hardware to recompute it is in the case of TSO.
1184                  */
1185                 if (tx_flags & I40E_TX_FLAGS_TSO) {
1186                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1187                         this_ip_hdr->check = 0;
1188                 } else {
1189                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1190                 }
1191                 /* Now set the td_offset for IP header length */
1192                 *td_offset = (network_hdr_len >> 2) <<
1193                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1194         } else if (tx_flags & I40E_TX_FLAGS_IPV6) {
1195                 l4_hdr = this_ipv6_hdr->nexthdr;
1196                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1197                 /* Now set the td_offset for IP header length */
1198                 *td_offset = (network_hdr_len >> 2) <<
1199                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1200         }
1201         /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1202         *td_offset |= (skb_network_offset(skb) >> 1) <<
1203                        I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1204
1205         /* Enable L4 checksum offloads */
1206         switch (l4_hdr) {
1207         case IPPROTO_TCP:
1208                 /* enable checksum offloads */
1209                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1210                 *td_offset |= (this_tcp_hdrlen >> 2) <<
1211                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1212                 break;
1213         case IPPROTO_SCTP:
1214                 /* enable SCTP checksum offload */
1215                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1216                 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1217                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1218                 break;
1219         case IPPROTO_UDP:
1220                 /* enable UDP checksum offload */
1221                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1222                 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1223                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1224                 break;
1225         default:
1226                 break;
1227         }
1228 }
1229
1230 /**
1231  * i40e_create_tx_ctx Build the Tx context descriptor
1232  * @tx_ring:  ring to create the descriptor on
1233  * @cd_type_cmd_tso_mss: Quad Word 1
1234  * @cd_tunneling: Quad Word 0 - bits 0-31
1235  * @cd_l2tag2: Quad Word 0 - bits 32-63
1236  **/
1237 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1238                                const u64 cd_type_cmd_tso_mss,
1239                                const u32 cd_tunneling, const u32 cd_l2tag2)
1240 {
1241         struct i40e_tx_context_desc *context_desc;
1242         int i = tx_ring->next_to_use;
1243
1244         if (!cd_type_cmd_tso_mss && !cd_tunneling && !cd_l2tag2)
1245                 return;
1246
1247         /* grab the next descriptor */
1248         context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1249
1250         i++;
1251         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1252
1253         /* cpu_to_le32 and assign to struct fields */
1254         context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1255         context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1256         context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1257 }
1258
1259 /**
1260  * i40e_tx_map - Build the Tx descriptor
1261  * @tx_ring:  ring to send buffer on
1262  * @skb:      send buffer
1263  * @first:    first buffer info buffer to use
1264  * @tx_flags: collected send information
1265  * @hdr_len:  size of the packet header
1266  * @td_cmd:   the command field in the descriptor
1267  * @td_offset: offset for checksum or crc
1268  **/
1269 static void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1270                         struct i40e_tx_buffer *first, u32 tx_flags,
1271                         const u8 hdr_len, u32 td_cmd, u32 td_offset)
1272 {
1273         unsigned int data_len = skb->data_len;
1274         unsigned int size = skb_headlen(skb);
1275         struct skb_frag_struct *frag;
1276         struct i40e_tx_buffer *tx_bi;
1277         struct i40e_tx_desc *tx_desc;
1278         u16 i = tx_ring->next_to_use;
1279         u32 td_tag = 0;
1280         dma_addr_t dma;
1281         u16 gso_segs;
1282
1283         if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1284                 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1285                 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1286                          I40E_TX_FLAGS_VLAN_SHIFT;
1287         }
1288
1289         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1290                 gso_segs = skb_shinfo(skb)->gso_segs;
1291         else
1292                 gso_segs = 1;
1293
1294         /* multiply data chunks by size of headers */
1295         first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1296         first->gso_segs = gso_segs;
1297         first->skb = skb;
1298         first->tx_flags = tx_flags;
1299
1300         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1301
1302         tx_desc = I40E_TX_DESC(tx_ring, i);
1303         tx_bi = first;
1304
1305         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1306                 if (dma_mapping_error(tx_ring->dev, dma))
1307                         goto dma_error;
1308
1309                 /* record length, and DMA address */
1310                 dma_unmap_len_set(tx_bi, len, size);
1311                 dma_unmap_addr_set(tx_bi, dma, dma);
1312
1313                 tx_desc->buffer_addr = cpu_to_le64(dma);
1314
1315                 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1316                         tx_desc->cmd_type_offset_bsz =
1317                                 build_ctob(td_cmd, td_offset,
1318                                            I40E_MAX_DATA_PER_TXD, td_tag);
1319
1320                         tx_desc++;
1321                         i++;
1322                         if (i == tx_ring->count) {
1323                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
1324                                 i = 0;
1325                         }
1326
1327                         dma += I40E_MAX_DATA_PER_TXD;
1328                         size -= I40E_MAX_DATA_PER_TXD;
1329
1330                         tx_desc->buffer_addr = cpu_to_le64(dma);
1331                 }
1332
1333                 if (likely(!data_len))
1334                         break;
1335
1336                 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1337                                                           size, td_tag);
1338
1339                 tx_desc++;
1340                 i++;
1341                 if (i == tx_ring->count) {
1342                         tx_desc = I40E_TX_DESC(tx_ring, 0);
1343                         i = 0;
1344                 }
1345
1346                 size = skb_frag_size(frag);
1347                 data_len -= size;
1348
1349                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1350                                        DMA_TO_DEVICE);
1351
1352                 tx_bi = &tx_ring->tx_bi[i];
1353         }
1354
1355         tx_desc->cmd_type_offset_bsz =
1356                 build_ctob(td_cmd, td_offset, size, td_tag) |
1357                 cpu_to_le64((u64)I40E_TXD_CMD << I40E_TXD_QW1_CMD_SHIFT);
1358
1359         netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
1360                                                  tx_ring->queue_index),
1361                              first->bytecount);
1362
1363         /* set the timestamp */
1364         first->time_stamp = jiffies;
1365
1366         /* Force memory writes to complete before letting h/w
1367          * know there are new descriptors to fetch.  (Only
1368          * applicable for weak-ordered memory model archs,
1369          * such as IA-64).
1370          */
1371         wmb();
1372
1373         /* set next_to_watch value indicating a packet is present */
1374         first->next_to_watch = tx_desc;
1375
1376         i++;
1377         if (i == tx_ring->count)
1378                 i = 0;
1379
1380         tx_ring->next_to_use = i;
1381
1382         /* notify HW of packet */
1383         writel(i, tx_ring->tail);
1384
1385         return;
1386
1387 dma_error:
1388         dev_info(tx_ring->dev, "TX DMA map failed\n");
1389
1390         /* clear dma mappings for failed tx_bi map */
1391         for (;;) {
1392                 tx_bi = &tx_ring->tx_bi[i];
1393                 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
1394                 if (tx_bi == first)
1395                         break;
1396                 if (i == 0)
1397                         i = tx_ring->count;
1398                 i--;
1399         }
1400
1401         tx_ring->next_to_use = i;
1402 }
1403
1404 /**
1405  * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
1406  * @tx_ring: the ring to be checked
1407  * @size:    the size buffer we want to assure is available
1408  *
1409  * Returns -EBUSY if a stop is needed, else 0
1410  **/
1411 static inline int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1412 {
1413         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1414         /* Memory barrier before checking head and tail */
1415         smp_mb();
1416
1417         /* Check again in a case another CPU has just made room available. */
1418         if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1419                 return -EBUSY;
1420
1421         /* A reprieve! - use start_queue because it doesn't call schedule */
1422         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1423         ++tx_ring->tx_stats.restart_queue;
1424         return 0;
1425 }
1426
1427 /**
1428  * i40e_maybe_stop_tx - 1st level check for tx stop conditions
1429  * @tx_ring: the ring to be checked
1430  * @size:    the size buffer we want to assure is available
1431  *
1432  * Returns 0 if stop is not needed
1433  **/
1434 static int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1435 {
1436         if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
1437                 return 0;
1438         return __i40e_maybe_stop_tx(tx_ring, size);
1439 }
1440
1441 /**
1442  * i40e_xmit_descriptor_count - calculate number of tx descriptors needed
1443  * @skb:     send buffer
1444  * @tx_ring: ring to send buffer on
1445  *
1446  * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1447  * there is not enough descriptors available in this ring since we need at least
1448  * one descriptor.
1449  **/
1450 static int i40e_xmit_descriptor_count(struct sk_buff *skb,
1451                                       struct i40e_ring *tx_ring)
1452 {
1453 #if PAGE_SIZE > I40E_MAX_DATA_PER_TXD
1454         unsigned int f;
1455 #endif
1456         int count = 0;
1457
1458         /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1459          *       + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
1460          *       + 2 desc gap to keep tail from touching head,
1461          *       + 1 desc for context descriptor,
1462          * otherwise try next time
1463          */
1464 #if PAGE_SIZE > I40E_MAX_DATA_PER_TXD
1465         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1466                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
1467 #else
1468         count += skb_shinfo(skb)->nr_frags;
1469 #endif
1470         count += TXD_USE_COUNT(skb_headlen(skb));
1471         if (i40e_maybe_stop_tx(tx_ring, count + 3)) {
1472                 tx_ring->tx_stats.tx_busy++;
1473                 return 0;
1474         }
1475         return count;
1476 }
1477
1478 /**
1479  * i40e_xmit_frame_ring - Sends buffer on Tx ring
1480  * @skb:     send buffer
1481  * @tx_ring: ring to send buffer on
1482  *
1483  * Returns NETDEV_TX_OK if sent, else an error code
1484  **/
1485 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
1486                                         struct i40e_ring *tx_ring)
1487 {
1488         u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
1489         u32 cd_tunneling = 0, cd_l2tag2 = 0;
1490         struct i40e_tx_buffer *first;
1491         u32 td_offset = 0;
1492         u32 tx_flags = 0;
1493         __be16 protocol;
1494         u32 td_cmd = 0;
1495         u8 hdr_len = 0;
1496         int tso;
1497         if (0 == i40e_xmit_descriptor_count(skb, tx_ring))
1498                 return NETDEV_TX_BUSY;
1499
1500         /* prepare the xmit flags */
1501         if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
1502                 goto out_drop;
1503
1504         /* obtain protocol of skb */
1505         protocol = skb->protocol;
1506
1507         /* record the location of the first descriptor for this packet */
1508         first = &tx_ring->tx_bi[tx_ring->next_to_use];
1509
1510         /* setup IPv4/IPv6 offloads */
1511         if (protocol == htons(ETH_P_IP))
1512                 tx_flags |= I40E_TX_FLAGS_IPV4;
1513         else if (protocol == htons(ETH_P_IPV6))
1514                 tx_flags |= I40E_TX_FLAGS_IPV6;
1515
1516         tso = i40e_tso(tx_ring, skb, tx_flags, protocol, &hdr_len,
1517                        &cd_type_cmd_tso_mss, &cd_tunneling);
1518
1519         if (tso < 0)
1520                 goto out_drop;
1521         else if (tso)
1522                 tx_flags |= I40E_TX_FLAGS_TSO;
1523
1524         skb_tx_timestamp(skb);
1525
1526         /* always enable CRC insertion offload */
1527         td_cmd |= I40E_TX_DESC_CMD_ICRC;
1528
1529         /* Always offload the checksum, since it's in the data descriptor */
1530         if (skb->ip_summed == CHECKSUM_PARTIAL) {
1531                 tx_flags |= I40E_TX_FLAGS_CSUM;
1532
1533                 i40e_tx_enable_csum(skb, tx_flags, &td_cmd, &td_offset,
1534                                     tx_ring, &cd_tunneling);
1535         }
1536
1537         i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
1538                            cd_tunneling, cd_l2tag2);
1539
1540         i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
1541                     td_cmd, td_offset);
1542
1543         i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
1544
1545         return NETDEV_TX_OK;
1546
1547 out_drop:
1548         dev_kfree_skb_any(skb);
1549         return NETDEV_TX_OK;
1550 }
1551
1552 /**
1553  * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
1554  * @skb:    send buffer
1555  * @netdev: network interface device structure
1556  *
1557  * Returns NETDEV_TX_OK if sent, else an error code
1558  **/
1559 netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1560 {
1561         struct i40evf_adapter *adapter = netdev_priv(netdev);
1562         struct i40e_ring *tx_ring = adapter->tx_rings[skb->queue_mapping];
1563
1564         /* hardware can't handle really short frames, hardware padding works
1565          * beyond this point
1566          */
1567         if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
1568                 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
1569                         return NETDEV_TX_OK;
1570                 skb->len = I40E_MIN_TX_LEN;
1571                 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
1572         }
1573
1574         return i40e_xmit_frame_ring(skb, tx_ring);
1575 }