drivers/net/ethernet/intel/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G 10/100 Network Connection
  31  * 82562G-2 10/100 Network Connection
  32  * 82562GT 10/100 Network Connection
  33  * 82562GT-2 10/100 Network Connection
  34  * 82562V 10/100 Network Connection
  35  * 82562V-2 10/100 Network Connection
  36  * 82566DC-2 Gigabit Network Connection
  37  * 82566DC Gigabit Network Connection
  38  * 82566DM-2 Gigabit Network Connection
  39  * 82566DM Gigabit Network Connection
  40  * 82566MC Gigabit Network Connection
  41  * 82566MM Gigabit Network Connection
  42  * 82567LM Gigabit Network Connection
  43  * 82567LF Gigabit Network Connection
  44  * 82567V Gigabit Network Connection
  45  * 82567LM-2 Gigabit Network Connection
  46  * 82567LF-2 Gigabit Network Connection
  47  * 82567V-2 Gigabit Network Connection
  48  * 82567LF-3 Gigabit Network Connection
  49  * 82567LM-3 Gigabit Network Connection
  50  * 82567LM-4 Gigabit Network Connection
  51  * 82577LM Gigabit Network Connection
  52  * 82577LC Gigabit Network Connection
  53  * 82578DM Gigabit Network Connection
  54  * 82578DC Gigabit Network Connection
  55  * 82579LM Gigabit Network Connection
  56  * 82579V Gigabit Network Connection
  57  */
  58
  59 #include "e1000.h"
  60
  61 #define ICH_FLASH_GFPREG                0x0000
  62 #define ICH_FLASH_HSFSTS                0x0004
  63 #define ICH_FLASH_HSFCTL                0x0006
  64 #define ICH_FLASH_FADDR                 0x0008
  65 #define ICH_FLASH_FDATA0                0x0010
  66 #define ICH_FLASH_PR0                   0x0074
  67
  68 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  69 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  70 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  71 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  72 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  73
  74 #define ICH_CYCLE_READ                  0
  75 #define ICH_CYCLE_WRITE                 2
  76 #define ICH_CYCLE_ERASE                 3
  77
  78 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  79 #define FLASH_SECTOR_ADDR_SHIFT         12
  80
  81 #define ICH_FLASH_SEG_SIZE_256          256
  82 #define ICH_FLASH_SEG_SIZE_4K           4096
  83 #define ICH_FLASH_SEG_SIZE_8K           8192
  84 #define ICH_FLASH_SEG_SIZE_64K          65536
  85
  86
  87 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  88 /* FW established a valid mode */
  89 #define E1000_ICH_FWSM_FW_VALID         0x00008000
  90
  91 #define E1000_ICH_MNG_IAMT_MODE         0x2
  92
  93 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  94                                  (ID_LED_DEF1_OFF2 <<  8) | \
  95                                  (ID_LED_DEF1_ON2  <<  4) | \
  96                                  (ID_LED_DEF1_DEF2))
  97
  98 #define E1000_ICH_NVM_SIG_WORD          0x13
  99 #define E1000_ICH_NVM_SIG_MASK          0xC000
 100 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
 101 #define E1000_ICH_NVM_SIG_VALUE         0x80
 102
 103 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
 104
 105 #define E1000_FEXTNVM_SW_CONFIG         1
 106 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 107
 108 #define E1000_FEXTNVM4_BEACON_DURATION_MASK    0x7
 109 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC   0x7
 110 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC  0x3
 111
 112 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 113
 114 #define E1000_ICH_RAR_ENTRIES           7
 115
 116 #define PHY_PAGE_SHIFT 5
 117 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 118                            ((reg) & MAX_PHY_REG_ADDRESS))
 119 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 120 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 121
 122 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 123 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 124 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 125
 126 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 127
 128 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
 129
 130 /* SMBus Address Phy Register */
 131 #define HV_SMB_ADDR            PHY_REG(768, 26)
 132 #define HV_SMB_ADDR_MASK       0x007F
 133 #define HV_SMB_ADDR_PEC_EN     0x0200
 134 #define HV_SMB_ADDR_VALID      0x0080
 135
 136 /* PHY Power Management Control */
 137 #define HV_PM_CTRL              PHY_REG(770, 17)
 138
 139 /* PHY Low Power Idle Control */
 140 #define I82579_LPI_CTRL                         PHY_REG(772, 20)
 141 #define I82579_LPI_CTRL_ENABLE_MASK             0x6000
 142 #define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT    0x80
 143
 144 /* EMI Registers */
 145 #define I82579_EMI_ADDR         0x10
 146 #define I82579_EMI_DATA         0x11
 147 #define I82579_LPI_UPDATE_TIMER 0x4805  /* in 40ns units + 40 ns base value */
 148
 149 /* Strapping Option Register - RO */
 150 #define E1000_STRAP                     0x0000C
 151 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
 152 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
 153
 154 /* OEM Bits Phy Register */
 155 #define HV_OEM_BITS            PHY_REG(768, 25)
 156 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
 157 #define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
 158 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
 159
 160 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
 161 #define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
 162
 163 /* KMRN Mode Control */
 164 #define HV_KMRN_MODE_CTRL      PHY_REG(769, 16)
 165 #define HV_KMRN_MDIO_SLOW      0x0400
 166
 167 /* KMRN FIFO Control and Status */
 168 #define HV_KMRN_FIFO_CTRLSTA                  PHY_REG(770, 16)
 169 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK    0x7000
 170 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT   12
 171
 172 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 173 /* Offset 04h HSFSTS */
 174 union ich8_hws_flash_status {
 175         struct ich8_hsfsts {
 176                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 177                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 178                 u16 dael       :1; /* bit 2 Direct Access error Log */
 179                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 180                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 181                 u16 reserved1  :2; /* bit 13:6 Reserved */
 182                 u16 reserved2  :6; /* bit 13:6 Reserved */
 183                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 184                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 185         } hsf_status;
 186         u16 regval;
 187 };
 188
 189 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 190 /* Offset 06h FLCTL */
 191 union ich8_hws_flash_ctrl {
 192         struct ich8_hsflctl {
 193                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 194                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 195                 u16 reserved   :5;   /* 7:3 Reserved  */
 196                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 197                 u16 flockdn    :6;   /* 15:10 Reserved */
 198         } hsf_ctrl;
 199         u16 regval;
 200 };
 201
 202 /* ICH Flash Region Access Permissions */
 203 union ich8_hws_flash_regacc {
 204         struct ich8_flracc {
 205                 u32 grra      :8; /* 0:7 GbE region Read Access */
 206                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 207                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 208                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 209         } hsf_flregacc;
 210         u16 regval;
 211 };
 212
 213 /* ICH Flash Protected Region */
 214 union ich8_flash_protected_range {
 215         struct ich8_pr {
 216                 u32 base:13;     /* 0:12 Protected Range Base */
 217                 u32 reserved1:2; /* 13:14 Reserved */
 218                 u32 rpe:1;       /* 15 Read Protection Enable */
 219                 u32 limit:13;    /* 16:28 Protected Range Limit */
 220                 u32 reserved2:2; /* 29:30 Reserved */
 221                 u32 wpe:1;       /* 31 Write Protection Enable */
 222         } range;
 223         u32 regval;
 224 };
 225
 226 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 227 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 228 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 229 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 230 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 231                                                 u32 offset, u8 byte);
 232 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 233                                          u8 *data);
 234 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 235                                          u16 *data);
 236 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 237                                          u8 size, u16 *data);
 238 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 239 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 240 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 241 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 242 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 243 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 244 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 245 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 246 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 247 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 248 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 249 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 250 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 251 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 252 static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 253 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 254 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 255 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 256 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 257 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 258
 259 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 260 {
 261         return readw(hw->flash_address + reg);
 262 }
 263
 264 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 265 {
 266         return readl(hw->flash_address + reg);
 267 }
 268
 269 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 270 {
 271         writew(val, hw->flash_address + reg);
 272 }
 273
 274 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 275 {
 276         writel(val, hw->flash_address + reg);
 277 }
 278
 279 #define er16flash(reg)          __er16flash(hw, (reg))
 280 #define er32flash(reg)          __er32flash(hw, (reg))
 281 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
 282 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
 283
 284 static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw *hw)
 285 {
 286         u32 ctrl;
 287
 288         ctrl = er32(CTRL);
 289         ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
 290         ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
 291         ew32(CTRL, ctrl);
 292         e1e_flush();
 293         udelay(10);
 294         ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 295         ew32(CTRL, ctrl);
 296 }
 297
 298 /**
 299  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 300  *  @hw: pointer to the HW structure
 301  *
 302  *  Initialize family-specific PHY parameters and function pointers.
 303  **/
 304 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 305 {
 306         struct e1000_phy_info *phy = &hw->phy;
 307         u32 fwsm;
 308         s32 ret_val = 0;
 309
 310         phy->addr                     = 1;
 311         phy->reset_delay_us           = 100;
 312
 313         phy->ops.set_page             = e1000_set_page_igp;
 314         phy->ops.read_reg             = e1000_read_phy_reg_hv;
 315         phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;
 316         phy->ops.read_reg_page        = e1000_read_phy_reg_page_hv;
 317         phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
 318         phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
 319         phy->ops.write_reg            = e1000_write_phy_reg_hv;
 320         phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;
 321         phy->ops.write_reg_page       = e1000_write_phy_reg_page_hv;
 322         phy->ops.power_up             = e1000_power_up_phy_copper;
 323         phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
 324         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 325
 326         /*
 327          * The MAC-PHY interconnect may still be in SMBus mode
 328          * after Sx->S0.  If the manageability engine (ME) is
 329          * disabled, then toggle the LANPHYPC Value bit to force
 330          * the interconnect to PCIe mode.
 331          */
 332         fwsm = er32(FWSM);
 333         if (!(fwsm & E1000_ICH_FWSM_FW_VALID) && !e1000_check_reset_block(hw)) {
 334                 e1000_toggle_lanphypc_value_ich8lan(hw);
 335                 msleep(50);
 336
 337                 /*
 338                  * Gate automatic PHY configuration by hardware on
 339                  * non-managed 82579
 340                  */
 341                 if (hw->mac.type == e1000_pch2lan)
 342                         e1000_gate_hw_phy_config_ich8lan(hw, true);
 343         }
 344
 345         /*
 346          * Reset the PHY before any access to it.  Doing so, ensures that
 347          * the PHY is in a known good state before we read/write PHY registers.
 348          * The generic reset is sufficient here, because we haven't determined
 349          * the PHY type yet.
 350          */
 351         ret_val = e1000e_phy_hw_reset_generic(hw);
 352         if (ret_val)
 353                 goto out;
 354
 355         /* Ungate automatic PHY configuration on non-managed 82579 */
 356         if ((hw->mac.type == e1000_pch2lan) &&
 357             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 358                 usleep_range(10000, 20000);
 359                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 360         }
 361
 362         phy->id = e1000_phy_unknown;
 363         switch (hw->mac.type) {
 364         default:
 365                 ret_val = e1000e_get_phy_id(hw);
 366                 if (ret_val)
 367                         goto out;
 368                 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 369                         break;
 370                 /* fall-through */
 371         case e1000_pch2lan:
 372                 /*
 373                  * In case the PHY needs to be in mdio slow mode,
 374                  * set slow mode and try to get the PHY id again.
 375                  */
 376                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 377                 if (ret_val)
 378                         goto out;
 379                 ret_val = e1000e_get_phy_id(hw);
 380                 if (ret_val)
 381                         goto out;
 382                 break;
 383         }
 384         phy->type = e1000e_get_phy_type_from_id(phy->id);
 385
 386         switch (phy->type) {
 387         case e1000_phy_82577:
 388         case e1000_phy_82579:
 389                 phy->ops.check_polarity = e1000_check_polarity_82577;
 390                 phy->ops.force_speed_duplex =
 391                     e1000_phy_force_speed_duplex_82577;
 392                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 393                 phy->ops.get_info = e1000_get_phy_info_82577;
 394                 phy->ops.commit = e1000e_phy_sw_reset;
 395                 break;
 396         case e1000_phy_82578:
 397                 phy->ops.check_polarity = e1000_check_polarity_m88;
 398                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 399                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 400                 phy->ops.get_info = e1000e_get_phy_info_m88;
 401                 break;
 402         default:
 403                 ret_val = -E1000_ERR_PHY;
 404                 break;
 405         }
 406
 407 out:
 408         return ret_val;
 409 }
 410
 411 /**
 412  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 413  *  @hw: pointer to the HW structure
 414  *
 415  *  Initialize family-specific PHY parameters and function pointers.
 416  **/
 417 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 418 {
 419         struct e1000_phy_info *phy = &hw->phy;
 420         s32 ret_val;
 421         u16 i = 0;
 422
 423         phy->addr                       = 1;
 424         phy->reset_delay_us             = 100;
 425
 426         phy->ops.power_up               = e1000_power_up_phy_copper;
 427         phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;
 428
 429         /*
 430          * We may need to do this twice - once for IGP and if that fails,
 431          * we'll set BM func pointers and try again
 432          */
 433         ret_val = e1000e_determine_phy_address(hw);
 434         if (ret_val) {
 435                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 436                 phy->ops.read_reg  = e1000e_read_phy_reg_bm;
 437                 ret_val = e1000e_determine_phy_address(hw);
 438                 if (ret_val) {
 439                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 440                         return ret_val;
 441                 }
 442         }
 443
 444         phy->id = 0;
 445         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 446                (i++ < 100)) {
 447                 usleep_range(1000, 2000);
 448                 ret_val = e1000e_get_phy_id(hw);
 449                 if (ret_val)
 450                         return ret_val;
 451         }
 452
 453         /* Verify phy id */
 454         switch (phy->id) {
 455         case IGP03E1000_E_PHY_ID:
 456                 phy->type = e1000_phy_igp_3;
 457                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 458                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 459                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 460                 phy->ops.get_info = e1000e_get_phy_info_igp;
 461                 phy->ops.check_polarity = e1000_check_polarity_igp;
 462                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 463                 break;
 464         case IFE_E_PHY_ID:
 465         case IFE_PLUS_E_PHY_ID:
 466         case IFE_C_E_PHY_ID:
 467                 phy->type = e1000_phy_ife;
 468                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 469                 phy->ops.get_info = e1000_get_phy_info_ife;
 470                 phy->ops.check_polarity = e1000_check_polarity_ife;
 471                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 472                 break;
 473         case BME1000_E_PHY_ID:
 474                 phy->type = e1000_phy_bm;
 475                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 476                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 477                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 478                 phy->ops.commit = e1000e_phy_sw_reset;
 479                 phy->ops.get_info = e1000e_get_phy_info_m88;
 480                 phy->ops.check_polarity = e1000_check_polarity_m88;
 481                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 482                 break;
 483         default:
 484                 return -E1000_ERR_PHY;
 485                 break;
 486         }
 487
 488         return 0;
 489 }
 490
 491 /**
 492  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 493  *  @hw: pointer to the HW structure
 494  *
 495  *  Initialize family-specific NVM parameters and function
 496  *  pointers.
 497  **/
 498 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 499 {
 500         struct e1000_nvm_info *nvm = &hw->nvm;
 501         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 502         u32 gfpreg, sector_base_addr, sector_end_addr;
 503         u16 i;
 504
 505         /* Can't read flash registers if the register set isn't mapped. */
 506         if (!hw->flash_address) {
 507                 e_dbg("ERROR: Flash registers not mapped\n");
 508                 return -E1000_ERR_CONFIG;
 509         }
 510
 511         nvm->type = e1000_nvm_flash_sw;
 512
 513         gfpreg = er32flash(ICH_FLASH_GFPREG);
 514
 515         /*
 516          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 517          * Add 1 to sector_end_addr since this sector is included in
 518          * the overall size.
 519          */
 520         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 521         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 522
 523         /* flash_base_addr is byte-aligned */
 524         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 525
 526         /*
 527          * find total size of the NVM, then cut in half since the total
 528          * size represents two separate NVM banks.
 529          */
 530         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 531                                 << FLASH_SECTOR_ADDR_SHIFT;
 532         nvm->flash_bank_size /= 2;
 533         /* Adjust to word count */
 534         nvm->flash_bank_size /= sizeof(u16);
 535
 536         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 537
 538         /* Clear shadow ram */
 539         for (i = 0; i < nvm->word_size; i++) {
 540                 dev_spec->shadow_ram[i].modified = false;
 541                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 542         }
 543
 544         return 0;
 545 }
 546
 547 /**
 548  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 549  *  @hw: pointer to the HW structure
 550  *
 551  *  Initialize family-specific MAC parameters and function
 552  *  pointers.
 553  **/
 554 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
 555 {
 556         struct e1000_hw *hw = &adapter->hw;
 557         struct e1000_mac_info *mac = &hw->mac;
 558
 559         /* Set media type function pointer */
 560         hw->phy.media_type = e1000_media_type_copper;
 561
 562         /* Set mta register count */
 563         mac->mta_reg_count = 32;
 564         /* Set rar entry count */
 565         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 566         if (mac->type == e1000_ich8lan)
 567                 mac->rar_entry_count--;
 568         /* FWSM register */
 569         mac->has_fwsm = true;
 570         /* ARC subsystem not supported */
 571         mac->arc_subsystem_valid = false;
 572         /* Adaptive IFS supported */
 573         mac->adaptive_ifs = true;
 574
 575         /* LED operations */
 576         switch (mac->type) {
 577         case e1000_ich8lan:
 578         case e1000_ich9lan:
 579         case e1000_ich10lan:
 580                 /* check management mode */
 581                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 582                 /* ID LED init */
 583                 mac->ops.id_led_init = e1000e_id_led_init;
 584                 /* blink LED */
 585                 mac->ops.blink_led = e1000e_blink_led_generic;
 586                 /* setup LED */
 587                 mac->ops.setup_led = e1000e_setup_led_generic;
 588                 /* cleanup LED */
 589                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 590                 /* turn on/off LED */
 591                 mac->ops.led_on = e1000_led_on_ich8lan;
 592                 mac->ops.led_off = e1000_led_off_ich8lan;
 593                 break;
 594         case e1000_pchlan:
 595         case e1000_pch2lan:
 596                 /* check management mode */
 597                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 598                 /* ID LED init */
 599                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 600                 /* setup LED */
 601                 mac->ops.setup_led = e1000_setup_led_pchlan;
 602                 /* cleanup LED */
 603                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 604                 /* turn on/off LED */
 605                 mac->ops.led_on = e1000_led_on_pchlan;
 606                 mac->ops.led_off = e1000_led_off_pchlan;
 607                 break;
 608         default:
 609                 break;
 610         }
 611
 612         /* Enable PCS Lock-loss workaround for ICH8 */
 613         if (mac->type == e1000_ich8lan)
 614                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 615
 616         /* Gate automatic PHY configuration by hardware on managed 82579 */
 617         if ((mac->type == e1000_pch2lan) &&
 618             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
 619                 e1000_gate_hw_phy_config_ich8lan(hw, true);
 620
 621         return 0;
 622 }
 623
 624 /**
 625  *  e1000_set_eee_pchlan - Enable/disable EEE support
 626  *  @hw: pointer to the HW structure
 627  *
 628  *  Enable/disable EEE based on setting in dev_spec structure.  The bits in
 629  *  the LPI Control register will remain set only if/when link is up.
 630  **/
 631 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 632 {
 633         s32 ret_val = 0;
 634         u16 phy_reg;
 635
 636         if (hw->phy.type != e1000_phy_82579)
 637                 goto out;
 638
 639         ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
 640         if (ret_val)
 641                 goto out;
 642
 643         if (hw->dev_spec.ich8lan.eee_disable)
 644                 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
 645         else
 646                 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
 647
 648         ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
 649 out:
 650         return ret_val;
 651 }
 652
 653 /**
 654  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 655  *  @hw: pointer to the HW structure
 656  *
 657  *  Checks to see of the link status of the hardware has changed.  If a
 658  *  change in link status has been detected, then we read the PHY registers
 659  *  to get the current speed/duplex if link exists.
 660  *
 661  *  Returns a negative error code (-E1000_ERR_*) or 0 (link down) or 1 (link
 662  *  up).
 663  **/
 664 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 665 {
 666         struct e1000_mac_info *mac = &hw->mac;
 667         s32 ret_val;
 668         bool link;
 669         u16 phy_reg;
 670
 671         /*
 672          * We only want to go out to the PHY registers to see if Auto-Neg
 673          * has completed and/or if our link status has changed.  The
 674          * get_link_status flag is set upon receiving a Link Status
 675          * Change or Rx Sequence Error interrupt.
 676          */
 677         if (!mac->get_link_status) {
 678                 ret_val = 1;
 679                 goto out;
 680         }
 681
 682         /*
 683          * First we want to see if the MII Status Register reports
 684          * link.  If so, then we want to get the current speed/duplex
 685          * of the PHY.
 686          */
 687         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 688         if (ret_val)
 689                 goto out;
 690
 691         if (hw->mac.type == e1000_pchlan) {
 692                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
 693                 if (ret_val)
 694                         goto out;
 695         }
 696
 697         if (!link)
 698                 goto out; /* No link detected */
 699
 700         mac->get_link_status = false;
 701
 702         switch (hw->mac.type) {
 703         case e1000_pch2lan:
 704                 ret_val = e1000_k1_workaround_lv(hw);
 705                 if (ret_val)
 706                         goto out;
 707                 /* fall-thru */
 708         case e1000_pchlan:
 709                 if (hw->phy.type == e1000_phy_82578) {
 710                         ret_val = e1000_link_stall_workaround_hv(hw);
 711                         if (ret_val)
 712                                 goto out;
 713                 }
 714
 715                 /*
 716                  * Workaround for PCHx parts in half-duplex:
 717                  * Set the number of preambles removed from the packet
 718                  * when it is passed from the PHY to the MAC to prevent
 719                  * the MAC from misinterpreting the packet type.
 720                  */
 721                 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
 722                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
 723
 724                 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
 725                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
 726
 727                 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
 728                 break;
 729         default:
 730                 break;
 731         }
 732
 733         /*
 734          * Check if there was DownShift, must be checked
 735          * immediately after link-up
 736          */
 737         e1000e_check_downshift(hw);
 738
 739         /* Enable/Disable EEE after link up */
 740         ret_val = e1000_set_eee_pchlan(hw);
 741         if (ret_val)
 742                 goto out;
 743
 744         /*
 745          * If we are forcing speed/duplex, then we simply return since
 746          * we have already determined whether we have link or not.
 747          */
 748         if (!mac->autoneg) {
 749                 ret_val = -E1000_ERR_CONFIG;
 750                 goto out;
 751         }
 752
 753         /*
 754          * Auto-Neg is enabled.  Auto Speed Detection takes care
 755          * of MAC speed/duplex configuration.  So we only need to
 756          * configure Collision Distance in the MAC.
 757          */
 758         e1000e_config_collision_dist(hw);
 759
 760         /*
 761          * Configure Flow Control now that Auto-Neg has completed.
 762          * First, we need to restore the desired flow control
 763          * settings because we may have had to re-autoneg with a
 764          * different link partner.
 765          */
 766         ret_val = e1000e_config_fc_after_link_up(hw);
 767         if (ret_val) {
 768                 e_dbg("Error configuring flow control\n");
 769                 return ret_val;
 770         }
 771
 772         ret_val = 1;
 773 out:
 774         return ret_val;
 775 }
 776
 777 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 778 {
 779         struct e1000_hw *hw = &adapter->hw;
 780         s32 rc;
 781
 782         rc = e1000_init_mac_params_ich8lan(adapter);
 783         if (rc)
 784                 return rc;
 785
 786         rc = e1000_init_nvm_params_ich8lan(hw);
 787         if (rc)
 788                 return rc;
 789
 790         switch (hw->mac.type) {
 791         case e1000_ich8lan:
 792         case e1000_ich9lan:
 793         case e1000_ich10lan:
 794                 rc = e1000_init_phy_params_ich8lan(hw);
 795                 break;
 796         case e1000_pchlan:
 797         case e1000_pch2lan:
 798                 rc = e1000_init_phy_params_pchlan(hw);
 799                 break;
 800         default:
 801                 break;
 802         }
 803         if (rc)
 804                 return rc;
 805
 806         /*
 807          * Disable Jumbo Frame support on parts with Intel 10/100 PHY or
 808          * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
 809          */
 810         if ((adapter->hw.phy.type == e1000_phy_ife) ||
 811             ((adapter->hw.mac.type >= e1000_pch2lan) &&
 812              (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
 813                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 814                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
 815
 816                 hw->mac.ops.blink_led = NULL;
 817         }
 818
 819         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 820             (adapter->hw.phy.type != e1000_phy_ife))
 821                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 822
 823         /* Enable workaround for 82579 w/ ME enabled */
 824         if ((adapter->hw.mac.type == e1000_pch2lan) &&
 825             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
 826                 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
 827
 828         /* Disable EEE by default until IEEE802.3az spec is finalized */
 829         if (adapter->flags2 & FLAG2_HAS_EEE)
 830                 adapter->hw.dev_spec.ich8lan.eee_disable = true;
 831
 832         return 0;
 833 }
 834
 835 static DEFINE_MUTEX(nvm_mutex);
 836
 837 /**
 838  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
 839  *  @hw: pointer to the HW structure
 840  *
 841  *  Acquires the mutex for performing NVM operations.
 842  **/
 843 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
 844 {
 845         mutex_lock(&nvm_mutex);
 846
 847         return 0;
 848 }
 849
 850 /**
 851  *  e1000_release_nvm_ich8lan - Release NVM mutex
 852  *  @hw: pointer to the HW structure
 853  *
 854  *  Releases the mutex used while performing NVM operations.
 855  **/
 856 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
 857 {
 858         mutex_unlock(&nvm_mutex);
 859 }
 860
 861 /**
 862  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 863  *  @hw: pointer to the HW structure
 864  *
 865  *  Acquires the software control flag for performing PHY and select
 866  *  MAC CSR accesses.
 867  **/
 868 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 869 {
 870         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
 871         s32 ret_val = 0;
 872
 873         if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
 874                              &hw->adapter->state)) {
 875                 e_dbg("contention for Phy access\n");
 876                 return -E1000_ERR_PHY;
 877         }
 878
 879         while (timeout) {
 880                 extcnf_ctrl = er32(EXTCNF_CTRL);
 881                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
 882                         break;
 883
 884                 mdelay(1);
 885                 timeout--;
 886         }
 887
 888         if (!timeout) {
 889                 e_dbg("SW has already locked the resource.\n");
 890                 ret_val = -E1000_ERR_CONFIG;
 891                 goto out;
 892         }
 893
 894         timeout = SW_FLAG_TIMEOUT;
 895
 896         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 897         ew32(EXTCNF_CTRL, extcnf_ctrl);
 898
 899         while (timeout) {
 900                 extcnf_ctrl = er32(EXTCNF_CTRL);
 901                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 902                         break;
 903
 904                 mdelay(1);
 905                 timeout--;
 906         }
 907
 908         if (!timeout) {
 909                 e_dbg("Failed to acquire the semaphore, FW or HW has it: "
 910                       "FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
 911                       er32(FWSM), extcnf_ctrl);
 912                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 913                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 914                 ret_val = -E1000_ERR_CONFIG;
 915                 goto out;
 916         }
 917
 918 out:
 919         if (ret_val)
 920                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
 921
 922         return ret_val;
 923 }
 924
 925 /**
 926  *  e1000_release_swflag_ich8lan - Release software control flag
 927  *  @hw: pointer to the HW structure
 928  *
 929  *  Releases the software control flag for performing PHY and select
 930  *  MAC CSR accesses.
 931  **/
 932 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 933 {
 934         u32 extcnf_ctrl;
 935
 936         extcnf_ctrl = er32(EXTCNF_CTRL);
 937
 938         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
 939                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 940                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 941         } else {
 942                 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
 943         }
 944
 945         clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
 946 }
 947
 948 /**
 949  *  e1000_check_mng_mode_ich8lan - Checks management mode
 950  *  @hw: pointer to the HW structure
 951  *
 952  *  This checks if the adapter has any manageability enabled.
 953  *  This is a function pointer entry point only called by read/write
 954  *  routines for the PHY and NVM parts.
 955  **/
 956 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 957 {
 958         u32 fwsm;
 959
 960         fwsm = er32(FWSM);
 961         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 962                ((fwsm & E1000_FWSM_MODE_MASK) ==
 963                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 964 }
 965
 966 /**
 967  *  e1000_check_mng_mode_pchlan - Checks management mode
 968  *  @hw: pointer to the HW structure
 969  *
 970  *  This checks if the adapter has iAMT enabled.
 971  *  This is a function pointer entry point only called by read/write
 972  *  routines for the PHY and NVM parts.
 973  **/
 974 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
 975 {
 976         u32 fwsm;
 977
 978         fwsm = er32(FWSM);
 979         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 980                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 981 }
 982
 983 /**
 984  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 985  *  @hw: pointer to the HW structure
 986  *
 987  *  Checks if firmware is blocking the reset of the PHY.
 988  *  This is a function pointer entry point only called by
 989  *  reset routines.
 990  **/
 991 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 992 {
 993         u32 fwsm;
 994
 995         fwsm = er32(FWSM);
 996
 997         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 998 }
 999
1000 /**
1001  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
1002  *  @hw: pointer to the HW structure
1003  *
1004  *  Assumes semaphore already acquired.
1005  *
1006  **/
1007 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1008 {
1009         u16 phy_data;
1010         u32 strap = er32(STRAP);
1011         s32 ret_val = 0;
1012
1013         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1014
1015         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1016         if (ret_val)
1017                 goto out;
1018
1019         phy_data &= ~HV_SMB_ADDR_MASK;
1020         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1021         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
1022         ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1023
1024 out:
1025         return ret_val;
1026 }
1027
1028 /**
1029  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1030  *  @hw:   pointer to the HW structure
1031  *
1032  *  SW should configure the LCD from the NVM extended configuration region
1033  *  as a workaround for certain parts.
1034  **/
1035 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1036 {
1037         struct e1000_phy_info *phy = &hw->phy;
1038         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
1039         s32 ret_val = 0;
1040         u16 word_addr, reg_data, reg_addr, phy_page = 0;
1041
1042         /*
1043          * Initialize the PHY from the NVM on ICH platforms.  This
1044          * is needed due to an issue where the NVM configuration is
1045          * not properly autoloaded after power transitions.
1046          * Therefore, after each PHY reset, we will load the
1047          * configuration data out of the NVM manually.
1048          */
1049         switch (hw->mac.type) {
1050         case e1000_ich8lan:
1051                 if (phy->type != e1000_phy_igp_3)
1052                         return ret_val;
1053
1054                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1055                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
1056                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1057                         break;
1058                 }
1059                 /* Fall-thru */
1060         case e1000_pchlan:
1061         case e1000_pch2lan:
1062                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1063                 break;
1064         default:
1065                 return ret_val;
1066         }
1067
1068         ret_val = hw->phy.ops.acquire(hw);
1069         if (ret_val)
1070                 return ret_val;
1071
1072         data = er32(FEXTNVM);
1073         if (!(data & sw_cfg_mask))
1074                 goto out;
1075
1076         /*
1077          * Make sure HW does not configure LCD from PHY
1078          * extended configuration before SW configuration
1079          */
1080         data = er32(EXTCNF_CTRL);
1081         if (!(hw->mac.type == e1000_pch2lan)) {
1082                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
1083                         goto out;
1084         }
1085
1086         cnf_size = er32(EXTCNF_SIZE);
1087         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1088         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1089         if (!cnf_size)
1090                 goto out;
1091
1092         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1093         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1094
1095         if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
1096             (hw->mac.type == e1000_pchlan)) ||
1097              (hw->mac.type == e1000_pch2lan)) {
1098                 /*
1099                  * HW configures the SMBus address and LEDs when the
1100                  * OEM and LCD Write Enable bits are set in the NVM.
1101                  * When both NVM bits are cleared, SW will configure
1102                  * them instead.
1103                  */
1104                 ret_val = e1000_write_smbus_addr(hw);
1105                 if (ret_val)
1106                         goto out;
1107
1108                 data = er32(LEDCTL);
1109                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1110                                                         (u16)data);
1111                 if (ret_val)
1112                         goto out;
1113         }
1114
1115         /* Configure LCD from extended configuration region. */
1116
1117         /* cnf_base_addr is in DWORD */
1118         word_addr = (u16)(cnf_base_addr << 1);
1119
1120         for (i = 0; i < cnf_size; i++) {
1121                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1122                                          &reg_data);
1123                 if (ret_val)
1124                         goto out;
1125
1126                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1127                                          1, &reg_addr);
1128                 if (ret_val)
1129                         goto out;
1130
1131                 /* Save off the PHY page for future writes. */
1132                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1133                         phy_page = reg_data;
1134                         continue;
1135                 }
1136
1137                 reg_addr &= PHY_REG_MASK;
1138                 reg_addr |= phy_page;
1139
1140                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1141                                                     reg_data);
1142                 if (ret_val)
1143                         goto out;
1144         }
1145
1146 out:
1147         hw->phy.ops.release(hw);
1148         return ret_val;
1149 }
1150
1151 /**
1152  *  e1000_k1_gig_workaround_hv - K1 Si workaround
1153  *  @hw:   pointer to the HW structure
1154  *  @link: link up bool flag
1155  *
1156  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1157  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
1158  *  If link is down, the function will restore the default K1 setting located
1159  *  in the NVM.
1160  **/
1161 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1162 {
1163         s32 ret_val = 0;
1164         u16 status_reg = 0;
1165         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1166
1167         if (hw->mac.type != e1000_pchlan)
1168                 goto out;
1169
1170         /* Wrap the whole flow with the sw flag */
1171         ret_val = hw->phy.ops.acquire(hw);
1172         if (ret_val)
1173                 goto out;
1174
1175         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1176         if (link) {
1177                 if (hw->phy.type == e1000_phy_82578) {
1178                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1179                                                                   &status_reg);
1180                         if (ret_val)
1181                                 goto release;
1182
1183                         status_reg &= BM_CS_STATUS_LINK_UP |
1184                                       BM_CS_STATUS_RESOLVED |
1185                                       BM_CS_STATUS_SPEED_MASK;
1186
1187                         if (status_reg == (BM_CS_STATUS_LINK_UP |
1188                                            BM_CS_STATUS_RESOLVED |
1189                                            BM_CS_STATUS_SPEED_1000))
1190                                 k1_enable = false;
1191                 }
1192
1193                 if (hw->phy.type == e1000_phy_82577) {
1194                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1195                                                                   &status_reg);
1196                         if (ret_val)
1197                                 goto release;
1198
1199                         status_reg &= HV_M_STATUS_LINK_UP |
1200                                       HV_M_STATUS_AUTONEG_COMPLETE |
1201                                       HV_M_STATUS_SPEED_MASK;
1202
1203                         if (status_reg == (HV_M_STATUS_LINK_UP |
1204                                            HV_M_STATUS_AUTONEG_COMPLETE |
1205                                            HV_M_STATUS_SPEED_1000))
1206                                 k1_enable = false;
1207                 }
1208
1209                 /* Link stall fix for link up */
1210                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1211                                                            0x0100);
1212                 if (ret_val)
1213                         goto release;
1214
1215         } else {
1216                 /* Link stall fix for link down */
1217                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1218                                                            0x4100);
1219                 if (ret_val)
1220                         goto release;
1221         }
1222
1223         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1224
1225 release:
1226         hw->phy.ops.release(hw);
1227 out:
1228         return ret_val;
1229 }
1230
1231 /**
1232  *  e1000_configure_k1_ich8lan - Configure K1 power state
1233  *  @hw: pointer to the HW structure
1234  *  @enable: K1 state to configure
1235  *
1236  *  Configure the K1 power state based on the provided parameter.
1237  *  Assumes semaphore already acquired.
1238  *
1239  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1240  **/
1241 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1242 {
1243         s32 ret_val = 0;
1244         u32 ctrl_reg = 0;
1245         u32 ctrl_ext = 0;
1246         u32 reg = 0;
1247         u16 kmrn_reg = 0;
1248
1249         ret_val = e1000e_read_kmrn_reg_locked(hw,
1250                                              E1000_KMRNCTRLSTA_K1_CONFIG,
1251                                              &kmrn_reg);
1252         if (ret_val)
1253                 goto out;
1254
1255         if (k1_enable)
1256                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1257         else
1258                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1259
1260         ret_val = e1000e_write_kmrn_reg_locked(hw,
1261                                               E1000_KMRNCTRLSTA_K1_CONFIG,
1262                                               kmrn_reg);
1263         if (ret_val)
1264                 goto out;
1265
1266         udelay(20);
1267         ctrl_ext = er32(CTRL_EXT);
1268         ctrl_reg = er32(CTRL);
1269
1270         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1271         reg |= E1000_CTRL_FRCSPD;
1272         ew32(CTRL, reg);
1273
1274         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1275         e1e_flush();
1276         udelay(20);
1277         ew32(CTRL, ctrl_reg);
1278         ew32(CTRL_EXT, ctrl_ext);
1279         e1e_flush();
1280         udelay(20);
1281
1282 out:
1283         return ret_val;
1284 }
1285
1286 /**
1287  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1288  *  @hw:       pointer to the HW structure
1289  *  @d0_state: boolean if entering d0 or d3 device state
1290  *
1291  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1292  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1293  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1294  **/
1295 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1296 {
1297         s32 ret_val = 0;
1298         u32 mac_reg;
1299         u16 oem_reg;
1300
1301         if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
1302                 return ret_val;
1303
1304         ret_val = hw->phy.ops.acquire(hw);
1305         if (ret_val)
1306                 return ret_val;
1307
1308         if (!(hw->mac.type == e1000_pch2lan)) {
1309                 mac_reg = er32(EXTCNF_CTRL);
1310                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1311                         goto out;
1312         }
1313
1314         mac_reg = er32(FEXTNVM);
1315         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1316                 goto out;
1317
1318         mac_reg = er32(PHY_CTRL);
1319
1320         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1321         if (ret_val)
1322                 goto out;
1323
1324         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1325
1326         if (d0_state) {
1327                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1328                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1329
1330                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1331                         oem_reg |= HV_OEM_BITS_LPLU;
1332
1333                 /* Set Restart auto-neg to activate the bits */
1334                 if (!e1000_check_reset_block(hw))
1335                         oem_reg |= HV_OEM_BITS_RESTART_AN;
1336         } else {
1337                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
1338                                E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
1339                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1340
1341                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
1342                                E1000_PHY_CTRL_NOND0A_LPLU))
1343                         oem_reg |= HV_OEM_BITS_LPLU;
1344         }
1345
1346         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1347
1348 out:
1349         hw->phy.ops.release(hw);
1350
1351         return ret_val;
1352 }
1353
1354
1355 /**
1356  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1357  *  @hw:   pointer to the HW structure
1358  **/
1359 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1360 {
1361         s32 ret_val;
1362         u16 data;
1363
1364         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1365         if (ret_val)
1366                 return ret_val;
1367
1368         data |= HV_KMRN_MDIO_SLOW;
1369
1370         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1371
1372         return ret_val;
1373 }
1374
1375 /**
1376  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1377  *  done after every PHY reset.
1378  **/
1379 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1380 {
1381         s32 ret_val = 0;
1382         u16 phy_data;
1383
1384         if (hw->mac.type != e1000_pchlan)
1385                 return ret_val;
1386
1387         /* Set MDIO slow mode before any other MDIO access */
1388         if (hw->phy.type == e1000_phy_82577) {
1389                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1390                 if (ret_val)
1391                         goto out;
1392         }
1393
1394         if (((hw->phy.type == e1000_phy_82577) &&
1395              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1396             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1397                 /* Disable generation of early preamble */
1398                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1399                 if (ret_val)
1400                         return ret_val;
1401
1402                 /* Preamble tuning for SSC */
1403                 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
1404                 if (ret_val)
1405                         return ret_val;
1406         }
1407
1408         if (hw->phy.type == e1000_phy_82578) {
1409                 /*
1410                  * Return registers to default by doing a soft reset then
1411                  * writing 0x3140 to the control register.
1412                  */
1413                 if (hw->phy.revision < 2) {
1414                         e1000e_phy_sw_reset(hw);
1415                         ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1416                 }
1417         }
1418
1419         /* Select page 0 */
1420         ret_val = hw->phy.ops.acquire(hw);
1421         if (ret_val)
1422                 return ret_val;
1423
1424         hw->phy.addr = 1;
1425         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1426         hw->phy.ops.release(hw);
1427         if (ret_val)
1428                 goto out;
1429
1430         /*
1431          * Configure the K1 Si workaround during phy reset assuming there is
1432          * link so that it disables K1 if link is in 1Gbps.
1433          */
1434         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1435         if (ret_val)
1436                 goto out;
1437
1438         /* Workaround for link disconnects on a busy hub in half duplex */
1439         ret_val = hw->phy.ops.acquire(hw);
1440         if (ret_val)
1441                 goto out;
1442         ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
1443         if (ret_val)
1444                 goto release;
1445         ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
1446                                                phy_data & 0x00FF);
1447 release:
1448         hw->phy.ops.release(hw);
1449 out:
1450         return ret_val;
1451 }
1452
1453 /**
1454  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1455  *  @hw:   pointer to the HW structure
1456  **/
1457 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1458 {
1459         u32 mac_reg;
1460         u16 i, phy_reg = 0;
1461         s32 ret_val;
1462
1463         ret_val = hw->phy.ops.acquire(hw);
1464         if (ret_val)
1465                 return;
1466         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1467         if (ret_val)
1468                 goto release;
1469
1470         /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1471         for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1472                 mac_reg = er32(RAL(i));
1473                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
1474                                            (u16)(mac_reg & 0xFFFF));
1475                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
1476                                            (u16)((mac_reg >> 16) & 0xFFFF));
1477
1478                 mac_reg = er32(RAH(i));
1479                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
1480                                            (u16)(mac_reg & 0xFFFF));
1481                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
1482                                            (u16)((mac_reg & E1000_RAH_AV)
1483                                                  >> 16));
1484         }
1485
1486         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1487
1488 release:
1489         hw->phy.ops.release(hw);
1490 }
1491
1492 /**
1493  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1494  *  with 82579 PHY
1495  *  @hw: pointer to the HW structure
1496  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
1497  **/
1498 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1499 {
1500         s32 ret_val = 0;
1501         u16 phy_reg, data;
1502         u32 mac_reg;
1503         u16 i;
1504
1505         if (hw->mac.type != e1000_pch2lan)
1506                 goto out;
1507
1508         /* disable Rx path while enabling/disabling workaround */
1509         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1510         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1511         if (ret_val)
1512                 goto out;
1513
1514         if (enable) {
1515                 /*
1516                  * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1517                  * SHRAL/H) and initial CRC values to the MAC
1518                  */
1519                 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1520                         u8 mac_addr[ETH_ALEN] = {0};
1521                         u32 addr_high, addr_low;
1522
1523                         addr_high = er32(RAH(i));
1524                         if (!(addr_high & E1000_RAH_AV))
1525                                 continue;
1526                         addr_low = er32(RAL(i));
1527                         mac_addr[0] = (addr_low & 0xFF);
1528                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
1529                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
1530                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
1531                         mac_addr[4] = (addr_high & 0xFF);
1532                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
1533
1534                         ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
1535                 }
1536
1537                 /* Write Rx addresses to the PHY */
1538                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1539
1540                 /* Enable jumbo frame workaround in the MAC */
1541                 mac_reg = er32(FFLT_DBG);
1542                 mac_reg &= ~(1 << 14);
1543                 mac_reg |= (7 << 15);
1544                 ew32(FFLT_DBG, mac_reg);
1545
1546                 mac_reg = er32(RCTL);
1547                 mac_reg |= E1000_RCTL_SECRC;
1548                 ew32(RCTL, mac_reg);
1549
1550                 ret_val = e1000e_read_kmrn_reg(hw,
1551                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1552                                                 &data);
1553                 if (ret_val)
1554                         goto out;
1555                 ret_val = e1000e_write_kmrn_reg(hw,
1556                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1557                                                 data | (1 << 0));
1558                 if (ret_val)
1559                         goto out;
1560                 ret_val = e1000e_read_kmrn_reg(hw,
1561                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1562                                                 &data);
1563                 if (ret_val)
1564                         goto out;
1565                 data &= ~(0xF << 8);
1566                 data |= (0xB << 8);
1567                 ret_val = e1000e_write_kmrn_reg(hw,
1568                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1569                                                 data);
1570                 if (ret_val)
1571                         goto out;
1572
1573                 /* Enable jumbo frame workaround in the PHY */
1574                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1575                 data &= ~(0x7F << 5);
1576                 data |= (0x37 << 5);
1577                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1578                 if (ret_val)
1579                         goto out;
1580                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1581                 data &= ~(1 << 13);
1582                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1583                 if (ret_val)
1584                         goto out;
1585                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1586                 data &= ~(0x3FF << 2);
1587                 data |= (0x1A << 2);
1588                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1589                 if (ret_val)
1590                         goto out;
1591                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
1592                 if (ret_val)
1593                         goto out;
1594                 e1e_rphy(hw, HV_PM_CTRL, &data);
1595                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1596                 if (ret_val)
1597                         goto out;
1598         } else {
1599                 /* Write MAC register values back to h/w defaults */
1600                 mac_reg = er32(FFLT_DBG);
1601                 mac_reg &= ~(0xF << 14);
1602                 ew32(FFLT_DBG, mac_reg);
1603
1604                 mac_reg = er32(RCTL);
1605                 mac_reg &= ~E1000_RCTL_SECRC;
1606                 ew32(RCTL, mac_reg);
1607
1608                 ret_val = e1000e_read_kmrn_reg(hw,
1609                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1610                                                 &data);
1611                 if (ret_val)
1612                         goto out;
1613                 ret_val = e1000e_write_kmrn_reg(hw,
1614                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1615                                                 data & ~(1 << 0));
1616                 if (ret_val)
1617                         goto out;
1618                 ret_val = e1000e_read_kmrn_reg(hw,
1619                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1620                                                 &data);
1621                 if (ret_val)
1622                         goto out;
1623                 data &= ~(0xF << 8);
1624                 data |= (0xB << 8);
1625                 ret_val = e1000e_write_kmrn_reg(hw,
1626                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1627                                                 data);
1628                 if (ret_val)
1629                         goto out;
1630
1631                 /* Write PHY register values back to h/w defaults */
1632                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1633                 data &= ~(0x7F << 5);
1634                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1635                 if (ret_val)
1636                         goto out;
1637                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1638                 data |= (1 << 13);
1639                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1640                 if (ret_val)
1641                         goto out;
1642                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1643                 data &= ~(0x3FF << 2);
1644                 data |= (0x8 << 2);
1645                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1646                 if (ret_val)
1647                         goto out;
1648                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1649                 if (ret_val)
1650                         goto out;
1651                 e1e_rphy(hw, HV_PM_CTRL, &data);
1652                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1653                 if (ret_val)
1654                         goto out;
1655         }
1656
1657         /* re-enable Rx path after enabling/disabling workaround */
1658         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1659
1660 out:
1661         return ret_val;
1662 }
1663
1664 /**
1665  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1666  *  done after every PHY reset.
1667  **/
1668 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1669 {
1670         s32 ret_val = 0;
1671
1672         if (hw->mac.type != e1000_pch2lan)
1673                 goto out;
1674
1675         /* Set MDIO slow mode before any other MDIO access */
1676         ret_val = e1000_set_mdio_slow_mode_hv(hw);
1677
1678 out:
1679         return ret_val;
1680 }
1681
1682 /**
1683  *  e1000_k1_gig_workaround_lv - K1 Si workaround
1684  *  @hw:   pointer to the HW structure
1685  *
1686  *  Workaround to set the K1 beacon duration for 82579 parts
1687  **/
1688 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
1689 {
1690         s32 ret_val = 0;
1691         u16 status_reg = 0;
1692         u32 mac_reg;
1693         u16 phy_reg;
1694
1695         if (hw->mac.type != e1000_pch2lan)
1696                 goto out;
1697
1698         /* Set K1 beacon duration based on 1Gbps speed or otherwise */
1699         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
1700         if (ret_val)
1701                 goto out;
1702
1703         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
1704             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
1705                 mac_reg = er32(FEXTNVM4);
1706                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1707
1708                 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
1709                 if (ret_val)
1710                         goto out;
1711
1712                 if (status_reg & HV_M_STATUS_SPEED_1000) {
1713                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1714                         phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
1715                 } else {
1716                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
1717                         phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
1718                 }
1719                 ew32(FEXTNVM4, mac_reg);
1720                 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
1721         }
1722
1723 out:
1724         return ret_val;
1725 }
1726
1727 /**
1728  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
1729  *  @hw:   pointer to the HW structure
1730  *  @gate: boolean set to true to gate, false to ungate
1731  *
1732  *  Gate/ungate the automatic PHY configuration via hardware; perform
1733  *  the configuration via software instead.
1734  **/
1735 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
1736 {
1737         u32 extcnf_ctrl;
1738
1739         if (hw->mac.type != e1000_pch2lan)
1740                 return;
1741
1742         extcnf_ctrl = er32(EXTCNF_CTRL);
1743
1744         if (gate)
1745                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1746         else
1747                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1748
1749         ew32(EXTCNF_CTRL, extcnf_ctrl);
1750         return;
1751 }
1752
1753 /**
1754  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
1755  *  @hw: pointer to the HW structure
1756  *
1757  *  Check the appropriate indication the MAC has finished configuring the
1758  *  PHY after a software reset.
1759  **/
1760 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1761 {
1762         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1763
1764         /* Wait for basic configuration completes before proceeding */
1765         do {
1766                 data = er32(STATUS);
1767                 data &= E1000_STATUS_LAN_INIT_DONE;
1768                 udelay(100);
1769         } while ((!data) && --loop);
1770
1771         /*
1772          * If basic configuration is incomplete before the above loop
1773          * count reaches 0, loading the configuration from NVM will
1774          * leave the PHY in a bad state possibly resulting in no link.
1775          */
1776         if (loop == 0)
1777                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1778
1779         /* Clear the Init Done bit for the next init event */
1780         data = er32(STATUS);
1781         data &= ~E1000_STATUS_LAN_INIT_DONE;
1782         ew32(STATUS, data);
1783 }
1784
1785 /**
1786  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
1787  *  @hw: pointer to the HW structure
1788  **/
1789 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
1790 {
1791         s32 ret_val = 0;
1792         u16 reg;
1793
1794         if (e1000_check_reset_block(hw))
1795                 goto out;
1796
1797         /* Allow time for h/w to get to quiescent state after reset */
1798         usleep_range(10000, 20000);
1799
1800         /* Perform any necessary post-reset workarounds */
1801         switch (hw->mac.type) {
1802         case e1000_pchlan:
1803                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1804                 if (ret_val)
1805                         goto out;
1806                 break;
1807         case e1000_pch2lan:
1808                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1809                 if (ret_val)
1810                         goto out;
1811                 break;
1812         default:
1813                 break;
1814         }
1815
1816         /* Clear the host wakeup bit after lcd reset */
1817         if (hw->mac.type >= e1000_pchlan) {
1818                 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
1819                 reg &= ~BM_WUC_HOST_WU_BIT;
1820                 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
1821         }
1822
1823         /* Configure the LCD with the extended configuration region in NVM */
1824         ret_val = e1000_sw_lcd_config_ich8lan(hw);
1825         if (ret_val)
1826                 goto out;
1827
1828         /* Configure the LCD with the OEM bits in NVM */
1829         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1830
1831         if (hw->mac.type == e1000_pch2lan) {
1832                 /* Ungate automatic PHY configuration on non-managed 82579 */
1833                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
1834                         usleep_range(10000, 20000);
1835                         e1000_gate_hw_phy_config_ich8lan(hw, false);
1836                 }
1837
1838                 /* Set EEE LPI Update Timer to 200usec */
1839                 ret_val = hw->phy.ops.acquire(hw);
1840                 if (ret_val)
1841                         goto out;
1842                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
1843                                                        I82579_LPI_UPDATE_TIMER);
1844                 if (ret_val)
1845                         goto release;
1846                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
1847                                                        0x1387);
1848 release:
1849                 hw->phy.ops.release(hw);
1850         }
1851
1852 out:
1853         return ret_val;
1854 }
1855
1856 /**
1857  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1858  *  @hw: pointer to the HW structure
1859  *
1860  *  Resets the PHY
1861  *  This is a function pointer entry point called by drivers
1862  *  or other shared routines.
1863  **/
1864 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1865 {
1866         s32 ret_val = 0;
1867
1868         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
1869         if ((hw->mac.type == e1000_pch2lan) &&
1870             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1871                 e1000_gate_hw_phy_config_ich8lan(hw, true);
1872
1873         ret_val = e1000e_phy_hw_reset_generic(hw);
1874         if (ret_val)
1875                 goto out;
1876
1877         ret_val = e1000_post_phy_reset_ich8lan(hw);
1878
1879 out:
1880         return ret_val;
1881 }
1882
1883 /**
1884  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1885  *  @hw: pointer to the HW structure
1886  *  @active: true to enable LPLU, false to disable
1887  *
1888  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
1889  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1890  *  the phy speed. This function will manually set the LPLU bit and restart
1891  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
1892  *  since it configures the same bit.
1893  **/
1894 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1895 {
1896         s32 ret_val = 0;
1897         u16 oem_reg;
1898
1899         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1900         if (ret_val)
1901                 goto out;
1902
1903         if (active)
1904                 oem_reg |= HV_OEM_BITS_LPLU;
1905         else
1906                 oem_reg &= ~HV_OEM_BITS_LPLU;
1907
1908         oem_reg |= HV_OEM_BITS_RESTART_AN;
1909         ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1910
1911 out:
1912         return ret_val;
1913 }
1914
1915 /**
1916  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1917  *  @hw: pointer to the HW structure
1918  *  @active: true to enable LPLU, false to disable
1919  *
1920  *  Sets the LPLU D0 state according to the active flag.  When
1921  *  activating LPLU this function also disables smart speed
1922  *  and vice versa.  LPLU will not be activated unless the
1923  *  device autonegotiation advertisement meets standards of
1924  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1925  *  This is a function pointer entry point only called by
1926  *  PHY setup routines.
1927  **/
1928 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1929 {
1930         struct e1000_phy_info *phy = &hw->phy;
1931         u32 phy_ctrl;
1932         s32 ret_val = 0;
1933         u16 data;
1934
1935         if (phy->type == e1000_phy_ife)
1936                 return ret_val;
1937
1938         phy_ctrl = er32(PHY_CTRL);
1939
1940         if (active) {
1941                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1942                 ew32(PHY_CTRL, phy_ctrl);
1943
1944                 if (phy->type != e1000_phy_igp_3)
1945                         return 0;
1946
1947                 /*
1948                  * Call gig speed drop workaround on LPLU before accessing
1949                  * any PHY registers
1950                  */
1951                 if (hw->mac.type == e1000_ich8lan)
1952                         e1000e_gig_downshift_workaround_ich8lan(hw);
1953
1954                 /* When LPLU is enabled, we should disable SmartSpeed */
1955                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1956                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1957                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1958                 if (ret_val)
1959                         return ret_val;
1960         } else {
1961                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1962                 ew32(PHY_CTRL, phy_ctrl);
1963
1964                 if (phy->type != e1000_phy_igp_3)
1965                         return 0;
1966
1967                 /*
1968                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1969                  * during Dx states where the power conservation is most
1970                  * important.  During driver activity we should enable
1971                  * SmartSpeed, so performance is maintained.
1972                  */
1973                 if (phy->smart_speed == e1000_smart_speed_on) {
1974                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1975                                            &data);
1976                         if (ret_val)
1977                                 return ret_val;
1978
1979                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1980                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1981                                            data);
1982                         if (ret_val)
1983                                 return ret_val;
1984                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1985                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1986                                            &data);
1987                         if (ret_val)
1988                                 return ret_val;
1989
1990                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1991                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1992                                            data);
1993                         if (ret_val)
1994                                 return ret_val;
1995                 }
1996         }
1997
1998         return 0;
1999 }
2000
2001 /**
2002  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
2003  *  @hw: pointer to the HW structure
2004  *  @active: true to enable LPLU, false to disable
2005  *
2006  *  Sets the LPLU D3 state according to the active flag.  When
2007  *  activating LPLU this function also disables smart speed
2008  *  and vice versa.  LPLU will not be activated unless the
2009  *  device autonegotiation advertisement meets standards of
2010  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2011  *  This is a function pointer entry point only called by
2012  *  PHY setup routines.
2013  **/
2014 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2015 {
2016         struct e1000_phy_info *phy = &hw->phy;
2017         u32 phy_ctrl;
2018         s32 ret_val;
2019         u16 data;
2020
2021         phy_ctrl = er32(PHY_CTRL);
2022
2023         if (!active) {
2024                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2025                 ew32(PHY_CTRL, phy_ctrl);
2026
2027                 if (phy->type != e1000_phy_igp_3)
2028                         return 0;
2029
2030                 /*
2031                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2032                  * during Dx states where the power conservation is most
2033                  * important.  During driver activity we should enable
2034                  * SmartSpeed, so performance is maintained.
2035                  */
2036                 if (phy->smart_speed == e1000_smart_speed_on) {
2037                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2038                                            &data);
2039                         if (ret_val)
2040                                 return ret_val;
2041
2042                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2043                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2044                                            data);
2045                         if (ret_val)
2046                                 return ret_val;
2047                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2048                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2049                                            &data);
2050                         if (ret_val)
2051                                 return ret_val;
2052
2053                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2054                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2055                                            data);
2056                         if (ret_val)
2057                                 return ret_val;
2058                 }
2059         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2060                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2061                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2062                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2063                 ew32(PHY_CTRL, phy_ctrl);
2064
2065                 if (phy->type != e1000_phy_igp_3)
2066                         return 0;
2067
2068                 /*
2069                  * Call gig speed drop workaround on LPLU before accessing
2070                  * any PHY registers
2071                  */
2072                 if (hw->mac.type == e1000_ich8lan)
2073                         e1000e_gig_downshift_workaround_ich8lan(hw);
2074
2075                 /* When LPLU is enabled, we should disable SmartSpeed */
2076                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2077                 if (ret_val)
2078                         return ret_val;
2079
2080                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2081                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2082         }
2083
2084         return 0;
2085 }
2086
2087 /**
2088  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2089  *  @hw: pointer to the HW structure
2090  *  @bank:  pointer to the variable that returns the active bank
2091  *
2092  *  Reads signature byte from the NVM using the flash access registers.
2093  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2094  **/
2095 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2096 {
2097         u32 eecd;
2098         struct e1000_nvm_info *nvm = &hw->nvm;
2099         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2100         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2101         u8 sig_byte = 0;
2102         s32 ret_val = 0;
2103
2104         switch (hw->mac.type) {
2105         case e1000_ich8lan:
2106         case e1000_ich9lan:
2107                 eecd = er32(EECD);
2108                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2109                     E1000_EECD_SEC1VAL_VALID_MASK) {
2110                         if (eecd & E1000_EECD_SEC1VAL)
2111                                 *bank = 1;
2112                         else
2113                                 *bank = 0;
2114
2115                         return 0;
2116                 }
2117                 e_dbg("Unable to determine valid NVM bank via EEC - "
2118                        "reading flash signature\n");
2119                 /* fall-thru */
2120         default:
2121                 /* set bank to 0 in case flash read fails */
2122                 *bank = 0;
2123
2124                 /* Check bank 0 */
2125                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2126                                                         &sig_byte);
2127                 if (ret_val)
2128                         return ret_val;
2129                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2130                     E1000_ICH_NVM_SIG_VALUE) {
2131                         *bank = 0;
2132                         return 0;
2133                 }
2134
2135                 /* Check bank 1 */
2136                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2137                                                         bank1_offset,
2138                                                         &sig_byte);
2139                 if (ret_val)
2140                         return ret_val;
2141                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2142                     E1000_ICH_NVM_SIG_VALUE) {
2143                         *bank = 1;
2144                         return 0;
2145                 }
2146
2147                 e_dbg("ERROR: No valid NVM bank present\n");
2148                 return -E1000_ERR_NVM;
2149         }
2150
2151         return 0;
2152 }
2153
2154 /**
2155  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
2156  *  @hw: pointer to the HW structure
2157  *  @offset: The offset (in bytes) of the word(s) to read.
2158  *  @words: Size of data to read in words
2159  *  @data: Pointer to the word(s) to read at offset.
2160  *
2161  *  Reads a word(s) from the NVM using the flash access registers.
2162  **/
2163 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2164                                   u16 *data)
2165 {
2166         struct e1000_nvm_info *nvm = &hw->nvm;
2167         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2168         u32 act_offset;
2169         s32 ret_val = 0;
2170         u32 bank = 0;
2171         u16 i, word;
2172
2173         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2174             (words == 0)) {
2175                 e_dbg("nvm parameter(s) out of bounds\n");
2176                 ret_val = -E1000_ERR_NVM;
2177                 goto out;
2178         }
2179
2180         nvm->ops.acquire(hw);
2181
2182         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2183         if (ret_val) {
2184                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2185                 bank = 0;
2186         }
2187
2188         act_offset = (bank) ? nvm->flash_bank_size : 0;
2189         act_offset += offset;
2190
2191         ret_val = 0;
2192         for (i = 0; i < words; i++) {
2193                 if (dev_spec->shadow_ram[offset+i].modified) {
2194                         data[i] = dev_spec->shadow_ram[offset+i].value;
2195                 } else {
2196                         ret_val = e1000_read_flash_word_ich8lan(hw,
2197                                                                 act_offset + i,
2198                                                                 &word);
2199                         if (ret_val)
2200                                 break;
2201                         data[i] = word;
2202                 }
2203         }
2204
2205         nvm->ops.release(hw);
2206
2207 out:
2208         if (ret_val)
2209                 e_dbg("NVM read error: %d\n", ret_val);
2210
2211         return ret_val;
2212 }
2213
2214 /**
2215  *  e1000_flash_cycle_init_ich8lan - Initialize flash
2216  *  @hw: pointer to the HW structure
2217  *
2218  *  This function does initial flash setup so that a new read/write/erase cycle
2219  *  can be started.
2220  **/
2221 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2222 {
2223         union ich8_hws_flash_status hsfsts;
2224         s32 ret_val = -E1000_ERR_NVM;
2225
2226         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2227
2228         /* Check if the flash descriptor is valid */
2229         if (hsfsts.hsf_status.fldesvalid == 0) {
2230                 e_dbg("Flash descriptor invalid.  "
2231                          "SW Sequencing must be used.\n");
2232                 return -E1000_ERR_NVM;
2233         }
2234
2235         /* Clear FCERR and DAEL in hw status by writing 1 */
2236         hsfsts.hsf_status.flcerr = 1;
2237         hsfsts.hsf_status.dael = 1;
2238
2239         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2240
2241         /*
2242          * Either we should have a hardware SPI cycle in progress
2243          * bit to check against, in order to start a new cycle or
2244          * FDONE bit should be changed in the hardware so that it
2245          * is 1 after hardware reset, which can then be used as an
2246          * indication whether a cycle is in progress or has been
2247          * completed.
2248          */
2249
2250         if (hsfsts.hsf_status.flcinprog == 0) {
2251                 /*
2252                  * There is no cycle running at present,
2253                  * so we can start a cycle.
2254                  * Begin by setting Flash Cycle Done.
2255                  */
2256                 hsfsts.hsf_status.flcdone = 1;
2257                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2258                 ret_val = 0;
2259         } else {
2260                 s32 i = 0;
2261
2262                 /*
2263                  * Otherwise poll for sometime so the current
2264                  * cycle has a chance to end before giving up.
2265                  */
2266                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2267                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
2268                         if (hsfsts.hsf_status.flcinprog == 0) {
2269                                 ret_val = 0;
2270                                 break;
2271                         }
2272                         udelay(1);
2273                 }
2274                 if (ret_val == 0) {
2275                         /*
2276                          * Successful in waiting for previous cycle to timeout,
2277                          * now set the Flash Cycle Done.
2278                          */
2279                         hsfsts.hsf_status.flcdone = 1;
2280                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2281                 } else {
2282                         e_dbg("Flash controller busy, cannot get access\n");
2283                 }
2284         }
2285
2286         return ret_val;
2287 }
2288
2289 /**
2290  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2291  *  @hw: pointer to the HW structure
2292  *  @timeout: maximum time to wait for completion
2293  *
2294  *  This function starts a flash cycle and waits for its completion.
2295  **/
2296 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2297 {
2298         union ich8_hws_flash_ctrl hsflctl;
2299         union ich8_hws_flash_status hsfsts;
2300         s32 ret_val = -E1000_ERR_NVM;
2301         u32 i = 0;
2302
2303         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2304         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2305         hsflctl.hsf_ctrl.flcgo = 1;
2306         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2307
2308         /* wait till FDONE bit is set to 1 */
2309         do {
2310                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2311                 if (hsfsts.hsf_status.flcdone == 1)
2312                         break;
2313                 udelay(1);
2314         } while (i++ < timeout);
2315
2316         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
2317                 return 0;
2318
2319         return ret_val;
2320 }
2321
2322 /**
2323  *  e1000_read_flash_word_ich8lan - Read word from flash
2324  *  @hw: pointer to the HW structure
2325  *  @offset: offset to data location
2326  *  @data: pointer to the location for storing the data
2327  *
2328  *  Reads the flash word at offset into data.  Offset is converted
2329  *  to bytes before read.
2330  **/
2331 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2332                                          u16 *data)
2333 {
2334         /* Must convert offset into bytes. */
2335         offset <<= 1;
2336
2337         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2338 }
2339
2340 /**
2341  *  e1000_read_flash_byte_ich8lan - Read byte from flash
2342  *  @hw: pointer to the HW structure
2343  *  @offset: The offset of the byte to read.
2344  *  @data: Pointer to a byte to store the value read.
2345  *
2346  *  Reads a single byte from the NVM using the flash access registers.
2347  **/
2348 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2349                                          u8 *data)
2350 {
2351         s32 ret_val;
2352         u16 word = 0;
2353
2354         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2355         if (ret_val)
2356                 return ret_val;
2357
2358         *data = (u8)word;
2359
2360         return 0;
2361 }
2362
2363 /**
2364  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
2365  *  @hw: pointer to the HW structure
2366  *  @offset: The offset (in bytes) of the byte or word to read.
2367  *  @size: Size of data to read, 1=byte 2=word
2368  *  @data: Pointer to the word to store the value read.
2369  *
2370  *  Reads a byte or word from the NVM using the flash access registers.
2371  **/
2372 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2373                                          u8 size, u16 *data)
2374 {
2375         union ich8_hws_flash_status hsfsts;
2376         union ich8_hws_flash_ctrl hsflctl;
2377         u32 flash_linear_addr;
2378         u32 flash_data = 0;
2379         s32 ret_val = -E1000_ERR_NVM;
2380         u8 count = 0;
2381
2382         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2383                 return -E1000_ERR_NVM;
2384
2385         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2386                             hw->nvm.flash_base_addr;
2387
2388         do {
2389                 udelay(1);
2390                 /* Steps */
2391                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2392                 if (ret_val != 0)
2393                         break;
2394
2395                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2396                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2397                 hsflctl.hsf_ctrl.fldbcount = size - 1;
2398                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2399                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2400
2401                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2402
2403                 ret_val = e1000_flash_cycle_ich8lan(hw,
2404                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
2405
2406                 /*
2407                  * Check if FCERR is set to 1, if set to 1, clear it
2408                  * and try the whole sequence a few more times, else
2409                  * read in (shift in) the Flash Data0, the order is
2410                  * least significant byte first msb to lsb
2411                  */
2412                 if (ret_val == 0) {
2413                         flash_data = er32flash(ICH_FLASH_FDATA0);
2414                         if (size == 1)
2415                                 *data = (u8)(flash_data & 0x000000FF);
2416                         else if (size == 2)
2417                                 *data = (u16)(flash_data & 0x0000FFFF);
2418                         break;
2419                 } else {
2420                         /*
2421                          * If we've gotten here, then things are probably
2422                          * completely hosed, but if the error condition is
2423                          * detected, it won't hurt to give it another try...
2424                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2425                          */
2426                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2427                         if (hsfsts.hsf_status.flcerr == 1) {
2428                                 /* Repeat for some time before giving up. */
2429                                 continue;
2430                         } else if (hsfsts.hsf_status.flcdone == 0) {
2431                                 e_dbg("Timeout error - flash cycle "
2432                                          "did not complete.\n");
2433                                 break;
2434                         }
2435                 }
2436         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2437
2438         return ret_val;
2439 }
2440
2441 /**
2442  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
2443  *  @hw: pointer to the HW structure
2444  *  @offset: The offset (in bytes) of the word(s) to write.
2445  *  @words: Size of data to write in words
2446  *  @data: Pointer to the word(s) to write at offset.
2447  *
2448  *  Writes a byte or word to the NVM using the flash access registers.
2449  **/
2450 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2451                                    u16 *data)
2452 {
2453         struct e1000_nvm_info *nvm = &hw->nvm;
2454         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2455         u16 i;
2456
2457         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2458             (words == 0)) {
2459                 e_dbg("nvm parameter(s) out of bounds\n");
2460                 return -E1000_ERR_NVM;
2461         }
2462
2463         nvm->ops.acquire(hw);
2464
2465         for (i = 0; i < words; i++) {
2466                 dev_spec->shadow_ram[offset+i].modified = true;
2467                 dev_spec->shadow_ram[offset+i].value = data[i];
2468         }
2469
2470         nvm->ops.release(hw);
2471
2472         return 0;
2473 }
2474
2475 /**
2476  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2477  *  @hw: pointer to the HW structure
2478  *
2479  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
2480  *  which writes the checksum to the shadow ram.  The changes in the shadow
2481  *  ram are then committed to the EEPROM by processing each bank at a time
2482  *  checking for the modified bit and writing only the pending changes.
2483  *  After a successful commit, the shadow ram is cleared and is ready for
2484  *  future writes.
2485  **/
2486 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2487 {
2488         struct e1000_nvm_info *nvm = &hw->nvm;
2489         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2490         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2491         s32 ret_val;
2492         u16 data;
2493
2494         ret_val = e1000e_update_nvm_checksum_generic(hw);
2495         if (ret_val)
2496                 goto out;
2497
2498         if (nvm->type != e1000_nvm_flash_sw)
2499                 goto out;
2500
2501         nvm->ops.acquire(hw);
2502
2503         /*
2504          * We're writing to the opposite bank so if we're on bank 1,
2505          * write to bank 0 etc.  We also need to erase the segment that
2506          * is going to be written
2507          */
2508         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2509         if (ret_val) {
2510                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2511                 bank = 0;
2512         }
2513
2514         if (bank == 0) {
2515                 new_bank_offset = nvm->flash_bank_size;
2516                 old_bank_offset = 0;
2517                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2518                 if (ret_val)
2519                         goto release;
2520         } else {
2521                 old_bank_offset = nvm->flash_bank_size;
2522                 new_bank_offset = 0;
2523                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2524                 if (ret_val)
2525                         goto release;
2526         }
2527
2528         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2529                 /*
2530                  * Determine whether to write the value stored
2531                  * in the other NVM bank or a modified value stored
2532                  * in the shadow RAM
2533                  */
2534                 if (dev_spec->shadow_ram[i].modified) {
2535                         data = dev_spec->shadow_ram[i].value;
2536                 } else {
2537                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
2538                                                                 old_bank_offset,
2539                                                                 &data);
2540                         if (ret_val)
2541                                 break;
2542                 }
2543
2544                 /*
2545                  * If the word is 0x13, then make sure the signature bits
2546                  * (15:14) are 11b until the commit has completed.
2547                  * This will allow us to write 10b which indicates the
2548                  * signature is valid.  We want to do this after the write
2549                  * has completed so that we don't mark the segment valid
2550                  * while the write is still in progress
2551                  */
2552                 if (i == E1000_ICH_NVM_SIG_WORD)
2553                         data |= E1000_ICH_NVM_SIG_MASK;
2554
2555                 /* Convert offset to bytes. */
2556                 act_offset = (i + new_bank_offset) << 1;
2557
2558                 udelay(100);
2559                 /* Write the bytes to the new bank. */
2560                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2561                                                                act_offset,
2562                                                                (u8)data);
2563                 if (ret_val)
2564                         break;
2565
2566                 udelay(100);
2567                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2568                                                           act_offset + 1,
2569                                                           (u8)(data >> 8));
2570                 if (ret_val)
2571                         break;
2572         }
2573
2574         /*
2575          * Don't bother writing the segment valid bits if sector
2576          * programming failed.
2577          */
2578         if (ret_val) {
2579                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2580                 e_dbg("Flash commit failed.\n");
2581                 goto release;
2582         }
2583
2584         /*
2585          * Finally validate the new segment by setting bit 15:14
2586          * to 10b in word 0x13 , this can be done without an
2587          * erase as well since these bits are 11 to start with
2588          * and we need to change bit 14 to 0b
2589          */
2590         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2591         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2592         if (ret_val)
2593                 goto release;
2594
2595         data &= 0xBFFF;
2596         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2597                                                        act_offset * 2 + 1,
2598                                                        (u8)(data >> 8));
2599         if (ret_val)
2600                 goto release;
2601
2602         /*
2603          * And invalidate the previously valid segment by setting
2604          * its signature word (0x13) high_byte to 0b. This can be
2605          * done without an erase because flash erase sets all bits
2606          * to 1's. We can write 1's to 0's without an erase
2607          */
2608         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2609         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2610         if (ret_val)
2611                 goto release;
2612
2613         /* Great!  Everything worked, we can now clear the cached entries. */
2614         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2615                 dev_spec->shadow_ram[i].modified = false;
2616                 dev_spec->shadow_ram[i].value = 0xFFFF;
2617         }
2618
2619 release:
2620         nvm->ops.release(hw);
2621
2622         /*
2623          * Reload the EEPROM, or else modifications will not appear
2624          * until after the next adapter reset.
2625          */
2626         if (!ret_val) {
2627                 e1000e_reload_nvm(hw);
2628                 usleep_range(10000, 20000);
2629         }
2630
2631 out:
2632         if (ret_val)
2633                 e_dbg("NVM update error: %d\n", ret_val);
2634
2635         return ret_val;
2636 }
2637
2638 /**
2639  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2640  *  @hw: pointer to the HW structure
2641  *
2642  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2643  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
2644  *  calculated, in which case we need to calculate the checksum and set bit 6.
2645  **/
2646 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2647 {
2648         s32 ret_val;
2649         u16 data;
2650
2651         /*
2652          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
2653          * needs to be fixed.  This bit is an indication that the NVM
2654          * was prepared by OEM software and did not calculate the
2655          * checksum...a likely scenario.
2656          */
2657         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2658         if (ret_val)
2659                 return ret_val;
2660
2661         if ((data & 0x40) == 0) {
2662                 data |= 0x40;
2663                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2664                 if (ret_val)
2665                         return ret_val;
2666                 ret_val = e1000e_update_nvm_checksum(hw);
2667                 if (ret_val)
2668                         return ret_val;
2669         }
2670
2671         return e1000e_validate_nvm_checksum_generic(hw);
2672 }
2673
2674 /**
2675  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2676  *  @hw: pointer to the HW structure
2677  *
2678  *  To prevent malicious write/erase of the NVM, set it to be read-only
2679  *  so that the hardware ignores all write/erase cycles of the NVM via
2680  *  the flash control registers.  The shadow-ram copy of the NVM will
2681  *  still be updated, however any updates to this copy will not stick
2682  *  across driver reloads.
2683  **/
2684 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2685 {
2686         struct e1000_nvm_info *nvm = &hw->nvm;
2687         union ich8_flash_protected_range pr0;
2688         union ich8_hws_flash_status hsfsts;
2689         u32 gfpreg;
2690
2691         nvm->ops.acquire(hw);
2692
2693         gfpreg = er32flash(ICH_FLASH_GFPREG);
2694
2695         /* Write-protect GbE Sector of NVM */
2696         pr0.regval = er32flash(ICH_FLASH_PR0);
2697         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2698         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2699         pr0.range.wpe = true;
2700         ew32flash(ICH_FLASH_PR0, pr0.regval);
2701
2702         /*
2703          * Lock down a subset of GbE Flash Control Registers, e.g.
2704          * PR0 to prevent the write-protection from being lifted.
2705          * Once FLOCKDN is set, the registers protected by it cannot
2706          * be written until FLOCKDN is cleared by a hardware reset.
2707          */
2708         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2709         hsfsts.hsf_status.flockdn = true;
2710         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2711
2712         nvm->ops.release(hw);
2713 }
2714
2715 /**
2716  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2717  *  @hw: pointer to the HW structure
2718  *  @offset: The offset (in bytes) of the byte/word to read.
2719  *  @size: Size of data to read, 1=byte 2=word
2720  *  @data: The byte(s) to write to the NVM.
2721  *
2722  *  Writes one/two bytes to the NVM using the flash access registers.
2723  **/
2724 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2725                                           u8 size, u16 data)
2726 {
2727         union ich8_hws_flash_status hsfsts;
2728         union ich8_hws_flash_ctrl hsflctl;
2729         u32 flash_linear_addr;
2730         u32 flash_data = 0;
2731         s32 ret_val;
2732         u8 count = 0;
2733
2734         if (size < 1 || size > 2 || data > size * 0xff ||
2735             offset > ICH_FLASH_LINEAR_ADDR_MASK)
2736                 return -E1000_ERR_NVM;
2737
2738         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2739                             hw->nvm.flash_base_addr;
2740
2741         do {
2742                 udelay(1);
2743                 /* Steps */
2744                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2745                 if (ret_val)
2746                         break;
2747
2748                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2749                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2750                 hsflctl.hsf_ctrl.fldbcount = size -1;
2751                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2752                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2753
2754                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2755
2756                 if (size == 1)
2757                         flash_data = (u32)data & 0x00FF;
2758                 else
2759                         flash_data = (u32)data;
2760
2761                 ew32flash(ICH_FLASH_FDATA0, flash_data);
2762
2763                 /*
2764                  * check if FCERR is set to 1 , if set to 1, clear it
2765                  * and try the whole sequence a few more times else done
2766                  */
2767                 ret_val = e1000_flash_cycle_ich8lan(hw,
2768                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2769                 if (!ret_val)
2770                         break;
2771
2772                 /*
2773                  * If we're here, then things are most likely
2774                  * completely hosed, but if the error condition
2775                  * is detected, it won't hurt to give it another
2776                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2777                  */
2778                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2779                 if (hsfsts.hsf_status.flcerr == 1)
2780                         /* Repeat for some time before giving up. */
2781                         continue;
2782                 if (hsfsts.hsf_status.flcdone == 0) {
2783                         e_dbg("Timeout error - flash cycle "
2784                                  "did not complete.");
2785                         break;
2786                 }
2787         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2788
2789         return ret_val;
2790 }
2791
2792 /**
2793  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2794  *  @hw: pointer to the HW structure
2795  *  @offset: The index of the byte to read.
2796  *  @data: The byte to write to the NVM.
2797  *
2798  *  Writes a single byte to the NVM using the flash access registers.
2799  **/
2800 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2801                                           u8 data)
2802 {
2803         u16 word = (u16)data;
2804
2805         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2806 }
2807
2808 /**
2809  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2810  *  @hw: pointer to the HW structure
2811  *  @offset: The offset of the byte to write.
2812  *  @byte: The byte to write to the NVM.
2813  *
2814  *  Writes a single byte to the NVM using the flash access registers.
2815  *  Goes through a retry algorithm before giving up.
2816  **/
2817 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2818                                                 u32 offset, u8 byte)
2819 {
2820         s32 ret_val;
2821         u16 program_retries;
2822
2823         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2824         if (!ret_val)
2825                 return ret_val;
2826
2827         for (program_retries = 0; program_retries < 100; program_retries++) {
2828                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2829                 udelay(100);
2830                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2831                 if (!ret_val)
2832                         break;
2833         }
2834         if (program_retries == 100)
2835                 return -E1000_ERR_NVM;
2836
2837         return 0;
2838 }
2839
2840 /**
2841  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2842  *  @hw: pointer to the HW structure
2843  *  @bank: 0 for first bank, 1 for second bank, etc.
2844  *
2845  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2846  *  bank N is 4096 * N + flash_reg_addr.
2847  **/
2848 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2849 {
2850         struct e1000_nvm_info *nvm = &hw->nvm;
2851         union ich8_hws_flash_status hsfsts;
2852         union ich8_hws_flash_ctrl hsflctl;
2853         u32 flash_linear_addr;
2854         /* bank size is in 16bit words - adjust to bytes */
2855         u32 flash_bank_size = nvm->flash_bank_size * 2;
2856         s32 ret_val;
2857         s32 count = 0;
2858         s32 j, iteration, sector_size;
2859
2860         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2861
2862         /*
2863          * Determine HW Sector size: Read BERASE bits of hw flash status
2864          * register
2865          * 00: The Hw sector is 256 bytes, hence we need to erase 16
2866          *     consecutive sectors.  The start index for the nth Hw sector
2867          *     can be calculated as = bank * 4096 + n * 256
2868          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2869          *     The start index for the nth Hw sector can be calculated
2870          *     as = bank * 4096
2871          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2872          *     (ich9 only, otherwise error condition)
2873          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2874          */
2875         switch (hsfsts.hsf_status.berasesz) {
2876         case 0:
2877                 /* Hw sector size 256 */
2878                 sector_size = ICH_FLASH_SEG_SIZE_256;
2879                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2880                 break;
2881         case 1:
2882                 sector_size = ICH_FLASH_SEG_SIZE_4K;
2883                 iteration = 1;
2884                 break;
2885         case 2:
2886                 sector_size = ICH_FLASH_SEG_SIZE_8K;
2887                 iteration = 1;
2888                 break;
2889         case 3:
2890                 sector_size = ICH_FLASH_SEG_SIZE_64K;
2891                 iteration = 1;
2892                 break;
2893         default:
2894                 return -E1000_ERR_NVM;
2895         }
2896
2897         /* Start with the base address, then add the sector offset. */
2898         flash_linear_addr = hw->nvm.flash_base_addr;
2899         flash_linear_addr += (bank) ? flash_bank_size : 0;
2900
2901         for (j = 0; j < iteration ; j++) {
2902                 do {
2903                         /* Steps */
2904                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
2905                         if (ret_val)
2906                                 return ret_val;
2907
2908                         /*
2909                          * Write a value 11 (block Erase) in Flash
2910                          * Cycle field in hw flash control
2911                          */
2912                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2913                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2914                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2915
2916                         /*
2917                          * Write the last 24 bits of an index within the
2918                          * block into Flash Linear address field in Flash
2919                          * Address.
2920                          */
2921                         flash_linear_addr += (j * sector_size);
2922                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2923
2924                         ret_val = e1000_flash_cycle_ich8lan(hw,
2925                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2926                         if (ret_val == 0)
2927                                 break;
2928
2929                         /*
2930                          * Check if FCERR is set to 1.  If 1,
2931                          * clear it and try the whole sequence
2932                          * a few more times else Done
2933                          */
2934                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2935                         if (hsfsts.hsf_status.flcerr == 1)
2936                                 /* repeat for some time before giving up */
2937                                 continue;
2938                         else if (hsfsts.hsf_status.flcdone == 0)
2939                                 return ret_val;
2940                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2941         }
2942
2943         return 0;
2944 }
2945
2946 /**
2947  *  e1000_valid_led_default_ich8lan - Set the default LED settings
2948  *  @hw: pointer to the HW structure
2949  *  @data: Pointer to the LED settings
2950  *
2951  *  Reads the LED default settings from the NVM to data.  If the NVM LED
2952  *  settings is all 0's or F's, set the LED default to a valid LED default
2953  *  setting.
2954  **/
2955 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2956 {
2957         s32 ret_val;
2958
2959         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2960         if (ret_val) {
2961                 e_dbg("NVM Read Error\n");
2962                 return ret_val;
2963         }
2964
2965         if (*data == ID_LED_RESERVED_0000 ||
2966             *data == ID_LED_RESERVED_FFFF)
2967                 *data = ID_LED_DEFAULT_ICH8LAN;
2968
2969         return 0;
2970 }
2971
2972 /**
2973  *  e1000_id_led_init_pchlan - store LED configurations
2974  *  @hw: pointer to the HW structure
2975  *
2976  *  PCH does not control LEDs via the LEDCTL register, rather it uses
2977  *  the PHY LED configuration register.
2978  *
2979  *  PCH also does not have an "always on" or "always off" mode which
2980  *  complicates the ID feature.  Instead of using the "on" mode to indicate
2981  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2982  *  use "link_up" mode.  The LEDs will still ID on request if there is no
2983  *  link based on logic in e1000_led_[on|off]_pchlan().
2984  **/
2985 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2986 {
2987         struct e1000_mac_info *mac = &hw->mac;
2988         s32 ret_val;
2989         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2990         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2991         u16 data, i, temp, shift;
2992
2993         /* Get default ID LED modes */
2994         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2995         if (ret_val)
2996                 goto out;
2997
2998         mac->ledctl_default = er32(LEDCTL);
2999         mac->ledctl_mode1 = mac->ledctl_default;
3000         mac->ledctl_mode2 = mac->ledctl_default;
3001
3002         for (i = 0; i < 4; i++) {
3003                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
3004                 shift = (i * 5);
3005                 switch (temp) {
3006                 case ID_LED_ON1_DEF2:
3007                 case ID_LED_ON1_ON2:
3008                 case ID_LED_ON1_OFF2:
3009                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3010                         mac->ledctl_mode1 |= (ledctl_on << shift);
3011                         break;
3012                 case ID_LED_OFF1_DEF2:
3013                 case ID_LED_OFF1_ON2:
3014                 case ID_LED_OFF1_OFF2:
3015                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3016                         mac->ledctl_mode1 |= (ledctl_off << shift);
3017                         break;
3018                 default:
3019                         /* Do nothing */
3020                         break;
3021                 }
3022                 switch (temp) {
3023                 case ID_LED_DEF1_ON2:
3024                 case ID_LED_ON1_ON2:
3025                 case ID_LED_OFF1_ON2:
3026                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3027                         mac->ledctl_mode2 |= (ledctl_on << shift);
3028                         break;
3029                 case ID_LED_DEF1_OFF2:
3030                 case ID_LED_ON1_OFF2:
3031                 case ID_LED_OFF1_OFF2:
3032                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3033                         mac->ledctl_mode2 |= (ledctl_off << shift);
3034                         break;
3035                 default:
3036                         /* Do nothing */
3037                         break;
3038                 }
3039         }
3040
3041 out:
3042         return ret_val;
3043 }
3044
3045 /**
3046  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3047  *  @hw: pointer to the HW structure
3048  *
3049  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3050  *  register, so the the bus width is hard coded.
3051  **/
3052 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3053 {
3054         struct e1000_bus_info *bus = &hw->bus;
3055         s32 ret_val;
3056
3057         ret_val = e1000e_get_bus_info_pcie(hw);
3058
3059         /*
3060          * ICH devices are "PCI Express"-ish.  They have
3061          * a configuration space, but do not contain
3062          * PCI Express Capability registers, so bus width
3063          * must be hardcoded.
3064          */
3065         if (bus->width == e1000_bus_width_unknown)
3066                 bus->width = e1000_bus_width_pcie_x1;
3067
3068         return ret_val;
3069 }
3070
3071 /**
3072  *  e1000_reset_hw_ich8lan - Reset the hardware
3073  *  @hw: pointer to the HW structure
3074  *
3075  *  Does a full reset of the hardware which includes a reset of the PHY and
3076  *  MAC.
3077  **/
3078 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3079 {
3080         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3081         u16 reg;
3082         u32 ctrl, kab;
3083         s32 ret_val;
3084
3085         /*
3086          * Prevent the PCI-E bus from sticking if there is no TLP connection
3087          * on the last TLP read/write transaction when MAC is reset.
3088          */
3089         ret_val = e1000e_disable_pcie_master(hw);
3090         if (ret_val)
3091                 e_dbg("PCI-E Master disable polling has failed.\n");
3092
3093         e_dbg("Masking off all interrupts\n");
3094         ew32(IMC, 0xffffffff);
3095
3096         /*
3097          * Disable the Transmit and Receive units.  Then delay to allow
3098          * any pending transactions to complete before we hit the MAC
3099          * with the global reset.
3100          */
3101         ew32(RCTL, 0);
3102         ew32(TCTL, E1000_TCTL_PSP);
3103         e1e_flush();
3104
3105         usleep_range(10000, 20000);
3106
3107         /* Workaround for ICH8 bit corruption issue in FIFO memory */
3108         if (hw->mac.type == e1000_ich8lan) {
3109                 /* Set Tx and Rx buffer allocation to 8k apiece. */
3110                 ew32(PBA, E1000_PBA_8K);
3111                 /* Set Packet Buffer Size to 16k. */
3112                 ew32(PBS, E1000_PBS_16K);
3113         }
3114
3115         if (hw->mac.type == e1000_pchlan) {
3116                 /* Save the NVM K1 bit setting*/
3117                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
3118                 if (ret_val)
3119                         return ret_val;
3120
3121                 if (reg & E1000_NVM_K1_ENABLE)
3122                         dev_spec->nvm_k1_enabled = true;
3123                 else
3124                         dev_spec->nvm_k1_enabled = false;
3125         }
3126
3127         ctrl = er32(CTRL);
3128
3129         if (!e1000_check_reset_block(hw)) {
3130                 /*
3131                  * Full-chip reset requires MAC and PHY reset at the same
3132                  * time to make sure the interface between MAC and the
3133                  * external PHY is reset.
3134                  */
3135                 ctrl |= E1000_CTRL_PHY_RST;
3136
3137                 /*
3138                  * Gate automatic PHY configuration by hardware on
3139                  * non-managed 82579
3140                  */
3141                 if ((hw->mac.type == e1000_pch2lan) &&
3142                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3143                         e1000_gate_hw_phy_config_ich8lan(hw, true);
3144         }
3145         ret_val = e1000_acquire_swflag_ich8lan(hw);
3146         e_dbg("Issuing a global reset to ich8lan\n");
3147         ew32(CTRL, (ctrl | E1000_CTRL_RST));
3148         /* cannot issue a flush here because it hangs the hardware */
3149         msleep(20);
3150
3151         if (!ret_val)
3152                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
3153
3154         if (ctrl & E1000_CTRL_PHY_RST) {
3155                 ret_val = hw->phy.ops.get_cfg_done(hw);
3156                 if (ret_val)
3157                         goto out;
3158
3159                 ret_val = e1000_post_phy_reset_ich8lan(hw);
3160                 if (ret_val)
3161                         goto out;
3162         }
3163
3164         /*
3165          * For PCH, this write will make sure that any noise
3166          * will be detected as a CRC error and be dropped rather than show up
3167          * as a bad packet to the DMA engine.
3168          */
3169         if (hw->mac.type == e1000_pchlan)
3170                 ew32(CRC_OFFSET, 0x65656565);
3171
3172         ew32(IMC, 0xffffffff);
3173         er32(ICR);
3174
3175         kab = er32(KABGTXD);
3176         kab |= E1000_KABGTXD_BGSQLBIAS;
3177         ew32(KABGTXD, kab);
3178
3179 out:
3180         return ret_val;
3181 }
3182
3183 /**
3184  *  e1000_init_hw_ich8lan - Initialize the hardware
3185  *  @hw: pointer to the HW structure
3186  *
3187  *  Prepares the hardware for transmit and receive by doing the following:
3188  *   - initialize hardware bits
3189  *   - initialize LED identification
3190  *   - setup receive address registers
3191  *   - setup flow control
3192  *   - setup transmit descriptors
3193  *   - clear statistics
3194  **/
3195 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3196 {
3197         struct e1000_mac_info *mac = &hw->mac;
3198         u32 ctrl_ext, txdctl, snoop;
3199         s32 ret_val;
3200         u16 i;
3201
3202         e1000_initialize_hw_bits_ich8lan(hw);
3203
3204         /* Initialize identification LED */
3205         ret_val = mac->ops.id_led_init(hw);
3206         if (ret_val)
3207                 e_dbg("Error initializing identification LED\n");
3208                 /* This is not fatal and we should not stop init due to this */
3209
3210         /* Setup the receive address. */
3211         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3212
3213         /* Zero out the Multicast HASH table */
3214         e_dbg("Zeroing the MTA\n");
3215         for (i = 0; i < mac->mta_reg_count; i++)
3216                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3217
3218         /*
3219          * The 82578 Rx buffer will stall if wakeup is enabled in host and
3220          * the ME.  Disable wakeup by clearing the host wakeup bit.
3221          * Reset the phy after disabling host wakeup to reset the Rx buffer.
3222          */
3223         if (hw->phy.type == e1000_phy_82578) {
3224                 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
3225                 i &= ~BM_WUC_HOST_WU_BIT;
3226                 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
3227                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3228                 if (ret_val)
3229                         return ret_val;
3230         }
3231
3232         /* Setup link and flow control */
3233         ret_val = e1000_setup_link_ich8lan(hw);
3234
3235         /* Set the transmit descriptor write-back policy for both queues */
3236         txdctl = er32(TXDCTL(0));
3237         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3238                  E1000_TXDCTL_FULL_TX_DESC_WB;
3239         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3240                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3241         ew32(TXDCTL(0), txdctl);
3242         txdctl = er32(TXDCTL(1));
3243         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3244                  E1000_TXDCTL_FULL_TX_DESC_WB;
3245         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3246                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3247         ew32(TXDCTL(1), txdctl);
3248
3249         /*
3250          * ICH8 has opposite polarity of no_snoop bits.
3251          * By default, we should use snoop behavior.
3252          */
3253         if (mac->type == e1000_ich8lan)
3254                 snoop = PCIE_ICH8_SNOOP_ALL;
3255         else
3256                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3257         e1000e_set_pcie_no_snoop(hw, snoop);
3258
3259         ctrl_ext = er32(CTRL_EXT);
3260         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3261         ew32(CTRL_EXT, ctrl_ext);
3262
3263         /*
3264          * Clear all of the statistics registers (clear on read).  It is
3265          * important that we do this after we have tried to establish link
3266          * because the symbol error count will increment wildly if there
3267          * is no link.
3268          */
3269         e1000_clear_hw_cntrs_ich8lan(hw);
3270
3271         return 0;
3272 }
3273 /**
3274  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3275  *  @hw: pointer to the HW structure
3276  *
3277  *  Sets/Clears required hardware bits necessary for correctly setting up the
3278  *  hardware for transmit and receive.
3279  **/
3280 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3281 {
3282         u32 reg;
3283
3284         /* Extended Device Control */
3285         reg = er32(CTRL_EXT);
3286         reg |= (1 << 22);
3287         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3288         if (hw->mac.type >= e1000_pchlan)
3289                 reg |= E1000_CTRL_EXT_PHYPDEN;
3290         ew32(CTRL_EXT, reg);
3291
3292         /* Transmit Descriptor Control 0 */
3293         reg = er32(TXDCTL(0));
3294         reg |= (1 << 22);
3295         ew32(TXDCTL(0), reg);
3296
3297         /* Transmit Descriptor Control 1 */
3298         reg = er32(TXDCTL(1));
3299         reg |= (1 << 22);
3300         ew32(TXDCTL(1), reg);
3301
3302         /* Transmit Arbitration Control 0 */
3303         reg = er32(TARC(0));
3304         if (hw->mac.type == e1000_ich8lan)
3305                 reg |= (1 << 28) | (1 << 29);
3306         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3307         ew32(TARC(0), reg);
3308
3309         /* Transmit Arbitration Control 1 */
3310         reg = er32(TARC(1));
3311         if (er32(TCTL) & E1000_TCTL_MULR)
3312                 reg &= ~(1 << 28);
3313         else
3314                 reg |= (1 << 28);
3315         reg |= (1 << 24) | (1 << 26) | (1 << 30);
3316         ew32(TARC(1), reg);
3317
3318         /* Device Status */
3319         if (hw->mac.type == e1000_ich8lan) {
3320                 reg = er32(STATUS);
3321                 reg &= ~(1 << 31);
3322                 ew32(STATUS, reg);
3323         }
3324
3325         /*
3326          * work-around descriptor data corruption issue during nfs v2 udp
3327          * traffic, just disable the nfs filtering capability
3328          */
3329         reg = er32(RFCTL);
3330         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3331         ew32(RFCTL, reg);
3332 }
3333
3334 /**
3335  *  e1000_setup_link_ich8lan - Setup flow control and link settings
3336  *  @hw: pointer to the HW structure
3337  *
3338  *  Determines which flow control settings to use, then configures flow
3339  *  control.  Calls the appropriate media-specific link configuration
3340  *  function.  Assuming the adapter has a valid link partner, a valid link
3341  *  should be established.  Assumes the hardware has previously been reset
3342  *  and the transmitter and receiver are not enabled.
3343  **/
3344 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3345 {
3346         s32 ret_val;
3347
3348         if (e1000_check_reset_block(hw))
3349                 return 0;
3350
3351         /*
3352          * ICH parts do not have a word in the NVM to determine
3353          * the default flow control setting, so we explicitly
3354          * set it to full.
3355          */
3356         if (hw->fc.requested_mode == e1000_fc_default) {
3357                 /* Workaround h/w hang when Tx flow control enabled */
3358                 if (hw->mac.type == e1000_pchlan)
3359                         hw->fc.requested_mode = e1000_fc_rx_pause;
3360                 else
3361                         hw->fc.requested_mode = e1000_fc_full;
3362         }
3363
3364         /*
3365          * Save off the requested flow control mode for use later.  Depending
3366          * on the link partner's capabilities, we may or may not use this mode.
3367          */
3368         hw->fc.current_mode = hw->fc.requested_mode;
3369
3370         e_dbg("After fix-ups FlowControl is now = %x\n",
3371                 hw->fc.current_mode);
3372
3373         /* Continue to configure the copper link. */
3374         ret_val = e1000_setup_copper_link_ich8lan(hw);
3375         if (ret_val)
3376                 return ret_val;
3377
3378         ew32(FCTTV, hw->fc.pause_time);
3379         if ((hw->phy.type == e1000_phy_82578) ||
3380             (hw->phy.type == e1000_phy_82579) ||
3381             (hw->phy.type == e1000_phy_82577)) {
3382                 ew32(FCRTV_PCH, hw->fc.refresh_time);
3383
3384                 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3385                                    hw->fc.pause_time);
3386                 if (ret_val)
3387                         return ret_val;
3388         }
3389
3390         return e1000e_set_fc_watermarks(hw);
3391 }
3392
3393 /**
3394  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3395  *  @hw: pointer to the HW structure
3396  *
3397  *  Configures the kumeran interface to the PHY to wait the appropriate time
3398  *  when polling the PHY, then call the generic setup_copper_link to finish
3399  *  configuring the copper link.
3400  **/
3401 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3402 {
3403         u32 ctrl;
3404         s32 ret_val;
3405         u16 reg_data;
3406
3407         ctrl = er32(CTRL);
3408         ctrl |= E1000_CTRL_SLU;
3409         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3410         ew32(CTRL, ctrl);
3411
3412         /*
3413          * Set the mac to wait the maximum time between each iteration
3414          * and increase the max iterations when polling the phy;
3415          * this fixes erroneous timeouts at 10Mbps.
3416          */
3417         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3418         if (ret_val)
3419                 return ret_val;
3420         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3421                                        &reg_data);
3422         if (ret_val)
3423                 return ret_val;
3424         reg_data |= 0x3F;
3425         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3426                                         reg_data);
3427         if (ret_val)
3428                 return ret_val;
3429
3430         switch (hw->phy.type) {
3431         case e1000_phy_igp_3:
3432                 ret_val = e1000e_copper_link_setup_igp(hw);
3433                 if (ret_val)
3434                         return ret_val;
3435                 break;
3436         case e1000_phy_bm:
3437         case e1000_phy_82578:
3438                 ret_val = e1000e_copper_link_setup_m88(hw);
3439                 if (ret_val)
3440                         return ret_val;
3441                 break;
3442         case e1000_phy_82577:
3443         case e1000_phy_82579:
3444                 ret_val = e1000_copper_link_setup_82577(hw);
3445                 if (ret_val)
3446                         return ret_val;
3447                 break;
3448         case e1000_phy_ife:
3449                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
3450                 if (ret_val)
3451                         return ret_val;
3452
3453                 reg_data &= ~IFE_PMC_AUTO_MDIX;
3454
3455                 switch (hw->phy.mdix) {
3456                 case 1:
3457                         reg_data &= ~IFE_PMC_FORCE_MDIX;
3458                         break;
3459                 case 2:
3460                         reg_data |= IFE_PMC_FORCE_MDIX;
3461                         break;
3462                 case 0:
3463                 default:
3464                         reg_data |= IFE_PMC_AUTO_MDIX;
3465                         break;
3466                 }
3467                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
3468                 if (ret_val)
3469                         return ret_val;
3470                 break;
3471         default:
3472                 break;
3473         }
3474         return e1000e_setup_copper_link(hw);
3475 }
3476
3477 /**
3478  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3479  *  @hw: pointer to the HW structure
3480  *  @speed: pointer to store current link speed
3481  *  @duplex: pointer to store the current link duplex
3482  *
3483  *  Calls the generic get_speed_and_duplex to retrieve the current link
3484  *  information and then calls the Kumeran lock loss workaround for links at
3485  *  gigabit speeds.
3486  **/
3487 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3488                                           u16 *duplex)
3489 {
3490         s32 ret_val;
3491
3492         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3493         if (ret_val)
3494                 return ret_val;
3495
3496         if ((hw->mac.type == e1000_ich8lan) &&
3497             (hw->phy.type == e1000_phy_igp_3) &&
3498             (*speed == SPEED_1000)) {
3499                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3500         }
3501
3502         return ret_val;
3503 }
3504
3505 /**
3506  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3507  *  @hw: pointer to the HW structure
3508  *
3509  *  Work-around for 82566 Kumeran PCS lock loss:
3510  *  On link status change (i.e. PCI reset, speed change) and link is up and
3511  *  speed is gigabit-
3512  *    0) if workaround is optionally disabled do nothing
3513  *    1) wait 1ms for Kumeran link to come up
3514  *    2) check Kumeran Diagnostic register PCS lock loss bit
3515  *    3) if not set the link is locked (all is good), otherwise...
3516  *    4) reset the PHY
3517  *    5) repeat up to 10 times
3518  *  Note: this is only called for IGP3 copper when speed is 1gb.
3519  **/
3520 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3521 {
3522         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3523         u32 phy_ctrl;
3524         s32 ret_val;
3525         u16 i, data;
3526         bool link;
3527
3528         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3529                 return 0;
3530
3531         /*
3532          * Make sure link is up before proceeding.  If not just return.
3533          * Attempting this while link is negotiating fouled up link
3534          * stability
3535          */
3536         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3537         if (!link)
3538                 return 0;
3539
3540         for (i = 0; i < 10; i++) {
3541                 /* read once to clear */
3542                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3543                 if (ret_val)
3544                         return ret_val;
3545                 /* and again to get new status */
3546                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3547                 if (ret_val)
3548                         return ret_val;
3549
3550                 /* check for PCS lock */
3551                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3552                         return 0;
3553
3554                 /* Issue PHY reset */
3555                 e1000_phy_hw_reset(hw);
3556                 mdelay(5);
3557         }
3558         /* Disable GigE link negotiation */
3559         phy_ctrl = er32(PHY_CTRL);
3560         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3561                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3562         ew32(PHY_CTRL, phy_ctrl);
3563
3564         /*
3565          * Call gig speed drop workaround on Gig disable before accessing
3566          * any PHY registers
3567          */
3568         e1000e_gig_downshift_workaround_ich8lan(hw);
3569
3570         /* unable to acquire PCS lock */
3571         return -E1000_ERR_PHY;
3572 }
3573
3574 /**
3575  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3576  *  @hw: pointer to the HW structure
3577  *  @state: boolean value used to set the current Kumeran workaround state
3578  *
3579  *  If ICH8, set the current Kumeran workaround state (enabled - true
3580  *  /disabled - false).
3581  **/
3582 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3583                                                  bool state)
3584 {
3585         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3586
3587         if (hw->mac.type != e1000_ich8lan) {
3588                 e_dbg("Workaround applies to ICH8 only.\n");
3589                 return;
3590         }
3591
3592         dev_spec->kmrn_lock_loss_workaround_enabled = state;
3593 }
3594
3595 /**
3596  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3597  *  @hw: pointer to the HW structure
3598  *
3599  *  Workaround for 82566 power-down on D3 entry:
3600  *    1) disable gigabit link
3601  *    2) write VR power-down enable
3602  *    3) read it back
3603  *  Continue if successful, else issue LCD reset and repeat
3604  **/
3605 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3606 {
3607         u32 reg;
3608         u16 data;
3609         u8  retry = 0;
3610
3611         if (hw->phy.type != e1000_phy_igp_3)
3612                 return;
3613
3614         /* Try the workaround twice (if needed) */
3615         do {
3616                 /* Disable link */
3617                 reg = er32(PHY_CTRL);
3618                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3619                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3620                 ew32(PHY_CTRL, reg);
3621
3622                 /*
3623                  * Call gig speed drop workaround on Gig disable before
3624                  * accessing any PHY registers
3625                  */
3626                 if (hw->mac.type == e1000_ich8lan)
3627                         e1000e_gig_downshift_workaround_ich8lan(hw);
3628
3629                 /* Write VR power-down enable */
3630                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3631                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3632                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3633
3634                 /* Read it back and test */
3635                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3636                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3637                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3638                         break;
3639
3640                 /* Issue PHY reset and repeat at most one more time */
3641                 reg = er32(CTRL);
3642                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3643                 retry++;
3644         } while (retry);
3645 }
3646
3647 /**
3648  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3649  *  @hw: pointer to the HW structure
3650  *
3651  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3652  *  LPLU, Gig disable, MDIC PHY reset):
3653  *    1) Set Kumeran Near-end loopback
3654  *    2) Clear Kumeran Near-end loopback
3655  *  Should only be called for ICH8[m] devices with any 1G Phy.
3656  **/
3657 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3658 {
3659         s32 ret_val;
3660         u16 reg_data;
3661
3662         if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
3663                 return;
3664
3665         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3666                                       &reg_data);
3667         if (ret_val)
3668                 return;
3669         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3670         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3671                                        reg_data);
3672         if (ret_val)
3673                 return;
3674         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3675         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3676                                        reg_data);
3677 }
3678
3679 /**
3680  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
3681  *  @hw: pointer to the HW structure
3682  *
3683  *  During S0 to Sx transition, it is possible the link remains at gig
3684  *  instead of negotiating to a lower speed.  Before going to Sx, set
3685  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3686  *  to a lower speed.  For PCH and newer parts, the OEM bits PHY register
3687  *  (LED, GbE disable and LPLU configurations) also needs to be written.
3688  **/
3689 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
3690 {
3691         u32 phy_ctrl;
3692         s32 ret_val;
3693
3694         phy_ctrl = er32(PHY_CTRL);
3695         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
3696         ew32(PHY_CTRL, phy_ctrl);
3697
3698         if (hw->mac.type == e1000_ich8lan)
3699                 e1000e_gig_downshift_workaround_ich8lan(hw);
3700
3701         if (hw->mac.type >= e1000_pchlan) {
3702                 e1000_oem_bits_config_ich8lan(hw, false);
3703                 e1000_phy_hw_reset_ich8lan(hw);
3704                 ret_val = hw->phy.ops.acquire(hw);
3705                 if (ret_val)
3706                         return;
3707                 e1000_write_smbus_addr(hw);
3708                 hw->phy.ops.release(hw);
3709         }
3710 }
3711
3712 /**
3713  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
3714  *  @hw: pointer to the HW structure
3715  *
3716  *  During Sx to S0 transitions on non-managed devices or managed devices
3717  *  on which PHY resets are not blocked, if the PHY registers cannot be
3718  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
3719  *  the PHY.
3720  **/
3721 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
3722 {
3723         u32 fwsm;
3724
3725         if (hw->mac.type != e1000_pch2lan)
3726                 return;
3727
3728         fwsm = er32(FWSM);
3729         if (!(fwsm & E1000_ICH_FWSM_FW_VALID) || !e1000_check_reset_block(hw)) {
3730                 u16 phy_id1, phy_id2;
3731                 s32 ret_val;
3732
3733                 ret_val = hw->phy.ops.acquire(hw);
3734                 if (ret_val) {
3735                         e_dbg("Failed to acquire PHY semaphore in resume\n");
3736                         return;
3737                 }
3738
3739                 /* Test access to the PHY registers by reading the ID regs */
3740                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_id1);
3741                 if (ret_val)
3742                         goto release;
3743                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_id2);
3744                 if (ret_val)
3745                         goto release;
3746
3747                 if (hw->phy.id == ((u32)(phy_id1 << 16) |
3748                                    (u32)(phy_id2 & PHY_REVISION_MASK)))
3749                         goto release;
3750
3751                 e1000_toggle_lanphypc_value_ich8lan(hw);
3752
3753                 hw->phy.ops.release(hw);
3754                 msleep(50);
3755                 e1000_phy_hw_reset(hw);
3756                 msleep(50);
3757                 return;
3758         }
3759
3760 release:
3761         hw->phy.ops.release(hw);
3762
3763         return;
3764 }
3765
3766 /**
3767  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
3768  *  @hw: pointer to the HW structure
3769  *
3770  *  Return the LED back to the default configuration.
3771  **/
3772 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3773 {
3774         if (hw->phy.type == e1000_phy_ife)
3775                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3776
3777         ew32(LEDCTL, hw->mac.ledctl_default);
3778         return 0;
3779 }
3780
3781 /**
3782  *  e1000_led_on_ich8lan - Turn LEDs on
3783  *  @hw: pointer to the HW structure
3784  *
3785  *  Turn on the LEDs.
3786  **/
3787 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3788 {
3789         if (hw->phy.type == e1000_phy_ife)
3790                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3791                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3792
3793         ew32(LEDCTL, hw->mac.ledctl_mode2);
3794         return 0;
3795 }
3796
3797 /**
3798  *  e1000_led_off_ich8lan - Turn LEDs off
3799  *  @hw: pointer to the HW structure
3800  *
3801  *  Turn off the LEDs.
3802  **/
3803 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3804 {
3805         if (hw->phy.type == e1000_phy_ife)
3806                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3807                                 (IFE_PSCL_PROBE_MODE |
3808                                  IFE_PSCL_PROBE_LEDS_OFF));
3809
3810         ew32(LEDCTL, hw->mac.ledctl_mode1);
3811         return 0;
3812 }
3813
3814 /**
3815  *  e1000_setup_led_pchlan - Configures SW controllable LED
3816  *  @hw: pointer to the HW structure
3817  *
3818  *  This prepares the SW controllable LED for use.
3819  **/
3820 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3821 {
3822         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
3823 }
3824
3825 /**
3826  *  e1000_cleanup_led_pchlan - Restore the default LED operation
3827  *  @hw: pointer to the HW structure
3828  *
3829  *  Return the LED back to the default configuration.
3830  **/
3831 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3832 {
3833         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
3834 }
3835
3836 /**
3837  *  e1000_led_on_pchlan - Turn LEDs on
3838  *  @hw: pointer to the HW structure
3839  *
3840  *  Turn on the LEDs.
3841  **/
3842 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3843 {
3844         u16 data = (u16)hw->mac.ledctl_mode2;
3845         u32 i, led;
3846
3847         /*
3848          * If no link, then turn LED on by setting the invert bit
3849          * for each LED that's mode is "link_up" in ledctl_mode2.
3850          */
3851         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3852                 for (i = 0; i < 3; i++) {
3853                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3854                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3855                             E1000_LEDCTL_MODE_LINK_UP)
3856                                 continue;
3857                         if (led & E1000_PHY_LED0_IVRT)
3858                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3859                         else
3860                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3861                 }
3862         }
3863
3864         return e1e_wphy(hw, HV_LED_CONFIG, data);
3865 }
3866
3867 /**
3868  *  e1000_led_off_pchlan - Turn LEDs off
3869  *  @hw: pointer to the HW structure
3870  *
3871  *  Turn off the LEDs.
3872  **/
3873 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3874 {
3875         u16 data = (u16)hw->mac.ledctl_mode1;
3876         u32 i, led;
3877
3878         /*
3879          * If no link, then turn LED off by clearing the invert bit
3880          * for each LED that's mode is "link_up" in ledctl_mode1.
3881          */
3882         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3883                 for (i = 0; i < 3; i++) {
3884                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3885                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3886                             E1000_LEDCTL_MODE_LINK_UP)
3887                                 continue;
3888                         if (led & E1000_PHY_LED0_IVRT)
3889                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3890                         else
3891                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3892                 }
3893         }
3894
3895         return e1e_wphy(hw, HV_LED_CONFIG, data);
3896 }
3897
3898 /**
3899  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
3900  *  @hw: pointer to the HW structure
3901  *
3902  *  Read appropriate register for the config done bit for completion status
3903  *  and configure the PHY through s/w for EEPROM-less parts.
3904  *
3905  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
3906  *  config done bit, so only an error is logged and continues.  If we were
3907  *  to return with error, EEPROM-less silicon would not be able to be reset
3908  *  or change link.
3909  **/
3910 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3911 {
3912         s32 ret_val = 0;
3913         u32 bank = 0;
3914         u32 status;
3915
3916         e1000e_get_cfg_done(hw);
3917
3918         /* Wait for indication from h/w that it has completed basic config */
3919         if (hw->mac.type >= e1000_ich10lan) {
3920                 e1000_lan_init_done_ich8lan(hw);
3921         } else {
3922                 ret_val = e1000e_get_auto_rd_done(hw);
3923                 if (ret_val) {
3924                         /*
3925                          * When auto config read does not complete, do not
3926                          * return with an error. This can happen in situations
3927                          * where there is no eeprom and prevents getting link.
3928                          */
3929                         e_dbg("Auto Read Done did not complete\n");
3930                         ret_val = 0;
3931                 }
3932         }
3933
3934         /* Clear PHY Reset Asserted bit */
3935         status = er32(STATUS);
3936         if (status & E1000_STATUS_PHYRA)
3937                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3938         else
3939                 e_dbg("PHY Reset Asserted not set - needs delay\n");
3940
3941         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3942         if (hw->mac.type <= e1000_ich9lan) {
3943                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3944                     (hw->phy.type == e1000_phy_igp_3)) {
3945                         e1000e_phy_init_script_igp3(hw);
3946                 }
3947         } else {
3948                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3949                         /* Maybe we should do a basic PHY config */
3950                         e_dbg("EEPROM not present\n");
3951                         ret_val = -E1000_ERR_CONFIG;
3952                 }
3953         }
3954
3955         return ret_val;
3956 }
3957
3958 /**
3959  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3960  * @hw: pointer to the HW structure
3961  *
3962  * In the case of a PHY power down to save power, or to turn off link during a
3963  * driver unload, or wake on lan is not enabled, remove the link.
3964  **/
3965 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3966 {
3967         /* If the management interface is not enabled, then power down */
3968         if (!(hw->mac.ops.check_mng_mode(hw) ||
3969               hw->phy.ops.check_reset_block(hw)))
3970                 e1000_power_down_phy_copper(hw);
3971 }
3972
3973 /**
3974  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3975  *  @hw: pointer to the HW structure
3976  *
3977  *  Clears hardware counters specific to the silicon family and calls
3978  *  clear_hw_cntrs_generic to clear all general purpose counters.
3979  **/
3980 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3981 {
3982         u16 phy_data;
3983         s32 ret_val;
3984
3985         e1000e_clear_hw_cntrs_base(hw);
3986
3987         er32(ALGNERRC);
3988         er32(RXERRC);
3989         er32(TNCRS);
3990         er32(CEXTERR);
3991         er32(TSCTC);
3992         er32(TSCTFC);
3993
3994         er32(MGTPRC);
3995         er32(MGTPDC);
3996         er32(MGTPTC);
3997
3998         er32(IAC);
3999         er32(ICRXOC);
4000
4001         /* Clear PHY statistics registers */
4002         if ((hw->phy.type == e1000_phy_82578) ||
4003             (hw->phy.type == e1000_phy_82579) ||
4004             (hw->phy.type == e1000_phy_82577)) {
4005                 ret_val = hw->phy.ops.acquire(hw);
4006                 if (ret_val)
4007                         return;
4008                 ret_val = hw->phy.ops.set_page(hw,
4009                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
4010                 if (ret_val)
4011                         goto release;
4012                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4013                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4014                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4015                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4016                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4017                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4018                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4019                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4020                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4021                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4022                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4023                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4024                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4025                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4026 release:
4027                 hw->phy.ops.release(hw);
4028         }
4029 }
4030
4031 static const struct e1000_mac_operations ich8_mac_ops = {
4032         .id_led_init            = e1000e_id_led_init,
4033         /* check_mng_mode dependent on mac type */
4034         .check_for_link         = e1000_check_for_copper_link_ich8lan,
4035         /* cleanup_led dependent on mac type */
4036         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
4037         .get_bus_info           = e1000_get_bus_info_ich8lan,
4038         .set_lan_id             = e1000_set_lan_id_single_port,
4039         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
4040         /* led_on dependent on mac type */
4041         /* led_off dependent on mac type */
4042         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
4043         .reset_hw               = e1000_reset_hw_ich8lan,
4044         .init_hw                = e1000_init_hw_ich8lan,
4045         .setup_link             = e1000_setup_link_ich8lan,
4046         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
4047         /* id_led_init dependent on mac type */
4048 };
4049
4050 static const struct e1000_phy_operations ich8_phy_ops = {
4051         .acquire                = e1000_acquire_swflag_ich8lan,
4052         .check_reset_block      = e1000_check_reset_block_ich8lan,
4053         .commit                 = NULL,
4054         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
4055         .get_cable_length       = e1000e_get_cable_length_igp_2,
4056         .read_reg               = e1000e_read_phy_reg_igp,
4057         .release                = e1000_release_swflag_ich8lan,
4058         .reset                  = e1000_phy_hw_reset_ich8lan,
4059         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
4060         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
4061         .write_reg              = e1000e_write_phy_reg_igp,
4062 };
4063
4064 static const struct e1000_nvm_operations ich8_nvm_ops = {
4065         .acquire                = e1000_acquire_nvm_ich8lan,
4066         .read                   = e1000_read_nvm_ich8lan,
4067         .release                = e1000_release_nvm_ich8lan,
4068         .update                 = e1000_update_nvm_checksum_ich8lan,
4069         .valid_led_default      = e1000_valid_led_default_ich8lan,
4070         .validate               = e1000_validate_nvm_checksum_ich8lan,
4071         .write                  = e1000_write_nvm_ich8lan,
4072 };
4073
4074 const struct e1000_info e1000_ich8_info = {
4075         .mac                    = e1000_ich8lan,
4076         .flags                  = FLAG_HAS_WOL
4077                                   | FLAG_IS_ICH
4078                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4079                                   | FLAG_HAS_AMT
4080                                   | FLAG_HAS_FLASH
4081                                   | FLAG_APME_IN_WUC,
4082         .pba                    = 8,
4083         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
4084         .get_variants           = e1000_get_variants_ich8lan,
4085         .mac_ops                = &ich8_mac_ops,
4086         .phy_ops                = &ich8_phy_ops,
4087         .nvm_ops                = &ich8_nvm_ops,
4088 };
4089
4090 const struct e1000_info e1000_ich9_info = {
4091         .mac                    = e1000_ich9lan,
4092         .flags                  = FLAG_HAS_JUMBO_FRAMES
4093                                   | FLAG_IS_ICH
4094                                   | FLAG_HAS_WOL
4095                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4096                                   | FLAG_HAS_AMT
4097                                   | FLAG_HAS_ERT
4098                                   | FLAG_HAS_FLASH
4099                                   | FLAG_APME_IN_WUC,
4100         .pba                    = 10,
4101         .max_hw_frame_size      = DEFAULT_JUMBO,
4102         .get_variants           = e1000_get_variants_ich8lan,
4103         .mac_ops                = &ich8_mac_ops,
4104         .phy_ops                = &ich8_phy_ops,
4105         .nvm_ops                = &ich8_nvm_ops,
4106 };
4107
4108 const struct e1000_info e1000_ich10_info = {
4109         .mac                    = e1000_ich10lan,
4110         .flags                  = FLAG_HAS_JUMBO_FRAMES
4111                                   | FLAG_IS_ICH
4112                                   | FLAG_HAS_WOL
4113                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4114                                   | FLAG_HAS_AMT
4115                                   | FLAG_HAS_ERT
4116                                   | FLAG_HAS_FLASH
4117                                   | FLAG_APME_IN_WUC,
4118         .pba                    = 10,
4119         .max_hw_frame_size      = DEFAULT_JUMBO,
4120         .get_variants           = e1000_get_variants_ich8lan,
4121         .mac_ops                = &ich8_mac_ops,
4122         .phy_ops                = &ich8_phy_ops,
4123         .nvm_ops                = &ich8_nvm_ops,
4124 };
4125
4126 const struct e1000_info e1000_pch_info = {
4127         .mac                    = e1000_pchlan,
4128         .flags                  = FLAG_IS_ICH
4129                                   | FLAG_HAS_WOL
4130                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4131                                   | FLAG_HAS_AMT
4132                                   | FLAG_HAS_FLASH
4133                                   | FLAG_HAS_JUMBO_FRAMES
4134                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
4135                                   | FLAG_APME_IN_WUC,
4136         .flags2                 = FLAG2_HAS_PHY_STATS,
4137         .pba                    = 26,
4138         .max_hw_frame_size      = 4096,
4139         .get_variants           = e1000_get_variants_ich8lan,
4140         .mac_ops                = &ich8_mac_ops,
4141         .phy_ops                = &ich8_phy_ops,
4142         .nvm_ops                = &ich8_nvm_ops,
4143 };
4144
4145 const struct e1000_info e1000_pch2_info = {
4146         .mac                    = e1000_pch2lan,
4147         .flags                  = FLAG_IS_ICH
4148                                   | FLAG_HAS_WOL
4149                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4150                                   | FLAG_HAS_AMT
4151                                   | FLAG_HAS_FLASH
4152                                   | FLAG_HAS_JUMBO_FRAMES
4153                                   | FLAG_APME_IN_WUC,
4154         .flags2                 = FLAG2_HAS_PHY_STATS
4155                                   | FLAG2_HAS_EEE,
4156         .pba                    = 26,
4157         .max_hw_frame_size      = DEFAULT_JUMBO,
4158         .get_variants           = e1000_get_variants_ich8lan,
4159         .mac_ops                = &ich8_mac_ops,
4160         .phy_ops                = &ich8_phy_ops,
4161         .nvm_ops                = &ich8_nvm_ops,
4162 };