2 * PTP 1588 clock using the eTSEC
4 * Copyright (C) 2010 OMICRON electronics GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 #include <linux/device.h>
21 #include <linux/hrtimer.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
27 #include <linux/of_platform.h>
28 #include <linux/timex.h>
31 #include <linux/ptp_clock_kernel.h>
36 * gianfar ptp registers
37 * Generated by regen.tcl on Thu May 13 01:38:57 PM CEST 2010
39 struct gianfar_ptp_registers {
40 u32 tmr_ctrl; /* Timer control register */
41 u32 tmr_tevent; /* Timestamp event register */
42 u32 tmr_temask; /* Timer event mask register */
43 u32 tmr_pevent; /* Timestamp event register */
44 u32 tmr_pemask; /* Timer event mask register */
45 u32 tmr_stat; /* Timestamp status register */
46 u32 tmr_cnt_h; /* Timer counter high register */
47 u32 tmr_cnt_l; /* Timer counter low register */
48 u32 tmr_add; /* Timer drift compensation addend register */
49 u32 tmr_acc; /* Timer accumulator register */
50 u32 tmr_prsc; /* Timer prescale */
52 u32 tmroff_h; /* Timer offset high */
53 u32 tmroff_l; /* Timer offset low */
55 u32 tmr_alarm1_h; /* Timer alarm 1 high register */
56 u32 tmr_alarm1_l; /* Timer alarm 1 high register */
57 u32 tmr_alarm2_h; /* Timer alarm 2 high register */
58 u32 tmr_alarm2_l; /* Timer alarm 2 high register */
60 u32 tmr_fiper1; /* Timer fixed period interval */
61 u32 tmr_fiper2; /* Timer fixed period interval */
62 u32 tmr_fiper3; /* Timer fixed period interval */
64 u32 tmr_etts1_h; /* Timestamp of general purpose external trigger */
65 u32 tmr_etts1_l; /* Timestamp of general purpose external trigger */
66 u32 tmr_etts2_h; /* Timestamp of general purpose external trigger */
67 u32 tmr_etts2_l; /* Timestamp of general purpose external trigger */
70 /* Bit definitions for the TMR_CTRL register */
71 #define ALM1P (1<<31) /* Alarm1 output polarity */
72 #define ALM2P (1<<30) /* Alarm2 output polarity */
73 #define FS (1<<28) /* FIPER start indication */
74 #define PP1L (1<<27) /* Fiper1 pulse loopback mode enabled. */
75 #define PP2L (1<<26) /* Fiper2 pulse loopback mode enabled. */
76 #define TCLK_PERIOD_SHIFT (16) /* 1588 timer reference clock period. */
77 #define TCLK_PERIOD_MASK (0x3ff)
78 #define RTPE (1<<15) /* Record Tx Timestamp to PAL Enable. */
79 #define FRD (1<<14) /* FIPER Realignment Disable */
80 #define ESFDP (1<<11) /* External Tx/Rx SFD Polarity. */
81 #define ESFDE (1<<10) /* External Tx/Rx SFD Enable. */
82 #define ETEP2 (1<<9) /* External trigger 2 edge polarity */
83 #define ETEP1 (1<<8) /* External trigger 1 edge polarity */
84 #define COPH (1<<7) /* Generated clock output phase. */
85 #define CIPH (1<<6) /* External oscillator input clock phase */
86 #define TMSR (1<<5) /* Timer soft reset. */
87 #define BYP (1<<3) /* Bypass drift compensated clock */
88 #define TE (1<<2) /* 1588 timer enable. */
89 #define CKSEL_SHIFT (0) /* 1588 Timer reference clock source */
90 #define CKSEL_MASK (0x3)
92 /* Bit definitions for the TMR_TEVENT register */
93 #define ETS2 (1<<25) /* External trigger 2 timestamp sampled */
94 #define ETS1 (1<<24) /* External trigger 1 timestamp sampled */
95 #define ALM2 (1<<17) /* Current time = alarm time register 2 */
96 #define ALM1 (1<<16) /* Current time = alarm time register 1 */
97 #define PP1 (1<<7) /* periodic pulse generated on FIPER1 */
98 #define PP2 (1<<6) /* periodic pulse generated on FIPER2 */
99 #define PP3 (1<<5) /* periodic pulse generated on FIPER3 */
101 /* Bit definitions for the TMR_TEMASK register */
102 #define ETS2EN (1<<25) /* External trigger 2 timestamp enable */
103 #define ETS1EN (1<<24) /* External trigger 1 timestamp enable */
104 #define ALM2EN (1<<17) /* Timer ALM2 event enable */
105 #define ALM1EN (1<<16) /* Timer ALM1 event enable */
106 #define PP1EN (1<<7) /* Periodic pulse event 1 enable */
107 #define PP2EN (1<<6) /* Periodic pulse event 2 enable */
109 /* Bit definitions for the TMR_PEVENT register */
110 #define TXP2 (1<<9) /* PTP transmitted timestamp im TXTS2 */
111 #define TXP1 (1<<8) /* PTP transmitted timestamp in TXTS1 */
112 #define RXP (1<<0) /* PTP frame has been received */
114 /* Bit definitions for the TMR_PEMASK register */
115 #define TXP2EN (1<<9) /* Transmit PTP packet event 2 enable */
116 #define TXP1EN (1<<8) /* Transmit PTP packet event 1 enable */
117 #define RXPEN (1<<0) /* Receive PTP packet event enable */
119 /* Bit definitions for the TMR_STAT register */
120 #define STAT_VEC_SHIFT (0) /* Timer general purpose status vector */
121 #define STAT_VEC_MASK (0x3f)
123 /* Bit definitions for the TMR_PRSC register */
124 #define PRSC_OCK_SHIFT (0) /* Output clock division/prescale factor. */
125 #define PRSC_OCK_MASK (0xffff)
128 #define DRIVER "gianfar_ptp"
129 #define DEFAULT_CKSEL 1
131 #define REG_SIZE sizeof(struct gianfar_ptp_registers)
134 struct gianfar_ptp_registers *regs;
135 spinlock_t lock; /* protects regs */
136 struct ptp_clock *clock;
137 struct ptp_clock_info caps;
138 struct resource *rsrc;
140 u64 alarm_interval; /* for periodic alarm */
142 u32 tclk_period; /* nanoseconds */
151 * Register access functions
154 /* Caller must hold etsects->lock. */
155 static u64 tmr_cnt_read(struct etsects *etsects)
160 lo = gfar_read(&etsects->regs->tmr_cnt_l);
161 hi = gfar_read(&etsects->regs->tmr_cnt_h);
162 ns = ((u64) hi) << 32;
167 /* Caller must hold etsects->lock. */
168 static void tmr_cnt_write(struct etsects *etsects, u64 ns)
171 u32 lo = ns & 0xffffffff;
173 gfar_write(&etsects->regs->tmr_cnt_l, lo);
174 gfar_write(&etsects->regs->tmr_cnt_h, hi);
177 /* Caller must hold etsects->lock. */
178 static void set_alarm(struct etsects *etsects)
183 ns = tmr_cnt_read(etsects) + 1500000000ULL;
184 ns = div_u64(ns, 1000000000UL) * 1000000000ULL;
185 ns -= etsects->tclk_period;
187 lo = ns & 0xffffffff;
188 gfar_write(&etsects->regs->tmr_alarm1_l, lo);
189 gfar_write(&etsects->regs->tmr_alarm1_h, hi);
192 /* Caller must hold etsects->lock. */
193 static void set_fipers(struct etsects *etsects)
196 gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
197 gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
201 * Interrupt service routine
204 static irqreturn_t isr(int irq, void *priv)
206 struct etsects *etsects = priv;
207 struct ptp_clock_event event;
209 u32 ack = 0, lo, hi, mask, val;
211 val = gfar_read(&etsects->regs->tmr_tevent);
215 hi = gfar_read(&etsects->regs->tmr_etts1_h);
216 lo = gfar_read(&etsects->regs->tmr_etts1_l);
217 event.type = PTP_CLOCK_EXTTS;
219 event.timestamp = ((u64) hi) << 32;
220 event.timestamp |= lo;
221 ptp_clock_event(etsects->clock, &event);
226 hi = gfar_read(&etsects->regs->tmr_etts2_h);
227 lo = gfar_read(&etsects->regs->tmr_etts2_l);
228 event.type = PTP_CLOCK_EXTTS;
230 event.timestamp = ((u64) hi) << 32;
231 event.timestamp |= lo;
232 ptp_clock_event(etsects->clock, &event);
237 if (etsects->alarm_value) {
238 event.type = PTP_CLOCK_ALARM;
240 event.timestamp = etsects->alarm_value;
241 ptp_clock_event(etsects->clock, &event);
243 if (etsects->alarm_interval) {
244 ns = etsects->alarm_value + etsects->alarm_interval;
246 lo = ns & 0xffffffff;
247 spin_lock(&etsects->lock);
248 gfar_write(&etsects->regs->tmr_alarm2_l, lo);
249 gfar_write(&etsects->regs->tmr_alarm2_h, hi);
250 spin_unlock(&etsects->lock);
251 etsects->alarm_value = ns;
253 gfar_write(&etsects->regs->tmr_tevent, ALM2);
254 spin_lock(&etsects->lock);
255 mask = gfar_read(&etsects->regs->tmr_temask);
257 gfar_write(&etsects->regs->tmr_temask, mask);
258 spin_unlock(&etsects->lock);
259 etsects->alarm_value = 0;
260 etsects->alarm_interval = 0;
266 event.type = PTP_CLOCK_PPS;
267 ptp_clock_event(etsects->clock, &event);
271 gfar_write(&etsects->regs->tmr_tevent, ack);
278 * PTP clock operations
281 static int ptp_gianfar_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
286 struct etsects *etsects = container_of(ptp, struct etsects, caps);
292 tmr_add = etsects->tmr_add;
295 diff = div_u64(adj, 1000000000ULL);
297 tmr_add = neg_adj ? tmr_add - diff : tmr_add + diff;
299 gfar_write(&etsects->regs->tmr_add, tmr_add);
304 static int ptp_gianfar_adjtime(struct ptp_clock_info *ptp, s64 delta)
308 struct etsects *etsects = container_of(ptp, struct etsects, caps);
310 spin_lock_irqsave(&etsects->lock, flags);
312 now = tmr_cnt_read(etsects);
314 tmr_cnt_write(etsects, now);
316 spin_unlock_irqrestore(&etsects->lock, flags);
323 static int ptp_gianfar_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
328 struct etsects *etsects = container_of(ptp, struct etsects, caps);
330 spin_lock_irqsave(&etsects->lock, flags);
332 ns = tmr_cnt_read(etsects);
334 spin_unlock_irqrestore(&etsects->lock, flags);
336 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
337 ts->tv_nsec = remainder;
341 static int ptp_gianfar_settime(struct ptp_clock_info *ptp,
342 const struct timespec *ts)
346 struct etsects *etsects = container_of(ptp, struct etsects, caps);
348 ns = ts->tv_sec * 1000000000ULL;
351 spin_lock_irqsave(&etsects->lock, flags);
353 tmr_cnt_write(etsects, ns);
356 spin_unlock_irqrestore(&etsects->lock, flags);
361 static int ptp_gianfar_enable(struct ptp_clock_info *ptp,
362 struct ptp_clock_request *rq, int on)
364 struct etsects *etsects = container_of(ptp, struct etsects, caps);
369 case PTP_CLK_REQ_EXTTS:
370 switch (rq->extts.index) {
380 spin_lock_irqsave(&etsects->lock, flags);
381 mask = gfar_read(&etsects->regs->tmr_temask);
386 gfar_write(&etsects->regs->tmr_temask, mask);
387 spin_unlock_irqrestore(&etsects->lock, flags);
390 case PTP_CLK_REQ_PPS:
391 spin_lock_irqsave(&etsects->lock, flags);
392 mask = gfar_read(&etsects->regs->tmr_temask);
397 gfar_write(&etsects->regs->tmr_temask, mask);
398 spin_unlock_irqrestore(&etsects->lock, flags);
408 static struct ptp_clock_info ptp_gianfar_caps = {
409 .owner = THIS_MODULE,
410 .name = "gianfar clock",
413 .n_ext_ts = N_EXT_TS,
416 .adjfreq = ptp_gianfar_adjfreq,
417 .adjtime = ptp_gianfar_adjtime,
418 .gettime = ptp_gianfar_gettime,
419 .settime = ptp_gianfar_settime,
420 .enable = ptp_gianfar_enable,
425 static int get_of_u32(struct device_node *node, char *str, u32 *val)
428 const u32 *prop = of_get_property(node, str, &plen);
430 if (!prop || plen != sizeof(*prop))
436 static int gianfar_ptp_probe(struct platform_device *dev)
438 struct device_node *node = dev->dev.of_node;
439 struct etsects *etsects;
445 etsects = kzalloc(sizeof(*etsects), GFP_KERNEL);
451 etsects->caps = ptp_gianfar_caps;
452 etsects->cksel = DEFAULT_CKSEL;
454 if (get_of_u32(node, "fsl,tclk-period", &etsects->tclk_period) ||
455 get_of_u32(node, "fsl,tmr-prsc", &etsects->tmr_prsc) ||
456 get_of_u32(node, "fsl,tmr-add", &etsects->tmr_add) ||
457 get_of_u32(node, "fsl,tmr-fiper1", &etsects->tmr_fiper1) ||
458 get_of_u32(node, "fsl,tmr-fiper2", &etsects->tmr_fiper2) ||
459 get_of_u32(node, "fsl,max-adj", &etsects->caps.max_adj)) {
460 pr_err("device tree node missing required elements\n");
464 etsects->irq = platform_get_irq(dev, 0);
466 if (etsects->irq == NO_IRQ) {
467 pr_err("irq not in device tree\n");
470 if (request_irq(etsects->irq, isr, 0, DRIVER, etsects)) {
471 pr_err("request_irq failed\n");
475 etsects->rsrc = platform_get_resource(dev, IORESOURCE_MEM, 0);
476 if (!etsects->rsrc) {
477 pr_err("no resource\n");
480 if (request_resource(&ioport_resource, etsects->rsrc)) {
481 pr_err("resource busy\n");
485 spin_lock_init(&etsects->lock);
487 etsects->regs = ioremap(etsects->rsrc->start,
488 resource_size(etsects->rsrc));
489 if (!etsects->regs) {
490 pr_err("ioremap ptp registers failed\n");
493 getnstimeofday(&now);
494 ptp_gianfar_settime(&etsects->caps, &now);
497 (etsects->tclk_period & TCLK_PERIOD_MASK) << TCLK_PERIOD_SHIFT |
498 (etsects->cksel & CKSEL_MASK) << CKSEL_SHIFT;
500 spin_lock_irqsave(&etsects->lock, flags);
502 gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl);
503 gfar_write(&etsects->regs->tmr_add, etsects->tmr_add);
504 gfar_write(&etsects->regs->tmr_prsc, etsects->tmr_prsc);
505 gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
506 gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
508 gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl|FS|RTPE|TE|FRD);
510 spin_unlock_irqrestore(&etsects->lock, flags);
512 etsects->clock = ptp_clock_register(&etsects->caps);
513 if (IS_ERR(etsects->clock)) {
514 err = PTR_ERR(etsects->clock);
518 dev_set_drvdata(&dev->dev, etsects);
523 iounmap(etsects->regs);
525 release_resource(etsects->rsrc);
527 free_irq(etsects->irq, etsects);
534 static int gianfar_ptp_remove(struct platform_device *dev)
536 struct etsects *etsects = dev_get_drvdata(&dev->dev);
538 gfar_write(&etsects->regs->tmr_temask, 0);
539 gfar_write(&etsects->regs->tmr_ctrl, 0);
541 ptp_clock_unregister(etsects->clock);
542 iounmap(etsects->regs);
543 release_resource(etsects->rsrc);
544 free_irq(etsects->irq, etsects);
550 static struct of_device_id match_table[] = {
551 { .compatible = "fsl,etsec-ptp" },
555 static struct platform_driver gianfar_ptp_driver = {
557 .name = "gianfar_ptp",
558 .of_match_table = match_table,
559 .owner = THIS_MODULE,
561 .probe = gianfar_ptp_probe,
562 .remove = gianfar_ptp_remove,
565 /* module operations */
567 static int __init ptp_gianfar_init(void)
569 return platform_driver_register(&gianfar_ptp_driver);
572 module_init(ptp_gianfar_init);
574 static void __exit ptp_gianfar_exit(void)
576 platform_driver_unregister(&gianfar_ptp_driver);
579 module_exit(ptp_gianfar_exit);
581 MODULE_AUTHOR("Richard Cochran <richard.cochran@omicron.at>");
582 MODULE_DESCRIPTION("PTP clock using the eTSEC");
583 MODULE_LICENSE("GPL");