2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
40 #include <linux/tcp.h>
41 #include <linux/udp.h>
42 #include <linux/icmp.h>
43 #include <linux/spinlock.h>
44 #include <linux/workqueue.h>
45 #include <linux/bitops.h>
47 #include <linux/irq.h>
48 #include <linux/clk.h>
49 #include <linux/platform_device.h>
50 #include <linux/phy.h>
51 #include <linux/fec.h>
53 #include <linux/of_device.h>
54 #include <linux/of_gpio.h>
55 #include <linux/of_net.h>
56 #include <linux/regulator/consumer.h>
57 #include <linux/if_vlan.h>
58 #include <linux/pinctrl/consumer.h>
60 #include <asm/cacheflush.h>
64 static void set_multicast_list(struct net_device *ndev);
66 #if defined(CONFIG_ARM)
67 #define FEC_ALIGNMENT 0xf
69 #define FEC_ALIGNMENT 0x3
72 #define DRIVER_NAME "fec"
74 /* Pause frame feild and FIFO threshold */
75 #define FEC_ENET_FCE (1 << 5)
76 #define FEC_ENET_RSEM_V 0x84
77 #define FEC_ENET_RSFL_V 16
78 #define FEC_ENET_RAEM_V 0x8
79 #define FEC_ENET_RAFL_V 0x8
80 #define FEC_ENET_OPD_V 0xFFF0
82 /* Controller is ENET-MAC */
83 #define FEC_QUIRK_ENET_MAC (1 << 0)
84 /* Controller needs driver to swap frame */
85 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
86 /* Controller uses gasket */
87 #define FEC_QUIRK_USE_GASKET (1 << 2)
88 /* Controller has GBIT support */
89 #define FEC_QUIRK_HAS_GBIT (1 << 3)
90 /* Controller has extend desc buffer */
91 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
92 /* Controller has hardware checksum support */
93 #define FEC_QUIRK_HAS_CSUM (1 << 5)
94 /* Controller has hardware vlan support */
95 #define FEC_QUIRK_HAS_VLAN (1 << 6)
96 /* ENET IP errata ERR006358
98 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
99 * detected as not set during a prior frame transmission, then the
100 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
101 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
102 * frames not being transmitted until there is a 0-to-1 transition on
105 #define FEC_QUIRK_ERR006358 (1 << 7)
107 static struct platform_device_id fec_devtype[] = {
109 /* keep it for coldfire */
114 .driver_data = FEC_QUIRK_USE_GASKET,
120 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
123 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
124 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
125 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
127 .name = "mvf600-fec",
128 .driver_data = FEC_QUIRK_ENET_MAC,
133 MODULE_DEVICE_TABLE(platform, fec_devtype);
136 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
137 IMX27_FEC, /* runs on i.mx27/35/51 */
143 static const struct of_device_id fec_dt_ids[] = {
144 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
145 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
146 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
147 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
148 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
151 MODULE_DEVICE_TABLE(of, fec_dt_ids);
153 static unsigned char macaddr[ETH_ALEN];
154 module_param_array(macaddr, byte, NULL, 0);
155 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
157 #if defined(CONFIG_M5272)
159 * Some hardware gets it MAC address out of local flash memory.
160 * if this is non-zero then assume it is the address to get MAC from.
162 #if defined(CONFIG_NETtel)
163 #define FEC_FLASHMAC 0xf0006006
164 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
165 #define FEC_FLASHMAC 0xf0006000
166 #elif defined(CONFIG_CANCam)
167 #define FEC_FLASHMAC 0xf0020000
168 #elif defined (CONFIG_M5272C3)
169 #define FEC_FLASHMAC (0xffe04000 + 4)
170 #elif defined(CONFIG_MOD5272)
171 #define FEC_FLASHMAC 0xffc0406b
173 #define FEC_FLASHMAC 0
175 #endif /* CONFIG_M5272 */
177 /* Interrupt events/masks. */
178 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
179 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
180 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
181 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
182 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
183 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
184 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
185 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
186 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
187 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
189 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
190 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
192 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
194 #define PKT_MAXBUF_SIZE 1522
195 #define PKT_MINBUF_SIZE 64
196 #define PKT_MAXBLR_SIZE 1536
198 /* FEC receive acceleration */
199 #define FEC_RACC_IPDIS (1 << 1)
200 #define FEC_RACC_PRODIS (1 << 2)
201 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
204 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
205 * size bits. Other FEC hardware does not, so we need to take that into
206 * account when setting it.
208 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
209 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
210 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
212 #define OPT_FRAME_SIZE 0
215 /* FEC MII MMFR bits definition */
216 #define FEC_MMFR_ST (1 << 30)
217 #define FEC_MMFR_OP_READ (2 << 28)
218 #define FEC_MMFR_OP_WRITE (1 << 28)
219 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
220 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
221 #define FEC_MMFR_TA (2 << 16)
222 #define FEC_MMFR_DATA(v) (v & 0xffff)
224 #define FEC_MII_TIMEOUT 30000 /* us */
226 /* Transmitter timeout */
227 #define TX_TIMEOUT (2 * HZ)
229 #define FEC_PAUSE_FLAG_AUTONEG 0x1
230 #define FEC_PAUSE_FLAG_ENABLE 0x2
232 #define TSO_HEADER_SIZE 128
233 /* Max number of allowed TCP segments for software TSO */
234 #define FEC_MAX_TSO_SEGS 100
235 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
237 #define IS_TSO_HEADER(txq, addr) \
238 ((addr >= txq->tso_hdrs_dma) && \
239 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
244 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
246 struct bufdesc *new_bd = bdp + 1;
247 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
248 struct bufdesc_ex *ex_base;
249 struct bufdesc *base;
252 if (bdp >= fep->tx_bd_base) {
253 base = fep->tx_bd_base;
254 ring_size = fep->tx_ring_size;
255 ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
257 base = fep->rx_bd_base;
258 ring_size = fep->rx_ring_size;
259 ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
263 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
264 ex_base : ex_new_bd);
266 return (new_bd >= (base + ring_size)) ?
271 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
273 struct bufdesc *new_bd = bdp - 1;
274 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
275 struct bufdesc_ex *ex_base;
276 struct bufdesc *base;
279 if (bdp >= fep->tx_bd_base) {
280 base = fep->tx_bd_base;
281 ring_size = fep->tx_ring_size;
282 ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
284 base = fep->rx_bd_base;
285 ring_size = fep->rx_ring_size;
286 ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
290 return (struct bufdesc *)((ex_new_bd < ex_base) ?
291 (ex_new_bd + ring_size) : ex_new_bd);
293 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
296 static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp,
297 struct fec_enet_private *fep)
299 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size;
302 static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep)
306 entries = ((const char *)fep->dirty_tx -
307 (const char *)fep->cur_tx) / fep->bufdesc_size - 1;
309 return entries > 0 ? entries : entries + fep->tx_ring_size;
312 static void *swap_buffer(void *bufaddr, int len)
315 unsigned int *buf = bufaddr;
317 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++)
318 *buf = cpu_to_be32(*buf);
323 static inline bool is_ipv4_pkt(struct sk_buff *skb)
325 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
329 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
331 /* Only run for packets requiring a checksum. */
332 if (skb->ip_summed != CHECKSUM_PARTIAL)
335 if (unlikely(skb_cow_head(skb, 0)))
338 if (is_ipv4_pkt(skb))
339 ip_hdr(skb)->check = 0;
340 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
346 fec_enet_submit_work(struct bufdesc *bdp, struct fec_enet_private *fep)
348 const struct platform_device_id *id_entry =
349 platform_get_device_id(fep->pdev);
350 struct bufdesc *bdp_pre;
352 bdp_pre = fec_enet_get_prevdesc(bdp, fep);
353 if ((id_entry->driver_data & FEC_QUIRK_ERR006358) &&
354 !(bdp_pre->cbd_sc & BD_ENET_TX_READY)) {
355 fep->delay_work.trig_tx = true;
356 schedule_delayed_work(&(fep->delay_work.delay_work),
357 msecs_to_jiffies(1));
362 fec_enet_txq_submit_frag_skb(struct sk_buff *skb, struct net_device *ndev)
364 struct fec_enet_private *fep = netdev_priv(ndev);
365 const struct platform_device_id *id_entry =
366 platform_get_device_id(fep->pdev);
367 struct bufdesc *bdp = fep->cur_tx;
368 struct bufdesc_ex *ebdp;
369 int nr_frags = skb_shinfo(skb)->nr_frags;
371 unsigned short status;
372 unsigned int estatus = 0;
373 skb_frag_t *this_frag;
378 for (frag = 0; frag < nr_frags; frag++) {
379 this_frag = &skb_shinfo(skb)->frags[frag];
380 bdp = fec_enet_get_nextdesc(bdp, fep);
381 ebdp = (struct bufdesc_ex *)bdp;
383 status = bdp->cbd_sc;
384 status &= ~BD_ENET_TX_STATS;
385 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
386 frag_len = skb_shinfo(skb)->frags[frag].size;
388 /* Handle the last BD specially */
389 if (frag == nr_frags - 1) {
390 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
391 if (fep->bufdesc_ex) {
392 estatus |= BD_ENET_TX_INT;
393 if (unlikely(skb_shinfo(skb)->tx_flags &
394 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
395 estatus |= BD_ENET_TX_TS;
399 if (fep->bufdesc_ex) {
400 if (skb->ip_summed == CHECKSUM_PARTIAL)
401 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
403 ebdp->cbd_esc = estatus;
406 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
408 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
409 if (((unsigned long) bufaddr) & FEC_ALIGNMENT ||
410 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
411 memcpy(fep->tx_bounce[index], bufaddr, frag_len);
412 bufaddr = fep->tx_bounce[index];
414 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
415 swap_buffer(bufaddr, frag_len);
418 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
419 frag_len, DMA_TO_DEVICE);
420 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
421 dev_kfree_skb_any(skb);
423 netdev_err(ndev, "Tx DMA memory map failed\n");
424 goto dma_mapping_error;
427 bdp->cbd_datlen = frag_len;
428 bdp->cbd_sc = status;
437 for (i = 0; i < frag; i++) {
438 bdp = fec_enet_get_nextdesc(bdp, fep);
439 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
440 bdp->cbd_datlen, DMA_TO_DEVICE);
445 static int fec_enet_txq_submit_skb(struct sk_buff *skb, struct net_device *ndev)
447 struct fec_enet_private *fep = netdev_priv(ndev);
448 const struct platform_device_id *id_entry =
449 platform_get_device_id(fep->pdev);
450 int nr_frags = skb_shinfo(skb)->nr_frags;
451 struct bufdesc *bdp, *last_bdp;
453 unsigned short status;
454 unsigned short buflen;
455 unsigned int estatus = 0;
460 entries_free = fec_enet_get_free_txdesc_num(fep);
461 if (entries_free < MAX_SKB_FRAGS + 1) {
462 dev_kfree_skb_any(skb);
464 netdev_err(ndev, "NOT enough BD for SG!\n");
468 /* Protocol checksum off-load for TCP and UDP. */
469 if (fec_enet_clear_csum(skb, ndev)) {
470 dev_kfree_skb_any(skb);
474 /* Fill in a Tx ring entry */
476 status = bdp->cbd_sc;
477 status &= ~BD_ENET_TX_STATS;
479 /* Set buffer length and buffer pointer */
481 buflen = skb_headlen(skb);
483 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
484 if (((unsigned long) bufaddr) & FEC_ALIGNMENT ||
485 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
486 memcpy(fep->tx_bounce[index], skb->data, buflen);
487 bufaddr = fep->tx_bounce[index];
489 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
490 swap_buffer(bufaddr, buflen);
493 /* Push the data cache so the CPM does not get stale memory
496 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
497 buflen, DMA_TO_DEVICE);
498 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
499 dev_kfree_skb_any(skb);
501 netdev_err(ndev, "Tx DMA memory map failed\n");
506 ret = fec_enet_txq_submit_frag_skb(skb, ndev);
510 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
511 if (fep->bufdesc_ex) {
512 estatus = BD_ENET_TX_INT;
513 if (unlikely(skb_shinfo(skb)->tx_flags &
514 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
515 estatus |= BD_ENET_TX_TS;
519 if (fep->bufdesc_ex) {
521 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
523 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
525 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
527 if (skb->ip_summed == CHECKSUM_PARTIAL)
528 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
531 ebdp->cbd_esc = estatus;
534 last_bdp = fep->cur_tx;
535 index = fec_enet_get_bd_index(fep->tx_bd_base, last_bdp, fep);
536 /* Save skb pointer */
537 fep->tx_skbuff[index] = skb;
539 bdp->cbd_datlen = buflen;
541 /* Send it on its way. Tell FEC it's ready, interrupt when done,
542 * it's the last BD of the frame, and to put the CRC on the end.
544 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
545 bdp->cbd_sc = status;
547 fec_enet_submit_work(bdp, fep);
549 /* If this was the last BD in the ring, start at the beginning again. */
550 bdp = fec_enet_get_nextdesc(last_bdp, fep);
552 skb_tx_timestamp(skb);
556 /* Trigger transmission start */
557 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
563 fec_enet_txq_put_data_tso(struct sk_buff *skb, struct net_device *ndev,
564 struct bufdesc *bdp, int index, char *data,
565 int size, bool last_tcp, bool is_last)
567 struct fec_enet_private *fep = netdev_priv(ndev);
568 const struct platform_device_id *id_entry =
569 platform_get_device_id(fep->pdev);
570 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
571 unsigned short status;
572 unsigned int estatus = 0;
574 status = bdp->cbd_sc;
575 status &= ~BD_ENET_TX_STATS;
577 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
578 bdp->cbd_datlen = size;
580 if (((unsigned long) data) & FEC_ALIGNMENT ||
581 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
582 memcpy(fep->tx_bounce[index], data, size);
583 data = fep->tx_bounce[index];
585 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
586 swap_buffer(data, size);
589 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
590 size, DMA_TO_DEVICE);
591 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
592 dev_kfree_skb_any(skb);
594 netdev_err(ndev, "Tx DMA memory map failed\n");
595 return NETDEV_TX_BUSY;
598 if (fep->bufdesc_ex) {
599 if (skb->ip_summed == CHECKSUM_PARTIAL)
600 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
602 ebdp->cbd_esc = estatus;
605 /* Handle the last BD specially */
607 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
609 status |= BD_ENET_TX_INTR;
611 ebdp->cbd_esc |= BD_ENET_TX_INT;
614 bdp->cbd_sc = status;
620 fec_enet_txq_put_hdr_tso(struct sk_buff *skb, struct net_device *ndev,
621 struct bufdesc *bdp, int index)
623 struct fec_enet_private *fep = netdev_priv(ndev);
624 const struct platform_device_id *id_entry =
625 platform_get_device_id(fep->pdev);
626 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
627 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
629 unsigned long dmabuf;
630 unsigned short status;
631 unsigned int estatus = 0;
633 status = bdp->cbd_sc;
634 status &= ~BD_ENET_TX_STATS;
635 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
637 bufaddr = fep->tso_hdrs + index * TSO_HEADER_SIZE;
638 dmabuf = fep->tso_hdrs_dma + index * TSO_HEADER_SIZE;
639 if (((unsigned long) bufaddr) & FEC_ALIGNMENT ||
640 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
641 memcpy(fep->tx_bounce[index], skb->data, hdr_len);
642 bufaddr = fep->tx_bounce[index];
644 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
645 swap_buffer(bufaddr, hdr_len);
647 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
648 hdr_len, DMA_TO_DEVICE);
649 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
650 dev_kfree_skb_any(skb);
652 netdev_err(ndev, "Tx DMA memory map failed\n");
653 return NETDEV_TX_BUSY;
657 bdp->cbd_bufaddr = dmabuf;
658 bdp->cbd_datlen = hdr_len;
660 if (fep->bufdesc_ex) {
661 if (skb->ip_summed == CHECKSUM_PARTIAL)
662 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
664 ebdp->cbd_esc = estatus;
667 bdp->cbd_sc = status;
672 static int fec_enet_txq_submit_tso(struct sk_buff *skb, struct net_device *ndev)
674 struct fec_enet_private *fep = netdev_priv(ndev);
675 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
676 int total_len, data_left;
677 struct bufdesc *bdp = fep->cur_tx;
679 unsigned int index = 0;
682 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep)) {
683 dev_kfree_skb_any(skb);
685 netdev_err(ndev, "NOT enough BD for TSO!\n");
689 /* Protocol checksum off-load for TCP and UDP. */
690 if (fec_enet_clear_csum(skb, ndev)) {
691 dev_kfree_skb_any(skb);
695 /* Initialize the TSO handler, and prepare the first payload */
696 tso_start(skb, &tso);
698 total_len = skb->len - hdr_len;
699 while (total_len > 0) {
702 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
703 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
704 total_len -= data_left;
706 /* prepare packet headers: MAC + IP + TCP */
707 hdr = fep->tso_hdrs + index * TSO_HEADER_SIZE;
708 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
709 ret = fec_enet_txq_put_hdr_tso(skb, ndev, bdp, index);
713 while (data_left > 0) {
716 size = min_t(int, tso.size, data_left);
717 bdp = fec_enet_get_nextdesc(bdp, fep);
718 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
719 ret = fec_enet_txq_put_data_tso(skb, ndev, bdp, index, tso.data,
720 size, size == data_left,
726 tso_build_data(skb, &tso, size);
729 bdp = fec_enet_get_nextdesc(bdp, fep);
732 /* Save skb pointer */
733 fep->tx_skbuff[index] = skb;
735 fec_enet_submit_work(bdp, fep);
737 skb_tx_timestamp(skb);
740 /* Trigger transmission start */
741 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
746 /* TODO: Release all used data descriptors for TSO */
751 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
753 struct fec_enet_private *fep = netdev_priv(ndev);
758 ret = fec_enet_txq_submit_tso(skb, ndev);
760 ret = fec_enet_txq_submit_skb(skb, ndev);
764 entries_free = fec_enet_get_free_txdesc_num(fep);
765 if (entries_free <= fep->tx_stop_threshold)
766 netif_stop_queue(ndev);
771 /* Init RX & TX buffer descriptors
773 static void fec_enet_bd_init(struct net_device *dev)
775 struct fec_enet_private *fep = netdev_priv(dev);
779 /* Initialize the receive buffer descriptors. */
780 bdp = fep->rx_bd_base;
781 for (i = 0; i < fep->rx_ring_size; i++) {
783 /* Initialize the BD for every fragment in the page. */
784 if (bdp->cbd_bufaddr)
785 bdp->cbd_sc = BD_ENET_RX_EMPTY;
788 bdp = fec_enet_get_nextdesc(bdp, fep);
791 /* Set the last buffer to wrap */
792 bdp = fec_enet_get_prevdesc(bdp, fep);
793 bdp->cbd_sc |= BD_SC_WRAP;
795 fep->cur_rx = fep->rx_bd_base;
797 /* ...and the same for transmit */
798 bdp = fep->tx_bd_base;
800 for (i = 0; i < fep->tx_ring_size; i++) {
802 /* Initialize the BD for every fragment in the page. */
804 if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) {
805 dev_kfree_skb_any(fep->tx_skbuff[i]);
806 fep->tx_skbuff[i] = NULL;
808 bdp->cbd_bufaddr = 0;
809 bdp = fec_enet_get_nextdesc(bdp, fep);
812 /* Set the last buffer to wrap */
813 bdp = fec_enet_get_prevdesc(bdp, fep);
814 bdp->cbd_sc |= BD_SC_WRAP;
818 /* This function is called to start or restart the FEC during a link
819 * change. This only happens when switching between half and full
823 fec_restart(struct net_device *ndev, int duplex)
825 struct fec_enet_private *fep = netdev_priv(ndev);
826 const struct platform_device_id *id_entry =
827 platform_get_device_id(fep->pdev);
831 u32 rcntl = OPT_FRAME_SIZE | 0x04;
832 u32 ecntl = 0x2; /* ETHEREN */
834 if (netif_running(ndev)) {
835 netif_device_detach(ndev);
836 napi_disable(&fep->napi);
837 netif_stop_queue(ndev);
838 netif_tx_lock_bh(ndev);
841 /* Whack a reset. We should wait for this. */
842 writel(1, fep->hwp + FEC_ECNTRL);
846 * enet-mac reset will reset mac address registers too,
847 * so need to reconfigure it.
849 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
850 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
851 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
852 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
855 /* Clear any outstanding interrupt. */
856 writel(0xffc00000, fep->hwp + FEC_IEVENT);
858 /* Set maximum receive buffer size. */
859 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
861 fec_enet_bd_init(ndev);
863 /* Set receive and transmit descriptor base. */
864 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
866 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
867 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
869 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
870 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
873 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
874 if (fep->tx_skbuff[i]) {
875 dev_kfree_skb_any(fep->tx_skbuff[i]);
876 fep->tx_skbuff[i] = NULL;
880 /* Enable MII mode */
883 writel(0x04, fep->hwp + FEC_X_CNTRL);
887 writel(0x0, fep->hwp + FEC_X_CNTRL);
890 fep->full_duplex = duplex;
893 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
895 #if !defined(CONFIG_M5272)
896 /* set RX checksum */
897 val = readl(fep->hwp + FEC_RACC);
898 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
899 val |= FEC_RACC_OPTIONS;
901 val &= ~FEC_RACC_OPTIONS;
902 writel(val, fep->hwp + FEC_RACC);
906 * The phy interface and speed need to get configured
907 * differently on enet-mac.
909 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
910 /* Enable flow control and length check */
911 rcntl |= 0x40000000 | 0x00000020;
913 /* RGMII, RMII or MII */
914 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
916 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
921 /* 1G, 100M or 10M */
923 if (fep->phy_dev->speed == SPEED_1000)
925 else if (fep->phy_dev->speed == SPEED_100)
931 #ifdef FEC_MIIGSK_ENR
932 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
934 /* disable the gasket and wait */
935 writel(0, fep->hwp + FEC_MIIGSK_ENR);
936 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
940 * configure the gasket:
941 * RMII, 50 MHz, no loopback, no echo
942 * MII, 25 MHz, no loopback, no echo
944 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
945 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
946 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
947 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
948 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
950 /* re-enable the gasket */
951 writel(2, fep->hwp + FEC_MIIGSK_ENR);
956 #if !defined(CONFIG_M5272)
957 /* enable pause frame*/
958 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
959 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
960 fep->phy_dev && fep->phy_dev->pause)) {
961 rcntl |= FEC_ENET_FCE;
963 /* set FIFO threshold parameter to reduce overrun */
964 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
965 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
966 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
967 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
970 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
972 rcntl &= ~FEC_ENET_FCE;
974 #endif /* !defined(CONFIG_M5272) */
976 writel(rcntl, fep->hwp + FEC_R_CNTRL);
978 /* Setup multicast filter. */
979 set_multicast_list(ndev);
981 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
982 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
985 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
986 /* enable ENET endian swap */
988 /* enable ENET store and forward mode */
989 writel(1 << 8, fep->hwp + FEC_X_WMRK);
996 /* Enable the MIB statistic event counters */
997 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1000 /* And last, enable the transmit and receive processing */
1001 writel(ecntl, fep->hwp + FEC_ECNTRL);
1002 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
1004 if (fep->bufdesc_ex)
1005 fec_ptp_start_cyclecounter(ndev);
1007 /* Enable interrupts we wish to service */
1008 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1010 if (netif_running(ndev)) {
1011 netif_tx_unlock_bh(ndev);
1012 netif_wake_queue(ndev);
1013 napi_enable(&fep->napi);
1014 netif_device_attach(ndev);
1019 fec_stop(struct net_device *ndev)
1021 struct fec_enet_private *fep = netdev_priv(ndev);
1022 const struct platform_device_id *id_entry =
1023 platform_get_device_id(fep->pdev);
1024 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1026 /* We cannot expect a graceful transmit stop without link !!! */
1028 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1030 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1031 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1034 /* Whack a reset. We should wait for this. */
1035 writel(1, fep->hwp + FEC_ECNTRL);
1037 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1038 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1040 /* We have to keep ENET enabled to have MII interrupt stay working */
1041 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
1042 writel(2, fep->hwp + FEC_ECNTRL);
1043 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1049 fec_timeout(struct net_device *ndev)
1051 struct fec_enet_private *fep = netdev_priv(ndev);
1053 ndev->stats.tx_errors++;
1055 fep->delay_work.timeout = true;
1056 schedule_delayed_work(&(fep->delay_work.delay_work), 0);
1059 static void fec_enet_work(struct work_struct *work)
1061 struct fec_enet_private *fep =
1063 struct fec_enet_private,
1064 delay_work.delay_work.work);
1066 if (fep->delay_work.timeout) {
1067 fep->delay_work.timeout = false;
1068 fec_restart(fep->netdev, fep->full_duplex);
1069 netif_wake_queue(fep->netdev);
1072 if (fep->delay_work.trig_tx) {
1073 fep->delay_work.trig_tx = false;
1074 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
1079 fec_enet_tx(struct net_device *ndev)
1081 struct fec_enet_private *fep;
1082 struct bufdesc *bdp;
1083 unsigned short status;
1084 struct sk_buff *skb;
1088 fep = netdev_priv(ndev);
1089 bdp = fep->dirty_tx;
1091 /* get next bdp of dirty_tx */
1092 bdp = fec_enet_get_nextdesc(bdp, fep);
1094 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
1096 /* current queue is empty */
1097 if (bdp == fep->cur_tx)
1100 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
1102 skb = fep->tx_skbuff[index];
1103 if (!IS_TSO_HEADER(fep, bdp->cbd_bufaddr))
1104 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1105 bdp->cbd_datlen, DMA_TO_DEVICE);
1106 bdp->cbd_bufaddr = 0;
1108 bdp = fec_enet_get_nextdesc(bdp, fep);
1112 /* Check for errors. */
1113 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1114 BD_ENET_TX_RL | BD_ENET_TX_UN |
1116 ndev->stats.tx_errors++;
1117 if (status & BD_ENET_TX_HB) /* No heartbeat */
1118 ndev->stats.tx_heartbeat_errors++;
1119 if (status & BD_ENET_TX_LC) /* Late collision */
1120 ndev->stats.tx_window_errors++;
1121 if (status & BD_ENET_TX_RL) /* Retrans limit */
1122 ndev->stats.tx_aborted_errors++;
1123 if (status & BD_ENET_TX_UN) /* Underrun */
1124 ndev->stats.tx_fifo_errors++;
1125 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1126 ndev->stats.tx_carrier_errors++;
1128 ndev->stats.tx_packets++;
1129 ndev->stats.tx_bytes += skb->len;
1132 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1134 struct skb_shared_hwtstamps shhwtstamps;
1135 unsigned long flags;
1136 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1138 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
1139 spin_lock_irqsave(&fep->tmreg_lock, flags);
1140 shhwtstamps.hwtstamp = ns_to_ktime(
1141 timecounter_cyc2time(&fep->tc, ebdp->ts));
1142 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1143 skb_tstamp_tx(skb, &shhwtstamps);
1146 if (status & BD_ENET_TX_READY)
1147 netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n");
1149 /* Deferred means some collisions occurred during transmit,
1150 * but we eventually sent the packet OK.
1152 if (status & BD_ENET_TX_DEF)
1153 ndev->stats.collisions++;
1155 /* Free the sk buffer associated with this last transmit */
1156 dev_kfree_skb_any(skb);
1157 fep->tx_skbuff[index] = NULL;
1159 fep->dirty_tx = bdp;
1161 /* Update pointer to next buffer descriptor to be transmitted */
1162 bdp = fec_enet_get_nextdesc(bdp, fep);
1164 /* Since we have freed up a buffer, the ring is no longer full
1166 if (netif_queue_stopped(ndev)) {
1167 entries_free = fec_enet_get_free_txdesc_num(fep);
1168 if (entries_free >= fep->tx_wake_threshold)
1169 netif_wake_queue(ndev);
1175 /* During a receive, the cur_rx points to the current incoming buffer.
1176 * When we update through the ring, if the next incoming buffer has
1177 * not been given to the system, we just set the empty indicator,
1178 * effectively tossing the packet.
1181 fec_enet_rx(struct net_device *ndev, int budget)
1183 struct fec_enet_private *fep = netdev_priv(ndev);
1184 const struct platform_device_id *id_entry =
1185 platform_get_device_id(fep->pdev);
1186 struct bufdesc *bdp;
1187 unsigned short status;
1188 struct sk_buff *skb;
1191 int pkt_received = 0;
1192 struct bufdesc_ex *ebdp = NULL;
1193 bool vlan_packet_rcvd = false;
1201 /* First, grab all of the stats for the incoming packet.
1202 * These get messed up if we get called due to a busy condition.
1206 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
1208 if (pkt_received >= budget)
1212 /* Since we have allocated space to hold a complete frame,
1213 * the last indicator should be set.
1215 if ((status & BD_ENET_RX_LAST) == 0)
1216 netdev_err(ndev, "rcv is not +last\n");
1219 goto rx_processing_done;
1221 /* Check for errors. */
1222 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1223 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
1224 ndev->stats.rx_errors++;
1225 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
1226 /* Frame too long or too short. */
1227 ndev->stats.rx_length_errors++;
1229 if (status & BD_ENET_RX_NO) /* Frame alignment */
1230 ndev->stats.rx_frame_errors++;
1231 if (status & BD_ENET_RX_CR) /* CRC Error */
1232 ndev->stats.rx_crc_errors++;
1233 if (status & BD_ENET_RX_OV) /* FIFO overrun */
1234 ndev->stats.rx_fifo_errors++;
1237 /* Report late collisions as a frame error.
1238 * On this error, the BD is closed, but we don't know what we
1239 * have in the buffer. So, just drop this frame on the floor.
1241 if (status & BD_ENET_RX_CL) {
1242 ndev->stats.rx_errors++;
1243 ndev->stats.rx_frame_errors++;
1244 goto rx_processing_done;
1247 /* Process the incoming frame. */
1248 ndev->stats.rx_packets++;
1249 pkt_len = bdp->cbd_datlen;
1250 ndev->stats.rx_bytes += pkt_len;
1252 index = fec_enet_get_bd_index(fep->rx_bd_base, bdp, fep);
1253 data = fep->rx_skbuff[index]->data;
1254 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
1255 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1257 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
1258 swap_buffer(data, pkt_len);
1260 /* Extract the enhanced buffer descriptor */
1262 if (fep->bufdesc_ex)
1263 ebdp = (struct bufdesc_ex *)bdp;
1265 /* If this is a VLAN packet remove the VLAN Tag */
1266 vlan_packet_rcvd = false;
1267 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1268 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
1269 /* Push and remove the vlan tag */
1270 struct vlan_hdr *vlan_header =
1271 (struct vlan_hdr *) (data + ETH_HLEN);
1272 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1273 pkt_len -= VLAN_HLEN;
1275 vlan_packet_rcvd = true;
1278 /* This does 16 byte alignment, exactly what we need.
1279 * The packet length includes FCS, but we don't want to
1280 * include that when passing upstream as it messes up
1281 * bridging applications.
1283 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
1285 if (unlikely(!skb)) {
1286 ndev->stats.rx_dropped++;
1288 int payload_offset = (2 * ETH_ALEN);
1289 skb_reserve(skb, NET_IP_ALIGN);
1290 skb_put(skb, pkt_len - 4); /* Make room */
1292 /* Extract the frame data without the VLAN header. */
1293 skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN));
1294 if (vlan_packet_rcvd)
1295 payload_offset = (2 * ETH_ALEN) + VLAN_HLEN;
1296 skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN),
1297 data + payload_offset,
1298 pkt_len - 4 - (2 * ETH_ALEN));
1300 skb->protocol = eth_type_trans(skb, ndev);
1302 /* Get receive timestamp from the skb */
1303 if (fep->hwts_rx_en && fep->bufdesc_ex) {
1304 struct skb_shared_hwtstamps *shhwtstamps =
1306 unsigned long flags;
1308 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
1310 spin_lock_irqsave(&fep->tmreg_lock, flags);
1311 shhwtstamps->hwtstamp = ns_to_ktime(
1312 timecounter_cyc2time(&fep->tc, ebdp->ts));
1313 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1316 if (fep->bufdesc_ex &&
1317 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1318 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
1319 /* don't check it */
1320 skb->ip_summed = CHECKSUM_UNNECESSARY;
1322 skb_checksum_none_assert(skb);
1326 /* Handle received VLAN packets */
1327 if (vlan_packet_rcvd)
1328 __vlan_hwaccel_put_tag(skb,
1332 napi_gro_receive(&fep->napi, skb);
1335 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
1336 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1338 /* Clear the status flags for this buffer */
1339 status &= ~BD_ENET_RX_STATS;
1341 /* Mark the buffer empty */
1342 status |= BD_ENET_RX_EMPTY;
1343 bdp->cbd_sc = status;
1345 if (fep->bufdesc_ex) {
1346 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1348 ebdp->cbd_esc = BD_ENET_RX_INT;
1353 /* Update BD pointer to next entry */
1354 bdp = fec_enet_get_nextdesc(bdp, fep);
1356 /* Doing this here will keep the FEC running while we process
1357 * incoming frames. On a heavily loaded network, we should be
1358 * able to keep up at the expense of system resources.
1360 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
1364 return pkt_received;
1368 fec_enet_interrupt(int irq, void *dev_id)
1370 struct net_device *ndev = dev_id;
1371 struct fec_enet_private *fep = netdev_priv(ndev);
1372 const unsigned napi_mask = FEC_ENET_RXF | FEC_ENET_TXF;
1374 irqreturn_t ret = IRQ_NONE;
1376 int_events = readl(fep->hwp + FEC_IEVENT);
1377 writel(int_events & ~napi_mask, fep->hwp + FEC_IEVENT);
1379 if (int_events & napi_mask) {
1382 /* Disable the NAPI interrupts */
1383 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1384 napi_schedule(&fep->napi);
1387 if (int_events & FEC_ENET_MII) {
1389 complete(&fep->mdio_done);
1395 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1397 struct net_device *ndev = napi->dev;
1398 struct fec_enet_private *fep = netdev_priv(ndev);
1402 * Clear any pending transmit or receive interrupts before
1403 * processing the rings to avoid racing with the hardware.
1405 writel(FEC_ENET_RXF | FEC_ENET_TXF, fep->hwp + FEC_IEVENT);
1407 pkts = fec_enet_rx(ndev, budget);
1411 if (pkts < budget) {
1412 napi_complete(napi);
1413 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1418 /* ------------------------------------------------------------------------- */
1419 static void fec_get_mac(struct net_device *ndev)
1421 struct fec_enet_private *fep = netdev_priv(ndev);
1422 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1423 unsigned char *iap, tmpaddr[ETH_ALEN];
1426 * try to get mac address in following order:
1428 * 1) module parameter via kernel command line in form
1429 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1434 * 2) from device tree data
1436 if (!is_valid_ether_addr(iap)) {
1437 struct device_node *np = fep->pdev->dev.of_node;
1439 const char *mac = of_get_mac_address(np);
1441 iap = (unsigned char *) mac;
1446 * 3) from flash or fuse (via platform data)
1448 if (!is_valid_ether_addr(iap)) {
1451 iap = (unsigned char *)FEC_FLASHMAC;
1454 iap = (unsigned char *)&pdata->mac;
1459 * 4) FEC mac registers set by bootloader
1461 if (!is_valid_ether_addr(iap)) {
1462 *((__be32 *) &tmpaddr[0]) =
1463 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1464 *((__be16 *) &tmpaddr[4]) =
1465 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1470 * 5) random mac address
1472 if (!is_valid_ether_addr(iap)) {
1473 /* Report it and use a random ethernet address instead */
1474 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1475 eth_hw_addr_random(ndev);
1476 netdev_info(ndev, "Using random MAC address: %pM\n",
1481 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1483 /* Adjust MAC if using macaddr */
1485 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1488 /* ------------------------------------------------------------------------- */
1493 static void fec_enet_adjust_link(struct net_device *ndev)
1495 struct fec_enet_private *fep = netdev_priv(ndev);
1496 struct phy_device *phy_dev = fep->phy_dev;
1497 int status_change = 0;
1499 /* Prevent a state halted on mii error */
1500 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1501 phy_dev->state = PHY_RESUMING;
1505 if (phy_dev->link) {
1507 fep->link = phy_dev->link;
1511 if (fep->full_duplex != phy_dev->duplex)
1514 if (phy_dev->speed != fep->speed) {
1515 fep->speed = phy_dev->speed;
1519 /* if any of the above changed restart the FEC */
1521 fec_restart(ndev, phy_dev->duplex);
1525 fep->link = phy_dev->link;
1531 phy_print_status(phy_dev);
1534 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1536 struct fec_enet_private *fep = bus->priv;
1537 unsigned long time_left;
1539 fep->mii_timeout = 0;
1540 init_completion(&fep->mdio_done);
1542 /* start a read op */
1543 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1544 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1545 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1547 /* wait for end of transfer */
1548 time_left = wait_for_completion_timeout(&fep->mdio_done,
1549 usecs_to_jiffies(FEC_MII_TIMEOUT));
1550 if (time_left == 0) {
1551 fep->mii_timeout = 1;
1552 netdev_err(fep->netdev, "MDIO read timeout\n");
1557 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1560 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1563 struct fec_enet_private *fep = bus->priv;
1564 unsigned long time_left;
1566 fep->mii_timeout = 0;
1567 init_completion(&fep->mdio_done);
1569 /* start a write op */
1570 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1571 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1572 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1573 fep->hwp + FEC_MII_DATA);
1575 /* wait for end of transfer */
1576 time_left = wait_for_completion_timeout(&fep->mdio_done,
1577 usecs_to_jiffies(FEC_MII_TIMEOUT));
1578 if (time_left == 0) {
1579 fep->mii_timeout = 1;
1580 netdev_err(fep->netdev, "MDIO write timeout\n");
1587 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1589 struct fec_enet_private *fep = netdev_priv(ndev);
1593 ret = clk_prepare_enable(fep->clk_ahb);
1596 ret = clk_prepare_enable(fep->clk_ipg);
1598 goto failed_clk_ipg;
1599 if (fep->clk_enet_out) {
1600 ret = clk_prepare_enable(fep->clk_enet_out);
1602 goto failed_clk_enet_out;
1605 ret = clk_prepare_enable(fep->clk_ptp);
1607 goto failed_clk_ptp;
1610 clk_disable_unprepare(fep->clk_ahb);
1611 clk_disable_unprepare(fep->clk_ipg);
1612 if (fep->clk_enet_out)
1613 clk_disable_unprepare(fep->clk_enet_out);
1615 clk_disable_unprepare(fep->clk_ptp);
1620 if (fep->clk_enet_out)
1621 clk_disable_unprepare(fep->clk_enet_out);
1622 failed_clk_enet_out:
1623 clk_disable_unprepare(fep->clk_ipg);
1625 clk_disable_unprepare(fep->clk_ahb);
1630 static int fec_enet_mii_probe(struct net_device *ndev)
1632 struct fec_enet_private *fep = netdev_priv(ndev);
1633 const struct platform_device_id *id_entry =
1634 platform_get_device_id(fep->pdev);
1635 struct phy_device *phy_dev = NULL;
1636 char mdio_bus_id[MII_BUS_ID_SIZE];
1637 char phy_name[MII_BUS_ID_SIZE + 3];
1639 int dev_id = fep->dev_id;
1641 fep->phy_dev = NULL;
1643 /* check for attached phy */
1644 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1645 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1647 if (fep->mii_bus->phy_map[phy_id] == NULL)
1649 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1653 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1657 if (phy_id >= PHY_MAX_ADDR) {
1658 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1659 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1663 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
1664 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1665 fep->phy_interface);
1666 if (IS_ERR(phy_dev)) {
1667 netdev_err(ndev, "could not attach to PHY\n");
1668 return PTR_ERR(phy_dev);
1671 /* mask with MAC supported features */
1672 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
1673 phy_dev->supported &= PHY_GBIT_FEATURES;
1674 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
1675 #if !defined(CONFIG_M5272)
1676 phy_dev->supported |= SUPPORTED_Pause;
1680 phy_dev->supported &= PHY_BASIC_FEATURES;
1682 phy_dev->advertising = phy_dev->supported;
1684 fep->phy_dev = phy_dev;
1686 fep->full_duplex = 0;
1688 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1689 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1695 static int fec_enet_mii_init(struct platform_device *pdev)
1697 static struct mii_bus *fec0_mii_bus;
1698 struct net_device *ndev = platform_get_drvdata(pdev);
1699 struct fec_enet_private *fep = netdev_priv(ndev);
1700 const struct platform_device_id *id_entry =
1701 platform_get_device_id(fep->pdev);
1702 int err = -ENXIO, i;
1705 * The dual fec interfaces are not equivalent with enet-mac.
1706 * Here are the differences:
1708 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1709 * - fec0 acts as the 1588 time master while fec1 is slave
1710 * - external phys can only be configured by fec0
1712 * That is to say fec1 can not work independently. It only works
1713 * when fec0 is working. The reason behind this design is that the
1714 * second interface is added primarily for Switch mode.
1716 * Because of the last point above, both phys are attached on fec0
1717 * mdio interface in board design, and need to be configured by
1720 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1721 /* fec1 uses fec0 mii_bus */
1722 if (mii_cnt && fec0_mii_bus) {
1723 fep->mii_bus = fec0_mii_bus;
1730 fep->mii_timeout = 0;
1733 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1735 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1736 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1737 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1740 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
1741 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1743 fep->phy_speed <<= 1;
1744 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1746 fep->mii_bus = mdiobus_alloc();
1747 if (fep->mii_bus == NULL) {
1752 fep->mii_bus->name = "fec_enet_mii_bus";
1753 fep->mii_bus->read = fec_enet_mdio_read;
1754 fep->mii_bus->write = fec_enet_mdio_write;
1755 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1756 pdev->name, fep->dev_id + 1);
1757 fep->mii_bus->priv = fep;
1758 fep->mii_bus->parent = &pdev->dev;
1760 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1761 if (!fep->mii_bus->irq) {
1763 goto err_out_free_mdiobus;
1766 for (i = 0; i < PHY_MAX_ADDR; i++)
1767 fep->mii_bus->irq[i] = PHY_POLL;
1769 if (mdiobus_register(fep->mii_bus))
1770 goto err_out_free_mdio_irq;
1774 /* save fec0 mii_bus */
1775 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1776 fec0_mii_bus = fep->mii_bus;
1780 err_out_free_mdio_irq:
1781 kfree(fep->mii_bus->irq);
1782 err_out_free_mdiobus:
1783 mdiobus_free(fep->mii_bus);
1788 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1790 if (--mii_cnt == 0) {
1791 mdiobus_unregister(fep->mii_bus);
1792 kfree(fep->mii_bus->irq);
1793 mdiobus_free(fep->mii_bus);
1797 static int fec_enet_get_settings(struct net_device *ndev,
1798 struct ethtool_cmd *cmd)
1800 struct fec_enet_private *fep = netdev_priv(ndev);
1801 struct phy_device *phydev = fep->phy_dev;
1806 return phy_ethtool_gset(phydev, cmd);
1809 static int fec_enet_set_settings(struct net_device *ndev,
1810 struct ethtool_cmd *cmd)
1812 struct fec_enet_private *fep = netdev_priv(ndev);
1813 struct phy_device *phydev = fep->phy_dev;
1818 return phy_ethtool_sset(phydev, cmd);
1821 static void fec_enet_get_drvinfo(struct net_device *ndev,
1822 struct ethtool_drvinfo *info)
1824 struct fec_enet_private *fep = netdev_priv(ndev);
1826 strlcpy(info->driver, fep->pdev->dev.driver->name,
1827 sizeof(info->driver));
1828 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
1829 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1832 static int fec_enet_get_ts_info(struct net_device *ndev,
1833 struct ethtool_ts_info *info)
1835 struct fec_enet_private *fep = netdev_priv(ndev);
1837 if (fep->bufdesc_ex) {
1839 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1840 SOF_TIMESTAMPING_RX_SOFTWARE |
1841 SOF_TIMESTAMPING_SOFTWARE |
1842 SOF_TIMESTAMPING_TX_HARDWARE |
1843 SOF_TIMESTAMPING_RX_HARDWARE |
1844 SOF_TIMESTAMPING_RAW_HARDWARE;
1846 info->phc_index = ptp_clock_index(fep->ptp_clock);
1848 info->phc_index = -1;
1850 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1851 (1 << HWTSTAMP_TX_ON);
1853 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1854 (1 << HWTSTAMP_FILTER_ALL);
1857 return ethtool_op_get_ts_info(ndev, info);
1861 #if !defined(CONFIG_M5272)
1863 static void fec_enet_get_pauseparam(struct net_device *ndev,
1864 struct ethtool_pauseparam *pause)
1866 struct fec_enet_private *fep = netdev_priv(ndev);
1868 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
1869 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
1870 pause->rx_pause = pause->tx_pause;
1873 static int fec_enet_set_pauseparam(struct net_device *ndev,
1874 struct ethtool_pauseparam *pause)
1876 struct fec_enet_private *fep = netdev_priv(ndev);
1878 if (pause->tx_pause != pause->rx_pause) {
1880 "hardware only support enable/disable both tx and rx");
1884 fep->pause_flag = 0;
1886 /* tx pause must be same as rx pause */
1887 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
1888 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
1890 if (pause->rx_pause || pause->autoneg) {
1891 fep->phy_dev->supported |= ADVERTISED_Pause;
1892 fep->phy_dev->advertising |= ADVERTISED_Pause;
1894 fep->phy_dev->supported &= ~ADVERTISED_Pause;
1895 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
1898 if (pause->autoneg) {
1899 if (netif_running(ndev))
1901 phy_start_aneg(fep->phy_dev);
1903 if (netif_running(ndev))
1904 fec_restart(ndev, fep->full_duplex);
1909 static const struct fec_stat {
1910 char name[ETH_GSTRING_LEN];
1914 { "tx_dropped", RMON_T_DROP },
1915 { "tx_packets", RMON_T_PACKETS },
1916 { "tx_broadcast", RMON_T_BC_PKT },
1917 { "tx_multicast", RMON_T_MC_PKT },
1918 { "tx_crc_errors", RMON_T_CRC_ALIGN },
1919 { "tx_undersize", RMON_T_UNDERSIZE },
1920 { "tx_oversize", RMON_T_OVERSIZE },
1921 { "tx_fragment", RMON_T_FRAG },
1922 { "tx_jabber", RMON_T_JAB },
1923 { "tx_collision", RMON_T_COL },
1924 { "tx_64byte", RMON_T_P64 },
1925 { "tx_65to127byte", RMON_T_P65TO127 },
1926 { "tx_128to255byte", RMON_T_P128TO255 },
1927 { "tx_256to511byte", RMON_T_P256TO511 },
1928 { "tx_512to1023byte", RMON_T_P512TO1023 },
1929 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
1930 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
1931 { "tx_octets", RMON_T_OCTETS },
1934 { "IEEE_tx_drop", IEEE_T_DROP },
1935 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
1936 { "IEEE_tx_1col", IEEE_T_1COL },
1937 { "IEEE_tx_mcol", IEEE_T_MCOL },
1938 { "IEEE_tx_def", IEEE_T_DEF },
1939 { "IEEE_tx_lcol", IEEE_T_LCOL },
1940 { "IEEE_tx_excol", IEEE_T_EXCOL },
1941 { "IEEE_tx_macerr", IEEE_T_MACERR },
1942 { "IEEE_tx_cserr", IEEE_T_CSERR },
1943 { "IEEE_tx_sqe", IEEE_T_SQE },
1944 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
1945 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
1948 { "rx_packets", RMON_R_PACKETS },
1949 { "rx_broadcast", RMON_R_BC_PKT },
1950 { "rx_multicast", RMON_R_MC_PKT },
1951 { "rx_crc_errors", RMON_R_CRC_ALIGN },
1952 { "rx_undersize", RMON_R_UNDERSIZE },
1953 { "rx_oversize", RMON_R_OVERSIZE },
1954 { "rx_fragment", RMON_R_FRAG },
1955 { "rx_jabber", RMON_R_JAB },
1956 { "rx_64byte", RMON_R_P64 },
1957 { "rx_65to127byte", RMON_R_P65TO127 },
1958 { "rx_128to255byte", RMON_R_P128TO255 },
1959 { "rx_256to511byte", RMON_R_P256TO511 },
1960 { "rx_512to1023byte", RMON_R_P512TO1023 },
1961 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
1962 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
1963 { "rx_octets", RMON_R_OCTETS },
1966 { "IEEE_rx_drop", IEEE_R_DROP },
1967 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
1968 { "IEEE_rx_crc", IEEE_R_CRC },
1969 { "IEEE_rx_align", IEEE_R_ALIGN },
1970 { "IEEE_rx_macerr", IEEE_R_MACERR },
1971 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
1972 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
1975 static void fec_enet_get_ethtool_stats(struct net_device *dev,
1976 struct ethtool_stats *stats, u64 *data)
1978 struct fec_enet_private *fep = netdev_priv(dev);
1981 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1982 data[i] = readl(fep->hwp + fec_stats[i].offset);
1985 static void fec_enet_get_strings(struct net_device *netdev,
1986 u32 stringset, u8 *data)
1989 switch (stringset) {
1991 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1992 memcpy(data + i * ETH_GSTRING_LEN,
1993 fec_stats[i].name, ETH_GSTRING_LEN);
1998 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2002 return ARRAY_SIZE(fec_stats);
2007 #endif /* !defined(CONFIG_M5272) */
2009 static int fec_enet_nway_reset(struct net_device *dev)
2011 struct fec_enet_private *fep = netdev_priv(dev);
2012 struct phy_device *phydev = fep->phy_dev;
2017 return genphy_restart_aneg(phydev);
2020 static const struct ethtool_ops fec_enet_ethtool_ops = {
2021 #if !defined(CONFIG_M5272)
2022 .get_pauseparam = fec_enet_get_pauseparam,
2023 .set_pauseparam = fec_enet_set_pauseparam,
2025 .get_settings = fec_enet_get_settings,
2026 .set_settings = fec_enet_set_settings,
2027 .get_drvinfo = fec_enet_get_drvinfo,
2028 .get_link = ethtool_op_get_link,
2029 .get_ts_info = fec_enet_get_ts_info,
2030 .nway_reset = fec_enet_nway_reset,
2031 #ifndef CONFIG_M5272
2032 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2033 .get_strings = fec_enet_get_strings,
2034 .get_sset_count = fec_enet_get_sset_count,
2038 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2040 struct fec_enet_private *fep = netdev_priv(ndev);
2041 struct phy_device *phydev = fep->phy_dev;
2043 if (!netif_running(ndev))
2049 if (fep->bufdesc_ex) {
2050 if (cmd == SIOCSHWTSTAMP)
2051 return fec_ptp_set(ndev, rq);
2052 if (cmd == SIOCGHWTSTAMP)
2053 return fec_ptp_get(ndev, rq);
2056 return phy_mii_ioctl(phydev, rq, cmd);
2059 static void fec_enet_free_buffers(struct net_device *ndev)
2061 struct fec_enet_private *fep = netdev_priv(ndev);
2063 struct sk_buff *skb;
2064 struct bufdesc *bdp;
2066 bdp = fep->rx_bd_base;
2067 for (i = 0; i < fep->rx_ring_size; i++) {
2068 skb = fep->rx_skbuff[i];
2070 if (bdp->cbd_bufaddr)
2071 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
2072 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
2075 bdp = fec_enet_get_nextdesc(bdp, fep);
2078 bdp = fep->tx_bd_base;
2079 for (i = 0; i < fep->tx_ring_size; i++)
2080 kfree(fep->tx_bounce[i]);
2083 static int fec_enet_alloc_buffers(struct net_device *ndev)
2085 struct fec_enet_private *fep = netdev_priv(ndev);
2087 struct sk_buff *skb;
2088 struct bufdesc *bdp;
2090 bdp = fep->rx_bd_base;
2091 for (i = 0; i < fep->rx_ring_size; i++) {
2092 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2094 fec_enet_free_buffers(ndev);
2097 fep->rx_skbuff[i] = skb;
2099 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
2100 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
2101 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
2102 fec_enet_free_buffers(ndev);
2103 if (net_ratelimit())
2104 netdev_err(ndev, "Rx DMA memory map failed\n");
2107 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2109 if (fep->bufdesc_ex) {
2110 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2111 ebdp->cbd_esc = BD_ENET_RX_INT;
2114 bdp = fec_enet_get_nextdesc(bdp, fep);
2117 /* Set the last buffer to wrap. */
2118 bdp = fec_enet_get_prevdesc(bdp, fep);
2119 bdp->cbd_sc |= BD_SC_WRAP;
2121 bdp = fep->tx_bd_base;
2122 for (i = 0; i < fep->tx_ring_size; i++) {
2123 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2126 bdp->cbd_bufaddr = 0;
2128 if (fep->bufdesc_ex) {
2129 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2130 ebdp->cbd_esc = BD_ENET_TX_INT;
2133 bdp = fec_enet_get_nextdesc(bdp, fep);
2136 /* Set the last buffer to wrap. */
2137 bdp = fec_enet_get_prevdesc(bdp, fep);
2138 bdp->cbd_sc |= BD_SC_WRAP;
2144 fec_enet_open(struct net_device *ndev)
2146 struct fec_enet_private *fep = netdev_priv(ndev);
2149 pinctrl_pm_select_default_state(&fep->pdev->dev);
2150 ret = fec_enet_clk_enable(ndev, true);
2154 /* I should reset the ring buffers here, but I don't yet know
2155 * a simple way to do that.
2158 ret = fec_enet_alloc_buffers(ndev);
2162 /* Probe and connect to PHY when open the interface */
2163 ret = fec_enet_mii_probe(ndev);
2165 fec_enet_free_buffers(ndev);
2169 napi_enable(&fep->napi);
2170 phy_start(fep->phy_dev);
2171 netif_start_queue(ndev);
2177 fec_enet_close(struct net_device *ndev)
2179 struct fec_enet_private *fep = netdev_priv(ndev);
2181 /* Don't know what to do yet. */
2182 napi_disable(&fep->napi);
2184 netif_stop_queue(ndev);
2188 phy_stop(fep->phy_dev);
2189 phy_disconnect(fep->phy_dev);
2192 fec_enet_clk_enable(ndev, false);
2193 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2194 fec_enet_free_buffers(ndev);
2199 /* Set or clear the multicast filter for this adaptor.
2200 * Skeleton taken from sunlance driver.
2201 * The CPM Ethernet implementation allows Multicast as well as individual
2202 * MAC address filtering. Some of the drivers check to make sure it is
2203 * a group multicast address, and discard those that are not. I guess I
2204 * will do the same for now, but just remove the test if you want
2205 * individual filtering as well (do the upper net layers want or support
2206 * this kind of feature?).
2209 #define HASH_BITS 6 /* #bits in hash */
2210 #define CRC32_POLY 0xEDB88320
2212 static void set_multicast_list(struct net_device *ndev)
2214 struct fec_enet_private *fep = netdev_priv(ndev);
2215 struct netdev_hw_addr *ha;
2216 unsigned int i, bit, data, crc, tmp;
2219 if (ndev->flags & IFF_PROMISC) {
2220 tmp = readl(fep->hwp + FEC_R_CNTRL);
2222 writel(tmp, fep->hwp + FEC_R_CNTRL);
2226 tmp = readl(fep->hwp + FEC_R_CNTRL);
2228 writel(tmp, fep->hwp + FEC_R_CNTRL);
2230 if (ndev->flags & IFF_ALLMULTI) {
2231 /* Catch all multicast addresses, so set the
2234 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2235 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2240 /* Clear filter and add the addresses in hash register
2242 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2243 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2245 netdev_for_each_mc_addr(ha, ndev) {
2246 /* calculate crc32 value of mac address */
2249 for (i = 0; i < ndev->addr_len; i++) {
2251 for (bit = 0; bit < 8; bit++, data >>= 1) {
2253 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2257 /* only upper 6 bits (HASH_BITS) are used
2258 * which point to specific bit in he hash registers
2260 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2263 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2264 tmp |= 1 << (hash - 32);
2265 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2267 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2269 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2274 /* Set a MAC change in hardware. */
2276 fec_set_mac_address(struct net_device *ndev, void *p)
2278 struct fec_enet_private *fep = netdev_priv(ndev);
2279 struct sockaddr *addr = p;
2282 if (!is_valid_ether_addr(addr->sa_data))
2283 return -EADDRNOTAVAIL;
2284 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
2287 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
2288 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
2289 fep->hwp + FEC_ADDR_LOW);
2290 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
2291 fep->hwp + FEC_ADDR_HIGH);
2295 #ifdef CONFIG_NET_POLL_CONTROLLER
2297 * fec_poll_controller - FEC Poll controller function
2298 * @dev: The FEC network adapter
2300 * Polled functionality used by netconsole and others in non interrupt mode
2303 static void fec_poll_controller(struct net_device *dev)
2306 struct fec_enet_private *fep = netdev_priv(dev);
2308 for (i = 0; i < FEC_IRQ_NUM; i++) {
2309 if (fep->irq[i] > 0) {
2310 disable_irq(fep->irq[i]);
2311 fec_enet_interrupt(fep->irq[i], dev);
2312 enable_irq(fep->irq[i]);
2318 static int fec_set_features(struct net_device *netdev,
2319 netdev_features_t features)
2321 struct fec_enet_private *fep = netdev_priv(netdev);
2322 netdev_features_t changed = features ^ netdev->features;
2324 netdev->features = features;
2326 /* Receive checksum has been changed */
2327 if (changed & NETIF_F_RXCSUM) {
2328 if (features & NETIF_F_RXCSUM)
2329 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2331 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
2333 if (netif_running(netdev)) {
2335 fec_restart(netdev, fep->phy_dev->duplex);
2336 netif_wake_queue(netdev);
2338 fec_restart(netdev, fep->phy_dev->duplex);
2345 static const struct net_device_ops fec_netdev_ops = {
2346 .ndo_open = fec_enet_open,
2347 .ndo_stop = fec_enet_close,
2348 .ndo_start_xmit = fec_enet_start_xmit,
2349 .ndo_set_rx_mode = set_multicast_list,
2350 .ndo_change_mtu = eth_change_mtu,
2351 .ndo_validate_addr = eth_validate_addr,
2352 .ndo_tx_timeout = fec_timeout,
2353 .ndo_set_mac_address = fec_set_mac_address,
2354 .ndo_do_ioctl = fec_enet_ioctl,
2355 #ifdef CONFIG_NET_POLL_CONTROLLER
2356 .ndo_poll_controller = fec_poll_controller,
2358 .ndo_set_features = fec_set_features,
2362 * XXX: We need to clean up on failure exits here.
2365 static int fec_enet_init(struct net_device *ndev)
2367 struct fec_enet_private *fep = netdev_priv(ndev);
2368 const struct platform_device_id *id_entry =
2369 platform_get_device_id(fep->pdev);
2370 struct bufdesc *cbd_base;
2373 /* init the tx & rx ring size */
2374 fep->tx_ring_size = TX_RING_SIZE;
2375 fep->rx_ring_size = RX_RING_SIZE;
2377 fep->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2378 fep->tx_wake_threshold = (fep->tx_ring_size - fep->tx_stop_threshold) / 2;
2380 if (fep->bufdesc_ex)
2381 fep->bufdesc_size = sizeof(struct bufdesc_ex);
2383 fep->bufdesc_size = sizeof(struct bufdesc);
2384 bd_size = (fep->tx_ring_size + fep->rx_ring_size) *
2387 /* Allocate memory for buffer descriptors. */
2388 cbd_base = dma_alloc_coherent(NULL, bd_size, &fep->bd_dma,
2393 fep->tso_hdrs = dma_alloc_coherent(NULL, fep->tx_ring_size * TSO_HEADER_SIZE,
2394 &fep->tso_hdrs_dma, GFP_KERNEL);
2395 if (!fep->tso_hdrs) {
2396 dma_free_coherent(NULL, bd_size, cbd_base, fep->bd_dma);
2400 memset(cbd_base, 0, PAGE_SIZE);
2404 /* Get the Ethernet address */
2406 /* make sure MAC we just acquired is programmed into the hw */
2407 fec_set_mac_address(ndev, NULL);
2409 /* Set receive and transmit descriptor base. */
2410 fep->rx_bd_base = cbd_base;
2411 if (fep->bufdesc_ex)
2412 fep->tx_bd_base = (struct bufdesc *)
2413 (((struct bufdesc_ex *)cbd_base) + fep->rx_ring_size);
2415 fep->tx_bd_base = cbd_base + fep->rx_ring_size;
2417 /* The FEC Ethernet specific entries in the device structure */
2418 ndev->watchdog_timeo = TX_TIMEOUT;
2419 ndev->netdev_ops = &fec_netdev_ops;
2420 ndev->ethtool_ops = &fec_enet_ethtool_ops;
2422 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
2423 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
2425 if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN)
2426 /* enable hw VLAN support */
2427 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2429 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) {
2430 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
2432 /* enable hw accelerator */
2433 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
2434 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
2435 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2438 ndev->hw_features = ndev->features;
2440 fec_restart(ndev, 0);
2446 static void fec_reset_phy(struct platform_device *pdev)
2450 struct device_node *np = pdev->dev.of_node;
2455 of_property_read_u32(np, "phy-reset-duration", &msec);
2456 /* A sane reset duration should not be longer than 1s */
2460 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
2461 if (!gpio_is_valid(phy_reset))
2464 err = devm_gpio_request_one(&pdev->dev, phy_reset,
2465 GPIOF_OUT_INIT_LOW, "phy-reset");
2467 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
2471 gpio_set_value(phy_reset, 1);
2473 #else /* CONFIG_OF */
2474 static void fec_reset_phy(struct platform_device *pdev)
2477 * In case of platform probe, the reset has been done
2481 #endif /* CONFIG_OF */
2484 fec_probe(struct platform_device *pdev)
2486 struct fec_enet_private *fep;
2487 struct fec_platform_data *pdata;
2488 struct net_device *ndev;
2489 int i, irq, ret = 0;
2491 const struct of_device_id *of_id;
2494 of_id = of_match_device(fec_dt_ids, &pdev->dev);
2496 pdev->id_entry = of_id->data;
2498 /* Init network device */
2499 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
2503 SET_NETDEV_DEV(ndev, &pdev->dev);
2505 /* setup board info structure */
2506 fep = netdev_priv(ndev);
2508 #if !defined(CONFIG_M5272)
2509 /* default enable pause frame auto negotiation */
2510 if (pdev->id_entry &&
2511 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
2512 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
2515 /* Select default pin state */
2516 pinctrl_pm_select_default_state(&pdev->dev);
2518 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2519 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
2520 if (IS_ERR(fep->hwp)) {
2521 ret = PTR_ERR(fep->hwp);
2522 goto failed_ioremap;
2526 fep->dev_id = dev_id++;
2528 fep->bufdesc_ex = 0;
2530 platform_set_drvdata(pdev, ndev);
2532 ret = of_get_phy_mode(pdev->dev.of_node);
2534 pdata = dev_get_platdata(&pdev->dev);
2536 fep->phy_interface = pdata->phy;
2538 fep->phy_interface = PHY_INTERFACE_MODE_MII;
2540 fep->phy_interface = ret;
2543 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2544 if (IS_ERR(fep->clk_ipg)) {
2545 ret = PTR_ERR(fep->clk_ipg);
2549 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
2550 if (IS_ERR(fep->clk_ahb)) {
2551 ret = PTR_ERR(fep->clk_ahb);
2555 /* enet_out is optional, depends on board */
2556 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
2557 if (IS_ERR(fep->clk_enet_out))
2558 fep->clk_enet_out = NULL;
2560 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
2562 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
2563 if (IS_ERR(fep->clk_ptp)) {
2564 fep->clk_ptp = NULL;
2565 fep->bufdesc_ex = 0;
2568 ret = fec_enet_clk_enable(ndev, true);
2572 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
2573 if (!IS_ERR(fep->reg_phy)) {
2574 ret = regulator_enable(fep->reg_phy);
2577 "Failed to enable phy regulator: %d\n", ret);
2578 goto failed_regulator;
2581 fep->reg_phy = NULL;
2584 fec_reset_phy(pdev);
2586 if (fep->bufdesc_ex)
2589 ret = fec_enet_init(ndev);
2593 for (i = 0; i < FEC_IRQ_NUM; i++) {
2594 irq = platform_get_irq(pdev, i);
2601 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
2602 0, pdev->name, ndev);
2607 ret = fec_enet_mii_init(pdev);
2609 goto failed_mii_init;
2611 /* Carrier starts down, phylib will bring it up */
2612 netif_carrier_off(ndev);
2613 fec_enet_clk_enable(ndev, false);
2614 pinctrl_pm_select_sleep_state(&pdev->dev);
2616 ret = register_netdev(ndev);
2618 goto failed_register;
2620 if (fep->bufdesc_ex && fep->ptp_clock)
2621 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
2623 INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work);
2627 fec_enet_mii_remove(fep);
2632 regulator_disable(fep->reg_phy);
2634 fec_enet_clk_enable(ndev, false);
2643 fec_drv_remove(struct platform_device *pdev)
2645 struct net_device *ndev = platform_get_drvdata(pdev);
2646 struct fec_enet_private *fep = netdev_priv(ndev);
2648 cancel_delayed_work_sync(&(fep->delay_work.delay_work));
2649 unregister_netdev(ndev);
2650 fec_enet_mii_remove(fep);
2651 del_timer_sync(&fep->time_keep);
2653 regulator_disable(fep->reg_phy);
2655 ptp_clock_unregister(fep->ptp_clock);
2656 fec_enet_clk_enable(ndev, false);
2662 #ifdef CONFIG_PM_SLEEP
2664 fec_suspend(struct device *dev)
2666 struct net_device *ndev = dev_get_drvdata(dev);
2667 struct fec_enet_private *fep = netdev_priv(ndev);
2669 if (netif_running(ndev)) {
2671 netif_device_detach(ndev);
2673 fec_enet_clk_enable(ndev, false);
2674 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2677 regulator_disable(fep->reg_phy);
2683 fec_resume(struct device *dev)
2685 struct net_device *ndev = dev_get_drvdata(dev);
2686 struct fec_enet_private *fep = netdev_priv(ndev);
2690 ret = regulator_enable(fep->reg_phy);
2695 pinctrl_pm_select_default_state(&fep->pdev->dev);
2696 ret = fec_enet_clk_enable(ndev, true);
2700 if (netif_running(ndev)) {
2701 fec_restart(ndev, fep->full_duplex);
2702 netif_device_attach(ndev);
2709 regulator_disable(fep->reg_phy);
2712 #endif /* CONFIG_PM_SLEEP */
2714 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
2716 static struct platform_driver fec_driver = {
2718 .name = DRIVER_NAME,
2719 .owner = THIS_MODULE,
2721 .of_match_table = fec_dt_ids,
2723 .id_table = fec_devtype,
2725 .remove = fec_drv_remove,
2728 module_platform_driver(fec_driver);
2730 MODULE_ALIAS("platform:"DRIVER_NAME);
2731 MODULE_LICENSE("GPL");