2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/pci.h>
33 #include <linux/init.h>
34 #include <linux/delay.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
38 #include <linux/spinlock.h>
39 #include <linux/workqueue.h>
40 #include <linux/bitops.h>
42 #include <linux/irq.h>
43 #include <linux/clk.h>
44 #include <linux/platform_device.h>
45 #include <linux/phy.h>
46 #include <linux/fec.h>
48 #include <linux/of_device.h>
49 #include <linux/of_gpio.h>
50 #include <linux/of_net.h>
51 #include <linux/pinctrl/consumer.h>
52 #include <linux/regulator/consumer.h>
54 #include <asm/cacheflush.h>
57 #include <asm/coldfire.h>
58 #include <asm/mcfsim.h>
63 #if defined(CONFIG_ARM)
64 #define FEC_ALIGNMENT 0xf
66 #define FEC_ALIGNMENT 0x3
69 #define DRIVER_NAME "fec"
71 /* Controller is ENET-MAC */
72 #define FEC_QUIRK_ENET_MAC (1 << 0)
73 /* Controller needs driver to swap frame */
74 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
75 /* Controller uses gasket */
76 #define FEC_QUIRK_USE_GASKET (1 << 2)
77 /* Controller has GBIT support */
78 #define FEC_QUIRK_HAS_GBIT (1 << 3)
80 static struct platform_device_id fec_devtype[] = {
82 /* keep it for coldfire */
87 .driver_data = FEC_QUIRK_USE_GASKET,
93 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
96 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT,
101 MODULE_DEVICE_TABLE(platform, fec_devtype);
104 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
105 IMX27_FEC, /* runs on i.mx27/35/51 */
110 static const struct of_device_id fec_dt_ids[] = {
111 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
112 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
113 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
114 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
117 MODULE_DEVICE_TABLE(of, fec_dt_ids);
119 static unsigned char macaddr[ETH_ALEN];
120 module_param_array(macaddr, byte, NULL, 0);
121 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
123 #if defined(CONFIG_M5272)
125 * Some hardware gets it MAC address out of local flash memory.
126 * if this is non-zero then assume it is the address to get MAC from.
128 #if defined(CONFIG_NETtel)
129 #define FEC_FLASHMAC 0xf0006006
130 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
131 #define FEC_FLASHMAC 0xf0006000
132 #elif defined(CONFIG_CANCam)
133 #define FEC_FLASHMAC 0xf0020000
134 #elif defined (CONFIG_M5272C3)
135 #define FEC_FLASHMAC (0xffe04000 + 4)
136 #elif defined(CONFIG_MOD5272)
137 #define FEC_FLASHMAC 0xffc0406b
139 #define FEC_FLASHMAC 0
141 #endif /* CONFIG_M5272 */
143 /* The number of Tx and Rx buffers. These are allocated from the page
144 * pool. The code may assume these are power of two, so it it best
145 * to keep them that size.
146 * We don't need to allocate pages for the transmitter. We just use
147 * the skbuffer directly.
149 #define FEC_ENET_RX_PAGES 8
150 #define FEC_ENET_RX_FRSIZE 2048
151 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
152 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
153 #define FEC_ENET_TX_FRSIZE 2048
154 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
155 #define TX_RING_SIZE 16 /* Must be power of two */
156 #define TX_RING_MOD_MASK 15 /* for this to work */
158 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
159 #error "FEC: descriptor ring size constants too large"
162 /* Interrupt events/masks. */
163 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
164 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
165 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
166 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
167 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
168 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
169 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
170 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
171 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
172 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
174 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
176 /* The FEC stores dest/src/type, data, and checksum for receive packets.
178 #define PKT_MAXBUF_SIZE 1518
179 #define PKT_MINBUF_SIZE 64
180 #define PKT_MAXBLR_SIZE 1520
182 /* This device has up to three irqs on some platforms */
183 #define FEC_IRQ_NUM 3
186 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
187 * size bits. Other FEC hardware does not, so we need to take that into
188 * account when setting it.
190 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
191 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
192 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
194 #define OPT_FRAME_SIZE 0
197 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
198 * tx_bd_base always point to the base of the buffer descriptors. The
199 * cur_rx and cur_tx point to the currently available buffer.
200 * The dirty_tx tracks the current buffer that is being sent by the
201 * controller. The cur_tx and dirty_tx are equal under both completely
202 * empty and completely full conditions. The empty/ready indicator in
203 * the buffer descriptor determines the actual condition.
205 struct fec_enet_private {
206 /* Hardware registers of the FEC device */
209 struct net_device *netdev;
214 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
215 unsigned char *tx_bounce[TX_RING_SIZE];
216 struct sk_buff* tx_skbuff[TX_RING_SIZE];
217 struct sk_buff* rx_skbuff[RX_RING_SIZE];
221 /* CPM dual port RAM relative addresses */
223 /* Address of Rx and Tx buffers */
224 struct bufdesc *rx_bd_base;
225 struct bufdesc *tx_bd_base;
226 /* The next free ring entry */
227 struct bufdesc *cur_rx, *cur_tx;
228 /* The ring entries to be free()ed */
229 struct bufdesc *dirty_tx;
232 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
235 struct platform_device *pdev;
240 /* Phylib and MDIO interface */
241 struct mii_bus *mii_bus;
242 struct phy_device *phy_dev;
245 phy_interface_t phy_interface;
248 struct completion mdio_done;
249 int irq[FEC_IRQ_NUM];
252 /* FEC MII MMFR bits definition */
253 #define FEC_MMFR_ST (1 << 30)
254 #define FEC_MMFR_OP_READ (2 << 28)
255 #define FEC_MMFR_OP_WRITE (1 << 28)
256 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
257 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
258 #define FEC_MMFR_TA (2 << 16)
259 #define FEC_MMFR_DATA(v) (v & 0xffff)
261 #define FEC_MII_TIMEOUT 30000 /* us */
263 /* Transmitter timeout */
264 #define TX_TIMEOUT (2 * HZ)
268 static void *swap_buffer(void *bufaddr, int len)
271 unsigned int *buf = bufaddr;
273 for (i = 0; i < (len + 3) / 4; i++, buf++)
274 *buf = cpu_to_be32(*buf);
280 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
282 struct fec_enet_private *fep = netdev_priv(ndev);
283 const struct platform_device_id *id_entry =
284 platform_get_device_id(fep->pdev);
287 unsigned short status;
291 /* Link is down or autonegotiation is in progress. */
292 return NETDEV_TX_BUSY;
295 spin_lock_irqsave(&fep->hw_lock, flags);
296 /* Fill in a Tx ring entry */
299 status = bdp->cbd_sc;
301 if (status & BD_ENET_TX_READY) {
302 /* Ooops. All transmit buffers are full. Bail out.
303 * This should not happen, since ndev->tbusy should be set.
305 printk("%s: tx queue full!.\n", ndev->name);
306 spin_unlock_irqrestore(&fep->hw_lock, flags);
307 return NETDEV_TX_BUSY;
310 /* Clear all of the status flags */
311 status &= ~BD_ENET_TX_STATS;
313 /* Set buffer length and buffer pointer */
315 bdp->cbd_datlen = skb->len;
318 * On some FEC implementations data must be aligned on
319 * 4-byte boundaries. Use bounce buffers to copy data
320 * and get it aligned. Ugh.
322 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
324 index = bdp - fep->tx_bd_base;
325 memcpy(fep->tx_bounce[index], skb->data, skb->len);
326 bufaddr = fep->tx_bounce[index];
330 * Some design made an incorrect assumption on endian mode of
331 * the system that it's running on. As the result, driver has to
332 * swap every frame going to and coming from the controller.
334 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
335 swap_buffer(bufaddr, skb->len);
337 /* Save skb pointer */
338 fep->tx_skbuff[fep->skb_cur] = skb;
340 ndev->stats.tx_bytes += skb->len;
341 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
343 /* Push the data cache so the CPM does not get stale memory
346 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
347 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
349 /* Send it on its way. Tell FEC it's ready, interrupt when done,
350 * it's the last BD of the frame, and to put the CRC on the end.
352 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
353 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
354 bdp->cbd_sc = status;
356 /* Trigger transmission start */
357 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
359 /* If this was the last BD in the ring, start at the beginning again. */
360 if (status & BD_ENET_TX_WRAP)
361 bdp = fep->tx_bd_base;
365 if (bdp == fep->dirty_tx) {
367 netif_stop_queue(ndev);
372 skb_tx_timestamp(skb);
374 spin_unlock_irqrestore(&fep->hw_lock, flags);
379 /* This function is called to start or restart the FEC during a link
380 * change. This only happens when switching between half and full
384 fec_restart(struct net_device *ndev, int duplex)
386 struct fec_enet_private *fep = netdev_priv(ndev);
387 const struct platform_device_id *id_entry =
388 platform_get_device_id(fep->pdev);
391 u32 rcntl = OPT_FRAME_SIZE | 0x04;
392 u32 ecntl = 0x2; /* ETHEREN */
394 /* Whack a reset. We should wait for this. */
395 writel(1, fep->hwp + FEC_ECNTRL);
399 * enet-mac reset will reset mac address registers too,
400 * so need to reconfigure it.
402 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
403 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
404 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
405 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
408 /* Clear any outstanding interrupt. */
409 writel(0xffc00000, fep->hwp + FEC_IEVENT);
411 /* Reset all multicast. */
412 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
413 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
415 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
416 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
419 /* Set maximum receive buffer size. */
420 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
422 /* Set receive and transmit descriptor base. */
423 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
424 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE,
425 fep->hwp + FEC_X_DES_START);
427 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
428 fep->cur_rx = fep->rx_bd_base;
430 /* Reset SKB transmit buffers. */
431 fep->skb_cur = fep->skb_dirty = 0;
432 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
433 if (fep->tx_skbuff[i]) {
434 dev_kfree_skb_any(fep->tx_skbuff[i]);
435 fep->tx_skbuff[i] = NULL;
439 /* Enable MII mode */
442 writel(0x04, fep->hwp + FEC_X_CNTRL);
446 writel(0x0, fep->hwp + FEC_X_CNTRL);
449 fep->full_duplex = duplex;
452 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
455 * The phy interface and speed need to get configured
456 * differently on enet-mac.
458 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
459 /* Enable flow control and length check */
460 rcntl |= 0x40000000 | 0x00000020;
462 /* RGMII, RMII or MII */
463 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
465 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
470 /* 1G, 100M or 10M */
472 if (fep->phy_dev->speed == SPEED_1000)
474 else if (fep->phy_dev->speed == SPEED_100)
480 #ifdef FEC_MIIGSK_ENR
481 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
483 /* disable the gasket and wait */
484 writel(0, fep->hwp + FEC_MIIGSK_ENR);
485 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
489 * configure the gasket:
490 * RMII, 50 MHz, no loopback, no echo
491 * MII, 25 MHz, no loopback, no echo
493 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
494 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
495 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
496 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
497 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
499 /* re-enable the gasket */
500 writel(2, fep->hwp + FEC_MIIGSK_ENR);
504 writel(rcntl, fep->hwp + FEC_R_CNTRL);
506 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
507 /* enable ENET endian swap */
509 /* enable ENET store and forward mode */
510 writel(1 << 8, fep->hwp + FEC_X_WMRK);
513 /* And last, enable the transmit and receive processing */
514 writel(ecntl, fep->hwp + FEC_ECNTRL);
515 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
517 /* Enable interrupts we wish to service */
518 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
522 fec_stop(struct net_device *ndev)
524 struct fec_enet_private *fep = netdev_priv(ndev);
525 const struct platform_device_id *id_entry =
526 platform_get_device_id(fep->pdev);
527 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
529 /* We cannot expect a graceful transmit stop without link !!! */
531 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
533 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
534 printk("fec_stop : Graceful transmit stop did not complete !\n");
537 /* Whack a reset. We should wait for this. */
538 writel(1, fep->hwp + FEC_ECNTRL);
540 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
541 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
543 /* We have to keep ENET enabled to have MII interrupt stay working */
544 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
545 writel(2, fep->hwp + FEC_ECNTRL);
546 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
552 fec_timeout(struct net_device *ndev)
554 struct fec_enet_private *fep = netdev_priv(ndev);
556 ndev->stats.tx_errors++;
558 fec_restart(ndev, fep->full_duplex);
559 netif_wake_queue(ndev);
563 fec_enet_tx(struct net_device *ndev)
565 struct fec_enet_private *fep;
567 unsigned short status;
570 fep = netdev_priv(ndev);
571 spin_lock(&fep->hw_lock);
574 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
575 if (bdp == fep->cur_tx && fep->tx_full == 0)
578 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
579 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
580 bdp->cbd_bufaddr = 0;
582 skb = fep->tx_skbuff[fep->skb_dirty];
583 /* Check for errors. */
584 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
585 BD_ENET_TX_RL | BD_ENET_TX_UN |
587 ndev->stats.tx_errors++;
588 if (status & BD_ENET_TX_HB) /* No heartbeat */
589 ndev->stats.tx_heartbeat_errors++;
590 if (status & BD_ENET_TX_LC) /* Late collision */
591 ndev->stats.tx_window_errors++;
592 if (status & BD_ENET_TX_RL) /* Retrans limit */
593 ndev->stats.tx_aborted_errors++;
594 if (status & BD_ENET_TX_UN) /* Underrun */
595 ndev->stats.tx_fifo_errors++;
596 if (status & BD_ENET_TX_CSL) /* Carrier lost */
597 ndev->stats.tx_carrier_errors++;
599 ndev->stats.tx_packets++;
602 if (status & BD_ENET_TX_READY)
603 printk("HEY! Enet xmit interrupt and TX_READY.\n");
605 /* Deferred means some collisions occurred during transmit,
606 * but we eventually sent the packet OK.
608 if (status & BD_ENET_TX_DEF)
609 ndev->stats.collisions++;
611 /* Free the sk buffer associated with this last transmit */
612 dev_kfree_skb_any(skb);
613 fep->tx_skbuff[fep->skb_dirty] = NULL;
614 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
616 /* Update pointer to next buffer descriptor to be transmitted */
617 if (status & BD_ENET_TX_WRAP)
618 bdp = fep->tx_bd_base;
622 /* Since we have freed up a buffer, the ring is no longer full
626 if (netif_queue_stopped(ndev))
627 netif_wake_queue(ndev);
631 spin_unlock(&fep->hw_lock);
635 /* During a receive, the cur_rx points to the current incoming buffer.
636 * When we update through the ring, if the next incoming buffer has
637 * not been given to the system, we just set the empty indicator,
638 * effectively tossing the packet.
641 fec_enet_rx(struct net_device *ndev)
643 struct fec_enet_private *fep = netdev_priv(ndev);
644 const struct platform_device_id *id_entry =
645 platform_get_device_id(fep->pdev);
647 unsigned short status;
656 spin_lock(&fep->hw_lock);
658 /* First, grab all of the stats for the incoming packet.
659 * These get messed up if we get called due to a busy condition.
663 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
665 /* Since we have allocated space to hold a complete frame,
666 * the last indicator should be set.
668 if ((status & BD_ENET_RX_LAST) == 0)
669 printk("FEC ENET: rcv is not +last\n");
672 goto rx_processing_done;
674 /* Check for errors. */
675 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
676 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
677 ndev->stats.rx_errors++;
678 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
679 /* Frame too long or too short. */
680 ndev->stats.rx_length_errors++;
682 if (status & BD_ENET_RX_NO) /* Frame alignment */
683 ndev->stats.rx_frame_errors++;
684 if (status & BD_ENET_RX_CR) /* CRC Error */
685 ndev->stats.rx_crc_errors++;
686 if (status & BD_ENET_RX_OV) /* FIFO overrun */
687 ndev->stats.rx_fifo_errors++;
690 /* Report late collisions as a frame error.
691 * On this error, the BD is closed, but we don't know what we
692 * have in the buffer. So, just drop this frame on the floor.
694 if (status & BD_ENET_RX_CL) {
695 ndev->stats.rx_errors++;
696 ndev->stats.rx_frame_errors++;
697 goto rx_processing_done;
700 /* Process the incoming frame. */
701 ndev->stats.rx_packets++;
702 pkt_len = bdp->cbd_datlen;
703 ndev->stats.rx_bytes += pkt_len;
704 data = (__u8*)__va(bdp->cbd_bufaddr);
706 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
707 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
709 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
710 swap_buffer(data, pkt_len);
712 /* This does 16 byte alignment, exactly what we need.
713 * The packet length includes FCS, but we don't want to
714 * include that when passing upstream as it messes up
715 * bridging applications.
717 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
719 if (unlikely(!skb)) {
720 printk("%s: Memory squeeze, dropping packet.\n",
722 ndev->stats.rx_dropped++;
724 skb_reserve(skb, NET_IP_ALIGN);
725 skb_put(skb, pkt_len - 4); /* Make room */
726 skb_copy_to_linear_data(skb, data, pkt_len - 4);
727 skb->protocol = eth_type_trans(skb, ndev);
728 if (!skb_defer_rx_timestamp(skb))
732 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
733 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
735 /* Clear the status flags for this buffer */
736 status &= ~BD_ENET_RX_STATS;
738 /* Mark the buffer empty */
739 status |= BD_ENET_RX_EMPTY;
740 bdp->cbd_sc = status;
742 /* Update BD pointer to next entry */
743 if (status & BD_ENET_RX_WRAP)
744 bdp = fep->rx_bd_base;
747 /* Doing this here will keep the FEC running while we process
748 * incoming frames. On a heavily loaded network, we should be
749 * able to keep up at the expense of system resources.
751 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
755 spin_unlock(&fep->hw_lock);
759 fec_enet_interrupt(int irq, void *dev_id)
761 struct net_device *ndev = dev_id;
762 struct fec_enet_private *fep = netdev_priv(ndev);
764 irqreturn_t ret = IRQ_NONE;
767 int_events = readl(fep->hwp + FEC_IEVENT);
768 writel(int_events, fep->hwp + FEC_IEVENT);
770 if (int_events & FEC_ENET_RXF) {
775 /* Transmit OK, or non-fatal error. Update the buffer
776 * descriptors. FEC handles all errors, we just discover
777 * them as part of the transmit process.
779 if (int_events & FEC_ENET_TXF) {
784 if (int_events & FEC_ENET_MII) {
786 complete(&fep->mdio_done);
788 } while (int_events);
795 /* ------------------------------------------------------------------------- */
796 static void __inline__ fec_get_mac(struct net_device *ndev)
798 struct fec_enet_private *fep = netdev_priv(ndev);
799 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
800 unsigned char *iap, tmpaddr[ETH_ALEN];
803 * try to get mac address in following order:
805 * 1) module parameter via kernel command line in form
806 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
812 * 2) from device tree data
814 if (!is_valid_ether_addr(iap)) {
815 struct device_node *np = fep->pdev->dev.of_node;
817 const char *mac = of_get_mac_address(np);
819 iap = (unsigned char *) mac;
825 * 3) from flash or fuse (via platform data)
827 if (!is_valid_ether_addr(iap)) {
830 iap = (unsigned char *)FEC_FLASHMAC;
833 iap = (unsigned char *)&pdata->mac;
838 * 4) FEC mac registers set by bootloader
840 if (!is_valid_ether_addr(iap)) {
841 *((unsigned long *) &tmpaddr[0]) =
842 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
843 *((unsigned short *) &tmpaddr[4]) =
844 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
848 memcpy(ndev->dev_addr, iap, ETH_ALEN);
850 /* Adjust MAC if using macaddr */
852 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
855 /* ------------------------------------------------------------------------- */
860 static void fec_enet_adjust_link(struct net_device *ndev)
862 struct fec_enet_private *fep = netdev_priv(ndev);
863 struct phy_device *phy_dev = fep->phy_dev;
866 int status_change = 0;
868 spin_lock_irqsave(&fep->hw_lock, flags);
870 /* Prevent a state halted on mii error */
871 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
872 phy_dev->state = PHY_RESUMING;
876 /* Duplex link change */
878 if (fep->full_duplex != phy_dev->duplex) {
879 fec_restart(ndev, phy_dev->duplex);
880 /* prevent unnecessary second fec_restart() below */
881 fep->link = phy_dev->link;
886 /* Link on or off change */
887 if (phy_dev->link != fep->link) {
888 fep->link = phy_dev->link;
890 fec_restart(ndev, phy_dev->duplex);
897 spin_unlock_irqrestore(&fep->hw_lock, flags);
900 phy_print_status(phy_dev);
903 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
905 struct fec_enet_private *fep = bus->priv;
906 unsigned long time_left;
908 fep->mii_timeout = 0;
909 init_completion(&fep->mdio_done);
911 /* start a read op */
912 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
913 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
914 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
916 /* wait for end of transfer */
917 time_left = wait_for_completion_timeout(&fep->mdio_done,
918 usecs_to_jiffies(FEC_MII_TIMEOUT));
919 if (time_left == 0) {
920 fep->mii_timeout = 1;
921 printk(KERN_ERR "FEC: MDIO read timeout\n");
926 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
929 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
932 struct fec_enet_private *fep = bus->priv;
933 unsigned long time_left;
935 fep->mii_timeout = 0;
936 init_completion(&fep->mdio_done);
938 /* start a write op */
939 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
940 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
941 FEC_MMFR_TA | FEC_MMFR_DATA(value),
942 fep->hwp + FEC_MII_DATA);
944 /* wait for end of transfer */
945 time_left = wait_for_completion_timeout(&fep->mdio_done,
946 usecs_to_jiffies(FEC_MII_TIMEOUT));
947 if (time_left == 0) {
948 fep->mii_timeout = 1;
949 printk(KERN_ERR "FEC: MDIO write timeout\n");
956 static int fec_enet_mdio_reset(struct mii_bus *bus)
961 static int fec_enet_mii_probe(struct net_device *ndev)
963 struct fec_enet_private *fep = netdev_priv(ndev);
964 const struct platform_device_id *id_entry =
965 platform_get_device_id(fep->pdev);
966 struct phy_device *phy_dev = NULL;
967 char mdio_bus_id[MII_BUS_ID_SIZE];
968 char phy_name[MII_BUS_ID_SIZE + 3];
970 int dev_id = fep->dev_id;
974 /* check for attached phy */
975 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
976 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
978 if (fep->mii_bus->phy_map[phy_id] == NULL)
980 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
984 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
988 if (phy_id >= PHY_MAX_ADDR) {
990 "%s: no PHY, assuming direct connection to switch\n",
992 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
996 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
997 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 0,
999 if (IS_ERR(phy_dev)) {
1000 printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name);
1001 return PTR_ERR(phy_dev);
1004 /* mask with MAC supported features */
1005 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT)
1006 phy_dev->supported &= PHY_GBIT_FEATURES;
1008 phy_dev->supported &= PHY_BASIC_FEATURES;
1010 phy_dev->advertising = phy_dev->supported;
1012 fep->phy_dev = phy_dev;
1014 fep->full_duplex = 0;
1017 "%s: Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1019 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1025 static int fec_enet_mii_init(struct platform_device *pdev)
1027 static struct mii_bus *fec0_mii_bus;
1028 struct net_device *ndev = platform_get_drvdata(pdev);
1029 struct fec_enet_private *fep = netdev_priv(ndev);
1030 const struct platform_device_id *id_entry =
1031 platform_get_device_id(fep->pdev);
1032 int err = -ENXIO, i;
1035 * The dual fec interfaces are not equivalent with enet-mac.
1036 * Here are the differences:
1038 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1039 * - fec0 acts as the 1588 time master while fec1 is slave
1040 * - external phys can only be configured by fec0
1042 * That is to say fec1 can not work independently. It only works
1043 * when fec0 is working. The reason behind this design is that the
1044 * second interface is added primarily for Switch mode.
1046 * Because of the last point above, both phys are attached on fec0
1047 * mdio interface in board design, and need to be configured by
1050 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1051 /* fec1 uses fec0 mii_bus */
1052 if (mii_cnt && fec0_mii_bus) {
1053 fep->mii_bus = fec0_mii_bus;
1060 fep->mii_timeout = 0;
1063 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1065 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1066 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1067 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1070 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000);
1071 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1073 fep->phy_speed <<= 1;
1074 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1076 fep->mii_bus = mdiobus_alloc();
1077 if (fep->mii_bus == NULL) {
1082 fep->mii_bus->name = "fec_enet_mii_bus";
1083 fep->mii_bus->read = fec_enet_mdio_read;
1084 fep->mii_bus->write = fec_enet_mdio_write;
1085 fep->mii_bus->reset = fec_enet_mdio_reset;
1086 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1087 pdev->name, fep->dev_id + 1);
1088 fep->mii_bus->priv = fep;
1089 fep->mii_bus->parent = &pdev->dev;
1091 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1092 if (!fep->mii_bus->irq) {
1094 goto err_out_free_mdiobus;
1097 for (i = 0; i < PHY_MAX_ADDR; i++)
1098 fep->mii_bus->irq[i] = PHY_POLL;
1100 if (mdiobus_register(fep->mii_bus))
1101 goto err_out_free_mdio_irq;
1105 /* save fec0 mii_bus */
1106 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1107 fec0_mii_bus = fep->mii_bus;
1111 err_out_free_mdio_irq:
1112 kfree(fep->mii_bus->irq);
1113 err_out_free_mdiobus:
1114 mdiobus_free(fep->mii_bus);
1119 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1121 if (--mii_cnt == 0) {
1122 mdiobus_unregister(fep->mii_bus);
1123 kfree(fep->mii_bus->irq);
1124 mdiobus_free(fep->mii_bus);
1128 static int fec_enet_get_settings(struct net_device *ndev,
1129 struct ethtool_cmd *cmd)
1131 struct fec_enet_private *fep = netdev_priv(ndev);
1132 struct phy_device *phydev = fep->phy_dev;
1137 return phy_ethtool_gset(phydev, cmd);
1140 static int fec_enet_set_settings(struct net_device *ndev,
1141 struct ethtool_cmd *cmd)
1143 struct fec_enet_private *fep = netdev_priv(ndev);
1144 struct phy_device *phydev = fep->phy_dev;
1149 return phy_ethtool_sset(phydev, cmd);
1152 static void fec_enet_get_drvinfo(struct net_device *ndev,
1153 struct ethtool_drvinfo *info)
1155 struct fec_enet_private *fep = netdev_priv(ndev);
1157 strcpy(info->driver, fep->pdev->dev.driver->name);
1158 strcpy(info->version, "Revision: 1.0");
1159 strcpy(info->bus_info, dev_name(&ndev->dev));
1162 static const struct ethtool_ops fec_enet_ethtool_ops = {
1163 .get_settings = fec_enet_get_settings,
1164 .set_settings = fec_enet_set_settings,
1165 .get_drvinfo = fec_enet_get_drvinfo,
1166 .get_link = ethtool_op_get_link,
1167 .get_ts_info = ethtool_op_get_ts_info,
1170 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1172 struct fec_enet_private *fep = netdev_priv(ndev);
1173 struct phy_device *phydev = fep->phy_dev;
1175 if (!netif_running(ndev))
1181 return phy_mii_ioctl(phydev, rq, cmd);
1184 static void fec_enet_free_buffers(struct net_device *ndev)
1186 struct fec_enet_private *fep = netdev_priv(ndev);
1188 struct sk_buff *skb;
1189 struct bufdesc *bdp;
1191 bdp = fep->rx_bd_base;
1192 for (i = 0; i < RX_RING_SIZE; i++) {
1193 skb = fep->rx_skbuff[i];
1195 if (bdp->cbd_bufaddr)
1196 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1197 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1203 bdp = fep->tx_bd_base;
1204 for (i = 0; i < TX_RING_SIZE; i++)
1205 kfree(fep->tx_bounce[i]);
1208 static int fec_enet_alloc_buffers(struct net_device *ndev)
1210 struct fec_enet_private *fep = netdev_priv(ndev);
1212 struct sk_buff *skb;
1213 struct bufdesc *bdp;
1215 bdp = fep->rx_bd_base;
1216 for (i = 0; i < RX_RING_SIZE; i++) {
1217 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1219 fec_enet_free_buffers(ndev);
1222 fep->rx_skbuff[i] = skb;
1224 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1225 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1226 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1230 /* Set the last buffer to wrap. */
1232 bdp->cbd_sc |= BD_SC_WRAP;
1234 bdp = fep->tx_bd_base;
1235 for (i = 0; i < TX_RING_SIZE; i++) {
1236 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1239 bdp->cbd_bufaddr = 0;
1243 /* Set the last buffer to wrap. */
1245 bdp->cbd_sc |= BD_SC_WRAP;
1251 fec_enet_open(struct net_device *ndev)
1253 struct fec_enet_private *fep = netdev_priv(ndev);
1256 /* I should reset the ring buffers here, but I don't yet know
1257 * a simple way to do that.
1260 ret = fec_enet_alloc_buffers(ndev);
1264 /* Probe and connect to PHY when open the interface */
1265 ret = fec_enet_mii_probe(ndev);
1267 fec_enet_free_buffers(ndev);
1270 phy_start(fep->phy_dev);
1271 netif_start_queue(ndev);
1277 fec_enet_close(struct net_device *ndev)
1279 struct fec_enet_private *fep = netdev_priv(ndev);
1281 /* Don't know what to do yet. */
1283 netif_stop_queue(ndev);
1287 phy_stop(fep->phy_dev);
1288 phy_disconnect(fep->phy_dev);
1291 fec_enet_free_buffers(ndev);
1296 /* Set or clear the multicast filter for this adaptor.
1297 * Skeleton taken from sunlance driver.
1298 * The CPM Ethernet implementation allows Multicast as well as individual
1299 * MAC address filtering. Some of the drivers check to make sure it is
1300 * a group multicast address, and discard those that are not. I guess I
1301 * will do the same for now, but just remove the test if you want
1302 * individual filtering as well (do the upper net layers want or support
1303 * this kind of feature?).
1306 #define HASH_BITS 6 /* #bits in hash */
1307 #define CRC32_POLY 0xEDB88320
1309 static void set_multicast_list(struct net_device *ndev)
1311 struct fec_enet_private *fep = netdev_priv(ndev);
1312 struct netdev_hw_addr *ha;
1313 unsigned int i, bit, data, crc, tmp;
1316 if (ndev->flags & IFF_PROMISC) {
1317 tmp = readl(fep->hwp + FEC_R_CNTRL);
1319 writel(tmp, fep->hwp + FEC_R_CNTRL);
1323 tmp = readl(fep->hwp + FEC_R_CNTRL);
1325 writel(tmp, fep->hwp + FEC_R_CNTRL);
1327 if (ndev->flags & IFF_ALLMULTI) {
1328 /* Catch all multicast addresses, so set the
1331 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1332 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1337 /* Clear filter and add the addresses in hash register
1339 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1340 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1342 netdev_for_each_mc_addr(ha, ndev) {
1343 /* calculate crc32 value of mac address */
1346 for (i = 0; i < ndev->addr_len; i++) {
1348 for (bit = 0; bit < 8; bit++, data >>= 1) {
1350 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1354 /* only upper 6 bits (HASH_BITS) are used
1355 * which point to specific bit in he hash registers
1357 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1360 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1361 tmp |= 1 << (hash - 32);
1362 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1364 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1366 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1371 /* Set a MAC change in hardware. */
1373 fec_set_mac_address(struct net_device *ndev, void *p)
1375 struct fec_enet_private *fep = netdev_priv(ndev);
1376 struct sockaddr *addr = p;
1378 if (!is_valid_ether_addr(addr->sa_data))
1379 return -EADDRNOTAVAIL;
1381 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1383 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1384 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1385 fep->hwp + FEC_ADDR_LOW);
1386 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1387 fep->hwp + FEC_ADDR_HIGH);
1391 #ifdef CONFIG_NET_POLL_CONTROLLER
1393 * fec_poll_controller - FEC Poll controller function
1394 * @dev: The FEC network adapter
1396 * Polled functionality used by netconsole and others in non interrupt mode
1399 void fec_poll_controller(struct net_device *dev)
1402 struct fec_enet_private *fep = netdev_priv(dev);
1404 for (i = 0; i < FEC_IRQ_NUM; i++) {
1405 if (fep->irq[i] > 0) {
1406 disable_irq(fep->irq[i]);
1407 fec_enet_interrupt(fep->irq[i], dev);
1408 enable_irq(fep->irq[i]);
1414 static const struct net_device_ops fec_netdev_ops = {
1415 .ndo_open = fec_enet_open,
1416 .ndo_stop = fec_enet_close,
1417 .ndo_start_xmit = fec_enet_start_xmit,
1418 .ndo_set_rx_mode = set_multicast_list,
1419 .ndo_change_mtu = eth_change_mtu,
1420 .ndo_validate_addr = eth_validate_addr,
1421 .ndo_tx_timeout = fec_timeout,
1422 .ndo_set_mac_address = fec_set_mac_address,
1423 .ndo_do_ioctl = fec_enet_ioctl,
1424 #ifdef CONFIG_NET_POLL_CONTROLLER
1425 .ndo_poll_controller = fec_poll_controller,
1430 * XXX: We need to clean up on failure exits here.
1433 static int fec_enet_init(struct net_device *ndev)
1435 struct fec_enet_private *fep = netdev_priv(ndev);
1436 struct bufdesc *cbd_base;
1437 struct bufdesc *bdp;
1440 /* Allocate memory for buffer descriptors. */
1441 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1444 printk("FEC: allocate descriptor memory failed?\n");
1448 spin_lock_init(&fep->hw_lock);
1452 /* Get the Ethernet address */
1455 /* Set receive and transmit descriptor base. */
1456 fep->rx_bd_base = cbd_base;
1457 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1459 /* The FEC Ethernet specific entries in the device structure */
1460 ndev->watchdog_timeo = TX_TIMEOUT;
1461 ndev->netdev_ops = &fec_netdev_ops;
1462 ndev->ethtool_ops = &fec_enet_ethtool_ops;
1464 /* Initialize the receive buffer descriptors. */
1465 bdp = fep->rx_bd_base;
1466 for (i = 0; i < RX_RING_SIZE; i++) {
1468 /* Initialize the BD for every fragment in the page. */
1473 /* Set the last buffer to wrap */
1475 bdp->cbd_sc |= BD_SC_WRAP;
1477 /* ...and the same for transmit */
1478 bdp = fep->tx_bd_base;
1479 for (i = 0; i < TX_RING_SIZE; i++) {
1481 /* Initialize the BD for every fragment in the page. */
1483 bdp->cbd_bufaddr = 0;
1487 /* Set the last buffer to wrap */
1489 bdp->cbd_sc |= BD_SC_WRAP;
1491 fec_restart(ndev, 0);
1497 static int __devinit fec_get_phy_mode_dt(struct platform_device *pdev)
1499 struct device_node *np = pdev->dev.of_node;
1502 return of_get_phy_mode(np);
1507 static void __devinit fec_reset_phy(struct platform_device *pdev)
1511 struct device_node *np = pdev->dev.of_node;
1516 of_property_read_u32(np, "phy-reset-duration", &msec);
1517 /* A sane reset duration should not be longer than 1s */
1521 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
1522 err = devm_gpio_request_one(&pdev->dev, phy_reset,
1523 GPIOF_OUT_INIT_LOW, "phy-reset");
1525 pr_debug("FEC: failed to get gpio phy-reset: %d\n", err);
1529 gpio_set_value(phy_reset, 1);
1531 #else /* CONFIG_OF */
1532 static inline int fec_get_phy_mode_dt(struct platform_device *pdev)
1537 static inline void fec_reset_phy(struct platform_device *pdev)
1540 * In case of platform probe, the reset has been done
1544 #endif /* CONFIG_OF */
1546 static int __devinit
1547 fec_probe(struct platform_device *pdev)
1549 struct fec_enet_private *fep;
1550 struct fec_platform_data *pdata;
1551 struct net_device *ndev;
1552 int i, irq, ret = 0;
1554 const struct of_device_id *of_id;
1556 struct pinctrl *pinctrl;
1557 struct regulator *reg_phy;
1559 of_id = of_match_device(fec_dt_ids, &pdev->dev);
1561 pdev->id_entry = of_id->data;
1563 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1567 r = request_mem_region(r->start, resource_size(r), pdev->name);
1571 /* Init network device */
1572 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
1575 goto failed_alloc_etherdev;
1578 SET_NETDEV_DEV(ndev, &pdev->dev);
1580 /* setup board info structure */
1581 fep = netdev_priv(ndev);
1583 fep->hwp = ioremap(r->start, resource_size(r));
1585 fep->dev_id = dev_id++;
1589 goto failed_ioremap;
1592 platform_set_drvdata(pdev, ndev);
1594 ret = fec_get_phy_mode_dt(pdev);
1596 pdata = pdev->dev.platform_data;
1598 fep->phy_interface = pdata->phy;
1600 fep->phy_interface = PHY_INTERFACE_MODE_MII;
1602 fep->phy_interface = ret;
1605 for (i = 0; i < FEC_IRQ_NUM; i++) {
1606 irq = platform_get_irq(pdev, i);
1613 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
1616 irq = platform_get_irq(pdev, i);
1617 free_irq(irq, ndev);
1623 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1624 if (IS_ERR(pinctrl)) {
1625 ret = PTR_ERR(pinctrl);
1629 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1630 if (IS_ERR(fep->clk_ipg)) {
1631 ret = PTR_ERR(fep->clk_ipg);
1635 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1636 if (IS_ERR(fep->clk_ahb)) {
1637 ret = PTR_ERR(fep->clk_ahb);
1641 clk_prepare_enable(fep->clk_ahb);
1642 clk_prepare_enable(fep->clk_ipg);
1644 reg_phy = devm_regulator_get(&pdev->dev, "phy");
1645 if (!IS_ERR(reg_phy)) {
1646 ret = regulator_enable(reg_phy);
1649 "Failed to enable phy regulator: %d\n", ret);
1650 goto failed_regulator;
1654 fec_reset_phy(pdev);
1656 ret = fec_enet_init(ndev);
1660 ret = fec_enet_mii_init(pdev);
1662 goto failed_mii_init;
1664 /* Carrier starts down, phylib will bring it up */
1665 netif_carrier_off(ndev);
1667 ret = register_netdev(ndev);
1669 goto failed_register;
1674 fec_enet_mii_remove(fep);
1678 clk_disable_unprepare(fep->clk_ahb);
1679 clk_disable_unprepare(fep->clk_ipg);
1682 for (i = 0; i < FEC_IRQ_NUM; i++) {
1683 irq = platform_get_irq(pdev, i);
1685 free_irq(irq, ndev);
1691 failed_alloc_etherdev:
1692 release_mem_region(r->start, resource_size(r));
1697 static int __devexit
1698 fec_drv_remove(struct platform_device *pdev)
1700 struct net_device *ndev = platform_get_drvdata(pdev);
1701 struct fec_enet_private *fep = netdev_priv(ndev);
1705 unregister_netdev(ndev);
1706 fec_enet_mii_remove(fep);
1707 for (i = 0; i < FEC_IRQ_NUM; i++) {
1708 int irq = platform_get_irq(pdev, i);
1710 free_irq(irq, ndev);
1712 clk_disable_unprepare(fep->clk_ahb);
1713 clk_disable_unprepare(fep->clk_ipg);
1717 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1719 release_mem_region(r->start, resource_size(r));
1721 platform_set_drvdata(pdev, NULL);
1728 fec_suspend(struct device *dev)
1730 struct net_device *ndev = dev_get_drvdata(dev);
1731 struct fec_enet_private *fep = netdev_priv(ndev);
1733 if (netif_running(ndev)) {
1735 netif_device_detach(ndev);
1737 clk_disable_unprepare(fep->clk_ahb);
1738 clk_disable_unprepare(fep->clk_ipg);
1744 fec_resume(struct device *dev)
1746 struct net_device *ndev = dev_get_drvdata(dev);
1747 struct fec_enet_private *fep = netdev_priv(ndev);
1749 clk_prepare_enable(fep->clk_ahb);
1750 clk_prepare_enable(fep->clk_ipg);
1751 if (netif_running(ndev)) {
1752 fec_restart(ndev, fep->full_duplex);
1753 netif_device_attach(ndev);
1759 static const struct dev_pm_ops fec_pm_ops = {
1760 .suspend = fec_suspend,
1761 .resume = fec_resume,
1762 .freeze = fec_suspend,
1764 .poweroff = fec_suspend,
1765 .restore = fec_resume,
1769 static struct platform_driver fec_driver = {
1771 .name = DRIVER_NAME,
1772 .owner = THIS_MODULE,
1776 .of_match_table = fec_dt_ids,
1778 .id_table = fec_devtype,
1780 .remove = __devexit_p(fec_drv_remove),
1783 module_platform_driver(fec_driver);
1785 MODULE_LICENSE("GPL");