2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/pci.h>
33 #include <linux/init.h>
34 #include <linux/delay.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
38 #include <linux/spinlock.h>
39 #include <linux/workqueue.h>
40 #include <linux/bitops.h>
42 #include <linux/irq.h>
43 #include <linux/clk.h>
44 #include <linux/platform_device.h>
45 #include <linux/phy.h>
46 #include <linux/fec.h>
48 #include <linux/of_device.h>
49 #include <linux/of_gpio.h>
50 #include <linux/of_net.h>
51 #include <linux/pinctrl/consumer.h>
53 #include <asm/cacheflush.h>
56 #include <asm/coldfire.h>
57 #include <asm/mcfsim.h>
62 #if defined(CONFIG_ARM)
63 #define FEC_ALIGNMENT 0xf
65 #define FEC_ALIGNMENT 0x3
68 #define DRIVER_NAME "fec"
70 /* Controller is ENET-MAC */
71 #define FEC_QUIRK_ENET_MAC (1 << 0)
72 /* Controller needs driver to swap frame */
73 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
74 /* Controller uses gasket */
75 #define FEC_QUIRK_USE_GASKET (1 << 2)
76 /* Controller has GBIT support */
77 #define FEC_QUIRK_HAS_GBIT (1 << 3)
79 static struct platform_device_id fec_devtype[] = {
81 /* keep it for coldfire */
86 .driver_data = FEC_QUIRK_USE_GASKET,
92 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
95 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT,
100 MODULE_DEVICE_TABLE(platform, fec_devtype);
103 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
104 IMX27_FEC, /* runs on i.mx27/35/51 */
109 static const struct of_device_id fec_dt_ids[] = {
110 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
111 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
112 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
113 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
116 MODULE_DEVICE_TABLE(of, fec_dt_ids);
118 static unsigned char macaddr[ETH_ALEN];
119 module_param_array(macaddr, byte, NULL, 0);
120 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
122 #if defined(CONFIG_M5272)
124 * Some hardware gets it MAC address out of local flash memory.
125 * if this is non-zero then assume it is the address to get MAC from.
127 #if defined(CONFIG_NETtel)
128 #define FEC_FLASHMAC 0xf0006006
129 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
130 #define FEC_FLASHMAC 0xf0006000
131 #elif defined(CONFIG_CANCam)
132 #define FEC_FLASHMAC 0xf0020000
133 #elif defined (CONFIG_M5272C3)
134 #define FEC_FLASHMAC (0xffe04000 + 4)
135 #elif defined(CONFIG_MOD5272)
136 #define FEC_FLASHMAC 0xffc0406b
138 #define FEC_FLASHMAC 0
140 #endif /* CONFIG_M5272 */
142 /* The number of Tx and Rx buffers. These are allocated from the page
143 * pool. The code may assume these are power of two, so it it best
144 * to keep them that size.
145 * We don't need to allocate pages for the transmitter. We just use
146 * the skbuffer directly.
148 #define FEC_ENET_RX_PAGES 8
149 #define FEC_ENET_RX_FRSIZE 2048
150 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
151 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
152 #define FEC_ENET_TX_FRSIZE 2048
153 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
154 #define TX_RING_SIZE 16 /* Must be power of two */
155 #define TX_RING_MOD_MASK 15 /* for this to work */
157 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
158 #error "FEC: descriptor ring size constants too large"
161 /* Interrupt events/masks. */
162 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
163 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
164 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
165 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
166 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
167 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
168 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
169 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
170 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
171 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
173 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
175 /* The FEC stores dest/src/type, data, and checksum for receive packets.
177 #define PKT_MAXBUF_SIZE 1518
178 #define PKT_MINBUF_SIZE 64
179 #define PKT_MAXBLR_SIZE 1520
181 /* This device has up to three irqs on some platforms */
182 #define FEC_IRQ_NUM 3
185 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
186 * size bits. Other FEC hardware does not, so we need to take that into
187 * account when setting it.
189 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
190 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
191 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
193 #define OPT_FRAME_SIZE 0
196 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
197 * tx_bd_base always point to the base of the buffer descriptors. The
198 * cur_rx and cur_tx point to the currently available buffer.
199 * The dirty_tx tracks the current buffer that is being sent by the
200 * controller. The cur_tx and dirty_tx are equal under both completely
201 * empty and completely full conditions. The empty/ready indicator in
202 * the buffer descriptor determines the actual condition.
204 struct fec_enet_private {
205 /* Hardware registers of the FEC device */
208 struct net_device *netdev;
212 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
213 unsigned char *tx_bounce[TX_RING_SIZE];
214 struct sk_buff* tx_skbuff[TX_RING_SIZE];
215 struct sk_buff* rx_skbuff[RX_RING_SIZE];
219 /* CPM dual port RAM relative addresses */
221 /* Address of Rx and Tx buffers */
222 struct bufdesc *rx_bd_base;
223 struct bufdesc *tx_bd_base;
224 /* The next free ring entry */
225 struct bufdesc *cur_rx, *cur_tx;
226 /* The ring entries to be free()ed */
227 struct bufdesc *dirty_tx;
230 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
233 struct platform_device *pdev;
238 /* Phylib and MDIO interface */
239 struct mii_bus *mii_bus;
240 struct phy_device *phy_dev;
243 phy_interface_t phy_interface;
246 struct completion mdio_done;
247 int irq[FEC_IRQ_NUM];
250 /* FEC MII MMFR bits definition */
251 #define FEC_MMFR_ST (1 << 30)
252 #define FEC_MMFR_OP_READ (2 << 28)
253 #define FEC_MMFR_OP_WRITE (1 << 28)
254 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
255 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
256 #define FEC_MMFR_TA (2 << 16)
257 #define FEC_MMFR_DATA(v) (v & 0xffff)
259 #define FEC_MII_TIMEOUT 30000 /* us */
261 /* Transmitter timeout */
262 #define TX_TIMEOUT (2 * HZ)
266 static void *swap_buffer(void *bufaddr, int len)
269 unsigned int *buf = bufaddr;
271 for (i = 0; i < (len + 3) / 4; i++, buf++)
272 *buf = cpu_to_be32(*buf);
278 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
280 struct fec_enet_private *fep = netdev_priv(ndev);
281 const struct platform_device_id *id_entry =
282 platform_get_device_id(fep->pdev);
285 unsigned short status;
289 /* Link is down or autonegotiation is in progress. */
290 return NETDEV_TX_BUSY;
293 spin_lock_irqsave(&fep->hw_lock, flags);
294 /* Fill in a Tx ring entry */
297 status = bdp->cbd_sc;
299 if (status & BD_ENET_TX_READY) {
300 /* Ooops. All transmit buffers are full. Bail out.
301 * This should not happen, since ndev->tbusy should be set.
303 printk("%s: tx queue full!.\n", ndev->name);
304 spin_unlock_irqrestore(&fep->hw_lock, flags);
305 return NETDEV_TX_BUSY;
308 /* Clear all of the status flags */
309 status &= ~BD_ENET_TX_STATS;
311 /* Set buffer length and buffer pointer */
313 bdp->cbd_datlen = skb->len;
316 * On some FEC implementations data must be aligned on
317 * 4-byte boundaries. Use bounce buffers to copy data
318 * and get it aligned. Ugh.
320 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
322 index = bdp - fep->tx_bd_base;
323 memcpy(fep->tx_bounce[index], skb->data, skb->len);
324 bufaddr = fep->tx_bounce[index];
328 * Some design made an incorrect assumption on endian mode of
329 * the system that it's running on. As the result, driver has to
330 * swap every frame going to and coming from the controller.
332 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
333 swap_buffer(bufaddr, skb->len);
335 /* Save skb pointer */
336 fep->tx_skbuff[fep->skb_cur] = skb;
338 ndev->stats.tx_bytes += skb->len;
339 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
341 /* Push the data cache so the CPM does not get stale memory
344 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
345 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
347 /* Send it on its way. Tell FEC it's ready, interrupt when done,
348 * it's the last BD of the frame, and to put the CRC on the end.
350 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
351 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
352 bdp->cbd_sc = status;
354 /* Trigger transmission start */
355 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
357 /* If this was the last BD in the ring, start at the beginning again. */
358 if (status & BD_ENET_TX_WRAP)
359 bdp = fep->tx_bd_base;
363 if (bdp == fep->dirty_tx) {
365 netif_stop_queue(ndev);
370 skb_tx_timestamp(skb);
372 spin_unlock_irqrestore(&fep->hw_lock, flags);
377 /* This function is called to start or restart the FEC during a link
378 * change. This only happens when switching between half and full
382 fec_restart(struct net_device *ndev, int duplex)
384 struct fec_enet_private *fep = netdev_priv(ndev);
385 const struct platform_device_id *id_entry =
386 platform_get_device_id(fep->pdev);
389 u32 rcntl = OPT_FRAME_SIZE | 0x04;
390 u32 ecntl = 0x2; /* ETHEREN */
392 /* Whack a reset. We should wait for this. */
393 writel(1, fep->hwp + FEC_ECNTRL);
397 * enet-mac reset will reset mac address registers too,
398 * so need to reconfigure it.
400 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
401 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
402 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
403 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
406 /* Clear any outstanding interrupt. */
407 writel(0xffc00000, fep->hwp + FEC_IEVENT);
409 /* Reset all multicast. */
410 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
411 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
413 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
414 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
417 /* Set maximum receive buffer size. */
418 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
420 /* Set receive and transmit descriptor base. */
421 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
422 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE,
423 fep->hwp + FEC_X_DES_START);
425 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
426 fep->cur_rx = fep->rx_bd_base;
428 /* Reset SKB transmit buffers. */
429 fep->skb_cur = fep->skb_dirty = 0;
430 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
431 if (fep->tx_skbuff[i]) {
432 dev_kfree_skb_any(fep->tx_skbuff[i]);
433 fep->tx_skbuff[i] = NULL;
437 /* Enable MII mode */
440 writel(0x04, fep->hwp + FEC_X_CNTRL);
444 writel(0x0, fep->hwp + FEC_X_CNTRL);
447 fep->full_duplex = duplex;
450 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
453 * The phy interface and speed need to get configured
454 * differently on enet-mac.
456 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
457 /* Enable flow control and length check */
458 rcntl |= 0x40000000 | 0x00000020;
460 /* RGMII, RMII or MII */
461 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
463 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
468 /* 1G, 100M or 10M */
470 if (fep->phy_dev->speed == SPEED_1000)
472 else if (fep->phy_dev->speed == SPEED_100)
478 #ifdef FEC_MIIGSK_ENR
479 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
481 /* disable the gasket and wait */
482 writel(0, fep->hwp + FEC_MIIGSK_ENR);
483 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
487 * configure the gasket:
488 * RMII, 50 MHz, no loopback, no echo
489 * MII, 25 MHz, no loopback, no echo
491 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
492 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
493 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
494 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
495 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
497 /* re-enable the gasket */
498 writel(2, fep->hwp + FEC_MIIGSK_ENR);
502 writel(rcntl, fep->hwp + FEC_R_CNTRL);
504 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
505 /* enable ENET endian swap */
507 /* enable ENET store and forward mode */
508 writel(1 << 8, fep->hwp + FEC_X_WMRK);
511 /* And last, enable the transmit and receive processing */
512 writel(ecntl, fep->hwp + FEC_ECNTRL);
513 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
515 /* Enable interrupts we wish to service */
516 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
520 fec_stop(struct net_device *ndev)
522 struct fec_enet_private *fep = netdev_priv(ndev);
523 const struct platform_device_id *id_entry =
524 platform_get_device_id(fep->pdev);
525 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
527 /* We cannot expect a graceful transmit stop without link !!! */
529 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
531 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
532 printk("fec_stop : Graceful transmit stop did not complete !\n");
535 /* Whack a reset. We should wait for this. */
536 writel(1, fep->hwp + FEC_ECNTRL);
538 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
539 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
541 /* We have to keep ENET enabled to have MII interrupt stay working */
542 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
543 writel(2, fep->hwp + FEC_ECNTRL);
544 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
550 fec_timeout(struct net_device *ndev)
552 struct fec_enet_private *fep = netdev_priv(ndev);
554 ndev->stats.tx_errors++;
556 fec_restart(ndev, fep->full_duplex);
557 netif_wake_queue(ndev);
561 fec_enet_tx(struct net_device *ndev)
563 struct fec_enet_private *fep;
565 unsigned short status;
568 fep = netdev_priv(ndev);
569 spin_lock(&fep->hw_lock);
572 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
573 if (bdp == fep->cur_tx && fep->tx_full == 0)
576 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
577 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
578 bdp->cbd_bufaddr = 0;
580 skb = fep->tx_skbuff[fep->skb_dirty];
581 /* Check for errors. */
582 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
583 BD_ENET_TX_RL | BD_ENET_TX_UN |
585 ndev->stats.tx_errors++;
586 if (status & BD_ENET_TX_HB) /* No heartbeat */
587 ndev->stats.tx_heartbeat_errors++;
588 if (status & BD_ENET_TX_LC) /* Late collision */
589 ndev->stats.tx_window_errors++;
590 if (status & BD_ENET_TX_RL) /* Retrans limit */
591 ndev->stats.tx_aborted_errors++;
592 if (status & BD_ENET_TX_UN) /* Underrun */
593 ndev->stats.tx_fifo_errors++;
594 if (status & BD_ENET_TX_CSL) /* Carrier lost */
595 ndev->stats.tx_carrier_errors++;
597 ndev->stats.tx_packets++;
600 if (status & BD_ENET_TX_READY)
601 printk("HEY! Enet xmit interrupt and TX_READY.\n");
603 /* Deferred means some collisions occurred during transmit,
604 * but we eventually sent the packet OK.
606 if (status & BD_ENET_TX_DEF)
607 ndev->stats.collisions++;
609 /* Free the sk buffer associated with this last transmit */
610 dev_kfree_skb_any(skb);
611 fep->tx_skbuff[fep->skb_dirty] = NULL;
612 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
614 /* Update pointer to next buffer descriptor to be transmitted */
615 if (status & BD_ENET_TX_WRAP)
616 bdp = fep->tx_bd_base;
620 /* Since we have freed up a buffer, the ring is no longer full
624 if (netif_queue_stopped(ndev))
625 netif_wake_queue(ndev);
629 spin_unlock(&fep->hw_lock);
633 /* During a receive, the cur_rx points to the current incoming buffer.
634 * When we update through the ring, if the next incoming buffer has
635 * not been given to the system, we just set the empty indicator,
636 * effectively tossing the packet.
639 fec_enet_rx(struct net_device *ndev)
641 struct fec_enet_private *fep = netdev_priv(ndev);
642 const struct platform_device_id *id_entry =
643 platform_get_device_id(fep->pdev);
645 unsigned short status;
654 spin_lock(&fep->hw_lock);
656 /* First, grab all of the stats for the incoming packet.
657 * These get messed up if we get called due to a busy condition.
661 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
663 /* Since we have allocated space to hold a complete frame,
664 * the last indicator should be set.
666 if ((status & BD_ENET_RX_LAST) == 0)
667 printk("FEC ENET: rcv is not +last\n");
670 goto rx_processing_done;
672 /* Check for errors. */
673 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
674 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
675 ndev->stats.rx_errors++;
676 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
677 /* Frame too long or too short. */
678 ndev->stats.rx_length_errors++;
680 if (status & BD_ENET_RX_NO) /* Frame alignment */
681 ndev->stats.rx_frame_errors++;
682 if (status & BD_ENET_RX_CR) /* CRC Error */
683 ndev->stats.rx_crc_errors++;
684 if (status & BD_ENET_RX_OV) /* FIFO overrun */
685 ndev->stats.rx_fifo_errors++;
688 /* Report late collisions as a frame error.
689 * On this error, the BD is closed, but we don't know what we
690 * have in the buffer. So, just drop this frame on the floor.
692 if (status & BD_ENET_RX_CL) {
693 ndev->stats.rx_errors++;
694 ndev->stats.rx_frame_errors++;
695 goto rx_processing_done;
698 /* Process the incoming frame. */
699 ndev->stats.rx_packets++;
700 pkt_len = bdp->cbd_datlen;
701 ndev->stats.rx_bytes += pkt_len;
702 data = (__u8*)__va(bdp->cbd_bufaddr);
704 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
705 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
707 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
708 swap_buffer(data, pkt_len);
710 /* This does 16 byte alignment, exactly what we need.
711 * The packet length includes FCS, but we don't want to
712 * include that when passing upstream as it messes up
713 * bridging applications.
715 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
717 if (unlikely(!skb)) {
718 printk("%s: Memory squeeze, dropping packet.\n",
720 ndev->stats.rx_dropped++;
722 skb_reserve(skb, NET_IP_ALIGN);
723 skb_put(skb, pkt_len - 4); /* Make room */
724 skb_copy_to_linear_data(skb, data, pkt_len - 4);
725 skb->protocol = eth_type_trans(skb, ndev);
726 if (!skb_defer_rx_timestamp(skb))
730 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
731 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
733 /* Clear the status flags for this buffer */
734 status &= ~BD_ENET_RX_STATS;
736 /* Mark the buffer empty */
737 status |= BD_ENET_RX_EMPTY;
738 bdp->cbd_sc = status;
740 /* Update BD pointer to next entry */
741 if (status & BD_ENET_RX_WRAP)
742 bdp = fep->rx_bd_base;
745 /* Doing this here will keep the FEC running while we process
746 * incoming frames. On a heavily loaded network, we should be
747 * able to keep up at the expense of system resources.
749 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
753 spin_unlock(&fep->hw_lock);
757 fec_enet_interrupt(int irq, void *dev_id)
759 struct net_device *ndev = dev_id;
760 struct fec_enet_private *fep = netdev_priv(ndev);
762 irqreturn_t ret = IRQ_NONE;
765 int_events = readl(fep->hwp + FEC_IEVENT);
766 writel(int_events, fep->hwp + FEC_IEVENT);
768 if (int_events & FEC_ENET_RXF) {
773 /* Transmit OK, or non-fatal error. Update the buffer
774 * descriptors. FEC handles all errors, we just discover
775 * them as part of the transmit process.
777 if (int_events & FEC_ENET_TXF) {
782 if (int_events & FEC_ENET_MII) {
784 complete(&fep->mdio_done);
786 } while (int_events);
793 /* ------------------------------------------------------------------------- */
794 static void __inline__ fec_get_mac(struct net_device *ndev)
796 struct fec_enet_private *fep = netdev_priv(ndev);
797 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
798 unsigned char *iap, tmpaddr[ETH_ALEN];
801 * try to get mac address in following order:
803 * 1) module parameter via kernel command line in form
804 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
810 * 2) from device tree data
812 if (!is_valid_ether_addr(iap)) {
813 struct device_node *np = fep->pdev->dev.of_node;
815 const char *mac = of_get_mac_address(np);
817 iap = (unsigned char *) mac;
823 * 3) from flash or fuse (via platform data)
825 if (!is_valid_ether_addr(iap)) {
828 iap = (unsigned char *)FEC_FLASHMAC;
831 iap = (unsigned char *)&pdata->mac;
836 * 4) FEC mac registers set by bootloader
838 if (!is_valid_ether_addr(iap)) {
839 *((unsigned long *) &tmpaddr[0]) =
840 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
841 *((unsigned short *) &tmpaddr[4]) =
842 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
846 memcpy(ndev->dev_addr, iap, ETH_ALEN);
848 /* Adjust MAC if using macaddr */
850 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
853 /* ------------------------------------------------------------------------- */
858 static void fec_enet_adjust_link(struct net_device *ndev)
860 struct fec_enet_private *fep = netdev_priv(ndev);
861 struct phy_device *phy_dev = fep->phy_dev;
864 int status_change = 0;
866 spin_lock_irqsave(&fep->hw_lock, flags);
868 /* Prevent a state halted on mii error */
869 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
870 phy_dev->state = PHY_RESUMING;
874 /* Duplex link change */
876 if (fep->full_duplex != phy_dev->duplex) {
877 fec_restart(ndev, phy_dev->duplex);
878 /* prevent unnecessary second fec_restart() below */
879 fep->link = phy_dev->link;
884 /* Link on or off change */
885 if (phy_dev->link != fep->link) {
886 fep->link = phy_dev->link;
888 fec_restart(ndev, phy_dev->duplex);
895 spin_unlock_irqrestore(&fep->hw_lock, flags);
898 phy_print_status(phy_dev);
901 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
903 struct fec_enet_private *fep = bus->priv;
904 unsigned long time_left;
906 fep->mii_timeout = 0;
907 init_completion(&fep->mdio_done);
909 /* start a read op */
910 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
911 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
912 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
914 /* wait for end of transfer */
915 time_left = wait_for_completion_timeout(&fep->mdio_done,
916 usecs_to_jiffies(FEC_MII_TIMEOUT));
917 if (time_left == 0) {
918 fep->mii_timeout = 1;
919 printk(KERN_ERR "FEC: MDIO read timeout\n");
924 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
927 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
930 struct fec_enet_private *fep = bus->priv;
931 unsigned long time_left;
933 fep->mii_timeout = 0;
934 init_completion(&fep->mdio_done);
936 /* start a write op */
937 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
938 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
939 FEC_MMFR_TA | FEC_MMFR_DATA(value),
940 fep->hwp + FEC_MII_DATA);
942 /* wait for end of transfer */
943 time_left = wait_for_completion_timeout(&fep->mdio_done,
944 usecs_to_jiffies(FEC_MII_TIMEOUT));
945 if (time_left == 0) {
946 fep->mii_timeout = 1;
947 printk(KERN_ERR "FEC: MDIO write timeout\n");
954 static int fec_enet_mdio_reset(struct mii_bus *bus)
959 static int fec_enet_mii_probe(struct net_device *ndev)
961 struct fec_enet_private *fep = netdev_priv(ndev);
962 const struct platform_device_id *id_entry =
963 platform_get_device_id(fep->pdev);
964 struct phy_device *phy_dev = NULL;
965 char mdio_bus_id[MII_BUS_ID_SIZE];
966 char phy_name[MII_BUS_ID_SIZE + 3];
968 int dev_id = fep->dev_id;
972 /* check for attached phy */
973 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
974 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
976 if (fep->mii_bus->phy_map[phy_id] == NULL)
978 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
982 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
986 if (phy_id >= PHY_MAX_ADDR) {
988 "%s: no PHY, assuming direct connection to switch\n",
990 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
994 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
995 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 0,
997 if (IS_ERR(phy_dev)) {
998 printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name);
999 return PTR_ERR(phy_dev);
1002 /* mask with MAC supported features */
1003 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT)
1004 phy_dev->supported &= PHY_GBIT_FEATURES;
1006 phy_dev->supported &= PHY_BASIC_FEATURES;
1008 phy_dev->advertising = phy_dev->supported;
1010 fep->phy_dev = phy_dev;
1012 fep->full_duplex = 0;
1015 "%s: Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1017 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1023 static int fec_enet_mii_init(struct platform_device *pdev)
1025 static struct mii_bus *fec0_mii_bus;
1026 struct net_device *ndev = platform_get_drvdata(pdev);
1027 struct fec_enet_private *fep = netdev_priv(ndev);
1028 const struct platform_device_id *id_entry =
1029 platform_get_device_id(fep->pdev);
1030 int err = -ENXIO, i;
1033 * The dual fec interfaces are not equivalent with enet-mac.
1034 * Here are the differences:
1036 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1037 * - fec0 acts as the 1588 time master while fec1 is slave
1038 * - external phys can only be configured by fec0
1040 * That is to say fec1 can not work independently. It only works
1041 * when fec0 is working. The reason behind this design is that the
1042 * second interface is added primarily for Switch mode.
1044 * Because of the last point above, both phys are attached on fec0
1045 * mdio interface in board design, and need to be configured by
1048 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1049 /* fec1 uses fec0 mii_bus */
1050 if (mii_cnt && fec0_mii_bus) {
1051 fep->mii_bus = fec0_mii_bus;
1058 fep->mii_timeout = 0;
1061 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1063 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1064 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1065 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1068 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000);
1069 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1071 fep->phy_speed <<= 1;
1072 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1074 fep->mii_bus = mdiobus_alloc();
1075 if (fep->mii_bus == NULL) {
1080 fep->mii_bus->name = "fec_enet_mii_bus";
1081 fep->mii_bus->read = fec_enet_mdio_read;
1082 fep->mii_bus->write = fec_enet_mdio_write;
1083 fep->mii_bus->reset = fec_enet_mdio_reset;
1084 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1085 pdev->name, fep->dev_id + 1);
1086 fep->mii_bus->priv = fep;
1087 fep->mii_bus->parent = &pdev->dev;
1089 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1090 if (!fep->mii_bus->irq) {
1092 goto err_out_free_mdiobus;
1095 for (i = 0; i < PHY_MAX_ADDR; i++)
1096 fep->mii_bus->irq[i] = PHY_POLL;
1098 if (mdiobus_register(fep->mii_bus))
1099 goto err_out_free_mdio_irq;
1103 /* save fec0 mii_bus */
1104 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1105 fec0_mii_bus = fep->mii_bus;
1109 err_out_free_mdio_irq:
1110 kfree(fep->mii_bus->irq);
1111 err_out_free_mdiobus:
1112 mdiobus_free(fep->mii_bus);
1117 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1119 if (--mii_cnt == 0) {
1120 mdiobus_unregister(fep->mii_bus);
1121 kfree(fep->mii_bus->irq);
1122 mdiobus_free(fep->mii_bus);
1126 static int fec_enet_get_settings(struct net_device *ndev,
1127 struct ethtool_cmd *cmd)
1129 struct fec_enet_private *fep = netdev_priv(ndev);
1130 struct phy_device *phydev = fep->phy_dev;
1135 return phy_ethtool_gset(phydev, cmd);
1138 static int fec_enet_set_settings(struct net_device *ndev,
1139 struct ethtool_cmd *cmd)
1141 struct fec_enet_private *fep = netdev_priv(ndev);
1142 struct phy_device *phydev = fep->phy_dev;
1147 return phy_ethtool_sset(phydev, cmd);
1150 static void fec_enet_get_drvinfo(struct net_device *ndev,
1151 struct ethtool_drvinfo *info)
1153 struct fec_enet_private *fep = netdev_priv(ndev);
1155 strcpy(info->driver, fep->pdev->dev.driver->name);
1156 strcpy(info->version, "Revision: 1.0");
1157 strcpy(info->bus_info, dev_name(&ndev->dev));
1160 static const struct ethtool_ops fec_enet_ethtool_ops = {
1161 .get_settings = fec_enet_get_settings,
1162 .set_settings = fec_enet_set_settings,
1163 .get_drvinfo = fec_enet_get_drvinfo,
1164 .get_link = ethtool_op_get_link,
1165 .get_ts_info = ethtool_op_get_ts_info,
1168 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1170 struct fec_enet_private *fep = netdev_priv(ndev);
1171 struct phy_device *phydev = fep->phy_dev;
1173 if (!netif_running(ndev))
1179 return phy_mii_ioctl(phydev, rq, cmd);
1182 static void fec_enet_free_buffers(struct net_device *ndev)
1184 struct fec_enet_private *fep = netdev_priv(ndev);
1186 struct sk_buff *skb;
1187 struct bufdesc *bdp;
1189 bdp = fep->rx_bd_base;
1190 for (i = 0; i < RX_RING_SIZE; i++) {
1191 skb = fep->rx_skbuff[i];
1193 if (bdp->cbd_bufaddr)
1194 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1195 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1201 bdp = fep->tx_bd_base;
1202 for (i = 0; i < TX_RING_SIZE; i++)
1203 kfree(fep->tx_bounce[i]);
1206 static int fec_enet_alloc_buffers(struct net_device *ndev)
1208 struct fec_enet_private *fep = netdev_priv(ndev);
1210 struct sk_buff *skb;
1211 struct bufdesc *bdp;
1213 bdp = fep->rx_bd_base;
1214 for (i = 0; i < RX_RING_SIZE; i++) {
1215 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1217 fec_enet_free_buffers(ndev);
1220 fep->rx_skbuff[i] = skb;
1222 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1223 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1224 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1228 /* Set the last buffer to wrap. */
1230 bdp->cbd_sc |= BD_SC_WRAP;
1232 bdp = fep->tx_bd_base;
1233 for (i = 0; i < TX_RING_SIZE; i++) {
1234 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1237 bdp->cbd_bufaddr = 0;
1241 /* Set the last buffer to wrap. */
1243 bdp->cbd_sc |= BD_SC_WRAP;
1249 fec_enet_open(struct net_device *ndev)
1251 struct fec_enet_private *fep = netdev_priv(ndev);
1254 /* I should reset the ring buffers here, but I don't yet know
1255 * a simple way to do that.
1258 ret = fec_enet_alloc_buffers(ndev);
1262 /* Probe and connect to PHY when open the interface */
1263 ret = fec_enet_mii_probe(ndev);
1265 fec_enet_free_buffers(ndev);
1268 phy_start(fep->phy_dev);
1269 netif_start_queue(ndev);
1275 fec_enet_close(struct net_device *ndev)
1277 struct fec_enet_private *fep = netdev_priv(ndev);
1279 /* Don't know what to do yet. */
1281 netif_stop_queue(ndev);
1285 phy_stop(fep->phy_dev);
1286 phy_disconnect(fep->phy_dev);
1289 fec_enet_free_buffers(ndev);
1294 /* Set or clear the multicast filter for this adaptor.
1295 * Skeleton taken from sunlance driver.
1296 * The CPM Ethernet implementation allows Multicast as well as individual
1297 * MAC address filtering. Some of the drivers check to make sure it is
1298 * a group multicast address, and discard those that are not. I guess I
1299 * will do the same for now, but just remove the test if you want
1300 * individual filtering as well (do the upper net layers want or support
1301 * this kind of feature?).
1304 #define HASH_BITS 6 /* #bits in hash */
1305 #define CRC32_POLY 0xEDB88320
1307 static void set_multicast_list(struct net_device *ndev)
1309 struct fec_enet_private *fep = netdev_priv(ndev);
1310 struct netdev_hw_addr *ha;
1311 unsigned int i, bit, data, crc, tmp;
1314 if (ndev->flags & IFF_PROMISC) {
1315 tmp = readl(fep->hwp + FEC_R_CNTRL);
1317 writel(tmp, fep->hwp + FEC_R_CNTRL);
1321 tmp = readl(fep->hwp + FEC_R_CNTRL);
1323 writel(tmp, fep->hwp + FEC_R_CNTRL);
1325 if (ndev->flags & IFF_ALLMULTI) {
1326 /* Catch all multicast addresses, so set the
1329 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1330 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1335 /* Clear filter and add the addresses in hash register
1337 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1338 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1340 netdev_for_each_mc_addr(ha, ndev) {
1341 /* calculate crc32 value of mac address */
1344 for (i = 0; i < ndev->addr_len; i++) {
1346 for (bit = 0; bit < 8; bit++, data >>= 1) {
1348 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1352 /* only upper 6 bits (HASH_BITS) are used
1353 * which point to specific bit in he hash registers
1355 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1358 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1359 tmp |= 1 << (hash - 32);
1360 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1362 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1364 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1369 /* Set a MAC change in hardware. */
1371 fec_set_mac_address(struct net_device *ndev, void *p)
1373 struct fec_enet_private *fep = netdev_priv(ndev);
1374 struct sockaddr *addr = p;
1376 if (!is_valid_ether_addr(addr->sa_data))
1377 return -EADDRNOTAVAIL;
1379 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1381 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1382 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1383 fep->hwp + FEC_ADDR_LOW);
1384 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1385 fep->hwp + FEC_ADDR_HIGH);
1389 #ifdef CONFIG_NET_POLL_CONTROLLER
1391 * fec_poll_controller: FEC Poll controller function
1392 * @dev: The FEC network adapter
1394 * Polled functionality used by netconsole and others in non interrupt mode
1397 void fec_poll_controller(struct net_device *dev)
1400 struct fec_enet_private *fep = netdev_priv(dev);
1402 for (i = 0; i < FEC_IRQ_NUM; i++) {
1403 if (fep->irq[i] > 0) {
1404 disable_irq(fep->irq[i]);
1405 fec_enet_interrupt(fep->irq[i], dev);
1406 enable_irq(fep->irq[i]);
1412 static const struct net_device_ops fec_netdev_ops = {
1413 .ndo_open = fec_enet_open,
1414 .ndo_stop = fec_enet_close,
1415 .ndo_start_xmit = fec_enet_start_xmit,
1416 .ndo_set_rx_mode = set_multicast_list,
1417 .ndo_change_mtu = eth_change_mtu,
1418 .ndo_validate_addr = eth_validate_addr,
1419 .ndo_tx_timeout = fec_timeout,
1420 .ndo_set_mac_address = fec_set_mac_address,
1421 .ndo_do_ioctl = fec_enet_ioctl,
1422 #ifdef CONFIG_NET_POLL_CONTROLLER
1423 .ndo_poll_controller = fec_poll_controller,
1428 * XXX: We need to clean up on failure exits here.
1431 static int fec_enet_init(struct net_device *ndev)
1433 struct fec_enet_private *fep = netdev_priv(ndev);
1434 struct bufdesc *cbd_base;
1435 struct bufdesc *bdp;
1438 /* Allocate memory for buffer descriptors. */
1439 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1442 printk("FEC: allocate descriptor memory failed?\n");
1446 spin_lock_init(&fep->hw_lock);
1450 /* Get the Ethernet address */
1453 /* Set receive and transmit descriptor base. */
1454 fep->rx_bd_base = cbd_base;
1455 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1457 /* The FEC Ethernet specific entries in the device structure */
1458 ndev->watchdog_timeo = TX_TIMEOUT;
1459 ndev->netdev_ops = &fec_netdev_ops;
1460 ndev->ethtool_ops = &fec_enet_ethtool_ops;
1462 /* Initialize the receive buffer descriptors. */
1463 bdp = fep->rx_bd_base;
1464 for (i = 0; i < RX_RING_SIZE; i++) {
1466 /* Initialize the BD for every fragment in the page. */
1471 /* Set the last buffer to wrap */
1473 bdp->cbd_sc |= BD_SC_WRAP;
1475 /* ...and the same for transmit */
1476 bdp = fep->tx_bd_base;
1477 for (i = 0; i < TX_RING_SIZE; i++) {
1479 /* Initialize the BD for every fragment in the page. */
1481 bdp->cbd_bufaddr = 0;
1485 /* Set the last buffer to wrap */
1487 bdp->cbd_sc |= BD_SC_WRAP;
1489 fec_restart(ndev, 0);
1495 static int __devinit fec_get_phy_mode_dt(struct platform_device *pdev)
1497 struct device_node *np = pdev->dev.of_node;
1500 return of_get_phy_mode(np);
1505 static void __devinit fec_reset_phy(struct platform_device *pdev)
1508 struct device_node *np = pdev->dev.of_node;
1513 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
1514 err = gpio_request_one(phy_reset, GPIOF_OUT_INIT_LOW, "phy-reset");
1516 pr_debug("FEC: failed to get gpio phy-reset: %d\n", err);
1520 gpio_set_value(phy_reset, 1);
1522 #else /* CONFIG_OF */
1523 static inline int fec_get_phy_mode_dt(struct platform_device *pdev)
1528 static inline void fec_reset_phy(struct platform_device *pdev)
1531 * In case of platform probe, the reset has been done
1535 #endif /* CONFIG_OF */
1537 static int __devinit
1538 fec_probe(struct platform_device *pdev)
1540 struct fec_enet_private *fep;
1541 struct fec_platform_data *pdata;
1542 struct net_device *ndev;
1543 int i, irq, ret = 0;
1545 const struct of_device_id *of_id;
1547 struct pinctrl *pinctrl;
1549 of_id = of_match_device(fec_dt_ids, &pdev->dev);
1551 pdev->id_entry = of_id->data;
1553 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1557 r = request_mem_region(r->start, resource_size(r), pdev->name);
1561 /* Init network device */
1562 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
1565 goto failed_alloc_etherdev;
1568 SET_NETDEV_DEV(ndev, &pdev->dev);
1570 /* setup board info structure */
1571 fep = netdev_priv(ndev);
1573 fep->hwp = ioremap(r->start, resource_size(r));
1575 fep->dev_id = dev_id++;
1579 goto failed_ioremap;
1582 platform_set_drvdata(pdev, ndev);
1584 ret = fec_get_phy_mode_dt(pdev);
1586 pdata = pdev->dev.platform_data;
1588 fep->phy_interface = pdata->phy;
1590 fep->phy_interface = PHY_INTERFACE_MODE_MII;
1592 fep->phy_interface = ret;
1595 fec_reset_phy(pdev);
1597 for (i = 0; i < FEC_IRQ_NUM; i++) {
1598 irq = platform_get_irq(pdev, i);
1605 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
1608 irq = platform_get_irq(pdev, i);
1609 free_irq(irq, ndev);
1615 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1616 if (IS_ERR(pinctrl)) {
1617 ret = PTR_ERR(pinctrl);
1621 fep->clk = clk_get(&pdev->dev, NULL);
1622 if (IS_ERR(fep->clk)) {
1623 ret = PTR_ERR(fep->clk);
1626 clk_prepare_enable(fep->clk);
1628 ret = fec_enet_init(ndev);
1632 ret = fec_enet_mii_init(pdev);
1634 goto failed_mii_init;
1636 /* Carrier starts down, phylib will bring it up */
1637 netif_carrier_off(ndev);
1639 ret = register_netdev(ndev);
1641 goto failed_register;
1646 fec_enet_mii_remove(fep);
1649 clk_disable_unprepare(fep->clk);
1653 for (i = 0; i < FEC_IRQ_NUM; i++) {
1654 irq = platform_get_irq(pdev, i);
1656 free_irq(irq, ndev);
1662 failed_alloc_etherdev:
1663 release_mem_region(r->start, resource_size(r));
1668 static int __devexit
1669 fec_drv_remove(struct platform_device *pdev)
1671 struct net_device *ndev = platform_get_drvdata(pdev);
1672 struct fec_enet_private *fep = netdev_priv(ndev);
1676 unregister_netdev(ndev);
1677 fec_enet_mii_remove(fep);
1678 for (i = 0; i < FEC_IRQ_NUM; i++) {
1679 int irq = platform_get_irq(pdev, i);
1681 free_irq(irq, ndev);
1683 clk_disable_unprepare(fep->clk);
1688 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1690 release_mem_region(r->start, resource_size(r));
1692 platform_set_drvdata(pdev, NULL);
1699 fec_suspend(struct device *dev)
1701 struct net_device *ndev = dev_get_drvdata(dev);
1702 struct fec_enet_private *fep = netdev_priv(ndev);
1704 if (netif_running(ndev)) {
1706 netif_device_detach(ndev);
1708 clk_disable_unprepare(fep->clk);
1714 fec_resume(struct device *dev)
1716 struct net_device *ndev = dev_get_drvdata(dev);
1717 struct fec_enet_private *fep = netdev_priv(ndev);
1719 clk_prepare_enable(fep->clk);
1720 if (netif_running(ndev)) {
1721 fec_restart(ndev, fep->full_duplex);
1722 netif_device_attach(ndev);
1728 static const struct dev_pm_ops fec_pm_ops = {
1729 .suspend = fec_suspend,
1730 .resume = fec_resume,
1731 .freeze = fec_suspend,
1733 .poweroff = fec_suspend,
1734 .restore = fec_resume,
1738 static struct platform_driver fec_driver = {
1740 .name = DRIVER_NAME,
1741 .owner = THIS_MODULE,
1745 .of_match_table = fec_dt_ids,
1747 .id_table = fec_devtype,
1749 .remove = __devexit_p(fec_drv_remove),
1752 module_platform_driver(fec_driver);
1754 MODULE_LICENSE("GPL");