drivers/net/ethernet/faraday/ftgmac100.c

   1 /*
   2  * Faraday FTGMAC100 Gigabit Ethernet
   3  *
   4  * (C) Copyright 2009-2011 Faraday Technology
   5  * Po-Yu Chuang <ratbert@faraday-tech.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 #define pr_fmt(fmt)     KBUILD_MODNAME ": " fmt
  23
  24 #include <linux/dma-mapping.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/ethtool.h>
  27 #include <linux/init.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/io.h>
  30 #include <linux/module.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/phy.h>
  33 #include <linux/platform_device.h>
  34 #include <net/ip.h>
  35
  36 #include "ftgmac100.h"
  37
  38 #define DRV_NAME        "ftgmac100"
  39 #define DRV_VERSION     "0.7"
  40
  41 #define RX_QUEUE_ENTRIES        256     /* must be power of 2 */
  42 #define TX_QUEUE_ENTRIES        512     /* must be power of 2 */
  43
  44 #define MAX_PKT_SIZE            1518
  45 #define RX_BUF_SIZE             PAGE_SIZE       /* must be smaller than 0x3fff */
  46
  47 /******************************************************************************
  48  * private data
  49  *****************************************************************************/
  50 struct ftgmac100_descs {
  51         struct ftgmac100_rxdes rxdes[RX_QUEUE_ENTRIES];
  52         struct ftgmac100_txdes txdes[TX_QUEUE_ENTRIES];
  53 };
  54
  55 struct ftgmac100 {
  56         struct resource *res;
  57         void __iomem *base;
  58         int irq;
  59
  60         struct ftgmac100_descs *descs;
  61         dma_addr_t descs_dma_addr;
  62
  63         unsigned int rx_pointer;
  64         unsigned int tx_clean_pointer;
  65         unsigned int tx_pointer;
  66         unsigned int tx_pending;
  67
  68         spinlock_t tx_lock;
  69
  70         struct net_device *netdev;
  71         struct device *dev;
  72         struct napi_struct napi;
  73
  74         struct mii_bus *mii_bus;
  75         int phy_irq[PHY_MAX_ADDR];
  76         struct phy_device *phydev;
  77         int old_speed;
  78 };
  79
  80 static int ftgmac100_alloc_rx_page(struct ftgmac100 *priv,
  81                                    struct ftgmac100_rxdes *rxdes, gfp_t gfp);
  82
  83 /******************************************************************************
  84  * internal functions (hardware register access)
  85  *****************************************************************************/
  86 #define INT_MASK_ALL_ENABLED    (FTGMAC100_INT_RPKT_LOST        | \
  87                                  FTGMAC100_INT_XPKT_ETH         | \
  88                                  FTGMAC100_INT_XPKT_LOST        | \
  89                                  FTGMAC100_INT_AHB_ERR          | \
  90                                  FTGMAC100_INT_PHYSTS_CHG       | \
  91                                  FTGMAC100_INT_RPKT_BUF         | \
  92                                  FTGMAC100_INT_NO_RXBUF)
  93
  94 static void ftgmac100_set_rx_ring_base(struct ftgmac100 *priv, dma_addr_t addr)
  95 {
  96         iowrite32(addr, priv->base + FTGMAC100_OFFSET_RXR_BADR);
  97 }
  98
  99 static void ftgmac100_set_rx_buffer_size(struct ftgmac100 *priv,
 100                 unsigned int size)
 101 {
 102         size = FTGMAC100_RBSR_SIZE(size);
 103         iowrite32(size, priv->base + FTGMAC100_OFFSET_RBSR);
 104 }
 105
 106 static void ftgmac100_set_normal_prio_tx_ring_base(struct ftgmac100 *priv,
 107                                                    dma_addr_t addr)
 108 {
 109         iowrite32(addr, priv->base + FTGMAC100_OFFSET_NPTXR_BADR);
 110 }
 111
 112 static void ftgmac100_txdma_normal_prio_start_polling(struct ftgmac100 *priv)
 113 {
 114         iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD);
 115 }
 116
 117 static int ftgmac100_reset_hw(struct ftgmac100 *priv)
 118 {
 119         struct net_device *netdev = priv->netdev;
 120         int i;
 121
 122         /* NOTE: reset clears all registers */
 123         iowrite32(FTGMAC100_MACCR_SW_RST, priv->base + FTGMAC100_OFFSET_MACCR);
 124         for (i = 0; i < 5; i++) {
 125                 unsigned int maccr;
 126
 127                 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
 128                 if (!(maccr & FTGMAC100_MACCR_SW_RST))
 129                         return 0;
 130
 131                 udelay(1000);
 132         }
 133
 134         netdev_err(netdev, "software reset failed\n");
 135         return -EIO;
 136 }
 137
 138 static void ftgmac100_set_mac(struct ftgmac100 *priv, const unsigned char *mac)
 139 {
 140         unsigned int maddr = mac[0] << 8 | mac[1];
 141         unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
 142
 143         iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR);
 144         iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR);
 145 }
 146
 147 static void ftgmac100_init_hw(struct ftgmac100 *priv)
 148 {
 149         /* setup ring buffer base registers */
 150         ftgmac100_set_rx_ring_base(priv,
 151                                    priv->descs_dma_addr +
 152                                    offsetof(struct ftgmac100_descs, rxdes));
 153         ftgmac100_set_normal_prio_tx_ring_base(priv,
 154                                                priv->descs_dma_addr +
 155                                                offsetof(struct ftgmac100_descs, txdes));
 156
 157         ftgmac100_set_rx_buffer_size(priv, RX_BUF_SIZE);
 158
 159         iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1), priv->base + FTGMAC100_OFFSET_APTC);
 160
 161         ftgmac100_set_mac(priv, priv->netdev->dev_addr);
 162 }
 163
 164 #define MACCR_ENABLE_ALL        (FTGMAC100_MACCR_TXDMA_EN       | \
 165                                  FTGMAC100_MACCR_RXDMA_EN       | \
 166                                  FTGMAC100_MACCR_TXMAC_EN       | \
 167                                  FTGMAC100_MACCR_RXMAC_EN       | \
 168                                  FTGMAC100_MACCR_FULLDUP        | \
 169                                  FTGMAC100_MACCR_CRC_APD        | \
 170                                  FTGMAC100_MACCR_RX_RUNT        | \
 171                                  FTGMAC100_MACCR_RX_BROADPKT)
 172
 173 static void ftgmac100_start_hw(struct ftgmac100 *priv, int speed)
 174 {
 175         int maccr = MACCR_ENABLE_ALL;
 176
 177         switch (speed) {
 178         default:
 179         case 10:
 180                 break;
 181
 182         case 100:
 183                 maccr |= FTGMAC100_MACCR_FAST_MODE;
 184                 break;
 185
 186         case 1000:
 187                 maccr |= FTGMAC100_MACCR_GIGA_MODE;
 188                 break;
 189         }
 190
 191         iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
 192 }
 193
 194 static void ftgmac100_stop_hw(struct ftgmac100 *priv)
 195 {
 196         iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR);
 197 }
 198
 199 /******************************************************************************
 200  * internal functions (receive descriptor)
 201  *****************************************************************************/
 202 static bool ftgmac100_rxdes_first_segment(struct ftgmac100_rxdes *rxdes)
 203 {
 204         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_FRS);
 205 }
 206
 207 static bool ftgmac100_rxdes_last_segment(struct ftgmac100_rxdes *rxdes)
 208 {
 209         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_LRS);
 210 }
 211
 212 static bool ftgmac100_rxdes_packet_ready(struct ftgmac100_rxdes *rxdes)
 213 {
 214         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY);
 215 }
 216
 217 static void ftgmac100_rxdes_set_dma_own(struct ftgmac100_rxdes *rxdes)
 218 {
 219         /* clear status bits */
 220         rxdes->rxdes0 &= cpu_to_le32(FTGMAC100_RXDES0_EDORR);
 221 }
 222
 223 static bool ftgmac100_rxdes_rx_error(struct ftgmac100_rxdes *rxdes)
 224 {
 225         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RX_ERR);
 226 }
 227
 228 static bool ftgmac100_rxdes_crc_error(struct ftgmac100_rxdes *rxdes)
 229 {
 230         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_CRC_ERR);
 231 }
 232
 233 static bool ftgmac100_rxdes_frame_too_long(struct ftgmac100_rxdes *rxdes)
 234 {
 235         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_FTL);
 236 }
 237
 238 static bool ftgmac100_rxdes_runt(struct ftgmac100_rxdes *rxdes)
 239 {
 240         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RUNT);
 241 }
 242
 243 static bool ftgmac100_rxdes_odd_nibble(struct ftgmac100_rxdes *rxdes)
 244 {
 245         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RX_ODD_NB);
 246 }
 247
 248 static unsigned int ftgmac100_rxdes_data_length(struct ftgmac100_rxdes *rxdes)
 249 {
 250         return le32_to_cpu(rxdes->rxdes0) & FTGMAC100_RXDES0_VDBC;
 251 }
 252
 253 static bool ftgmac100_rxdes_multicast(struct ftgmac100_rxdes *rxdes)
 254 {
 255         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_MULTICAST);
 256 }
 257
 258 static void ftgmac100_rxdes_set_end_of_ring(struct ftgmac100_rxdes *rxdes)
 259 {
 260         rxdes->rxdes0 |= cpu_to_le32(FTGMAC100_RXDES0_EDORR);
 261 }
 262
 263 static void ftgmac100_rxdes_set_dma_addr(struct ftgmac100_rxdes *rxdes,
 264                                          dma_addr_t addr)
 265 {
 266         rxdes->rxdes3 = cpu_to_le32(addr);
 267 }
 268
 269 static dma_addr_t ftgmac100_rxdes_get_dma_addr(struct ftgmac100_rxdes *rxdes)
 270 {
 271         return le32_to_cpu(rxdes->rxdes3);
 272 }
 273
 274 static bool ftgmac100_rxdes_is_tcp(struct ftgmac100_rxdes *rxdes)
 275 {
 276         return (rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_PROT_MASK)) ==
 277                cpu_to_le32(FTGMAC100_RXDES1_PROT_TCPIP);
 278 }
 279
 280 static bool ftgmac100_rxdes_is_udp(struct ftgmac100_rxdes *rxdes)
 281 {
 282         return (rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_PROT_MASK)) ==
 283                cpu_to_le32(FTGMAC100_RXDES1_PROT_UDPIP);
 284 }
 285
 286 static bool ftgmac100_rxdes_tcpcs_err(struct ftgmac100_rxdes *rxdes)
 287 {
 288         return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_TCP_CHKSUM_ERR);
 289 }
 290
 291 static bool ftgmac100_rxdes_udpcs_err(struct ftgmac100_rxdes *rxdes)
 292 {
 293         return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_UDP_CHKSUM_ERR);
 294 }
 295
 296 static bool ftgmac100_rxdes_ipcs_err(struct ftgmac100_rxdes *rxdes)
 297 {
 298         return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_IP_CHKSUM_ERR);
 299 }
 300
 301 /*
 302  * rxdes2 is not used by hardware. We use it to keep track of page.
 303  * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu().
 304  */
 305 static void ftgmac100_rxdes_set_page(struct ftgmac100_rxdes *rxdes, struct page *page)
 306 {
 307         rxdes->rxdes2 = (unsigned int)page;
 308 }
 309
 310 static struct page *ftgmac100_rxdes_get_page(struct ftgmac100_rxdes *rxdes)
 311 {
 312         return (struct page *)rxdes->rxdes2;
 313 }
 314
 315 /******************************************************************************
 316  * internal functions (receive)
 317  *****************************************************************************/
 318 static int ftgmac100_next_rx_pointer(int pointer)
 319 {
 320         return (pointer + 1) & (RX_QUEUE_ENTRIES - 1);
 321 }
 322
 323 static void ftgmac100_rx_pointer_advance(struct ftgmac100 *priv)
 324 {
 325         priv->rx_pointer = ftgmac100_next_rx_pointer(priv->rx_pointer);
 326 }
 327
 328 static struct ftgmac100_rxdes *ftgmac100_current_rxdes(struct ftgmac100 *priv)
 329 {
 330         return &priv->descs->rxdes[priv->rx_pointer];
 331 }
 332
 333 static struct ftgmac100_rxdes *
 334 ftgmac100_rx_locate_first_segment(struct ftgmac100 *priv)
 335 {
 336         struct ftgmac100_rxdes *rxdes = ftgmac100_current_rxdes(priv);
 337
 338         while (ftgmac100_rxdes_packet_ready(rxdes)) {
 339                 if (ftgmac100_rxdes_first_segment(rxdes))
 340                         return rxdes;
 341
 342                 ftgmac100_rxdes_set_dma_own(rxdes);
 343                 ftgmac100_rx_pointer_advance(priv);
 344                 rxdes = ftgmac100_current_rxdes(priv);
 345         }
 346
 347         return NULL;
 348 }
 349
 350 static bool ftgmac100_rx_packet_error(struct ftgmac100 *priv,
 351                                       struct ftgmac100_rxdes *rxdes)
 352 {
 353         struct net_device *netdev = priv->netdev;
 354         bool error = false;
 355
 356         if (unlikely(ftgmac100_rxdes_rx_error(rxdes))) {
 357                 if (net_ratelimit())
 358                         netdev_info(netdev, "rx err\n");
 359
 360                 netdev->stats.rx_errors++;
 361                 error = true;
 362         }
 363
 364         if (unlikely(ftgmac100_rxdes_crc_error(rxdes))) {
 365                 if (net_ratelimit())
 366                         netdev_info(netdev, "rx crc err\n");
 367
 368                 netdev->stats.rx_crc_errors++;
 369                 error = true;
 370         } else if (unlikely(ftgmac100_rxdes_ipcs_err(rxdes))) {
 371                 if (net_ratelimit())
 372                         netdev_info(netdev, "rx IP checksum err\n");
 373
 374                 error = true;
 375         }
 376
 377         if (unlikely(ftgmac100_rxdes_frame_too_long(rxdes))) {
 378                 if (net_ratelimit())
 379                         netdev_info(netdev, "rx frame too long\n");
 380
 381                 netdev->stats.rx_length_errors++;
 382                 error = true;
 383         } else if (unlikely(ftgmac100_rxdes_runt(rxdes))) {
 384                 if (net_ratelimit())
 385                         netdev_info(netdev, "rx runt\n");
 386
 387                 netdev->stats.rx_length_errors++;
 388                 error = true;
 389         } else if (unlikely(ftgmac100_rxdes_odd_nibble(rxdes))) {
 390                 if (net_ratelimit())
 391                         netdev_info(netdev, "rx odd nibble\n");
 392
 393                 netdev->stats.rx_length_errors++;
 394                 error = true;
 395         }
 396
 397         return error;
 398 }
 399
 400 static void ftgmac100_rx_drop_packet(struct ftgmac100 *priv)
 401 {
 402         struct net_device *netdev = priv->netdev;
 403         struct ftgmac100_rxdes *rxdes = ftgmac100_current_rxdes(priv);
 404         bool done = false;
 405
 406         if (net_ratelimit())
 407                 netdev_dbg(netdev, "drop packet %p\n", rxdes);
 408
 409         do {
 410                 if (ftgmac100_rxdes_last_segment(rxdes))
 411                         done = true;
 412
 413                 ftgmac100_rxdes_set_dma_own(rxdes);
 414                 ftgmac100_rx_pointer_advance(priv);
 415                 rxdes = ftgmac100_current_rxdes(priv);
 416         } while (!done && ftgmac100_rxdes_packet_ready(rxdes));
 417
 418         netdev->stats.rx_dropped++;
 419 }
 420
 421 static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed)
 422 {
 423         struct net_device *netdev = priv->netdev;
 424         struct ftgmac100_rxdes *rxdes;
 425         struct sk_buff *skb;
 426         bool done = false;
 427
 428         rxdes = ftgmac100_rx_locate_first_segment(priv);
 429         if (!rxdes)
 430                 return false;
 431
 432         if (unlikely(ftgmac100_rx_packet_error(priv, rxdes))) {
 433                 ftgmac100_rx_drop_packet(priv);
 434                 return true;
 435         }
 436
 437         /* start processing */
 438         skb = netdev_alloc_skb_ip_align(netdev, 128);
 439         if (unlikely(!skb)) {
 440                 if (net_ratelimit())
 441                         netdev_err(netdev, "rx skb alloc failed\n");
 442
 443                 ftgmac100_rx_drop_packet(priv);
 444                 return true;
 445         }
 446
 447         if (unlikely(ftgmac100_rxdes_multicast(rxdes)))
 448                 netdev->stats.multicast++;
 449
 450         /*
 451          * It seems that HW does checksum incorrectly with fragmented packets,
 452          * so we are conservative here - if HW checksum error, let software do
 453          * the checksum again.
 454          */
 455         if ((ftgmac100_rxdes_is_tcp(rxdes) && !ftgmac100_rxdes_tcpcs_err(rxdes)) ||
 456             (ftgmac100_rxdes_is_udp(rxdes) && !ftgmac100_rxdes_udpcs_err(rxdes)))
 457                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 458
 459         do {
 460                 dma_addr_t map = ftgmac100_rxdes_get_dma_addr(rxdes);
 461                 struct page *page = ftgmac100_rxdes_get_page(rxdes);
 462                 unsigned int size;
 463
 464                 dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
 465
 466                 size = ftgmac100_rxdes_data_length(rxdes);
 467                 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, page, 0, size);
 468
 469                 skb->len += size;
 470                 skb->data_len += size;
 471                 skb->truesize += PAGE_SIZE;
 472
 473                 if (ftgmac100_rxdes_last_segment(rxdes))
 474                         done = true;
 475
 476                 ftgmac100_alloc_rx_page(priv, rxdes, GFP_ATOMIC);
 477
 478                 ftgmac100_rx_pointer_advance(priv);
 479                 rxdes = ftgmac100_current_rxdes(priv);
 480         } while (!done);
 481
 482         if (skb->len <= 64)
 483                 skb->truesize -= PAGE_SIZE;
 484         __pskb_pull_tail(skb, min(skb->len, 64U));
 485         skb->protocol = eth_type_trans(skb, netdev);
 486
 487         netdev->stats.rx_packets++;
 488         netdev->stats.rx_bytes += skb->len;
 489
 490         /* push packet to protocol stack */
 491         napi_gro_receive(&priv->napi, skb);
 492
 493         (*processed)++;
 494         return true;
 495 }
 496
 497 /******************************************************************************
 498  * internal functions (transmit descriptor)
 499  *****************************************************************************/
 500 static void ftgmac100_txdes_reset(struct ftgmac100_txdes *txdes)
 501 {
 502         /* clear all except end of ring bit */
 503         txdes->txdes0 &= cpu_to_le32(FTGMAC100_TXDES0_EDOTR);
 504         txdes->txdes1 = 0;
 505         txdes->txdes2 = 0;
 506         txdes->txdes3 = 0;
 507 }
 508
 509 static bool ftgmac100_txdes_owned_by_dma(struct ftgmac100_txdes *txdes)
 510 {
 511         return txdes->txdes0 & cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN);
 512 }
 513
 514 static void ftgmac100_txdes_set_dma_own(struct ftgmac100_txdes *txdes)
 515 {
 516         /*
 517          * Make sure dma own bit will not be set before any other
 518          * descriptor fields.
 519          */
 520         wmb();
 521         txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN);
 522 }
 523
 524 static void ftgmac100_txdes_set_end_of_ring(struct ftgmac100_txdes *txdes)
 525 {
 526         txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_EDOTR);
 527 }
 528
 529 static void ftgmac100_txdes_set_first_segment(struct ftgmac100_txdes *txdes)
 530 {
 531         txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_FTS);
 532 }
 533
 534 static void ftgmac100_txdes_set_last_segment(struct ftgmac100_txdes *txdes)
 535 {
 536         txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_LTS);
 537 }
 538
 539 static void ftgmac100_txdes_set_buffer_size(struct ftgmac100_txdes *txdes,
 540                                             unsigned int len)
 541 {
 542         txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXBUF_SIZE(len));
 543 }
 544
 545 static void ftgmac100_txdes_set_txint(struct ftgmac100_txdes *txdes)
 546 {
 547         txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TXIC);
 548 }
 549
 550 static void ftgmac100_txdes_set_tcpcs(struct ftgmac100_txdes *txdes)
 551 {
 552         txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TCP_CHKSUM);
 553 }
 554
 555 static void ftgmac100_txdes_set_udpcs(struct ftgmac100_txdes *txdes)
 556 {
 557         txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_UDP_CHKSUM);
 558 }
 559
 560 static void ftgmac100_txdes_set_ipcs(struct ftgmac100_txdes *txdes)
 561 {
 562         txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_IP_CHKSUM);
 563 }
 564
 565 static void ftgmac100_txdes_set_dma_addr(struct ftgmac100_txdes *txdes,
 566                                          dma_addr_t addr)
 567 {
 568         txdes->txdes3 = cpu_to_le32(addr);
 569 }
 570
 571 static dma_addr_t ftgmac100_txdes_get_dma_addr(struct ftgmac100_txdes *txdes)
 572 {
 573         return le32_to_cpu(txdes->txdes3);
 574 }
 575
 576 /*
 577  * txdes2 is not used by hardware. We use it to keep track of socket buffer.
 578  * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu().
 579  */
 580 static void ftgmac100_txdes_set_skb(struct ftgmac100_txdes *txdes,
 581                                     struct sk_buff *skb)
 582 {
 583         txdes->txdes2 = (unsigned int)skb;
 584 }
 585
 586 static struct sk_buff *ftgmac100_txdes_get_skb(struct ftgmac100_txdes *txdes)
 587 {
 588         return (struct sk_buff *)txdes->txdes2;
 589 }
 590
 591 /******************************************************************************
 592  * internal functions (transmit)
 593  *****************************************************************************/
 594 static int ftgmac100_next_tx_pointer(int pointer)
 595 {
 596         return (pointer + 1) & (TX_QUEUE_ENTRIES - 1);
 597 }
 598
 599 static void ftgmac100_tx_pointer_advance(struct ftgmac100 *priv)
 600 {
 601         priv->tx_pointer = ftgmac100_next_tx_pointer(priv->tx_pointer);
 602 }
 603
 604 static void ftgmac100_tx_clean_pointer_advance(struct ftgmac100 *priv)
 605 {
 606         priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv->tx_clean_pointer);
 607 }
 608
 609 static struct ftgmac100_txdes *ftgmac100_current_txdes(struct ftgmac100 *priv)
 610 {
 611         return &priv->descs->txdes[priv->tx_pointer];
 612 }
 613
 614 static struct ftgmac100_txdes *
 615 ftgmac100_current_clean_txdes(struct ftgmac100 *priv)
 616 {
 617         return &priv->descs->txdes[priv->tx_clean_pointer];
 618 }
 619
 620 static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv)
 621 {
 622         struct net_device *netdev = priv->netdev;
 623         struct ftgmac100_txdes *txdes;
 624         struct sk_buff *skb;
 625         dma_addr_t map;
 626
 627         if (priv->tx_pending == 0)
 628                 return false;
 629
 630         txdes = ftgmac100_current_clean_txdes(priv);
 631
 632         if (ftgmac100_txdes_owned_by_dma(txdes))
 633                 return false;
 634
 635         skb = ftgmac100_txdes_get_skb(txdes);
 636         map = ftgmac100_txdes_get_dma_addr(txdes);
 637
 638         netdev->stats.tx_packets++;
 639         netdev->stats.tx_bytes += skb->len;
 640
 641         dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
 642
 643         dev_kfree_skb(skb);
 644
 645         ftgmac100_txdes_reset(txdes);
 646
 647         ftgmac100_tx_clean_pointer_advance(priv);
 648
 649         spin_lock(&priv->tx_lock);
 650         priv->tx_pending--;
 651         spin_unlock(&priv->tx_lock);
 652         netif_wake_queue(netdev);
 653
 654         return true;
 655 }
 656
 657 static void ftgmac100_tx_complete(struct ftgmac100 *priv)
 658 {
 659         while (ftgmac100_tx_complete_packet(priv))
 660                 ;
 661 }
 662
 663 static int ftgmac100_xmit(struct ftgmac100 *priv, struct sk_buff *skb,
 664                           dma_addr_t map)
 665 {
 666         struct net_device *netdev = priv->netdev;
 667         struct ftgmac100_txdes *txdes;
 668         unsigned int len = (skb->len < ETH_ZLEN) ? ETH_ZLEN : skb->len;
 669
 670         txdes = ftgmac100_current_txdes(priv);
 671         ftgmac100_tx_pointer_advance(priv);
 672
 673         /* setup TX descriptor */
 674         ftgmac100_txdes_set_skb(txdes, skb);
 675         ftgmac100_txdes_set_dma_addr(txdes, map);
 676         ftgmac100_txdes_set_buffer_size(txdes, len);
 677
 678         ftgmac100_txdes_set_first_segment(txdes);
 679         ftgmac100_txdes_set_last_segment(txdes);
 680         ftgmac100_txdes_set_txint(txdes);
 681         if (skb->ip_summed == CHECKSUM_PARTIAL) {
 682                 __be16 protocol = skb->protocol;
 683
 684                 if (protocol == cpu_to_be16(ETH_P_IP)) {
 685                         u8 ip_proto = ip_hdr(skb)->protocol;
 686
 687                         ftgmac100_txdes_set_ipcs(txdes);
 688                         if (ip_proto == IPPROTO_TCP)
 689                                 ftgmac100_txdes_set_tcpcs(txdes);
 690                         else if (ip_proto == IPPROTO_UDP)
 691                                 ftgmac100_txdes_set_udpcs(txdes);
 692                 }
 693         }
 694
 695         spin_lock(&priv->tx_lock);
 696         priv->tx_pending++;
 697         if (priv->tx_pending == TX_QUEUE_ENTRIES)
 698                 netif_stop_queue(netdev);
 699
 700         /* start transmit */
 701         ftgmac100_txdes_set_dma_own(txdes);
 702         spin_unlock(&priv->tx_lock);
 703
 704         ftgmac100_txdma_normal_prio_start_polling(priv);
 705
 706         return NETDEV_TX_OK;
 707 }
 708
 709 /******************************************************************************
 710  * internal functions (buffer)
 711  *****************************************************************************/
 712 static int ftgmac100_alloc_rx_page(struct ftgmac100 *priv,
 713                                    struct ftgmac100_rxdes *rxdes, gfp_t gfp)
 714 {
 715         struct net_device *netdev = priv->netdev;
 716         struct page *page;
 717         dma_addr_t map;
 718
 719         page = alloc_page(gfp);
 720         if (!page) {
 721                 if (net_ratelimit())
 722                         netdev_err(netdev, "failed to allocate rx page\n");
 723                 return -ENOMEM;
 724         }
 725
 726         map = dma_map_page(priv->dev, page, 0, RX_BUF_SIZE, DMA_FROM_DEVICE);
 727         if (unlikely(dma_mapping_error(priv->dev, map))) {
 728                 if (net_ratelimit())
 729                         netdev_err(netdev, "failed to map rx page\n");
 730                 __free_page(page);
 731                 return -ENOMEM;
 732         }
 733
 734         ftgmac100_rxdes_set_page(rxdes, page);
 735         ftgmac100_rxdes_set_dma_addr(rxdes, map);
 736         ftgmac100_rxdes_set_dma_own(rxdes);
 737         return 0;
 738 }
 739
 740 static void ftgmac100_free_buffers(struct ftgmac100 *priv)
 741 {
 742         int i;
 743
 744         for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
 745                 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i];
 746                 struct page *page = ftgmac100_rxdes_get_page(rxdes);
 747                 dma_addr_t map = ftgmac100_rxdes_get_dma_addr(rxdes);
 748
 749                 if (!page)
 750                         continue;
 751
 752                 dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
 753                 __free_page(page);
 754         }
 755
 756         for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
 757                 struct ftgmac100_txdes *txdes = &priv->descs->txdes[i];
 758                 struct sk_buff *skb = ftgmac100_txdes_get_skb(txdes);
 759                 dma_addr_t map = ftgmac100_txdes_get_dma_addr(txdes);
 760
 761                 if (!skb)
 762                         continue;
 763
 764                 dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
 765                 dev_kfree_skb(skb);
 766         }
 767
 768         dma_free_coherent(priv->dev, sizeof(struct ftgmac100_descs),
 769                           priv->descs, priv->descs_dma_addr);
 770 }
 771
 772 static int ftgmac100_alloc_buffers(struct ftgmac100 *priv)
 773 {
 774         int i;
 775
 776         priv->descs = dma_alloc_coherent(priv->dev,
 777                                          sizeof(struct ftgmac100_descs),
 778                                          &priv->descs_dma_addr, GFP_KERNEL);
 779         if (!priv->descs)
 780                 return -ENOMEM;
 781
 782         memset(priv->descs, 0, sizeof(struct ftgmac100_descs));
 783
 784         /* initialize RX ring */
 785         ftgmac100_rxdes_set_end_of_ring(&priv->descs->rxdes[RX_QUEUE_ENTRIES - 1]);
 786
 787         for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
 788                 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i];
 789
 790                 if (ftgmac100_alloc_rx_page(priv, rxdes, GFP_KERNEL))
 791                         goto err;
 792         }
 793
 794         /* initialize TX ring */
 795         ftgmac100_txdes_set_end_of_ring(&priv->descs->txdes[TX_QUEUE_ENTRIES - 1]);
 796         return 0;
 797
 798 err:
 799         ftgmac100_free_buffers(priv);
 800         return -ENOMEM;
 801 }
 802
 803 /******************************************************************************
 804  * internal functions (mdio)
 805  *****************************************************************************/
 806 static void ftgmac100_adjust_link(struct net_device *netdev)
 807 {
 808         struct ftgmac100 *priv = netdev_priv(netdev);
 809         struct phy_device *phydev = priv->phydev;
 810         int ier;
 811
 812         if (phydev->speed == priv->old_speed)
 813                 return;
 814
 815         priv->old_speed = phydev->speed;
 816
 817         ier = ioread32(priv->base + FTGMAC100_OFFSET_IER);
 818
 819         /* disable all interrupts */
 820         iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
 821
 822         netif_stop_queue(netdev);
 823         ftgmac100_stop_hw(priv);
 824
 825         netif_start_queue(netdev);
 826         ftgmac100_init_hw(priv);
 827         ftgmac100_start_hw(priv, phydev->speed);
 828
 829         /* re-enable interrupts */
 830         iowrite32(ier, priv->base + FTGMAC100_OFFSET_IER);
 831 }
 832
 833 static int ftgmac100_mii_probe(struct ftgmac100 *priv)
 834 {
 835         struct net_device *netdev = priv->netdev;
 836         struct phy_device *phydev = NULL;
 837         int i;
 838
 839         /* search for connect PHY device */
 840         for (i = 0; i < PHY_MAX_ADDR; i++) {
 841                 struct phy_device *tmp = priv->mii_bus->phy_map[i];
 842
 843                 if (tmp) {
 844                         phydev = tmp;
 845                         break;
 846                 }
 847         }
 848
 849         /* now we are supposed to have a proper phydev, to attach to... */
 850         if (!phydev) {
 851                 netdev_info(netdev, "%s: no PHY found\n", netdev->name);
 852                 return -ENODEV;
 853         }
 854
 855         phydev = phy_connect(netdev, dev_name(&phydev->dev),
 856                              &ftgmac100_adjust_link, 0,
 857                              PHY_INTERFACE_MODE_GMII);
 858
 859         if (IS_ERR(phydev)) {
 860                 netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name);
 861                 return PTR_ERR(phydev);
 862         }
 863
 864         priv->phydev = phydev;
 865         return 0;
 866 }
 867
 868 /******************************************************************************
 869  * struct mii_bus functions
 870  *****************************************************************************/
 871 static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
 872 {
 873         struct net_device *netdev = bus->priv;
 874         struct ftgmac100 *priv = netdev_priv(netdev);
 875         unsigned int phycr;
 876         int i;
 877
 878         phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
 879
 880         /* preserve MDC cycle threshold */
 881         phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
 882
 883         phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
 884                  FTGMAC100_PHYCR_REGAD(regnum) |
 885                  FTGMAC100_PHYCR_MIIRD;
 886
 887         iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
 888
 889         for (i = 0; i < 10; i++) {
 890                 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
 891
 892                 if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
 893                         int data;
 894
 895                         data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA);
 896                         return FTGMAC100_PHYDATA_MIIRDATA(data);
 897                 }
 898
 899                 udelay(100);
 900         }
 901
 902         netdev_err(netdev, "mdio read timed out\n");
 903         return -EIO;
 904 }
 905
 906 static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr,
 907                                    int regnum, u16 value)
 908 {
 909         struct net_device *netdev = bus->priv;
 910         struct ftgmac100 *priv = netdev_priv(netdev);
 911         unsigned int phycr;
 912         int data;
 913         int i;
 914
 915         phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
 916
 917         /* preserve MDC cycle threshold */
 918         phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
 919
 920         phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
 921                  FTGMAC100_PHYCR_REGAD(regnum) |
 922                  FTGMAC100_PHYCR_MIIWR;
 923
 924         data = FTGMAC100_PHYDATA_MIIWDATA(value);
 925
 926         iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA);
 927         iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
 928
 929         for (i = 0; i < 10; i++) {
 930                 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
 931
 932                 if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0)
 933                         return 0;
 934
 935                 udelay(100);
 936         }
 937
 938         netdev_err(netdev, "mdio write timed out\n");
 939         return -EIO;
 940 }
 941
 942 static int ftgmac100_mdiobus_reset(struct mii_bus *bus)
 943 {
 944         return 0;
 945 }
 946
 947 /******************************************************************************
 948  * struct ethtool_ops functions
 949  *****************************************************************************/
 950 static void ftgmac100_get_drvinfo(struct net_device *netdev,
 951                                   struct ethtool_drvinfo *info)
 952 {
 953         strcpy(info->driver, DRV_NAME);
 954         strcpy(info->version, DRV_VERSION);
 955         strcpy(info->bus_info, dev_name(&netdev->dev));
 956 }
 957
 958 static int ftgmac100_get_settings(struct net_device *netdev,
 959                                   struct ethtool_cmd *cmd)
 960 {
 961         struct ftgmac100 *priv = netdev_priv(netdev);
 962
 963         return phy_ethtool_gset(priv->phydev, cmd);
 964 }
 965
 966 static int ftgmac100_set_settings(struct net_device *netdev,
 967                                   struct ethtool_cmd *cmd)
 968 {
 969         struct ftgmac100 *priv = netdev_priv(netdev);
 970
 971         return phy_ethtool_sset(priv->phydev, cmd);
 972 }
 973
 974 static const struct ethtool_ops ftgmac100_ethtool_ops = {
 975         .set_settings           = ftgmac100_set_settings,
 976         .get_settings           = ftgmac100_get_settings,
 977         .get_drvinfo            = ftgmac100_get_drvinfo,
 978         .get_link               = ethtool_op_get_link,
 979 };
 980
 981 /******************************************************************************
 982  * interrupt handler
 983  *****************************************************************************/
 984 static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id)
 985 {
 986         struct net_device *netdev = dev_id;
 987         struct ftgmac100 *priv = netdev_priv(netdev);
 988
 989         if (likely(netif_running(netdev))) {
 990                 /* Disable interrupts for polling */
 991                 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
 992                 napi_schedule(&priv->napi);
 993         }
 994
 995         return IRQ_HANDLED;
 996 }
 997
 998 /******************************************************************************
 999  * struct napi_struct functions
1000  *****************************************************************************/
1001 static int ftgmac100_poll(struct napi_struct *napi, int budget)
1002 {
1003         struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi);
1004         struct net_device *netdev = priv->netdev;
1005         unsigned int status;
1006         bool completed = true;
1007         int rx = 0;
1008
1009         status = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
1010         iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR);
1011
1012         if (status & (FTGMAC100_INT_RPKT_BUF | FTGMAC100_INT_NO_RXBUF)) {
1013                 /*
1014                  * FTGMAC100_INT_RPKT_BUF:
1015                  *      RX DMA has received packets into RX buffer successfully
1016                  *
1017                  * FTGMAC100_INT_NO_RXBUF:
1018                  *      RX buffer unavailable
1019                  */
1020                 bool retry;
1021
1022                 do {
1023                         retry = ftgmac100_rx_packet(priv, &rx);
1024                 } while (retry && rx < budget);
1025
1026                 if (retry && rx == budget)
1027                         completed = false;
1028         }
1029
1030         if (status & (FTGMAC100_INT_XPKT_ETH | FTGMAC100_INT_XPKT_LOST)) {
1031                 /*
1032                  * FTGMAC100_INT_XPKT_ETH:
1033                  *      packet transmitted to ethernet successfully
1034                  *
1035                  * FTGMAC100_INT_XPKT_LOST:
1036                  *      packet transmitted to ethernet lost due to late
1037                  *      collision or excessive collision
1038                  */
1039                 ftgmac100_tx_complete(priv);
1040         }
1041
1042         if (status & (FTGMAC100_INT_NO_RXBUF | FTGMAC100_INT_RPKT_LOST |
1043                       FTGMAC100_INT_AHB_ERR | FTGMAC100_INT_PHYSTS_CHG)) {
1044                 if (net_ratelimit())
1045                         netdev_info(netdev, "[ISR] = 0x%x: %s%s%s%s\n", status,
1046                                     status & FTGMAC100_INT_NO_RXBUF ? "NO_RXBUF " : "",
1047                                     status & FTGMAC100_INT_RPKT_LOST ? "RPKT_LOST " : "",
1048                                     status & FTGMAC100_INT_AHB_ERR ? "AHB_ERR " : "",
1049                                     status & FTGMAC100_INT_PHYSTS_CHG ? "PHYSTS_CHG" : "");
1050
1051                 if (status & FTGMAC100_INT_NO_RXBUF) {
1052                         /* RX buffer unavailable */
1053                         netdev->stats.rx_over_errors++;
1054                 }
1055
1056                 if (status & FTGMAC100_INT_RPKT_LOST) {
1057                         /* received packet lost due to RX FIFO full */
1058                         netdev->stats.rx_fifo_errors++;
1059                 }
1060         }
1061
1062         if (completed) {
1063                 napi_complete(napi);
1064
1065                 /* enable all interrupts */
1066                 iowrite32(INT_MASK_ALL_ENABLED, priv->base + FTGMAC100_OFFSET_IER);
1067         }
1068
1069         return rx;
1070 }
1071
1072 /******************************************************************************
1073  * struct net_device_ops functions
1074  *****************************************************************************/
1075 static int ftgmac100_open(struct net_device *netdev)
1076 {
1077         struct ftgmac100 *priv = netdev_priv(netdev);
1078         int err;
1079
1080         err = ftgmac100_alloc_buffers(priv);
1081         if (err) {
1082                 netdev_err(netdev, "failed to allocate buffers\n");
1083                 goto err_alloc;
1084         }
1085
1086         err = request_irq(priv->irq, ftgmac100_interrupt, 0, netdev->name, netdev);
1087         if (err) {
1088                 netdev_err(netdev, "failed to request irq %d\n", priv->irq);
1089                 goto err_irq;
1090         }
1091
1092         priv->rx_pointer = 0;
1093         priv->tx_clean_pointer = 0;
1094         priv->tx_pointer = 0;
1095         priv->tx_pending = 0;
1096
1097         err = ftgmac100_reset_hw(priv);
1098         if (err)
1099                 goto err_hw;
1100
1101         ftgmac100_init_hw(priv);
1102         ftgmac100_start_hw(priv, 10);
1103
1104         phy_start(priv->phydev);
1105
1106         napi_enable(&priv->napi);
1107         netif_start_queue(netdev);
1108
1109         /* enable all interrupts */
1110         iowrite32(INT_MASK_ALL_ENABLED, priv->base + FTGMAC100_OFFSET_IER);
1111         return 0;
1112
1113 err_hw:
1114         free_irq(priv->irq, netdev);
1115 err_irq:
1116         ftgmac100_free_buffers(priv);
1117 err_alloc:
1118         return err;
1119 }
1120
1121 static int ftgmac100_stop(struct net_device *netdev)
1122 {
1123         struct ftgmac100 *priv = netdev_priv(netdev);
1124
1125         /* disable all interrupts */
1126         iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1127
1128         netif_stop_queue(netdev);
1129         napi_disable(&priv->napi);
1130         phy_stop(priv->phydev);
1131
1132         ftgmac100_stop_hw(priv);
1133         free_irq(priv->irq, netdev);
1134         ftgmac100_free_buffers(priv);
1135
1136         return 0;
1137 }
1138
1139 static int ftgmac100_hard_start_xmit(struct sk_buff *skb,
1140                                      struct net_device *netdev)
1141 {
1142         struct ftgmac100 *priv = netdev_priv(netdev);
1143         dma_addr_t map;
1144
1145         if (unlikely(skb->len > MAX_PKT_SIZE)) {
1146                 if (net_ratelimit())
1147                         netdev_dbg(netdev, "tx packet too big\n");
1148
1149                 netdev->stats.tx_dropped++;
1150                 dev_kfree_skb(skb);
1151                 return NETDEV_TX_OK;
1152         }
1153
1154         map = dma_map_single(priv->dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE);
1155         if (unlikely(dma_mapping_error(priv->dev, map))) {
1156                 /* drop packet */
1157                 if (net_ratelimit())
1158                         netdev_err(netdev, "map socket buffer failed\n");
1159
1160                 netdev->stats.tx_dropped++;
1161                 dev_kfree_skb(skb);
1162                 return NETDEV_TX_OK;
1163         }
1164
1165         return ftgmac100_xmit(priv, skb, map);
1166 }
1167
1168 /* optional */
1169 static int ftgmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1170 {
1171         struct ftgmac100 *priv = netdev_priv(netdev);
1172
1173         return phy_mii_ioctl(priv->phydev, ifr, cmd);
1174 }
1175
1176 static const struct net_device_ops ftgmac100_netdev_ops = {
1177         .ndo_open               = ftgmac100_open,
1178         .ndo_stop               = ftgmac100_stop,
1179         .ndo_start_xmit         = ftgmac100_hard_start_xmit,
1180         .ndo_set_mac_address    = eth_mac_addr,
1181         .ndo_validate_addr      = eth_validate_addr,
1182         .ndo_do_ioctl           = ftgmac100_do_ioctl,
1183 };
1184
1185 /******************************************************************************
1186  * struct platform_driver functions
1187  *****************************************************************************/
1188 static int ftgmac100_probe(struct platform_device *pdev)
1189 {
1190         struct resource *res;
1191         int irq;
1192         struct net_device *netdev;
1193         struct ftgmac100 *priv;
1194         int err;
1195         int i;
1196
1197         if (!pdev)
1198                 return -ENODEV;
1199
1200         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1201         if (!res)
1202                 return -ENXIO;
1203
1204         irq = platform_get_irq(pdev, 0);
1205         if (irq < 0)
1206                 return irq;
1207
1208         /* setup net_device */
1209         netdev = alloc_etherdev(sizeof(*priv));
1210         if (!netdev) {
1211                 err = -ENOMEM;
1212                 goto err_alloc_etherdev;
1213         }
1214
1215         SET_NETDEV_DEV(netdev, &pdev->dev);
1216
1217         SET_ETHTOOL_OPS(netdev, &ftgmac100_ethtool_ops);
1218         netdev->netdev_ops = &ftgmac100_netdev_ops;
1219         netdev->features = NETIF_F_IP_CSUM | NETIF_F_GRO;
1220
1221         platform_set_drvdata(pdev, netdev);
1222
1223         /* setup private data */
1224         priv = netdev_priv(netdev);
1225         priv->netdev = netdev;
1226         priv->dev = &pdev->dev;
1227
1228         spin_lock_init(&priv->tx_lock);
1229
1230         /* initialize NAPI */
1231         netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64);
1232
1233         /* map io memory */
1234         priv->res = request_mem_region(res->start, resource_size(res),
1235                                        dev_name(&pdev->dev));
1236         if (!priv->res) {
1237                 dev_err(&pdev->dev, "Could not reserve memory region\n");
1238                 err = -ENOMEM;
1239                 goto err_req_mem;
1240         }
1241
1242         priv->base = ioremap(res->start, resource_size(res));
1243         if (!priv->base) {
1244                 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
1245                 err = -EIO;
1246                 goto err_ioremap;
1247         }
1248
1249         priv->irq = irq;
1250
1251         /* initialize mdio bus */
1252         priv->mii_bus = mdiobus_alloc();
1253         if (!priv->mii_bus) {
1254                 err = -EIO;
1255                 goto err_alloc_mdiobus;
1256         }
1257
1258         priv->mii_bus->name = "ftgmac100_mdio";
1259         snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "ftgmac100_mii");
1260
1261         priv->mii_bus->priv = netdev;
1262         priv->mii_bus->read = ftgmac100_mdiobus_read;
1263         priv->mii_bus->write = ftgmac100_mdiobus_write;
1264         priv->mii_bus->reset = ftgmac100_mdiobus_reset;
1265         priv->mii_bus->irq = priv->phy_irq;
1266
1267         for (i = 0; i < PHY_MAX_ADDR; i++)
1268                 priv->mii_bus->irq[i] = PHY_POLL;
1269
1270         err = mdiobus_register(priv->mii_bus);
1271         if (err) {
1272                 dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
1273                 goto err_register_mdiobus;
1274         }
1275
1276         err = ftgmac100_mii_probe(priv);
1277         if (err) {
1278                 dev_err(&pdev->dev, "MII Probe failed!\n");
1279                 goto err_mii_probe;
1280         }
1281
1282         /* register network device */
1283         err = register_netdev(netdev);
1284         if (err) {
1285                 dev_err(&pdev->dev, "Failed to register netdev\n");
1286                 goto err_register_netdev;
1287         }
1288
1289         netdev_info(netdev, "irq %d, mapped at %p\n", priv->irq, priv->base);
1290
1291         if (!is_valid_ether_addr(netdev->dev_addr)) {
1292                 eth_hw_addr_random(netdev);
1293                 netdev_info(netdev, "generated random MAC address %pM\n",
1294                             netdev->dev_addr);
1295         }
1296
1297         return 0;
1298
1299 err_register_netdev:
1300         phy_disconnect(priv->phydev);
1301 err_mii_probe:
1302         mdiobus_unregister(priv->mii_bus);
1303 err_register_mdiobus:
1304         mdiobus_free(priv->mii_bus);
1305 err_alloc_mdiobus:
1306         iounmap(priv->base);
1307 err_ioremap:
1308         release_resource(priv->res);
1309 err_req_mem:
1310         netif_napi_del(&priv->napi);
1311         platform_set_drvdata(pdev, NULL);
1312         free_netdev(netdev);
1313 err_alloc_etherdev:
1314         return err;
1315 }
1316
1317 static int __exit ftgmac100_remove(struct platform_device *pdev)
1318 {
1319         struct net_device *netdev;
1320         struct ftgmac100 *priv;
1321
1322         netdev = platform_get_drvdata(pdev);
1323         priv = netdev_priv(netdev);
1324
1325         unregister_netdev(netdev);
1326
1327         phy_disconnect(priv->phydev);
1328         mdiobus_unregister(priv->mii_bus);
1329         mdiobus_free(priv->mii_bus);
1330
1331         iounmap(priv->base);
1332         release_resource(priv->res);
1333
1334         netif_napi_del(&priv->napi);
1335         platform_set_drvdata(pdev, NULL);
1336         free_netdev(netdev);
1337         return 0;
1338 }
1339
1340 static struct platform_driver ftgmac100_driver = {
1341         .probe          = ftgmac100_probe,
1342         .remove         = __exit_p(ftgmac100_remove),
1343         .driver         = {
1344                 .name   = DRV_NAME,
1345                 .owner  = THIS_MODULE,
1346         },
1347 };
1348
1349 /******************************************************************************
1350  * initialization / finalization
1351  *****************************************************************************/
1352 static int __init ftgmac100_init(void)
1353 {
1354         pr_info("Loading version " DRV_VERSION " ...\n");
1355         return platform_driver_register(&ftgmac100_driver);
1356 }
1357
1358 static void __exit ftgmac100_exit(void)
1359 {
1360         platform_driver_unregister(&ftgmac100_driver);
1361 }
1362
1363 module_init(ftgmac100_init);
1364 module_exit(ftgmac100_exit);
1365
1366 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
1367 MODULE_DESCRIPTION("FTGMAC100 driver");
1368 MODULE_LICENSE("GPL");