2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
38 #define MYPF_BASE 0x1b000
39 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
41 #define PF0_BASE 0x1e000
42 #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))
44 #define PF_STRIDE 0x400
45 #define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
46 #define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
48 #define MYPORT_BASE 0x1c000
49 #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))
51 #define PORT0_BASE 0x20000
52 #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))
54 #define PORT_STRIDE 0x2000
55 #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)
56 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
58 #define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)
59 #define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)
61 #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
62 #define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
63 #define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
64 #define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
66 #define SGE_PF_KDOORBELL 0x0
67 #define QID_MASK 0xffff8000U
69 #define QID(x) ((x) << QID_SHIFT)
70 #define DBPRIO(x) ((x) << 14)
71 #define DBTYPE(x) ((x) << 13)
72 #define PIDX_MASK 0x00003fffU
74 #define PIDX(x) ((x) << PIDX_SHIFT)
75 #define PIDX_SHIFT_T5 0
76 #define PIDX_T5(x) ((x) << PIDX_SHIFT_T5)
79 #define SGE_TIMERREGS 6
80 #define SGE_PF_GTS 0x4
81 #define INGRESSQID_MASK 0xffff0000U
82 #define INGRESSQID_SHIFT 16
83 #define INGRESSQID(x) ((x) << INGRESSQID_SHIFT)
84 #define TIMERREG_MASK 0x0000e000U
85 #define TIMERREG_SHIFT 13
86 #define TIMERREG(x) ((x) << TIMERREG_SHIFT)
87 #define SEINTARM_MASK 0x00001000U
88 #define SEINTARM_SHIFT 12
89 #define SEINTARM(x) ((x) << SEINTARM_SHIFT)
90 #define CIDXINC_MASK 0x00000fffU
91 #define CIDXINC_SHIFT 0
92 #define CIDXINC(x) ((x) << CIDXINC_SHIFT)
94 #define X_RXPKTCPLMODE_SPLIT 1
95 #define X_INGPADBOUNDARY_SHIFT 5
97 #define SGE_CONTROL 0x1008
98 #define SGE_CONTROL2_A 0x1124
99 #define DCASYSTYPE 0x00080000U
100 #define RXPKTCPLMODE_MASK 0x00040000U
101 #define RXPKTCPLMODE_SHIFT 18
102 #define RXPKTCPLMODE(x) ((x) << RXPKTCPLMODE_SHIFT)
103 #define EGRSTATUSPAGESIZE_MASK 0x00020000U
104 #define EGRSTATUSPAGESIZE_SHIFT 17
105 #define EGRSTATUSPAGESIZE(x) ((x) << EGRSTATUSPAGESIZE_SHIFT)
106 #define PKTSHIFT_MASK 0x00001c00U
107 #define PKTSHIFT_SHIFT 10
108 #define PKTSHIFT(x) ((x) << PKTSHIFT_SHIFT)
109 #define PKTSHIFT_GET(x) (((x) & PKTSHIFT_MASK) >> PKTSHIFT_SHIFT)
110 #define INGPCIEBOUNDARY_32B_X 0
111 #define INGPCIEBOUNDARY_MASK 0x00000380U
112 #define INGPCIEBOUNDARY_SHIFT 7
113 #define INGPCIEBOUNDARY(x) ((x) << INGPCIEBOUNDARY_SHIFT)
114 #define INGPADBOUNDARY_MASK 0x00000070U
115 #define INGPADBOUNDARY_SHIFT 4
116 #define INGPADBOUNDARY(x) ((x) << INGPADBOUNDARY_SHIFT)
117 #define INGPADBOUNDARY_GET(x) (((x) & INGPADBOUNDARY_MASK) \
118 >> INGPADBOUNDARY_SHIFT)
119 #define INGPACKBOUNDARY_16B_X 0
120 #define INGPACKBOUNDARY_SHIFT_X 5
122 #define INGPACKBOUNDARY_S 16
123 #define INGPACKBOUNDARY_M 0x7U
124 #define INGPACKBOUNDARY_V(x) ((x) << INGPACKBOUNDARY_S)
125 #define INGPACKBOUNDARY_G(x) (((x) >> INGPACKBOUNDARY_S) \
127 #define EGRPCIEBOUNDARY_MASK 0x0000000eU
128 #define EGRPCIEBOUNDARY_SHIFT 1
129 #define EGRPCIEBOUNDARY(x) ((x) << EGRPCIEBOUNDARY_SHIFT)
130 #define GLOBALENABLE 0x00000001U
132 #define SGE_HOST_PAGE_SIZE 0x100c
134 #define HOSTPAGESIZEPF7_MASK 0x0000000fU
135 #define HOSTPAGESIZEPF7_SHIFT 28
136 #define HOSTPAGESIZEPF7(x) ((x) << HOSTPAGESIZEPF7_SHIFT)
138 #define HOSTPAGESIZEPF6_MASK 0x0000000fU
139 #define HOSTPAGESIZEPF6_SHIFT 24
140 #define HOSTPAGESIZEPF6(x) ((x) << HOSTPAGESIZEPF6_SHIFT)
142 #define HOSTPAGESIZEPF5_MASK 0x0000000fU
143 #define HOSTPAGESIZEPF5_SHIFT 20
144 #define HOSTPAGESIZEPF5(x) ((x) << HOSTPAGESIZEPF5_SHIFT)
146 #define HOSTPAGESIZEPF4_MASK 0x0000000fU
147 #define HOSTPAGESIZEPF4_SHIFT 16
148 #define HOSTPAGESIZEPF4(x) ((x) << HOSTPAGESIZEPF4_SHIFT)
150 #define HOSTPAGESIZEPF3_MASK 0x0000000fU
151 #define HOSTPAGESIZEPF3_SHIFT 12
152 #define HOSTPAGESIZEPF3(x) ((x) << HOSTPAGESIZEPF3_SHIFT)
154 #define HOSTPAGESIZEPF2_MASK 0x0000000fU
155 #define HOSTPAGESIZEPF2_SHIFT 8
156 #define HOSTPAGESIZEPF2(x) ((x) << HOSTPAGESIZEPF2_SHIFT)
158 #define HOSTPAGESIZEPF1_M 0x0000000fU
159 #define HOSTPAGESIZEPF1_S 4
160 #define HOSTPAGESIZEPF1(x) ((x) << HOSTPAGESIZEPF1_S)
162 #define HOSTPAGESIZEPF0_M 0x0000000fU
163 #define HOSTPAGESIZEPF0_S 0
164 #define HOSTPAGESIZEPF0(x) ((x) << HOSTPAGESIZEPF0_S)
166 #define SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010
167 #define SGE_EGRESS_QUEUES_PER_PAGE_VF_A 0x1014
169 #define QUEUESPERPAGEPF1_S 4
171 #define QUEUESPERPAGEPF0_S 0
172 #define QUEUESPERPAGEPF0_MASK 0x0000000fU
173 #define QUEUESPERPAGEPF0_GET(x) ((x) & QUEUESPERPAGEPF0_MASK)
175 #define QUEUESPERPAGEPF0 0
176 #define QUEUESPERPAGEPF1 4
178 /* T5 and later support a new BAR2-based doorbell mechanism for Egress Queues.
179 * The User Doorbells are each 128 bytes in length with a Simple Doorbell at
180 * offsets 8x and a Write Combining single 64-byte Egress Queue Unit
181 * (X_IDXSIZE_UNIT) Gather Buffer interface at offset 64. For Ingress Queues,
182 * we have a Going To Sleep register at offsets 8x+4.
184 * As noted above, we have many instances of the Simple Doorbell and Going To
185 * Sleep registers at offsets 8x and 8x+4, respectively. We want to use a
186 * non-64-byte aligned offset for the Simple Doorbell in order to attempt to
187 * avoid buffering of the writes to the Simple Doorbell and we want to use a
188 * non-contiguous offset for the Going To Sleep writes in order to avoid
189 * possible combining between them.
191 #define SGE_UDB_SIZE 128
192 #define SGE_UDB_KDOORBELL 8
193 #define SGE_UDB_GTS 20
194 #define SGE_UDB_WCDOORBELL 64
196 #define SGE_INT_CAUSE1 0x1024
197 #define SGE_INT_CAUSE2 0x1030
198 #define SGE_INT_CAUSE3 0x103c
199 #define ERR_FLM_DBP 0x80000000U
200 #define ERR_FLM_IDMA1 0x40000000U
201 #define ERR_FLM_IDMA0 0x20000000U
202 #define ERR_FLM_HINT 0x10000000U
203 #define ERR_PCIE_ERROR3 0x08000000U
204 #define ERR_PCIE_ERROR2 0x04000000U
205 #define ERR_PCIE_ERROR1 0x02000000U
206 #define ERR_PCIE_ERROR0 0x01000000U
207 #define ERR_TIMER_ABOVE_MAX_QID 0x00800000U
208 #define ERR_CPL_EXCEED_IQE_SIZE 0x00400000U
209 #define ERR_INVALID_CIDX_INC 0x00200000U
210 #define ERR_ITP_TIME_PAUSED 0x00100000U
211 #define ERR_CPL_OPCODE_0 0x00080000U
212 #define ERR_DROPPED_DB 0x00040000U
213 #define ERR_DATA_CPL_ON_HIGH_QID1 0x00020000U
214 #define ERR_DATA_CPL_ON_HIGH_QID0 0x00010000U
215 #define ERR_BAD_DB_PIDX3 0x00008000U
216 #define ERR_BAD_DB_PIDX2 0x00004000U
217 #define ERR_BAD_DB_PIDX1 0x00002000U
218 #define ERR_BAD_DB_PIDX0 0x00001000U
219 #define ERR_ING_PCIE_CHAN 0x00000800U
220 #define ERR_ING_CTXT_PRIO 0x00000400U
221 #define ERR_EGR_CTXT_PRIO 0x00000200U
222 #define DBFIFO_HP_INT 0x00000100U
223 #define DBFIFO_LP_INT 0x00000080U
224 #define REG_ADDRESS_ERR 0x00000040U
225 #define INGRESS_SIZE_ERR 0x00000020U
226 #define EGRESS_SIZE_ERR 0x00000010U
227 #define ERR_INV_CTXT3 0x00000008U
228 #define ERR_INV_CTXT2 0x00000004U
229 #define ERR_INV_CTXT1 0x00000002U
230 #define ERR_INV_CTXT0 0x00000001U
232 #define SGE_INT_ENABLE3 0x1040
233 #define SGE_FL_BUFFER_SIZE0 0x1044
234 #define SGE_FL_BUFFER_SIZE1 0x1048
235 #define SGE_FL_BUFFER_SIZE2 0x104c
236 #define SGE_FL_BUFFER_SIZE3 0x1050
237 #define SGE_FL_BUFFER_SIZE4 0x1054
238 #define SGE_FL_BUFFER_SIZE5 0x1058
239 #define SGE_FL_BUFFER_SIZE6 0x105c
240 #define SGE_FL_BUFFER_SIZE7 0x1060
241 #define SGE_FL_BUFFER_SIZE8 0x1064
243 #define SGE_INGRESS_RX_THRESHOLD 0x10a0
244 #define THRESHOLD_0_MASK 0x3f000000U
245 #define THRESHOLD_0_SHIFT 24
246 #define THRESHOLD_0(x) ((x) << THRESHOLD_0_SHIFT)
247 #define THRESHOLD_0_GET(x) (((x) & THRESHOLD_0_MASK) >> THRESHOLD_0_SHIFT)
248 #define THRESHOLD_1_MASK 0x003f0000U
249 #define THRESHOLD_1_SHIFT 16
250 #define THRESHOLD_1(x) ((x) << THRESHOLD_1_SHIFT)
251 #define THRESHOLD_1_GET(x) (((x) & THRESHOLD_1_MASK) >> THRESHOLD_1_SHIFT)
252 #define THRESHOLD_2_MASK 0x00003f00U
253 #define THRESHOLD_2_SHIFT 8
254 #define THRESHOLD_2(x) ((x) << THRESHOLD_2_SHIFT)
255 #define THRESHOLD_2_GET(x) (((x) & THRESHOLD_2_MASK) >> THRESHOLD_2_SHIFT)
256 #define THRESHOLD_3_MASK 0x0000003fU
257 #define THRESHOLD_3_SHIFT 0
258 #define THRESHOLD_3(x) ((x) << THRESHOLD_3_SHIFT)
259 #define THRESHOLD_3_GET(x) (((x) & THRESHOLD_3_MASK) >> THRESHOLD_3_SHIFT)
261 #define SGE_CONM_CTRL 0x1094
262 #define EGRTHRESHOLD_MASK 0x00003f00U
263 #define EGRTHRESHOLDshift 8
264 #define EGRTHRESHOLD(x) ((x) << EGRTHRESHOLDshift)
265 #define EGRTHRESHOLD_GET(x) (((x) & EGRTHRESHOLD_MASK) >> EGRTHRESHOLDshift)
267 #define EGRTHRESHOLDPACKING_MASK 0x3fU
268 #define EGRTHRESHOLDPACKING_SHIFT 14
269 #define EGRTHRESHOLDPACKING(x) ((x) << EGRTHRESHOLDPACKING_SHIFT)
270 #define EGRTHRESHOLDPACKING_GET(x) (((x) >> EGRTHRESHOLDPACKING_SHIFT) & \
271 EGRTHRESHOLDPACKING_MASK)
273 #define SGE_DBFIFO_STATUS 0x10a4
274 #define HP_INT_THRESH_SHIFT 28
275 #define HP_INT_THRESH_MASK 0xfU
276 #define HP_INT_THRESH(x) ((x) << HP_INT_THRESH_SHIFT)
277 #define LP_INT_THRESH_SHIFT 12
278 #define LP_INT_THRESH_MASK 0xfU
279 #define LP_INT_THRESH(x) ((x) << LP_INT_THRESH_SHIFT)
281 #define SGE_DOORBELL_CONTROL 0x10a8
282 #define ENABLE_DROP (1 << 13)
284 #define S_NOCOALESCE 26
285 #define V_NOCOALESCE(x) ((x) << S_NOCOALESCE)
286 #define F_NOCOALESCE V_NOCOALESCE(1U)
288 #define SGE_TIMESTAMP_LO 0x1098
289 #define SGE_TIMESTAMP_HI 0x109c
291 #define M_TSVAL 0xfffffffU
292 #define GET_TSVAL(x) (((x) >> S_TSVAL) & M_TSVAL)
294 #define SGE_TIMER_VALUE_0_AND_1 0x10b8
295 #define TIMERVALUE0_MASK 0xffff0000U
296 #define TIMERVALUE0_SHIFT 16
297 #define TIMERVALUE0(x) ((x) << TIMERVALUE0_SHIFT)
298 #define TIMERVALUE0_GET(x) (((x) & TIMERVALUE0_MASK) >> TIMERVALUE0_SHIFT)
299 #define TIMERVALUE1_MASK 0x0000ffffU
300 #define TIMERVALUE1_SHIFT 0
301 #define TIMERVALUE1(x) ((x) << TIMERVALUE1_SHIFT)
302 #define TIMERVALUE1_GET(x) (((x) & TIMERVALUE1_MASK) >> TIMERVALUE1_SHIFT)
304 #define SGE_TIMER_VALUE_2_AND_3 0x10bc
305 #define TIMERVALUE2_MASK 0xffff0000U
306 #define TIMERVALUE2_SHIFT 16
307 #define TIMERVALUE2(x) ((x) << TIMERVALUE2_SHIFT)
308 #define TIMERVALUE2_GET(x) (((x) & TIMERVALUE2_MASK) >> TIMERVALUE2_SHIFT)
309 #define TIMERVALUE3_MASK 0x0000ffffU
310 #define TIMERVALUE3_SHIFT 0
311 #define TIMERVALUE3(x) ((x) << TIMERVALUE3_SHIFT)
312 #define TIMERVALUE3_GET(x) (((x) & TIMERVALUE3_MASK) >> TIMERVALUE3_SHIFT)
314 #define SGE_TIMER_VALUE_4_AND_5 0x10c0
315 #define TIMERVALUE4_MASK 0xffff0000U
316 #define TIMERVALUE4_SHIFT 16
317 #define TIMERVALUE4(x) ((x) << TIMERVALUE4_SHIFT)
318 #define TIMERVALUE4_GET(x) (((x) & TIMERVALUE4_MASK) >> TIMERVALUE4_SHIFT)
319 #define TIMERVALUE5_MASK 0x0000ffffU
320 #define TIMERVALUE5_SHIFT 0
321 #define TIMERVALUE5(x) ((x) << TIMERVALUE5_SHIFT)
322 #define TIMERVALUE5_GET(x) (((x) & TIMERVALUE5_MASK) >> TIMERVALUE5_SHIFT)
324 #define SGE_DEBUG_INDEX 0x10cc
325 #define SGE_DEBUG_DATA_HIGH 0x10d0
326 #define SGE_DEBUG_DATA_LOW 0x10d4
327 #define SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8
328 #define SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc
329 #define SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8
330 #define SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4
331 #define SGE_INGRESS_QUEUES_PER_PAGE_VF_A 0x10f8
333 #define S_HP_INT_THRESH 28
334 #define M_HP_INT_THRESH 0xfU
335 #define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH)
336 #define S_LP_INT_THRESH_T5 18
337 #define V_LP_INT_THRESH_T5(x) ((x) << S_LP_INT_THRESH_T5)
338 #define M_LP_COUNT_T5 0x3ffffU
339 #define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT) & M_LP_COUNT_T5)
340 #define M_HP_COUNT 0x7ffU
341 #define S_HP_COUNT 16
342 #define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT)
343 #define S_LP_INT_THRESH 12
344 #define M_LP_INT_THRESH 0xfU
345 #define M_LP_INT_THRESH_T5 0xfffU
346 #define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH)
347 #define M_LP_COUNT 0x7ffU
349 #define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT)
350 #define A_SGE_DBFIFO_STATUS 0x10a4
352 #define SGE_STAT_TOTAL 0x10e4
353 #define SGE_STAT_MATCH 0x10e8
355 #define SGE_STAT_CFG 0x10ec
356 #define S_STATSOURCE_T5 9
357 #define STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5)
359 #define SGE_DBFIFO_STATUS2 0x1118
360 #define M_HP_COUNT_T5 0x3ffU
361 #define G_HP_COUNT_T5(x) ((x) & M_HP_COUNT_T5)
362 #define S_HP_INT_THRESH_T5 10
363 #define M_HP_INT_THRESH_T5 0xfU
364 #define V_HP_INT_THRESH_T5(x) ((x) << S_HP_INT_THRESH_T5)
366 #define S_ENABLE_DROP 13
367 #define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP)
368 #define F_ENABLE_DROP V_ENABLE_DROP(1U)
369 #define S_DROPPED_DB 0
370 #define V_DROPPED_DB(x) ((x) << S_DROPPED_DB)
371 #define F_DROPPED_DB V_DROPPED_DB(1U)
372 #define A_SGE_DOORBELL_CONTROL 0x10a8
374 #define A_SGE_CTXT_CMD 0x11fc
375 #define A_SGE_DBQ_CTXT_BADDR 0x1084
377 #define PCIE_PF_CFG 0x40
378 #define AIVEC(x) ((x) << 4)
379 #define AIVEC_MASK 0x3ffU
381 #define PCIE_PF_CLI 0x44
382 #define PCIE_INT_CAUSE 0x3004
383 #define UNXSPLCPLERR 0x20000000U
384 #define PCIEPINT 0x10000000U
385 #define PCIESINT 0x08000000U
386 #define RPLPERR 0x04000000U
387 #define RXWRPERR 0x02000000U
388 #define RXCPLPERR 0x01000000U
389 #define PIOTAGPERR 0x00800000U
390 #define MATAGPERR 0x00400000U
391 #define INTXCLRPERR 0x00200000U
392 #define FIDPERR 0x00100000U
393 #define CFGSNPPERR 0x00080000U
394 #define HRSPPERR 0x00040000U
395 #define HREQPERR 0x00020000U
396 #define HCNTPERR 0x00010000U
397 #define DRSPPERR 0x00008000U
398 #define DREQPERR 0x00004000U
399 #define DCNTPERR 0x00002000U
400 #define CRSPPERR 0x00001000U
401 #define CREQPERR 0x00000800U
402 #define CCNTPERR 0x00000400U
403 #define TARTAGPERR 0x00000200U
404 #define PIOREQPERR 0x00000100U
405 #define PIOCPLPERR 0x00000080U
406 #define MSIXDIPERR 0x00000040U
407 #define MSIXDATAPERR 0x00000020U
408 #define MSIXADDRHPERR 0x00000010U
409 #define MSIXADDRLPERR 0x00000008U
410 #define MSIDATAPERR 0x00000004U
411 #define MSIADDRHPERR 0x00000002U
412 #define MSIADDRLPERR 0x00000001U
414 #define READRSPERR 0x20000000U
415 #define TRGT1GRPPERR 0x10000000U
416 #define IPSOTPERR 0x08000000U
417 #define IPRXDATAGRPPERR 0x02000000U
418 #define IPRXHDRGRPPERR 0x01000000U
419 #define MAGRPPERR 0x00400000U
420 #define VFIDPERR 0x00200000U
421 #define HREQWRPERR 0x00010000U
422 #define DREQWRPERR 0x00002000U
423 #define MSTTAGQPERR 0x00000400U
424 #define PIOREQGRPPERR 0x00000100U
425 #define PIOCPLGRPPERR 0x00000080U
426 #define MSIXSTIPERR 0x00000004U
427 #define MSTTIMEOUTPERR 0x00000002U
428 #define MSTGRPPERR 0x00000001U
430 #define PCIE_NONFAT_ERR 0x3010
431 #define PCIE_CFG_SPACE_REQ 0x3060
432 #define PCIE_CFG_SPACE_DATA 0x3064
433 #define PCIE_MEM_ACCESS_BASE_WIN 0x3068
434 #define S_PCIEOFST 10
435 #define M_PCIEOFST 0x3fffffU
436 #define GET_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST)
437 #define PCIEOFST_MASK 0xfffffc00U
438 #define BIR_MASK 0x00000300U
440 #define BIR(x) ((x) << BIR_SHIFT)
441 #define WINDOW_MASK 0x000000ffU
442 #define WINDOW_SHIFT 0
443 #define WINDOW(x) ((x) << WINDOW_SHIFT)
444 #define GET_WINDOW(x) (((x) >> WINDOW_SHIFT) & WINDOW_MASK)
445 #define PCIE_MEM_ACCESS_OFFSET 0x306c
446 #define ENABLE (1U << 30)
447 #define FUNCTION(x) ((x) << 12)
448 #define F_LOCALCFG (1U << 28)
451 #define V_PFNUM(x) ((x) << S_PFNUM)
453 #define PCIE_FW 0x30b8
454 #define PCIE_FW_ERR 0x80000000U
455 #define PCIE_FW_INIT 0x40000000U
456 #define PCIE_FW_HALT 0x20000000U
457 #define PCIE_FW_MASTER_VLD 0x00008000U
458 #define PCIE_FW_MASTER(x) ((x) << 12)
459 #define PCIE_FW_MASTER_MASK 0x7
460 #define PCIE_FW_MASTER_GET(x) (((x) >> 12) & PCIE_FW_MASTER_MASK)
462 #define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908
463 #define RNPP 0x80000000U
464 #define RPCP 0x20000000U
465 #define RCIP 0x08000000U
466 #define RCCP 0x04000000U
467 #define RFTP 0x00800000U
468 #define PTRP 0x00100000U
470 #define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS 0x59a4
471 #define TPCP 0x40000000U
472 #define TNPP 0x20000000U
473 #define TFTP 0x10000000U
474 #define TCAP 0x08000000U
475 #define TCIP 0x04000000U
476 #define RCAP 0x02000000U
477 #define PLUP 0x00800000U
478 #define PLDN 0x00400000U
479 #define OTDD 0x00200000U
480 #define GTRP 0x00100000U
481 #define RDPE 0x00040000U
482 #define TDCE 0x00020000U
483 #define TDUE 0x00010000U
485 #define MC_INT_CAUSE 0x7518
486 #define MC_P_INT_CAUSE 0x41318
487 #define ECC_UE_INT_CAUSE 0x00000004U
488 #define ECC_CE_INT_CAUSE 0x00000002U
489 #define PERR_INT_CAUSE 0x00000001U
491 #define MC_ECC_STATUS 0x751c
492 #define MC_P_ECC_STATUS 0x4131c
493 #define ECC_CECNT_MASK 0xffff0000U
494 #define ECC_CECNT_SHIFT 16
495 #define ECC_CECNT(x) ((x) << ECC_CECNT_SHIFT)
496 #define ECC_CECNT_GET(x) (((x) & ECC_CECNT_MASK) >> ECC_CECNT_SHIFT)
497 #define ECC_UECNT_MASK 0x0000ffffU
498 #define ECC_UECNT_SHIFT 0
499 #define ECC_UECNT(x) ((x) << ECC_UECNT_SHIFT)
500 #define ECC_UECNT_GET(x) (((x) & ECC_UECNT_MASK) >> ECC_UECNT_SHIFT)
502 #define MC_BIST_CMD 0x7600
503 #define START_BIST 0x80000000U
504 #define BIST_CMD_GAP_MASK 0x0000ff00U
505 #define BIST_CMD_GAP_SHIFT 8
506 #define BIST_CMD_GAP(x) ((x) << BIST_CMD_GAP_SHIFT)
507 #define BIST_OPCODE_MASK 0x00000003U
508 #define BIST_OPCODE_SHIFT 0
509 #define BIST_OPCODE(x) ((x) << BIST_OPCODE_SHIFT)
511 #define MC_BIST_CMD_ADDR 0x7604
512 #define MC_BIST_CMD_LEN 0x7608
513 #define MC_BIST_DATA_PATTERN 0x760c
514 #define BIST_DATA_TYPE_MASK 0x0000000fU
515 #define BIST_DATA_TYPE_SHIFT 0
516 #define BIST_DATA_TYPE(x) ((x) << BIST_DATA_TYPE_SHIFT)
518 #define MC_BIST_STATUS_RDATA 0x7688
520 #define MA_EDRAM0_BAR_A 0x77c0
522 #define EDRAM0_SIZE_S 0
523 #define EDRAM0_SIZE_M 0xfffU
524 #define EDRAM0_SIZE_V(x) ((x) << EDRAM0_SIZE_S)
525 #define EDRAM0_SIZE_G(x) (((x) >> EDRAM0_SIZE_S) & EDRAM0_SIZE_M)
527 #define MA_EDRAM1_BAR_A 0x77c4
529 #define EDRAM1_SIZE_S 0
530 #define EDRAM1_SIZE_M 0xfffU
531 #define EDRAM1_SIZE_V(x) ((x) << EDRAM1_SIZE_S)
532 #define EDRAM1_SIZE_G(x) (((x) >> EDRAM1_SIZE_S) & EDRAM1_SIZE_M)
534 #define MA_EXT_MEMORY_BAR_A 0x77c8
536 #define EXT_MEM_SIZE_S 0
537 #define EXT_MEM_SIZE_M 0xfffU
538 #define EXT_MEM_SIZE_V(x) ((x) << EXT_MEM_SIZE_S)
539 #define EXT_MEM_SIZE_G(x) (((x) >> EXT_MEM_SIZE_S) & EXT_MEM_SIZE_M)
541 #define MA_EXT_MEMORY1_BAR_A 0x7808
543 #define EXT_MEM1_SIZE_S 0
544 #define EXT_MEM1_SIZE_M 0xfffU
545 #define EXT_MEM1_SIZE_V(x) ((x) << EXT_MEM1_SIZE_S)
546 #define EXT_MEM1_SIZE_G(x) (((x) >> EXT_MEM1_SIZE_S) & EXT_MEM1_SIZE_M)
548 #define MA_EXT_MEMORY0_BAR_A 0x77c8
550 #define EXT_MEM0_SIZE_S 0
551 #define EXT_MEM0_SIZE_M 0xfffU
552 #define EXT_MEM0_SIZE_V(x) ((x) << EXT_MEM0_SIZE_S)
553 #define EXT_MEM0_SIZE_G(x) (((x) >> EXT_MEM0_SIZE_S) & EXT_MEM0_SIZE_M)
555 #define MA_TARGET_MEM_ENABLE_A 0x77d8
557 #define EXT_MEM_ENABLE_S 2
558 #define EXT_MEM_ENABLE_V(x) ((x) << EXT_MEM_ENABLE_S)
559 #define EXT_MEM_ENABLE_F EXT_MEM_ENABLE_V(1U)
561 #define EDRAM1_ENABLE_S 1
562 #define EDRAM1_ENABLE_V(x) ((x) << EDRAM1_ENABLE_S)
563 #define EDRAM1_ENABLE_F EDRAM1_ENABLE_V(1U)
565 #define EDRAM0_ENABLE_S 0
566 #define EDRAM0_ENABLE_V(x) ((x) << EDRAM0_ENABLE_S)
567 #define EDRAM0_ENABLE_F EDRAM0_ENABLE_V(1U)
569 #define EXT_MEM1_ENABLE_S 4
570 #define EXT_MEM1_ENABLE_V(x) ((x) << EXT_MEM1_ENABLE_S)
571 #define EXT_MEM1_ENABLE_F EXT_MEM1_ENABLE_V(1U)
573 #define EXT_MEM0_ENABLE_S 2
574 #define EXT_MEM0_ENABLE_V(x) ((x) << EXT_MEM0_ENABLE_S)
575 #define EXT_MEM0_ENABLE_F EXT_MEM0_ENABLE_V(1U)
577 #define MA_INT_CAUSE 0x77e0
578 #define MEM_PERR_INT_CAUSE 0x00000002U
579 #define MEM_WRAP_INT_CAUSE 0x00000001U
581 #define MA_INT_WRAP_STATUS 0x77e4
582 #define MEM_WRAP_ADDRESS_MASK 0xfffffff0U
583 #define MEM_WRAP_ADDRESS_SHIFT 4
584 #define MEM_WRAP_ADDRESS_GET(x) (((x) & MEM_WRAP_ADDRESS_MASK) >> MEM_WRAP_ADDRESS_SHIFT)
585 #define MEM_WRAP_CLIENT_NUM_MASK 0x0000000fU
586 #define MEM_WRAP_CLIENT_NUM_SHIFT 0
587 #define MEM_WRAP_CLIENT_NUM_GET(x) (((x) & MEM_WRAP_CLIENT_NUM_MASK) >> MEM_WRAP_CLIENT_NUM_SHIFT)
588 #define MA_PCIE_FW 0x30b8
589 #define MA_PARITY_ERROR_STATUS 0x77f4
590 #define MA_PARITY_ERROR_STATUS2 0x7804
592 #define EDC_0_BASE_ADDR 0x7900
594 #define EDC_BIST_CMD 0x7904
595 #define EDC_BIST_CMD_ADDR 0x7908
596 #define EDC_BIST_CMD_LEN 0x790c
597 #define EDC_BIST_DATA_PATTERN 0x7910
598 #define EDC_BIST_STATUS_RDATA 0x7928
599 #define EDC_INT_CAUSE 0x7978
600 #define ECC_UE_PAR 0x00000020U
601 #define ECC_CE_PAR 0x00000010U
602 #define PERR_PAR_CAUSE 0x00000008U
604 #define EDC_ECC_STATUS 0x797c
606 #define EDC_1_BASE_ADDR 0x7980
608 #define CIM_BOOT_CFG 0x7b00
609 #define BOOTADDR_MASK 0xffffff00U
612 #define CIM_PF_MAILBOX_DATA 0x240
613 #define CIM_PF_MAILBOX_CTRL 0x280
614 #define MBMSGVALID 0x00000008U
615 #define MBINTREQ 0x00000004U
616 #define MBOWNER_MASK 0x00000003U
617 #define MBOWNER_SHIFT 0
618 #define MBOWNER(x) ((x) << MBOWNER_SHIFT)
619 #define MBOWNER_GET(x) (((x) & MBOWNER_MASK) >> MBOWNER_SHIFT)
621 #define CIM_PF_HOST_INT_ENABLE 0x288
622 #define MBMSGRDYINTEN(x) ((x) << 19)
624 #define CIM_PF_HOST_INT_CAUSE 0x28c
625 #define MBMSGRDYINT 0x00080000U
627 #define CIM_HOST_INT_CAUSE 0x7b2c
628 #define TIEQOUTPARERRINT 0x00100000U
629 #define TIEQINPARERRINT 0x00080000U
630 #define MBHOSTPARERR 0x00040000U
631 #define MBUPPARERR 0x00020000U
632 #define IBQPARERR 0x0001f800U
633 #define IBQTP0PARERR 0x00010000U
634 #define IBQTP1PARERR 0x00008000U
635 #define IBQULPPARERR 0x00004000U
636 #define IBQSGELOPARERR 0x00002000U
637 #define IBQSGEHIPARERR 0x00001000U
638 #define IBQNCSIPARERR 0x00000800U
639 #define OBQPARERR 0x000007e0U
640 #define OBQULP0PARERR 0x00000400U
641 #define OBQULP1PARERR 0x00000200U
642 #define OBQULP2PARERR 0x00000100U
643 #define OBQULP3PARERR 0x00000080U
644 #define OBQSGEPARERR 0x00000040U
645 #define OBQNCSIPARERR 0x00000020U
646 #define PREFDROPINT 0x00000002U
647 #define UPACCNONZERO 0x00000001U
649 #define CIM_HOST_UPACC_INT_CAUSE 0x7b34
650 #define EEPROMWRINT 0x40000000U
651 #define TIMEOUTMAINT 0x20000000U
652 #define TIMEOUTINT 0x10000000U
653 #define RSPOVRLOOKUPINT 0x08000000U
654 #define REQOVRLOOKUPINT 0x04000000U
655 #define BLKWRPLINT 0x02000000U
656 #define BLKRDPLINT 0x01000000U
657 #define SGLWRPLINT 0x00800000U
658 #define SGLRDPLINT 0x00400000U
659 #define BLKWRCTLINT 0x00200000U
660 #define BLKRDCTLINT 0x00100000U
661 #define SGLWRCTLINT 0x00080000U
662 #define SGLRDCTLINT 0x00040000U
663 #define BLKWREEPROMINT 0x00020000U
664 #define BLKRDEEPROMINT 0x00010000U
665 #define SGLWREEPROMINT 0x00008000U
666 #define SGLRDEEPROMINT 0x00004000U
667 #define BLKWRFLASHINT 0x00002000U
668 #define BLKRDFLASHINT 0x00001000U
669 #define SGLWRFLASHINT 0x00000800U
670 #define SGLRDFLASHINT 0x00000400U
671 #define BLKWRBOOTINT 0x00000200U
672 #define BLKRDBOOTINT 0x00000100U
673 #define SGLWRBOOTINT 0x00000080U
674 #define SGLRDBOOTINT 0x00000040U
675 #define ILLWRBEINT 0x00000020U
676 #define ILLRDBEINT 0x00000010U
677 #define ILLRDINT 0x00000008U
678 #define ILLWRINT 0x00000004U
679 #define ILLTRANSINT 0x00000002U
680 #define RSVDSPACEINT 0x00000001U
682 #define TP_OUT_CONFIG 0x7d04
683 #define VLANEXTENABLE_MASK 0x0000f000U
684 #define VLANEXTENABLE_SHIFT 12
686 #define TP_GLOBAL_CONFIG 0x7d08
687 #define FIVETUPLELOOKUP_SHIFT 17
688 #define FIVETUPLELOOKUP_MASK 0x00060000U
689 #define FIVETUPLELOOKUP(x) ((x) << FIVETUPLELOOKUP_SHIFT)
690 #define FIVETUPLELOOKUP_GET(x) (((x) & FIVETUPLELOOKUP_MASK) >> \
691 FIVETUPLELOOKUP_SHIFT)
693 #define TP_PARA_REG2 0x7d68
694 #define MAXRXDATA_MASK 0xffff0000U
695 #define MAXRXDATA_SHIFT 16
696 #define MAXRXDATA_GET(x) (((x) & MAXRXDATA_MASK) >> MAXRXDATA_SHIFT)
698 #define TP_TIMER_RESOLUTION 0x7d90
699 #define TIMERRESOLUTION_MASK 0x00ff0000U
700 #define TIMERRESOLUTION_SHIFT 16
701 #define TIMERRESOLUTION_GET(x) (((x) & TIMERRESOLUTION_MASK) >> TIMERRESOLUTION_SHIFT)
702 #define DELAYEDACKRESOLUTION_MASK 0x000000ffU
703 #define DELAYEDACKRESOLUTION_SHIFT 0
704 #define DELAYEDACKRESOLUTION_GET(x) \
705 (((x) & DELAYEDACKRESOLUTION_MASK) >> DELAYEDACKRESOLUTION_SHIFT)
707 #define TP_SHIFT_CNT 0x7dc0
708 #define SYNSHIFTMAX_SHIFT 24
709 #define SYNSHIFTMAX_MASK 0xff000000U
710 #define SYNSHIFTMAX(x) ((x) << SYNSHIFTMAX_SHIFT)
711 #define SYNSHIFTMAX_GET(x) (((x) & SYNSHIFTMAX_MASK) >> \
713 #define RXTSHIFTMAXR1_SHIFT 20
714 #define RXTSHIFTMAXR1_MASK 0x00f00000U
715 #define RXTSHIFTMAXR1(x) ((x) << RXTSHIFTMAXR1_SHIFT)
716 #define RXTSHIFTMAXR1_GET(x) (((x) & RXTSHIFTMAXR1_MASK) >> \
718 #define RXTSHIFTMAXR2_SHIFT 16
719 #define RXTSHIFTMAXR2_MASK 0x000f0000U
720 #define RXTSHIFTMAXR2(x) ((x) << RXTSHIFTMAXR2_SHIFT)
721 #define RXTSHIFTMAXR2_GET(x) (((x) & RXTSHIFTMAXR2_MASK) >> \
723 #define PERSHIFTBACKOFFMAX_SHIFT 12
724 #define PERSHIFTBACKOFFMAX_MASK 0x0000f000U
725 #define PERSHIFTBACKOFFMAX(x) ((x) << PERSHIFTBACKOFFMAX_SHIFT)
726 #define PERSHIFTBACKOFFMAX_GET(x) (((x) & PERSHIFTBACKOFFMAX_MASK) >> \
727 PERSHIFTBACKOFFMAX_SHIFT)
728 #define PERSHIFTMAX_SHIFT 8
729 #define PERSHIFTMAX_MASK 0x00000f00U
730 #define PERSHIFTMAX(x) ((x) << PERSHIFTMAX_SHIFT)
731 #define PERSHIFTMAX_GET(x) (((x) & PERSHIFTMAX_MASK) >> \
733 #define KEEPALIVEMAXR1_SHIFT 4
734 #define KEEPALIVEMAXR1_MASK 0x000000f0U
735 #define KEEPALIVEMAXR1(x) ((x) << KEEPALIVEMAXR1_SHIFT)
736 #define KEEPALIVEMAXR1_GET(x) (((x) & KEEPALIVEMAXR1_MASK) >> \
737 KEEPALIVEMAXR1_SHIFT)
738 #define KEEPALIVEMAXR2_SHIFT 0
739 #define KEEPALIVEMAXR2_MASK 0x0000000fU
740 #define KEEPALIVEMAXR2(x) ((x) << KEEPALIVEMAXR2_SHIFT)
741 #define KEEPALIVEMAXR2_GET(x) (((x) & KEEPALIVEMAXR2_MASK) >> \
742 KEEPALIVEMAXR2_SHIFT)
744 #define TP_CCTRL_TABLE 0x7ddc
745 #define TP_MTU_TABLE 0x7de4
746 #define MTUINDEX_MASK 0xff000000U
747 #define MTUINDEX_SHIFT 24
748 #define MTUINDEX(x) ((x) << MTUINDEX_SHIFT)
749 #define MTUWIDTH_MASK 0x000f0000U
750 #define MTUWIDTH_SHIFT 16
751 #define MTUWIDTH(x) ((x) << MTUWIDTH_SHIFT)
752 #define MTUWIDTH_GET(x) (((x) & MTUWIDTH_MASK) >> MTUWIDTH_SHIFT)
753 #define MTUVALUE_MASK 0x00003fffU
754 #define MTUVALUE_SHIFT 0
755 #define MTUVALUE(x) ((x) << MTUVALUE_SHIFT)
756 #define MTUVALUE_GET(x) (((x) & MTUVALUE_MASK) >> MTUVALUE_SHIFT)
758 #define TP_RSS_LKP_TABLE 0x7dec
759 #define LKPTBLROWVLD 0x80000000U
760 #define LKPTBLQUEUE1_MASK 0x000ffc00U
761 #define LKPTBLQUEUE1_SHIFT 10
762 #define LKPTBLQUEUE1(x) ((x) << LKPTBLQUEUE1_SHIFT)
763 #define LKPTBLQUEUE1_GET(x) (((x) & LKPTBLQUEUE1_MASK) >> LKPTBLQUEUE1_SHIFT)
764 #define LKPTBLQUEUE0_MASK 0x000003ffU
765 #define LKPTBLQUEUE0_SHIFT 0
766 #define LKPTBLQUEUE0(x) ((x) << LKPTBLQUEUE0_SHIFT)
767 #define LKPTBLQUEUE0_GET(x) (((x) & LKPTBLQUEUE0_MASK) >> LKPTBLQUEUE0_SHIFT)
769 #define TP_PIO_ADDR 0x7e40
770 #define TP_PIO_DATA 0x7e44
771 #define TP_MIB_INDEX 0x7e50
772 #define TP_MIB_DATA 0x7e54
773 #define TP_INT_CAUSE 0x7e74
774 #define FLMTXFLSTEMPTY 0x40000000U
776 #define TP_VLAN_PRI_MAP 0x140
777 #define FRAGMENTATION_SHIFT 9
778 #define FRAGMENTATION_MASK 0x00000200U
779 #define MPSHITTYPE_MASK 0x00000100U
780 #define MACMATCH_MASK 0x00000080U
781 #define ETHERTYPE_MASK 0x00000040U
782 #define PROTOCOL_MASK 0x00000020U
783 #define TOS_MASK 0x00000010U
784 #define VLAN_MASK 0x00000008U
785 #define VNIC_ID_MASK 0x00000004U
786 #define PORT_MASK 0x00000002U
788 #define FCOE_MASK 0x00000001U
790 #define TP_INGRESS_CONFIG 0x141
791 #define VNIC 0x00000800U
792 #define CSUM_HAS_PSEUDO_HDR 0x00000400U
793 #define RM_OVLAN 0x00000200U
794 #define LOOKUPEVERYPKT 0x00000100U
796 #define TP_MIB_MAC_IN_ERR_0 0x0
797 #define TP_MIB_TCP_OUT_RST 0xc
798 #define TP_MIB_TCP_IN_SEG_HI 0x10
799 #define TP_MIB_TCP_IN_SEG_LO 0x11
800 #define TP_MIB_TCP_OUT_SEG_HI 0x12
801 #define TP_MIB_TCP_OUT_SEG_LO 0x13
802 #define TP_MIB_TCP_RXT_SEG_HI 0x14
803 #define TP_MIB_TCP_RXT_SEG_LO 0x15
804 #define TP_MIB_TNL_CNG_DROP_0 0x18
805 #define TP_MIB_TCP_V6IN_ERR_0 0x28
806 #define TP_MIB_TCP_V6OUT_RST 0x2c
807 #define TP_MIB_OFD_ARP_DROP 0x36
808 #define TP_MIB_TNL_DROP_0 0x44
809 #define TP_MIB_OFD_VLN_DROP_0 0x58
811 #define ULP_TX_INT_CAUSE 0x8dcc
812 #define PBL_BOUND_ERR_CH3 0x80000000U
813 #define PBL_BOUND_ERR_CH2 0x40000000U
814 #define PBL_BOUND_ERR_CH1 0x20000000U
815 #define PBL_BOUND_ERR_CH0 0x10000000U
817 #define PM_RX_INT_CAUSE 0x8fdc
818 #define ZERO_E_CMD_ERROR 0x00400000U
819 #define PMRX_FRAMING_ERROR 0x003ffff0U
820 #define OCSPI_PAR_ERROR 0x00000008U
821 #define DB_OPTIONS_PAR_ERROR 0x00000004U
822 #define IESPI_PAR_ERROR 0x00000002U
823 #define E_PCMD_PAR_ERROR 0x00000001U
825 #define PM_TX_INT_CAUSE 0x8ffc
826 #define PCMD_LEN_OVFL0 0x80000000U
827 #define PCMD_LEN_OVFL1 0x40000000U
828 #define PCMD_LEN_OVFL2 0x20000000U
829 #define ZERO_C_CMD_ERROR 0x10000000U
830 #define PMTX_FRAMING_ERROR 0x0ffffff0U
831 #define OESPI_PAR_ERROR 0x00000008U
832 #define ICSPI_PAR_ERROR 0x00000002U
833 #define C_PCMD_PAR_ERROR 0x00000001U
835 #define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
836 #define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
837 #define MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
838 #define MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
839 #define MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
840 #define MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
841 #define MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
842 #define MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
843 #define MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
844 #define MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
845 #define MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
846 #define MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
847 #define MPS_PORT_STAT_TX_PORT_64B_L 0x430
848 #define MPS_PORT_STAT_TX_PORT_64B_H 0x434
849 #define MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
850 #define MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
851 #define MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
852 #define MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
853 #define MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
854 #define MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
855 #define MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
856 #define MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
857 #define MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
858 #define MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
859 #define MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
860 #define MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
861 #define MPS_PORT_STAT_TX_PORT_DROP_L 0x468
862 #define MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
863 #define MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
864 #define MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
865 #define MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
866 #define MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
867 #define MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
868 #define MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
869 #define MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
870 #define MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
871 #define MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
872 #define MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
873 #define MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
874 #define MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
875 #define MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
876 #define MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
877 #define MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
878 #define MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
879 #define MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
880 #define MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
881 #define MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
882 #define MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
883 #define MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
884 #define MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
885 #define MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
886 #define MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
887 #define MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
888 #define MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
889 #define MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
890 #define MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
891 #define MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
892 #define MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
893 #define MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
894 #define MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
895 #define MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
896 #define MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
897 #define MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
898 #define MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
899 #define MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
900 #define MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
901 #define MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
902 #define MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
903 #define MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
904 #define MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
905 #define MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
906 #define MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
907 #define MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
908 #define MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
909 #define MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
910 #define MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
911 #define MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
912 #define MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
913 #define MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
914 #define MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
915 #define MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
916 #define MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
917 #define MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
918 #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
919 #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
920 #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
921 #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
922 #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
923 #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
924 #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
925 #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
926 #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
927 #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
928 #define MPS_PORT_STAT_RX_PORT_64B_L 0x590
929 #define MPS_PORT_STAT_RX_PORT_64B_H 0x594
930 #define MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
931 #define MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
932 #define MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
933 #define MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
934 #define MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
935 #define MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
936 #define MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
937 #define MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
938 #define MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
939 #define MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
940 #define MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
941 #define MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
942 #define MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
943 #define MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
944 #define MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
945 #define MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
946 #define MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
947 #define MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
948 #define MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
949 #define MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
950 #define MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
951 #define MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
952 #define MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
953 #define MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
954 #define MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
955 #define MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
956 #define MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
957 #define MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
958 #define MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
959 #define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
960 #define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
961 #define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
962 #define MAC_PORT_CFG2 0x818
963 #define MAC_PORT_MAGIC_MACID_LO 0x824
964 #define MAC_PORT_MAGIC_MACID_HI 0x828
965 #define MAC_PORT_EPIO_DATA0 0x8c0
966 #define MAC_PORT_EPIO_DATA1 0x8c4
967 #define MAC_PORT_EPIO_DATA2 0x8c8
968 #define MAC_PORT_EPIO_DATA3 0x8cc
969 #define MAC_PORT_EPIO_OP 0x8d0
971 #define MPS_CMN_CTL 0x9000
972 #define NUMPORTS_MASK 0x00000003U
973 #define NUMPORTS_SHIFT 0
974 #define NUMPORTS_GET(x) (((x) & NUMPORTS_MASK) >> NUMPORTS_SHIFT)
976 #define MPS_INT_CAUSE 0x9008
977 #define STATINT 0x00000020U
978 #define TXINT 0x00000010U
979 #define RXINT 0x00000008U
980 #define TRCINT 0x00000004U
981 #define CLSINT 0x00000002U
982 #define PLINT 0x00000001U
984 #define MPS_TX_INT_CAUSE 0x9408
985 #define PORTERR 0x00010000U
986 #define FRMERR 0x00008000U
987 #define SECNTERR 0x00004000U
988 #define BUBBLE 0x00002000U
989 #define TXDESCFIFO 0x00001e00U
990 #define TXDATAFIFO 0x000001e0U
991 #define NCSIFIFO 0x00000010U
992 #define TPFIFO 0x0000000fU
994 #define MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614
995 #define MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620
996 #define MPS_STAT_PERR_INT_CAUSE_RX_FIFO 0x962c
998 #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
999 #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
1000 #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
1001 #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
1002 #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
1003 #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
1004 #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
1005 #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
1006 #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
1007 #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
1008 #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
1009 #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
1010 #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
1011 #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
1012 #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
1013 #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
1014 #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
1015 #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
1016 #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
1017 #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
1018 #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
1019 #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
1020 #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
1021 #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
1022 #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
1023 #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
1024 #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
1025 #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
1026 #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
1027 #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
1028 #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
1029 #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
1030 #define MPS_TRC_CFG 0x9800
1031 #define TRCFIFOEMPTY 0x00000010U
1032 #define TRCIGNOREDROPINPUT 0x00000008U
1033 #define TRCKEEPDUPLICATES 0x00000004U
1034 #define TRCEN 0x00000002U
1035 #define TRCMULTIFILTER 0x00000001U
1037 #define MPS_TRC_RSS_CONTROL 0x9808
1038 #define MPS_T5_TRC_RSS_CONTROL 0xa00c
1039 #define RSSCONTROL_MASK 0x00ff0000U
1040 #define RSSCONTROL_SHIFT 16
1041 #define RSSCONTROL(x) ((x) << RSSCONTROL_SHIFT)
1042 #define QUEUENUMBER_MASK 0x0000ffffU
1043 #define QUEUENUMBER_SHIFT 0
1044 #define QUEUENUMBER(x) ((x) << QUEUENUMBER_SHIFT)
1046 #define MPS_TRC_FILTER_MATCH_CTL_A 0x9810
1047 #define TFINVERTMATCH 0x01000000U
1048 #define TFPKTTOOLARGE 0x00800000U
1049 #define TFEN 0x00400000U
1050 #define TFPORT_MASK 0x003c0000U
1051 #define TFPORT_SHIFT 18
1052 #define TFPORT(x) ((x) << TFPORT_SHIFT)
1053 #define TFPORT_GET(x) (((x) & TFPORT_MASK) >> TFPORT_SHIFT)
1054 #define TFDROP 0x00020000U
1055 #define TFSOPEOPERR 0x00010000U
1056 #define TFLENGTH_MASK 0x00001f00U
1057 #define TFLENGTH_SHIFT 8
1058 #define TFLENGTH(x) ((x) << TFLENGTH_SHIFT)
1059 #define TFLENGTH_GET(x) (((x) & TFLENGTH_MASK) >> TFLENGTH_SHIFT)
1060 #define TFOFFSET_MASK 0x0000001fU
1061 #define TFOFFSET_SHIFT 0
1062 #define TFOFFSET(x) ((x) << TFOFFSET_SHIFT)
1063 #define TFOFFSET_GET(x) (((x) & TFOFFSET_MASK) >> TFOFFSET_SHIFT)
1065 #define MPS_TRC_FILTER_MATCH_CTL_B 0x9820
1066 #define TFMINPKTSIZE_MASK 0x01ff0000U
1067 #define TFMINPKTSIZE_SHIFT 16
1068 #define TFMINPKTSIZE(x) ((x) << TFMINPKTSIZE_SHIFT)
1069 #define TFMINPKTSIZE_GET(x) (((x) & TFMINPKTSIZE_MASK) >> TFMINPKTSIZE_SHIFT)
1070 #define TFCAPTUREMAX_MASK 0x00003fffU
1071 #define TFCAPTUREMAX_SHIFT 0
1072 #define TFCAPTUREMAX(x) ((x) << TFCAPTUREMAX_SHIFT)
1073 #define TFCAPTUREMAX_GET(x) (((x) & TFCAPTUREMAX_MASK) >> TFCAPTUREMAX_SHIFT)
1075 #define MPS_TRC_INT_CAUSE 0x985c
1076 #define MISCPERR 0x00000100U
1077 #define PKTFIFO 0x000000f0U
1078 #define FILTMEM 0x0000000fU
1080 #define MPS_TRC_FILTER0_MATCH 0x9c00
1081 #define MPS_TRC_FILTER0_DONT_CARE 0x9c80
1082 #define MPS_TRC_FILTER1_MATCH 0x9d00
1083 #define MPS_CLS_INT_CAUSE 0xd028
1084 #define PLERRENB 0x00000008U
1085 #define HASHSRAM 0x00000004U
1086 #define MATCHTCAM 0x00000002U
1087 #define MATCHSRAM 0x00000001U
1089 #define MPS_RX_PERR_INT_CAUSE 0x11074
1091 #define CPL_INTR_CAUSE 0x19054
1092 #define CIM_OP_MAP_PERR 0x00000020U
1093 #define CIM_OVFL_ERROR 0x00000010U
1094 #define TP_FRAMING_ERROR 0x00000008U
1095 #define SGE_FRAMING_ERROR 0x00000004U
1096 #define CIM_FRAMING_ERROR 0x00000002U
1097 #define ZERO_SWITCH_ERROR 0x00000001U
1099 #define SMB_INT_CAUSE 0x19090
1100 #define MSTTXFIFOPARINT 0x00200000U
1101 #define MSTRXFIFOPARINT 0x00100000U
1102 #define SLVFIFOPARINT 0x00080000U
1104 #define ULP_RX_INT_CAUSE 0x19158
1105 #define ULP_RX_ISCSI_TAGMASK 0x19164
1106 #define ULP_RX_ISCSI_PSZ 0x19168
1107 #define HPZ3_MASK 0x0f000000U
1108 #define HPZ3_SHIFT 24
1109 #define HPZ3(x) ((x) << HPZ3_SHIFT)
1110 #define HPZ2_MASK 0x000f0000U
1111 #define HPZ2_SHIFT 16
1112 #define HPZ2(x) ((x) << HPZ2_SHIFT)
1113 #define HPZ1_MASK 0x00000f00U
1114 #define HPZ1_SHIFT 8
1115 #define HPZ1(x) ((x) << HPZ1_SHIFT)
1116 #define HPZ0_MASK 0x0000000fU
1117 #define HPZ0_SHIFT 0
1118 #define HPZ0(x) ((x) << HPZ0_SHIFT)
1120 #define ULP_RX_TDDP_PSZ 0x19178
1122 #define SF_DATA 0x193f8
1123 #define SF_OP 0x193fc
1124 #define SF_BUSY 0x80000000U
1125 #define SF_LOCK 0x00000010U
1126 #define SF_CONT 0x00000008U
1127 #define BYTECNT_MASK 0x00000006U
1128 #define BYTECNT_SHIFT 1
1129 #define BYTECNT(x) ((x) << BYTECNT_SHIFT)
1130 #define OP_WR 0x00000001U
1132 #define PL_PF_INT_CAUSE 0x3c0
1133 #define PFSW 0x00000008U
1134 #define PFSGE 0x00000004U
1135 #define PFCIM 0x00000002U
1136 #define PFMPS 0x00000001U
1138 #define PL_PF_INT_ENABLE 0x3c4
1139 #define PL_PF_CTL 0x3c8
1140 #define SWINT 0x00000001U
1142 #define PL_WHOAMI 0x19400
1143 #define SOURCEPF_MASK 0x00000700U
1144 #define SOURCEPF_SHIFT 8
1145 #define SOURCEPF(x) ((x) << SOURCEPF_SHIFT)
1146 #define SOURCEPF_GET(x) (((x) & SOURCEPF_MASK) >> SOURCEPF_SHIFT)
1147 #define ISVF 0x00000080U
1148 #define VFID_MASK 0x0000007fU
1149 #define VFID_SHIFT 0
1150 #define VFID(x) ((x) << VFID_SHIFT)
1151 #define VFID_GET(x) (((x) & VFID_MASK) >> VFID_SHIFT)
1153 #define PL_INT_CAUSE 0x1940c
1154 #define ULP_TX 0x08000000U
1155 #define SGE 0x04000000U
1156 #define HMA 0x02000000U
1157 #define CPL_SWITCH 0x01000000U
1158 #define ULP_RX 0x00800000U
1159 #define PM_RX 0x00400000U
1160 #define PM_TX 0x00200000U
1161 #define MA 0x00100000U
1162 #define TP 0x00080000U
1163 #define LE 0x00040000U
1164 #define EDC1 0x00020000U
1165 #define EDC0 0x00010000U
1166 #define MC 0x00008000U
1167 #define PCIE 0x00004000U
1168 #define PMU 0x00002000U
1169 #define XGMAC_KR1 0x00001000U
1170 #define XGMAC_KR0 0x00000800U
1171 #define XGMAC1 0x00000400U
1172 #define XGMAC0 0x00000200U
1173 #define SMB 0x00000100U
1174 #define SF 0x00000080U
1175 #define PL 0x00000040U
1176 #define NCSI 0x00000020U
1177 #define MPS 0x00000010U
1178 #define MI 0x00000008U
1179 #define DBG 0x00000004U
1180 #define I2CM 0x00000002U
1181 #define CIM 0x00000001U
1184 #define PL_INT_ENABLE 0x19410
1185 #define PL_INT_MAP0 0x19414
1186 #define PL_RST 0x19428
1187 #define PIORST 0x00000002U
1188 #define PIORSTMODE 0x00000001U
1190 #define PL_PL_INT_CAUSE 0x19430
1191 #define FATALPERR 0x00000010U
1192 #define PERRVFID 0x00000001U
1194 #define PL_REV 0x1943c
1198 #define V_REV(x) ((x) << S_REV)
1199 #define G_REV(x) (((x) >> S_REV) & M_REV)
1201 #define LE_DB_CONFIG 0x19c04
1202 #define HASHEN 0x00100000U
1204 #define LE_DB_SERVER_INDEX 0x19c18
1205 #define LE_DB_ACT_CNT_IPV4 0x19c20
1206 #define LE_DB_ACT_CNT_IPV6 0x19c24
1208 #define LE_DB_INT_CAUSE 0x19c3c
1209 #define REQQPARERR 0x00010000U
1210 #define UNKNOWNCMD 0x00008000U
1211 #define PARITYERR 0x00000040U
1212 #define LIPMISS 0x00000020U
1213 #define LIP0 0x00000010U
1215 #define LE_DB_TID_HASHBASE 0x19df8
1217 #define NCSI_INT_CAUSE 0x1a0d8
1218 #define CIM_DM_PRTY_ERR 0x00000100U
1219 #define MPS_DM_PRTY_ERR 0x00000080U
1220 #define TXFIFO_PRTY_ERR 0x00000002U
1221 #define RXFIFO_PRTY_ERR 0x00000001U
1223 #define XGMAC_PORT_CFG2 0x1018
1224 #define PATEN 0x00040000U
1225 #define MAGICEN 0x00020000U
1227 #define XGMAC_PORT_MAGIC_MACID_LO 0x1024
1228 #define XGMAC_PORT_MAGIC_MACID_HI 0x1028
1230 #define XGMAC_PORT_EPIO_DATA0 0x10c0
1231 #define XGMAC_PORT_EPIO_DATA1 0x10c4
1232 #define XGMAC_PORT_EPIO_DATA2 0x10c8
1233 #define XGMAC_PORT_EPIO_DATA3 0x10cc
1234 #define XGMAC_PORT_EPIO_OP 0x10d0
1235 #define EPIOWR 0x00000100U
1236 #define ADDRESS_MASK 0x000000ffU
1237 #define ADDRESS_SHIFT 0
1238 #define ADDRESS(x) ((x) << ADDRESS_SHIFT)
1240 #define MAC_PORT_INT_CAUSE 0x8dc
1241 #define XGMAC_PORT_INT_CAUSE 0x10dc
1243 #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x7e28
1245 #define A_TP_TX_MOD_CHANNEL_WEIGHT 0x7e34
1247 #define S_TX_MOD_QUEUE_REQ_MAP 0
1248 #define M_TX_MOD_QUEUE_REQ_MAP 0xffffU
1249 #define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP)
1251 #define A_TP_TX_MOD_QUEUE_WEIGHT0 0x7e30
1253 #define S_TX_MODQ_WEIGHT3 24
1254 #define M_TX_MODQ_WEIGHT3 0xffU
1255 #define V_TX_MODQ_WEIGHT3(x) ((x) << S_TX_MODQ_WEIGHT3)
1257 #define S_TX_MODQ_WEIGHT2 16
1258 #define M_TX_MODQ_WEIGHT2 0xffU
1259 #define V_TX_MODQ_WEIGHT2(x) ((x) << S_TX_MODQ_WEIGHT2)
1261 #define S_TX_MODQ_WEIGHT1 8
1262 #define M_TX_MODQ_WEIGHT1 0xffU
1263 #define V_TX_MODQ_WEIGHT1(x) ((x) << S_TX_MODQ_WEIGHT1)
1265 #define S_TX_MODQ_WEIGHT0 0
1266 #define M_TX_MODQ_WEIGHT0 0xffU
1267 #define V_TX_MODQ_WEIGHT0(x) ((x) << S_TX_MODQ_WEIGHT0)
1269 #define A_TP_TX_SCHED_HDR 0x23
1271 #define A_TP_TX_SCHED_FIFO 0x24
1273 #define A_TP_TX_SCHED_PCMD 0x25
1276 #define V_VNIC(x) ((x) << S_VNIC)
1277 #define F_VNIC V_VNIC(1U)
1279 #define S_FRAGMENTATION 9
1280 #define V_FRAGMENTATION(x) ((x) << S_FRAGMENTATION)
1281 #define F_FRAGMENTATION V_FRAGMENTATION(1U)
1283 #define S_MPSHITTYPE 8
1284 #define V_MPSHITTYPE(x) ((x) << S_MPSHITTYPE)
1285 #define F_MPSHITTYPE V_MPSHITTYPE(1U)
1287 #define S_MACMATCH 7
1288 #define V_MACMATCH(x) ((x) << S_MACMATCH)
1289 #define F_MACMATCH V_MACMATCH(1U)
1291 #define S_ETHERTYPE 6
1292 #define V_ETHERTYPE(x) ((x) << S_ETHERTYPE)
1293 #define F_ETHERTYPE V_ETHERTYPE(1U)
1295 #define S_PROTOCOL 5
1296 #define V_PROTOCOL(x) ((x) << S_PROTOCOL)
1297 #define F_PROTOCOL V_PROTOCOL(1U)
1300 #define V_TOS(x) ((x) << S_TOS)
1301 #define F_TOS V_TOS(1U)
1304 #define V_VLAN(x) ((x) << S_VLAN)
1305 #define F_VLAN V_VLAN(1U)
1308 #define V_VNIC_ID(x) ((x) << S_VNIC_ID)
1309 #define F_VNIC_ID V_VNIC_ID(1U)
1312 #define V_PORT(x) ((x) << S_PORT)
1313 #define F_PORT V_PORT(1U)
1316 #define V_FCOE(x) ((x) << S_FCOE)
1317 #define F_FCOE V_FCOE(1U)
1319 #define NUM_MPS_CLS_SRAM_L_INSTANCES 336
1320 #define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512
1322 #define T5_PORT0_BASE 0x30000
1323 #define T5_PORT_STRIDE 0x4000
1324 #define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)
1325 #define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))
1327 #define MC_0_BASE_ADDR 0x40000
1328 #define MC_1_BASE_ADDR 0x48000
1329 #define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR)
1330 #define MC_REG(reg, idx) (reg + MC_STRIDE * idx)
1332 #define MC_P_BIST_CMD 0x41400
1333 #define MC_P_BIST_CMD_ADDR 0x41404
1334 #define MC_P_BIST_CMD_LEN 0x41408
1335 #define MC_P_BIST_DATA_PATTERN 0x4140c
1336 #define MC_P_BIST_STATUS_RDATA 0x41488
1337 #define EDC_T50_BASE_ADDR 0x50000
1338 #define EDC_H_BIST_CMD 0x50004
1339 #define EDC_H_BIST_CMD_ADDR 0x50008
1340 #define EDC_H_BIST_CMD_LEN 0x5000c
1341 #define EDC_H_BIST_DATA_PATTERN 0x50010
1342 #define EDC_H_BIST_STATUS_RDATA 0x50028
1344 #define EDC_T51_BASE_ADDR 0x50800
1345 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
1346 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
1348 #define A_PL_VF_REV 0x4
1349 #define A_PL_VF_WHOAMI 0x0
1350 #define A_PL_VF_REVISION 0x8
1353 #define M_CHIPID 0xfU
1354 #define V_CHIPID(x) ((x) << S_CHIPID)
1355 #define G_CHIPID(x) (((x) >> S_CHIPID) & M_CHIPID)
1357 /* TP_VLAN_PRI_MAP controls which subset of fields will be present in the
1358 * Compressed Filter Tuple for LE filters. Each bit set in TP_VLAN_PRI_MAP
1359 * selects for a particular field being present. These fields, when present
1360 * in the Compressed Filter Tuple, have the following widths in bits.
1364 #define W_FT_VNIC_ID 17
1365 #define W_FT_VLAN 17
1367 #define W_FT_PROTOCOL 8
1368 #define W_FT_ETHERTYPE 16
1369 #define W_FT_MACMATCH 9
1370 #define W_FT_MPSHITTYPE 3
1371 #define W_FT_FRAGMENTATION 1
1373 /* Some of the Compressed Filter Tuple fields have internal structure. These
1374 * bit shifts/masks describe those structures. All shifts are relative to the
1375 * base position of the fields within the Compressed Filter Tuple
1377 #define S_FT_VLAN_VLD 16
1378 #define V_FT_VLAN_VLD(x) ((x) << S_FT_VLAN_VLD)
1379 #define F_FT_VLAN_VLD V_FT_VLAN_VLD(1U)
1381 #define S_FT_VNID_ID_VF 0
1382 #define V_FT_VNID_ID_VF(x) ((x) << S_FT_VNID_ID_VF)
1384 #define S_FT_VNID_ID_PF 7
1385 #define V_FT_VNID_ID_PF(x) ((x) << S_FT_VNID_ID_PF)
1387 #define S_FT_VNID_ID_VLD 16
1388 #define V_FT_VNID_ID_VLD(x) ((x) << S_FT_VNID_ID_VLD)
1390 #endif /* __T4_REGS_H */