drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  36
  37 #include <linux/bitmap.h>
  38 #include <linux/crc32.h>
  39 #include <linux/ctype.h>
  40 #include <linux/debugfs.h>
  41 #include <linux/err.h>
  42 #include <linux/etherdevice.h>
  43 #include <linux/firmware.h>
  44 #include <linux/if.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/init.h>
  47 #include <linux/log2.h>
  48 #include <linux/mdio.h>
  49 #include <linux/module.h>
  50 #include <linux/moduleparam.h>
  51 #include <linux/mutex.h>
  52 #include <linux/netdevice.h>
  53 #include <linux/pci.h>
  54 #include <linux/aer.h>
  55 #include <linux/rtnetlink.h>
  56 #include <linux/sched.h>
  57 #include <linux/seq_file.h>
  58 #include <linux/sockios.h>
  59 #include <linux/vmalloc.h>
  60 #include <linux/workqueue.h>
  61 #include <net/neighbour.h>
  62 #include <net/netevent.h>
  63 #include <net/addrconf.h>
  64 #include <asm/uaccess.h>
  65
  66 #include "cxgb4.h"
  67 #include "t4_regs.h"
  68 #include "t4_msg.h"
  69 #include "t4fw_api.h"
  70 #include "cxgb4_dcb.h"
  71 #include "l2t.h"
  72
  73 #include <../drivers/net/bonding/bonding.h>
  74
  75 #ifdef DRV_VERSION
  76 #undef DRV_VERSION
  77 #endif
  78 #define DRV_VERSION "2.0.0-ko"
  79 #define DRV_DESC "Chelsio T4/T5 Network Driver"
  80
  81 /*
  82  * Max interrupt hold-off timer value in us.  Queues fall back to this value
  83  * under extreme memory pressure so it's largish to give the system time to
  84  * recover.
  85  */
  86 #define MAX_SGE_TIMERVAL 200U
  87
  88 enum {
  89         /*
  90          * Physical Function provisioning constants.
  91          */
  92         PFRES_NVI = 4,                  /* # of Virtual Interfaces */
  93         PFRES_NETHCTRL = 128,           /* # of EQs used for ETH or CTRL Qs */
  94         PFRES_NIQFLINT = 128,           /* # of ingress Qs/w Free List(s)/intr
  95                                          */
  96         PFRES_NEQ = 256,                /* # of egress queues */
  97         PFRES_NIQ = 0,                  /* # of ingress queues */
  98         PFRES_TC = 0,                   /* PCI-E traffic class */
  99         PFRES_NEXACTF = 128,            /* # of exact MPS filters */
 100
 101         PFRES_R_CAPS = FW_CMD_CAP_PF,
 102         PFRES_WX_CAPS = FW_CMD_CAP_PF,
 103
 104 #ifdef CONFIG_PCI_IOV
 105         /*
 106          * Virtual Function provisioning constants.  We need two extra Ingress
 107          * Queues with Interrupt capability to serve as the VF's Firmware
 108          * Event Queue and Forwarded Interrupt Queue (when using MSI mode) --
 109          * neither will have Free Lists associated with them).  For each
 110          * Ethernet/Control Egress Queue and for each Free List, we need an
 111          * Egress Context.
 112          */
 113         VFRES_NPORTS = 1,               /* # of "ports" per VF */
 114         VFRES_NQSETS = 2,               /* # of "Queue Sets" per VF */
 115
 116         VFRES_NVI = VFRES_NPORTS,       /* # of Virtual Interfaces */
 117         VFRES_NETHCTRL = VFRES_NQSETS,  /* # of EQs used for ETH or CTRL Qs */
 118         VFRES_NIQFLINT = VFRES_NQSETS+2,/* # of ingress Qs/w Free List(s)/intr */
 119         VFRES_NEQ = VFRES_NQSETS*2,     /* # of egress queues */
 120         VFRES_NIQ = 0,                  /* # of non-fl/int ingress queues */
 121         VFRES_TC = 0,                   /* PCI-E traffic class */
 122         VFRES_NEXACTF = 16,             /* # of exact MPS filters */
 123
 124         VFRES_R_CAPS = FW_CMD_CAP_DMAQ|FW_CMD_CAP_VF|FW_CMD_CAP_PORT,
 125         VFRES_WX_CAPS = FW_CMD_CAP_DMAQ|FW_CMD_CAP_VF,
 126 #endif
 127 };
 128
 129 /*
 130  * Provide a Port Access Rights Mask for the specified PF/VF.  This is very
 131  * static and likely not to be useful in the long run.  We really need to
 132  * implement some form of persistent configuration which the firmware
 133  * controls.
 134  */
 135 static unsigned int pfvfres_pmask(struct adapter *adapter,
 136                                   unsigned int pf, unsigned int vf)
 137 {
 138         unsigned int portn, portvec;
 139
 140         /*
 141          * Give PF's access to all of the ports.
 142          */
 143         if (vf == 0)
 144                 return FW_PFVF_CMD_PMASK_MASK;
 145
 146         /*
 147          * For VFs, we'll assign them access to the ports based purely on the
 148          * PF.  We assign active ports in order, wrapping around if there are
 149          * fewer active ports than PFs: e.g. active port[pf % nports].
 150          * Unfortunately the adapter's port_info structs haven't been
 151          * initialized yet so we have to compute this.
 152          */
 153         if (adapter->params.nports == 0)
 154                 return 0;
 155
 156         portn = pf % adapter->params.nports;
 157         portvec = adapter->params.portvec;
 158         for (;;) {
 159                 /*
 160                  * Isolate the lowest set bit in the port vector.  If we're at
 161                  * the port number that we want, return that as the pmask.
 162                  * otherwise mask that bit out of the port vector and
 163                  * decrement our port number ...
 164                  */
 165                 unsigned int pmask = portvec ^ (portvec & (portvec-1));
 166                 if (portn == 0)
 167                         return pmask;
 168                 portn--;
 169                 portvec &= ~pmask;
 170         }
 171         /*NOTREACHED*/
 172 }
 173
 174 enum {
 175         MAX_TXQ_ENTRIES      = 16384,
 176         MAX_CTRL_TXQ_ENTRIES = 1024,
 177         MAX_RSPQ_ENTRIES     = 16384,
 178         MAX_RX_BUFFERS       = 16384,
 179         MIN_TXQ_ENTRIES      = 32,
 180         MIN_CTRL_TXQ_ENTRIES = 32,
 181         MIN_RSPQ_ENTRIES     = 128,
 182         MIN_FL_ENTRIES       = 16
 183 };
 184
 185 /* Host shadow copy of ingress filter entry.  This is in host native format
 186  * and doesn't match the ordering or bit order, etc. of the hardware of the
 187  * firmware command.  The use of bit-field structure elements is purely to
 188  * remind ourselves of the field size limitations and save memory in the case
 189  * where the filter table is large.
 190  */
 191 struct filter_entry {
 192         /* Administrative fields for filter.
 193          */
 194         u32 valid:1;            /* filter allocated and valid */
 195         u32 locked:1;           /* filter is administratively locked */
 196
 197         u32 pending:1;          /* filter action is pending firmware reply */
 198         u32 smtidx:8;           /* Source MAC Table index for smac */
 199         struct l2t_entry *l2t;  /* Layer Two Table entry for dmac */
 200
 201         /* The filter itself.  Most of this is a straight copy of information
 202          * provided by the extended ioctl().  Some fields are translated to
 203          * internal forms -- for instance the Ingress Queue ID passed in from
 204          * the ioctl() is translated into the Absolute Ingress Queue ID.
 205          */
 206         struct ch_filter_specification fs;
 207 };
 208
 209 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
 210                          NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
 211                          NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
 212
 213 #define CH_DEVICE(devid, data) { PCI_VDEVICE(CHELSIO, devid), (data) }
 214
 215 static const struct pci_device_id cxgb4_pci_tbl[] = {
 216         CH_DEVICE(0xa000, 0),  /* PE10K */
 217         CH_DEVICE(0x4001, -1),
 218         CH_DEVICE(0x4002, -1),
 219         CH_DEVICE(0x4003, -1),
 220         CH_DEVICE(0x4004, -1),
 221         CH_DEVICE(0x4005, -1),
 222         CH_DEVICE(0x4006, -1),
 223         CH_DEVICE(0x4007, -1),
 224         CH_DEVICE(0x4008, -1),
 225         CH_DEVICE(0x4009, -1),
 226         CH_DEVICE(0x400a, -1),
 227         CH_DEVICE(0x400d, -1),
 228         CH_DEVICE(0x400e, -1),
 229         CH_DEVICE(0x4080, -1),
 230         CH_DEVICE(0x4081, -1),
 231         CH_DEVICE(0x4082, -1),
 232         CH_DEVICE(0x4083, -1),
 233         CH_DEVICE(0x4084, -1),
 234         CH_DEVICE(0x4085, -1),
 235         CH_DEVICE(0x4086, -1),
 236         CH_DEVICE(0x4087, -1),
 237         CH_DEVICE(0x4088, -1),
 238         CH_DEVICE(0x4401, 4),
 239         CH_DEVICE(0x4402, 4),
 240         CH_DEVICE(0x4403, 4),
 241         CH_DEVICE(0x4404, 4),
 242         CH_DEVICE(0x4405, 4),
 243         CH_DEVICE(0x4406, 4),
 244         CH_DEVICE(0x4407, 4),
 245         CH_DEVICE(0x4408, 4),
 246         CH_DEVICE(0x4409, 4),
 247         CH_DEVICE(0x440a, 4),
 248         CH_DEVICE(0x440d, 4),
 249         CH_DEVICE(0x440e, 4),
 250         CH_DEVICE(0x4480, 4),
 251         CH_DEVICE(0x4481, 4),
 252         CH_DEVICE(0x4482, 4),
 253         CH_DEVICE(0x4483, 4),
 254         CH_DEVICE(0x4484, 4),
 255         CH_DEVICE(0x4485, 4),
 256         CH_DEVICE(0x4486, 4),
 257         CH_DEVICE(0x4487, 4),
 258         CH_DEVICE(0x4488, 4),
 259         CH_DEVICE(0x5001, 4),
 260         CH_DEVICE(0x5002, 4),
 261         CH_DEVICE(0x5003, 4),
 262         CH_DEVICE(0x5004, 4),
 263         CH_DEVICE(0x5005, 4),
 264         CH_DEVICE(0x5006, 4),
 265         CH_DEVICE(0x5007, 4),
 266         CH_DEVICE(0x5008, 4),
 267         CH_DEVICE(0x5009, 4),
 268         CH_DEVICE(0x500A, 4),
 269         CH_DEVICE(0x500B, 4),
 270         CH_DEVICE(0x500C, 4),
 271         CH_DEVICE(0x500D, 4),
 272         CH_DEVICE(0x500E, 4),
 273         CH_DEVICE(0x500F, 4),
 274         CH_DEVICE(0x5010, 4),
 275         CH_DEVICE(0x5011, 4),
 276         CH_DEVICE(0x5012, 4),
 277         CH_DEVICE(0x5013, 4),
 278         CH_DEVICE(0x5014, 4),
 279         CH_DEVICE(0x5015, 4),
 280         CH_DEVICE(0x5080, 4),
 281         CH_DEVICE(0x5081, 4),
 282         CH_DEVICE(0x5082, 4),
 283         CH_DEVICE(0x5083, 4),
 284         CH_DEVICE(0x5084, 4),
 285         CH_DEVICE(0x5085, 4),
 286         CH_DEVICE(0x5401, 4),
 287         CH_DEVICE(0x5402, 4),
 288         CH_DEVICE(0x5403, 4),
 289         CH_DEVICE(0x5404, 4),
 290         CH_DEVICE(0x5405, 4),
 291         CH_DEVICE(0x5406, 4),
 292         CH_DEVICE(0x5407, 4),
 293         CH_DEVICE(0x5408, 4),
 294         CH_DEVICE(0x5409, 4),
 295         CH_DEVICE(0x540A, 4),
 296         CH_DEVICE(0x540B, 4),
 297         CH_DEVICE(0x540C, 4),
 298         CH_DEVICE(0x540D, 4),
 299         CH_DEVICE(0x540E, 4),
 300         CH_DEVICE(0x540F, 4),
 301         CH_DEVICE(0x5410, 4),
 302         CH_DEVICE(0x5411, 4),
 303         CH_DEVICE(0x5412, 4),
 304         CH_DEVICE(0x5413, 4),
 305         CH_DEVICE(0x5414, 4),
 306         CH_DEVICE(0x5415, 4),
 307         CH_DEVICE(0x5480, 4),
 308         CH_DEVICE(0x5481, 4),
 309         CH_DEVICE(0x5482, 4),
 310         CH_DEVICE(0x5483, 4),
 311         CH_DEVICE(0x5484, 4),
 312         CH_DEVICE(0x5485, 4),
 313         { 0, }
 314 };
 315
 316 #define FW4_FNAME "cxgb4/t4fw.bin"
 317 #define FW5_FNAME "cxgb4/t5fw.bin"
 318 #define FW4_CFNAME "cxgb4/t4-config.txt"
 319 #define FW5_CFNAME "cxgb4/t5-config.txt"
 320
 321 MODULE_DESCRIPTION(DRV_DESC);
 322 MODULE_AUTHOR("Chelsio Communications");
 323 MODULE_LICENSE("Dual BSD/GPL");
 324 MODULE_VERSION(DRV_VERSION);
 325 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
 326 MODULE_FIRMWARE(FW4_FNAME);
 327 MODULE_FIRMWARE(FW5_FNAME);
 328
 329 /*
 330  * Normally we're willing to become the firmware's Master PF but will be happy
 331  * if another PF has already become the Master and initialized the adapter.
 332  * Setting "force_init" will cause this driver to forcibly establish itself as
 333  * the Master PF and initialize the adapter.
 334  */
 335 static uint force_init;
 336
 337 module_param(force_init, uint, 0644);
 338 MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter");
 339
 340 /*
 341  * Normally if the firmware we connect to has Configuration File support, we
 342  * use that and only fall back to the old Driver-based initialization if the
 343  * Configuration File fails for some reason.  If force_old_init is set, then
 344  * we'll always use the old Driver-based initialization sequence.
 345  */
 346 static uint force_old_init;
 347
 348 module_param(force_old_init, uint, 0644);
 349 MODULE_PARM_DESC(force_old_init, "Force old initialization sequence");
 350
 351 static int dflt_msg_enable = DFLT_MSG_ENABLE;
 352
 353 module_param(dflt_msg_enable, int, 0644);
 354 MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap");
 355
 356 /*
 357  * The driver uses the best interrupt scheme available on a platform in the
 358  * order MSI-X, MSI, legacy INTx interrupts.  This parameter determines which
 359  * of these schemes the driver may consider as follows:
 360  *
 361  * msi = 2: choose from among all three options
 362  * msi = 1: only consider MSI and INTx interrupts
 363  * msi = 0: force INTx interrupts
 364  */
 365 static int msi = 2;
 366
 367 module_param(msi, int, 0644);
 368 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
 369
 370 /*
 371  * Queue interrupt hold-off timer values.  Queues default to the first of these
 372  * upon creation.
 373  */
 374 static unsigned int intr_holdoff[SGE_NTIMERS - 1] = { 5, 10, 20, 50, 100 };
 375
 376 module_param_array(intr_holdoff, uint, NULL, 0644);
 377 MODULE_PARM_DESC(intr_holdoff, "values for queue interrupt hold-off timers "
 378                  "0..4 in microseconds");
 379
 380 static unsigned int intr_cnt[SGE_NCOUNTERS - 1] = { 4, 8, 16 };
 381
 382 module_param_array(intr_cnt, uint, NULL, 0644);
 383 MODULE_PARM_DESC(intr_cnt,
 384                  "thresholds 1..3 for queue interrupt packet counters");
 385
 386 /*
 387  * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
 388  * offset by 2 bytes in order to have the IP headers line up on 4-byte
 389  * boundaries.  This is a requirement for many architectures which will throw
 390  * a machine check fault if an attempt is made to access one of the 4-byte IP
 391  * header fields on a non-4-byte boundary.  And it's a major performance issue
 392  * even on some architectures which allow it like some implementations of the
 393  * x86 ISA.  However, some architectures don't mind this and for some very
 394  * edge-case performance sensitive applications (like forwarding large volumes
 395  * of small packets), setting this DMA offset to 0 will decrease the number of
 396  * PCI-E Bus transfers enough to measurably affect performance.
 397  */
 398 static int rx_dma_offset = 2;
 399
 400 static bool vf_acls;
 401
 402 #ifdef CONFIG_PCI_IOV
 403 module_param(vf_acls, bool, 0644);
 404 MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement");
 405
 406 /* Configure the number of PCI-E Virtual Function which are to be instantiated
 407  * on SR-IOV Capable Physical Functions.
 408  */
 409 static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV];
 410
 411 module_param_array(num_vf, uint, NULL, 0644);
 412 MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3");
 413 #endif
 414
 415 /* TX Queue select used to determine what algorithm to use for selecting TX
 416  * queue. Select between the kernel provided function (select_queue=0) or user
 417  * cxgb_select_queue function (select_queue=1)
 418  *
 419  * Default: select_queue=0
 420  */
 421 static int select_queue;
 422 module_param(select_queue, int, 0644);
 423 MODULE_PARM_DESC(select_queue,
 424                  "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
 425
 426 /*
 427  * The filter TCAM has a fixed portion and a variable portion.  The fixed
 428  * portion can match on source/destination IP IPv4/IPv6 addresses and TCP/UDP
 429  * ports.  The variable portion is 36 bits which can include things like Exact
 430  * Match MAC Index (9 bits), Ether Type (16 bits), IP Protocol (8 bits),
 431  * [Inner] VLAN Tag (17 bits), etc. which, if all were somehow selected, would
 432  * far exceed the 36-bit budget for this "compressed" header portion of the
 433  * filter.  Thus, we have a scarce resource which must be carefully managed.
 434  *
 435  * By default we set this up to mostly match the set of filter matching
 436  * capabilities of T3 but with accommodations for some of T4's more
 437  * interesting features:
 438  *
 439  *   { IP Fragment (1), MPS Match Type (3), IP Protocol (8),
 440  *     [Inner] VLAN (17), Port (3), FCoE (1) }
 441  */
 442 enum {
 443         TP_VLAN_PRI_MAP_DEFAULT = HW_TPL_FR_MT_PR_IV_P_FC,
 444         TP_VLAN_PRI_MAP_FIRST = FCOE_SHIFT,
 445         TP_VLAN_PRI_MAP_LAST = FRAGMENTATION_SHIFT,
 446 };
 447
 448 static unsigned int tp_vlan_pri_map = TP_VLAN_PRI_MAP_DEFAULT;
 449
 450 module_param(tp_vlan_pri_map, uint, 0644);
 451 MODULE_PARM_DESC(tp_vlan_pri_map, "global compressed filter configuration");
 452
 453 static struct dentry *cxgb4_debugfs_root;
 454
 455 static LIST_HEAD(adapter_list);
 456 static DEFINE_MUTEX(uld_mutex);
 457 /* Adapter list to be accessed from atomic context */
 458 static LIST_HEAD(adap_rcu_list);
 459 static DEFINE_SPINLOCK(adap_rcu_lock);
 460 static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX];
 461 static const char *uld_str[] = { "RDMA", "iSCSI" };
 462
 463 static void link_report(struct net_device *dev)
 464 {
 465         if (!netif_carrier_ok(dev))
 466                 netdev_info(dev, "link down\n");
 467         else {
 468                 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
 469
 470                 const char *s = "10Mbps";
 471                 const struct port_info *p = netdev_priv(dev);
 472
 473                 switch (p->link_cfg.speed) {
 474                 case 10000:
 475                         s = "10Gbps";
 476                         break;
 477                 case 1000:
 478                         s = "1000Mbps";
 479                         break;
 480                 case 100:
 481                         s = "100Mbps";
 482                         break;
 483                 case 40000:
 484                         s = "40Gbps";
 485                         break;
 486                 }
 487
 488                 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
 489                             fc[p->link_cfg.fc]);
 490         }
 491 }
 492
 493 #ifdef CONFIG_CHELSIO_T4_DCB
 494 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */
 495 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
 496 {
 497         struct port_info *pi = netdev_priv(dev);
 498         struct adapter *adap = pi->adapter;
 499         struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
 500         int i;
 501
 502         /* We use a simple mapping of Port TX Queue Index to DCB
 503          * Priority when we're enabling DCB.
 504          */
 505         for (i = 0; i < pi->nqsets; i++, txq++) {
 506                 u32 name, value;
 507                 int err;
 508
 509                 name = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
 510                         FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
 511                         FW_PARAMS_PARAM_YZ(txq->q.cntxt_id));
 512                 value = enable ? i : 0xffffffff;
 513
 514                 /* Since we can be called while atomic (from "interrupt
 515                  * level") we need to issue the Set Parameters Commannd
 516                  * without sleeping (timeout < 0).
 517                  */
 518                 err = t4_set_params_nosleep(adap, adap->mbox, adap->fn, 0, 1,
 519                                             &name, &value);
 520
 521                 if (err)
 522                         dev_err(adap->pdev_dev,
 523                                 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
 524                                 enable ? "set" : "unset", pi->port_id, i, -err);
 525                 else
 526                         txq->dcb_prio = value;
 527         }
 528 }
 529 #endif /* CONFIG_CHELSIO_T4_DCB */
 530
 531 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
 532 {
 533         struct net_device *dev = adapter->port[port_id];
 534
 535         /* Skip changes from disabled ports. */
 536         if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
 537                 if (link_stat)
 538                         netif_carrier_on(dev);
 539                 else {
 540 #ifdef CONFIG_CHELSIO_T4_DCB
 541                         cxgb4_dcb_state_init(dev);
 542                         dcb_tx_queue_prio_enable(dev, false);
 543 #endif /* CONFIG_CHELSIO_T4_DCB */
 544                         netif_carrier_off(dev);
 545                 }
 546
 547                 link_report(dev);
 548         }
 549 }
 550
 551 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
 552 {
 553         static const char *mod_str[] = {
 554                 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
 555         };
 556
 557         const struct net_device *dev = adap->port[port_id];
 558         const struct port_info *pi = netdev_priv(dev);
 559
 560         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
 561                 netdev_info(dev, "port module unplugged\n");
 562         else if (pi->mod_type < ARRAY_SIZE(mod_str))
 563                 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
 564 }
 565
 566 /*
 567  * Configure the exact and hash address filters to handle a port's multicast
 568  * and secondary unicast MAC addresses.
 569  */
 570 static int set_addr_filters(const struct net_device *dev, bool sleep)
 571 {
 572         u64 mhash = 0;
 573         u64 uhash = 0;
 574         bool free = true;
 575         u16 filt_idx[7];
 576         const u8 *addr[7];
 577         int ret, naddr = 0;
 578         const struct netdev_hw_addr *ha;
 579         int uc_cnt = netdev_uc_count(dev);
 580         int mc_cnt = netdev_mc_count(dev);
 581         const struct port_info *pi = netdev_priv(dev);
 582         unsigned int mb = pi->adapter->fn;
 583
 584         /* first do the secondary unicast addresses */
 585         netdev_for_each_uc_addr(ha, dev) {
 586                 addr[naddr++] = ha->addr;
 587                 if (--uc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
 588                         ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
 589                                         naddr, addr, filt_idx, &uhash, sleep);
 590                         if (ret < 0)
 591                                 return ret;
 592
 593                         free = false;
 594                         naddr = 0;
 595                 }
 596         }
 597
 598         /* next set up the multicast addresses */
 599         netdev_for_each_mc_addr(ha, dev) {
 600                 addr[naddr++] = ha->addr;
 601                 if (--mc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
 602                         ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
 603                                         naddr, addr, filt_idx, &mhash, sleep);
 604                         if (ret < 0)
 605                                 return ret;
 606
 607                         free = false;
 608                         naddr = 0;
 609                 }
 610         }
 611
 612         return t4_set_addr_hash(pi->adapter, mb, pi->viid, uhash != 0,
 613                                 uhash | mhash, sleep);
 614 }
 615
 616 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
 617 module_param(dbfifo_int_thresh, int, 0644);
 618 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
 619
 620 /*
 621  * usecs to sleep while draining the dbfifo
 622  */
 623 static int dbfifo_drain_delay = 1000;
 624 module_param(dbfifo_drain_delay, int, 0644);
 625 MODULE_PARM_DESC(dbfifo_drain_delay,
 626                  "usecs to sleep while draining the dbfifo");
 627
 628 /*
 629  * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
 630  * If @mtu is -1 it is left unchanged.
 631  */
 632 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
 633 {
 634         int ret;
 635         struct port_info *pi = netdev_priv(dev);
 636
 637         ret = set_addr_filters(dev, sleep_ok);
 638         if (ret == 0)
 639                 ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, mtu,
 640                                     (dev->flags & IFF_PROMISC) ? 1 : 0,
 641                                     (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
 642                                     sleep_ok);
 643         return ret;
 644 }
 645
 646 /**
 647  *      link_start - enable a port
 648  *      @dev: the port to enable
 649  *
 650  *      Performs the MAC and PHY actions needed to enable a port.
 651  */
 652 static int link_start(struct net_device *dev)
 653 {
 654         int ret;
 655         struct port_info *pi = netdev_priv(dev);
 656         unsigned int mb = pi->adapter->fn;
 657
 658         /*
 659          * We do not set address filters and promiscuity here, the stack does
 660          * that step explicitly.
 661          */
 662         ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
 663                             !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
 664         if (ret == 0) {
 665                 ret = t4_change_mac(pi->adapter, mb, pi->viid,
 666                                     pi->xact_addr_filt, dev->dev_addr, true,
 667                                     true);
 668                 if (ret >= 0) {
 669                         pi->xact_addr_filt = ret;
 670                         ret = 0;
 671                 }
 672         }
 673         if (ret == 0)
 674                 ret = t4_link_start(pi->adapter, mb, pi->tx_chan,
 675                                     &pi->link_cfg);
 676         if (ret == 0) {
 677                 local_bh_disable();
 678                 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true,
 679                                           true, CXGB4_DCB_ENABLED);
 680                 local_bh_enable();
 681         }
 682
 683         return ret;
 684 }
 685
 686 int cxgb4_dcb_enabled(const struct net_device *dev)
 687 {
 688 #ifdef CONFIG_CHELSIO_T4_DCB
 689         struct port_info *pi = netdev_priv(dev);
 690
 691         return pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED;
 692 #else
 693         return 0;
 694 #endif
 695 }
 696 EXPORT_SYMBOL(cxgb4_dcb_enabled);
 697
 698 #ifdef CONFIG_CHELSIO_T4_DCB
 699 /* Handle a Data Center Bridging update message from the firmware. */
 700 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
 701 {
 702         int port = FW_PORT_CMD_PORTID_GET(ntohl(pcmd->op_to_portid));
 703         struct net_device *dev = adap->port[port];
 704         int old_dcb_enabled = cxgb4_dcb_enabled(dev);
 705         int new_dcb_enabled;
 706
 707         cxgb4_dcb_handle_fw_update(adap, pcmd);
 708         new_dcb_enabled = cxgb4_dcb_enabled(dev);
 709
 710         /* If the DCB has become enabled or disabled on the port then we're
 711          * going to need to set up/tear down DCB Priority parameters for the
 712          * TX Queues associated with the port.
 713          */
 714         if (new_dcb_enabled != old_dcb_enabled)
 715                 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
 716 }
 717 #endif /* CONFIG_CHELSIO_T4_DCB */
 718
 719 /* Clear a filter and release any of its resources that we own.  This also
 720  * clears the filter's "pending" status.
 721  */
 722 static void clear_filter(struct adapter *adap, struct filter_entry *f)
 723 {
 724         /* If the new or old filter have loopback rewriteing rules then we'll
 725          * need to free any existing Layer Two Table (L2T) entries of the old
 726          * filter rule.  The firmware will handle freeing up any Source MAC
 727          * Table (SMT) entries used for rewriting Source MAC Addresses in
 728          * loopback rules.
 729          */
 730         if (f->l2t)
 731                 cxgb4_l2t_release(f->l2t);
 732
 733         /* The zeroing of the filter rule below clears the filter valid,
 734          * pending, locked flags, l2t pointer, etc. so it's all we need for
 735          * this operation.
 736          */
 737         memset(f, 0, sizeof(*f));
 738 }
 739
 740 /* Handle a filter write/deletion reply.
 741  */
 742 static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
 743 {
 744         unsigned int idx = GET_TID(rpl);
 745         unsigned int nidx = idx - adap->tids.ftid_base;
 746         unsigned int ret;
 747         struct filter_entry *f;
 748
 749         if (idx >= adap->tids.ftid_base && nidx <
 750            (adap->tids.nftids + adap->tids.nsftids)) {
 751                 idx = nidx;
 752                 ret = GET_TCB_COOKIE(rpl->cookie);
 753                 f = &adap->tids.ftid_tab[idx];
 754
 755                 if (ret == FW_FILTER_WR_FLT_DELETED) {
 756                         /* Clear the filter when we get confirmation from the
 757                          * hardware that the filter has been deleted.
 758                          */
 759                         clear_filter(adap, f);
 760                 } else if (ret == FW_FILTER_WR_SMT_TBL_FULL) {
 761                         dev_err(adap->pdev_dev, "filter %u setup failed due to full SMT\n",
 762                                 idx);
 763                         clear_filter(adap, f);
 764                 } else if (ret == FW_FILTER_WR_FLT_ADDED) {
 765                         f->smtidx = (be64_to_cpu(rpl->oldval) >> 24) & 0xff;
 766                         f->pending = 0;  /* asynchronous setup completed */
 767                         f->valid = 1;
 768                 } else {
 769                         /* Something went wrong.  Issue a warning about the
 770                          * problem and clear everything out.
 771                          */
 772                         dev_err(adap->pdev_dev, "filter %u setup failed with error %u\n",
 773                                 idx, ret);
 774                         clear_filter(adap, f);
 775                 }
 776         }
 777 }
 778
 779 /* Response queue handler for the FW event queue.
 780  */
 781 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
 782                           const struct pkt_gl *gl)
 783 {
 784         u8 opcode = ((const struct rss_header *)rsp)->opcode;
 785
 786         rsp++;                                          /* skip RSS header */
 787
 788         /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
 789          */
 790         if (unlikely(opcode == CPL_FW4_MSG &&
 791            ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
 792                 rsp++;
 793                 opcode = ((const struct rss_header *)rsp)->opcode;
 794                 rsp++;
 795                 if (opcode != CPL_SGE_EGR_UPDATE) {
 796                         dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
 797                                 , opcode);
 798                         goto out;
 799                 }
 800         }
 801
 802         if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
 803                 const struct cpl_sge_egr_update *p = (void *)rsp;
 804                 unsigned int qid = EGR_QID(ntohl(p->opcode_qid));
 805                 struct sge_txq *txq;
 806
 807                 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
 808                 txq->restarts++;
 809                 if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) {
 810                         struct sge_eth_txq *eq;
 811
 812                         eq = container_of(txq, struct sge_eth_txq, q);
 813                         netif_tx_wake_queue(eq->txq);
 814                 } else {
 815                         struct sge_ofld_txq *oq;
 816
 817                         oq = container_of(txq, struct sge_ofld_txq, q);
 818                         tasklet_schedule(&oq->qresume_tsk);
 819                 }
 820         } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
 821                 const struct cpl_fw6_msg *p = (void *)rsp;
 822
 823 #ifdef CONFIG_CHELSIO_T4_DCB
 824                 const struct fw_port_cmd *pcmd = (const void *)p->data;
 825                 unsigned int cmd = FW_CMD_OP_GET(ntohl(pcmd->op_to_portid));
 826                 unsigned int action =
 827                         FW_PORT_CMD_ACTION_GET(ntohl(pcmd->action_to_len16));
 828
 829                 if (cmd == FW_PORT_CMD &&
 830                     action == FW_PORT_ACTION_GET_PORT_INFO) {
 831                         int port = FW_PORT_CMD_PORTID_GET(
 832                                         be32_to_cpu(pcmd->op_to_portid));
 833                         struct net_device *dev = q->adap->port[port];
 834                         int state_input = ((pcmd->u.info.dcbxdis_pkd &
 835                                             FW_PORT_CMD_DCBXDIS)
 836                                            ? CXGB4_DCB_INPUT_FW_DISABLED
 837                                            : CXGB4_DCB_INPUT_FW_ENABLED);
 838
 839                         cxgb4_dcb_state_fsm(dev, state_input);
 840                 }
 841
 842                 if (cmd == FW_PORT_CMD &&
 843                     action == FW_PORT_ACTION_L2_DCB_CFG)
 844                         dcb_rpl(q->adap, pcmd);
 845                 else
 846 #endif
 847                         if (p->type == 0)
 848                                 t4_handle_fw_rpl(q->adap, p->data);
 849         } else if (opcode == CPL_L2T_WRITE_RPL) {
 850                 const struct cpl_l2t_write_rpl *p = (void *)rsp;
 851
 852                 do_l2t_write_rpl(q->adap, p);
 853         } else if (opcode == CPL_SET_TCB_RPL) {
 854                 const struct cpl_set_tcb_rpl *p = (void *)rsp;
 855
 856                 filter_rpl(q->adap, p);
 857         } else
 858                 dev_err(q->adap->pdev_dev,
 859                         "unexpected CPL %#x on FW event queue\n", opcode);
 860 out:
 861         return 0;
 862 }
 863
 864 /**
 865  *      uldrx_handler - response queue handler for ULD queues
 866  *      @q: the response queue that received the packet
 867  *      @rsp: the response queue descriptor holding the offload message
 868  *      @gl: the gather list of packet fragments
 869  *
 870  *      Deliver an ingress offload packet to a ULD.  All processing is done by
 871  *      the ULD, we just maintain statistics.
 872  */
 873 static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
 874                          const struct pkt_gl *gl)
 875 {
 876         struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
 877
 878         /* FW can send CPLs encapsulated in a CPL_FW4_MSG.
 879          */
 880         if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG &&
 881             ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL)
 882                 rsp += 2;
 883
 884         if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) {
 885                 rxq->stats.nomem++;
 886                 return -1;
 887         }
 888         if (gl == NULL)
 889                 rxq->stats.imm++;
 890         else if (gl == CXGB4_MSG_AN)
 891                 rxq->stats.an++;
 892         else
 893                 rxq->stats.pkts++;
 894         return 0;
 895 }
 896
 897 static void disable_msi(struct adapter *adapter)
 898 {
 899         if (adapter->flags & USING_MSIX) {
 900                 pci_disable_msix(adapter->pdev);
 901                 adapter->flags &= ~USING_MSIX;
 902         } else if (adapter->flags & USING_MSI) {
 903                 pci_disable_msi(adapter->pdev);
 904                 adapter->flags &= ~USING_MSI;
 905         }
 906 }
 907
 908 /*
 909  * Interrupt handler for non-data events used with MSI-X.
 910  */
 911 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
 912 {
 913         struct adapter *adap = cookie;
 914
 915         u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE));
 916         if (v & PFSW) {
 917                 adap->swintr = 1;
 918                 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE), v);
 919         }
 920         t4_slow_intr_handler(adap);
 921         return IRQ_HANDLED;
 922 }
 923
 924 /*
 925  * Name the MSI-X interrupts.
 926  */
 927 static void name_msix_vecs(struct adapter *adap)
 928 {
 929         int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
 930
 931         /* non-data interrupts */
 932         snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
 933
 934         /* FW events */
 935         snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
 936                  adap->port[0]->name);
 937
 938         /* Ethernet queues */
 939         for_each_port(adap, j) {
 940                 struct net_device *d = adap->port[j];
 941                 const struct port_info *pi = netdev_priv(d);
 942
 943                 for (i = 0; i < pi->nqsets; i++, msi_idx++)
 944                         snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
 945                                  d->name, i);
 946         }
 947
 948         /* offload queues */
 949         for_each_ofldrxq(&adap->sge, i)
 950                 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-ofld%d",
 951                          adap->port[0]->name, i);
 952
 953         for_each_rdmarxq(&adap->sge, i)
 954                 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d",
 955                          adap->port[0]->name, i);
 956
 957         for_each_rdmaciq(&adap->sge, i)
 958                 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma-ciq%d",
 959                          adap->port[0]->name, i);
 960 }
 961
 962 static int request_msix_queue_irqs(struct adapter *adap)
 963 {
 964         struct sge *s = &adap->sge;
 965         int err, ethqidx, ofldqidx = 0, rdmaqidx = 0, rdmaciqqidx = 0;
 966         int msi_index = 2;
 967
 968         err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
 969                           adap->msix_info[1].desc, &s->fw_evtq);
 970         if (err)
 971                 return err;
 972
 973         for_each_ethrxq(s, ethqidx) {
 974                 err = request_irq(adap->msix_info[msi_index].vec,
 975                                   t4_sge_intr_msix, 0,
 976                                   adap->msix_info[msi_index].desc,
 977                                   &s->ethrxq[ethqidx].rspq);
 978                 if (err)
 979                         goto unwind;
 980                 msi_index++;
 981         }
 982         for_each_ofldrxq(s, ofldqidx) {
 983                 err = request_irq(adap->msix_info[msi_index].vec,
 984                                   t4_sge_intr_msix, 0,
 985                                   adap->msix_info[msi_index].desc,
 986                                   &s->ofldrxq[ofldqidx].rspq);
 987                 if (err)
 988                         goto unwind;
 989                 msi_index++;
 990         }
 991         for_each_rdmarxq(s, rdmaqidx) {
 992                 err = request_irq(adap->msix_info[msi_index].vec,
 993                                   t4_sge_intr_msix, 0,
 994                                   adap->msix_info[msi_index].desc,
 995                                   &s->rdmarxq[rdmaqidx].rspq);
 996                 if (err)
 997                         goto unwind;
 998                 msi_index++;
 999         }
1000         for_each_rdmaciq(s, rdmaciqqidx) {
1001                 err = request_irq(adap->msix_info[msi_index].vec,
1002                                   t4_sge_intr_msix, 0,
1003                                   adap->msix_info[msi_index].desc,
1004                                   &s->rdmaciq[rdmaciqqidx].rspq);
1005                 if (err)
1006                         goto unwind;
1007                 msi_index++;
1008         }
1009         return 0;
1010
1011 unwind:
1012         while (--rdmaciqqidx >= 0)
1013                 free_irq(adap->msix_info[--msi_index].vec,
1014                          &s->rdmaciq[rdmaciqqidx].rspq);
1015         while (--rdmaqidx >= 0)
1016                 free_irq(adap->msix_info[--msi_index].vec,
1017                          &s->rdmarxq[rdmaqidx].rspq);
1018         while (--ofldqidx >= 0)
1019                 free_irq(adap->msix_info[--msi_index].vec,
1020                          &s->ofldrxq[ofldqidx].rspq);
1021         while (--ethqidx >= 0)
1022                 free_irq(adap->msix_info[--msi_index].vec,
1023                          &s->ethrxq[ethqidx].rspq);
1024         free_irq(adap->msix_info[1].vec, &s->fw_evtq);
1025         return err;
1026 }
1027
1028 static void free_msix_queue_irqs(struct adapter *adap)
1029 {
1030         int i, msi_index = 2;
1031         struct sge *s = &adap->sge;
1032
1033         free_irq(adap->msix_info[1].vec, &s->fw_evtq);
1034         for_each_ethrxq(s, i)
1035                 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
1036         for_each_ofldrxq(s, i)
1037                 free_irq(adap->msix_info[msi_index++].vec, &s->ofldrxq[i].rspq);
1038         for_each_rdmarxq(s, i)
1039                 free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq);
1040         for_each_rdmaciq(s, i)
1041                 free_irq(adap->msix_info[msi_index++].vec, &s->rdmaciq[i].rspq);
1042 }
1043
1044 /**
1045  *      write_rss - write the RSS table for a given port
1046  *      @pi: the port
1047  *      @queues: array of queue indices for RSS
1048  *
1049  *      Sets up the portion of the HW RSS table for the port's VI to distribute
1050  *      packets to the Rx queues in @queues.
1051  */
1052 static int write_rss(const struct port_info *pi, const u16 *queues)
1053 {
1054         u16 *rss;
1055         int i, err;
1056         const struct sge_eth_rxq *q = &pi->adapter->sge.ethrxq[pi->first_qset];
1057
1058         rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
1059         if (!rss)
1060                 return -ENOMEM;
1061
1062         /* map the queue indices to queue ids */
1063         for (i = 0; i < pi->rss_size; i++, queues++)
1064                 rss[i] = q[*queues].rspq.abs_id;
1065
1066         err = t4_config_rss_range(pi->adapter, pi->adapter->fn, pi->viid, 0,
1067                                   pi->rss_size, rss, pi->rss_size);
1068         kfree(rss);
1069         return err;
1070 }
1071
1072 /**
1073  *      setup_rss - configure RSS
1074  *      @adap: the adapter
1075  *
1076  *      Sets up RSS for each port.
1077  */
1078 static int setup_rss(struct adapter *adap)
1079 {
1080         int i, err;
1081
1082         for_each_port(adap, i) {
1083                 const struct port_info *pi = adap2pinfo(adap, i);
1084
1085                 err = write_rss(pi, pi->rss);
1086                 if (err)
1087                         return err;
1088         }
1089         return 0;
1090 }
1091
1092 /*
1093  * Return the channel of the ingress queue with the given qid.
1094  */
1095 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
1096 {
1097         qid -= p->ingr_start;
1098         return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
1099 }
1100
1101 /*
1102  * Wait until all NAPI handlers are descheduled.
1103  */
1104 static void quiesce_rx(struct adapter *adap)
1105 {
1106         int i;
1107
1108         for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
1109                 struct sge_rspq *q = adap->sge.ingr_map[i];
1110
1111                 if (q && q->handler)
1112                         napi_disable(&q->napi);
1113         }
1114 }
1115
1116 /*
1117  * Enable NAPI scheduling and interrupt generation for all Rx queues.
1118  */
1119 static void enable_rx(struct adapter *adap)
1120 {
1121         int i;
1122
1123         for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
1124                 struct sge_rspq *q = adap->sge.ingr_map[i];
1125
1126                 if (!q)
1127                         continue;
1128                 if (q->handler)
1129                         napi_enable(&q->napi);
1130                 /* 0-increment GTS to start the timer and enable interrupts */
1131                 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS),
1132                              SEINTARM(q->intr_params) |
1133                              INGRESSQID(q->cntxt_id));
1134         }
1135 }
1136
1137 /**
1138  *      setup_sge_queues - configure SGE Tx/Rx/response queues
1139  *      @adap: the adapter
1140  *
1141  *      Determines how many sets of SGE queues to use and initializes them.
1142  *      We support multiple queue sets per port if we have MSI-X, otherwise
1143  *      just one queue set per port.
1144  */
1145 static int setup_sge_queues(struct adapter *adap)
1146 {
1147         int err, msi_idx, i, j;
1148         struct sge *s = &adap->sge;
1149
1150         bitmap_zero(s->starving_fl, MAX_EGRQ);
1151         bitmap_zero(s->txq_maperr, MAX_EGRQ);
1152
1153         if (adap->flags & USING_MSIX)
1154                 msi_idx = 1;         /* vector 0 is for non-queue interrupts */
1155         else {
1156                 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
1157                                        NULL, NULL);
1158                 if (err)
1159                         return err;
1160                 msi_idx = -((int)s->intrq.abs_id + 1);
1161         }
1162
1163         err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
1164                                msi_idx, NULL, fwevtq_handler);
1165         if (err) {
1166 freeout:        t4_free_sge_resources(adap);
1167                 return err;
1168         }
1169
1170         for_each_port(adap, i) {
1171                 struct net_device *dev = adap->port[i];
1172                 struct port_info *pi = netdev_priv(dev);
1173                 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
1174                 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
1175
1176                 for (j = 0; j < pi->nqsets; j++, q++) {
1177                         if (msi_idx > 0)
1178                                 msi_idx++;
1179                         err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
1180                                                msi_idx, &q->fl,
1181                                                t4_ethrx_handler);
1182                         if (err)
1183                                 goto freeout;
1184                         q->rspq.idx = j;
1185                         memset(&q->stats, 0, sizeof(q->stats));
1186                 }
1187                 for (j = 0; j < pi->nqsets; j++, t++) {
1188                         err = t4_sge_alloc_eth_txq(adap, t, dev,
1189                                         netdev_get_tx_queue(dev, j),
1190                                         s->fw_evtq.cntxt_id);
1191                         if (err)
1192                                 goto freeout;
1193                 }
1194         }
1195
1196         j = s->ofldqsets / adap->params.nports; /* ofld queues per channel */
1197         for_each_ofldrxq(s, i) {
1198                 struct sge_ofld_rxq *q = &s->ofldrxq[i];
1199                 struct net_device *dev = adap->port[i / j];
1200
1201                 if (msi_idx > 0)
1202                         msi_idx++;
1203                 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev, msi_idx,
1204                                        q->fl.size ? &q->fl : NULL,
1205                                        uldrx_handler);
1206                 if (err)
1207                         goto freeout;
1208                 memset(&q->stats, 0, sizeof(q->stats));
1209                 s->ofld_rxq[i] = q->rspq.abs_id;
1210                 err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i], dev,
1211                                             s->fw_evtq.cntxt_id);
1212                 if (err)
1213                         goto freeout;
1214         }
1215
1216         for_each_rdmarxq(s, i) {
1217                 struct sge_ofld_rxq *q = &s->rdmarxq[i];
1218
1219                 if (msi_idx > 0)
1220                         msi_idx++;
1221                 err = t4_sge_alloc_rxq(adap, &q->rspq, false, adap->port[i],
1222                                        msi_idx, q->fl.size ? &q->fl : NULL,
1223                                        uldrx_handler);
1224                 if (err)
1225                         goto freeout;
1226                 memset(&q->stats, 0, sizeof(q->stats));
1227                 s->rdma_rxq[i] = q->rspq.abs_id;
1228         }
1229
1230         for_each_rdmaciq(s, i) {
1231                 struct sge_ofld_rxq *q = &s->rdmaciq[i];
1232
1233                 if (msi_idx > 0)
1234                         msi_idx++;
1235                 err = t4_sge_alloc_rxq(adap, &q->rspq, false, adap->port[i],
1236                                        msi_idx, q->fl.size ? &q->fl : NULL,
1237                                        uldrx_handler);
1238                 if (err)
1239                         goto freeout;
1240                 memset(&q->stats, 0, sizeof(q->stats));
1241                 s->rdma_ciq[i] = q->rspq.abs_id;
1242         }
1243
1244         for_each_port(adap, i) {
1245                 /*
1246                  * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't
1247                  * have RDMA queues, and that's the right value.
1248                  */
1249                 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
1250                                             s->fw_evtq.cntxt_id,
1251                                             s->rdmarxq[i].rspq.cntxt_id);
1252                 if (err)
1253                         goto freeout;
1254         }
1255
1256         t4_write_reg(adap, is_t4(adap->params.chip) ?
1257                                 MPS_TRC_RSS_CONTROL :
1258                                 MPS_T5_TRC_RSS_CONTROL,
1259                      RSSCONTROL(netdev2pinfo(adap->port[0])->tx_chan) |
1260                      QUEUENUMBER(s->ethrxq[0].rspq.abs_id));
1261         return 0;
1262 }
1263
1264 /*
1265  * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
1266  * The allocated memory is cleared.
1267  */
1268 void *t4_alloc_mem(size_t size)
1269 {
1270         void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
1271
1272         if (!p)
1273                 p = vzalloc(size);
1274         return p;
1275 }
1276
1277 /*
1278  * Free memory allocated through alloc_mem().
1279  */
1280 static void t4_free_mem(void *addr)
1281 {
1282         if (is_vmalloc_addr(addr))
1283                 vfree(addr);
1284         else
1285                 kfree(addr);
1286 }
1287
1288 /* Send a Work Request to write the filter at a specified index.  We construct
1289  * a Firmware Filter Work Request to have the work done and put the indicated
1290  * filter into "pending" mode which will prevent any further actions against
1291  * it till we get a reply from the firmware on the completion status of the
1292  * request.
1293  */
1294 static int set_filter_wr(struct adapter *adapter, int fidx)
1295 {
1296         struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1297         struct sk_buff *skb;
1298         struct fw_filter_wr *fwr;
1299         unsigned int ftid;
1300
1301         /* If the new filter requires loopback Destination MAC and/or VLAN
1302          * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
1303          * the filter.
1304          */
1305         if (f->fs.newdmac || f->fs.newvlan) {
1306                 /* allocate L2T entry for new filter */
1307                 f->l2t = t4_l2t_alloc_switching(adapter->l2t);
1308                 if (f->l2t == NULL)
1309                         return -EAGAIN;
1310                 if (t4_l2t_set_switching(adapter, f->l2t, f->fs.vlan,
1311                                         f->fs.eport, f->fs.dmac)) {
1312                         cxgb4_l2t_release(f->l2t);
1313                         f->l2t = NULL;
1314                         return -ENOMEM;
1315                 }
1316         }
1317
1318         ftid = adapter->tids.ftid_base + fidx;
1319
1320         skb = alloc_skb(sizeof(*fwr), GFP_KERNEL | __GFP_NOFAIL);
1321         fwr = (struct fw_filter_wr *)__skb_put(skb, sizeof(*fwr));
1322         memset(fwr, 0, sizeof(*fwr));
1323
1324         /* It would be nice to put most of the following in t4_hw.c but most
1325          * of the work is translating the cxgbtool ch_filter_specification
1326          * into the Work Request and the definition of that structure is
1327          * currently in cxgbtool.h which isn't appropriate to pull into the
1328          * common code.  We may eventually try to come up with a more neutral
1329          * filter specification structure but for now it's easiest to simply
1330          * put this fairly direct code in line ...
1331          */
1332         fwr->op_pkd = htonl(FW_WR_OP(FW_FILTER_WR));
1333         fwr->len16_pkd = htonl(FW_WR_LEN16(sizeof(*fwr)/16));
1334         fwr->tid_to_iq =
1335                 htonl(V_FW_FILTER_WR_TID(ftid) |
1336                       V_FW_FILTER_WR_RQTYPE(f->fs.type) |
1337                       V_FW_FILTER_WR_NOREPLY(0) |
1338                       V_FW_FILTER_WR_IQ(f->fs.iq));
1339         fwr->del_filter_to_l2tix =
1340                 htonl(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) |
1341                       V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
1342                       V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
1343                       V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) |
1344                       V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) |
1345                       V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
1346                       V_FW_FILTER_WR_DMAC(f->fs.newdmac) |
1347                       V_FW_FILTER_WR_SMAC(f->fs.newsmac) |
1348                       V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT ||
1349                                              f->fs.newvlan == VLAN_REWRITE) |
1350                       V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE ||
1351                                             f->fs.newvlan == VLAN_REWRITE) |
1352                       V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
1353                       V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
1354                       V_FW_FILTER_WR_PRIO(f->fs.prio) |
1355                       V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
1356         fwr->ethtype = htons(f->fs.val.ethtype);
1357         fwr->ethtypem = htons(f->fs.mask.ethtype);
1358         fwr->frag_to_ovlan_vldm =
1359                 (V_FW_FILTER_WR_FRAG(f->fs.val.frag) |
1360                  V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) |
1361                  V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.ivlan_vld) |
1362                  V_FW_FILTER_WR_OVLAN_VLD(f->fs.val.ovlan_vld) |
1363                  V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.ivlan_vld) |
1364                  V_FW_FILTER_WR_OVLAN_VLDM(f->fs.mask.ovlan_vld));
1365         fwr->smac_sel = 0;
1366         fwr->rx_chan_rx_rpl_iq =
1367                 htons(V_FW_FILTER_WR_RX_CHAN(0) |
1368                       V_FW_FILTER_WR_RX_RPL_IQ(adapter->sge.fw_evtq.abs_id));
1369         fwr->maci_to_matchtypem =
1370                 htonl(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
1371                       V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
1372                       V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) |
1373                       V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) |
1374                       V_FW_FILTER_WR_PORT(f->fs.val.iport) |
1375                       V_FW_FILTER_WR_PORTM(f->fs.mask.iport) |
1376                       V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) |
1377                       V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype));
1378         fwr->ptcl = f->fs.val.proto;
1379         fwr->ptclm = f->fs.mask.proto;
1380         fwr->ttyp = f->fs.val.tos;
1381         fwr->ttypm = f->fs.mask.tos;
1382         fwr->ivlan = htons(f->fs.val.ivlan);
1383         fwr->ivlanm = htons(f->fs.mask.ivlan);
1384         fwr->ovlan = htons(f->fs.val.ovlan);
1385         fwr->ovlanm = htons(f->fs.mask.ovlan);
1386         memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
1387         memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
1388         memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
1389         memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
1390         fwr->lp = htons(f->fs.val.lport);
1391         fwr->lpm = htons(f->fs.mask.lport);
1392         fwr->fp = htons(f->fs.val.fport);
1393         fwr->fpm = htons(f->fs.mask.fport);
1394         if (f->fs.newsmac)
1395                 memcpy(fwr->sma, f->fs.smac, sizeof(fwr->sma));
1396
1397         /* Mark the filter as "pending" and ship off the Filter Work Request.
1398          * When we get the Work Request Reply we'll clear the pending status.
1399          */
1400         f->pending = 1;
1401         set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3);
1402         t4_ofld_send(adapter, skb);
1403         return 0;
1404 }
1405
1406 /* Delete the filter at a specified index.
1407  */
1408 static int del_filter_wr(struct adapter *adapter, int fidx)
1409 {
1410         struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1411         struct sk_buff *skb;
1412         struct fw_filter_wr *fwr;
1413         unsigned int len, ftid;
1414
1415         len = sizeof(*fwr);
1416         ftid = adapter->tids.ftid_base + fidx;
1417
1418         skb = alloc_skb(len, GFP_KERNEL | __GFP_NOFAIL);
1419         fwr = (struct fw_filter_wr *)__skb_put(skb, len);
1420         t4_mk_filtdelwr(ftid, fwr, adapter->sge.fw_evtq.abs_id);
1421
1422         /* Mark the filter as "pending" and ship off the Filter Work Request.
1423          * When we get the Work Request Reply we'll clear the pending status.
1424          */
1425         f->pending = 1;
1426         t4_mgmt_tx(adapter, skb);
1427         return 0;
1428 }
1429
1430 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
1431                              void *accel_priv, select_queue_fallback_t fallback)
1432 {
1433         int txq;
1434
1435 #ifdef CONFIG_CHELSIO_T4_DCB
1436         /* If a Data Center Bridging has been successfully negotiated on this
1437          * link then we'll use the skb's priority to map it to a TX Queue.
1438          * The skb's priority is determined via the VLAN Tag Priority Code
1439          * Point field.
1440          */
1441         if (cxgb4_dcb_enabled(dev)) {
1442                 u16 vlan_tci;
1443                 int err;
1444
1445                 err = vlan_get_tag(skb, &vlan_tci);
1446                 if (unlikely(err)) {
1447                         if (net_ratelimit())
1448                                 netdev_warn(dev,
1449                                             "TX Packet without VLAN Tag on DCB Link\n");
1450                         txq = 0;
1451                 } else {
1452                         txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1453                 }
1454                 return txq;
1455         }
1456 #endif /* CONFIG_CHELSIO_T4_DCB */
1457
1458         if (select_queue) {
1459                 txq = (skb_rx_queue_recorded(skb)
1460                         ? skb_get_rx_queue(skb)
1461                         : smp_processor_id());
1462
1463                 while (unlikely(txq >= dev->real_num_tx_queues))
1464                         txq -= dev->real_num_tx_queues;
1465
1466                 return txq;
1467         }
1468
1469         return fallback(dev, skb) % dev->real_num_tx_queues;
1470 }
1471
1472 static inline int is_offload(const struct adapter *adap)
1473 {
1474         return adap->params.offload;
1475 }
1476
1477 /*
1478  * Implementation of ethtool operations.
1479  */
1480
1481 static u32 get_msglevel(struct net_device *dev)
1482 {
1483         return netdev2adap(dev)->msg_enable;
1484 }
1485
1486 static void set_msglevel(struct net_device *dev, u32 val)
1487 {
1488         netdev2adap(dev)->msg_enable = val;
1489 }
1490
1491 static char stats_strings[][ETH_GSTRING_LEN] = {
1492         "TxOctetsOK         ",
1493         "TxFramesOK         ",
1494         "TxBroadcastFrames  ",
1495         "TxMulticastFrames  ",
1496         "TxUnicastFrames    ",
1497         "TxErrorFrames      ",
1498
1499         "TxFrames64         ",
1500         "TxFrames65To127    ",
1501         "TxFrames128To255   ",
1502         "TxFrames256To511   ",
1503         "TxFrames512To1023  ",
1504         "TxFrames1024To1518 ",
1505         "TxFrames1519ToMax  ",
1506
1507         "TxFramesDropped    ",
1508         "TxPauseFrames      ",
1509         "TxPPP0Frames       ",
1510         "TxPPP1Frames       ",
1511         "TxPPP2Frames       ",
1512         "TxPPP3Frames       ",
1513         "TxPPP4Frames       ",
1514         "TxPPP5Frames       ",
1515         "TxPPP6Frames       ",
1516         "TxPPP7Frames       ",
1517
1518         "RxOctetsOK         ",
1519         "RxFramesOK         ",
1520         "RxBroadcastFrames  ",
1521         "RxMulticastFrames  ",
1522         "RxUnicastFrames    ",
1523
1524         "RxFramesTooLong    ",
1525         "RxJabberErrors     ",
1526         "RxFCSErrors        ",
1527         "RxLengthErrors     ",
1528         "RxSymbolErrors     ",
1529         "RxRuntFrames       ",
1530
1531         "RxFrames64         ",
1532         "RxFrames65To127    ",
1533         "RxFrames128To255   ",
1534         "RxFrames256To511   ",
1535         "RxFrames512To1023  ",
1536         "RxFrames1024To1518 ",
1537         "RxFrames1519ToMax  ",
1538
1539         "RxPauseFrames      ",
1540         "RxPPP0Frames       ",
1541         "RxPPP1Frames       ",
1542         "RxPPP2Frames       ",
1543         "RxPPP3Frames       ",
1544         "RxPPP4Frames       ",
1545         "RxPPP5Frames       ",
1546         "RxPPP6Frames       ",
1547         "RxPPP7Frames       ",
1548
1549         "RxBG0FramesDropped ",
1550         "RxBG1FramesDropped ",
1551         "RxBG2FramesDropped ",
1552         "RxBG3FramesDropped ",
1553         "RxBG0FramesTrunc   ",
1554         "RxBG1FramesTrunc   ",
1555         "RxBG2FramesTrunc   ",
1556         "RxBG3FramesTrunc   ",
1557
1558         "TSO                ",
1559         "TxCsumOffload      ",
1560         "RxCsumGood         ",
1561         "VLANextractions    ",
1562         "VLANinsertions     ",
1563         "GROpackets         ",
1564         "GROmerged          ",
1565         "WriteCoalSuccess   ",
1566         "WriteCoalFail      ",
1567 };
1568
1569 static int get_sset_count(struct net_device *dev, int sset)
1570 {
1571         switch (sset) {
1572         case ETH_SS_STATS:
1573                 return ARRAY_SIZE(stats_strings);
1574         default:
1575                 return -EOPNOTSUPP;
1576         }
1577 }
1578
1579 #define T4_REGMAP_SIZE (160 * 1024)
1580 #define T5_REGMAP_SIZE (332 * 1024)
1581
1582 static int get_regs_len(struct net_device *dev)
1583 {
1584         struct adapter *adap = netdev2adap(dev);
1585         if (is_t4(adap->params.chip))
1586                 return T4_REGMAP_SIZE;
1587         else
1588                 return T5_REGMAP_SIZE;
1589 }
1590
1591 static int get_eeprom_len(struct net_device *dev)
1592 {
1593         return EEPROMSIZE;
1594 }
1595
1596 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1597 {
1598         struct adapter *adapter = netdev2adap(dev);
1599
1600         strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1601         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1602         strlcpy(info->bus_info, pci_name(adapter->pdev),
1603                 sizeof(info->bus_info));
1604
1605         if (adapter->params.fw_vers)
1606                 snprintf(info->fw_version, sizeof(info->fw_version),
1607                         "%u.%u.%u.%u, TP %u.%u.%u.%u",
1608                         FW_HDR_FW_VER_MAJOR_GET(adapter->params.fw_vers),
1609                         FW_HDR_FW_VER_MINOR_GET(adapter->params.fw_vers),
1610                         FW_HDR_FW_VER_MICRO_GET(adapter->params.fw_vers),
1611                         FW_HDR_FW_VER_BUILD_GET(adapter->params.fw_vers),
1612                         FW_HDR_FW_VER_MAJOR_GET(adapter->params.tp_vers),
1613                         FW_HDR_FW_VER_MINOR_GET(adapter->params.tp_vers),
1614                         FW_HDR_FW_VER_MICRO_GET(adapter->params.tp_vers),
1615                         FW_HDR_FW_VER_BUILD_GET(adapter->params.tp_vers));
1616 }
1617
1618 static void get_strings(struct net_device *dev, u32 stringset, u8 *data)
1619 {
1620         if (stringset == ETH_SS_STATS)
1621                 memcpy(data, stats_strings, sizeof(stats_strings));
1622 }
1623
1624 /*
1625  * port stats maintained per queue of the port.  They should be in the same
1626  * order as in stats_strings above.
1627  */
1628 struct queue_port_stats {
1629         u64 tso;
1630         u64 tx_csum;
1631         u64 rx_csum;
1632         u64 vlan_ex;
1633         u64 vlan_ins;
1634         u64 gro_pkts;
1635         u64 gro_merged;
1636 };
1637
1638 static void collect_sge_port_stats(const struct adapter *adap,
1639                 const struct port_info *p, struct queue_port_stats *s)
1640 {
1641         int i;
1642         const struct sge_eth_txq *tx = &adap->sge.ethtxq[p->first_qset];
1643         const struct sge_eth_rxq *rx = &adap->sge.ethrxq[p->first_qset];
1644
1645         memset(s, 0, sizeof(*s));
1646         for (i = 0; i < p->nqsets; i++, rx++, tx++) {
1647                 s->tso += tx->tso;
1648                 s->tx_csum += tx->tx_cso;
1649                 s->rx_csum += rx->stats.rx_cso;
1650                 s->vlan_ex += rx->stats.vlan_ex;
1651                 s->vlan_ins += tx->vlan_ins;
1652                 s->gro_pkts += rx->stats.lro_pkts;
1653                 s->gro_merged += rx->stats.lro_merged;
1654         }
1655 }
1656
1657 static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
1658                       u64 *data)
1659 {
1660         struct port_info *pi = netdev_priv(dev);
1661         struct adapter *adapter = pi->adapter;
1662         u32 val1, val2;
1663
1664         t4_get_port_stats(adapter, pi->tx_chan, (struct port_stats *)data);
1665
1666         data += sizeof(struct port_stats) / sizeof(u64);
1667         collect_sge_port_stats(adapter, pi, (struct queue_port_stats *)data);
1668         data += sizeof(struct queue_port_stats) / sizeof(u64);
1669         if (!is_t4(adapter->params.chip)) {
1670                 t4_write_reg(adapter, SGE_STAT_CFG, STATSOURCE_T5(7));
1671                 val1 = t4_read_reg(adapter, SGE_STAT_TOTAL);
1672                 val2 = t4_read_reg(adapter, SGE_STAT_MATCH);
1673                 *data = val1 - val2;
1674                 data++;
1675                 *data = val2;
1676                 data++;
1677         } else {
1678                 memset(data, 0, 2 * sizeof(u64));
1679                 *data += 2;
1680         }
1681 }
1682
1683 /*
1684  * Return a version number to identify the type of adapter.  The scheme is:
1685  * - bits 0..9: chip version
1686  * - bits 10..15: chip revision
1687  * - bits 16..23: register dump version
1688  */
1689 static inline unsigned int mk_adap_vers(const struct adapter *ap)
1690 {
1691         return CHELSIO_CHIP_VERSION(ap->params.chip) |
1692                 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1693 }
1694
1695 static void reg_block_dump(struct adapter *ap, void *buf, unsigned int start,
1696                            unsigned int end)
1697 {
1698         u32 *p = buf + start;
1699
1700         for ( ; start <= end; start += sizeof(u32))
1701                 *p++ = t4_read_reg(ap, start);
1702 }
1703
1704 static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
1705                      void *buf)
1706 {
1707         static const unsigned int t4_reg_ranges[] = {
1708                 0x1008, 0x1108,
1709                 0x1180, 0x11b4,
1710                 0x11fc, 0x123c,
1711                 0x1300, 0x173c,
1712                 0x1800, 0x18fc,
1713                 0x3000, 0x30d8,
1714                 0x30e0, 0x5924,
1715                 0x5960, 0x59d4,
1716                 0x5a00, 0x5af8,
1717                 0x6000, 0x6098,
1718                 0x6100, 0x6150,
1719                 0x6200, 0x6208,
1720                 0x6240, 0x6248,
1721                 0x6280, 0x6338,
1722                 0x6370, 0x638c,
1723                 0x6400, 0x643c,
1724                 0x6500, 0x6524,
1725                 0x6a00, 0x6a38,
1726                 0x6a60, 0x6a78,
1727                 0x6b00, 0x6b84,
1728                 0x6bf0, 0x6c84,
1729                 0x6cf0, 0x6d84,
1730                 0x6df0, 0x6e84,
1731                 0x6ef0, 0x6f84,
1732                 0x6ff0, 0x7084,
1733                 0x70f0, 0x7184,
1734                 0x71f0, 0x7284,
1735                 0x72f0, 0x7384,
1736                 0x73f0, 0x7450,
1737                 0x7500, 0x7530,
1738                 0x7600, 0x761c,
1739                 0x7680, 0x76cc,
1740                 0x7700, 0x7798,
1741                 0x77c0, 0x77fc,
1742                 0x7900, 0x79fc,
1743                 0x7b00, 0x7c38,
1744                 0x7d00, 0x7efc,
1745                 0x8dc0, 0x8e1c,
1746                 0x8e30, 0x8e78,
1747                 0x8ea0, 0x8f6c,
1748                 0x8fc0, 0x9074,
1749                 0x90fc, 0x90fc,
1750                 0x9400, 0x9458,
1751                 0x9600, 0x96bc,
1752                 0x9800, 0x9808,
1753                 0x9820, 0x983c,
1754                 0x9850, 0x9864,
1755                 0x9c00, 0x9c6c,
1756                 0x9c80, 0x9cec,
1757                 0x9d00, 0x9d6c,
1758                 0x9d80, 0x9dec,
1759                 0x9e00, 0x9e6c,
1760                 0x9e80, 0x9eec,
1761                 0x9f00, 0x9f6c,
1762                 0x9f80, 0x9fec,
1763                 0xd004, 0xd03c,
1764                 0xdfc0, 0xdfe0,
1765                 0xe000, 0xea7c,
1766                 0xf000, 0x11110,
1767                 0x11118, 0x11190,
1768                 0x19040, 0x1906c,
1769                 0x19078, 0x19080,
1770                 0x1908c, 0x19124,
1771                 0x19150, 0x191b0,
1772                 0x191d0, 0x191e8,
1773                 0x19238, 0x1924c,
1774                 0x193f8, 0x19474,
1775                 0x19490, 0x194f8,
1776                 0x19800, 0x19f30,
1777                 0x1a000, 0x1a06c,
1778                 0x1a0b0, 0x1a120,
1779                 0x1a128, 0x1a138,
1780                 0x1a190, 0x1a1c4,
1781                 0x1a1fc, 0x1a1fc,
1782                 0x1e040, 0x1e04c,
1783                 0x1e284, 0x1e28c,
1784                 0x1e2c0, 0x1e2c0,
1785                 0x1e2e0, 0x1e2e0,
1786                 0x1e300, 0x1e384,
1787                 0x1e3c0, 0x1e3c8,
1788                 0x1e440, 0x1e44c,
1789                 0x1e684, 0x1e68c,
1790                 0x1e6c0, 0x1e6c0,
1791                 0x1e6e0, 0x1e6e0,
1792                 0x1e700, 0x1e784,
1793                 0x1e7c0, 0x1e7c8,
1794                 0x1e840, 0x1e84c,
1795                 0x1ea84, 0x1ea8c,
1796                 0x1eac0, 0x1eac0,
1797                 0x1eae0, 0x1eae0,
1798                 0x1eb00, 0x1eb84,
1799                 0x1ebc0, 0x1ebc8,
1800                 0x1ec40, 0x1ec4c,
1801                 0x1ee84, 0x1ee8c,
1802                 0x1eec0, 0x1eec0,
1803                 0x1eee0, 0x1eee0,
1804                 0x1ef00, 0x1ef84,
1805                 0x1efc0, 0x1efc8,
1806                 0x1f040, 0x1f04c,
1807                 0x1f284, 0x1f28c,
1808                 0x1f2c0, 0x1f2c0,
1809                 0x1f2e0, 0x1f2e0,
1810                 0x1f300, 0x1f384,
1811                 0x1f3c0, 0x1f3c8,
1812                 0x1f440, 0x1f44c,
1813                 0x1f684, 0x1f68c,
1814                 0x1f6c0, 0x1f6c0,
1815                 0x1f6e0, 0x1f6e0,
1816                 0x1f700, 0x1f784,
1817                 0x1f7c0, 0x1f7c8,
1818                 0x1f840, 0x1f84c,
1819                 0x1fa84, 0x1fa8c,
1820                 0x1fac0, 0x1fac0,
1821                 0x1fae0, 0x1fae0,
1822                 0x1fb00, 0x1fb84,
1823                 0x1fbc0, 0x1fbc8,
1824                 0x1fc40, 0x1fc4c,
1825                 0x1fe84, 0x1fe8c,
1826                 0x1fec0, 0x1fec0,
1827                 0x1fee0, 0x1fee0,
1828                 0x1ff00, 0x1ff84,
1829                 0x1ffc0, 0x1ffc8,
1830                 0x20000, 0x2002c,
1831                 0x20100, 0x2013c,
1832                 0x20190, 0x201c8,
1833                 0x20200, 0x20318,
1834                 0x20400, 0x20528,
1835                 0x20540, 0x20614,
1836                 0x21000, 0x21040,
1837                 0x2104c, 0x21060,
1838                 0x210c0, 0x210ec,
1839                 0x21200, 0x21268,
1840                 0x21270, 0x21284,
1841                 0x212fc, 0x21388,
1842                 0x21400, 0x21404,
1843                 0x21500, 0x21518,
1844                 0x2152c, 0x2153c,
1845                 0x21550, 0x21554,
1846                 0x21600, 0x21600,
1847                 0x21608, 0x21628,
1848                 0x21630, 0x2163c,
1849                 0x21700, 0x2171c,
1850                 0x21780, 0x2178c,
1851                 0x21800, 0x21c38,
1852                 0x21c80, 0x21d7c,
1853                 0x21e00, 0x21e04,
1854                 0x22000, 0x2202c,
1855                 0x22100, 0x2213c,
1856                 0x22190, 0x221c8,
1857                 0x22200, 0x22318,
1858                 0x22400, 0x22528,
1859                 0x22540, 0x22614,
1860                 0x23000, 0x23040,
1861                 0x2304c, 0x23060,
1862                 0x230c0, 0x230ec,
1863                 0x23200, 0x23268,
1864                 0x23270, 0x23284,
1865                 0x232fc, 0x23388,
1866                 0x23400, 0x23404,
1867                 0x23500, 0x23518,
1868                 0x2352c, 0x2353c,
1869                 0x23550, 0x23554,
1870                 0x23600, 0x23600,
1871                 0x23608, 0x23628,
1872                 0x23630, 0x2363c,
1873                 0x23700, 0x2371c,
1874                 0x23780, 0x2378c,
1875                 0x23800, 0x23c38,
1876                 0x23c80, 0x23d7c,
1877                 0x23e00, 0x23e04,
1878                 0x24000, 0x2402c,
1879                 0x24100, 0x2413c,
1880                 0x24190, 0x241c8,
1881                 0x24200, 0x24318,
1882                 0x24400, 0x24528,
1883                 0x24540, 0x24614,
1884                 0x25000, 0x25040,
1885                 0x2504c, 0x25060,
1886                 0x250c0, 0x250ec,
1887                 0x25200, 0x25268,
1888                 0x25270, 0x25284,
1889                 0x252fc, 0x25388,
1890                 0x25400, 0x25404,
1891                 0x25500, 0x25518,
1892                 0x2552c, 0x2553c,
1893                 0x25550, 0x25554,
1894                 0x25600, 0x25600,
1895                 0x25608, 0x25628,
1896                 0x25630, 0x2563c,
1897                 0x25700, 0x2571c,
1898                 0x25780, 0x2578c,
1899                 0x25800, 0x25c38,
1900                 0x25c80, 0x25d7c,
1901                 0x25e00, 0x25e04,
1902                 0x26000, 0x2602c,
1903                 0x26100, 0x2613c,
1904                 0x26190, 0x261c8,
1905                 0x26200, 0x26318,
1906                 0x26400, 0x26528,
1907                 0x26540, 0x26614,
1908                 0x27000, 0x27040,
1909                 0x2704c, 0x27060,
1910                 0x270c0, 0x270ec,
1911                 0x27200, 0x27268,
1912                 0x27270, 0x27284,
1913                 0x272fc, 0x27388,
1914                 0x27400, 0x27404,
1915                 0x27500, 0x27518,
1916                 0x2752c, 0x2753c,
1917                 0x27550, 0x27554,
1918                 0x27600, 0x27600,
1919                 0x27608, 0x27628,
1920                 0x27630, 0x2763c,
1921                 0x27700, 0x2771c,
1922                 0x27780, 0x2778c,
1923                 0x27800, 0x27c38,
1924                 0x27c80, 0x27d7c,
1925                 0x27e00, 0x27e04
1926         };
1927
1928         static const unsigned int t5_reg_ranges[] = {
1929                 0x1008, 0x1148,
1930                 0x1180, 0x11b4,
1931                 0x11fc, 0x123c,
1932                 0x1280, 0x173c,
1933                 0x1800, 0x18fc,
1934                 0x3000, 0x3028,
1935                 0x3060, 0x30d8,
1936                 0x30e0, 0x30fc,
1937                 0x3140, 0x357c,
1938                 0x35a8, 0x35cc,
1939                 0x35ec, 0x35ec,
1940                 0x3600, 0x5624,
1941                 0x56cc, 0x575c,
1942                 0x580c, 0x5814,
1943                 0x5890, 0x58bc,
1944                 0x5940, 0x59dc,
1945                 0x59fc, 0x5a18,
1946                 0x5a60, 0x5a9c,
1947                 0x5b9c, 0x5bfc,
1948                 0x6000, 0x6040,
1949                 0x6058, 0x614c,
1950                 0x7700, 0x7798,
1951                 0x77c0, 0x78fc,
1952                 0x7b00, 0x7c54,
1953                 0x7d00, 0x7efc,
1954                 0x8dc0, 0x8de0,
1955                 0x8df8, 0x8e84,
1956                 0x8ea0, 0x8f84,
1957                 0x8fc0, 0x90f8,
1958                 0x9400, 0x9470,
1959                 0x9600, 0x96f4,
1960                 0x9800, 0x9808,
1961                 0x9820, 0x983c,
1962                 0x9850, 0x9864,
1963                 0x9c00, 0x9c6c,
1964                 0x9c80, 0x9cec,
1965                 0x9d00, 0x9d6c,
1966                 0x9d80, 0x9dec,
1967                 0x9e00, 0x9e6c,
1968                 0x9e80, 0x9eec,
1969                 0x9f00, 0x9f6c,
1970                 0x9f80, 0xa020,
1971                 0xd004, 0xd03c,
1972                 0xdfc0, 0xdfe0,
1973                 0xe000, 0x11088,
1974                 0x1109c, 0x11110,
1975                 0x11118, 0x1117c,
1976                 0x11190, 0x11204,
1977                 0x19040, 0x1906c,
1978                 0x19078, 0x19080,
1979                 0x1908c, 0x19124,
1980                 0x19150, 0x191b0,
1981                 0x191d0, 0x191e8,
1982                 0x19238, 0x19290,
1983                 0x193f8, 0x19474,
1984                 0x19490, 0x194cc,
1985                 0x194f0, 0x194f8,
1986                 0x19c00, 0x19c60,
1987                 0x19c94, 0x19e10,
1988                 0x19e50, 0x19f34,
1989                 0x19f40, 0x19f50,
1990                 0x19f90, 0x19fe4,
1991                 0x1a000, 0x1a06c,
1992                 0x1a0b0, 0x1a120,
1993                 0x1a128, 0x1a138,
1994                 0x1a190, 0x1a1c4,
1995                 0x1a1fc, 0x1a1fc,
1996                 0x1e008, 0x1e00c,
1997                 0x1e040, 0x1e04c,
1998                 0x1e284, 0x1e290,
1999                 0x1e2c0, 0x1e2c0,
2000                 0x1e2e0, 0x1e2e0,
2001                 0x1e300, 0x1e384,
2002                 0x1e3c0, 0x1e3c8,
2003                 0x1e408, 0x1e40c,
2004                 0x1e440, 0x1e44c,
2005                 0x1e684, 0x1e690,
2006                 0x1e6c0, 0x1e6c0,
2007                 0x1e6e0, 0x1e6e0,
2008                 0x1e700, 0x1e784,
2009                 0x1e7c0, 0x1e7c8,
2010                 0x1e808, 0x1e80c,
2011                 0x1e840, 0x1e84c,
2012                 0x1ea84, 0x1ea90,
2013                 0x1eac0, 0x1eac0,
2014                 0x1eae0, 0x1eae0,
2015                 0x1eb00, 0x1eb84,
2016                 0x1ebc0, 0x1ebc8,
2017                 0x1ec08, 0x1ec0c,
2018                 0x1ec40, 0x1ec4c,
2019                 0x1ee84, 0x1ee90,
2020                 0x1eec0, 0x1eec0,
2021                 0x1eee0, 0x1eee0,
2022                 0x1ef00, 0x1ef84,
2023                 0x1efc0, 0x1efc8,
2024                 0x1f008, 0x1f00c,
2025                 0x1f040, 0x1f04c,
2026                 0x1f284, 0x1f290,
2027                 0x1f2c0, 0x1f2c0,
2028                 0x1f2e0, 0x1f2e0,
2029                 0x1f300, 0x1f384,
2030                 0x1f3c0, 0x1f3c8,
2031                 0x1f408, 0x1f40c,
2032                 0x1f440, 0x1f44c,
2033                 0x1f684, 0x1f690,
2034                 0x1f6c0, 0x1f6c0,
2035                 0x1f6e0, 0x1f6e0,
2036                 0x1f700, 0x1f784,
2037                 0x1f7c0, 0x1f7c8,
2038                 0x1f808, 0x1f80c,
2039                 0x1f840, 0x1f84c,
2040                 0x1fa84, 0x1fa90,
2041                 0x1fac0, 0x1fac0,
2042                 0x1fae0, 0x1fae0,
2043                 0x1fb00, 0x1fb84,
2044                 0x1fbc0, 0x1fbc8,
2045                 0x1fc08, 0x1fc0c,
2046                 0x1fc40, 0x1fc4c,
2047                 0x1fe84, 0x1fe90,
2048                 0x1fec0, 0x1fec0,
2049                 0x1fee0, 0x1fee0,
2050                 0x1ff00, 0x1ff84,
2051                 0x1ffc0, 0x1ffc8,
2052                 0x30000, 0x30030,
2053                 0x30100, 0x30144,
2054                 0x30190, 0x301d0,
2055                 0x30200, 0x30318,
2056                 0x30400, 0x3052c,
2057                 0x30540, 0x3061c,
2058                 0x30800, 0x30834,
2059                 0x308c0, 0x30908,
2060                 0x30910, 0x309ac,
2061                 0x30a00, 0x30a04,
2062                 0x30a0c, 0x30a2c,
2063                 0x30a44, 0x30a50,
2064                 0x30a74, 0x30c24,
2065                 0x30d08, 0x30d14,
2066                 0x30d1c, 0x30d20,
2067                 0x30d3c, 0x30d50,
2068                 0x31200, 0x3120c,
2069                 0x31220, 0x31220,
2070                 0x31240, 0x31240,
2071                 0x31600, 0x31600,
2072                 0x31608, 0x3160c,
2073                 0x31a00, 0x31a1c,
2074                 0x31e04, 0x31e20,
2075                 0x31e38, 0x31e3c,
2076                 0x31e80, 0x31e80,
2077                 0x31e88, 0x31ea8,
2078                 0x31eb0, 0x31eb4,
2079                 0x31ec8, 0x31ed4,
2080                 0x31fb8, 0x32004,
2081                 0x32208, 0x3223c,
2082                 0x32600, 0x32630,
2083                 0x32a00, 0x32abc,
2084                 0x32b00, 0x32b70,
2085                 0x33000, 0x33048,
2086                 0x33060, 0x3309c,
2087                 0x330f0, 0x33148,
2088                 0x33160, 0x3319c,
2089                 0x331f0, 0x332e4,
2090                 0x332f8, 0x333e4,
2091                 0x333f8, 0x33448,
2092                 0x33460, 0x3349c,
2093                 0x334f0, 0x33548,
2094                 0x33560, 0x3359c,
2095                 0x335f0, 0x336e4,
2096                 0x336f8, 0x337e4,
2097                 0x337f8, 0x337fc,
2098                 0x33814, 0x33814,
2099                 0x3382c, 0x3382c,
2100                 0x33880, 0x3388c,
2101                 0x338e8, 0x338ec,
2102                 0x33900, 0x33948,
2103                 0x33960, 0x3399c,
2104                 0x339f0, 0x33ae4,
2105                 0x33af8, 0x33b10,
2106                 0x33b28, 0x33b28,
2107                 0x33b3c, 0x33b50,
2108                 0x33bf0, 0x33c10,
2109                 0x33c28, 0x33c28,
2110                 0x33c3c, 0x33c50,
2111                 0x33cf0, 0x33cfc,
2112                 0x34000, 0x34030,
2113                 0x34100, 0x34144,
2114                 0x34190, 0x341d0,
2115                 0x34200, 0x34318,
2116                 0x34400, 0x3452c,
2117                 0x34540, 0x3461c,
2118                 0x34800, 0x34834,
2119                 0x348c0, 0x34908,
2120                 0x34910, 0x349ac,
2121                 0x34a00, 0x34a04,
2122                 0x34a0c, 0x34a2c,
2123                 0x34a44, 0x34a50,
2124                 0x34a74, 0x34c24,
2125                 0x34d08, 0x34d14,
2126                 0x34d1c, 0x34d20,
2127                 0x34d3c, 0x34d50,
2128                 0x35200, 0x3520c,
2129                 0x35220, 0x35220,
2130                 0x35240, 0x35240,
2131                 0x35600, 0x35600,
2132                 0x35608, 0x3560c,
2133                 0x35a00, 0x35a1c,
2134                 0x35e04, 0x35e20,
2135                 0x35e38, 0x35e3c,
2136                 0x35e80, 0x35e80,
2137                 0x35e88, 0x35ea8,
2138                 0x35eb0, 0x35eb4,
2139                 0x35ec8, 0x35ed4,
2140                 0x35fb8, 0x36004,
2141                 0x36208, 0x3623c,
2142                 0x36600, 0x36630,
2143                 0x36a00, 0x36abc,
2144                 0x36b00, 0x36b70,
2145                 0x37000, 0x37048,
2146                 0x37060, 0x3709c,
2147                 0x370f0, 0x37148,
2148                 0x37160, 0x3719c,
2149                 0x371f0, 0x372e4,
2150                 0x372f8, 0x373e4,
2151                 0x373f8, 0x37448,
2152                 0x37460, 0x3749c,
2153                 0x374f0, 0x37548,
2154                 0x37560, 0x3759c,
2155                 0x375f0, 0x376e4,
2156                 0x376f8, 0x377e4,
2157                 0x377f8, 0x377fc,
2158                 0x37814, 0x37814,
2159                 0x3782c, 0x3782c,
2160                 0x37880, 0x3788c,
2161                 0x378e8, 0x378ec,
2162                 0x37900, 0x37948,
2163                 0x37960, 0x3799c,
2164                 0x379f0, 0x37ae4,
2165                 0x37af8, 0x37b10,
2166                 0x37b28, 0x37b28,
2167                 0x37b3c, 0x37b50,
2168                 0x37bf0, 0x37c10,
2169                 0x37c28, 0x37c28,
2170                 0x37c3c, 0x37c50,
2171                 0x37cf0, 0x37cfc,
2172                 0x38000, 0x38030,
2173                 0x38100, 0x38144,
2174                 0x38190, 0x381d0,
2175                 0x38200, 0x38318,
2176                 0x38400, 0x3852c,
2177                 0x38540, 0x3861c,
2178                 0x38800, 0x38834,
2179                 0x388c0, 0x38908,
2180                 0x38910, 0x389ac,
2181                 0x38a00, 0x38a04,
2182                 0x38a0c, 0x38a2c,
2183                 0x38a44, 0x38a50,
2184                 0x38a74, 0x38c24,
2185                 0x38d08, 0x38d14,
2186                 0x38d1c, 0x38d20,
2187                 0x38d3c, 0x38d50,
2188                 0x39200, 0x3920c,
2189                 0x39220, 0x39220,
2190                 0x39240, 0x39240,
2191                 0x39600, 0x39600,
2192                 0x39608, 0x3960c,
2193                 0x39a00, 0x39a1c,
2194                 0x39e04, 0x39e20,
2195                 0x39e38, 0x39e3c,
2196                 0x39e80, 0x39e80,
2197                 0x39e88, 0x39ea8,
2198                 0x39eb0, 0x39eb4,
2199                 0x39ec8, 0x39ed4,
2200                 0x39fb8, 0x3a004,
2201                 0x3a208, 0x3a23c,
2202                 0x3a600, 0x3a630,
2203                 0x3aa00, 0x3aabc,
2204                 0x3ab00, 0x3ab70,
2205                 0x3b000, 0x3b048,
2206                 0x3b060, 0x3b09c,
2207                 0x3b0f0, 0x3b148,
2208                 0x3b160, 0x3b19c,
2209                 0x3b1f0, 0x3b2e4,
2210                 0x3b2f8, 0x3b3e4,
2211                 0x3b3f8, 0x3b448,
2212                 0x3b460, 0x3b49c,
2213                 0x3b4f0, 0x3b548,
2214                 0x3b560, 0x3b59c,
2215                 0x3b5f0, 0x3b6e4,
2216                 0x3b6f8, 0x3b7e4,
2217                 0x3b7f8, 0x3b7fc,
2218                 0x3b814, 0x3b814,
2219                 0x3b82c, 0x3b82c,
2220                 0x3b880, 0x3b88c,
2221                 0x3b8e8, 0x3b8ec,
2222                 0x3b900, 0x3b948,
2223                 0x3b960, 0x3b99c,
2224                 0x3b9f0, 0x3bae4,
2225                 0x3baf8, 0x3bb10,
2226                 0x3bb28, 0x3bb28,
2227                 0x3bb3c, 0x3bb50,
2228                 0x3bbf0, 0x3bc10,
2229                 0x3bc28, 0x3bc28,
2230                 0x3bc3c, 0x3bc50,
2231                 0x3bcf0, 0x3bcfc,
2232                 0x3c000, 0x3c030,
2233                 0x3c100, 0x3c144,
2234                 0x3c190, 0x3c1d0,
2235                 0x3c200, 0x3c318,
2236                 0x3c400, 0x3c52c,
2237                 0x3c540, 0x3c61c,
2238                 0x3c800, 0x3c834,
2239                 0x3c8c0, 0x3c908,
2240                 0x3c910, 0x3c9ac,
2241                 0x3ca00, 0x3ca04,
2242                 0x3ca0c, 0x3ca2c,
2243                 0x3ca44, 0x3ca50,
2244                 0x3ca74, 0x3cc24,
2245                 0x3cd08, 0x3cd14,
2246                 0x3cd1c, 0x3cd20,
2247                 0x3cd3c, 0x3cd50,
2248                 0x3d200, 0x3d20c,
2249                 0x3d220, 0x3d220,
2250                 0x3d240, 0x3d240,
2251                 0x3d600, 0x3d600,
2252                 0x3d608, 0x3d60c,
2253                 0x3da00, 0x3da1c,
2254                 0x3de04, 0x3de20,
2255                 0x3de38, 0x3de3c,
2256                 0x3de80, 0x3de80,
2257                 0x3de88, 0x3dea8,
2258                 0x3deb0, 0x3deb4,
2259                 0x3dec8, 0x3ded4,
2260                 0x3dfb8, 0x3e004,
2261                 0x3e208, 0x3e23c,
2262                 0x3e600, 0x3e630,
2263                 0x3ea00, 0x3eabc,
2264                 0x3eb00, 0x3eb70,
2265                 0x3f000, 0x3f048,
2266                 0x3f060, 0x3f09c,
2267                 0x3f0f0, 0x3f148,
2268                 0x3f160, 0x3f19c,
2269                 0x3f1f0, 0x3f2e4,
2270                 0x3f2f8, 0x3f3e4,
2271                 0x3f3f8, 0x3f448,
2272                 0x3f460, 0x3f49c,
2273                 0x3f4f0, 0x3f548,
2274                 0x3f560, 0x3f59c,
2275                 0x3f5f0, 0x3f6e4,
2276                 0x3f6f8, 0x3f7e4,
2277                 0x3f7f8, 0x3f7fc,
2278                 0x3f814, 0x3f814,
2279                 0x3f82c, 0x3f82c,
2280                 0x3f880, 0x3f88c,
2281                 0x3f8e8, 0x3f8ec,
2282                 0x3f900, 0x3f948,
2283                 0x3f960, 0x3f99c,
2284                 0x3f9f0, 0x3fae4,
2285                 0x3faf8, 0x3fb10,
2286                 0x3fb28, 0x3fb28,
2287                 0x3fb3c, 0x3fb50,
2288                 0x3fbf0, 0x3fc10,
2289                 0x3fc28, 0x3fc28,
2290                 0x3fc3c, 0x3fc50,
2291                 0x3fcf0, 0x3fcfc,
2292                 0x40000, 0x4000c,
2293                 0x40040, 0x40068,
2294                 0x40080, 0x40144,
2295                 0x40180, 0x4018c,
2296                 0x40200, 0x40298,
2297                 0x402ac, 0x4033c,
2298                 0x403f8, 0x403fc,
2299                 0x41304, 0x413c4,
2300                 0x41400, 0x4141c,
2301                 0x41480, 0x414d0,
2302                 0x44000, 0x44078,
2303                 0x440c0, 0x44278,
2304                 0x442c0, 0x44478,
2305                 0x444c0, 0x44678,
2306                 0x446c0, 0x44878,
2307                 0x448c0, 0x449fc,
2308                 0x45000, 0x45068,
2309                 0x45080, 0x45084,
2310                 0x450a0, 0x450b0,
2311                 0x45200, 0x45268,
2312                 0x45280, 0x45284,
2313                 0x452a0, 0x452b0,
2314                 0x460c0, 0x460e4,
2315                 0x47000, 0x4708c,
2316                 0x47200, 0x47250,
2317                 0x47400, 0x47420,
2318                 0x47600, 0x47618,
2319                 0x47800, 0x47814,
2320                 0x48000, 0x4800c,
2321                 0x48040, 0x48068,
2322                 0x48080, 0x48144,
2323                 0x48180, 0x4818c,
2324                 0x48200, 0x48298,
2325                 0x482ac, 0x4833c,
2326                 0x483f8, 0x483fc,
2327                 0x49304, 0x493c4,
2328                 0x49400, 0x4941c,
2329                 0x49480, 0x494d0,
2330                 0x4c000, 0x4c078,
2331                 0x4c0c0, 0x4c278,
2332                 0x4c2c0, 0x4c478,
2333                 0x4c4c0, 0x4c678,
2334                 0x4c6c0, 0x4c878,
2335                 0x4c8c0, 0x4c9fc,
2336                 0x4d000, 0x4d068,
2337                 0x4d080, 0x4d084,
2338                 0x4d0a0, 0x4d0b0,
2339                 0x4d200, 0x4d268,
2340                 0x4d280, 0x4d284,
2341                 0x4d2a0, 0x4d2b0,
2342                 0x4e0c0, 0x4e0e4,
2343                 0x4f000, 0x4f08c,
2344                 0x4f200, 0x4f250,
2345                 0x4f400, 0x4f420,
2346                 0x4f600, 0x4f618,
2347                 0x4f800, 0x4f814,
2348                 0x50000, 0x500cc,
2349                 0x50400, 0x50400,
2350                 0x50800, 0x508cc,
2351                 0x50c00, 0x50c00,
2352                 0x51000, 0x5101c,
2353                 0x51300, 0x51308,
2354         };
2355
2356         int i;
2357         struct adapter *ap = netdev2adap(dev);
2358         static const unsigned int *reg_ranges;
2359         int arr_size = 0, buf_size = 0;
2360
2361         if (is_t4(ap->params.chip)) {
2362                 reg_ranges = &t4_reg_ranges[0];
2363                 arr_size = ARRAY_SIZE(t4_reg_ranges);
2364                 buf_size = T4_REGMAP_SIZE;
2365         } else {
2366                 reg_ranges = &t5_reg_ranges[0];
2367                 arr_size = ARRAY_SIZE(t5_reg_ranges);
2368                 buf_size = T5_REGMAP_SIZE;
2369         }
2370
2371         regs->version = mk_adap_vers(ap);
2372
2373         memset(buf, 0, buf_size);
2374         for (i = 0; i < arr_size; i += 2)
2375                 reg_block_dump(ap, buf, reg_ranges[i], reg_ranges[i + 1]);
2376 }
2377
2378 static int restart_autoneg(struct net_device *dev)
2379 {
2380         struct port_info *p = netdev_priv(dev);
2381
2382         if (!netif_running(dev))
2383                 return -EAGAIN;
2384         if (p->link_cfg.autoneg != AUTONEG_ENABLE)
2385                 return -EINVAL;
2386         t4_restart_aneg(p->adapter, p->adapter->fn, p->tx_chan);
2387         return 0;
2388 }
2389
2390 static int identify_port(struct net_device *dev,
2391                          enum ethtool_phys_id_state state)
2392 {
2393         unsigned int val;
2394         struct adapter *adap = netdev2adap(dev);
2395
2396         if (state == ETHTOOL_ID_ACTIVE)
2397                 val = 0xffff;
2398         else if (state == ETHTOOL_ID_INACTIVE)
2399                 val = 0;
2400         else
2401                 return -EINVAL;
2402
2403         return t4_identify_port(adap, adap->fn, netdev2pinfo(dev)->viid, val);
2404 }
2405
2406 static unsigned int from_fw_linkcaps(unsigned int type, unsigned int caps)
2407 {
2408         unsigned int v = 0;
2409
2410         if (type == FW_PORT_TYPE_BT_SGMII || type == FW_PORT_TYPE_BT_XFI ||
2411             type == FW_PORT_TYPE_BT_XAUI) {
2412                 v |= SUPPORTED_TP;
2413                 if (caps & FW_PORT_CAP_SPEED_100M)
2414                         v |= SUPPORTED_100baseT_Full;
2415                 if (caps & FW_PORT_CAP_SPEED_1G)
2416                         v |= SUPPORTED_1000baseT_Full;
2417                 if (caps & FW_PORT_CAP_SPEED_10G)
2418                         v |= SUPPORTED_10000baseT_Full;
2419         } else if (type == FW_PORT_TYPE_KX4 || type == FW_PORT_TYPE_KX) {
2420                 v |= SUPPORTED_Backplane;
2421                 if (caps & FW_PORT_CAP_SPEED_1G)
2422                         v |= SUPPORTED_1000baseKX_Full;
2423                 if (caps & FW_PORT_CAP_SPEED_10G)
2424                         v |= SUPPORTED_10000baseKX4_Full;
2425         } else if (type == FW_PORT_TYPE_KR)
2426                 v |= SUPPORTED_Backplane | SUPPORTED_10000baseKR_Full;
2427         else if (type == FW_PORT_TYPE_BP_AP)
2428                 v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
2429                      SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full;
2430         else if (type == FW_PORT_TYPE_BP4_AP)
2431                 v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
2432                      SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full |
2433                      SUPPORTED_10000baseKX4_Full;
2434         else if (type == FW_PORT_TYPE_FIBER_XFI ||
2435                  type == FW_PORT_TYPE_FIBER_XAUI || type == FW_PORT_TYPE_SFP)
2436                 v |= SUPPORTED_FIBRE;
2437         else if (type == FW_PORT_TYPE_BP40_BA)
2438                 v |= SUPPORTED_40000baseSR4_Full;
2439
2440         if (caps & FW_PORT_CAP_ANEG)
2441                 v |= SUPPORTED_Autoneg;
2442         return v;
2443 }
2444
2445 static unsigned int to_fw_linkcaps(unsigned int caps)
2446 {
2447         unsigned int v = 0;
2448
2449         if (caps & ADVERTISED_100baseT_Full)
2450                 v |= FW_PORT_CAP_SPEED_100M;
2451         if (caps & ADVERTISED_1000baseT_Full)
2452                 v |= FW_PORT_CAP_SPEED_1G;
2453         if (caps & ADVERTISED_10000baseT_Full)
2454                 v |= FW_PORT_CAP_SPEED_10G;
2455         if (caps & ADVERTISED_40000baseSR4_Full)
2456                 v |= FW_PORT_CAP_SPEED_40G;
2457         return v;
2458 }
2459
2460 static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2461 {
2462         const struct port_info *p = netdev_priv(dev);
2463
2464         if (p->port_type == FW_PORT_TYPE_BT_SGMII ||
2465             p->port_type == FW_PORT_TYPE_BT_XFI ||
2466             p->port_type == FW_PORT_TYPE_BT_XAUI)
2467                 cmd->port = PORT_TP;
2468         else if (p->port_type == FW_PORT_TYPE_FIBER_XFI ||
2469                  p->port_type == FW_PORT_TYPE_FIBER_XAUI)
2470                 cmd->port = PORT_FIBRE;
2471         else if (p->port_type == FW_PORT_TYPE_SFP ||
2472                  p->port_type == FW_PORT_TYPE_QSFP_10G ||
2473                  p->port_type == FW_PORT_TYPE_QSFP) {
2474                 if (p->mod_type == FW_PORT_MOD_TYPE_LR ||
2475                     p->mod_type == FW_PORT_MOD_TYPE_SR ||
2476                     p->mod_type == FW_PORT_MOD_TYPE_ER ||
2477                     p->mod_type == FW_PORT_MOD_TYPE_LRM)
2478                         cmd->port = PORT_FIBRE;
2479                 else if (p->mod_type == FW_PORT_MOD_TYPE_TWINAX_PASSIVE ||
2480                          p->mod_type == FW_PORT_MOD_TYPE_TWINAX_ACTIVE)
2481                         cmd->port = PORT_DA;
2482                 else
2483                         cmd->port = PORT_OTHER;
2484         } else
2485                 cmd->port = PORT_OTHER;
2486
2487         if (p->mdio_addr >= 0) {
2488                 cmd->phy_address = p->mdio_addr;
2489                 cmd->transceiver = XCVR_EXTERNAL;
2490                 cmd->mdio_support = p->port_type == FW_PORT_TYPE_BT_SGMII ?
2491                         MDIO_SUPPORTS_C22 : MDIO_SUPPORTS_C45;
2492         } else {
2493                 cmd->phy_address = 0;  /* not really, but no better option */
2494                 cmd->transceiver = XCVR_INTERNAL;
2495                 cmd->mdio_support = 0;
2496         }
2497
2498         cmd->supported = from_fw_linkcaps(p->port_type, p->link_cfg.supported);
2499         cmd->advertising = from_fw_linkcaps(p->port_type,
2500                                             p->link_cfg.advertising);
2501         ethtool_cmd_speed_set(cmd,
2502                               netif_carrier_ok(dev) ? p->link_cfg.speed : 0);
2503         cmd->duplex = DUPLEX_FULL;
2504         cmd->autoneg = p->link_cfg.autoneg;
2505         cmd->maxtxpkt = 0;
2506         cmd->maxrxpkt = 0;
2507         return 0;
2508 }
2509
2510 static unsigned int speed_to_caps(int speed)
2511 {
2512         if (speed == 100)
2513                 return FW_PORT_CAP_SPEED_100M;
2514         if (speed == 1000)
2515                 return FW_PORT_CAP_SPEED_1G;
2516         if (speed == 10000)
2517                 return FW_PORT_CAP_SPEED_10G;
2518         if (speed == 40000)
2519                 return FW_PORT_CAP_SPEED_40G;
2520         return 0;
2521 }
2522
2523 static int set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2524 {
2525         unsigned int cap;
2526         struct port_info *p = netdev_priv(dev);
2527         struct link_config *lc = &p->link_cfg;
2528         u32 speed = ethtool_cmd_speed(cmd);
2529
2530         if (cmd->duplex != DUPLEX_FULL)     /* only full-duplex supported */
2531                 return -EINVAL;
2532
2533         if (!(lc->supported & FW_PORT_CAP_ANEG)) {
2534                 /*
2535                  * PHY offers a single speed.  See if that's what's
2536                  * being requested.
2537                  */
2538                 if (cmd->autoneg == AUTONEG_DISABLE &&
2539                     (lc->supported & speed_to_caps(speed)))
2540                         return 0;
2541                 return -EINVAL;
2542         }
2543
2544         if (cmd->autoneg == AUTONEG_DISABLE) {
2545                 cap = speed_to_caps(speed);
2546
2547                 if (!(lc->supported & cap) ||
2548                     (speed == 1000) ||
2549                     (speed == 10000) ||
2550                     (speed == 40000))
2551                         return -EINVAL;
2552                 lc->requested_speed = cap;
2553                 lc->advertising = 0;
2554         } else {
2555                 cap = to_fw_linkcaps(cmd->advertising);
2556                 if (!(lc->supported & cap))
2557                         return -EINVAL;
2558                 lc->requested_speed = 0;
2559                 lc->advertising = cap | FW_PORT_CAP_ANEG;
2560         }
2561         lc->autoneg = cmd->autoneg;
2562
2563         if (netif_running(dev))
2564                 return t4_link_start(p->adapter, p->adapter->fn, p->tx_chan,
2565                                      lc);
2566         return 0;
2567 }
2568
2569 static void get_pauseparam(struct net_device *dev,
2570                            struct ethtool_pauseparam *epause)
2571 {
2572         struct port_info *p = netdev_priv(dev);
2573
2574         epause->autoneg = (p->link_cfg.requested_fc & PAUSE_AUTONEG) != 0;
2575         epause->rx_pause = (p->link_cfg.fc & PAUSE_RX) != 0;
2576         epause->tx_pause = (p->link_cfg.fc & PAUSE_TX) != 0;
2577 }
2578
2579 static int set_pauseparam(struct net_device *dev,
2580                           struct ethtool_pauseparam *epause)
2581 {
2582         struct port_info *p = netdev_priv(dev);
2583         struct link_config *lc = &p->link_cfg;
2584
2585         if (epause->autoneg == AUTONEG_DISABLE)
2586                 lc->requested_fc = 0;
2587         else if (lc->supported & FW_PORT_CAP_ANEG)
2588                 lc->requested_fc = PAUSE_AUTONEG;
2589         else
2590                 return -EINVAL;
2591
2592         if (epause->rx_pause)
2593                 lc->requested_fc |= PAUSE_RX;
2594         if (epause->tx_pause)
2595                 lc->requested_fc |= PAUSE_TX;
2596         if (netif_running(dev))
2597                 return t4_link_start(p->adapter, p->adapter->fn, p->tx_chan,
2598                                      lc);
2599         return 0;
2600 }
2601
2602 static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
2603 {
2604         const struct port_info *pi = netdev_priv(dev);
2605         const struct sge *s = &pi->adapter->sge;
2606
2607         e->rx_max_pending = MAX_RX_BUFFERS;
2608         e->rx_mini_max_pending = MAX_RSPQ_ENTRIES;
2609         e->rx_jumbo_max_pending = 0;
2610         e->tx_max_pending = MAX_TXQ_ENTRIES;
2611
2612         e->rx_pending = s->ethrxq[pi->first_qset].fl.size - 8;
2613         e->rx_mini_pending = s->ethrxq[pi->first_qset].rspq.size;
2614         e->rx_jumbo_pending = 0;
2615         e->tx_pending = s->ethtxq[pi->first_qset].q.size;
2616 }
2617
2618 static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
2619 {
2620         int i;
2621         const struct port_info *pi = netdev_priv(dev);
2622         struct adapter *adapter = pi->adapter;
2623         struct sge *s = &adapter->sge;
2624
2625         if (e->rx_pending > MAX_RX_BUFFERS || e->rx_jumbo_pending ||
2626             e->tx_pending > MAX_TXQ_ENTRIES ||
2627             e->rx_mini_pending > MAX_RSPQ_ENTRIES ||
2628             e->rx_mini_pending < MIN_RSPQ_ENTRIES ||
2629             e->rx_pending < MIN_FL_ENTRIES || e->tx_pending < MIN_TXQ_ENTRIES)
2630                 return -EINVAL;
2631
2632         if (adapter->flags & FULL_INIT_DONE)
2633                 return -EBUSY;
2634
2635         for (i = 0; i < pi->nqsets; ++i) {
2636                 s->ethtxq[pi->first_qset + i].q.size = e->tx_pending;
2637                 s->ethrxq[pi->first_qset + i].fl.size = e->rx_pending + 8;
2638                 s->ethrxq[pi->first_qset + i].rspq.size = e->rx_mini_pending;
2639         }
2640         return 0;
2641 }
2642
2643 static int closest_timer(const struct sge *s, int time)
2644 {
2645         int i, delta, match = 0, min_delta = INT_MAX;
2646
2647         for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
2648                 delta = time - s->timer_val[i];
2649                 if (delta < 0)
2650                         delta = -delta;
2651                 if (delta < min_delta) {
2652                         min_delta = delta;
2653                         match = i;
2654                 }
2655         }
2656         return match;
2657 }
2658
2659 static int closest_thres(const struct sge *s, int thres)
2660 {
2661         int i, delta, match = 0, min_delta = INT_MAX;
2662
2663         for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
2664                 delta = thres - s->counter_val[i];
2665                 if (delta < 0)
2666                         delta = -delta;
2667                 if (delta < min_delta) {
2668                         min_delta = delta;
2669                         match = i;
2670                 }
2671         }
2672         return match;
2673 }
2674
2675 /*
2676  * Return a queue's interrupt hold-off time in us.  0 means no timer.
2677  */
2678 static unsigned int qtimer_val(const struct adapter *adap,
2679                                const struct sge_rspq *q)
2680 {
2681         unsigned int idx = q->intr_params >> 1;
2682
2683         return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
2684 }
2685
2686 /**
2687  *      set_rspq_intr_params - set a queue's interrupt holdoff parameters
2688  *      @q: the Rx queue
2689  *      @us: the hold-off time in us, or 0 to disable timer
2690  *      @cnt: the hold-off packet count, or 0 to disable counter
2691  *
2692  *      Sets an Rx queue's interrupt hold-off time and packet count.  At least
2693  *      one of the two needs to be enabled for the queue to generate interrupts.
2694  */
2695 static int set_rspq_intr_params(struct sge_rspq *q,
2696                                 unsigned int us, unsigned int cnt)
2697 {
2698         struct adapter *adap = q->adap;
2699
2700         if ((us | cnt) == 0)
2701                 cnt = 1;
2702
2703         if (cnt) {
2704                 int err;
2705                 u32 v, new_idx;
2706
2707                 new_idx = closest_thres(&adap->sge, cnt);
2708                 if (q->desc && q->pktcnt_idx != new_idx) {
2709                         /* the queue has already been created, update it */
2710                         v = FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
2711                             FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
2712                             FW_PARAMS_PARAM_YZ(q->cntxt_id);
2713                         err = t4_set_params(adap, adap->fn, adap->fn, 0, 1, &v,
2714                                             &new_idx);
2715                         if (err)
2716                                 return err;
2717                 }
2718                 q->pktcnt_idx = new_idx;
2719         }
2720
2721         us = us == 0 ? 6 : closest_timer(&adap->sge, us);
2722         q->intr_params = QINTR_TIMER_IDX(us) | (cnt > 0 ? QINTR_CNT_EN : 0);
2723         return 0;
2724 }
2725
2726 /**
2727  * set_rx_intr_params - set a net devices's RX interrupt holdoff paramete!
2728  * @dev: the network device
2729  * @us: the hold-off time in us, or 0 to disable timer
2730  * @cnt: the hold-off packet count, or 0 to disable counter
2731  *
2732  * Set the RX interrupt hold-off parameters for a network device.
2733  */
2734 static int set_rx_intr_params(struct net_device *dev,
2735                               unsigned int us, unsigned int cnt)
2736 {
2737         int i, err;
2738         struct port_info *pi = netdev_priv(dev);
2739         struct adapter *adap = pi->adapter;
2740         struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
2741
2742         for (i = 0; i < pi->nqsets; i++, q++) {
2743                 err = set_rspq_intr_params(&q->rspq, us, cnt);
2744                 if (err)
2745                         return err;
2746         }
2747         return 0;
2748 }
2749
2750 static int set_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
2751 {
2752         return set_rx_intr_params(dev, c->rx_coalesce_usecs,
2753                                   c->rx_max_coalesced_frames);
2754 }
2755
2756 static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
2757 {
2758         const struct port_info *pi = netdev_priv(dev);
2759         const struct adapter *adap = pi->adapter;
2760         const struct sge_rspq *rq = &adap->sge.ethrxq[pi->first_qset].rspq;
2761
2762         c->rx_coalesce_usecs = qtimer_val(adap, rq);
2763         c->rx_max_coalesced_frames = (rq->intr_params & QINTR_CNT_EN) ?
2764                 adap->sge.counter_val[rq->pktcnt_idx] : 0;
2765         return 0;
2766 }
2767
2768 /**
2769  *      eeprom_ptov - translate a physical EEPROM address to virtual
2770  *      @phys_addr: the physical EEPROM address
2771  *      @fn: the PCI function number
2772  *      @sz: size of function-specific area
2773  *
2774  *      Translate a physical EEPROM address to virtual.  The first 1K is
2775  *      accessed through virtual addresses starting at 31K, the rest is
2776  *      accessed through virtual addresses starting at 0.
2777  *
2778  *      The mapping is as follows:
2779  *      [0..1K) -> [31K..32K)
2780  *      [1K..1K+A) -> [31K-A..31K)
2781  *      [1K+A..ES) -> [0..ES-A-1K)
2782  *
2783  *      where A = @fn * @sz, and ES = EEPROM size.
2784  */
2785 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2786 {
2787         fn *= sz;
2788         if (phys_addr < 1024)
2789                 return phys_addr + (31 << 10);
2790         if (phys_addr < 1024 + fn)
2791                 return 31744 - fn + phys_addr - 1024;
2792         if (phys_addr < EEPROMSIZE)
2793                 return phys_addr - 1024 - fn;
2794         return -EINVAL;
2795 }
2796
2797 /*
2798  * The next two routines implement eeprom read/write from physical addresses.
2799  */
2800 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
2801 {
2802         int vaddr = eeprom_ptov(phys_addr, adap->fn, EEPROMPFSIZE);
2803
2804         if (vaddr >= 0)
2805                 vaddr = pci_read_vpd(adap->pdev, vaddr, sizeof(u32), v);
2806         return vaddr < 0 ? vaddr : 0;
2807 }
2808
2809 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
2810 {
2811         int vaddr = eeprom_ptov(phys_addr, adap->fn, EEPROMPFSIZE);
2812
2813         if (vaddr >= 0)
2814                 vaddr = pci_write_vpd(adap->pdev, vaddr, sizeof(u32), &v);
2815         return vaddr < 0 ? vaddr : 0;
2816 }
2817
2818 #define EEPROM_MAGIC 0x38E2F10C
2819
2820 static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
2821                       u8 *data)
2822 {
2823         int i, err = 0;
2824         struct adapter *adapter = netdev2adap(dev);
2825
2826         u8 *buf = kmalloc(EEPROMSIZE, GFP_KERNEL);
2827         if (!buf)
2828                 return -ENOMEM;
2829
2830         e->magic = EEPROM_MAGIC;
2831         for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4)
2832                 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
2833
2834         if (!err)
2835                 memcpy(data, buf + e->offset, e->len);
2836         kfree(buf);
2837         return err;
2838 }
2839
2840 static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
2841                       u8 *data)
2842 {
2843         u8 *buf;
2844         int err = 0;
2845         u32 aligned_offset, aligned_len, *p;
2846         struct adapter *adapter = netdev2adap(dev);
2847
2848         if (eeprom->magic != EEPROM_MAGIC)
2849                 return -EINVAL;
2850
2851         aligned_offset = eeprom->offset & ~3;
2852         aligned_len = (eeprom->len + (eeprom->offset & 3) + 3) & ~3;
2853
2854         if (adapter->fn > 0) {
2855                 u32 start = 1024 + adapter->fn * EEPROMPFSIZE;
2856
2857                 if (aligned_offset < start ||
2858                     aligned_offset + aligned_len > start + EEPROMPFSIZE)
2859                         return -EPERM;
2860         }
2861
2862         if (aligned_offset != eeprom->offset || aligned_len != eeprom->len) {
2863                 /*
2864                  * RMW possibly needed for first or last words.
2865                  */
2866                 buf = kmalloc(aligned_len, GFP_KERNEL);
2867                 if (!buf)
2868                         return -ENOMEM;
2869                 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
2870                 if (!err && aligned_len > 4)
2871                         err = eeprom_rd_phys(adapter,
2872                                              aligned_offset + aligned_len - 4,
2873                                              (u32 *)&buf[aligned_len - 4]);
2874                 if (err)
2875                         goto out;
2876                 memcpy(buf + (eeprom->offset & 3), data, eeprom->len);
2877         } else
2878                 buf = data;
2879
2880         err = t4_seeprom_wp(adapter, false);
2881         if (err)
2882                 goto out;
2883
2884         for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
2885                 err = eeprom_wr_phys(adapter, aligned_offset, *p);
2886                 aligned_offset += 4;
2887         }
2888
2889         if (!err)
2890                 err = t4_seeprom_wp(adapter, true);
2891 out:
2892         if (buf != data)
2893                 kfree(buf);
2894         return err;
2895 }
2896
2897 static int set_flash(struct net_device *netdev, struct ethtool_flash *ef)
2898 {
2899         int ret;
2900         const struct firmware *fw;
2901         struct adapter *adap = netdev2adap(netdev);
2902
2903         ef->data[sizeof(ef->data) - 1] = '\0';
2904         ret = request_firmware(&fw, ef->data, adap->pdev_dev);
2905         if (ret < 0)
2906                 return ret;
2907
2908         ret = t4_load_fw(adap, fw->data, fw->size);
2909         release_firmware(fw);
2910         if (!ret)
2911                 dev_info(adap->pdev_dev, "loaded firmware %s\n", ef->data);
2912         return ret;
2913 }
2914
2915 #define WOL_SUPPORTED (WAKE_BCAST | WAKE_MAGIC)
2916 #define BCAST_CRC 0xa0ccc1a6
2917
2918 static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2919 {
2920         wol->supported = WAKE_BCAST | WAKE_MAGIC;
2921         wol->wolopts = netdev2adap(dev)->wol;
2922         memset(&wol->sopass, 0, sizeof(wol->sopass));
2923 }
2924
2925 static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2926 {
2927         int err = 0;
2928         struct port_info *pi = netdev_priv(dev);
2929
2930         if (wol->wolopts & ~WOL_SUPPORTED)
2931                 return -EINVAL;
2932         t4_wol_magic_enable(pi->adapter, pi->tx_chan,
2933                             (wol->wolopts & WAKE_MAGIC) ? dev->dev_addr : NULL);
2934         if (wol->wolopts & WAKE_BCAST) {
2935                 err = t4_wol_pat_enable(pi->adapter, pi->tx_chan, 0xfe, ~0ULL,
2936                                         ~0ULL, 0, false);
2937                 if (!err)
2938                         err = t4_wol_pat_enable(pi->adapter, pi->tx_chan, 1,
2939                                                 ~6ULL, ~0ULL, BCAST_CRC, true);
2940         } else
2941                 t4_wol_pat_enable(pi->adapter, pi->tx_chan, 0, 0, 0, 0, false);
2942         return err;
2943 }
2944
2945 static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
2946 {
2947         const struct port_info *pi = netdev_priv(dev);
2948         netdev_features_t changed = dev->features ^ features;
2949         int err;
2950
2951         if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
2952                 return 0;
2953
2954         err = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, -1,
2955                             -1, -1, -1,
2956                             !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
2957         if (unlikely(err))
2958                 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
2959         return err;
2960 }
2961
2962 static u32 get_rss_table_size(struct net_device *dev)
2963 {
2964         const struct port_info *pi = netdev_priv(dev);
2965
2966         return pi->rss_size;
2967 }
2968
2969 static int get_rss_table(struct net_device *dev, u32 *p, u8 *key)
2970 {
2971         const struct port_info *pi = netdev_priv(dev);
2972         unsigned int n = pi->rss_size;
2973
2974         while (n--)
2975                 p[n] = pi->rss[n];
2976         return 0;
2977 }
2978
2979 static int set_rss_table(struct net_device *dev, const u32 *p, const u8 *key)
2980 {
2981         unsigned int i;
2982         struct port_info *pi = netdev_priv(dev);
2983
2984         for (i = 0; i < pi->rss_size; i++)
2985                 pi->rss[i] = p[i];
2986         if (pi->adapter->flags & FULL_INIT_DONE)
2987                 return write_rss(pi, pi->rss);
2988         return 0;
2989 }
2990
2991 static int get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2992                      u32 *rules)
2993 {
2994         const struct port_info *pi = netdev_priv(dev);
2995
2996         switch (info->cmd) {
2997         case ETHTOOL_GRXFH: {
2998                 unsigned int v = pi->rss_mode;
2999
3000                 info->data = 0;
3001                 switch (info->flow_type) {
3002                 case TCP_V4_FLOW:
3003                         if (v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
3004                                 info->data = RXH_IP_SRC | RXH_IP_DST |
3005                                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
3006                         else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
3007                                 info->data = RXH_IP_SRC | RXH_IP_DST;
3008                         break;
3009                 case UDP_V4_FLOW:
3010                         if ((v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) &&
3011                             (v & FW_RSS_VI_CONFIG_CMD_UDPEN))
3012                                 info->data = RXH_IP_SRC | RXH_IP_DST |
3013                                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
3014                         else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
3015                                 info->data = RXH_IP_SRC | RXH_IP_DST;
3016                         break;
3017                 case SCTP_V4_FLOW:
3018                 case AH_ESP_V4_FLOW:
3019                 case IPV4_FLOW:
3020                         if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
3021                                 info->data = RXH_IP_SRC | RXH_IP_DST;
3022                         break;
3023                 case TCP_V6_FLOW:
3024                         if (v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
3025                                 info->data = RXH_IP_SRC | RXH_IP_DST |
3026                                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
3027                         else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
3028                                 info->data = RXH_IP_SRC | RXH_IP_DST;
3029                         break;
3030                 case UDP_V6_FLOW:
3031                         if ((v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) &&
3032                             (v & FW_RSS_VI_CONFIG_CMD_UDPEN))
3033                                 info->data = RXH_IP_SRC | RXH_IP_DST |
3034                                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
3035                         else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
3036                                 info->data = RXH_IP_SRC | RXH_IP_DST;
3037                         break;
3038                 case SCTP_V6_FLOW:
3039                 case AH_ESP_V6_FLOW:
3040                 case IPV6_FLOW:
3041                         if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
3042                                 info->data = RXH_IP_SRC | RXH_IP_DST;
3043                         break;
3044                 }
3045                 return 0;
3046         }
3047         case ETHTOOL_GRXRINGS:
3048                 info->data = pi->nqsets;
3049                 return 0;
3050         }
3051         return -EOPNOTSUPP;
3052 }
3053
3054 static const struct ethtool_ops cxgb_ethtool_ops = {
3055         .get_settings      = get_settings,
3056         .set_settings      = set_settings,
3057         .get_drvinfo       = get_drvinfo,
3058         .get_msglevel      = get_msglevel,
3059         .set_msglevel      = set_msglevel,
3060         .get_ringparam     = get_sge_param,
3061         .set_ringparam     = set_sge_param,
3062         .get_coalesce      = get_coalesce,
3063         .set_coalesce      = set_coalesce,
3064         .get_eeprom_len    = get_eeprom_len,
3065         .get_eeprom        = get_eeprom,
3066         .set_eeprom        = set_eeprom,
3067         .get_pauseparam    = get_pauseparam,
3068         .set_pauseparam    = set_pauseparam,
3069         .get_link          = ethtool_op_get_link,
3070         .get_strings       = get_strings,
3071         .set_phys_id       = identify_port,
3072         .nway_reset        = restart_autoneg,
3073         .get_sset_count    = get_sset_count,
3074         .get_ethtool_stats = get_stats,
3075         .get_regs_len      = get_regs_len,
3076         .get_regs          = get_regs,
3077         .get_wol           = get_wol,
3078         .set_wol           = set_wol,
3079         .get_rxnfc         = get_rxnfc,
3080         .get_rxfh_indir_size = get_rss_table_size,
3081         .get_rxfh          = get_rss_table,
3082         .set_rxfh          = set_rss_table,
3083         .flash_device      = set_flash,
3084 };
3085
3086 /*
3087  * debugfs support
3088  */
3089 static ssize_t mem_read(struct file *file, char __user *buf, size_t count,
3090                         loff_t *ppos)
3091 {
3092         loff_t pos = *ppos;
3093         loff_t avail = file_inode(file)->i_size;
3094         unsigned int mem = (uintptr_t)file->private_data & 3;
3095         struct adapter *adap = file->private_data - mem;
3096         __be32 *data;
3097         int ret;
3098
3099         if (pos < 0)
3100                 return -EINVAL;
3101         if (pos >= avail)
3102                 return 0;
3103         if (count > avail - pos)
3104                 count = avail - pos;
3105
3106         data = t4_alloc_mem(count);
3107         if (!data)
3108                 return -ENOMEM;
3109
3110         spin_lock(&adap->win0_lock);
3111         ret = t4_memory_rw(adap, 0, mem, pos, count, data, T4_MEMORY_READ);
3112         spin_unlock(&adap->win0_lock);
3113         if (ret) {
3114                 t4_free_mem(data);
3115                 return ret;
3116         }
3117         ret = copy_to_user(buf, data, count);
3118
3119         t4_free_mem(data);
3120         if (ret)
3121                 return -EFAULT;
3122
3123         *ppos = pos + count;
3124         return count;
3125 }
3126
3127 static const struct file_operations mem_debugfs_fops = {
3128         .owner   = THIS_MODULE,
3129         .open    = simple_open,
3130         .read    = mem_read,
3131         .llseek  = default_llseek,
3132 };
3133
3134 static void add_debugfs_mem(struct adapter *adap, const char *name,
3135                             unsigned int idx, unsigned int size_mb)
3136 {
3137         struct dentry *de;
3138
3139         de = debugfs_create_file(name, S_IRUSR, adap->debugfs_root,
3140                                  (void *)adap + idx, &mem_debugfs_fops);
3141         if (de && de->d_inode)
3142                 de->d_inode->i_size = size_mb << 20;
3143 }
3144
3145 static int setup_debugfs(struct adapter *adap)
3146 {
3147         int i;
3148         u32 size;
3149
3150         if (IS_ERR_OR_NULL(adap->debugfs_root))
3151                 return -1;
3152
3153         i = t4_read_reg(adap, MA_TARGET_MEM_ENABLE);
3154         if (i & EDRAM0_ENABLE) {
3155                 size = t4_read_reg(adap, MA_EDRAM0_BAR);
3156                 add_debugfs_mem(adap, "edc0", MEM_EDC0, EDRAM_SIZE_GET(size));
3157         }
3158         if (i & EDRAM1_ENABLE) {
3159                 size = t4_read_reg(adap, MA_EDRAM1_BAR);
3160                 add_debugfs_mem(adap, "edc1", MEM_EDC1, EDRAM_SIZE_GET(size));
3161         }
3162         if (is_t4(adap->params.chip)) {
3163                 size = t4_read_reg(adap, MA_EXT_MEMORY_BAR);
3164                 if (i & EXT_MEM_ENABLE)
3165                         add_debugfs_mem(adap, "mc", MEM_MC,
3166                                         EXT_MEM_SIZE_GET(size));
3167         } else {
3168                 if (i & EXT_MEM_ENABLE) {
3169                         size = t4_read_reg(adap, MA_EXT_MEMORY_BAR);
3170                         add_debugfs_mem(adap, "mc0", MEM_MC0,
3171                                         EXT_MEM_SIZE_GET(size));
3172                 }
3173                 if (i & EXT_MEM1_ENABLE) {
3174                         size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR);
3175                         add_debugfs_mem(adap, "mc1", MEM_MC1,
3176                                         EXT_MEM_SIZE_GET(size));
3177                 }
3178         }
3179         if (adap->l2t)
3180                 debugfs_create_file("l2t", S_IRUSR, adap->debugfs_root, adap,
3181                                     &t4_l2t_fops);
3182         return 0;
3183 }
3184
3185 /*
3186  * upper-layer driver support
3187  */
3188
3189 /*
3190  * Allocate an active-open TID and set it to the supplied value.
3191  */
3192 int cxgb4_alloc_atid(struct tid_info *t, void *data)
3193 {
3194         int atid = -1;
3195
3196         spin_lock_bh(&t->atid_lock);
3197         if (t->afree) {
3198                 union aopen_entry *p = t->afree;
3199
3200                 atid = (p - t->atid_tab) + t->atid_base;
3201                 t->afree = p->next;
3202                 p->data = data;
3203                 t->atids_in_use++;
3204         }
3205         spin_unlock_bh(&t->atid_lock);
3206         return atid;
3207 }
3208 EXPORT_SYMBOL(cxgb4_alloc_atid);
3209
3210 /*
3211  * Release an active-open TID.
3212  */
3213 void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
3214 {
3215         union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
3216
3217         spin_lock_bh(&t->atid_lock);
3218         p->next = t->afree;
3219         t->afree = p;
3220         t->atids_in_use--;
3221         spin_unlock_bh(&t->atid_lock);
3222 }
3223 EXPORT_SYMBOL(cxgb4_free_atid);
3224
3225 /*
3226  * Allocate a server TID and set it to the supplied value.
3227  */
3228 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
3229 {
3230         int stid;
3231
3232         spin_lock_bh(&t->stid_lock);
3233         if (family == PF_INET) {
3234                 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
3235                 if (stid < t->nstids)
3236                         __set_bit(stid, t->stid_bmap);
3237                 else
3238                         stid = -1;
3239         } else {
3240                 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 2);
3241                 if (stid < 0)
3242                         stid = -1;
3243         }
3244         if (stid >= 0) {
3245                 t->stid_tab[stid].data = data;
3246                 stid += t->stid_base;
3247                 /* IPv6 requires max of 520 bits or 16 cells in TCAM
3248                  * This is equivalent to 4 TIDs. With CLIP enabled it
3249                  * needs 2 TIDs.
3250                  */
3251                 if (family == PF_INET)
3252                         t->stids_in_use++;
3253                 else
3254                         t->stids_in_use += 4;
3255         }
3256         spin_unlock_bh(&t->stid_lock);
3257         return stid;
3258 }
3259 EXPORT_SYMBOL(cxgb4_alloc_stid);
3260
3261 /* Allocate a server filter TID and set it to the supplied value.
3262  */
3263 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
3264 {
3265         int stid;
3266
3267         spin_lock_bh(&t->stid_lock);
3268         if (family == PF_INET) {
3269                 stid = find_next_zero_bit(t->stid_bmap,
3270                                 t->nstids + t->nsftids, t->nstids);
3271                 if (stid < (t->nstids + t->nsftids))
3272                         __set_bit(stid, t->stid_bmap);
3273                 else
3274                         stid = -1;
3275         } else {
3276                 stid = -1;
3277         }
3278         if (stid >= 0) {
3279                 t->stid_tab[stid].data = data;
3280                 stid -= t->nstids;
3281                 stid += t->sftid_base;
3282                 t->stids_in_use++;
3283         }
3284         spin_unlock_bh(&t->stid_lock);
3285         return stid;
3286 }
3287 EXPORT_SYMBOL(cxgb4_alloc_sftid);
3288
3289 /* Release a server TID.
3290  */
3291 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
3292 {
3293         /* Is it a server filter TID? */
3294         if (t->nsftids && (stid >= t->sftid_base)) {
3295                 stid -= t->sftid_base;
3296                 stid += t->nstids;
3297         } else {
3298                 stid -= t->stid_base;
3299         }
3300
3301         spin_lock_bh(&t->stid_lock);
3302         if (family == PF_INET)
3303                 __clear_bit(stid, t->stid_bmap);
3304         else
3305                 bitmap_release_region(t->stid_bmap, stid, 2);
3306         t->stid_tab[stid].data = NULL;
3307         if (family == PF_INET)
3308                 t->stids_in_use--;
3309         else
3310                 t->stids_in_use -= 4;
3311         spin_unlock_bh(&t->stid_lock);
3312 }
3313 EXPORT_SYMBOL(cxgb4_free_stid);
3314
3315 /*
3316  * Populate a TID_RELEASE WR.  Caller must properly size the skb.
3317  */
3318 static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
3319                            unsigned int tid)
3320 {
3321         struct cpl_tid_release *req;
3322
3323         set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
3324         req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req));
3325         INIT_TP_WR(req, tid);
3326         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
3327 }
3328
3329 /*
3330  * Queue a TID release request and if necessary schedule a work queue to
3331  * process it.
3332  */
3333 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
3334                                     unsigned int tid)
3335 {
3336         void **p = &t->tid_tab[tid];
3337         struct adapter *adap = container_of(t, struct adapter, tids);
3338
3339         spin_lock_bh(&adap->tid_release_lock);
3340         *p = adap->tid_release_head;
3341         /* Low 2 bits encode the Tx channel number */
3342         adap->tid_release_head = (void **)((uintptr_t)p | chan);
3343         if (!adap->tid_release_task_busy) {
3344                 adap->tid_release_task_busy = true;
3345                 queue_work(adap->workq, &adap->tid_release_task);
3346         }
3347         spin_unlock_bh(&adap->tid_release_lock);
3348 }
3349
3350 /*
3351  * Process the list of pending TID release requests.
3352  */
3353 static void process_tid_release_list(struct work_struct *work)
3354 {
3355         struct sk_buff *skb;
3356         struct adapter *adap;
3357
3358         adap = container_of(work, struct adapter, tid_release_task);
3359
3360         spin_lock_bh(&adap->tid_release_lock);
3361         while (adap->tid_release_head) {
3362                 void **p = adap->tid_release_head;
3363                 unsigned int chan = (uintptr_t)p & 3;
3364                 p = (void *)p - chan;
3365
3366                 adap->tid_release_head = *p;
3367                 *p = NULL;
3368                 spin_unlock_bh(&adap->tid_release_lock);
3369
3370                 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
3371                                          GFP_KERNEL)))
3372                         schedule_timeout_uninterruptible(1);
3373
3374                 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
3375                 t4_ofld_send(adap, skb);
3376                 spin_lock_bh(&adap->tid_release_lock);
3377         }
3378         adap->tid_release_task_busy = false;
3379         spin_unlock_bh(&adap->tid_release_lock);
3380 }
3381
3382 /*
3383  * Release a TID and inform HW.  If we are unable to allocate the release
3384  * message we defer to a work queue.
3385  */
3386 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid)
3387 {
3388         void *old;
3389         struct sk_buff *skb;
3390         struct adapter *adap = container_of(t, struct adapter, tids);
3391
3392         old = t->tid_tab[tid];
3393         skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
3394         if (likely(skb)) {
3395                 t->tid_tab[tid] = NULL;
3396                 mk_tid_release(skb, chan, tid);
3397                 t4_ofld_send(adap, skb);
3398         } else
3399                 cxgb4_queue_tid_release(t, chan, tid);
3400         if (old)
3401                 atomic_dec(&t->tids_in_use);
3402 }
3403 EXPORT_SYMBOL(cxgb4_remove_tid);
3404
3405 /*
3406  * Allocate and initialize the TID tables.  Returns 0 on success.
3407  */
3408 static int tid_init(struct tid_info *t)
3409 {
3410         size_t size;
3411         unsigned int stid_bmap_size;
3412         unsigned int natids = t->natids;
3413         struct adapter *adap = container_of(t, struct adapter, tids);
3414
3415         stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
3416         size = t->ntids * sizeof(*t->tid_tab) +
3417                natids * sizeof(*t->atid_tab) +
3418                t->nstids * sizeof(*t->stid_tab) +
3419                t->nsftids * sizeof(*t->stid_tab) +
3420                stid_bmap_size * sizeof(long) +
3421                t->nftids * sizeof(*t->ftid_tab) +
3422                t->nsftids * sizeof(*t->ftid_tab);
3423
3424         t->tid_tab = t4_alloc_mem(size);
3425         if (!t->tid_tab)
3426                 return -ENOMEM;
3427
3428         t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
3429         t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
3430         t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
3431         t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
3432         spin_lock_init(&t->stid_lock);
3433         spin_lock_init(&t->atid_lock);
3434
3435         t->stids_in_use = 0;
3436         t->afree = NULL;
3437         t->atids_in_use = 0;
3438         atomic_set(&t->tids_in_use, 0);
3439
3440         /* Setup the free list for atid_tab and clear the stid bitmap. */
3441         if (natids) {
3442                 while (--natids)
3443                         t->atid_tab[natids - 1].next = &t->atid_tab[natids];
3444                 t->afree = t->atid_tab;
3445         }
3446         bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
3447         /* Reserve stid 0 for T4/T5 adapters */
3448         if (!t->stid_base &&
3449             (is_t4(adap->params.chip) || is_t5(adap->params.chip)))
3450                 __set_bit(0, t->stid_bmap);
3451
3452         return 0;
3453 }
3454
3455 int cxgb4_clip_get(const struct net_device *dev,
3456                    const struct in6_addr *lip)
3457 {
3458         struct adapter *adap;
3459         struct fw_clip_cmd c;
3460
3461         adap = netdev2adap(dev);
3462         memset(&c, 0, sizeof(c));
3463         c.op_to_write = htonl(FW_CMD_OP(FW_CLIP_CMD) |
3464                         FW_CMD_REQUEST | FW_CMD_WRITE);
3465         c.alloc_to_len16 = htonl(F_FW_CLIP_CMD_ALLOC | FW_LEN16(c));
3466         c.ip_hi = *(__be64 *)(lip->s6_addr);
3467         c.ip_lo = *(__be64 *)(lip->s6_addr + 8);
3468         return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, false);
3469 }
3470 EXPORT_SYMBOL(cxgb4_clip_get);
3471
3472 int cxgb4_clip_release(const struct net_device *dev,
3473                        const struct in6_addr *lip)
3474 {
3475         struct adapter *adap;
3476         struct fw_clip_cmd c;
3477
3478         adap = netdev2adap(dev);
3479         memset(&c, 0, sizeof(c));
3480         c.op_to_write = htonl(FW_CMD_OP(FW_CLIP_CMD) |
3481                         FW_CMD_REQUEST | FW_CMD_READ);
3482         c.alloc_to_len16 = htonl(F_FW_CLIP_CMD_FREE | FW_LEN16(c));
3483         c.ip_hi = *(__be64 *)(lip->s6_addr);
3484         c.ip_lo = *(__be64 *)(lip->s6_addr + 8);
3485         return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, false);
3486 }
3487 EXPORT_SYMBOL(cxgb4_clip_release);
3488
3489 /**
3490  *      cxgb4_create_server - create an IP server
3491  *      @dev: the device
3492  *      @stid: the server TID
3493  *      @sip: local IP address to bind server to
3494  *      @sport: the server's TCP port
3495  *      @queue: queue to direct messages from this server to
3496  *
3497  *      Create an IP server for the given port and address.
3498  *      Returns <0 on error and one of the %NET_XMIT_* values on success.
3499  */
3500 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
3501                         __be32 sip, __be16 sport, __be16 vlan,
3502                         unsigned int queue)
3503 {
3504         unsigned int chan;
3505         struct sk_buff *skb;
3506         struct adapter *adap;
3507         struct cpl_pass_open_req *req;
3508         int ret;
3509
3510         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3511         if (!skb)
3512                 return -ENOMEM;
3513
3514         adap = netdev2adap(dev);
3515         req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req));
3516         INIT_TP_WR(req, 0);
3517         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
3518         req->local_port = sport;
3519         req->peer_port = htons(0);
3520         req->local_ip = sip;
3521         req->peer_ip = htonl(0);
3522         chan = rxq_to_chan(&adap->sge, queue);
3523         req->opt0 = cpu_to_be64(TX_CHAN(chan));
3524         req->opt1 = cpu_to_be64(CONN_POLICY_ASK |
3525                                 SYN_RSS_ENABLE | SYN_RSS_QUEUE(queue));
3526         ret = t4_mgmt_tx(adap, skb);
3527         return net_xmit_eval(ret);
3528 }
3529 EXPORT_SYMBOL(cxgb4_create_server);
3530
3531 /*      cxgb4_create_server6 - create an IPv6 server
3532  *      @dev: the device
3533  *      @stid: the server TID
3534  *      @sip: local IPv6 address to bind server to
3535  *      @sport: the server's TCP port
3536  *      @queue: queue to direct messages from this server to
3537  *
3538  *      Create an IPv6 server for the given port and address.
3539  *      Returns <0 on error and one of the %NET_XMIT_* values on success.
3540  */
3541 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
3542                          const struct in6_addr *sip, __be16 sport,
3543                          unsigned int queue)
3544 {
3545         unsigned int chan;
3546         struct sk_buff *skb;
3547         struct adapter *adap;
3548         struct cpl_pass_open_req6 *req;
3549         int ret;
3550
3551         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3552         if (!skb)
3553                 return -ENOMEM;
3554
3555         adap = netdev2adap(dev);
3556         req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req));
3557         INIT_TP_WR(req, 0);
3558         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
3559         req->local_port = sport;
3560         req->peer_port = htons(0);
3561         req->local_ip_hi = *(__be64 *)(sip->s6_addr);
3562         req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
3563         req->peer_ip_hi = cpu_to_be64(0);
3564         req->peer_ip_lo = cpu_to_be64(0);
3565         chan = rxq_to_chan(&adap->sge, queue);
3566         req->opt0 = cpu_to_be64(TX_CHAN(chan));
3567         req->opt1 = cpu_to_be64(CONN_POLICY_ASK |
3568                                 SYN_RSS_ENABLE | SYN_RSS_QUEUE(queue));
3569         ret = t4_mgmt_tx(adap, skb);
3570         return net_xmit_eval(ret);
3571 }
3572 EXPORT_SYMBOL(cxgb4_create_server6);
3573
3574 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
3575                         unsigned int queue, bool ipv6)
3576 {
3577         struct sk_buff *skb;
3578         struct adapter *adap;
3579         struct cpl_close_listsvr_req *req;
3580         int ret;
3581
3582         adap = netdev2adap(dev);
3583
3584         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3585         if (!skb)
3586                 return -ENOMEM;
3587
3588         req = (struct cpl_close_listsvr_req *)__skb_put(skb, sizeof(*req));
3589         INIT_TP_WR(req, 0);
3590         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
3591         req->reply_ctrl = htons(NO_REPLY(0) | (ipv6 ? LISTSVR_IPV6(1) :
3592                                 LISTSVR_IPV6(0)) | QUEUENO(queue));
3593         ret = t4_mgmt_tx(adap, skb);
3594         return net_xmit_eval(ret);
3595 }
3596 EXPORT_SYMBOL(cxgb4_remove_server);
3597
3598 /**
3599  *      cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
3600  *      @mtus: the HW MTU table
3601  *      @mtu: the target MTU
3602  *      @idx: index of selected entry in the MTU table
3603  *
3604  *      Returns the index and the value in the HW MTU table that is closest to
3605  *      but does not exceed @mtu, unless @mtu is smaller than any value in the
3606  *      table, in which case that smallest available value is selected.
3607  */
3608 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
3609                             unsigned int *idx)
3610 {
3611         unsigned int i = 0;
3612
3613         while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
3614                 ++i;
3615         if (idx)
3616                 *idx = i;
3617         return mtus[i];
3618 }
3619 EXPORT_SYMBOL(cxgb4_best_mtu);
3620
3621 /**
3622  *     cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
3623  *     @mtus: the HW MTU table
3624  *     @header_size: Header Size
3625  *     @data_size_max: maximum Data Segment Size
3626  *     @data_size_align: desired Data Segment Size Alignment (2^N)
3627  *     @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
3628  *
3629  *     Similar to cxgb4_best_mtu() but instead of searching the Hardware
3630  *     MTU Table based solely on a Maximum MTU parameter, we break that
3631  *     parameter up into a Header Size and Maximum Data Segment Size, and
3632  *     provide a desired Data Segment Size Alignment.  If we find an MTU in
3633  *     the Hardware MTU Table which will result in a Data Segment Size with
3634  *     the requested alignment _and_ that MTU isn't "too far" from the
3635  *     closest MTU, then we'll return that rather than the closest MTU.
3636  */
3637 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
3638                                     unsigned short header_size,
3639                                     unsigned short data_size_max,
3640                                     unsigned short data_size_align,
3641                                     unsigned int *mtu_idxp)
3642 {
3643         unsigned short max_mtu = header_size + data_size_max;
3644         unsigned short data_size_align_mask = data_size_align - 1;
3645         int mtu_idx, aligned_mtu_idx;
3646
3647         /* Scan the MTU Table till we find an MTU which is larger than our
3648          * Maximum MTU or we reach the end of the table.  Along the way,
3649          * record the last MTU found, if any, which will result in a Data
3650          * Segment Length matching the requested alignment.
3651          */
3652         for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
3653                 unsigned short data_size = mtus[mtu_idx] - header_size;
3654
3655                 /* If this MTU minus the Header Size would result in a
3656                  * Data Segment Size of the desired alignment, remember it.
3657                  */
3658                 if ((data_size & data_size_align_mask) == 0)
3659                         aligned_mtu_idx = mtu_idx;
3660
3661                 /* If we're not at the end of the Hardware MTU Table and the
3662                  * next element is larger than our Maximum MTU, drop out of
3663                  * the loop.
3664                  */
3665                 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
3666                         break;
3667         }
3668
3669         /* If we fell out of the loop because we ran to the end of the table,
3670          * then we just have to use the last [largest] entry.
3671          */
3672         if (mtu_idx == NMTUS)
3673                 mtu_idx--;
3674
3675         /* If we found an MTU which resulted in the requested Data Segment
3676          * Length alignment and that's "not far" from the largest MTU which is
3677          * less than or equal to the maximum MTU, then use that.
3678          */
3679         if (aligned_mtu_idx >= 0 &&
3680             mtu_idx - aligned_mtu_idx <= 1)
3681                 mtu_idx = aligned_mtu_idx;
3682
3683         /* If the caller has passed in an MTU Index pointer, pass the
3684          * MTU Index back.  Return the MTU value.
3685          */
3686         if (mtu_idxp)
3687                 *mtu_idxp = mtu_idx;
3688         return mtus[mtu_idx];
3689 }
3690 EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
3691
3692 /**
3693  *      cxgb4_port_chan - get the HW channel of a port
3694  *      @dev: the net device for the port
3695  *
3696  *      Return the HW Tx channel of the given port.
3697  */
3698 unsigned int cxgb4_port_chan(const struct net_device *dev)
3699 {
3700         return netdev2pinfo(dev)->tx_chan;
3701 }
3702 EXPORT_SYMBOL(cxgb4_port_chan);
3703
3704 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
3705 {
3706         struct adapter *adap = netdev2adap(dev);
3707         u32 v1, v2, lp_count, hp_count;
3708
3709         v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
3710         v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);
3711         if (is_t4(adap->params.chip)) {
3712                 lp_count = G_LP_COUNT(v1);
3713                 hp_count = G_HP_COUNT(v1);
3714         } else {
3715                 lp_count = G_LP_COUNT_T5(v1);
3716                 hp_count = G_HP_COUNT_T5(v2);
3717         }
3718         return lpfifo ? lp_count : hp_count;
3719 }
3720 EXPORT_SYMBOL(cxgb4_dbfifo_count);
3721
3722 /**
3723  *      cxgb4_port_viid - get the VI id of a port
3724  *      @dev: the net device for the port
3725  *
3726  *      Return the VI id of the given port.
3727  */
3728 unsigned int cxgb4_port_viid(const struct net_device *dev)
3729 {
3730         return netdev2pinfo(dev)->viid;
3731 }
3732 EXPORT_SYMBOL(cxgb4_port_viid);
3733
3734 /**
3735  *      cxgb4_port_idx - get the index of a port
3736  *      @dev: the net device for the port
3737  *
3738  *      Return the index of the given port.
3739  */
3740 unsigned int cxgb4_port_idx(const struct net_device *dev)
3741 {
3742         return netdev2pinfo(dev)->port_id;
3743 }
3744 EXPORT_SYMBOL(cxgb4_port_idx);
3745
3746 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
3747                          struct tp_tcp_stats *v6)
3748 {
3749         struct adapter *adap = pci_get_drvdata(pdev);
3750
3751         spin_lock(&adap->stats_lock);
3752         t4_tp_get_tcp_stats(adap, v4, v6);
3753         spin_unlock(&adap->stats_lock);
3754 }
3755 EXPORT_SYMBOL(cxgb4_get_tcp_stats);
3756
3757 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
3758                       const unsigned int *pgsz_order)
3759 {
3760         struct adapter *adap = netdev2adap(dev);
3761
3762         t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK, tag_mask);
3763         t4_write_reg(adap, ULP_RX_ISCSI_PSZ, HPZ0(pgsz_order[0]) |
3764                      HPZ1(pgsz_order[1]) | HPZ2(pgsz_order[2]) |
3765                      HPZ3(pgsz_order[3]));
3766 }
3767 EXPORT_SYMBOL(cxgb4_iscsi_init);
3768
3769 int cxgb4_flush_eq_cache(struct net_device *dev)
3770 {
3771         struct adapter *adap = netdev2adap(dev);
3772         int ret;
3773
3774         ret = t4_fwaddrspace_write(adap, adap->mbox,
3775                                    0xe1000000 + A_SGE_CTXT_CMD, 0x20000000);
3776         return ret;
3777 }
3778 EXPORT_SYMBOL(cxgb4_flush_eq_cache);
3779
3780 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
3781 {
3782         u32 addr = t4_read_reg(adap, A_SGE_DBQ_CTXT_BADDR) + 24 * qid + 8;
3783         __be64 indices;
3784         int ret;
3785
3786         spin_lock(&adap->win0_lock);
3787         ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
3788                            sizeof(indices), (__be32 *)&indices,
3789                            T4_MEMORY_READ);
3790         spin_unlock(&adap->win0_lock);
3791         if (!ret) {
3792                 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
3793                 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
3794         }
3795         return ret;
3796 }
3797
3798 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
3799                         u16 size)
3800 {
3801         struct adapter *adap = netdev2adap(dev);
3802         u16 hw_pidx, hw_cidx;
3803         int ret;
3804
3805         ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
3806         if (ret)
3807                 goto out;
3808
3809         if (pidx != hw_pidx) {
3810                 u16 delta;
3811
3812                 if (pidx >= hw_pidx)
3813                         delta = pidx - hw_pidx;
3814                 else
3815                         delta = size - hw_pidx + pidx;
3816                 wmb();
3817                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
3818                              QID(qid) | PIDX(delta));
3819         }
3820 out:
3821         return ret;
3822 }
3823 EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
3824
3825 void cxgb4_disable_db_coalescing(struct net_device *dev)
3826 {
3827         struct adapter *adap;
3828
3829         adap = netdev2adap(dev);
3830         t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_NOCOALESCE,
3831                          F_NOCOALESCE);
3832 }
3833 EXPORT_SYMBOL(cxgb4_disable_db_coalescing);
3834
3835 void cxgb4_enable_db_coalescing(struct net_device *dev)
3836 {
3837         struct adapter *adap;
3838
3839         adap = netdev2adap(dev);
3840         t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_NOCOALESCE, 0);
3841 }
3842 EXPORT_SYMBOL(cxgb4_enable_db_coalescing);
3843
3844 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
3845 {
3846         struct adapter *adap;
3847         u32 offset, memtype, memaddr;
3848         u32 edc0_size, edc1_size, mc0_size, mc1_size;
3849         u32 edc0_end, edc1_end, mc0_end, mc1_end;
3850         int ret;
3851
3852         adap = netdev2adap(dev);
3853
3854         offset = ((stag >> 8) * 32) + adap->vres.stag.start;
3855
3856         /* Figure out where the offset lands in the Memory Type/Address scheme.
3857          * This code assumes that the memory is laid out starting at offset 0
3858          * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
3859          * and EDC1.  Some cards will have neither MC0 nor MC1, most cards have
3860          * MC0, and some have both MC0 and MC1.
3861          */
3862         edc0_size = EDRAM_SIZE_GET(t4_read_reg(adap, MA_EDRAM0_BAR)) << 20;
3863         edc1_size = EDRAM_SIZE_GET(t4_read_reg(adap, MA_EDRAM1_BAR)) << 20;
3864         mc0_size = EXT_MEM_SIZE_GET(t4_read_reg(adap, MA_EXT_MEMORY_BAR)) << 20;
3865
3866         edc0_end = edc0_size;
3867         edc1_end = edc0_end + edc1_size;
3868         mc0_end = edc1_end + mc0_size;
3869
3870         if (offset < edc0_end) {
3871                 memtype = MEM_EDC0;
3872                 memaddr = offset;
3873         } else if (offset < edc1_end) {
3874                 memtype = MEM_EDC1;
3875                 memaddr = offset - edc0_end;
3876         } else {
3877                 if (offset < mc0_end) {
3878                         memtype = MEM_MC0;
3879                         memaddr = offset - edc1_end;
3880                 } else if (is_t4(adap->params.chip)) {
3881                         /* T4 only has a single memory channel */
3882                         goto err;
3883                 } else {
3884                         mc1_size = EXT_MEM_SIZE_GET(
3885                                         t4_read_reg(adap,
3886                                                     MA_EXT_MEMORY1_BAR)) << 20;
3887                         mc1_end = mc0_end + mc1_size;
3888                         if (offset < mc1_end) {
3889                                 memtype = MEM_MC1;
3890                                 memaddr = offset - mc0_end;
3891                         } else {
3892                                 /* offset beyond the end of any memory */
3893                                 goto err;
3894                         }
3895                 }
3896         }
3897
3898         spin_lock(&adap->win0_lock);
3899         ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
3900         spin_unlock(&adap->win0_lock);
3901         return ret;
3902
3903 err:
3904         dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
3905                 stag, offset);
3906         return -EINVAL;
3907 }
3908 EXPORT_SYMBOL(cxgb4_read_tpte);
3909
3910 u64 cxgb4_read_sge_timestamp(struct net_device *dev)
3911 {
3912         u32 hi, lo;
3913         struct adapter *adap;
3914
3915         adap = netdev2adap(dev);
3916         lo = t4_read_reg(adap, SGE_TIMESTAMP_LO);
3917         hi = GET_TSVAL(t4_read_reg(adap, SGE_TIMESTAMP_HI));
3918
3919         return ((u64)hi << 32) | (u64)lo;
3920 }
3921 EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
3922
3923 static struct pci_driver cxgb4_driver;
3924
3925 static void check_neigh_update(struct neighbour *neigh)
3926 {
3927         const struct device *parent;
3928         const struct net_device *netdev = neigh->dev;
3929
3930         if (netdev->priv_flags & IFF_802_1Q_VLAN)
3931                 netdev = vlan_dev_real_dev(netdev);
3932         parent = netdev->dev.parent;
3933         if (parent && parent->driver == &cxgb4_driver.driver)
3934                 t4_l2t_update(dev_get_drvdata(parent), neigh);
3935 }
3936
3937 static int netevent_cb(struct notifier_block *nb, unsigned long event,
3938                        void *data)
3939 {
3940         switch (event) {
3941         case NETEVENT_NEIGH_UPDATE:
3942                 check_neigh_update(data);
3943                 break;
3944         case NETEVENT_REDIRECT:
3945         default:
3946                 break;
3947         }
3948         return 0;
3949 }
3950
3951 static bool netevent_registered;
3952 static struct notifier_block cxgb4_netevent_nb = {
3953         .notifier_call = netevent_cb
3954 };
3955
3956 static void drain_db_fifo(struct adapter *adap, int usecs)
3957 {
3958         u32 v1, v2, lp_count, hp_count;
3959
3960         do {
3961                 v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
3962                 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);
3963                 if (is_t4(adap->params.chip)) {
3964                         lp_count = G_LP_COUNT(v1);
3965                         hp_count = G_HP_COUNT(v1);
3966                 } else {
3967                         lp_count = G_LP_COUNT_T5(v1);
3968                         hp_count = G_HP_COUNT_T5(v2);
3969                 }
3970
3971                 if (lp_count == 0 && hp_count == 0)
3972                         break;
3973                 set_current_state(TASK_UNINTERRUPTIBLE);
3974                 schedule_timeout(usecs_to_jiffies(usecs));
3975         } while (1);
3976 }
3977
3978 static void disable_txq_db(struct sge_txq *q)
3979 {
3980         unsigned long flags;
3981
3982         spin_lock_irqsave(&q->db_lock, flags);
3983         q->db_disabled = 1;
3984         spin_unlock_irqrestore(&q->db_lock, flags);
3985 }
3986
3987 static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
3988 {
3989         spin_lock_irq(&q->db_lock);
3990         if (q->db_pidx_inc) {
3991                 /* Make sure that all writes to the TX descriptors
3992                  * are committed before we tell HW about them.
3993                  */
3994                 wmb();
3995                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
3996                              QID(q->cntxt_id) | PIDX(q->db_pidx_inc));
3997                 q->db_pidx_inc = 0;
3998         }
3999         q->db_disabled = 0;
4000         spin_unlock_irq(&q->db_lock);
4001 }
4002
4003 static void disable_dbs(struct adapter *adap)
4004 {
4005         int i;
4006
4007         for_each_ethrxq(&adap->sge, i)
4008                 disable_txq_db(&adap->sge.ethtxq[i].q);
4009         for_each_ofldrxq(&adap->sge, i)
4010                 disable_txq_db(&adap->sge.ofldtxq[i].q);
4011         for_each_port(adap, i)
4012                 disable_txq_db(&adap->sge.ctrlq[i].q);
4013 }
4014
4015 static void enable_dbs(struct adapter *adap)
4016 {
4017         int i;
4018
4019         for_each_ethrxq(&adap->sge, i)
4020                 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
4021         for_each_ofldrxq(&adap->sge, i)
4022                 enable_txq_db(adap, &adap->sge.ofldtxq[i].q);
4023         for_each_port(adap, i)
4024                 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
4025 }
4026
4027 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
4028 {
4029         if (adap->uld_handle[CXGB4_ULD_RDMA])
4030                 ulds[CXGB4_ULD_RDMA].control(adap->uld_handle[CXGB4_ULD_RDMA],
4031                                 cmd);
4032 }
4033
4034 static void process_db_full(struct work_struct *work)
4035 {
4036         struct adapter *adap;
4037
4038         adap = container_of(work, struct adapter, db_full_task);
4039
4040         drain_db_fifo(adap, dbfifo_drain_delay);
4041         enable_dbs(adap);
4042         notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
4043         t4_set_reg_field(adap, SGE_INT_ENABLE3,
4044                          DBFIFO_HP_INT | DBFIFO_LP_INT,
4045                          DBFIFO_HP_INT | DBFIFO_LP_INT);
4046 }
4047
4048 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
4049 {
4050         u16 hw_pidx, hw_cidx;
4051         int ret;
4052
4053         spin_lock_irq(&q->db_lock);
4054         ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
4055         if (ret)
4056                 goto out;
4057         if (q->db_pidx != hw_pidx) {
4058                 u16 delta;
4059
4060                 if (q->db_pidx >= hw_pidx)
4061                         delta = q->db_pidx - hw_pidx;
4062                 else
4063                         delta = q->size - hw_pidx + q->db_pidx;
4064                 wmb();
4065                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
4066                              QID(q->cntxt_id) | PIDX(delta));
4067         }
4068 out:
4069         q->db_disabled = 0;
4070         q->db_pidx_inc = 0;
4071         spin_unlock_irq(&q->db_lock);
4072         if (ret)
4073                 CH_WARN(adap, "DB drop recovery failed.\n");
4074 }
4075 static void recover_all_queues(struct adapter *adap)
4076 {
4077         int i;
4078
4079         for_each_ethrxq(&adap->sge, i)
4080                 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
4081         for_each_ofldrxq(&adap->sge, i)
4082                 sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q);
4083         for_each_port(adap, i)
4084                 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
4085 }
4086
4087 static void process_db_drop(struct work_struct *work)
4088 {
4089         struct adapter *adap;
4090
4091         adap = container_of(work, struct adapter, db_drop_task);
4092
4093         if (is_t4(adap->params.chip)) {
4094                 drain_db_fifo(adap, dbfifo_drain_delay);
4095                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
4096                 drain_db_fifo(adap, dbfifo_drain_delay);
4097                 recover_all_queues(adap);
4098                 drain_db_fifo(adap, dbfifo_drain_delay);
4099                 enable_dbs(adap);
4100                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
4101         } else {
4102                 u32 dropped_db = t4_read_reg(adap, 0x010ac);
4103                 u16 qid = (dropped_db >> 15) & 0x1ffff;
4104                 u16 pidx_inc = dropped_db & 0x1fff;
4105                 unsigned int s_qpp;
4106                 unsigned short udb_density;
4107                 unsigned long qpshift;
4108                 int page;
4109                 u32 udb;
4110
4111                 dev_warn(adap->pdev_dev,
4112                          "Dropped DB 0x%x qid %d bar2 %d coalesce %d pidx %d\n",
4113                          dropped_db, qid,
4114                          (dropped_db >> 14) & 1,
4115                          (dropped_db >> 13) & 1,
4116                          pidx_inc);
4117
4118                 drain_db_fifo(adap, 1);
4119
4120                 s_qpp = QUEUESPERPAGEPF1 * adap->fn;
4121                 udb_density = 1 << QUEUESPERPAGEPF0_GET(t4_read_reg(adap,
4122                                 SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp);
4123                 qpshift = PAGE_SHIFT - ilog2(udb_density);
4124                 udb = qid << qpshift;
4125                 udb &= PAGE_MASK;
4126                 page = udb / PAGE_SIZE;
4127                 udb += (qid - (page * udb_density)) * 128;
4128
4129                 writel(PIDX(pidx_inc),  adap->bar2 + udb + 8);
4130
4131                 /* Re-enable BAR2 WC */
4132                 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
4133         }
4134
4135         t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_DROPPED_DB, 0);
4136 }
4137
4138 void t4_db_full(struct adapter *adap)
4139 {
4140         if (is_t4(adap->params.chip)) {
4141                 disable_dbs(adap);
4142                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
4143                 t4_set_reg_field(adap, SGE_INT_ENABLE3,
4144                                  DBFIFO_HP_INT | DBFIFO_LP_INT, 0);
4145                 queue_work(adap->workq, &adap->db_full_task);
4146         }
4147 }
4148
4149 void t4_db_dropped(struct adapter *adap)
4150 {
4151         if (is_t4(adap->params.chip)) {
4152                 disable_dbs(adap);
4153                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
4154         }
4155         queue_work(adap->workq, &adap->db_drop_task);
4156 }
4157
4158 static void uld_attach(struct adapter *adap, unsigned int uld)
4159 {
4160         void *handle;
4161         struct cxgb4_lld_info lli;
4162         unsigned short i;
4163
4164         lli.pdev = adap->pdev;
4165         lli.pf = adap->fn;
4166         lli.l2t = adap->l2t;
4167         lli.tids = &adap->tids;
4168         lli.ports = adap->port;
4169         lli.vr = &adap->vres;
4170         lli.mtus = adap->params.mtus;
4171         if (uld == CXGB4_ULD_RDMA) {
4172                 lli.rxq_ids = adap->sge.rdma_rxq;
4173                 lli.ciq_ids = adap->sge.rdma_ciq;
4174                 lli.nrxq = adap->sge.rdmaqs;
4175                 lli.nciq = adap->sge.rdmaciqs;
4176         } else if (uld == CXGB4_ULD_ISCSI) {
4177                 lli.rxq_ids = adap->sge.ofld_rxq;
4178                 lli.nrxq = adap->sge.ofldqsets;
4179         }
4180         lli.ntxq = adap->sge.ofldqsets;
4181         lli.nchan = adap->params.nports;
4182         lli.nports = adap->params.nports;
4183         lli.wr_cred = adap->params.ofldq_wr_cred;
4184         lli.adapter_type = adap->params.chip;
4185         lli.iscsi_iolen = MAXRXDATA_GET(t4_read_reg(adap, TP_PARA_REG2));
4186         lli.cclk_ps = 1000000000 / adap->params.vpd.cclk;
4187         lli.udb_density = 1 << QUEUESPERPAGEPF0_GET(
4188                         t4_read_reg(adap, SGE_EGRESS_QUEUES_PER_PAGE_PF) >>
4189                         (adap->fn * 4));
4190         lli.ucq_density = 1 << QUEUESPERPAGEPF0_GET(
4191                         t4_read_reg(adap, SGE_INGRESS_QUEUES_PER_PAGE_PF) >>
4192                         (adap->fn * 4));
4193         lli.filt_mode = adap->params.tp.vlan_pri_map;
4194         /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */
4195         for (i = 0; i < NCHAN; i++)
4196                 lli.tx_modq[i] = i;
4197         lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS);
4198         lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL);
4199         lli.fw_vers = adap->params.fw_vers;
4200         lli.dbfifo_int_thresh = dbfifo_int_thresh;
4201         lli.sge_ingpadboundary = adap->sge.fl_align;
4202         lli.sge_egrstatuspagesize = adap->sge.stat_len;
4203         lli.sge_pktshift = adap->sge.pktshift;
4204         lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
4205         lli.max_ordird_qp = adap->params.max_ordird_qp;
4206         lli.max_ird_adapter = adap->params.max_ird_adapter;
4207         lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
4208
4209         handle = ulds[uld].add(&lli);
4210         if (IS_ERR(handle)) {
4211                 dev_warn(adap->pdev_dev,
4212                          "could not attach to the %s driver, error %ld\n",
4213                          uld_str[uld], PTR_ERR(handle));
4214                 return;
4215         }
4216
4217         adap->uld_handle[uld] = handle;
4218
4219         if (!netevent_registered) {
4220                 register_netevent_notifier(&cxgb4_netevent_nb);
4221                 netevent_registered = true;
4222         }
4223
4224         if (adap->flags & FULL_INIT_DONE)
4225                 ulds[uld].state_change(handle, CXGB4_STATE_UP);
4226 }
4227
4228 static void attach_ulds(struct adapter *adap)
4229 {
4230         unsigned int i;
4231
4232         spin_lock(&adap_rcu_lock);
4233         list_add_tail_rcu(&adap->rcu_node, &adap_rcu_list);
4234         spin_unlock(&adap_rcu_lock);
4235
4236         mutex_lock(&uld_mutex);
4237         list_add_tail(&adap->list_node, &adapter_list);
4238         for (i = 0; i < CXGB4_ULD_MAX; i++)
4239                 if (ulds[i].add)
4240                         uld_attach(adap, i);
4241         mutex_unlock(&uld_mutex);
4242 }
4243
4244 static void detach_ulds(struct adapter *adap)
4245 {
4246         unsigned int i;
4247
4248         mutex_lock(&uld_mutex);
4249         list_del(&adap->list_node);
4250         for (i = 0; i < CXGB4_ULD_MAX; i++)
4251                 if (adap->uld_handle[i]) {
4252                         ulds[i].state_change(adap->uld_handle[i],
4253                                              CXGB4_STATE_DETACH);
4254                         adap->uld_handle[i] = NULL;
4255                 }
4256         if (netevent_registered && list_empty(&adapter_list)) {
4257                 unregister_netevent_notifier(&cxgb4_netevent_nb);
4258                 netevent_registered = false;
4259         }
4260         mutex_unlock(&uld_mutex);
4261
4262         spin_lock(&adap_rcu_lock);
4263         list_del_rcu(&adap->rcu_node);
4264         spin_unlock(&adap_rcu_lock);
4265 }
4266
4267 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
4268 {
4269         unsigned int i;
4270
4271         mutex_lock(&uld_mutex);
4272         for (i = 0; i < CXGB4_ULD_MAX; i++)
4273                 if (adap->uld_handle[i])
4274                         ulds[i].state_change(adap->uld_handle[i], new_state);
4275         mutex_unlock(&uld_mutex);
4276 }
4277
4278 /**
4279  *      cxgb4_register_uld - register an upper-layer driver
4280  *      @type: the ULD type
4281  *      @p: the ULD methods
4282  *
4283  *      Registers an upper-layer driver with this driver and notifies the ULD
4284  *      about any presently available devices that support its type.  Returns
4285  *      %-EBUSY if a ULD of the same type is already registered.
4286  */
4287 int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p)
4288 {
4289         int ret = 0;
4290         struct adapter *adap;
4291
4292         if (type >= CXGB4_ULD_MAX)
4293                 return -EINVAL;
4294         mutex_lock(&uld_mutex);
4295         if (ulds[type].add) {
4296                 ret = -EBUSY;
4297                 goto out;
4298         }
4299         ulds[type] = *p;
4300         list_for_each_entry(adap, &adapter_list, list_node)
4301                 uld_attach(adap, type);
4302 out:    mutex_unlock(&uld_mutex);
4303         return ret;
4304 }
4305 EXPORT_SYMBOL(cxgb4_register_uld);
4306
4307 /**
4308  *      cxgb4_unregister_uld - unregister an upper-layer driver
4309  *      @type: the ULD type
4310  *
4311  *      Unregisters an existing upper-layer driver.
4312  */
4313 int cxgb4_unregister_uld(enum cxgb4_uld type)
4314 {
4315         struct adapter *adap;
4316
4317         if (type >= CXGB4_ULD_MAX)
4318                 return -EINVAL;
4319         mutex_lock(&uld_mutex);
4320         list_for_each_entry(adap, &adapter_list, list_node)
4321                 adap->uld_handle[type] = NULL;
4322         ulds[type].add = NULL;
4323         mutex_unlock(&uld_mutex);
4324         return 0;
4325 }
4326 EXPORT_SYMBOL(cxgb4_unregister_uld);
4327
4328 /* Check if netdev on which event is occured belongs to us or not. Return
4329  * success (true) if it belongs otherwise failure (false).
4330  * Called with rcu_read_lock() held.
4331  */
4332 static bool cxgb4_netdev(const struct net_device *netdev)
4333 {
4334         struct adapter *adap;
4335         int i;
4336
4337         list_for_each_entry_rcu(adap, &adap_rcu_list, rcu_node)
4338                 for (i = 0; i < MAX_NPORTS; i++)
4339                         if (adap->port[i] == netdev)
4340                                 return true;
4341         return false;
4342 }
4343
4344 static int clip_add(struct net_device *event_dev, struct inet6_ifaddr *ifa,
4345                     unsigned long event)
4346 {
4347         int ret = NOTIFY_DONE;
4348
4349         rcu_read_lock();
4350         if (cxgb4_netdev(event_dev)) {
4351                 switch (event) {
4352                 case NETDEV_UP:
4353                         ret = cxgb4_clip_get(event_dev,
4354                                 (const struct in6_addr *)ifa->addr.s6_addr);
4355                         if (ret < 0) {
4356                                 rcu_read_unlock();
4357                                 return ret;
4358                         }
4359                         ret = NOTIFY_OK;
4360                         break;
4361                 case NETDEV_DOWN:
4362                         cxgb4_clip_release(event_dev,
4363                                 (const struct in6_addr *)ifa->addr.s6_addr);
4364                         ret = NOTIFY_OK;
4365                         break;
4366                 default:
4367                         break;
4368                 }
4369         }
4370         rcu_read_unlock();
4371         return ret;
4372 }
4373
4374 static int cxgb4_inet6addr_handler(struct notifier_block *this,
4375                 unsigned long event, void *data)
4376 {
4377         struct inet6_ifaddr *ifa = data;
4378         struct net_device *event_dev;
4379         int ret = NOTIFY_DONE;
4380         struct bonding *bond = netdev_priv(ifa->idev->dev);
4381         struct list_head *iter;
4382         struct slave *slave;
4383         struct pci_dev *first_pdev = NULL;
4384
4385         if (ifa->idev->dev->priv_flags & IFF_802_1Q_VLAN) {
4386                 event_dev = vlan_dev_real_dev(ifa->idev->dev);
4387                 ret = clip_add(event_dev, ifa, event);
4388         } else if (ifa->idev->dev->flags & IFF_MASTER) {
4389                 /* It is possible that two different adapters are bonded in one
4390                  * bond. We need to find such different adapters and add clip
4391                  * in all of them only once.
4392                  */
4393                 read_lock(&bond->lock);
4394                 bond_for_each_slave(bond, slave, iter) {
4395                         if (!first_pdev) {
4396                                 ret = clip_add(slave->dev, ifa, event);
4397                                 /* If clip_add is success then only initialize
4398                                  * first_pdev since it means it is our device
4399                                  */
4400                                 if (ret == NOTIFY_OK)
4401                                         first_pdev = to_pci_dev(
4402                                                         slave->dev->dev.parent);
4403                         } else if (first_pdev !=
4404                                    to_pci_dev(slave->dev->dev.parent))
4405                                         ret = clip_add(slave->dev, ifa, event);
4406                 }
4407                 read_unlock(&bond->lock);
4408         } else
4409                 ret = clip_add(ifa->idev->dev, ifa, event);
4410
4411         return ret;
4412 }
4413
4414 static struct notifier_block cxgb4_inet6addr_notifier = {
4415         .notifier_call = cxgb4_inet6addr_handler
4416 };
4417
4418 /* Retrieves IPv6 addresses from a root device (bond, vlan) associated with
4419  * a physical device.
4420  * The physical device reference is needed to send the actul CLIP command.
4421  */
4422 static int update_dev_clip(struct net_device *root_dev, struct net_device *dev)
4423 {
4424         struct inet6_dev *idev = NULL;
4425         struct inet6_ifaddr *ifa;
4426         int ret = 0;
4427
4428         idev = __in6_dev_get(root_dev);
4429         if (!idev)
4430                 return ret;
4431
4432         read_lock_bh(&idev->lock);
4433         list_for_each_entry(ifa, &idev->addr_list, if_list) {
4434                 ret = cxgb4_clip_get(dev,
4435                                 (const struct in6_addr *)ifa->addr.s6_addr);
4436                 if (ret < 0)
4437                         break;
4438         }
4439         read_unlock_bh(&idev->lock);
4440
4441         return ret;
4442 }
4443
4444 static int update_root_dev_clip(struct net_device *dev)
4445 {
4446         struct net_device *root_dev = NULL;
4447         int i, ret = 0;
4448
4449         /* First populate the real net device's IPv6 addresses */
4450         ret = update_dev_clip(dev, dev);
4451         if (ret)
4452                 return ret;
4453
4454         /* Parse all bond and vlan devices layered on top of the physical dev */
4455         for (i = 0; i < VLAN_N_VID; i++) {
4456                 root_dev = __vlan_find_dev_deep_rcu(dev, htons(ETH_P_8021Q), i);
4457                 if (!root_dev)
4458                         continue;
4459
4460                 ret = update_dev_clip(root_dev, dev);
4461                 if (ret)
4462                         break;
4463         }
4464         return ret;
4465 }
4466
4467 static void update_clip(const struct adapter *adap)
4468 {
4469         int i;
4470         struct net_device *dev;
4471         int ret;
4472
4473         rcu_read_lock();
4474
4475         for (i = 0; i < MAX_NPORTS; i++) {
4476                 dev = adap->port[i];
4477                 ret = 0;
4478
4479                 if (dev)
4480                         ret = update_root_dev_clip(dev);
4481
4482                 if (ret < 0)
4483                         break;
4484         }
4485         rcu_read_unlock();
4486 }
4487
4488 /**
4489  *      cxgb_up - enable the adapter
4490  *      @adap: adapter being enabled
4491  *
4492  *      Called when the first port is enabled, this function performs the
4493  *      actions necessary to make an adapter operational, such as completing
4494  *      the initialization of HW modules, and enabling interrupts.
4495  *
4496  *      Must be called with the rtnl lock held.
4497  */
4498 static int cxgb_up(struct adapter *adap)
4499 {
4500         int err;
4501
4502         err = setup_sge_queues(adap);
4503         if (err)
4504                 goto out;
4505         err = setup_rss(adap);
4506         if (err)
4507                 goto freeq;
4508
4509         if (adap->flags & USING_MSIX) {
4510                 name_msix_vecs(adap);
4511                 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
4512                                   adap->msix_info[0].desc, adap);
4513                 if (err)
4514                         goto irq_err;
4515
4516                 err = request_msix_queue_irqs(adap);
4517                 if (err) {
4518                         free_irq(adap->msix_info[0].vec, adap);
4519                         goto irq_err;
4520                 }
4521         } else {
4522                 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
4523                                   (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
4524                                   adap->port[0]->name, adap);
4525                 if (err)
4526                         goto irq_err;
4527         }
4528         enable_rx(adap);
4529         t4_sge_start(adap);
4530         t4_intr_enable(adap);
4531         adap->flags |= FULL_INIT_DONE;
4532         notify_ulds(adap, CXGB4_STATE_UP);
4533         update_clip(adap);
4534  out:
4535         return err;
4536  irq_err:
4537         dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
4538  freeq:
4539         t4_free_sge_resources(adap);
4540         goto out;
4541 }
4542
4543 static void cxgb_down(struct adapter *adapter)
4544 {
4545         t4_intr_disable(adapter);
4546         cancel_work_sync(&adapter->tid_release_task);
4547         cancel_work_sync(&adapter->db_full_task);
4548         cancel_work_sync(&adapter->db_drop_task);
4549         adapter->tid_release_task_busy = false;
4550         adapter->tid_release_head = NULL;
4551
4552         if (adapter->flags & USING_MSIX) {
4553                 free_msix_queue_irqs(adapter);
4554                 free_irq(adapter->msix_info[0].vec, adapter);
4555         } else
4556                 free_irq(adapter->pdev->irq, adapter);
4557         quiesce_rx(adapter);
4558         t4_sge_stop(adapter);
4559         t4_free_sge_resources(adapter);
4560         adapter->flags &= ~FULL_INIT_DONE;
4561 }
4562
4563 /*
4564  * net_device operations
4565  */
4566 static int cxgb_open(struct net_device *dev)
4567 {
4568         int err;
4569         struct port_info *pi = netdev_priv(dev);
4570         struct adapter *adapter = pi->adapter;
4571
4572         netif_carrier_off(dev);
4573
4574         if (!(adapter->flags & FULL_INIT_DONE)) {
4575                 err = cxgb_up(adapter);
4576                 if (err < 0)
4577                         return err;
4578         }
4579
4580         err = link_start(dev);
4581         if (!err)
4582                 netif_tx_start_all_queues(dev);
4583         return err;
4584 }
4585
4586 static int cxgb_close(struct net_device *dev)
4587 {
4588         struct port_info *pi = netdev_priv(dev);
4589         struct adapter *adapter = pi->adapter;
4590
4591         netif_tx_stop_all_queues(dev);
4592         netif_carrier_off(dev);
4593         return t4_enable_vi(adapter, adapter->fn, pi->viid, false, false);
4594 }
4595
4596 /* Return an error number if the indicated filter isn't writable ...
4597  */
4598 static int writable_filter(struct filter_entry *f)
4599 {
4600         if (f->locked)
4601                 return -EPERM;
4602         if (f->pending)
4603                 return -EBUSY;
4604
4605         return 0;
4606 }
4607
4608 /* Delete the filter at the specified index (if valid).  The checks for all
4609  * the common problems with doing this like the filter being locked, currently
4610  * pending in another operation, etc.
4611  */
4612 static int delete_filter(struct adapter *adapter, unsigned int fidx)
4613 {
4614         struct filter_entry *f;
4615         int ret;
4616
4617         if (fidx >= adapter->tids.nftids + adapter->tids.nsftids)
4618                 return -EINVAL;
4619
4620         f = &adapter->tids.ftid_tab[fidx];
4621         ret = writable_filter(f);
4622         if (ret)
4623                 return ret;
4624         if (f->valid)
4625                 return del_filter_wr(adapter, fidx);
4626
4627         return 0;
4628 }
4629
4630 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
4631                 __be32 sip, __be16 sport, __be16 vlan,
4632                 unsigned int queue, unsigned char port, unsigned char mask)
4633 {
4634         int ret;
4635         struct filter_entry *f;
4636         struct adapter *adap;
4637         int i;
4638         u8 *val;
4639
4640         adap = netdev2adap(dev);
4641
4642         /* Adjust stid to correct filter index */
4643         stid -= adap->tids.sftid_base;
4644         stid += adap->tids.nftids;
4645
4646         /* Check to make sure the filter requested is writable ...
4647          */
4648         f = &adap->tids.ftid_tab[stid];
4649         ret = writable_filter(f);
4650         if (ret)
4651                 return ret;
4652
4653         /* Clear out any old resources being used by the filter before
4654          * we start constructing the new filter.
4655          */
4656         if (f->valid)
4657                 clear_filter(adap, f);
4658
4659         /* Clear out filter specifications */
4660         memset(&f->fs, 0, sizeof(struct ch_filter_specification));
4661         f->fs.val.lport = cpu_to_be16(sport);
4662         f->fs.mask.lport  = ~0;
4663         val = (u8 *)&sip;
4664         if ((val[0] | val[1] | val[2] | val[3]) != 0) {
4665                 for (i = 0; i < 4; i++) {
4666                         f->fs.val.lip[i] = val[i];
4667                         f->fs.mask.lip[i] = ~0;
4668                 }
4669                 if (adap->params.tp.vlan_pri_map & F_PORT) {
4670                         f->fs.val.iport = port;
4671                         f->fs.mask.iport = mask;
4672                 }
4673         }
4674
4675         if (adap->params.tp.vlan_pri_map & F_PROTOCOL) {
4676                 f->fs.val.proto = IPPROTO_TCP;
4677                 f->fs.mask.proto = ~0;
4678         }
4679
4680         f->fs.dirsteer = 1;
4681         f->fs.iq = queue;
4682         /* Mark filter as locked */
4683         f->locked = 1;
4684         f->fs.rpttid = 1;
4685
4686         ret = set_filter_wr(adap, stid);
4687         if (ret) {
4688                 clear_filter(adap, f);
4689                 return ret;
4690         }
4691
4692         return 0;
4693 }
4694 EXPORT_SYMBOL(cxgb4_create_server_filter);
4695
4696 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
4697                 unsigned int queue, bool ipv6)
4698 {
4699         int ret;
4700         struct filter_entry *f;
4701         struct adapter *adap;
4702
4703         adap = netdev2adap(dev);
4704
4705         /* Adjust stid to correct filter index */
4706         stid -= adap->tids.sftid_base;
4707         stid += adap->tids.nftids;
4708
4709         f = &adap->tids.ftid_tab[stid];
4710         /* Unlock the filter */
4711         f->locked = 0;
4712
4713         ret = delete_filter(adap, stid);
4714         if (ret)
4715                 return ret;
4716
4717         return 0;
4718 }
4719 EXPORT_SYMBOL(cxgb4_remove_server_filter);
4720
4721 static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev,
4722                                                 struct rtnl_link_stats64 *ns)
4723 {
4724         struct port_stats stats;
4725         struct port_info *p = netdev_priv(dev);
4726         struct adapter *adapter = p->adapter;
4727
4728         /* Block retrieving statistics during EEH error
4729          * recovery. Otherwise, the recovery might fail
4730          * and the PCI device will be removed permanently
4731          */
4732         spin_lock(&adapter->stats_lock);
4733         if (!netif_device_present(dev)) {
4734                 spin_unlock(&adapter->stats_lock);
4735                 return ns;
4736         }
4737         t4_get_port_stats(adapter, p->tx_chan, &stats);
4738         spin_unlock(&adapter->stats_lock);
4739
4740         ns->tx_bytes   = stats.tx_octets;
4741         ns->tx_packets = stats.tx_frames;
4742         ns->rx_bytes   = stats.rx_octets;
4743         ns->rx_packets = stats.rx_frames;
4744         ns->multicast  = stats.rx_mcast_frames;
4745
4746         /* detailed rx_errors */
4747         ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
4748                                stats.rx_runt;
4749         ns->rx_over_errors   = 0;
4750         ns->rx_crc_errors    = stats.rx_fcs_err;
4751         ns->rx_frame_errors  = stats.rx_symbol_err;
4752         ns->rx_fifo_errors   = stats.rx_ovflow0 + stats.rx_ovflow1 +
4753                                stats.rx_ovflow2 + stats.rx_ovflow3 +
4754                                stats.rx_trunc0 + stats.rx_trunc1 +
4755                                stats.rx_trunc2 + stats.rx_trunc3;
4756         ns->rx_missed_errors = 0;
4757
4758         /* detailed tx_errors */
4759         ns->tx_aborted_errors   = 0;
4760         ns->tx_carrier_errors   = 0;
4761         ns->tx_fifo_errors      = 0;
4762         ns->tx_heartbeat_errors = 0;
4763         ns->tx_window_errors    = 0;
4764
4765         ns->tx_errors = stats.tx_error_frames;
4766         ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
4767                 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
4768         return ns;
4769 }
4770
4771 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
4772 {
4773         unsigned int mbox;
4774         int ret = 0, prtad, devad;
4775         struct port_info *pi = netdev_priv(dev);
4776         struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
4777
4778         switch (cmd) {
4779         case SIOCGMIIPHY:
4780                 if (pi->mdio_addr < 0)
4781                         return -EOPNOTSUPP;
4782                 data->phy_id = pi->mdio_addr;
4783                 break;
4784         case SIOCGMIIREG:
4785         case SIOCSMIIREG:
4786                 if (mdio_phy_id_is_c45(data->phy_id)) {
4787                         prtad = mdio_phy_id_prtad(data->phy_id);
4788                         devad = mdio_phy_id_devad(data->phy_id);
4789                 } else if (data->phy_id < 32) {
4790                         prtad = data->phy_id;
4791                         devad = 0;
4792                         data->reg_num &= 0x1f;
4793                 } else
4794                         return -EINVAL;
4795
4796                 mbox = pi->adapter->fn;
4797                 if (cmd == SIOCGMIIREG)
4798                         ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
4799                                          data->reg_num, &data->val_out);
4800                 else
4801                         ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
4802                                          data->reg_num, data->val_in);
4803                 break;
4804         default:
4805                 return -EOPNOTSUPP;
4806         }
4807         return ret;
4808 }
4809
4810 static void cxgb_set_rxmode(struct net_device *dev)
4811 {
4812         /* unfortunately we can't return errors to the stack */
4813         set_rxmode(dev, -1, false);
4814 }
4815
4816 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
4817 {
4818         int ret;
4819         struct port_info *pi = netdev_priv(dev);
4820
4821         if (new_mtu < 81 || new_mtu > MAX_MTU)         /* accommodate SACK */
4822                 return -EINVAL;
4823         ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, new_mtu, -1,
4824                             -1, -1, -1, true);
4825         if (!ret)
4826                 dev->mtu = new_mtu;
4827         return ret;
4828 }
4829
4830 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
4831 {
4832         int ret;
4833         struct sockaddr *addr = p;
4834         struct port_info *pi = netdev_priv(dev);
4835
4836         if (!is_valid_ether_addr(addr->sa_data))
4837                 return -EADDRNOTAVAIL;
4838
4839         ret = t4_change_mac(pi->adapter, pi->adapter->fn, pi->viid,
4840                             pi->xact_addr_filt, addr->sa_data, true, true);
4841         if (ret < 0)
4842                 return ret;
4843
4844         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4845         pi->xact_addr_filt = ret;
4846         return 0;
4847 }
4848
4849 #ifdef CONFIG_NET_POLL_CONTROLLER
4850 static void cxgb_netpoll(struct net_device *dev)
4851 {
4852         struct port_info *pi = netdev_priv(dev);
4853         struct adapter *adap = pi->adapter;
4854
4855         if (adap->flags & USING_MSIX) {
4856                 int i;
4857                 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
4858
4859                 for (i = pi->nqsets; i; i--, rx++)
4860                         t4_sge_intr_msix(0, &rx->rspq);
4861         } else
4862                 t4_intr_handler(adap)(0, adap);
4863 }
4864 #endif
4865
4866 static const struct net_device_ops cxgb4_netdev_ops = {
4867         .ndo_open             = cxgb_open,
4868         .ndo_stop             = cxgb_close,
4869         .ndo_start_xmit       = t4_eth_xmit,
4870         .ndo_select_queue     = cxgb_select_queue,
4871         .ndo_get_stats64      = cxgb_get_stats,
4872         .ndo_set_rx_mode      = cxgb_set_rxmode,
4873         .ndo_set_mac_address  = cxgb_set_mac_addr,
4874         .ndo_set_features     = cxgb_set_features,
4875         .ndo_validate_addr    = eth_validate_addr,
4876         .ndo_do_ioctl         = cxgb_ioctl,
4877         .ndo_change_mtu       = cxgb_change_mtu,
4878 #ifdef CONFIG_NET_POLL_CONTROLLER
4879         .ndo_poll_controller  = cxgb_netpoll,
4880 #endif
4881 };
4882
4883 void t4_fatal_err(struct adapter *adap)
4884 {
4885         t4_set_reg_field(adap, SGE_CONTROL, GLOBALENABLE, 0);
4886         t4_intr_disable(adap);
4887         dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
4888 }
4889
4890 /* Return the specified PCI-E Configuration Space register from our Physical
4891  * Function.  We try first via a Firmware LDST Command since we prefer to let
4892  * the firmware own all of these registers, but if that fails we go for it
4893  * directly ourselves.
4894  */
4895 static u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
4896 {
4897         struct fw_ldst_cmd ldst_cmd;
4898         u32 val;
4899         int ret;
4900
4901         /* Construct and send the Firmware LDST Command to retrieve the
4902          * specified PCI-E Configuration Space register.
4903          */
4904         memset(&ldst_cmd, 0, sizeof(ldst_cmd));
4905         ldst_cmd.op_to_addrspace =
4906                 htonl(FW_CMD_OP(FW_LDST_CMD) |
4907                       FW_CMD_REQUEST |
4908                       FW_CMD_READ |
4909                       FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE));
4910         ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd));
4911         ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS(1);
4912         ldst_cmd.u.pcie.ctrl_to_fn =
4913                 (FW_LDST_CMD_LC | FW_LDST_CMD_FN(adap->fn));
4914         ldst_cmd.u.pcie.r = reg;
4915         ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
4916                          &ldst_cmd);
4917
4918         /* If the LDST Command suucceeded, exctract the returned register
4919          * value.  Otherwise read it directly ourself.
4920          */
4921         if (ret == 0)
4922                 val = ntohl(ldst_cmd.u.pcie.data[0]);
4923         else
4924                 t4_hw_pci_read_cfg4(adap, reg, &val);
4925
4926         return val;
4927 }
4928
4929 static void setup_memwin(struct adapter *adap)
4930 {
4931         u32 mem_win0_base, mem_win1_base, mem_win2_base, mem_win2_aperture;
4932
4933         if (is_t4(adap->params.chip)) {
4934                 u32 bar0;
4935
4936                 /* Truncation intentional: we only read the bottom 32-bits of
4937                  * the 64-bit BAR0/BAR1 ...  We use the hardware backdoor
4938                  * mechanism to read BAR0 instead of using
4939                  * pci_resource_start() because we could be operating from
4940                  * within a Virtual Machine which is trapping our accesses to
4941                  * our Configuration Space and we need to set up the PCI-E
4942                  * Memory Window decoders with the actual addresses which will
4943                  * be coming across the PCI-E link.
4944                  */
4945                 bar0 = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_0);
4946                 bar0 &= PCI_BASE_ADDRESS_MEM_MASK;
4947                 adap->t4_bar0 = bar0;
4948
4949                 mem_win0_base = bar0 + MEMWIN0_BASE;
4950                 mem_win1_base = bar0 + MEMWIN1_BASE;
4951                 mem_win2_base = bar0 + MEMWIN2_BASE;
4952                 mem_win2_aperture = MEMWIN2_APERTURE;
4953         } else {
4954                 /* For T5, only relative offset inside the PCIe BAR is passed */
4955                 mem_win0_base = MEMWIN0_BASE;
4956                 mem_win1_base = MEMWIN1_BASE;
4957                 mem_win2_base = MEMWIN2_BASE_T5;
4958                 mem_win2_aperture = MEMWIN2_APERTURE_T5;
4959         }
4960         t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 0),
4961                      mem_win0_base | BIR(0) |
4962                      WINDOW(ilog2(MEMWIN0_APERTURE) - 10));
4963         t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 1),
4964                      mem_win1_base | BIR(0) |
4965                      WINDOW(ilog2(MEMWIN1_APERTURE) - 10));
4966         t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2),
4967                      mem_win2_base | BIR(0) |
4968                      WINDOW(ilog2(mem_win2_aperture) - 10));
4969         t4_read_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2));
4970 }
4971
4972 static void setup_memwin_rdma(struct adapter *adap)
4973 {
4974         if (adap->vres.ocq.size) {
4975                 u32 start;
4976                 unsigned int sz_kb;
4977
4978                 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
4979                 start &= PCI_BASE_ADDRESS_MEM_MASK;
4980                 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
4981                 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
4982                 t4_write_reg(adap,
4983                              PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 3),
4984                              start | BIR(1) | WINDOW(ilog2(sz_kb)));
4985                 t4_write_reg(adap,
4986                              PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3),
4987                              adap->vres.ocq.start);
4988                 t4_read_reg(adap,
4989                             PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3));
4990         }
4991 }
4992
4993 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
4994 {
4995         u32 v;
4996         int ret;
4997
4998         /* get device capabilities */
4999         memset(c, 0, sizeof(*c));
5000         c->op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5001                                FW_CMD_REQUEST | FW_CMD_READ);
5002         c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
5003         ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), c);
5004         if (ret < 0)
5005                 return ret;
5006
5007         /* select capabilities we'll be using */
5008         if (c->niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
5009                 if (!vf_acls)
5010                         c->niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
5011                 else
5012                         c->niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
5013         } else if (vf_acls) {
5014                 dev_err(adap->pdev_dev, "virtualization ACLs not supported");
5015                 return ret;
5016         }
5017         c->op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5018                                FW_CMD_REQUEST | FW_CMD_WRITE);
5019         ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), NULL);
5020         if (ret < 0)
5021                 return ret;
5022
5023         ret = t4_config_glbl_rss(adap, adap->fn,
5024                                  FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
5025                                  FW_RSS_GLB_CONFIG_CMD_TNLMAPEN |
5026                                  FW_RSS_GLB_CONFIG_CMD_TNLALLLKP);
5027         if (ret < 0)
5028                 return ret;
5029
5030         ret = t4_cfg_pfvf(adap, adap->fn, adap->fn, 0, MAX_EGRQ, 64, MAX_INGQ,
5031                           0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF, FW_CMD_CAP_PF);
5032         if (ret < 0)
5033                 return ret;
5034
5035         t4_sge_init(adap);
5036
5037         /* tweak some settings */
5038         t4_write_reg(adap, TP_SHIFT_CNT, 0x64f8849);
5039         t4_write_reg(adap, ULP_RX_TDDP_PSZ, HPZ0(PAGE_SHIFT - 12));
5040         t4_write_reg(adap, TP_PIO_ADDR, TP_INGRESS_CONFIG);
5041         v = t4_read_reg(adap, TP_PIO_DATA);
5042         t4_write_reg(adap, TP_PIO_DATA, v & ~CSUM_HAS_PSEUDO_HDR);
5043
5044         /* first 4 Tx modulation queues point to consecutive Tx channels */
5045         adap->params.tp.tx_modq_map = 0xE4;
5046         t4_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP,
5047                      V_TX_MOD_QUEUE_REQ_MAP(adap->params.tp.tx_modq_map));
5048
5049         /* associate each Tx modulation queue with consecutive Tx channels */
5050         v = 0x84218421;
5051         t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
5052                           &v, 1, A_TP_TX_SCHED_HDR);
5053         t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
5054                           &v, 1, A_TP_TX_SCHED_FIFO);
5055         t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
5056                           &v, 1, A_TP_TX_SCHED_PCMD);
5057
5058 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
5059         if (is_offload(adap)) {
5060                 t4_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0,
5061                              V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
5062                              V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
5063                              V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
5064                              V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
5065                 t4_write_reg(adap, A_TP_TX_MOD_CHANNEL_WEIGHT,
5066                              V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
5067                              V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
5068                              V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
5069                              V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
5070         }
5071
5072         /* get basic stuff going */
5073         return t4_early_init(adap, adap->fn);
5074 }
5075
5076 /*
5077  * Max # of ATIDs.  The absolute HW max is 16K but we keep it lower.
5078  */
5079 #define MAX_ATIDS 8192U
5080
5081 /*
5082  * Phase 0 of initialization: contact FW, obtain config, perform basic init.
5083  *
5084  * If the firmware we're dealing with has Configuration File support, then
5085  * we use that to perform all configuration
5086  */
5087
5088 /*
5089  * Tweak configuration based on module parameters, etc.  Most of these have
5090  * defaults assigned to them by Firmware Configuration Files (if we're using
5091  * them) but need to be explicitly set if we're using hard-coded
5092  * initialization.  But even in the case of using Firmware Configuration
5093  * Files, we'd like to expose the ability to change these via module
5094  * parameters so these are essentially common tweaks/settings for
5095  * Configuration Files and hard-coded initialization ...
5096  */
5097 static int adap_init0_tweaks(struct adapter *adapter)
5098 {
5099         /*
5100          * Fix up various Host-Dependent Parameters like Page Size, Cache
5101          * Line Size, etc.  The firmware default is for a 4KB Page Size and
5102          * 64B Cache Line Size ...
5103          */
5104         t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
5105
5106         /*
5107          * Process module parameters which affect early initialization.
5108          */
5109         if (rx_dma_offset != 2 && rx_dma_offset != 0) {
5110                 dev_err(&adapter->pdev->dev,
5111                         "Ignoring illegal rx_dma_offset=%d, using 2\n",
5112                         rx_dma_offset);
5113                 rx_dma_offset = 2;
5114         }
5115         t4_set_reg_field(adapter, SGE_CONTROL,
5116                          PKTSHIFT_MASK,
5117                          PKTSHIFT(rx_dma_offset));
5118
5119         /*
5120          * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
5121          * adds the pseudo header itself.
5122          */
5123         t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG,
5124                                CSUM_HAS_PSEUDO_HDR, 0);
5125
5126         return 0;
5127 }
5128
5129 /*
5130  * Attempt to initialize the adapter via a Firmware Configuration File.
5131  */
5132 static int adap_init0_config(struct adapter *adapter, int reset)
5133 {
5134         struct fw_caps_config_cmd caps_cmd;
5135         const struct firmware *cf;
5136         unsigned long mtype = 0, maddr = 0;
5137         u32 finiver, finicsum, cfcsum;
5138         int ret;
5139         int config_issued = 0;
5140         char *fw_config_file, fw_config_file_path[256];
5141         char *config_name = NULL;
5142
5143         /*
5144          * Reset device if necessary.
5145          */
5146         if (reset) {
5147                 ret = t4_fw_reset(adapter, adapter->mbox,
5148                                   PIORSTMODE | PIORST);
5149                 if (ret < 0)
5150                         goto bye;
5151         }
5152
5153         /*
5154          * If we have a T4 configuration file under /lib/firmware/cxgb4/,
5155          * then use that.  Otherwise, use the configuration file stored
5156          * in the adapter flash ...
5157          */
5158         switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
5159         case CHELSIO_T4:
5160                 fw_config_file = FW4_CFNAME;
5161                 break;
5162         case CHELSIO_T5:
5163                 fw_config_file = FW5_CFNAME;
5164                 break;
5165         default:
5166                 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
5167                        adapter->pdev->device);
5168                 ret = -EINVAL;
5169                 goto bye;
5170         }
5171
5172         ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
5173         if (ret < 0) {
5174                 config_name = "On FLASH";
5175                 mtype = FW_MEMTYPE_CF_FLASH;
5176                 maddr = t4_flash_cfg_addr(adapter);
5177         } else {
5178                 u32 params[7], val[7];
5179
5180                 sprintf(fw_config_file_path,
5181                         "/lib/firmware/%s", fw_config_file);
5182                 config_name = fw_config_file_path;
5183
5184                 if (cf->size >= FLASH_CFG_MAX_SIZE)
5185                         ret = -ENOMEM;
5186                 else {
5187                         params[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5188                              FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CF));
5189                         ret = t4_query_params(adapter, adapter->mbox,
5190                                               adapter->fn, 0, 1, params, val);
5191                         if (ret == 0) {
5192                                 /*
5193                                  * For t4_memory_rw() below addresses and
5194                                  * sizes have to be in terms of multiples of 4
5195                                  * bytes.  So, if the Configuration File isn't
5196                                  * a multiple of 4 bytes in length we'll have
5197                                  * to write that out separately since we can't
5198                                  * guarantee that the bytes following the
5199                                  * residual byte in the buffer returned by
5200                                  * request_firmware() are zeroed out ...
5201                                  */
5202                                 size_t resid = cf->size & 0x3;
5203                                 size_t size = cf->size & ~0x3;
5204                                 __be32 *data = (__be32 *)cf->data;
5205
5206                                 mtype = FW_PARAMS_PARAM_Y_GET(val[0]);
5207                                 maddr = FW_PARAMS_PARAM_Z_GET(val[0]) << 16;
5208
5209                                 spin_lock(&adapter->win0_lock);
5210                                 ret = t4_memory_rw(adapter, 0, mtype, maddr,
5211                                                    size, data, T4_MEMORY_WRITE);
5212                                 if (ret == 0 && resid != 0) {
5213                                         union {
5214                                                 __be32 word;
5215                                                 char buf[4];
5216                                         } last;
5217                                         int i;
5218
5219                                         last.word = data[size >> 2];
5220                                         for (i = resid; i < 4; i++)
5221                                                 last.buf[i] = 0;
5222                                         ret = t4_memory_rw(adapter, 0, mtype,
5223                                                            maddr + size,
5224                                                            4, &last.word,
5225                                                            T4_MEMORY_WRITE);
5226                                 }
5227                                 spin_unlock(&adapter->win0_lock);
5228                         }
5229                 }
5230
5231                 release_firmware(cf);
5232                 if (ret)
5233                         goto bye;
5234         }
5235
5236         /*
5237          * Issue a Capability Configuration command to the firmware to get it
5238          * to parse the Configuration File.  We don't use t4_fw_config_file()
5239          * because we want the ability to modify various features after we've
5240          * processed the configuration file ...
5241          */
5242         memset(&caps_cmd, 0, sizeof(caps_cmd));
5243         caps_cmd.op_to_write =
5244                 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5245                       FW_CMD_REQUEST |
5246                       FW_CMD_READ);
5247         caps_cmd.cfvalid_to_len16 =
5248                 htonl(FW_CAPS_CONFIG_CMD_CFVALID |
5249                       FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
5250                       FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
5251                       FW_LEN16(caps_cmd));
5252         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5253                          &caps_cmd);
5254
5255         /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
5256          * Configuration File in FLASH), our last gasp effort is to use the
5257          * Firmware Configuration File which is embedded in the firmware.  A
5258          * very few early versions of the firmware didn't have one embedded
5259          * but we can ignore those.
5260          */
5261         if (ret == -ENOENT) {
5262                 memset(&caps_cmd, 0, sizeof(caps_cmd));
5263                 caps_cmd.op_to_write =
5264                         htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5265                                         FW_CMD_REQUEST |
5266                                         FW_CMD_READ);
5267                 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
5268                 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
5269                                 sizeof(caps_cmd), &caps_cmd);
5270                 config_name = "Firmware Default";
5271         }
5272
5273         config_issued = 1;
5274         if (ret < 0)
5275                 goto bye;
5276
5277         finiver = ntohl(caps_cmd.finiver);
5278         finicsum = ntohl(caps_cmd.finicsum);
5279         cfcsum = ntohl(caps_cmd.cfcsum);
5280         if (finicsum != cfcsum)
5281                 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
5282                          "mismatch: [fini] csum=%#x, computed csum=%#x\n",
5283                          finicsum, cfcsum);
5284
5285         /*
5286          * And now tell the firmware to use the configuration we just loaded.
5287          */
5288         caps_cmd.op_to_write =
5289                 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5290                       FW_CMD_REQUEST |
5291                       FW_CMD_WRITE);
5292         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
5293         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5294                          NULL);
5295         if (ret < 0)
5296                 goto bye;
5297
5298         /*
5299          * Tweak configuration based on system architecture, module
5300          * parameters, etc.
5301          */
5302         ret = adap_init0_tweaks(adapter);
5303         if (ret < 0)
5304                 goto bye;
5305
5306         /*
5307          * And finally tell the firmware to initialize itself using the
5308          * parameters from the Configuration File.
5309          */
5310         ret = t4_fw_initialize(adapter, adapter->mbox);
5311         if (ret < 0)
5312                 goto bye;
5313
5314         /*
5315          * Return successfully and note that we're operating with parameters
5316          * not supplied by the driver, rather than from hard-wired
5317          * initialization constants burried in the driver.
5318          */
5319         adapter->flags |= USING_SOFT_PARAMS;
5320         dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
5321                  "Configuration File \"%s\", version %#x, computed checksum %#x\n",
5322                  config_name, finiver, cfcsum);
5323         return 0;
5324
5325         /*
5326          * Something bad happened.  Return the error ...  (If the "error"
5327          * is that there's no Configuration File on the adapter we don't
5328          * want to issue a warning since this is fairly common.)
5329          */
5330 bye:
5331         if (config_issued && ret != -ENOENT)
5332                 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
5333                          config_name, -ret);
5334         return ret;
5335 }
5336
5337 /*
5338  * Attempt to initialize the adapter via hard-coded, driver supplied
5339  * parameters ...
5340  */
5341 static int adap_init0_no_config(struct adapter *adapter, int reset)
5342 {
5343         struct sge *s = &adapter->sge;
5344         struct fw_caps_config_cmd caps_cmd;
5345         u32 v;
5346         int i, ret;
5347
5348         /*
5349          * Reset device if necessary
5350          */
5351         if (reset) {
5352                 ret = t4_fw_reset(adapter, adapter->mbox,
5353                                   PIORSTMODE | PIORST);
5354                 if (ret < 0)
5355                         goto bye;
5356         }
5357
5358         /*
5359          * Get device capabilities and select which we'll be using.
5360          */
5361         memset(&caps_cmd, 0, sizeof(caps_cmd));
5362         caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5363                                      FW_CMD_REQUEST | FW_CMD_READ);
5364         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
5365         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5366                          &caps_cmd);
5367         if (ret < 0)
5368                 goto bye;
5369
5370         if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
5371                 if (!vf_acls)
5372                         caps_cmd.niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
5373                 else
5374                         caps_cmd.niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
5375         } else if (vf_acls) {
5376                 dev_err(adapter->pdev_dev, "virtualization ACLs not supported");
5377                 goto bye;
5378         }
5379         caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5380                               FW_CMD_REQUEST | FW_CMD_WRITE);
5381         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5382                          NULL);
5383         if (ret < 0)
5384                 goto bye;
5385
5386         /*
5387          * Tweak configuration based on system architecture, module
5388          * parameters, etc.
5389          */
5390         ret = adap_init0_tweaks(adapter);
5391         if (ret < 0)
5392                 goto bye;
5393
5394         /*
5395          * Select RSS Global Mode we want to use.  We use "Basic Virtual"
5396          * mode which maps each Virtual Interface to its own section of
5397          * the RSS Table and we turn on all map and hash enables ...
5398          */
5399         adapter->flags |= RSS_TNLALLLOOKUP;
5400         ret = t4_config_glbl_rss(adapter, adapter->mbox,
5401                                  FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
5402                                  FW_RSS_GLB_CONFIG_CMD_TNLMAPEN |
5403                                  FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ |
5404                                  ((adapter->flags & RSS_TNLALLLOOKUP) ?
5405                                         FW_RSS_GLB_CONFIG_CMD_TNLALLLKP : 0));
5406         if (ret < 0)
5407                 goto bye;
5408
5409         /*
5410          * Set up our own fundamental resource provisioning ...
5411          */
5412         ret = t4_cfg_pfvf(adapter, adapter->mbox, adapter->fn, 0,
5413                           PFRES_NEQ, PFRES_NETHCTRL,
5414                           PFRES_NIQFLINT, PFRES_NIQ,
5415                           PFRES_TC, PFRES_NVI,
5416                           FW_PFVF_CMD_CMASK_MASK,
5417                           pfvfres_pmask(adapter, adapter->fn, 0),
5418                           PFRES_NEXACTF,
5419                           PFRES_R_CAPS, PFRES_WX_CAPS);
5420         if (ret < 0)
5421                 goto bye;
5422
5423         /*
5424          * Perform low level SGE initialization.  We need to do this before we
5425          * send the firmware the INITIALIZE command because that will cause
5426          * any other PF Drivers which are waiting for the Master
5427          * Initialization to proceed forward.
5428          */
5429         for (i = 0; i < SGE_NTIMERS - 1; i++)
5430                 s->timer_val[i] = min(intr_holdoff[i], MAX_SGE_TIMERVAL);
5431         s->timer_val[SGE_NTIMERS - 1] = MAX_SGE_TIMERVAL;
5432         s->counter_val[0] = 1;
5433         for (i = 1; i < SGE_NCOUNTERS; i++)
5434                 s->counter_val[i] = min(intr_cnt[i - 1],
5435                                         THRESHOLD_0_GET(THRESHOLD_0_MASK));
5436         t4_sge_init(adapter);
5437
5438 #ifdef CONFIG_PCI_IOV
5439         /*
5440          * Provision resource limits for Virtual Functions.  We currently
5441          * grant them all the same static resource limits except for the Port
5442          * Access Rights Mask which we're assigning based on the PF.  All of
5443          * the static provisioning stuff for both the PF and VF really needs
5444          * to be managed in a persistent manner for each device which the
5445          * firmware controls.
5446          */
5447         {
5448                 int pf, vf;
5449
5450                 for (pf = 0; pf < ARRAY_SIZE(num_vf); pf++) {
5451                         if (num_vf[pf] <= 0)
5452                                 continue;
5453
5454                         /* VF numbering starts at 1! */
5455                         for (vf = 1; vf <= num_vf[pf]; vf++) {
5456                                 ret = t4_cfg_pfvf(adapter, adapter->mbox,
5457                                                   pf, vf,
5458                                                   VFRES_NEQ, VFRES_NETHCTRL,
5459                                                   VFRES_NIQFLINT, VFRES_NIQ,
5460                                                   VFRES_TC, VFRES_NVI,
5461                                                   FW_PFVF_CMD_CMASK_MASK,
5462                                                   pfvfres_pmask(
5463                                                   adapter, pf, vf),
5464                                                   VFRES_NEXACTF,
5465                                                   VFRES_R_CAPS, VFRES_WX_CAPS);
5466                                 if (ret < 0)
5467                                         dev_warn(adapter->pdev_dev,
5468                                                  "failed to "\
5469                                                  "provision pf/vf=%d/%d; "
5470                                                  "err=%d\n", pf, vf, ret);
5471                         }
5472                 }
5473         }
5474 #endif
5475
5476         /*
5477          * Set up the default filter mode.  Later we'll want to implement this
5478          * via a firmware command, etc. ...  This needs to be done before the
5479          * firmare initialization command ...  If the selected set of fields
5480          * isn't equal to the default value, we'll need to make sure that the
5481          * field selections will fit in the 36-bit budget.
5482          */
5483         if (tp_vlan_pri_map != TP_VLAN_PRI_MAP_DEFAULT) {
5484                 int j, bits = 0;
5485
5486                 for (j = TP_VLAN_PRI_MAP_FIRST; j <= TP_VLAN_PRI_MAP_LAST; j++)
5487                         switch (tp_vlan_pri_map & (1 << j)) {
5488                         case 0:
5489                                 /* compressed filter field not enabled */
5490                                 break;
5491                         case FCOE_MASK:
5492                                 bits +=  1;
5493                                 break;
5494                         case PORT_MASK:
5495                                 bits +=  3;
5496                                 break;
5497                         case VNIC_ID_MASK:
5498                                 bits += 17;
5499                                 break;
5500                         case VLAN_MASK:
5501                                 bits += 17;
5502                                 break;
5503                         case TOS_MASK:
5504                                 bits +=  8;
5505                                 break;
5506                         case PROTOCOL_MASK:
5507                                 bits +=  8;
5508                                 break;
5509                         case ETHERTYPE_MASK:
5510                                 bits += 16;
5511                                 break;
5512                         case MACMATCH_MASK:
5513                                 bits +=  9;
5514                                 break;
5515                         case MPSHITTYPE_MASK:
5516                                 bits +=  3;
5517                                 break;
5518                         case FRAGMENTATION_MASK:
5519                                 bits +=  1;
5520                                 break;
5521                         }
5522
5523                 if (bits > 36) {
5524                         dev_err(adapter->pdev_dev,
5525                                 "tp_vlan_pri_map=%#x needs %d bits > 36;"\
5526                                 " using %#x\n", tp_vlan_pri_map, bits,
5527                                 TP_VLAN_PRI_MAP_DEFAULT);
5528                         tp_vlan_pri_map = TP_VLAN_PRI_MAP_DEFAULT;
5529                 }
5530         }
5531         v = tp_vlan_pri_map;
5532         t4_write_indirect(adapter, TP_PIO_ADDR, TP_PIO_DATA,
5533                           &v, 1, TP_VLAN_PRI_MAP);
5534
5535         /*
5536          * We need Five Tuple Lookup mode to be set in TP_GLOBAL_CONFIG order
5537          * to support any of the compressed filter fields above.  Newer
5538          * versions of the firmware do this automatically but it doesn't hurt
5539          * to set it here.  Meanwhile, we do _not_ need to set Lookup Every
5540          * Packet in TP_INGRESS_CONFIG to support matching non-TCP packets
5541          * since the firmware automatically turns this on and off when we have
5542          * a non-zero number of filters active (since it does have a
5543          * performance impact).
5544          */
5545         if (tp_vlan_pri_map)
5546                 t4_set_reg_field(adapter, TP_GLOBAL_CONFIG,
5547                                  FIVETUPLELOOKUP_MASK,
5548                                  FIVETUPLELOOKUP_MASK);
5549
5550         /*
5551          * Tweak some settings.
5552          */
5553         t4_write_reg(adapter, TP_SHIFT_CNT, SYNSHIFTMAX(6) |
5554                      RXTSHIFTMAXR1(4) | RXTSHIFTMAXR2(15) |
5555                      PERSHIFTBACKOFFMAX(8) | PERSHIFTMAX(8) |
5556                      KEEPALIVEMAXR1(4) | KEEPALIVEMAXR2(9));
5557
5558         /*
5559          * Get basic stuff going by issuing the Firmware Initialize command.
5560          * Note that this _must_ be after all PFVF commands ...
5561          */
5562         ret = t4_fw_initialize(adapter, adapter->mbox);
5563         if (ret < 0)
5564                 goto bye;
5565
5566         /*
5567          * Return successfully!
5568          */
5569         dev_info(adapter->pdev_dev, "Successfully configured using built-in "\
5570                  "driver parameters\n");
5571         return 0;
5572
5573         /*
5574          * Something bad happened.  Return the error ...
5575          */
5576 bye:
5577         return ret;
5578 }
5579
5580 static struct fw_info fw_info_array[] = {
5581         {
5582                 .chip = CHELSIO_T4,
5583                 .fs_name = FW4_CFNAME,
5584                 .fw_mod_name = FW4_FNAME,
5585                 .fw_hdr = {
5586                         .chip = FW_HDR_CHIP_T4,
5587                         .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
5588                         .intfver_nic = FW_INTFVER(T4, NIC),
5589                         .intfver_vnic = FW_INTFVER(T4, VNIC),
5590                         .intfver_ri = FW_INTFVER(T4, RI),
5591                         .intfver_iscsi = FW_INTFVER(T4, ISCSI),
5592                         .intfver_fcoe = FW_INTFVER(T4, FCOE),
5593                 },
5594         }, {
5595                 .chip = CHELSIO_T5,
5596                 .fs_name = FW5_CFNAME,
5597                 .fw_mod_name = FW5_FNAME,
5598                 .fw_hdr = {
5599                         .chip = FW_HDR_CHIP_T5,
5600                         .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
5601                         .intfver_nic = FW_INTFVER(T5, NIC),
5602                         .intfver_vnic = FW_INTFVER(T5, VNIC),
5603                         .intfver_ri = FW_INTFVER(T5, RI),
5604                         .intfver_iscsi = FW_INTFVER(T5, ISCSI),
5605                         .intfver_fcoe = FW_INTFVER(T5, FCOE),
5606                 },
5607         }
5608 };
5609
5610 static struct fw_info *find_fw_info(int chip)
5611 {
5612         int i;
5613
5614         for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
5615                 if (fw_info_array[i].chip == chip)
5616                         return &fw_info_array[i];
5617         }
5618         return NULL;
5619 }
5620
5621 /*
5622  * Phase 0 of initialization: contact FW, obtain config, perform basic init.
5623  */
5624 static int adap_init0(struct adapter *adap)
5625 {
5626         int ret;
5627         u32 v, port_vec;
5628         enum dev_state state;
5629         u32 params[7], val[7];
5630         struct fw_caps_config_cmd caps_cmd;
5631         int reset = 1;
5632
5633         /*
5634          * Contact FW, advertising Master capability (and potentially forcing
5635          * ourselves as the Master PF if our module parameter force_init is
5636          * set).
5637          */
5638         ret = t4_fw_hello(adap, adap->mbox, adap->fn,
5639                           force_init ? MASTER_MUST : MASTER_MAY,
5640                           &state);
5641         if (ret < 0) {
5642                 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
5643                         ret);
5644                 return ret;
5645         }
5646         if (ret == adap->mbox)
5647                 adap->flags |= MASTER_PF;
5648         if (force_init && state == DEV_STATE_INIT)
5649                 state = DEV_STATE_UNINIT;
5650
5651         /*
5652          * If we're the Master PF Driver and the device is uninitialized,
5653          * then let's consider upgrading the firmware ...  (We always want
5654          * to check the firmware version number in order to A. get it for
5655          * later reporting and B. to warn if the currently loaded firmware
5656          * is excessively mismatched relative to the driver.)
5657          */
5658         t4_get_fw_version(adap, &adap->params.fw_vers);
5659         t4_get_tp_version(adap, &adap->params.tp_vers);
5660         if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
5661                 struct fw_info *fw_info;
5662                 struct fw_hdr *card_fw;
5663                 const struct firmware *fw;
5664                 const u8 *fw_data = NULL;
5665                 unsigned int fw_size = 0;
5666
5667                 /* This is the firmware whose headers the driver was compiled
5668                  * against
5669                  */
5670                 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
5671                 if (fw_info == NULL) {
5672                         dev_err(adap->pdev_dev,
5673                                 "unable to get firmware info for chip %d.\n",
5674                                 CHELSIO_CHIP_VERSION(adap->params.chip));
5675                         return -EINVAL;
5676                 }
5677
5678                 /* allocate memory to read the header of the firmware on the
5679                  * card
5680                  */
5681                 card_fw = t4_alloc_mem(sizeof(*card_fw));
5682
5683                 /* Get FW from from /lib/firmware/ */
5684                 ret = request_firmware(&fw, fw_info->fw_mod_name,
5685                                        adap->pdev_dev);
5686                 if (ret < 0) {
5687                         dev_err(adap->pdev_dev,
5688                                 "unable to load firmware image %s, error %d\n",
5689                                 fw_info->fw_mod_name, ret);
5690                 } else {
5691                         fw_data = fw->data;
5692                         fw_size = fw->size;
5693                 }
5694
5695                 /* upgrade FW logic */
5696                 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
5697                                  state, &reset);
5698
5699                 /* Cleaning up */
5700                 if (fw != NULL)
5701                         release_firmware(fw);
5702                 t4_free_mem(card_fw);
5703
5704                 if (ret < 0)
5705                         goto bye;
5706         }
5707
5708         /*
5709          * Grab VPD parameters.  This should be done after we establish a
5710          * connection to the firmware since some of the VPD parameters
5711          * (notably the Core Clock frequency) are retrieved via requests to
5712          * the firmware.  On the other hand, we need these fairly early on
5713          * so we do this right after getting ahold of the firmware.
5714          */
5715         ret = get_vpd_params(adap, &adap->params.vpd);
5716         if (ret < 0)
5717                 goto bye;
5718
5719         /*
5720          * Find out what ports are available to us.  Note that we need to do
5721          * this before calling adap_init0_no_config() since it needs nports
5722          * and portvec ...
5723          */
5724         v =
5725             FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5726             FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
5727         ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1, &v, &port_vec);
5728         if (ret < 0)
5729                 goto bye;
5730
5731         adap->params.nports = hweight32(port_vec);
5732         adap->params.portvec = port_vec;
5733
5734         /*
5735          * If the firmware is initialized already (and we're not forcing a
5736          * master initialization), note that we're living with existing
5737          * adapter parameters.  Otherwise, it's time to try initializing the
5738          * adapter ...
5739          */
5740         if (state == DEV_STATE_INIT) {
5741                 dev_info(adap->pdev_dev, "Coming up as %s: "\
5742                          "Adapter already initialized\n",
5743                          adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
5744                 adap->flags |= USING_SOFT_PARAMS;
5745         } else {
5746                 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
5747                          "Initializing adapter\n");
5748
5749                 /*
5750                  * If the firmware doesn't support Configuration
5751                  * Files warn user and exit,
5752                  */
5753                 if (ret < 0)
5754                         dev_warn(adap->pdev_dev, "Firmware doesn't support "
5755                                  "configuration file.\n");
5756                 if (force_old_init)
5757                         ret = adap_init0_no_config(adap, reset);
5758                 else {
5759                         /*
5760                          * Find out whether we're dealing with a version of
5761                          * the firmware which has configuration file support.
5762                          */
5763                         params[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5764                                      FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CF));
5765                         ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1,
5766                                               params, val);
5767
5768                         /*
5769                          * If the firmware doesn't support Configuration
5770                          * Files, use the old Driver-based, hard-wired
5771                          * initialization.  Otherwise, try using the
5772                          * Configuration File support and fall back to the
5773                          * Driver-based initialization if there's no
5774                          * Configuration File found.
5775                          */
5776                         if (ret < 0)
5777                                 ret = adap_init0_no_config(adap, reset);
5778                         else {
5779                                 /*
5780                                  * The firmware provides us with a memory
5781                                  * buffer where we can load a Configuration
5782                                  * File from the host if we want to override
5783                                  * the Configuration File in flash.
5784                                  */
5785
5786                                 ret = adap_init0_config(adap, reset);
5787                                 if (ret == -ENOENT) {
5788                                         dev_info(adap->pdev_dev,
5789                                             "No Configuration File present "
5790                                             "on adapter. Using hard-wired "
5791                                             "configuration parameters.\n");
5792                                         ret = adap_init0_no_config(adap, reset);
5793                                 }
5794                         }
5795                 }
5796                 if (ret < 0) {
5797                         dev_err(adap->pdev_dev,
5798                                 "could not initialize adapter, error %d\n",
5799                                 -ret);
5800                         goto bye;
5801                 }
5802         }
5803
5804         /*
5805          * If we're living with non-hard-coded parameters (either from a
5806          * Firmware Configuration File or values programmed by a different PF
5807          * Driver), give the SGE code a chance to pull in anything that it
5808          * needs ...  Note that this must be called after we retrieve our VPD
5809          * parameters in order to know how to convert core ticks to seconds.
5810          */
5811         if (adap->flags & USING_SOFT_PARAMS) {
5812                 ret = t4_sge_init(adap);
5813                 if (ret < 0)
5814                         goto bye;
5815         }
5816
5817         if (is_bypass_device(adap->pdev->device))
5818                 adap->params.bypass = 1;
5819
5820         /*
5821          * Grab some of our basic fundamental operating parameters.
5822          */
5823 #define FW_PARAM_DEV(param) \
5824         (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
5825         FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
5826
5827 #define FW_PARAM_PFVF(param) \
5828         FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
5829         FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)|  \
5830         FW_PARAMS_PARAM_Y(0) | \
5831         FW_PARAMS_PARAM_Z(0)
5832
5833         params[0] = FW_PARAM_PFVF(EQ_START);
5834         params[1] = FW_PARAM_PFVF(L2T_START);
5835         params[2] = FW_PARAM_PFVF(L2T_END);
5836         params[3] = FW_PARAM_PFVF(FILTER_START);
5837         params[4] = FW_PARAM_PFVF(FILTER_END);
5838         params[5] = FW_PARAM_PFVF(IQFLINT_START);
5839         ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6, params, val);
5840         if (ret < 0)
5841                 goto bye;
5842         adap->sge.egr_start = val[0];
5843         adap->l2t_start = val[1];
5844         adap->l2t_end = val[2];
5845         adap->tids.ftid_base = val[3];
5846         adap->tids.nftids = val[4] - val[3] + 1;
5847         adap->sge.ingr_start = val[5];
5848
5849         /* query params related to active filter region */
5850         params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
5851         params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
5852         ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params, val);
5853         /* If Active filter size is set we enable establishing
5854          * offload connection through firmware work request
5855          */
5856         if ((val[0] != val[1]) && (ret >= 0)) {
5857                 adap->flags |= FW_OFLD_CONN;
5858                 adap->tids.aftid_base = val[0];
5859                 adap->tids.aftid_end = val[1];
5860         }
5861
5862         /* If we're running on newer firmware, let it know that we're
5863          * prepared to deal with encapsulated CPL messages.  Older
5864          * firmware won't understand this and we'll just get
5865          * unencapsulated messages ...
5866          */
5867         params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
5868         val[0] = 1;
5869         (void) t4_set_params(adap, adap->mbox, adap->fn, 0, 1, params, val);
5870
5871         /*
5872          * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
5873          * capability.  Earlier versions of the firmware didn't have the
5874          * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
5875          * permission to use ULPTX MEMWRITE DSGL.
5876          */
5877         if (is_t4(adap->params.chip)) {
5878                 adap->params.ulptx_memwrite_dsgl = false;
5879         } else {
5880                 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
5881                 ret = t4_query_params(adap, adap->mbox, adap->fn, 0,
5882                                       1, params, val);
5883                 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
5884         }
5885
5886         /*
5887          * Get device capabilities so we can determine what resources we need
5888          * to manage.
5889          */
5890         memset(&caps_cmd, 0, sizeof(caps_cmd));
5891         caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5892                                      FW_CMD_REQUEST | FW_CMD_READ);
5893         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
5894         ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
5895                          &caps_cmd);
5896         if (ret < 0)
5897                 goto bye;
5898
5899         if (caps_cmd.ofldcaps) {
5900                 /* query offload-related parameters */
5901                 params[0] = FW_PARAM_DEV(NTID);
5902                 params[1] = FW_PARAM_PFVF(SERVER_START);
5903                 params[2] = FW_PARAM_PFVF(SERVER_END);
5904                 params[3] = FW_PARAM_PFVF(TDDP_START);
5905                 params[4] = FW_PARAM_PFVF(TDDP_END);
5906                 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
5907                 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
5908                                       params, val);
5909                 if (ret < 0)
5910                         goto bye;
5911                 adap->tids.ntids = val[0];
5912                 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
5913                 adap->tids.stid_base = val[1];
5914                 adap->tids.nstids = val[2] - val[1] + 1;
5915                 /*
5916                  * Setup server filter region. Divide the availble filter
5917                  * region into two parts. Regular filters get 1/3rd and server
5918                  * filters get 2/3rd part. This is only enabled if workarond
5919                  * path is enabled.
5920                  * 1. For regular filters.
5921                  * 2. Server filter: This are special filters which are used
5922                  * to redirect SYN packets to offload queue.
5923                  */
5924                 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
5925                         adap->tids.sftid_base = adap->tids.ftid_base +
5926                                         DIV_ROUND_UP(adap->tids.nftids, 3);
5927                         adap->tids.nsftids = adap->tids.nftids -
5928                                          DIV_ROUND_UP(adap->tids.nftids, 3);
5929                         adap->tids.nftids = adap->tids.sftid_base -
5930                                                 adap->tids.ftid_base;
5931                 }
5932                 adap->vres.ddp.start = val[3];
5933                 adap->vres.ddp.size = val[4] - val[3] + 1;
5934                 adap->params.ofldq_wr_cred = val[5];
5935
5936                 adap->params.offload = 1;
5937         }
5938         if (caps_cmd.rdmacaps) {
5939                 params[0] = FW_PARAM_PFVF(STAG_START);
5940                 params[1] = FW_PARAM_PFVF(STAG_END);
5941                 params[2] = FW_PARAM_PFVF(RQ_START);
5942                 params[3] = FW_PARAM_PFVF(RQ_END);
5943                 params[4] = FW_PARAM_PFVF(PBL_START);
5944                 params[5] = FW_PARAM_PFVF(PBL_END);
5945                 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
5946                                       params, val);
5947                 if (ret < 0)
5948                         goto bye;
5949                 adap->vres.stag.start = val[0];
5950                 adap->vres.stag.size = val[1] - val[0] + 1;
5951                 adap->vres.rq.start = val[2];
5952                 adap->vres.rq.size = val[3] - val[2] + 1;
5953                 adap->vres.pbl.start = val[4];
5954                 adap->vres.pbl.size = val[5] - val[4] + 1;
5955
5956                 params[0] = FW_PARAM_PFVF(SQRQ_START);
5957                 params[1] = FW_PARAM_PFVF(SQRQ_END);
5958                 params[2] = FW_PARAM_PFVF(CQ_START);
5959                 params[3] = FW_PARAM_PFVF(CQ_END);
5960                 params[4] = FW_PARAM_PFVF(OCQ_START);
5961                 params[5] = FW_PARAM_PFVF(OCQ_END);
5962                 ret = t4_query_params(adap, 0, 0, 0, 6, params, val);
5963                 if (ret < 0)
5964                         goto bye;
5965                 adap->vres.qp.start = val[0];
5966                 adap->vres.qp.size = val[1] - val[0] + 1;
5967                 adap->vres.cq.start = val[2];
5968                 adap->vres.cq.size = val[3] - val[2] + 1;
5969                 adap->vres.ocq.start = val[4];
5970                 adap->vres.ocq.size = val[5] - val[4] + 1;
5971
5972                 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
5973                 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
5974                 ret = t4_query_params(adap, 0, 0, 0, 2, params, val);
5975                 if (ret < 0) {
5976                         adap->params.max_ordird_qp = 8;
5977                         adap->params.max_ird_adapter = 32 * adap->tids.ntids;
5978                         ret = 0;
5979                 } else {
5980                         adap->params.max_ordird_qp = val[0];
5981                         adap->params.max_ird_adapter = val[1];
5982                 }
5983                 dev_info(adap->pdev_dev,
5984                          "max_ordird_qp %d max_ird_adapter %d\n",
5985                          adap->params.max_ordird_qp,
5986                          adap->params.max_ird_adapter);
5987         }
5988         if (caps_cmd.iscsicaps) {
5989                 params[0] = FW_PARAM_PFVF(ISCSI_START);
5990                 params[1] = FW_PARAM_PFVF(ISCSI_END);
5991                 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2,
5992                                       params, val);
5993                 if (ret < 0)
5994                         goto bye;
5995                 adap->vres.iscsi.start = val[0];
5996                 adap->vres.iscsi.size = val[1] - val[0] + 1;
5997         }
5998 #undef FW_PARAM_PFVF
5999 #undef FW_PARAM_DEV
6000
6001         /* The MTU/MSS Table is initialized by now, so load their values.  If
6002          * we're initializing the adapter, then we'll make any modifications
6003          * we want to the MTU/MSS Table and also initialize the congestion
6004          * parameters.
6005          */
6006         t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
6007         if (state != DEV_STATE_INIT) {
6008                 int i;
6009
6010                 /* The default MTU Table contains values 1492 and 1500.
6011                  * However, for TCP, it's better to have two values which are
6012                  * a multiple of 8 +/- 4 bytes apart near this popular MTU.
6013                  * This allows us to have a TCP Data Payload which is a
6014                  * multiple of 8 regardless of what combination of TCP Options
6015                  * are in use (always a multiple of 4 bytes) which is
6016                  * important for performance reasons.  For instance, if no
6017                  * options are in use, then we have a 20-byte IP header and a
6018                  * 20-byte TCP header.  In this case, a 1500-byte MSS would
6019                  * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
6020                  * which is not a multiple of 8.  So using an MSS of 1488 in
6021                  * this case results in a TCP Data Payload of 1448 bytes which
6022                  * is a multiple of 8.  On the other hand, if 12-byte TCP Time
6023                  * Stamps have been negotiated, then an MTU of 1500 bytes
6024                  * results in a TCP Data Payload of 1448 bytes which, as
6025                  * above, is a multiple of 8 bytes ...
6026                  */
6027                 for (i = 0; i < NMTUS; i++)
6028                         if (adap->params.mtus[i] == 1492) {
6029                                 adap->params.mtus[i] = 1488;
6030                                 break;
6031                         }
6032
6033                 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
6034                              adap->params.b_wnd);
6035         }
6036         t4_init_tp_params(adap);
6037         adap->flags |= FW_OK;
6038         return 0;
6039
6040         /*
6041          * Something bad happened.  If a command timed out or failed with EIO
6042          * FW does not operate within its spec or something catastrophic
6043          * happened to HW/FW, stop issuing commands.
6044          */
6045 bye:
6046         if (ret != -ETIMEDOUT && ret != -EIO)
6047                 t4_fw_bye(adap, adap->mbox);
6048         return ret;
6049 }
6050
6051 /* EEH callbacks */
6052
6053 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
6054                                          pci_channel_state_t state)
6055 {
6056         int i;
6057         struct adapter *adap = pci_get_drvdata(pdev);
6058
6059         if (!adap)
6060                 goto out;
6061
6062         rtnl_lock();
6063         adap->flags &= ~FW_OK;
6064         notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
6065         spin_lock(&adap->stats_lock);
6066         for_each_port(adap, i) {
6067                 struct net_device *dev = adap->port[i];
6068
6069                 netif_device_detach(dev);
6070                 netif_carrier_off(dev);
6071         }
6072         spin_unlock(&adap->stats_lock);
6073         if (adap->flags & FULL_INIT_DONE)
6074                 cxgb_down(adap);
6075         rtnl_unlock();
6076         if ((adap->flags & DEV_ENABLED)) {
6077                 pci_disable_device(pdev);
6078                 adap->flags &= ~DEV_ENABLED;
6079         }
6080 out:    return state == pci_channel_io_perm_failure ?
6081                 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
6082 }
6083
6084 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
6085 {
6086         int i, ret;
6087         struct fw_caps_config_cmd c;
6088         struct adapter *adap = pci_get_drvdata(pdev);
6089
6090         if (!adap) {
6091                 pci_restore_state(pdev);
6092                 pci_save_state(pdev);
6093                 return PCI_ERS_RESULT_RECOVERED;
6094         }
6095
6096         if (!(adap->flags & DEV_ENABLED)) {
6097                 if (pci_enable_device(pdev)) {
6098                         dev_err(&pdev->dev, "Cannot reenable PCI "
6099                                             "device after reset\n");
6100                         return PCI_ERS_RESULT_DISCONNECT;
6101                 }
6102                 adap->flags |= DEV_ENABLED;
6103         }
6104
6105         pci_set_master(pdev);
6106         pci_restore_state(pdev);
6107         pci_save_state(pdev);
6108         pci_cleanup_aer_uncorrect_error_status(pdev);
6109
6110         if (t4_wait_dev_ready(adap) < 0)
6111                 return PCI_ERS_RESULT_DISCONNECT;
6112         if (t4_fw_hello(adap, adap->fn, adap->fn, MASTER_MUST, NULL) < 0)
6113                 return PCI_ERS_RESULT_DISCONNECT;
6114         adap->flags |= FW_OK;
6115         if (adap_init1(adap, &c))
6116                 return PCI_ERS_RESULT_DISCONNECT;
6117
6118         for_each_port(adap, i) {
6119                 struct port_info *p = adap2pinfo(adap, i);
6120
6121                 ret = t4_alloc_vi(adap, adap->fn, p->tx_chan, adap->fn, 0, 1,
6122                                   NULL, NULL);
6123                 if (ret < 0)
6124                         return PCI_ERS_RESULT_DISCONNECT;
6125                 p->viid = ret;
6126                 p->xact_addr_filt = -1;
6127         }
6128
6129         t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
6130                      adap->params.b_wnd);
6131         setup_memwin(adap);
6132         if (cxgb_up(adap))
6133                 return PCI_ERS_RESULT_DISCONNECT;
6134         return PCI_ERS_RESULT_RECOVERED;
6135 }
6136
6137 static void eeh_resume(struct pci_dev *pdev)
6138 {
6139         int i;
6140         struct adapter *adap = pci_get_drvdata(pdev);
6141
6142         if (!adap)
6143                 return;
6144
6145         rtnl_lock();
6146         for_each_port(adap, i) {
6147                 struct net_device *dev = adap->port[i];
6148
6149                 if (netif_running(dev)) {
6150                         link_start(dev);
6151                         cxgb_set_rxmode(dev);
6152                 }
6153                 netif_device_attach(dev);
6154         }
6155         rtnl_unlock();
6156 }
6157
6158 static const struct pci_error_handlers cxgb4_eeh = {
6159         .error_detected = eeh_err_detected,
6160         .slot_reset     = eeh_slot_reset,
6161         .resume         = eeh_resume,
6162 };
6163
6164 static inline bool is_x_10g_port(const struct link_config *lc)
6165 {
6166         return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0 ||
6167                (lc->supported & FW_PORT_CAP_SPEED_40G) != 0;
6168 }
6169
6170 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
6171                              unsigned int us, unsigned int cnt,
6172                              unsigned int size, unsigned int iqe_size)
6173 {
6174         q->adap = adap;
6175         set_rspq_intr_params(q, us, cnt);
6176         q->iqe_len = iqe_size;
6177         q->size = size;
6178 }
6179
6180 /*
6181  * Perform default configuration of DMA queues depending on the number and type
6182  * of ports we found and the number of available CPUs.  Most settings can be
6183  * modified by the admin prior to actual use.
6184  */
6185 static void cfg_queues(struct adapter *adap)
6186 {
6187         struct sge *s = &adap->sge;
6188         int i, n10g = 0, qidx = 0;
6189 #ifndef CONFIG_CHELSIO_T4_DCB
6190         int q10g = 0;
6191 #endif
6192         int ciq_size;
6193
6194         for_each_port(adap, i)
6195                 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
6196 #ifdef CONFIG_CHELSIO_T4_DCB
6197         /* For Data Center Bridging support we need to be able to support up
6198          * to 8 Traffic Priorities; each of which will be assigned to its
6199          * own TX Queue in order to prevent Head-Of-Line Blocking.
6200          */
6201         if (adap->params.nports * 8 > MAX_ETH_QSETS) {
6202                 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n",
6203                         MAX_ETH_QSETS, adap->params.nports * 8);
6204                 BUG_ON(1);
6205         }
6206
6207         for_each_port(adap, i) {
6208                 struct port_info *pi = adap2pinfo(adap, i);
6209
6210                 pi->first_qset = qidx;
6211                 pi->nqsets = 8;
6212                 qidx += pi->nqsets;
6213         }
6214 #else /* !CONFIG_CHELSIO_T4_DCB */
6215         /*
6216          * We default to 1 queue per non-10G port and up to # of cores queues
6217          * per 10G port.
6218          */
6219         if (n10g)
6220                 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
6221         if (q10g > netif_get_num_default_rss_queues())
6222                 q10g = netif_get_num_default_rss_queues();
6223
6224         for_each_port(adap, i) {
6225                 struct port_info *pi = adap2pinfo(adap, i);
6226
6227                 pi->first_qset = qidx;
6228                 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
6229                 qidx += pi->nqsets;
6230         }
6231 #endif /* !CONFIG_CHELSIO_T4_DCB */
6232
6233         s->ethqsets = qidx;
6234         s->max_ethqsets = qidx;   /* MSI-X may lower it later */
6235
6236         if (is_offload(adap)) {
6237                 /*
6238                  * For offload we use 1 queue/channel if all ports are up to 1G,
6239                  * otherwise we divide all available queues amongst the channels
6240                  * capped by the number of available cores.
6241                  */
6242                 if (n10g) {
6243                         i = min_t(int, ARRAY_SIZE(s->ofldrxq),
6244                                   num_online_cpus());
6245                         s->ofldqsets = roundup(i, adap->params.nports);
6246                 } else
6247                         s->ofldqsets = adap->params.nports;
6248                 /* For RDMA one Rx queue per channel suffices */
6249                 s->rdmaqs = adap->params.nports;
6250                 s->rdmaciqs = adap->params.nports;
6251         }
6252
6253         for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
6254                 struct sge_eth_rxq *r = &s->ethrxq[i];
6255
6256                 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
6257                 r->fl.size = 72;
6258         }
6259
6260         for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
6261                 s->ethtxq[i].q.size = 1024;
6262
6263         for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
6264                 s->ctrlq[i].q.size = 512;
6265
6266         for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++)
6267                 s->ofldtxq[i].q.size = 1024;
6268
6269         for (i = 0; i < ARRAY_SIZE(s->ofldrxq); i++) {
6270                 struct sge_ofld_rxq *r = &s->ofldrxq[i];
6271
6272                 init_rspq(adap, &r->rspq, 5, 1, 1024, 64);
6273                 r->rspq.uld = CXGB4_ULD_ISCSI;
6274                 r->fl.size = 72;
6275         }
6276
6277         for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) {
6278                 struct sge_ofld_rxq *r = &s->rdmarxq[i];
6279
6280                 init_rspq(adap, &r->rspq, 5, 1, 511, 64);
6281                 r->rspq.uld = CXGB4_ULD_RDMA;
6282                 r->fl.size = 72;
6283         }
6284
6285         ciq_size = 64 + adap->vres.cq.size + adap->tids.nftids;
6286         if (ciq_size > SGE_MAX_IQ_SIZE) {
6287                 CH_WARN(adap, "CIQ size too small for available IQs\n");
6288                 ciq_size = SGE_MAX_IQ_SIZE;
6289         }
6290
6291         for (i = 0; i < ARRAY_SIZE(s->rdmaciq); i++) {
6292                 struct sge_ofld_rxq *r = &s->rdmaciq[i];
6293
6294                 init_rspq(adap, &r->rspq, 5, 1, ciq_size, 64);
6295                 r->rspq.uld = CXGB4_ULD_RDMA;
6296         }
6297
6298         init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
6299         init_rspq(adap, &s->intrq, 0, 1, 2 * MAX_INGQ, 64);
6300 }
6301
6302 /*
6303  * Reduce the number of Ethernet queues across all ports to at most n.
6304  * n provides at least one queue per port.
6305  */
6306 static void reduce_ethqs(struct adapter *adap, int n)
6307 {
6308         int i;
6309         struct port_info *pi;
6310
6311         while (n < adap->sge.ethqsets)
6312                 for_each_port(adap, i) {
6313                         pi = adap2pinfo(adap, i);
6314                         if (pi->nqsets > 1) {
6315                                 pi->nqsets--;
6316                                 adap->sge.ethqsets--;
6317                                 if (adap->sge.ethqsets <= n)
6318                                         break;
6319                         }
6320                 }
6321
6322         n = 0;
6323         for_each_port(adap, i) {
6324                 pi = adap2pinfo(adap, i);
6325                 pi->first_qset = n;
6326                 n += pi->nqsets;
6327         }
6328 }
6329
6330 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
6331 #define EXTRA_VECS 2
6332
6333 static int enable_msix(struct adapter *adap)
6334 {
6335         int ofld_need = 0;
6336         int i, want, need;
6337         struct sge *s = &adap->sge;
6338         unsigned int nchan = adap->params.nports;
6339         struct msix_entry entries[MAX_INGQ + 1];
6340
6341         for (i = 0; i < ARRAY_SIZE(entries); ++i)
6342                 entries[i].entry = i;
6343
6344         want = s->max_ethqsets + EXTRA_VECS;
6345         if (is_offload(adap)) {
6346                 want += s->rdmaqs + s->rdmaciqs + s->ofldqsets;
6347                 /* need nchan for each possible ULD */
6348                 ofld_need = 3 * nchan;
6349         }
6350 #ifdef CONFIG_CHELSIO_T4_DCB
6351         /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
6352          * each port.
6353          */
6354         need = 8 * adap->params.nports + EXTRA_VECS + ofld_need;
6355 #else
6356         need = adap->params.nports + EXTRA_VECS + ofld_need;
6357 #endif
6358         want = pci_enable_msix_range(adap->pdev, entries, need, want);
6359         if (want < 0)
6360                 return want;
6361
6362         /*
6363          * Distribute available vectors to the various queue groups.
6364          * Every group gets its minimum requirement and NIC gets top
6365          * priority for leftovers.
6366          */
6367         i = want - EXTRA_VECS - ofld_need;
6368         if (i < s->max_ethqsets) {
6369                 s->max_ethqsets = i;
6370                 if (i < s->ethqsets)
6371                         reduce_ethqs(adap, i);
6372         }
6373         if (is_offload(adap)) {
6374                 i = want - EXTRA_VECS - s->max_ethqsets;
6375                 i -= ofld_need - nchan;
6376                 s->ofldqsets = (i / nchan) * nchan;  /* round down */
6377         }
6378         for (i = 0; i < want; ++i)
6379                 adap->msix_info[i].vec = entries[i].vector;
6380
6381         return 0;
6382 }
6383
6384 #undef EXTRA_VECS
6385
6386 static int init_rss(struct adapter *adap)
6387 {
6388         unsigned int i, j;
6389
6390         for_each_port(adap, i) {
6391                 struct port_info *pi = adap2pinfo(adap, i);
6392
6393                 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
6394                 if (!pi->rss)
6395                         return -ENOMEM;
6396                 for (j = 0; j < pi->rss_size; j++)
6397                         pi->rss[j] = ethtool_rxfh_indir_default(j, pi->nqsets);
6398         }
6399         return 0;
6400 }
6401
6402 static void print_port_info(const struct net_device *dev)
6403 {
6404         char buf[80];
6405         char *bufp = buf;
6406         const char *spd = "";
6407         const struct port_info *pi = netdev_priv(dev);
6408         const struct adapter *adap = pi->adapter;
6409
6410         if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
6411                 spd = " 2.5 GT/s";
6412         else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
6413                 spd = " 5 GT/s";
6414         else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
6415                 spd = " 8 GT/s";
6416
6417         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
6418                 bufp += sprintf(bufp, "100/");
6419         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
6420                 bufp += sprintf(bufp, "1000/");
6421         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
6422                 bufp += sprintf(bufp, "10G/");
6423         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
6424                 bufp += sprintf(bufp, "40G/");
6425         if (bufp != buf)
6426                 --bufp;
6427         sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
6428
6429         netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n",
6430                     adap->params.vpd.id,
6431                     CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
6432                     is_offload(adap) ? "R" : "", adap->params.pci.width, spd,
6433                     (adap->flags & USING_MSIX) ? " MSI-X" :
6434                     (adap->flags & USING_MSI) ? " MSI" : "");
6435         netdev_info(dev, "S/N: %s, P/N: %s\n",
6436                     adap->params.vpd.sn, adap->params.vpd.pn);
6437 }
6438
6439 static void enable_pcie_relaxed_ordering(struct pci_dev *dev)
6440 {
6441         pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
6442 }
6443
6444 /*
6445  * Free the following resources:
6446  * - memory used for tables
6447  * - MSI/MSI-X
6448  * - net devices
6449  * - resources FW is holding for us
6450  */
6451 static void free_some_resources(struct adapter *adapter)
6452 {
6453         unsigned int i;
6454
6455         t4_free_mem(adapter->l2t);
6456         t4_free_mem(adapter->tids.tid_tab);
6457         disable_msi(adapter);
6458
6459         for_each_port(adapter, i)
6460                 if (adapter->port[i]) {
6461                         kfree(adap2pinfo(adapter, i)->rss);
6462                         free_netdev(adapter->port[i]);
6463                 }
6464         if (adapter->flags & FW_OK)
6465                 t4_fw_bye(adapter, adapter->fn);
6466 }
6467
6468 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
6469 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
6470                    NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
6471 #define SEGMENT_SIZE 128
6472
6473 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6474 {
6475         int func, i, err, s_qpp, qpp, num_seg;
6476         struct port_info *pi;
6477         bool highdma = false;
6478         struct adapter *adapter = NULL;
6479
6480         printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
6481
6482         err = pci_request_regions(pdev, KBUILD_MODNAME);
6483         if (err) {
6484                 /* Just info, some other driver may have claimed the device. */
6485                 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
6486                 return err;
6487         }
6488
6489         err = pci_enable_device(pdev);
6490         if (err) {
6491                 dev_err(&pdev->dev, "cannot enable PCI device\n");
6492                 goto out_release_regions;
6493         }
6494
6495         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
6496                 highdma = true;
6497                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
6498                 if (err) {
6499                         dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
6500                                 "coherent allocations\n");
6501                         goto out_disable_device;
6502                 }
6503         } else {
6504                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6505                 if (err) {
6506                         dev_err(&pdev->dev, "no usable DMA configuration\n");
6507                         goto out_disable_device;
6508                 }
6509         }
6510
6511         pci_enable_pcie_error_reporting(pdev);
6512         enable_pcie_relaxed_ordering(pdev);
6513         pci_set_master(pdev);
6514         pci_save_state(pdev);
6515
6516         adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
6517         if (!adapter) {
6518                 err = -ENOMEM;
6519                 goto out_disable_device;
6520         }
6521
6522         adapter->workq = create_singlethread_workqueue("cxgb4");
6523         if (!adapter->workq) {
6524                 err = -ENOMEM;
6525                 goto out_free_adapter;
6526         }
6527
6528         /* PCI device has been enabled */
6529         adapter->flags |= DEV_ENABLED;
6530
6531         adapter->regs = pci_ioremap_bar(pdev, 0);
6532         if (!adapter->regs) {
6533                 dev_err(&pdev->dev, "cannot map device registers\n");
6534                 err = -ENOMEM;
6535                 goto out_free_adapter;
6536         }
6537
6538         /* We control everything through one PF */
6539         func = SOURCEPF_GET(readl(adapter->regs + PL_WHOAMI));
6540         if (func != ent->driver_data) {
6541                 pci_save_state(pdev);        /* to restore SR-IOV later */
6542                 goto sriov;
6543         }
6544
6545         adapter->pdev = pdev;
6546         adapter->pdev_dev = &pdev->dev;
6547         adapter->mbox = func;
6548         adapter->fn = func;
6549         adapter->msg_enable = dflt_msg_enable;
6550         memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
6551
6552         spin_lock_init(&adapter->stats_lock);
6553         spin_lock_init(&adapter->tid_release_lock);
6554
6555         INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
6556         INIT_WORK(&adapter->db_full_task, process_db_full);
6557         INIT_WORK(&adapter->db_drop_task, process_db_drop);
6558
6559         err = t4_prep_adapter(adapter);
6560         if (err)
6561                 goto out_unmap_bar0;
6562
6563         if (!is_t4(adapter->params.chip)) {
6564                 s_qpp = QUEUESPERPAGEPF1 * adapter->fn;
6565                 qpp = 1 << QUEUESPERPAGEPF0_GET(t4_read_reg(adapter,
6566                       SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp);
6567                 num_seg = PAGE_SIZE / SEGMENT_SIZE;
6568
6569                 /* Each segment size is 128B. Write coalescing is enabled only
6570                  * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
6571                  * queue is less no of segments that can be accommodated in
6572                  * a page size.
6573                  */
6574                 if (qpp > num_seg) {
6575                         dev_err(&pdev->dev,
6576                                 "Incorrect number of egress queues per page\n");
6577                         err = -EINVAL;
6578                         goto out_unmap_bar0;
6579                 }
6580                 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
6581                 pci_resource_len(pdev, 2));
6582                 if (!adapter->bar2) {
6583                         dev_err(&pdev->dev, "cannot map device bar2 region\n");
6584                         err = -ENOMEM;
6585                         goto out_unmap_bar0;
6586                 }
6587         }
6588
6589         setup_memwin(adapter);
6590         err = adap_init0(adapter);
6591         setup_memwin_rdma(adapter);
6592         if (err)
6593                 goto out_unmap_bar;
6594
6595         for_each_port(adapter, i) {
6596                 struct net_device *netdev;
6597
6598                 netdev = alloc_etherdev_mq(sizeof(struct port_info),
6599                                            MAX_ETH_QSETS);
6600                 if (!netdev) {
6601                         err = -ENOMEM;
6602                         goto out_free_dev;
6603                 }
6604
6605                 SET_NETDEV_DEV(netdev, &pdev->dev);
6606
6607                 adapter->port[i] = netdev;
6608                 pi = netdev_priv(netdev);
6609                 pi->adapter = adapter;
6610                 pi->xact_addr_filt = -1;
6611                 pi->port_id = i;
6612                 netdev->irq = pdev->irq;
6613
6614                 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
6615                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
6616                         NETIF_F_RXCSUM | NETIF_F_RXHASH |
6617                         NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
6618                 if (highdma)
6619                         netdev->hw_features |= NETIF_F_HIGHDMA;
6620                 netdev->features |= netdev->hw_features;
6621                 netdev->vlan_features = netdev->features & VLAN_FEAT;
6622
6623                 netdev->priv_flags |= IFF_UNICAST_FLT;
6624
6625                 netdev->netdev_ops = &cxgb4_netdev_ops;
6626 #ifdef CONFIG_CHELSIO_T4_DCB
6627                 netdev->dcbnl_ops = &cxgb4_dcb_ops;
6628                 cxgb4_dcb_state_init(netdev);
6629 #endif
6630                 netdev->ethtool_ops = &cxgb_ethtool_ops;
6631         }
6632
6633         pci_set_drvdata(pdev, adapter);
6634
6635         if (adapter->flags & FW_OK) {
6636                 err = t4_port_init(adapter, func, func, 0);
6637                 if (err)
6638                         goto out_free_dev;
6639         }
6640
6641         /*
6642          * Configure queues and allocate tables now, they can be needed as
6643          * soon as the first register_netdev completes.
6644          */
6645         cfg_queues(adapter);
6646
6647         adapter->l2t = t4_init_l2t();
6648         if (!adapter->l2t) {
6649                 /* We tolerate a lack of L2T, giving up some functionality */
6650                 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
6651                 adapter->params.offload = 0;
6652         }
6653
6654         if (is_offload(adapter) && tid_init(&adapter->tids) < 0) {
6655                 dev_warn(&pdev->dev, "could not allocate TID table, "
6656                          "continuing\n");
6657                 adapter->params.offload = 0;
6658         }
6659
6660         /* See what interrupts we'll be using */
6661         if (msi > 1 && enable_msix(adapter) == 0)
6662                 adapter->flags |= USING_MSIX;
6663         else if (msi > 0 && pci_enable_msi(pdev) == 0)
6664                 adapter->flags |= USING_MSI;
6665
6666         err = init_rss(adapter);
6667         if (err)
6668                 goto out_free_dev;
6669
6670         /*
6671          * The card is now ready to go.  If any errors occur during device
6672          * registration we do not fail the whole card but rather proceed only
6673          * with the ports we manage to register successfully.  However we must
6674          * register at least one net device.
6675          */
6676         for_each_port(adapter, i) {
6677                 pi = adap2pinfo(adapter, i);
6678                 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
6679                 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
6680
6681                 err = register_netdev(adapter->port[i]);
6682                 if (err)
6683                         break;
6684                 adapter->chan_map[pi->tx_chan] = i;
6685                 print_port_info(adapter->port[i]);
6686         }
6687         if (i == 0) {
6688                 dev_err(&pdev->dev, "could not register any net devices\n");
6689                 goto out_free_dev;
6690         }
6691         if (err) {
6692                 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
6693                 err = 0;
6694         }
6695
6696         if (cxgb4_debugfs_root) {
6697                 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
6698                                                            cxgb4_debugfs_root);
6699                 setup_debugfs(adapter);
6700         }
6701
6702         /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
6703         pdev->needs_freset = 1;
6704
6705         if (is_offload(adapter))
6706                 attach_ulds(adapter);
6707
6708 sriov:
6709 #ifdef CONFIG_PCI_IOV
6710         if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0)
6711                 if (pci_enable_sriov(pdev, num_vf[func]) == 0)
6712                         dev_info(&pdev->dev,
6713                                  "instantiated %u virtual functions\n",
6714                                  num_vf[func]);
6715 #endif
6716         return 0;
6717
6718  out_free_dev:
6719         free_some_resources(adapter);
6720  out_unmap_bar:
6721         if (!is_t4(adapter->params.chip))
6722                 iounmap(adapter->bar2);
6723  out_unmap_bar0:
6724         iounmap(adapter->regs);
6725  out_free_adapter:
6726         if (adapter->workq)
6727                 destroy_workqueue(adapter->workq);
6728
6729         kfree(adapter);
6730  out_disable_device:
6731         pci_disable_pcie_error_reporting(pdev);
6732         pci_disable_device(pdev);
6733  out_release_regions:
6734         pci_release_regions(pdev);
6735         return err;
6736 }
6737
6738 static void remove_one(struct pci_dev *pdev)
6739 {
6740         struct adapter *adapter = pci_get_drvdata(pdev);
6741
6742 #ifdef CONFIG_PCI_IOV
6743         pci_disable_sriov(pdev);
6744
6745 #endif
6746
6747         if (adapter) {
6748                 int i;
6749
6750                 /* Tear down per-adapter Work Queue first since it can contain
6751                  * references to our adapter data structure.
6752                  */
6753                 destroy_workqueue(adapter->workq);
6754
6755                 if (is_offload(adapter))
6756                         detach_ulds(adapter);
6757
6758                 for_each_port(adapter, i)
6759                         if (adapter->port[i]->reg_state == NETREG_REGISTERED)
6760                                 unregister_netdev(adapter->port[i]);
6761
6762                 debugfs_remove_recursive(adapter->debugfs_root);
6763
6764                 /* If we allocated filters, free up state associated with any
6765                  * valid filters ...
6766                  */
6767                 if (adapter->tids.ftid_tab) {
6768                         struct filter_entry *f = &adapter->tids.ftid_tab[0];
6769                         for (i = 0; i < (adapter->tids.nftids +
6770                                         adapter->tids.nsftids); i++, f++)
6771                                 if (f->valid)
6772                                         clear_filter(adapter, f);
6773                 }
6774
6775                 if (adapter->flags & FULL_INIT_DONE)
6776                         cxgb_down(adapter);
6777
6778                 free_some_resources(adapter);
6779                 iounmap(adapter->regs);
6780                 if (!is_t4(adapter->params.chip))
6781                         iounmap(adapter->bar2);
6782                 pci_disable_pcie_error_reporting(pdev);
6783                 if ((adapter->flags & DEV_ENABLED)) {
6784                         pci_disable_device(pdev);
6785                         adapter->flags &= ~DEV_ENABLED;
6786                 }
6787                 pci_release_regions(pdev);
6788                 synchronize_rcu();
6789                 kfree(adapter);
6790         } else
6791                 pci_release_regions(pdev);
6792 }
6793
6794 static struct pci_driver cxgb4_driver = {
6795         .name     = KBUILD_MODNAME,
6796         .id_table = cxgb4_pci_tbl,
6797         .probe    = init_one,
6798         .remove   = remove_one,
6799         .shutdown = remove_one,
6800         .err_handler = &cxgb4_eeh,
6801 };
6802
6803 static int __init cxgb4_init_module(void)
6804 {
6805         int ret;
6806
6807         /* Debugfs support is optional, just warn if this fails */
6808         cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
6809         if (!cxgb4_debugfs_root)
6810                 pr_warn("could not create debugfs entry, continuing\n");
6811
6812         ret = pci_register_driver(&cxgb4_driver);
6813         if (ret < 0)
6814                 debugfs_remove(cxgb4_debugfs_root);
6815
6816         register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6817
6818         return ret;
6819 }
6820
6821 static void __exit cxgb4_cleanup_module(void)
6822 {
6823         unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6824         pci_unregister_driver(&cxgb4_driver);
6825         debugfs_remove(cxgb4_debugfs_root);  /* NULL ok */
6826 }
6827
6828 module_init(cxgb4_init_module);
6829 module_exit(cxgb4_cleanup_module);