2 * Cadence MACB/GEM Ethernet Controller driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/circ_buf.h>
18 #include <linux/slab.h>
19 #include <linux/init.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_data/macb.h>
27 #include <linux/platform_device.h>
28 #include <linux/phy.h>
30 #include <linux/of_device.h>
31 #include <linux/of_mdio.h>
32 #include <linux/of_net.h>
36 #define MACB_RX_BUFFER_SIZE 128
37 #define RX_BUFFER_MULTIPLE 64 /* bytes */
38 #define RX_RING_SIZE 512 /* must be power of 2 */
39 #define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
41 #define TX_RING_SIZE 128 /* must be power of 2 */
42 #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
44 /* level of occupied TX descriptors under which we wake up TX process */
45 #define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4)
47 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
49 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
52 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
54 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1))
55 #define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1))
57 #define GEM_MTU_MIN_SIZE 68
60 * Graceful stop timeouts in us. We should allow up to
61 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
63 #define MACB_HALT_TIMEOUT 1230
65 /* Ring buffer accessors */
66 static unsigned int macb_tx_ring_wrap(unsigned int index)
68 return index & (TX_RING_SIZE - 1);
71 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
74 return &queue->tx_ring[macb_tx_ring_wrap(index)];
77 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
80 return &queue->tx_skb[macb_tx_ring_wrap(index)];
83 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
87 offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc);
89 return queue->tx_ring_dma + offset;
92 static unsigned int macb_rx_ring_wrap(unsigned int index)
94 return index & (RX_RING_SIZE - 1);
97 static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
99 return &bp->rx_ring[macb_rx_ring_wrap(index)];
102 static void *macb_rx_buffer(struct macb *bp, unsigned int index)
104 return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index);
108 static u32 hw_readl_native(struct macb *bp, int offset)
110 return __raw_readl(bp->regs + offset);
113 static void hw_writel_native(struct macb *bp, int offset, u32 value)
115 __raw_writel(value, bp->regs + offset);
118 static u32 hw_readl(struct macb *bp, int offset)
120 return readl_relaxed(bp->regs + offset);
123 static void hw_writel(struct macb *bp, int offset, u32 value)
125 writel_relaxed(value, bp->regs + offset);
129 * Find the CPU endianness by using the loopback bit of NCR register. When the
130 * CPU is in big endian we need to program swaped mode for management
133 static bool hw_is_native_io(void __iomem *addr)
135 u32 value = MACB_BIT(LLB);
137 __raw_writel(value, addr + MACB_NCR);
138 value = __raw_readl(addr + MACB_NCR);
140 /* Write 0 back to disable everything */
141 __raw_writel(0, addr + MACB_NCR);
143 return value == MACB_BIT(LLB);
146 static bool hw_is_gem(void __iomem *addr, bool native_io)
151 id = __raw_readl(addr + MACB_MID);
153 id = readl_relaxed(addr + MACB_MID);
155 return MACB_BFEXT(IDNUM, id) >= 0x2;
158 static void macb_set_hwaddr(struct macb *bp)
163 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
164 macb_or_gem_writel(bp, SA1B, bottom);
165 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
166 macb_or_gem_writel(bp, SA1T, top);
168 /* Clear unused address register sets */
169 macb_or_gem_writel(bp, SA2B, 0);
170 macb_or_gem_writel(bp, SA2T, 0);
171 macb_or_gem_writel(bp, SA3B, 0);
172 macb_or_gem_writel(bp, SA3T, 0);
173 macb_or_gem_writel(bp, SA4B, 0);
174 macb_or_gem_writel(bp, SA4T, 0);
177 static void macb_get_hwaddr(struct macb *bp)
179 struct macb_platform_data *pdata;
185 pdata = dev_get_platdata(&bp->pdev->dev);
187 /* Check all 4 address register for vaild address */
188 for (i = 0; i < 4; i++) {
189 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
190 top = macb_or_gem_readl(bp, SA1T + i * 8);
192 if (pdata && pdata->rev_eth_addr) {
193 addr[5] = bottom & 0xff;
194 addr[4] = (bottom >> 8) & 0xff;
195 addr[3] = (bottom >> 16) & 0xff;
196 addr[2] = (bottom >> 24) & 0xff;
197 addr[1] = top & 0xff;
198 addr[0] = (top & 0xff00) >> 8;
200 addr[0] = bottom & 0xff;
201 addr[1] = (bottom >> 8) & 0xff;
202 addr[2] = (bottom >> 16) & 0xff;
203 addr[3] = (bottom >> 24) & 0xff;
204 addr[4] = top & 0xff;
205 addr[5] = (top >> 8) & 0xff;
208 if (is_valid_ether_addr(addr)) {
209 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
214 netdev_info(bp->dev, "invalid hw address, using random\n");
215 eth_hw_addr_random(bp->dev);
218 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
220 struct macb *bp = bus->priv;
223 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
224 | MACB_BF(RW, MACB_MAN_READ)
225 | MACB_BF(PHYA, mii_id)
226 | MACB_BF(REGA, regnum)
227 | MACB_BF(CODE, MACB_MAN_CODE)));
229 /* wait for end of transfer */
230 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
233 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
238 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
241 struct macb *bp = bus->priv;
243 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
244 | MACB_BF(RW, MACB_MAN_WRITE)
245 | MACB_BF(PHYA, mii_id)
246 | MACB_BF(REGA, regnum)
247 | MACB_BF(CODE, MACB_MAN_CODE)
248 | MACB_BF(DATA, value)));
250 /* wait for end of transfer */
251 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
258 * macb_set_tx_clk() - Set a clock to a new frequency
259 * @clk Pointer to the clock to change
260 * @rate New frequency in Hz
261 * @dev Pointer to the struct net_device
263 static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
265 long ferr, rate, rate_rounded;
284 rate_rounded = clk_round_rate(clk, rate);
285 if (rate_rounded < 0)
288 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
291 ferr = abs(rate_rounded - rate);
292 ferr = DIV_ROUND_UP(ferr, rate / 100000);
294 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
297 if (clk_set_rate(clk, rate_rounded))
298 netdev_err(dev, "adjusting tx_clk failed.\n");
301 static void macb_handle_link_change(struct net_device *dev)
303 struct macb *bp = netdev_priv(dev);
304 struct phy_device *phydev = bp->phy_dev;
307 int status_change = 0;
309 spin_lock_irqsave(&bp->lock, flags);
312 if ((bp->speed != phydev->speed) ||
313 (bp->duplex != phydev->duplex)) {
316 reg = macb_readl(bp, NCFGR);
317 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
319 reg &= ~GEM_BIT(GBE);
323 if (phydev->speed == SPEED_100)
324 reg |= MACB_BIT(SPD);
325 if (phydev->speed == SPEED_1000 &&
326 bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
329 macb_or_gem_writel(bp, NCFGR, reg);
331 bp->speed = phydev->speed;
332 bp->duplex = phydev->duplex;
337 if (phydev->link != bp->link) {
342 bp->link = phydev->link;
347 spin_unlock_irqrestore(&bp->lock, flags);
351 /* Update the TX clock rate if and only if the link is
352 * up and there has been a link change.
354 macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
356 netif_carrier_on(dev);
357 netdev_info(dev, "link up (%d/%s)\n",
359 phydev->duplex == DUPLEX_FULL ?
362 netif_carrier_off(dev);
363 netdev_info(dev, "link down\n");
368 /* based on au1000_eth. c*/
369 static int macb_mii_probe(struct net_device *dev)
371 struct macb *bp = netdev_priv(dev);
372 struct macb_platform_data *pdata;
373 struct phy_device *phydev;
377 phydev = phy_find_first(bp->mii_bus);
379 netdev_err(dev, "no PHY found\n");
383 pdata = dev_get_platdata(&bp->pdev->dev);
384 if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
385 ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, "phy int");
387 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
388 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
392 /* attach the mac to the phy */
393 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
396 netdev_err(dev, "Could not attach to PHY\n");
400 /* mask with MAC supported features */
401 if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
402 phydev->supported &= PHY_GBIT_FEATURES;
404 phydev->supported &= PHY_BASIC_FEATURES;
406 if (bp->caps & MACB_CAPS_NO_GIGABIT_HALF)
407 phydev->supported &= ~SUPPORTED_1000baseT_Half;
409 phydev->advertising = phydev->supported;
414 bp->phy_dev = phydev;
419 static int macb_mii_init(struct macb *bp)
421 struct macb_platform_data *pdata;
422 struct device_node *np;
425 /* Enable management port */
426 macb_writel(bp, NCR, MACB_BIT(MPE));
428 bp->mii_bus = mdiobus_alloc();
429 if (bp->mii_bus == NULL) {
434 bp->mii_bus->name = "MACB_mii_bus";
435 bp->mii_bus->read = &macb_mdio_read;
436 bp->mii_bus->write = &macb_mdio_write;
437 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
438 bp->pdev->name, bp->pdev->id);
439 bp->mii_bus->priv = bp;
440 bp->mii_bus->parent = &bp->dev->dev;
441 pdata = dev_get_platdata(&bp->pdev->dev);
443 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
444 if (!bp->mii_bus->irq) {
446 goto err_out_free_mdiobus;
449 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
451 np = bp->pdev->dev.of_node;
453 /* try dt phy registration */
454 err = of_mdiobus_register(bp->mii_bus, np);
456 /* fallback to standard phy registration if no phy were
457 found during dt phy registration */
458 if (!err && !phy_find_first(bp->mii_bus)) {
459 for (i = 0; i < PHY_MAX_ADDR; i++) {
460 struct phy_device *phydev;
462 phydev = mdiobus_scan(bp->mii_bus, i);
463 if (IS_ERR(phydev)) {
464 err = PTR_ERR(phydev);
470 goto err_out_unregister_bus;
473 for (i = 0; i < PHY_MAX_ADDR; i++)
474 bp->mii_bus->irq[i] = PHY_POLL;
477 bp->mii_bus->phy_mask = pdata->phy_mask;
479 err = mdiobus_register(bp->mii_bus);
483 goto err_out_free_mdio_irq;
485 err = macb_mii_probe(bp->dev);
487 goto err_out_unregister_bus;
491 err_out_unregister_bus:
492 mdiobus_unregister(bp->mii_bus);
493 err_out_free_mdio_irq:
494 kfree(bp->mii_bus->irq);
495 err_out_free_mdiobus:
496 mdiobus_free(bp->mii_bus);
501 static void macb_update_stats(struct macb *bp)
503 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
504 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
505 int offset = MACB_PFR;
507 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
509 for(; p < end; p++, offset += 4)
510 *p += bp->readl(bp, offset);
513 static int macb_halt_tx(struct macb *bp)
515 unsigned long halt_time, timeout;
518 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
520 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
523 status = macb_readl(bp, TSR);
524 if (!(status & MACB_BIT(TGO)))
527 usleep_range(10, 250);
528 } while (time_before(halt_time, timeout));
533 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
535 if (tx_skb->mapping) {
536 if (tx_skb->mapped_as_page)
537 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
538 tx_skb->size, DMA_TO_DEVICE);
540 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
541 tx_skb->size, DMA_TO_DEVICE);
546 dev_kfree_skb_any(tx_skb->skb);
551 static void macb_tx_error_task(struct work_struct *work)
553 struct macb_queue *queue = container_of(work, struct macb_queue,
555 struct macb *bp = queue->bp;
556 struct macb_tx_skb *tx_skb;
557 struct macb_dma_desc *desc;
562 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
563 (unsigned int)(queue - bp->queues),
564 queue->tx_tail, queue->tx_head);
566 /* Prevent the queue IRQ handlers from running: each of them may call
567 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
568 * As explained below, we have to halt the transmission before updating
569 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
570 * network engine about the macb/gem being halted.
572 spin_lock_irqsave(&bp->lock, flags);
574 /* Make sure nobody is trying to queue up new packets */
575 netif_tx_stop_all_queues(bp->dev);
578 * Stop transmission now
579 * (in case we have just queued new packets)
580 * macb/gem must be halted to write TBQP register
582 if (macb_halt_tx(bp))
583 /* Just complain for now, reinitializing TX path can be good */
584 netdev_err(bp->dev, "BUG: halt tx timed out\n");
587 * Treat frames in TX queue including the ones that caused the error.
588 * Free transmit buffers in upper layer.
590 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
593 desc = macb_tx_desc(queue, tail);
595 tx_skb = macb_tx_skb(queue, tail);
598 if (ctrl & MACB_BIT(TX_USED)) {
599 /* skb is set for the last buffer of the frame */
601 macb_tx_unmap(bp, tx_skb);
603 tx_skb = macb_tx_skb(queue, tail);
607 /* ctrl still refers to the first buffer descriptor
608 * since it's the only one written back by the hardware
610 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
611 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
612 macb_tx_ring_wrap(tail), skb->data);
613 bp->stats.tx_packets++;
614 bp->stats.tx_bytes += skb->len;
618 * "Buffers exhausted mid-frame" errors may only happen
619 * if the driver is buggy, so complain loudly about those.
620 * Statistics are updated by hardware.
622 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
624 "BUG: TX buffers exhausted mid-frame\n");
626 desc->ctrl = ctrl | MACB_BIT(TX_USED);
629 macb_tx_unmap(bp, tx_skb);
632 /* Set end of TX queue */
633 desc = macb_tx_desc(queue, 0);
635 desc->ctrl = MACB_BIT(TX_USED);
637 /* Make descriptor updates visible to hardware */
640 /* Reinitialize the TX desc queue */
641 queue_writel(queue, TBQP, queue->tx_ring_dma);
642 /* Make TX ring reflect state of hardware */
646 /* Housework before enabling TX IRQ */
647 macb_writel(bp, TSR, macb_readl(bp, TSR));
648 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
650 /* Now we are ready to start transmission again */
651 netif_tx_start_all_queues(bp->dev);
652 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
654 spin_unlock_irqrestore(&bp->lock, flags);
657 static void macb_tx_interrupt(struct macb_queue *queue)
662 struct macb *bp = queue->bp;
663 u16 queue_index = queue - bp->queues;
665 status = macb_readl(bp, TSR);
666 macb_writel(bp, TSR, status);
668 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
669 queue_writel(queue, ISR, MACB_BIT(TCOMP));
671 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
672 (unsigned long)status);
674 head = queue->tx_head;
675 for (tail = queue->tx_tail; tail != head; tail++) {
676 struct macb_tx_skb *tx_skb;
678 struct macb_dma_desc *desc;
681 desc = macb_tx_desc(queue, tail);
683 /* Make hw descriptor updates visible to CPU */
688 /* TX_USED bit is only set by hardware on the very first buffer
689 * descriptor of the transmitted frame.
691 if (!(ctrl & MACB_BIT(TX_USED)))
694 /* Process all buffers of the current transmitted frame */
696 tx_skb = macb_tx_skb(queue, tail);
699 /* First, update TX stats if needed */
701 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
702 macb_tx_ring_wrap(tail), skb->data);
703 bp->stats.tx_packets++;
704 bp->stats.tx_bytes += skb->len;
707 /* Now we can safely release resources */
708 macb_tx_unmap(bp, tx_skb);
710 /* skb is set only for the last buffer of the frame.
711 * WARNING: at this point skb has been freed by
719 queue->tx_tail = tail;
720 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
721 CIRC_CNT(queue->tx_head, queue->tx_tail,
722 TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH)
723 netif_wake_subqueue(bp->dev, queue_index);
726 static void gem_rx_refill(struct macb *bp)
732 while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail, RX_RING_SIZE) > 0) {
733 entry = macb_rx_ring_wrap(bp->rx_prepared_head);
735 /* Make hw descriptor updates visible to CPU */
738 bp->rx_prepared_head++;
740 if (bp->rx_skbuff[entry] == NULL) {
741 /* allocate sk_buff for this free entry in ring */
742 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
743 if (unlikely(skb == NULL)) {
745 "Unable to allocate sk_buff\n");
749 /* now fill corresponding descriptor entry */
750 paddr = dma_map_single(&bp->pdev->dev, skb->data,
751 bp->rx_buffer_size, DMA_FROM_DEVICE);
752 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
757 bp->rx_skbuff[entry] = skb;
759 if (entry == RX_RING_SIZE - 1)
760 paddr |= MACB_BIT(RX_WRAP);
761 bp->rx_ring[entry].addr = paddr;
762 bp->rx_ring[entry].ctrl = 0;
764 /* properly align Ethernet header */
765 skb_reserve(skb, NET_IP_ALIGN);
767 bp->rx_ring[entry].addr &= ~MACB_BIT(RX_USED);
768 bp->rx_ring[entry].ctrl = 0;
772 /* Make descriptor updates visible to hardware */
775 netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
776 bp->rx_prepared_head, bp->rx_tail);
779 /* Mark DMA descriptors from begin up to and not including end as unused */
780 static void discard_partial_frame(struct macb *bp, unsigned int begin,
785 for (frag = begin; frag != end; frag++) {
786 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
787 desc->addr &= ~MACB_BIT(RX_USED);
790 /* Make descriptor updates visible to hardware */
794 * When this happens, the hardware stats registers for
795 * whatever caused this is updated, so we don't have to record
800 static int gem_rx(struct macb *bp, int budget)
805 struct macb_dma_desc *desc;
808 while (count < budget) {
811 entry = macb_rx_ring_wrap(bp->rx_tail);
812 desc = &bp->rx_ring[entry];
814 /* Make hw descriptor updates visible to CPU */
820 if (!(addr & MACB_BIT(RX_USED)))
826 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
828 "not whole frame pointed by descriptor\n");
829 bp->stats.rx_dropped++;
832 skb = bp->rx_skbuff[entry];
833 if (unlikely(!skb)) {
835 "inconsistent Rx descriptor chain\n");
836 bp->stats.rx_dropped++;
839 /* now everything is ready for receiving packet */
840 bp->rx_skbuff[entry] = NULL;
841 len = ctrl & bp->rx_frm_len_mask;
843 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
846 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, addr));
847 dma_unmap_single(&bp->pdev->dev, addr,
848 bp->rx_buffer_size, DMA_FROM_DEVICE);
850 skb->protocol = eth_type_trans(skb, bp->dev);
851 skb_checksum_none_assert(skb);
852 if (bp->dev->features & NETIF_F_RXCSUM &&
853 !(bp->dev->flags & IFF_PROMISC) &&
854 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
855 skb->ip_summed = CHECKSUM_UNNECESSARY;
857 bp->stats.rx_packets++;
858 bp->stats.rx_bytes += skb->len;
860 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
861 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
862 skb->len, skb->csum);
863 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
864 skb_mac_header(skb), 16, true);
865 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
866 skb->data, 32, true);
869 netif_receive_skb(skb);
877 static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
878 unsigned int last_frag)
884 struct macb_dma_desc *desc;
886 desc = macb_rx_desc(bp, last_frag);
887 len = desc->ctrl & bp->rx_frm_len_mask;
889 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
890 macb_rx_ring_wrap(first_frag),
891 macb_rx_ring_wrap(last_frag), len);
894 * The ethernet header starts NET_IP_ALIGN bytes into the
895 * first buffer. Since the header is 14 bytes, this makes the
896 * payload word-aligned.
898 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
899 * the two padding bytes into the skb so that we avoid hitting
900 * the slowpath in memcpy(), and pull them off afterwards.
902 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
904 bp->stats.rx_dropped++;
905 for (frag = first_frag; ; frag++) {
906 desc = macb_rx_desc(bp, frag);
907 desc->addr &= ~MACB_BIT(RX_USED);
908 if (frag == last_frag)
912 /* Make descriptor updates visible to hardware */
920 skb_checksum_none_assert(skb);
923 for (frag = first_frag; ; frag++) {
924 unsigned int frag_len = bp->rx_buffer_size;
926 if (offset + frag_len > len) {
927 BUG_ON(frag != last_frag);
928 frag_len = len - offset;
930 skb_copy_to_linear_data_offset(skb, offset,
931 macb_rx_buffer(bp, frag), frag_len);
932 offset += bp->rx_buffer_size;
933 desc = macb_rx_desc(bp, frag);
934 desc->addr &= ~MACB_BIT(RX_USED);
936 if (frag == last_frag)
940 /* Make descriptor updates visible to hardware */
943 __skb_pull(skb, NET_IP_ALIGN);
944 skb->protocol = eth_type_trans(skb, bp->dev);
946 bp->stats.rx_packets++;
947 bp->stats.rx_bytes += skb->len;
948 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
949 skb->len, skb->csum);
950 netif_receive_skb(skb);
955 static int macb_rx(struct macb *bp, int budget)
961 for (tail = bp->rx_tail; budget > 0; tail++) {
962 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
965 /* Make hw descriptor updates visible to CPU */
971 if (!(addr & MACB_BIT(RX_USED)))
974 if (ctrl & MACB_BIT(RX_SOF)) {
975 if (first_frag != -1)
976 discard_partial_frame(bp, first_frag, tail);
980 if (ctrl & MACB_BIT(RX_EOF)) {
982 BUG_ON(first_frag == -1);
984 dropped = macb_rx_frame(bp, first_frag, tail);
993 if (first_frag != -1)
994 bp->rx_tail = first_frag;
1001 static int macb_poll(struct napi_struct *napi, int budget)
1003 struct macb *bp = container_of(napi, struct macb, napi);
1007 status = macb_readl(bp, RSR);
1008 macb_writel(bp, RSR, status);
1012 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
1013 (unsigned long)status, budget);
1015 work_done = bp->macbgem_ops.mog_rx(bp, budget);
1016 if (work_done < budget) {
1017 napi_complete(napi);
1019 /* Packets received while interrupts were disabled */
1020 status = macb_readl(bp, RSR);
1022 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1023 macb_writel(bp, ISR, MACB_BIT(RCOMP));
1024 napi_reschedule(napi);
1026 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
1030 /* TODO: Handle errors */
1035 static irqreturn_t macb_interrupt(int irq, void *dev_id)
1037 struct macb_queue *queue = dev_id;
1038 struct macb *bp = queue->bp;
1039 struct net_device *dev = bp->dev;
1042 status = queue_readl(queue, ISR);
1044 if (unlikely(!status))
1047 spin_lock(&bp->lock);
1050 /* close possible race with dev_close */
1051 if (unlikely(!netif_running(dev))) {
1052 queue_writel(queue, IDR, -1);
1056 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1057 (unsigned int)(queue - bp->queues),
1058 (unsigned long)status);
1060 if (status & MACB_RX_INT_FLAGS) {
1062 * There's no point taking any more interrupts
1063 * until we have processed the buffers. The
1064 * scheduling call may fail if the poll routine
1065 * is already scheduled, so disable interrupts
1068 queue_writel(queue, IDR, MACB_RX_INT_FLAGS);
1069 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1070 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1072 if (napi_schedule_prep(&bp->napi)) {
1073 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1074 __napi_schedule(&bp->napi);
1078 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1079 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1080 schedule_work(&queue->tx_error_task);
1082 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1083 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1088 if (status & MACB_BIT(TCOMP))
1089 macb_tx_interrupt(queue);
1092 * Link change detection isn't possible with RMII, so we'll
1093 * add that if/when we get our hands on a full-blown MII PHY.
1096 /* There is a hardware issue under heavy load where DMA can
1097 * stop, this causes endless "used buffer descriptor read"
1098 * interrupts but it can be cleared by re-enabling RX. See
1099 * the at91 manual, section 41.3.1 or the Zynq manual
1100 * section 16.7.4 for details.
1102 if (status & MACB_BIT(RXUBR)) {
1103 ctrl = macb_readl(bp, NCR);
1104 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1105 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1107 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1108 macb_writel(bp, ISR, MACB_BIT(RXUBR));
1111 if (status & MACB_BIT(ISR_ROVR)) {
1112 /* We missed at least one packet */
1113 if (macb_is_gem(bp))
1114 bp->hw_stats.gem.rx_overruns++;
1116 bp->hw_stats.macb.rx_overruns++;
1118 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1119 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1122 if (status & MACB_BIT(HRESP)) {
1124 * TODO: Reset the hardware, and maybe move the
1125 * netdev_err to a lower-priority context as well
1128 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1130 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1131 queue_writel(queue, ISR, MACB_BIT(HRESP));
1134 status = queue_readl(queue, ISR);
1137 spin_unlock(&bp->lock);
1142 #ifdef CONFIG_NET_POLL_CONTROLLER
1144 * Polling receive - used by netconsole and other diagnostic tools
1145 * to allow network i/o with interrupts disabled.
1147 static void macb_poll_controller(struct net_device *dev)
1149 struct macb *bp = netdev_priv(dev);
1150 struct macb_queue *queue;
1151 unsigned long flags;
1154 local_irq_save(flags);
1155 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1156 macb_interrupt(dev->irq, queue);
1157 local_irq_restore(flags);
1161 static inline unsigned int macb_count_tx_descriptors(struct macb *bp,
1164 return (len + bp->max_tx_length - 1) / bp->max_tx_length;
1167 static unsigned int macb_tx_map(struct macb *bp,
1168 struct macb_queue *queue,
1169 struct sk_buff *skb)
1172 unsigned int len, entry, i, tx_head = queue->tx_head;
1173 struct macb_tx_skb *tx_skb = NULL;
1174 struct macb_dma_desc *desc;
1175 unsigned int offset, size, count = 0;
1176 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1177 unsigned int eof = 1;
1180 /* First, map non-paged data */
1181 len = skb_headlen(skb);
1184 size = min(len, bp->max_tx_length);
1185 entry = macb_tx_ring_wrap(tx_head);
1186 tx_skb = &queue->tx_skb[entry];
1188 mapping = dma_map_single(&bp->pdev->dev,
1190 size, DMA_TO_DEVICE);
1191 if (dma_mapping_error(&bp->pdev->dev, mapping))
1194 /* Save info to properly release resources */
1196 tx_skb->mapping = mapping;
1197 tx_skb->size = size;
1198 tx_skb->mapped_as_page = false;
1206 /* Then, map paged data from fragments */
1207 for (f = 0; f < nr_frags; f++) {
1208 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1210 len = skb_frag_size(frag);
1213 size = min(len, bp->max_tx_length);
1214 entry = macb_tx_ring_wrap(tx_head);
1215 tx_skb = &queue->tx_skb[entry];
1217 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1218 offset, size, DMA_TO_DEVICE);
1219 if (dma_mapping_error(&bp->pdev->dev, mapping))
1222 /* Save info to properly release resources */
1224 tx_skb->mapping = mapping;
1225 tx_skb->size = size;
1226 tx_skb->mapped_as_page = true;
1235 /* Should never happen */
1236 if (unlikely(tx_skb == NULL)) {
1237 netdev_err(bp->dev, "BUG! empty skb!\n");
1241 /* This is the last buffer of the frame: save socket buffer */
1244 /* Update TX ring: update buffer descriptors in reverse order
1245 * to avoid race condition
1248 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1249 * to set the end of TX queue
1252 entry = macb_tx_ring_wrap(i);
1253 ctrl = MACB_BIT(TX_USED);
1254 desc = &queue->tx_ring[entry];
1259 entry = macb_tx_ring_wrap(i);
1260 tx_skb = &queue->tx_skb[entry];
1261 desc = &queue->tx_ring[entry];
1263 ctrl = (u32)tx_skb->size;
1265 ctrl |= MACB_BIT(TX_LAST);
1268 if (unlikely(entry == (TX_RING_SIZE - 1)))
1269 ctrl |= MACB_BIT(TX_WRAP);
1271 /* Set TX buffer descriptor */
1272 desc->addr = tx_skb->mapping;
1273 /* desc->addr must be visible to hardware before clearing
1274 * 'TX_USED' bit in desc->ctrl.
1278 } while (i != queue->tx_head);
1280 queue->tx_head = tx_head;
1285 netdev_err(bp->dev, "TX DMA map failed\n");
1287 for (i = queue->tx_head; i != tx_head; i++) {
1288 tx_skb = macb_tx_skb(queue, i);
1290 macb_tx_unmap(bp, tx_skb);
1296 static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1298 u16 queue_index = skb_get_queue_mapping(skb);
1299 struct macb *bp = netdev_priv(dev);
1300 struct macb_queue *queue = &bp->queues[queue_index];
1301 unsigned long flags;
1302 unsigned int count, nr_frags, frag_size, f;
1304 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1305 netdev_vdbg(bp->dev,
1306 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
1307 queue_index, skb->len, skb->head, skb->data,
1308 skb_tail_pointer(skb), skb_end_pointer(skb));
1309 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1310 skb->data, 16, true);
1313 /* Count how many TX buffer descriptors are needed to send this
1314 * socket buffer: skb fragments of jumbo frames may need to be
1315 * splitted into many buffer descriptors.
1317 count = macb_count_tx_descriptors(bp, skb_headlen(skb));
1318 nr_frags = skb_shinfo(skb)->nr_frags;
1319 for (f = 0; f < nr_frags; f++) {
1320 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
1321 count += macb_count_tx_descriptors(bp, frag_size);
1324 spin_lock_irqsave(&bp->lock, flags);
1326 /* This is a hard error, log it. */
1327 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, TX_RING_SIZE) < count) {
1328 netif_stop_subqueue(dev, queue_index);
1329 spin_unlock_irqrestore(&bp->lock, flags);
1330 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1331 queue->tx_head, queue->tx_tail);
1332 return NETDEV_TX_BUSY;
1335 /* Map socket buffer for DMA transfer */
1336 if (!macb_tx_map(bp, queue, skb)) {
1337 dev_kfree_skb_any(skb);
1341 /* Make newly initialized descriptor visible to hardware */
1344 skb_tx_timestamp(skb);
1346 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1348 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, TX_RING_SIZE) < 1)
1349 netif_stop_subqueue(dev, queue_index);
1352 spin_unlock_irqrestore(&bp->lock, flags);
1354 return NETDEV_TX_OK;
1357 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1359 if (!macb_is_gem(bp)) {
1360 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1362 bp->rx_buffer_size = size;
1364 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
1366 "RX buffer must be multiple of %d bytes, expanding\n",
1367 RX_BUFFER_MULTIPLE);
1368 bp->rx_buffer_size =
1369 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1373 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%Zu]\n",
1374 bp->dev->mtu, bp->rx_buffer_size);
1377 static void gem_free_rx_buffers(struct macb *bp)
1379 struct sk_buff *skb;
1380 struct macb_dma_desc *desc;
1387 for (i = 0; i < RX_RING_SIZE; i++) {
1388 skb = bp->rx_skbuff[i];
1393 desc = &bp->rx_ring[i];
1394 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
1395 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
1397 dev_kfree_skb_any(skb);
1401 kfree(bp->rx_skbuff);
1402 bp->rx_skbuff = NULL;
1405 static void macb_free_rx_buffers(struct macb *bp)
1407 if (bp->rx_buffers) {
1408 dma_free_coherent(&bp->pdev->dev,
1409 RX_RING_SIZE * bp->rx_buffer_size,
1410 bp->rx_buffers, bp->rx_buffers_dma);
1411 bp->rx_buffers = NULL;
1415 static void macb_free_consistent(struct macb *bp)
1417 struct macb_queue *queue;
1420 bp->macbgem_ops.mog_free_rx_buffers(bp);
1422 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
1423 bp->rx_ring, bp->rx_ring_dma);
1427 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1428 kfree(queue->tx_skb);
1429 queue->tx_skb = NULL;
1430 if (queue->tx_ring) {
1431 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
1432 queue->tx_ring, queue->tx_ring_dma);
1433 queue->tx_ring = NULL;
1438 static int gem_alloc_rx_buffers(struct macb *bp)
1442 size = RX_RING_SIZE * sizeof(struct sk_buff *);
1443 bp->rx_skbuff = kzalloc(size, GFP_KERNEL);
1448 "Allocated %d RX struct sk_buff entries at %p\n",
1449 RX_RING_SIZE, bp->rx_skbuff);
1453 static int macb_alloc_rx_buffers(struct macb *bp)
1457 size = RX_RING_SIZE * bp->rx_buffer_size;
1458 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1459 &bp->rx_buffers_dma, GFP_KERNEL);
1460 if (!bp->rx_buffers)
1464 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1465 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
1469 static int macb_alloc_consistent(struct macb *bp)
1471 struct macb_queue *queue;
1475 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1476 size = TX_RING_BYTES;
1477 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1478 &queue->tx_ring_dma,
1480 if (!queue->tx_ring)
1483 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
1484 q, size, (unsigned long)queue->tx_ring_dma,
1487 size = TX_RING_SIZE * sizeof(struct macb_tx_skb);
1488 queue->tx_skb = kmalloc(size, GFP_KERNEL);
1493 size = RX_RING_BYTES;
1494 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1495 &bp->rx_ring_dma, GFP_KERNEL);
1499 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1500 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
1502 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
1508 macb_free_consistent(bp);
1512 static void gem_init_rings(struct macb *bp)
1514 struct macb_queue *queue;
1518 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1519 for (i = 0; i < TX_RING_SIZE; i++) {
1520 queue->tx_ring[i].addr = 0;
1521 queue->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1523 queue->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1529 bp->rx_prepared_head = 0;
1534 static void macb_init_rings(struct macb *bp)
1539 addr = bp->rx_buffers_dma;
1540 for (i = 0; i < RX_RING_SIZE; i++) {
1541 bp->rx_ring[i].addr = addr;
1542 bp->rx_ring[i].ctrl = 0;
1543 addr += bp->rx_buffer_size;
1545 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
1547 for (i = 0; i < TX_RING_SIZE; i++) {
1548 bp->queues[0].tx_ring[i].addr = 0;
1549 bp->queues[0].tx_ring[i].ctrl = MACB_BIT(TX_USED);
1551 bp->queues[0].tx_head = 0;
1552 bp->queues[0].tx_tail = 0;
1553 bp->queues[0].tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1558 static void macb_reset_hw(struct macb *bp)
1560 struct macb_queue *queue;
1564 * Disable RX and TX (XXX: Should we halt the transmission
1567 macb_writel(bp, NCR, 0);
1569 /* Clear the stats registers (XXX: Update stats first?) */
1570 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
1572 /* Clear all status flags */
1573 macb_writel(bp, TSR, -1);
1574 macb_writel(bp, RSR, -1);
1576 /* Disable all interrupts */
1577 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1578 queue_writel(queue, IDR, -1);
1579 queue_readl(queue, ISR);
1583 static u32 gem_mdc_clk_div(struct macb *bp)
1586 unsigned long pclk_hz = clk_get_rate(bp->pclk);
1588 if (pclk_hz <= 20000000)
1589 config = GEM_BF(CLK, GEM_CLK_DIV8);
1590 else if (pclk_hz <= 40000000)
1591 config = GEM_BF(CLK, GEM_CLK_DIV16);
1592 else if (pclk_hz <= 80000000)
1593 config = GEM_BF(CLK, GEM_CLK_DIV32);
1594 else if (pclk_hz <= 120000000)
1595 config = GEM_BF(CLK, GEM_CLK_DIV48);
1596 else if (pclk_hz <= 160000000)
1597 config = GEM_BF(CLK, GEM_CLK_DIV64);
1599 config = GEM_BF(CLK, GEM_CLK_DIV96);
1604 static u32 macb_mdc_clk_div(struct macb *bp)
1607 unsigned long pclk_hz;
1609 if (macb_is_gem(bp))
1610 return gem_mdc_clk_div(bp);
1612 pclk_hz = clk_get_rate(bp->pclk);
1613 if (pclk_hz <= 20000000)
1614 config = MACB_BF(CLK, MACB_CLK_DIV8);
1615 else if (pclk_hz <= 40000000)
1616 config = MACB_BF(CLK, MACB_CLK_DIV16);
1617 else if (pclk_hz <= 80000000)
1618 config = MACB_BF(CLK, MACB_CLK_DIV32);
1620 config = MACB_BF(CLK, MACB_CLK_DIV64);
1626 * Get the DMA bus width field of the network configuration register that we
1627 * should program. We find the width from decoding the design configuration
1628 * register to find the maximum supported data bus width.
1630 static u32 macb_dbw(struct macb *bp)
1632 if (!macb_is_gem(bp))
1635 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
1637 return GEM_BF(DBW, GEM_DBW128);
1639 return GEM_BF(DBW, GEM_DBW64);
1642 return GEM_BF(DBW, GEM_DBW32);
1647 * Configure the receive DMA engine
1648 * - use the correct receive buffer size
1649 * - set best burst length for DMA operations
1650 * (if not supported by FIFO, it will fallback to default)
1651 * - set both rx/tx packet buffers to full memory size
1652 * These are configurable parameters for GEM.
1654 static void macb_configure_dma(struct macb *bp)
1658 if (macb_is_gem(bp)) {
1659 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
1660 dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
1661 if (bp->dma_burst_length)
1662 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
1663 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
1664 dmacfg &= ~GEM_BIT(ENDIA_PKT);
1667 dmacfg &= ~GEM_BIT(ENDIA_DESC);
1669 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
1671 if (bp->dev->features & NETIF_F_HW_CSUM)
1672 dmacfg |= GEM_BIT(TXCOEN);
1674 dmacfg &= ~GEM_BIT(TXCOEN);
1675 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
1677 gem_writel(bp, DMACFG, dmacfg);
1681 static void macb_init_hw(struct macb *bp)
1683 struct macb_queue *queue;
1689 macb_set_hwaddr(bp);
1691 config = macb_mdc_clk_div(bp);
1692 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
1693 config |= MACB_BIT(PAE); /* PAuse Enable */
1694 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
1695 if (bp->caps & MACB_CAPS_JUMBO)
1696 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
1698 config |= MACB_BIT(BIG); /* Receive oversized frames */
1699 if (bp->dev->flags & IFF_PROMISC)
1700 config |= MACB_BIT(CAF); /* Copy All Frames */
1701 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
1702 config |= GEM_BIT(RXCOEN);
1703 if (!(bp->dev->flags & IFF_BROADCAST))
1704 config |= MACB_BIT(NBC); /* No BroadCast */
1705 config |= macb_dbw(bp);
1706 macb_writel(bp, NCFGR, config);
1707 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
1708 gem_writel(bp, JML, bp->jumbo_max_len);
1709 bp->speed = SPEED_10;
1710 bp->duplex = DUPLEX_HALF;
1711 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
1712 if (bp->caps & MACB_CAPS_JUMBO)
1713 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
1715 macb_configure_dma(bp);
1717 /* Initialize TX and RX buffers */
1718 macb_writel(bp, RBQP, bp->rx_ring_dma);
1719 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1720 queue_writel(queue, TBQP, queue->tx_ring_dma);
1722 /* Enable interrupts */
1723 queue_writel(queue, IER,
1729 /* Enable TX and RX */
1730 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
1734 * The hash address register is 64 bits long and takes up two
1735 * locations in the memory map. The least significant bits are stored
1736 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1738 * The unicast hash enable and the multicast hash enable bits in the
1739 * network configuration register enable the reception of hash matched
1740 * frames. The destination address is reduced to a 6 bit index into
1741 * the 64 bit hash register using the following hash function. The
1742 * hash function is an exclusive or of every sixth bit of the
1743 * destination address.
1745 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1746 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
1747 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
1748 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1749 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1750 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1752 * da[0] represents the least significant bit of the first byte
1753 * received, that is, the multicast/unicast indicator, and da[47]
1754 * represents the most significant bit of the last byte received. If
1755 * the hash index, hi[n], points to a bit that is set in the hash
1756 * register then the frame will be matched according to whether the
1757 * frame is multicast or unicast. A multicast match will be signalled
1758 * if the multicast hash enable bit is set, da[0] is 1 and the hash
1759 * index points to a bit set in the hash register. A unicast match
1760 * will be signalled if the unicast hash enable bit is set, da[0] is 0
1761 * and the hash index points to a bit set in the hash register. To
1762 * receive all multicast frames, the hash register should be set with
1763 * all ones and the multicast hash enable bit should be set in the
1764 * network configuration register.
1767 static inline int hash_bit_value(int bitnr, __u8 *addr)
1769 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
1775 * Return the hash index value for the specified address.
1777 static int hash_get_index(__u8 *addr)
1782 for (j = 0; j < 6; j++) {
1783 for (i = 0, bitval = 0; i < 8; i++)
1784 bitval ^= hash_bit_value(i * 6 + j, addr);
1786 hash_index |= (bitval << j);
1793 * Add multicast addresses to the internal multicast-hash table.
1795 static void macb_sethashtable(struct net_device *dev)
1797 struct netdev_hw_addr *ha;
1798 unsigned long mc_filter[2];
1800 struct macb *bp = netdev_priv(dev);
1802 mc_filter[0] = mc_filter[1] = 0;
1804 netdev_for_each_mc_addr(ha, dev) {
1805 bitnr = hash_get_index(ha->addr);
1806 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1809 macb_or_gem_writel(bp, HRB, mc_filter[0]);
1810 macb_or_gem_writel(bp, HRT, mc_filter[1]);
1814 * Enable/Disable promiscuous and multicast modes.
1816 static void macb_set_rx_mode(struct net_device *dev)
1819 struct macb *bp = netdev_priv(dev);
1821 cfg = macb_readl(bp, NCFGR);
1823 if (dev->flags & IFF_PROMISC) {
1824 /* Enable promiscuous mode */
1825 cfg |= MACB_BIT(CAF);
1827 /* Disable RX checksum offload */
1828 if (macb_is_gem(bp))
1829 cfg &= ~GEM_BIT(RXCOEN);
1831 /* Disable promiscuous mode */
1832 cfg &= ~MACB_BIT(CAF);
1834 /* Enable RX checksum offload only if requested */
1835 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
1836 cfg |= GEM_BIT(RXCOEN);
1839 if (dev->flags & IFF_ALLMULTI) {
1840 /* Enable all multicast mode */
1841 macb_or_gem_writel(bp, HRB, -1);
1842 macb_or_gem_writel(bp, HRT, -1);
1843 cfg |= MACB_BIT(NCFGR_MTI);
1844 } else if (!netdev_mc_empty(dev)) {
1845 /* Enable specific multicasts */
1846 macb_sethashtable(dev);
1847 cfg |= MACB_BIT(NCFGR_MTI);
1848 } else if (dev->flags & (~IFF_ALLMULTI)) {
1849 /* Disable all multicast mode */
1850 macb_or_gem_writel(bp, HRB, 0);
1851 macb_or_gem_writel(bp, HRT, 0);
1852 cfg &= ~MACB_BIT(NCFGR_MTI);
1855 macb_writel(bp, NCFGR, cfg);
1858 static int macb_open(struct net_device *dev)
1860 struct macb *bp = netdev_priv(dev);
1861 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
1864 netdev_dbg(bp->dev, "open\n");
1866 /* carrier starts down */
1867 netif_carrier_off(dev);
1869 /* if the phy is not yet register, retry later*/
1873 /* RX buffers initialization */
1874 macb_init_rx_buffer_size(bp, bufsz);
1876 err = macb_alloc_consistent(bp);
1878 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1883 napi_enable(&bp->napi);
1885 bp->macbgem_ops.mog_init_rings(bp);
1888 /* schedule a link state check */
1889 phy_start(bp->phy_dev);
1891 netif_tx_start_all_queues(dev);
1896 static int macb_close(struct net_device *dev)
1898 struct macb *bp = netdev_priv(dev);
1899 unsigned long flags;
1901 netif_tx_stop_all_queues(dev);
1902 napi_disable(&bp->napi);
1905 phy_stop(bp->phy_dev);
1907 spin_lock_irqsave(&bp->lock, flags);
1909 netif_carrier_off(dev);
1910 spin_unlock_irqrestore(&bp->lock, flags);
1912 macb_free_consistent(bp);
1917 static int macb_change_mtu(struct net_device *dev, int new_mtu)
1919 struct macb *bp = netdev_priv(dev);
1922 if (netif_running(dev))
1925 max_mtu = ETH_DATA_LEN;
1926 if (bp->caps & MACB_CAPS_JUMBO)
1927 max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
1929 if ((new_mtu > max_mtu) || (new_mtu < GEM_MTU_MIN_SIZE))
1937 static void gem_update_stats(struct macb *bp)
1940 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
1942 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
1943 u32 offset = gem_statistics[i].offset;
1944 u64 val = bp->readl(bp, offset);
1946 bp->ethtool_stats[i] += val;
1949 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
1950 /* Add GEM_OCTTXH, GEM_OCTRXH */
1951 val = bp->readl(bp, offset + 4);
1952 bp->ethtool_stats[i] += ((u64)val) << 32;
1958 static struct net_device_stats *gem_get_stats(struct macb *bp)
1960 struct gem_stats *hwstat = &bp->hw_stats.gem;
1961 struct net_device_stats *nstat = &bp->stats;
1963 gem_update_stats(bp);
1965 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
1966 hwstat->rx_alignment_errors +
1967 hwstat->rx_resource_errors +
1968 hwstat->rx_overruns +
1969 hwstat->rx_oversize_frames +
1970 hwstat->rx_jabbers +
1971 hwstat->rx_undersized_frames +
1972 hwstat->rx_length_field_frame_errors);
1973 nstat->tx_errors = (hwstat->tx_late_collisions +
1974 hwstat->tx_excessive_collisions +
1975 hwstat->tx_underrun +
1976 hwstat->tx_carrier_sense_errors);
1977 nstat->multicast = hwstat->rx_multicast_frames;
1978 nstat->collisions = (hwstat->tx_single_collision_frames +
1979 hwstat->tx_multiple_collision_frames +
1980 hwstat->tx_excessive_collisions);
1981 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
1982 hwstat->rx_jabbers +
1983 hwstat->rx_undersized_frames +
1984 hwstat->rx_length_field_frame_errors);
1985 nstat->rx_over_errors = hwstat->rx_resource_errors;
1986 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
1987 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
1988 nstat->rx_fifo_errors = hwstat->rx_overruns;
1989 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
1990 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
1991 nstat->tx_fifo_errors = hwstat->tx_underrun;
1996 static void gem_get_ethtool_stats(struct net_device *dev,
1997 struct ethtool_stats *stats, u64 *data)
2001 bp = netdev_priv(dev);
2002 gem_update_stats(bp);
2003 memcpy(data, &bp->ethtool_stats, sizeof(u64) * GEM_STATS_LEN);
2006 static int gem_get_sset_count(struct net_device *dev, int sset)
2010 return GEM_STATS_LEN;
2016 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
2022 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
2023 memcpy(p, gem_statistics[i].stat_string,
2029 static struct net_device_stats *macb_get_stats(struct net_device *dev)
2031 struct macb *bp = netdev_priv(dev);
2032 struct net_device_stats *nstat = &bp->stats;
2033 struct macb_stats *hwstat = &bp->hw_stats.macb;
2035 if (macb_is_gem(bp))
2036 return gem_get_stats(bp);
2038 /* read stats from hardware */
2039 macb_update_stats(bp);
2041 /* Convert HW stats into netdevice stats */
2042 nstat->rx_errors = (hwstat->rx_fcs_errors +
2043 hwstat->rx_align_errors +
2044 hwstat->rx_resource_errors +
2045 hwstat->rx_overruns +
2046 hwstat->rx_oversize_pkts +
2047 hwstat->rx_jabbers +
2048 hwstat->rx_undersize_pkts +
2049 hwstat->rx_length_mismatch);
2050 nstat->tx_errors = (hwstat->tx_late_cols +
2051 hwstat->tx_excessive_cols +
2052 hwstat->tx_underruns +
2053 hwstat->tx_carrier_errors +
2054 hwstat->sqe_test_errors);
2055 nstat->collisions = (hwstat->tx_single_cols +
2056 hwstat->tx_multiple_cols +
2057 hwstat->tx_excessive_cols);
2058 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2059 hwstat->rx_jabbers +
2060 hwstat->rx_undersize_pkts +
2061 hwstat->rx_length_mismatch);
2062 nstat->rx_over_errors = hwstat->rx_resource_errors +
2063 hwstat->rx_overruns;
2064 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2065 nstat->rx_frame_errors = hwstat->rx_align_errors;
2066 nstat->rx_fifo_errors = hwstat->rx_overruns;
2067 /* XXX: What does "missed" mean? */
2068 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
2069 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
2070 nstat->tx_fifo_errors = hwstat->tx_underruns;
2071 /* Don't know about heartbeat or window errors... */
2076 static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2078 struct macb *bp = netdev_priv(dev);
2079 struct phy_device *phydev = bp->phy_dev;
2084 return phy_ethtool_gset(phydev, cmd);
2087 static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2089 struct macb *bp = netdev_priv(dev);
2090 struct phy_device *phydev = bp->phy_dev;
2095 return phy_ethtool_sset(phydev, cmd);
2098 static int macb_get_regs_len(struct net_device *netdev)
2100 return MACB_GREGS_NBR * sizeof(u32);
2103 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2106 struct macb *bp = netdev_priv(dev);
2107 unsigned int tail, head;
2110 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2111 | MACB_GREGS_VERSION;
2113 tail = macb_tx_ring_wrap(bp->queues[0].tx_tail);
2114 head = macb_tx_ring_wrap(bp->queues[0].tx_head);
2116 regs_buff[0] = macb_readl(bp, NCR);
2117 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
2118 regs_buff[2] = macb_readl(bp, NSR);
2119 regs_buff[3] = macb_readl(bp, TSR);
2120 regs_buff[4] = macb_readl(bp, RBQP);
2121 regs_buff[5] = macb_readl(bp, TBQP);
2122 regs_buff[6] = macb_readl(bp, RSR);
2123 regs_buff[7] = macb_readl(bp, IMR);
2125 regs_buff[8] = tail;
2126 regs_buff[9] = head;
2127 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2128 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
2130 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
2131 if (macb_is_gem(bp)) {
2132 regs_buff[13] = gem_readl(bp, DMACFG);
2136 static const struct ethtool_ops macb_ethtool_ops = {
2137 .get_settings = macb_get_settings,
2138 .set_settings = macb_set_settings,
2139 .get_regs_len = macb_get_regs_len,
2140 .get_regs = macb_get_regs,
2141 .get_link = ethtool_op_get_link,
2142 .get_ts_info = ethtool_op_get_ts_info,
2145 static const struct ethtool_ops gem_ethtool_ops = {
2146 .get_settings = macb_get_settings,
2147 .set_settings = macb_set_settings,
2148 .get_regs_len = macb_get_regs_len,
2149 .get_regs = macb_get_regs,
2150 .get_link = ethtool_op_get_link,
2151 .get_ts_info = ethtool_op_get_ts_info,
2152 .get_ethtool_stats = gem_get_ethtool_stats,
2153 .get_strings = gem_get_ethtool_strings,
2154 .get_sset_count = gem_get_sset_count,
2157 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2159 struct macb *bp = netdev_priv(dev);
2160 struct phy_device *phydev = bp->phy_dev;
2162 if (!netif_running(dev))
2168 return phy_mii_ioctl(phydev, rq, cmd);
2171 static int macb_set_features(struct net_device *netdev,
2172 netdev_features_t features)
2174 struct macb *bp = netdev_priv(netdev);
2175 netdev_features_t changed = features ^ netdev->features;
2177 /* TX checksum offload */
2178 if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) {
2181 dmacfg = gem_readl(bp, DMACFG);
2182 if (features & NETIF_F_HW_CSUM)
2183 dmacfg |= GEM_BIT(TXCOEN);
2185 dmacfg &= ~GEM_BIT(TXCOEN);
2186 gem_writel(bp, DMACFG, dmacfg);
2189 /* RX checksum offload */
2190 if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) {
2193 netcfg = gem_readl(bp, NCFGR);
2194 if (features & NETIF_F_RXCSUM &&
2195 !(netdev->flags & IFF_PROMISC))
2196 netcfg |= GEM_BIT(RXCOEN);
2198 netcfg &= ~GEM_BIT(RXCOEN);
2199 gem_writel(bp, NCFGR, netcfg);
2205 static const struct net_device_ops macb_netdev_ops = {
2206 .ndo_open = macb_open,
2207 .ndo_stop = macb_close,
2208 .ndo_start_xmit = macb_start_xmit,
2209 .ndo_set_rx_mode = macb_set_rx_mode,
2210 .ndo_get_stats = macb_get_stats,
2211 .ndo_do_ioctl = macb_ioctl,
2212 .ndo_validate_addr = eth_validate_addr,
2213 .ndo_change_mtu = macb_change_mtu,
2214 .ndo_set_mac_address = eth_mac_addr,
2215 #ifdef CONFIG_NET_POLL_CONTROLLER
2216 .ndo_poll_controller = macb_poll_controller,
2218 .ndo_set_features = macb_set_features,
2222 * Configure peripheral capabilities according to device tree
2223 * and integration options used
2225 static void macb_configure_caps(struct macb *bp, const struct macb_config *dt_conf)
2230 bp->caps = dt_conf->caps;
2232 if (hw_is_gem(bp->regs, bp->native_io)) {
2233 bp->caps |= MACB_CAPS_MACB_IS_GEM;
2235 dcfg = gem_readl(bp, DCFG1);
2236 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
2237 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
2238 dcfg = gem_readl(bp, DCFG2);
2239 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
2240 bp->caps |= MACB_CAPS_FIFO_MODE;
2243 netdev_dbg(bp->dev, "Cadence caps 0x%08x\n", bp->caps);
2246 static void macb_probe_queues(void __iomem *mem,
2248 unsigned int *queue_mask,
2249 unsigned int *num_queues)
2256 /* is it macb or gem ?
2258 * We need to read directly from the hardware here because
2259 * we are early in the probe process and don't have the
2260 * MACB_CAPS_MACB_IS_GEM flag positioned
2262 if (!hw_is_gem(mem, native_io))
2265 /* bit 0 is never set but queue 0 always exists */
2266 *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff;
2270 for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q)
2271 if (*queue_mask & (1 << hw_q))
2275 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
2276 struct clk **hclk, struct clk **tx_clk)
2280 *pclk = devm_clk_get(&pdev->dev, "pclk");
2281 if (IS_ERR(*pclk)) {
2282 err = PTR_ERR(*pclk);
2283 dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err);
2287 *hclk = devm_clk_get(&pdev->dev, "hclk");
2288 if (IS_ERR(*hclk)) {
2289 err = PTR_ERR(*hclk);
2290 dev_err(&pdev->dev, "failed to get hclk (%u)\n", err);
2294 *tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
2295 if (IS_ERR(*tx_clk))
2298 err = clk_prepare_enable(*pclk);
2300 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
2304 err = clk_prepare_enable(*hclk);
2306 dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err);
2307 goto err_disable_pclk;
2310 err = clk_prepare_enable(*tx_clk);
2312 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
2313 goto err_disable_hclk;
2319 clk_disable_unprepare(*hclk);
2322 clk_disable_unprepare(*pclk);
2327 static int macb_init(struct platform_device *pdev)
2329 struct net_device *dev = platform_get_drvdata(pdev);
2330 unsigned int hw_q, q;
2331 struct macb *bp = netdev_priv(dev);
2332 struct macb_queue *queue;
2336 /* set the queue register mapping once for all: queue0 has a special
2337 * register mapping but we don't want to test the queue index then
2338 * compute the corresponding register offset at run time.
2340 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
2341 if (!(bp->queue_mask & (1 << hw_q)))
2344 queue = &bp->queues[q];
2347 queue->ISR = GEM_ISR(hw_q - 1);
2348 queue->IER = GEM_IER(hw_q - 1);
2349 queue->IDR = GEM_IDR(hw_q - 1);
2350 queue->IMR = GEM_IMR(hw_q - 1);
2351 queue->TBQP = GEM_TBQP(hw_q - 1);
2353 /* queue0 uses legacy registers */
2354 queue->ISR = MACB_ISR;
2355 queue->IER = MACB_IER;
2356 queue->IDR = MACB_IDR;
2357 queue->IMR = MACB_IMR;
2358 queue->TBQP = MACB_TBQP;
2361 /* get irq: here we use the linux queue index, not the hardware
2362 * queue index. the queue irq definitions in the device tree
2363 * must remove the optional gaps that could exist in the
2364 * hardware queue mask.
2366 queue->irq = platform_get_irq(pdev, q);
2367 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
2368 IRQF_SHARED, dev->name, queue);
2371 "Unable to request IRQ %d (error %d)\n",
2376 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
2380 dev->netdev_ops = &macb_netdev_ops;
2381 netif_napi_add(dev, &bp->napi, macb_poll, 64);
2383 /* setup appropriated routines according to adapter type */
2384 if (macb_is_gem(bp)) {
2385 bp->max_tx_length = GEM_MAX_TX_LEN;
2386 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
2387 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
2388 bp->macbgem_ops.mog_init_rings = gem_init_rings;
2389 bp->macbgem_ops.mog_rx = gem_rx;
2390 dev->ethtool_ops = &gem_ethtool_ops;
2392 bp->max_tx_length = MACB_MAX_TX_LEN;
2393 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
2394 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
2395 bp->macbgem_ops.mog_init_rings = macb_init_rings;
2396 bp->macbgem_ops.mog_rx = macb_rx;
2397 dev->ethtool_ops = &macb_ethtool_ops;
2401 dev->hw_features = NETIF_F_SG;
2402 /* Checksum offload is only available on gem with packet buffer */
2403 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
2404 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
2405 if (bp->caps & MACB_CAPS_SG_DISABLED)
2406 dev->hw_features &= ~NETIF_F_SG;
2407 dev->features = dev->hw_features;
2410 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
2411 val = GEM_BIT(RGMII);
2412 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
2413 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
2414 val = MACB_BIT(RMII);
2415 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
2416 val = MACB_BIT(MII);
2418 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
2419 val |= MACB_BIT(CLKEN);
2421 macb_or_gem_writel(bp, USRIO, val);
2423 /* Set MII management clock divider */
2424 val = macb_mdc_clk_div(bp);
2425 val |= macb_dbw(bp);
2426 macb_writel(bp, NCFGR, val);
2431 #if defined(CONFIG_OF)
2432 /* 1518 rounded up */
2433 #define AT91ETHER_MAX_RBUFF_SZ 0x600
2434 /* max number of receive buffers */
2435 #define AT91ETHER_MAX_RX_DESCR 9
2437 /* Initialize and start the Receiver and Transmit subsystems */
2438 static int at91ether_start(struct net_device *dev)
2440 struct macb *lp = netdev_priv(dev);
2445 lp->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
2446 (AT91ETHER_MAX_RX_DESCR *
2447 sizeof(struct macb_dma_desc)),
2448 &lp->rx_ring_dma, GFP_KERNEL);
2452 lp->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
2453 AT91ETHER_MAX_RX_DESCR *
2454 AT91ETHER_MAX_RBUFF_SZ,
2455 &lp->rx_buffers_dma, GFP_KERNEL);
2456 if (!lp->rx_buffers) {
2457 dma_free_coherent(&lp->pdev->dev,
2458 AT91ETHER_MAX_RX_DESCR *
2459 sizeof(struct macb_dma_desc),
2460 lp->rx_ring, lp->rx_ring_dma);
2465 addr = lp->rx_buffers_dma;
2466 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
2467 lp->rx_ring[i].addr = addr;
2468 lp->rx_ring[i].ctrl = 0;
2469 addr += AT91ETHER_MAX_RBUFF_SZ;
2472 /* Set the Wrap bit on the last descriptor */
2473 lp->rx_ring[AT91ETHER_MAX_RX_DESCR - 1].addr |= MACB_BIT(RX_WRAP);
2475 /* Reset buffer index */
2478 /* Program address of descriptor list in Rx Buffer Queue register */
2479 macb_writel(lp, RBQP, lp->rx_ring_dma);
2481 /* Enable Receive and Transmit */
2482 ctl = macb_readl(lp, NCR);
2483 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
2488 /* Open the ethernet interface */
2489 static int at91ether_open(struct net_device *dev)
2491 struct macb *lp = netdev_priv(dev);
2495 /* Clear internal statistics */
2496 ctl = macb_readl(lp, NCR);
2497 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
2499 macb_set_hwaddr(lp);
2501 ret = at91ether_start(dev);
2505 /* Enable MAC interrupts */
2506 macb_writel(lp, IER, MACB_BIT(RCOMP) |
2508 MACB_BIT(ISR_TUND) |
2511 MACB_BIT(ISR_ROVR) |
2514 /* schedule a link state check */
2515 phy_start(lp->phy_dev);
2517 netif_start_queue(dev);
2522 /* Close the interface */
2523 static int at91ether_close(struct net_device *dev)
2525 struct macb *lp = netdev_priv(dev);
2528 /* Disable Receiver and Transmitter */
2529 ctl = macb_readl(lp, NCR);
2530 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
2532 /* Disable MAC interrupts */
2533 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
2535 MACB_BIT(ISR_TUND) |
2538 MACB_BIT(ISR_ROVR) |
2541 netif_stop_queue(dev);
2543 dma_free_coherent(&lp->pdev->dev,
2544 AT91ETHER_MAX_RX_DESCR *
2545 sizeof(struct macb_dma_desc),
2546 lp->rx_ring, lp->rx_ring_dma);
2549 dma_free_coherent(&lp->pdev->dev,
2550 AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ,
2551 lp->rx_buffers, lp->rx_buffers_dma);
2552 lp->rx_buffers = NULL;
2557 /* Transmit packet */
2558 static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
2560 struct macb *lp = netdev_priv(dev);
2562 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
2563 netif_stop_queue(dev);
2565 /* Store packet information (to free when Tx completed) */
2567 lp->skb_length = skb->len;
2568 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len,
2571 /* Set address of the data in the Transmit Address register */
2572 macb_writel(lp, TAR, lp->skb_physaddr);
2573 /* Set length of the packet in the Transmit Control register */
2574 macb_writel(lp, TCR, skb->len);
2577 netdev_err(dev, "%s called, but device is busy!\n", __func__);
2578 return NETDEV_TX_BUSY;
2581 return NETDEV_TX_OK;
2584 /* Extract received frame from buffer descriptors and sent to upper layers.
2585 * (Called from interrupt context)
2587 static void at91ether_rx(struct net_device *dev)
2589 struct macb *lp = netdev_priv(dev);
2590 unsigned char *p_recv;
2591 struct sk_buff *skb;
2592 unsigned int pktlen;
2594 while (lp->rx_ring[lp->rx_tail].addr & MACB_BIT(RX_USED)) {
2595 p_recv = lp->rx_buffers + lp->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
2596 pktlen = MACB_BF(RX_FRMLEN, lp->rx_ring[lp->rx_tail].ctrl);
2597 skb = netdev_alloc_skb(dev, pktlen + 2);
2599 skb_reserve(skb, 2);
2600 memcpy(skb_put(skb, pktlen), p_recv, pktlen);
2602 skb->protocol = eth_type_trans(skb, dev);
2603 lp->stats.rx_packets++;
2604 lp->stats.rx_bytes += pktlen;
2607 lp->stats.rx_dropped++;
2610 if (lp->rx_ring[lp->rx_tail].ctrl & MACB_BIT(RX_MHASH_MATCH))
2611 lp->stats.multicast++;
2613 /* reset ownership bit */
2614 lp->rx_ring[lp->rx_tail].addr &= ~MACB_BIT(RX_USED);
2616 /* wrap after last buffer */
2617 if (lp->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
2624 /* MAC interrupt handler */
2625 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
2627 struct net_device *dev = dev_id;
2628 struct macb *lp = netdev_priv(dev);
2631 /* MAC Interrupt Status register indicates what interrupts are pending.
2632 * It is automatically cleared once read.
2634 intstatus = macb_readl(lp, ISR);
2636 /* Receive complete */
2637 if (intstatus & MACB_BIT(RCOMP))
2640 /* Transmit complete */
2641 if (intstatus & MACB_BIT(TCOMP)) {
2642 /* The TCOM bit is set even if the transmission failed */
2643 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
2644 lp->stats.tx_errors++;
2647 dev_kfree_skb_irq(lp->skb);
2649 dma_unmap_single(NULL, lp->skb_physaddr,
2650 lp->skb_length, DMA_TO_DEVICE);
2651 lp->stats.tx_packets++;
2652 lp->stats.tx_bytes += lp->skb_length;
2654 netif_wake_queue(dev);
2657 /* Work-around for EMAC Errata section 41.3.1 */
2658 if (intstatus & MACB_BIT(RXUBR)) {
2659 ctl = macb_readl(lp, NCR);
2660 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
2661 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
2664 if (intstatus & MACB_BIT(ISR_ROVR))
2665 netdev_err(dev, "ROVR error\n");
2670 #ifdef CONFIG_NET_POLL_CONTROLLER
2671 static void at91ether_poll_controller(struct net_device *dev)
2673 unsigned long flags;
2675 local_irq_save(flags);
2676 at91ether_interrupt(dev->irq, dev);
2677 local_irq_restore(flags);
2681 static const struct net_device_ops at91ether_netdev_ops = {
2682 .ndo_open = at91ether_open,
2683 .ndo_stop = at91ether_close,
2684 .ndo_start_xmit = at91ether_start_xmit,
2685 .ndo_get_stats = macb_get_stats,
2686 .ndo_set_rx_mode = macb_set_rx_mode,
2687 .ndo_set_mac_address = eth_mac_addr,
2688 .ndo_do_ioctl = macb_ioctl,
2689 .ndo_validate_addr = eth_validate_addr,
2690 .ndo_change_mtu = eth_change_mtu,
2691 #ifdef CONFIG_NET_POLL_CONTROLLER
2692 .ndo_poll_controller = at91ether_poll_controller,
2696 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
2697 struct clk **hclk, struct clk **tx_clk)
2704 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
2706 return PTR_ERR(*pclk);
2708 err = clk_prepare_enable(*pclk);
2710 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
2717 static int at91ether_init(struct platform_device *pdev)
2719 struct net_device *dev = platform_get_drvdata(pdev);
2720 struct macb *bp = netdev_priv(dev);
2724 dev->netdev_ops = &at91ether_netdev_ops;
2725 dev->ethtool_ops = &macb_ethtool_ops;
2727 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
2732 macb_writel(bp, NCR, 0);
2734 reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG);
2735 if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
2736 reg |= MACB_BIT(RM9200_RMII);
2738 macb_writel(bp, NCFGR, reg);
2743 static const struct macb_config at91sam9260_config = {
2744 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII,
2745 .clk_init = macb_clk_init,
2749 static const struct macb_config pc302gem_config = {
2750 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
2751 .dma_burst_length = 16,
2752 .clk_init = macb_clk_init,
2756 static const struct macb_config sama5d2_config = {
2758 .dma_burst_length = 16,
2759 .clk_init = macb_clk_init,
2763 static const struct macb_config sama5d3_config = {
2764 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
2765 .dma_burst_length = 16,
2766 .clk_init = macb_clk_init,
2770 static const struct macb_config sama5d4_config = {
2772 .dma_burst_length = 4,
2773 .clk_init = macb_clk_init,
2777 static const struct macb_config emac_config = {
2778 .clk_init = at91ether_clk_init,
2779 .init = at91ether_init,
2783 static const struct macb_config zynqmp_config = {
2784 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE |
2786 .dma_burst_length = 16,
2787 .clk_init = macb_clk_init,
2789 .jumbo_max_len = 10240,
2792 static const struct macb_config zynq_config = {
2793 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE |
2794 MACB_CAPS_NO_GIGABIT_HALF,
2795 .dma_burst_length = 16,
2796 .clk_init = macb_clk_init,
2800 static const struct of_device_id macb_dt_ids[] = {
2801 { .compatible = "cdns,at32ap7000-macb" },
2802 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
2803 { .compatible = "cdns,macb" },
2804 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
2805 { .compatible = "cdns,gem", .data = &pc302gem_config },
2806 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
2807 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
2808 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
2809 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
2810 { .compatible = "cdns,emac", .data = &emac_config },
2811 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
2812 { .compatible = "cdns,zynq-gem", .data = &zynq_config },
2815 MODULE_DEVICE_TABLE(of, macb_dt_ids);
2816 #endif /* CONFIG_OF */
2818 static int macb_probe(struct platform_device *pdev)
2820 int (*clk_init)(struct platform_device *, struct clk **,
2821 struct clk **, struct clk **)
2823 int (*init)(struct platform_device *) = macb_init;
2824 struct device_node *np = pdev->dev.of_node;
2825 const struct macb_config *macb_config = NULL;
2826 struct clk *pclk, *hclk, *tx_clk;
2827 unsigned int queue_mask, num_queues;
2828 struct macb_platform_data *pdata;
2830 struct phy_device *phydev;
2831 struct net_device *dev;
2832 struct resource *regs;
2838 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2839 mem = devm_ioremap_resource(&pdev->dev, regs);
2841 return PTR_ERR(mem);
2844 const struct of_device_id *match;
2846 match = of_match_node(macb_dt_ids, np);
2847 if (match && match->data) {
2848 macb_config = match->data;
2849 clk_init = macb_config->clk_init;
2850 init = macb_config->init;
2854 err = clk_init(pdev, &pclk, &hclk, &tx_clk);
2858 native_io = hw_is_native_io(mem);
2860 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
2861 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
2864 goto err_disable_clocks;
2867 dev->base_addr = regs->start;
2869 SET_NETDEV_DEV(dev, &pdev->dev);
2871 bp = netdev_priv(dev);
2875 bp->native_io = native_io;
2877 bp->readl = hw_readl_native;
2878 bp->writel = hw_writel_native;
2880 bp->readl = hw_readl;
2881 bp->writel = hw_writel;
2883 bp->num_queues = num_queues;
2884 bp->queue_mask = queue_mask;
2886 bp->dma_burst_length = macb_config->dma_burst_length;
2889 bp->tx_clk = tx_clk;
2890 if (macb_config->jumbo_max_len) {
2891 bp->jumbo_max_len = macb_config->jumbo_max_len;
2894 spin_lock_init(&bp->lock);
2896 /* setup capabilities */
2897 macb_configure_caps(bp, macb_config);
2899 platform_set_drvdata(pdev, dev);
2901 dev->irq = platform_get_irq(pdev, 0);
2904 goto err_disable_clocks;
2907 mac = of_get_mac_address(np);
2909 memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
2911 macb_get_hwaddr(bp);
2913 err = of_get_phy_mode(np);
2915 pdata = dev_get_platdata(&pdev->dev);
2916 if (pdata && pdata->is_rmii)
2917 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
2919 bp->phy_interface = PHY_INTERFACE_MODE_MII;
2921 bp->phy_interface = err;
2924 /* IP specific init */
2927 goto err_out_free_netdev;
2929 err = register_netdev(dev);
2931 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
2932 goto err_out_unregister_netdev;
2935 err = macb_mii_init(bp);
2937 goto err_out_unregister_netdev;
2939 netif_carrier_off(dev);
2941 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
2942 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
2943 dev->base_addr, dev->irq, dev->dev_addr);
2945 phydev = bp->phy_dev;
2946 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
2947 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
2951 err_out_unregister_netdev:
2952 unregister_netdev(dev);
2954 err_out_free_netdev:
2958 clk_disable_unprepare(tx_clk);
2959 clk_disable_unprepare(hclk);
2960 clk_disable_unprepare(pclk);
2965 static int macb_remove(struct platform_device *pdev)
2967 struct net_device *dev;
2970 dev = platform_get_drvdata(pdev);
2973 bp = netdev_priv(dev);
2975 phy_disconnect(bp->phy_dev);
2976 mdiobus_unregister(bp->mii_bus);
2977 kfree(bp->mii_bus->irq);
2978 mdiobus_free(bp->mii_bus);
2979 unregister_netdev(dev);
2980 clk_disable_unprepare(bp->tx_clk);
2981 clk_disable_unprepare(bp->hclk);
2982 clk_disable_unprepare(bp->pclk);
2989 static int __maybe_unused macb_suspend(struct device *dev)
2991 struct platform_device *pdev = to_platform_device(dev);
2992 struct net_device *netdev = platform_get_drvdata(pdev);
2993 struct macb *bp = netdev_priv(netdev);
2995 netif_carrier_off(netdev);
2996 netif_device_detach(netdev);
2998 clk_disable_unprepare(bp->tx_clk);
2999 clk_disable_unprepare(bp->hclk);
3000 clk_disable_unprepare(bp->pclk);
3005 static int __maybe_unused macb_resume(struct device *dev)
3007 struct platform_device *pdev = to_platform_device(dev);
3008 struct net_device *netdev = platform_get_drvdata(pdev);
3009 struct macb *bp = netdev_priv(netdev);
3011 clk_prepare_enable(bp->pclk);
3012 clk_prepare_enable(bp->hclk);
3013 clk_prepare_enable(bp->tx_clk);
3015 netif_device_attach(netdev);
3020 static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
3022 static struct platform_driver macb_driver = {
3023 .probe = macb_probe,
3024 .remove = macb_remove,
3027 .of_match_table = of_match_ptr(macb_dt_ids),
3032 module_platform_driver(macb_driver);
3034 MODULE_LICENSE("GPL");
3035 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
3036 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
3037 MODULE_ALIAS("platform:macb");