2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2011 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/skbuff.h>
35 #include <linux/ethtool.h>
36 #include <linux/mdio.h>
37 #include <linux/mii.h>
38 #include <linux/phy.h>
39 #include <linux/brcmphy.h>
40 #include <linux/if_vlan.h>
42 #include <linux/tcp.h>
43 #include <linux/workqueue.h>
44 #include <linux/prefetch.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/firmware.h>
48 #include <net/checksum.h>
51 #include <asm/system.h>
53 #include <asm/byteorder.h>
54 #include <linux/uaccess.h>
57 #include <asm/idprom.h>
66 /* Functions & macros to verify TG3_FLAGS types */
68 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
70 return test_bit(flag, bits);
73 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
78 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
80 clear_bit(flag, bits);
83 #define tg3_flag(tp, flag) \
84 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
85 #define tg3_flag_set(tp, flag) \
86 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
87 #define tg3_flag_clear(tp, flag) \
88 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
90 #define DRV_MODULE_NAME "tg3"
92 #define TG3_MIN_NUM 121
93 #define DRV_MODULE_VERSION \
94 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
95 #define DRV_MODULE_RELDATE "November 2, 2011"
97 #define RESET_KIND_SHUTDOWN 0
98 #define RESET_KIND_INIT 1
99 #define RESET_KIND_SUSPEND 2
101 #define TG3_DEF_RX_MODE 0
102 #define TG3_DEF_TX_MODE 0
103 #define TG3_DEF_MSG_ENABLE \
113 #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
115 /* length of time before we decide the hardware is borked,
116 * and dev->tx_timeout() should be called to fix the problem
119 #define TG3_TX_TIMEOUT (5 * HZ)
121 /* hardware minimum and maximum for a single frame's data payload */
122 #define TG3_MIN_MTU 60
123 #define TG3_MAX_MTU(tp) \
124 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
126 /* These numbers seem to be hard coded in the NIC firmware somehow.
127 * You can't change the ring sizes, but you can change where you place
128 * them in the NIC onboard memory.
130 #define TG3_RX_STD_RING_SIZE(tp) \
131 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
132 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
133 #define TG3_DEF_RX_RING_PENDING 200
134 #define TG3_RX_JMB_RING_SIZE(tp) \
135 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
136 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
137 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
138 #define TG3_RSS_INDIR_TBL_SIZE 128
140 /* Do not place this n-ring entries value into the tp struct itself,
141 * we really want to expose these constants to GCC so that modulo et
142 * al. operations are done with shifts and masks instead of with
143 * hw multiply/modulo instructions. Another solution would be to
144 * replace things like '% foo' with '& (foo - 1)'.
147 #define TG3_TX_RING_SIZE 512
148 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
150 #define TG3_RX_STD_RING_BYTES(tp) \
151 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
152 #define TG3_RX_JMB_RING_BYTES(tp) \
153 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
154 #define TG3_RX_RCB_RING_BYTES(tp) \
155 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
156 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
158 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
160 #define TG3_DMA_BYTE_ENAB 64
162 #define TG3_RX_STD_DMA_SZ 1536
163 #define TG3_RX_JMB_DMA_SZ 9046
165 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
167 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
168 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
170 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
171 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
173 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
174 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
176 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
177 * that are at least dword aligned when used in PCIX mode. The driver
178 * works around this bug by double copying the packet. This workaround
179 * is built into the normal double copy length check for efficiency.
181 * However, the double copy is only necessary on those architectures
182 * where unaligned memory accesses are inefficient. For those architectures
183 * where unaligned memory accesses incur little penalty, we can reintegrate
184 * the 5701 in the normal rx path. Doing so saves a device structure
185 * dereference by hardcoding the double copy threshold in place.
187 #define TG3_RX_COPY_THRESHOLD 256
188 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
189 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
191 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
194 #if (NET_IP_ALIGN != 0)
195 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
197 #define TG3_RX_OFFSET(tp) 0
200 /* minimum number of free TX descriptors required to wake up TX process */
201 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
202 #define TG3_TX_BD_DMA_MAX 4096
204 #define TG3_RAW_IP_ALIGN 2
206 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
208 #define FIRMWARE_TG3 "tigon/tg3.bin"
209 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
210 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
212 static char version[] __devinitdata =
213 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
215 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
216 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
217 MODULE_LICENSE("GPL");
218 MODULE_VERSION(DRV_MODULE_VERSION);
219 MODULE_FIRMWARE(FIRMWARE_TG3);
220 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
221 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
223 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
224 module_param(tg3_debug, int, 0);
225 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
227 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
289 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
290 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
291 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
292 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
295 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
301 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
302 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
303 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
304 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
305 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
306 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
307 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
308 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
312 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
314 static const struct {
315 const char string[ETH_GSTRING_LEN];
316 } ethtool_stats_keys[] = {
319 { "rx_ucast_packets" },
320 { "rx_mcast_packets" },
321 { "rx_bcast_packets" },
323 { "rx_align_errors" },
324 { "rx_xon_pause_rcvd" },
325 { "rx_xoff_pause_rcvd" },
326 { "rx_mac_ctrl_rcvd" },
327 { "rx_xoff_entered" },
328 { "rx_frame_too_long_errors" },
330 { "rx_undersize_packets" },
331 { "rx_in_length_errors" },
332 { "rx_out_length_errors" },
333 { "rx_64_or_less_octet_packets" },
334 { "rx_65_to_127_octet_packets" },
335 { "rx_128_to_255_octet_packets" },
336 { "rx_256_to_511_octet_packets" },
337 { "rx_512_to_1023_octet_packets" },
338 { "rx_1024_to_1522_octet_packets" },
339 { "rx_1523_to_2047_octet_packets" },
340 { "rx_2048_to_4095_octet_packets" },
341 { "rx_4096_to_8191_octet_packets" },
342 { "rx_8192_to_9022_octet_packets" },
349 { "tx_flow_control" },
351 { "tx_single_collisions" },
352 { "tx_mult_collisions" },
354 { "tx_excessive_collisions" },
355 { "tx_late_collisions" },
356 { "tx_collide_2times" },
357 { "tx_collide_3times" },
358 { "tx_collide_4times" },
359 { "tx_collide_5times" },
360 { "tx_collide_6times" },
361 { "tx_collide_7times" },
362 { "tx_collide_8times" },
363 { "tx_collide_9times" },
364 { "tx_collide_10times" },
365 { "tx_collide_11times" },
366 { "tx_collide_12times" },
367 { "tx_collide_13times" },
368 { "tx_collide_14times" },
369 { "tx_collide_15times" },
370 { "tx_ucast_packets" },
371 { "tx_mcast_packets" },
372 { "tx_bcast_packets" },
373 { "tx_carrier_sense_errors" },
377 { "dma_writeq_full" },
378 { "dma_write_prioq_full" },
382 { "rx_threshold_hit" },
384 { "dma_readq_full" },
385 { "dma_read_prioq_full" },
386 { "tx_comp_queue_full" },
388 { "ring_set_send_prod_index" },
389 { "ring_status_update" },
391 { "nic_avoided_irqs" },
392 { "nic_tx_threshold_hit" },
394 { "mbuf_lwm_thresh_hit" },
397 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
400 static const struct {
401 const char string[ETH_GSTRING_LEN];
402 } ethtool_test_keys[] = {
403 { "nvram test (online) " },
404 { "link test (online) " },
405 { "register test (offline)" },
406 { "memory test (offline)" },
407 { "mac loopback test (offline)" },
408 { "phy loopback test (offline)" },
409 { "ext loopback test (offline)" },
410 { "interrupt test (offline)" },
413 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
416 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
418 writel(val, tp->regs + off);
421 static u32 tg3_read32(struct tg3 *tp, u32 off)
423 return readl(tp->regs + off);
426 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
428 writel(val, tp->aperegs + off);
431 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
433 return readl(tp->aperegs + off);
436 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
440 spin_lock_irqsave(&tp->indirect_lock, flags);
441 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
442 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
443 spin_unlock_irqrestore(&tp->indirect_lock, flags);
446 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
448 writel(val, tp->regs + off);
449 readl(tp->regs + off);
452 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
457 spin_lock_irqsave(&tp->indirect_lock, flags);
458 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
459 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
460 spin_unlock_irqrestore(&tp->indirect_lock, flags);
464 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
468 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
469 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
470 TG3_64BIT_REG_LOW, val);
473 if (off == TG3_RX_STD_PROD_IDX_REG) {
474 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
475 TG3_64BIT_REG_LOW, val);
479 spin_lock_irqsave(&tp->indirect_lock, flags);
480 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
481 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
482 spin_unlock_irqrestore(&tp->indirect_lock, flags);
484 /* In indirect mode when disabling interrupts, we also need
485 * to clear the interrupt bit in the GRC local ctrl register.
487 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
489 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
490 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
494 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
499 spin_lock_irqsave(&tp->indirect_lock, flags);
500 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
501 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
502 spin_unlock_irqrestore(&tp->indirect_lock, flags);
506 /* usec_wait specifies the wait time in usec when writing to certain registers
507 * where it is unsafe to read back the register without some delay.
508 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
509 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
511 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
513 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
514 /* Non-posted methods */
515 tp->write32(tp, off, val);
518 tg3_write32(tp, off, val);
523 /* Wait again after the read for the posted method to guarantee that
524 * the wait time is met.
530 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
532 tp->write32_mbox(tp, off, val);
533 if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
534 tp->read32_mbox(tp, off);
537 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
539 void __iomem *mbox = tp->regs + off;
541 if (tg3_flag(tp, TXD_MBOX_HWBUG))
543 if (tg3_flag(tp, MBOX_WRITE_REORDER))
547 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
549 return readl(tp->regs + off + GRCMBOX_BASE);
552 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
554 writel(val, tp->regs + off + GRCMBOX_BASE);
557 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
558 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
559 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
560 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
561 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
563 #define tw32(reg, val) tp->write32(tp, reg, val)
564 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
565 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
566 #define tr32(reg) tp->read32(tp, reg)
568 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
572 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
573 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
576 spin_lock_irqsave(&tp->indirect_lock, flags);
577 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
578 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
579 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
581 /* Always leave this as zero. */
582 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
584 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
585 tw32_f(TG3PCI_MEM_WIN_DATA, val);
587 /* Always leave this as zero. */
588 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
590 spin_unlock_irqrestore(&tp->indirect_lock, flags);
593 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
597 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
598 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
603 spin_lock_irqsave(&tp->indirect_lock, flags);
604 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
605 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
606 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
608 /* Always leave this as zero. */
609 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
611 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
612 *val = tr32(TG3PCI_MEM_WIN_DATA);
614 /* Always leave this as zero. */
615 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
617 spin_unlock_irqrestore(&tp->indirect_lock, flags);
620 static void tg3_ape_lock_init(struct tg3 *tp)
625 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
626 regbase = TG3_APE_LOCK_GRANT;
628 regbase = TG3_APE_PER_LOCK_GRANT;
630 /* Make sure the driver hasn't any stale locks. */
631 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
633 case TG3_APE_LOCK_PHY0:
634 case TG3_APE_LOCK_PHY1:
635 case TG3_APE_LOCK_PHY2:
636 case TG3_APE_LOCK_PHY3:
637 bit = APE_LOCK_GRANT_DRIVER;
641 bit = APE_LOCK_GRANT_DRIVER;
643 bit = 1 << tp->pci_fn;
645 tg3_ape_write32(tp, regbase + 4 * i, bit);
650 static int tg3_ape_lock(struct tg3 *tp, int locknum)
654 u32 status, req, gnt, bit;
656 if (!tg3_flag(tp, ENABLE_APE))
660 case TG3_APE_LOCK_GPIO:
661 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
663 case TG3_APE_LOCK_GRC:
664 case TG3_APE_LOCK_MEM:
666 bit = APE_LOCK_REQ_DRIVER;
668 bit = 1 << tp->pci_fn;
674 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
675 req = TG3_APE_LOCK_REQ;
676 gnt = TG3_APE_LOCK_GRANT;
678 req = TG3_APE_PER_LOCK_REQ;
679 gnt = TG3_APE_PER_LOCK_GRANT;
684 tg3_ape_write32(tp, req + off, bit);
686 /* Wait for up to 1 millisecond to acquire lock. */
687 for (i = 0; i < 100; i++) {
688 status = tg3_ape_read32(tp, gnt + off);
695 /* Revoke the lock request. */
696 tg3_ape_write32(tp, gnt + off, bit);
703 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
707 if (!tg3_flag(tp, ENABLE_APE))
711 case TG3_APE_LOCK_GPIO:
712 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
714 case TG3_APE_LOCK_GRC:
715 case TG3_APE_LOCK_MEM:
717 bit = APE_LOCK_GRANT_DRIVER;
719 bit = 1 << tp->pci_fn;
725 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
726 gnt = TG3_APE_LOCK_GRANT;
728 gnt = TG3_APE_PER_LOCK_GRANT;
730 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
733 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
738 /* NCSI does not support APE events */
739 if (tg3_flag(tp, APE_HAS_NCSI))
742 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
743 if (apedata != APE_SEG_SIG_MAGIC)
746 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
747 if (!(apedata & APE_FW_STATUS_READY))
750 /* Wait for up to 1 millisecond for APE to service previous event. */
751 for (i = 0; i < 10; i++) {
752 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
755 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
757 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
758 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
759 event | APE_EVENT_STATUS_EVENT_PENDING);
761 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
763 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
769 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
770 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
773 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
778 if (!tg3_flag(tp, ENABLE_APE))
782 case RESET_KIND_INIT:
783 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
784 APE_HOST_SEG_SIG_MAGIC);
785 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
786 APE_HOST_SEG_LEN_MAGIC);
787 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
788 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
789 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
790 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
791 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
792 APE_HOST_BEHAV_NO_PHYLOCK);
793 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
794 TG3_APE_HOST_DRVR_STATE_START);
796 event = APE_EVENT_STATUS_STATE_START;
798 case RESET_KIND_SHUTDOWN:
799 /* With the interface we are currently using,
800 * APE does not track driver state. Wiping
801 * out the HOST SEGMENT SIGNATURE forces
802 * the APE to assume OS absent status.
804 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
806 if (device_may_wakeup(&tp->pdev->dev) &&
807 tg3_flag(tp, WOL_ENABLE)) {
808 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
809 TG3_APE_HOST_WOL_SPEED_AUTO);
810 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
812 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
814 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
816 event = APE_EVENT_STATUS_STATE_UNLOAD;
818 case RESET_KIND_SUSPEND:
819 event = APE_EVENT_STATUS_STATE_SUSPEND;
825 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
827 tg3_ape_send_event(tp, event);
830 static void tg3_disable_ints(struct tg3 *tp)
834 tw32(TG3PCI_MISC_HOST_CTRL,
835 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
836 for (i = 0; i < tp->irq_max; i++)
837 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
840 static void tg3_enable_ints(struct tg3 *tp)
847 tw32(TG3PCI_MISC_HOST_CTRL,
848 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
850 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
851 for (i = 0; i < tp->irq_cnt; i++) {
852 struct tg3_napi *tnapi = &tp->napi[i];
854 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
855 if (tg3_flag(tp, 1SHOT_MSI))
856 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
858 tp->coal_now |= tnapi->coal_now;
861 /* Force an initial interrupt */
862 if (!tg3_flag(tp, TAGGED_STATUS) &&
863 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
864 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
866 tw32(HOSTCC_MODE, tp->coal_now);
868 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
871 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
873 struct tg3 *tp = tnapi->tp;
874 struct tg3_hw_status *sblk = tnapi->hw_status;
875 unsigned int work_exists = 0;
877 /* check for phy events */
878 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
879 if (sblk->status & SD_STATUS_LINK_CHG)
883 /* check for TX work to do */
884 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
887 /* check for RX work to do */
888 if (tnapi->rx_rcb_prod_idx &&
889 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
896 * similar to tg3_enable_ints, but it accurately determines whether there
897 * is new work pending and can return without flushing the PIO write
898 * which reenables interrupts
900 static void tg3_int_reenable(struct tg3_napi *tnapi)
902 struct tg3 *tp = tnapi->tp;
904 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
907 /* When doing tagged status, this work check is unnecessary.
908 * The last_tag we write above tells the chip which piece of
909 * work we've completed.
911 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
912 tw32(HOSTCC_MODE, tp->coalesce_mode |
913 HOSTCC_MODE_ENABLE | tnapi->coal_now);
916 static void tg3_switch_clocks(struct tg3 *tp)
921 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
924 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
926 orig_clock_ctrl = clock_ctrl;
927 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
928 CLOCK_CTRL_CLKRUN_OENABLE |
930 tp->pci_clock_ctrl = clock_ctrl;
932 if (tg3_flag(tp, 5705_PLUS)) {
933 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
934 tw32_wait_f(TG3PCI_CLOCK_CTRL,
935 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
937 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
938 tw32_wait_f(TG3PCI_CLOCK_CTRL,
940 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
942 tw32_wait_f(TG3PCI_CLOCK_CTRL,
943 clock_ctrl | (CLOCK_CTRL_ALTCLK),
946 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
949 #define PHY_BUSY_LOOPS 5000
951 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
957 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
959 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
965 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
966 MI_COM_PHY_ADDR_MASK);
967 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
968 MI_COM_REG_ADDR_MASK);
969 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
971 tw32_f(MAC_MI_COM, frame_val);
973 loops = PHY_BUSY_LOOPS;
976 frame_val = tr32(MAC_MI_COM);
978 if ((frame_val & MI_COM_BUSY) == 0) {
980 frame_val = tr32(MAC_MI_COM);
988 *val = frame_val & MI_COM_DATA_MASK;
992 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
993 tw32_f(MAC_MI_MODE, tp->mi_mode);
1000 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1006 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1007 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1010 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1012 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1016 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1017 MI_COM_PHY_ADDR_MASK);
1018 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1019 MI_COM_REG_ADDR_MASK);
1020 frame_val |= (val & MI_COM_DATA_MASK);
1021 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1023 tw32_f(MAC_MI_COM, frame_val);
1025 loops = PHY_BUSY_LOOPS;
1026 while (loops != 0) {
1028 frame_val = tr32(MAC_MI_COM);
1029 if ((frame_val & MI_COM_BUSY) == 0) {
1031 frame_val = tr32(MAC_MI_COM);
1041 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1042 tw32_f(MAC_MI_MODE, tp->mi_mode);
1049 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1053 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1057 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1061 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1062 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1066 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1072 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1076 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1080 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1084 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1085 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1089 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1095 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1099 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1101 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1106 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1110 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1112 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1117 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1121 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1122 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1123 MII_TG3_AUXCTL_SHDWSEL_MISC);
1125 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1130 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1132 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1133 set |= MII_TG3_AUXCTL_MISC_WREN;
1135 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1138 static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1143 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1149 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1151 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1153 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1154 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1159 static int tg3_bmcr_reset(struct tg3 *tp)
1164 /* OK, reset it, and poll the BMCR_RESET bit until it
1165 * clears or we time out.
1167 phy_control = BMCR_RESET;
1168 err = tg3_writephy(tp, MII_BMCR, phy_control);
1174 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1178 if ((phy_control & BMCR_RESET) == 0) {
1190 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1192 struct tg3 *tp = bp->priv;
1195 spin_lock_bh(&tp->lock);
1197 if (tg3_readphy(tp, reg, &val))
1200 spin_unlock_bh(&tp->lock);
1205 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1207 struct tg3 *tp = bp->priv;
1210 spin_lock_bh(&tp->lock);
1212 if (tg3_writephy(tp, reg, val))
1215 spin_unlock_bh(&tp->lock);
1220 static int tg3_mdio_reset(struct mii_bus *bp)
1225 static void tg3_mdio_config_5785(struct tg3 *tp)
1228 struct phy_device *phydev;
1230 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1231 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1232 case PHY_ID_BCM50610:
1233 case PHY_ID_BCM50610M:
1234 val = MAC_PHYCFG2_50610_LED_MODES;
1236 case PHY_ID_BCMAC131:
1237 val = MAC_PHYCFG2_AC131_LED_MODES;
1239 case PHY_ID_RTL8211C:
1240 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1242 case PHY_ID_RTL8201E:
1243 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1249 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1250 tw32(MAC_PHYCFG2, val);
1252 val = tr32(MAC_PHYCFG1);
1253 val &= ~(MAC_PHYCFG1_RGMII_INT |
1254 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1255 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1256 tw32(MAC_PHYCFG1, val);
1261 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1262 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1263 MAC_PHYCFG2_FMODE_MASK_MASK |
1264 MAC_PHYCFG2_GMODE_MASK_MASK |
1265 MAC_PHYCFG2_ACT_MASK_MASK |
1266 MAC_PHYCFG2_QUAL_MASK_MASK |
1267 MAC_PHYCFG2_INBAND_ENABLE;
1269 tw32(MAC_PHYCFG2, val);
1271 val = tr32(MAC_PHYCFG1);
1272 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1273 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1274 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1275 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1276 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1277 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1278 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1280 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1281 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1282 tw32(MAC_PHYCFG1, val);
1284 val = tr32(MAC_EXT_RGMII_MODE);
1285 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1286 MAC_RGMII_MODE_RX_QUALITY |
1287 MAC_RGMII_MODE_RX_ACTIVITY |
1288 MAC_RGMII_MODE_RX_ENG_DET |
1289 MAC_RGMII_MODE_TX_ENABLE |
1290 MAC_RGMII_MODE_TX_LOWPWR |
1291 MAC_RGMII_MODE_TX_RESET);
1292 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1293 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1294 val |= MAC_RGMII_MODE_RX_INT_B |
1295 MAC_RGMII_MODE_RX_QUALITY |
1296 MAC_RGMII_MODE_RX_ACTIVITY |
1297 MAC_RGMII_MODE_RX_ENG_DET;
1298 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1299 val |= MAC_RGMII_MODE_TX_ENABLE |
1300 MAC_RGMII_MODE_TX_LOWPWR |
1301 MAC_RGMII_MODE_TX_RESET;
1303 tw32(MAC_EXT_RGMII_MODE, val);
1306 static void tg3_mdio_start(struct tg3 *tp)
1308 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1309 tw32_f(MAC_MI_MODE, tp->mi_mode);
1312 if (tg3_flag(tp, MDIOBUS_INITED) &&
1313 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1314 tg3_mdio_config_5785(tp);
1317 static int tg3_mdio_init(struct tg3 *tp)
1321 struct phy_device *phydev;
1323 if (tg3_flag(tp, 5717_PLUS)) {
1326 tp->phy_addr = tp->pci_fn + 1;
1328 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1329 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1331 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1332 TG3_CPMU_PHY_STRAP_IS_SERDES;
1336 tp->phy_addr = TG3_PHY_MII_ADDR;
1340 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1343 tp->mdio_bus = mdiobus_alloc();
1344 if (tp->mdio_bus == NULL)
1347 tp->mdio_bus->name = "tg3 mdio bus";
1348 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1349 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1350 tp->mdio_bus->priv = tp;
1351 tp->mdio_bus->parent = &tp->pdev->dev;
1352 tp->mdio_bus->read = &tg3_mdio_read;
1353 tp->mdio_bus->write = &tg3_mdio_write;
1354 tp->mdio_bus->reset = &tg3_mdio_reset;
1355 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1356 tp->mdio_bus->irq = &tp->mdio_irq[0];
1358 for (i = 0; i < PHY_MAX_ADDR; i++)
1359 tp->mdio_bus->irq[i] = PHY_POLL;
1361 /* The bus registration will look for all the PHYs on the mdio bus.
1362 * Unfortunately, it does not ensure the PHY is powered up before
1363 * accessing the PHY ID registers. A chip reset is the
1364 * quickest way to bring the device back to an operational state..
1366 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1369 i = mdiobus_register(tp->mdio_bus);
1371 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1372 mdiobus_free(tp->mdio_bus);
1376 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1378 if (!phydev || !phydev->drv) {
1379 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1380 mdiobus_unregister(tp->mdio_bus);
1381 mdiobus_free(tp->mdio_bus);
1385 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1386 case PHY_ID_BCM57780:
1387 phydev->interface = PHY_INTERFACE_MODE_GMII;
1388 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1390 case PHY_ID_BCM50610:
1391 case PHY_ID_BCM50610M:
1392 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1393 PHY_BRCM_RX_REFCLK_UNUSED |
1394 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1395 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1396 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1397 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1398 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1399 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1400 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1401 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1403 case PHY_ID_RTL8211C:
1404 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1406 case PHY_ID_RTL8201E:
1407 case PHY_ID_BCMAC131:
1408 phydev->interface = PHY_INTERFACE_MODE_MII;
1409 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1410 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1414 tg3_flag_set(tp, MDIOBUS_INITED);
1416 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1417 tg3_mdio_config_5785(tp);
1422 static void tg3_mdio_fini(struct tg3 *tp)
1424 if (tg3_flag(tp, MDIOBUS_INITED)) {
1425 tg3_flag_clear(tp, MDIOBUS_INITED);
1426 mdiobus_unregister(tp->mdio_bus);
1427 mdiobus_free(tp->mdio_bus);
1431 /* tp->lock is held. */
1432 static inline void tg3_generate_fw_event(struct tg3 *tp)
1436 val = tr32(GRC_RX_CPU_EVENT);
1437 val |= GRC_RX_CPU_DRIVER_EVENT;
1438 tw32_f(GRC_RX_CPU_EVENT, val);
1440 tp->last_event_jiffies = jiffies;
1443 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1445 /* tp->lock is held. */
1446 static void tg3_wait_for_event_ack(struct tg3 *tp)
1449 unsigned int delay_cnt;
1452 /* If enough time has passed, no wait is necessary. */
1453 time_remain = (long)(tp->last_event_jiffies + 1 +
1454 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1456 if (time_remain < 0)
1459 /* Check if we can shorten the wait time. */
1460 delay_cnt = jiffies_to_usecs(time_remain);
1461 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1462 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1463 delay_cnt = (delay_cnt >> 3) + 1;
1465 for (i = 0; i < delay_cnt; i++) {
1466 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1472 /* tp->lock is held. */
1473 static void tg3_ump_link_report(struct tg3 *tp)
1478 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1481 tg3_wait_for_event_ack(tp);
1483 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1485 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1488 if (!tg3_readphy(tp, MII_BMCR, ®))
1490 if (!tg3_readphy(tp, MII_BMSR, ®))
1491 val |= (reg & 0xffff);
1492 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1495 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1497 if (!tg3_readphy(tp, MII_LPA, ®))
1498 val |= (reg & 0xffff);
1499 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1502 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1503 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1505 if (!tg3_readphy(tp, MII_STAT1000, ®))
1506 val |= (reg & 0xffff);
1508 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1510 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1514 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1516 tg3_generate_fw_event(tp);
1519 /* tp->lock is held. */
1520 static void tg3_stop_fw(struct tg3 *tp)
1522 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1523 /* Wait for RX cpu to ACK the previous event. */
1524 tg3_wait_for_event_ack(tp);
1526 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1528 tg3_generate_fw_event(tp);
1530 /* Wait for RX cpu to ACK this event. */
1531 tg3_wait_for_event_ack(tp);
1535 /* tp->lock is held. */
1536 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1538 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1539 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1541 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1543 case RESET_KIND_INIT:
1544 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1548 case RESET_KIND_SHUTDOWN:
1549 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1553 case RESET_KIND_SUSPEND:
1554 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1563 if (kind == RESET_KIND_INIT ||
1564 kind == RESET_KIND_SUSPEND)
1565 tg3_ape_driver_state_change(tp, kind);
1568 /* tp->lock is held. */
1569 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1571 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1573 case RESET_KIND_INIT:
1574 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1575 DRV_STATE_START_DONE);
1578 case RESET_KIND_SHUTDOWN:
1579 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1580 DRV_STATE_UNLOAD_DONE);
1588 if (kind == RESET_KIND_SHUTDOWN)
1589 tg3_ape_driver_state_change(tp, kind);
1592 /* tp->lock is held. */
1593 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1595 if (tg3_flag(tp, ENABLE_ASF)) {
1597 case RESET_KIND_INIT:
1598 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1602 case RESET_KIND_SHUTDOWN:
1603 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1607 case RESET_KIND_SUSPEND:
1608 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1618 static int tg3_poll_fw(struct tg3 *tp)
1623 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1624 /* Wait up to 20ms for init done. */
1625 for (i = 0; i < 200; i++) {
1626 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1633 /* Wait for firmware initialization to complete. */
1634 for (i = 0; i < 100000; i++) {
1635 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1636 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1641 /* Chip might not be fitted with firmware. Some Sun onboard
1642 * parts are configured like that. So don't signal the timeout
1643 * of the above loop as an error, but do report the lack of
1644 * running firmware once.
1646 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1647 tg3_flag_set(tp, NO_FWARE_REPORTED);
1649 netdev_info(tp->dev, "No firmware running\n");
1652 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
1653 /* The 57765 A0 needs a little more
1654 * time to do some important work.
1662 static void tg3_link_report(struct tg3 *tp)
1664 if (!netif_carrier_ok(tp->dev)) {
1665 netif_info(tp, link, tp->dev, "Link is down\n");
1666 tg3_ump_link_report(tp);
1667 } else if (netif_msg_link(tp)) {
1668 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1669 (tp->link_config.active_speed == SPEED_1000 ?
1671 (tp->link_config.active_speed == SPEED_100 ?
1673 (tp->link_config.active_duplex == DUPLEX_FULL ?
1676 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1677 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1679 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1682 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1683 netdev_info(tp->dev, "EEE is %s\n",
1684 tp->setlpicnt ? "enabled" : "disabled");
1686 tg3_ump_link_report(tp);
1690 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1694 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1695 miireg = ADVERTISE_PAUSE_CAP;
1696 else if (flow_ctrl & FLOW_CTRL_TX)
1697 miireg = ADVERTISE_PAUSE_ASYM;
1698 else if (flow_ctrl & FLOW_CTRL_RX)
1699 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1706 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1710 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1711 miireg = ADVERTISE_1000XPAUSE;
1712 else if (flow_ctrl & FLOW_CTRL_TX)
1713 miireg = ADVERTISE_1000XPSE_ASYM;
1714 else if (flow_ctrl & FLOW_CTRL_RX)
1715 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1722 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1726 if (lcladv & ADVERTISE_1000XPAUSE) {
1727 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1728 if (rmtadv & LPA_1000XPAUSE)
1729 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1730 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1733 if (rmtadv & LPA_1000XPAUSE)
1734 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1736 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1737 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1744 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1748 u32 old_rx_mode = tp->rx_mode;
1749 u32 old_tx_mode = tp->tx_mode;
1751 if (tg3_flag(tp, USE_PHYLIB))
1752 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1754 autoneg = tp->link_config.autoneg;
1756 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1757 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1758 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1760 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1762 flowctrl = tp->link_config.flowctrl;
1764 tp->link_config.active_flowctrl = flowctrl;
1766 if (flowctrl & FLOW_CTRL_RX)
1767 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1769 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1771 if (old_rx_mode != tp->rx_mode)
1772 tw32_f(MAC_RX_MODE, tp->rx_mode);
1774 if (flowctrl & FLOW_CTRL_TX)
1775 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1777 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1779 if (old_tx_mode != tp->tx_mode)
1780 tw32_f(MAC_TX_MODE, tp->tx_mode);
1783 static void tg3_adjust_link(struct net_device *dev)
1785 u8 oldflowctrl, linkmesg = 0;
1786 u32 mac_mode, lcl_adv, rmt_adv;
1787 struct tg3 *tp = netdev_priv(dev);
1788 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1790 spin_lock_bh(&tp->lock);
1792 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1793 MAC_MODE_HALF_DUPLEX);
1795 oldflowctrl = tp->link_config.active_flowctrl;
1801 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1802 mac_mode |= MAC_MODE_PORT_MODE_MII;
1803 else if (phydev->speed == SPEED_1000 ||
1804 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1805 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1807 mac_mode |= MAC_MODE_PORT_MODE_MII;
1809 if (phydev->duplex == DUPLEX_HALF)
1810 mac_mode |= MAC_MODE_HALF_DUPLEX;
1812 lcl_adv = tg3_advert_flowctrl_1000T(
1813 tp->link_config.flowctrl);
1816 rmt_adv = LPA_PAUSE_CAP;
1817 if (phydev->asym_pause)
1818 rmt_adv |= LPA_PAUSE_ASYM;
1821 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1823 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1825 if (mac_mode != tp->mac_mode) {
1826 tp->mac_mode = mac_mode;
1827 tw32_f(MAC_MODE, tp->mac_mode);
1831 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1832 if (phydev->speed == SPEED_10)
1834 MAC_MI_STAT_10MBPS_MODE |
1835 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1837 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1840 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1841 tw32(MAC_TX_LENGTHS,
1842 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1843 (6 << TX_LENGTHS_IPG_SHIFT) |
1844 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1846 tw32(MAC_TX_LENGTHS,
1847 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1848 (6 << TX_LENGTHS_IPG_SHIFT) |
1849 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1851 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1852 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1853 phydev->speed != tp->link_config.active_speed ||
1854 phydev->duplex != tp->link_config.active_duplex ||
1855 oldflowctrl != tp->link_config.active_flowctrl)
1858 tp->link_config.active_speed = phydev->speed;
1859 tp->link_config.active_duplex = phydev->duplex;
1861 spin_unlock_bh(&tp->lock);
1864 tg3_link_report(tp);
1867 static int tg3_phy_init(struct tg3 *tp)
1869 struct phy_device *phydev;
1871 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1874 /* Bring the PHY back to a known state. */
1877 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1879 /* Attach the MAC to the PHY. */
1880 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1881 phydev->dev_flags, phydev->interface);
1882 if (IS_ERR(phydev)) {
1883 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1884 return PTR_ERR(phydev);
1887 /* Mask with MAC supported features. */
1888 switch (phydev->interface) {
1889 case PHY_INTERFACE_MODE_GMII:
1890 case PHY_INTERFACE_MODE_RGMII:
1891 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1892 phydev->supported &= (PHY_GBIT_FEATURES |
1894 SUPPORTED_Asym_Pause);
1898 case PHY_INTERFACE_MODE_MII:
1899 phydev->supported &= (PHY_BASIC_FEATURES |
1901 SUPPORTED_Asym_Pause);
1904 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1908 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1910 phydev->advertising = phydev->supported;
1915 static void tg3_phy_start(struct tg3 *tp)
1917 struct phy_device *phydev;
1919 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1922 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1924 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1925 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1926 phydev->speed = tp->link_config.orig_speed;
1927 phydev->duplex = tp->link_config.orig_duplex;
1928 phydev->autoneg = tp->link_config.orig_autoneg;
1929 phydev->advertising = tp->link_config.orig_advertising;
1934 phy_start_aneg(phydev);
1937 static void tg3_phy_stop(struct tg3 *tp)
1939 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1942 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1945 static void tg3_phy_fini(struct tg3 *tp)
1947 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1948 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1949 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1953 static int tg3_phy_set_extloopbk(struct tg3 *tp)
1958 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
1961 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1962 /* Cannot do read-modify-write on 5401 */
1963 err = tg3_phy_auxctl_write(tp,
1964 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1965 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
1970 err = tg3_phy_auxctl_read(tp,
1971 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1975 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
1976 err = tg3_phy_auxctl_write(tp,
1977 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
1983 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1987 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1990 tg3_writephy(tp, MII_TG3_FET_TEST,
1991 phytest | MII_TG3_FET_SHADOW_EN);
1992 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1994 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1996 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1997 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1999 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2003 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2007 if (!tg3_flag(tp, 5705_PLUS) ||
2008 (tg3_flag(tp, 5717_PLUS) &&
2009 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2012 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2013 tg3_phy_fet_toggle_apd(tp, enable);
2017 reg = MII_TG3_MISC_SHDW_WREN |
2018 MII_TG3_MISC_SHDW_SCR5_SEL |
2019 MII_TG3_MISC_SHDW_SCR5_LPED |
2020 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2021 MII_TG3_MISC_SHDW_SCR5_SDTL |
2022 MII_TG3_MISC_SHDW_SCR5_C125OE;
2023 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
2024 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2026 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2029 reg = MII_TG3_MISC_SHDW_WREN |
2030 MII_TG3_MISC_SHDW_APD_SEL |
2031 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2033 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2035 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2038 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
2042 if (!tg3_flag(tp, 5705_PLUS) ||
2043 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2046 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2049 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2050 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2052 tg3_writephy(tp, MII_TG3_FET_TEST,
2053 ephy | MII_TG3_FET_SHADOW_EN);
2054 if (!tg3_readphy(tp, reg, &phy)) {
2056 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2058 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2059 tg3_writephy(tp, reg, phy);
2061 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2066 ret = tg3_phy_auxctl_read(tp,
2067 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2070 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2072 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2073 tg3_phy_auxctl_write(tp,
2074 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2079 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2084 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2087 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2089 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2090 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2093 static void tg3_phy_apply_otp(struct tg3 *tp)
2102 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
2105 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2106 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2107 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2109 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2110 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2111 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2113 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2114 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2115 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2117 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2118 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2120 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2121 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2123 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2124 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2125 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2127 tg3_phy_toggle_auxctl_smdsp(tp, false);
2130 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
2134 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2139 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2140 current_link_up == 1 &&
2141 tp->link_config.active_duplex == DUPLEX_FULL &&
2142 (tp->link_config.active_speed == SPEED_100 ||
2143 tp->link_config.active_speed == SPEED_1000)) {
2146 if (tp->link_config.active_speed == SPEED_1000)
2147 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2149 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2151 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2153 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
2154 TG3_CL45_D7_EEERES_STAT, &val);
2156 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2157 val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
2161 if (!tp->setlpicnt) {
2162 if (current_link_up == 1 &&
2163 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2164 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2165 tg3_phy_toggle_auxctl_smdsp(tp, false);
2168 val = tr32(TG3_CPMU_EEE_MODE);
2169 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2173 static void tg3_phy_eee_enable(struct tg3 *tp)
2177 if (tp->link_config.active_speed == SPEED_1000 &&
2178 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2179 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2180 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
2181 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2182 val = MII_TG3_DSP_TAP26_ALNOKO |
2183 MII_TG3_DSP_TAP26_RMRXSTO;
2184 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2185 tg3_phy_toggle_auxctl_smdsp(tp, false);
2188 val = tr32(TG3_CPMU_EEE_MODE);
2189 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2192 static int tg3_wait_macro_done(struct tg3 *tp)
2199 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2200 if ((tmp32 & 0x1000) == 0)
2210 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2212 static const u32 test_pat[4][6] = {
2213 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2214 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2215 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2216 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2220 for (chan = 0; chan < 4; chan++) {
2223 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2224 (chan * 0x2000) | 0x0200);
2225 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2227 for (i = 0; i < 6; i++)
2228 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2231 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2232 if (tg3_wait_macro_done(tp)) {
2237 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2238 (chan * 0x2000) | 0x0200);
2239 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2240 if (tg3_wait_macro_done(tp)) {
2245 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2246 if (tg3_wait_macro_done(tp)) {
2251 for (i = 0; i < 6; i += 2) {
2254 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2255 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2256 tg3_wait_macro_done(tp)) {
2262 if (low != test_pat[chan][i] ||
2263 high != test_pat[chan][i+1]) {
2264 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2265 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2266 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2276 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2280 for (chan = 0; chan < 4; chan++) {
2283 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2284 (chan * 0x2000) | 0x0200);
2285 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2286 for (i = 0; i < 6; i++)
2287 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2288 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2289 if (tg3_wait_macro_done(tp))
2296 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2298 u32 reg32, phy9_orig;
2299 int retries, do_phy_reset, err;
2305 err = tg3_bmcr_reset(tp);
2311 /* Disable transmitter and interrupt. */
2312 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
2316 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2318 /* Set full-duplex, 1000 mbps. */
2319 tg3_writephy(tp, MII_BMCR,
2320 BMCR_FULLDPLX | BMCR_SPEED1000);
2322 /* Set to master mode. */
2323 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2326 tg3_writephy(tp, MII_CTRL1000,
2327 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2329 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
2333 /* Block the PHY control access. */
2334 tg3_phydsp_write(tp, 0x8005, 0x0800);
2336 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2339 } while (--retries);
2341 err = tg3_phy_reset_chanpat(tp);
2345 tg3_phydsp_write(tp, 0x8005, 0x0000);
2347 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2348 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2350 tg3_phy_toggle_auxctl_smdsp(tp, false);
2352 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2354 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
2356 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2363 /* This will reset the tigon3 PHY if there is no valid
2364 * link unless the FORCE argument is non-zero.
2366 static int tg3_phy_reset(struct tg3 *tp)
2371 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2372 val = tr32(GRC_MISC_CFG);
2373 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2376 err = tg3_readphy(tp, MII_BMSR, &val);
2377 err |= tg3_readphy(tp, MII_BMSR, &val);
2381 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2382 netif_carrier_off(tp->dev);
2383 tg3_link_report(tp);
2386 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2387 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2388 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2389 err = tg3_phy_reset_5703_4_5(tp);
2396 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2397 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2398 cpmuctrl = tr32(TG3_CPMU_CTRL);
2399 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2401 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2404 err = tg3_bmcr_reset(tp);
2408 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2409 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2410 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2412 tw32(TG3_CPMU_CTRL, cpmuctrl);
2415 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2416 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2417 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2418 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2419 CPMU_LSPD_1000MB_MACCLK_12_5) {
2420 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2422 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2426 if (tg3_flag(tp, 5717_PLUS) &&
2427 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2430 tg3_phy_apply_otp(tp);
2432 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2433 tg3_phy_toggle_apd(tp, true);
2435 tg3_phy_toggle_apd(tp, false);
2438 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2439 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2440 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2441 tg3_phydsp_write(tp, 0x000a, 0x0323);
2442 tg3_phy_toggle_auxctl_smdsp(tp, false);
2445 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2446 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2447 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2450 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2451 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2452 tg3_phydsp_write(tp, 0x000a, 0x310b);
2453 tg3_phydsp_write(tp, 0x201f, 0x9506);
2454 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2455 tg3_phy_toggle_auxctl_smdsp(tp, false);
2457 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2458 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2459 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2460 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2461 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2462 tg3_writephy(tp, MII_TG3_TEST1,
2463 MII_TG3_TEST1_TRIM_EN | 0x4);
2465 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2467 tg3_phy_toggle_auxctl_smdsp(tp, false);
2471 /* Set Extended packet length bit (bit 14) on all chips that */
2472 /* support jumbo frames */
2473 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2474 /* Cannot do read-modify-write on 5401 */
2475 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2476 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2477 /* Set bit 14 with read-modify-write to preserve other bits */
2478 err = tg3_phy_auxctl_read(tp,
2479 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2481 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2482 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2485 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2486 * jumbo frames transmission.
2488 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2489 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2490 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2491 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2494 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2495 /* adjust output voltage */
2496 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2499 tg3_phy_toggle_automdix(tp, 1);
2500 tg3_phy_set_wirespeed(tp);
2504 #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2505 #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2506 #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2507 TG3_GPIO_MSG_NEED_VAUX)
2508 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2509 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2510 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2511 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2512 (TG3_GPIO_MSG_DRVR_PRES << 12))
2514 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2515 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2516 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2517 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2518 (TG3_GPIO_MSG_NEED_VAUX << 12))
2520 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2524 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2525 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2526 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2528 status = tr32(TG3_CPMU_DRV_STATUS);
2530 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2531 status &= ~(TG3_GPIO_MSG_MASK << shift);
2532 status |= (newstat << shift);
2534 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2535 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2536 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2538 tw32(TG3_CPMU_DRV_STATUS, status);
2540 return status >> TG3_APE_GPIO_MSG_SHIFT;
2543 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2545 if (!tg3_flag(tp, IS_NIC))
2548 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2549 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2550 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2551 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2554 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2556 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2557 TG3_GRC_LCLCTL_PWRSW_DELAY);
2559 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2561 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2562 TG3_GRC_LCLCTL_PWRSW_DELAY);
2568 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2572 if (!tg3_flag(tp, IS_NIC) ||
2573 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2574 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)
2577 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2579 tw32_wait_f(GRC_LOCAL_CTRL,
2580 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2581 TG3_GRC_LCLCTL_PWRSW_DELAY);
2583 tw32_wait_f(GRC_LOCAL_CTRL,
2585 TG3_GRC_LCLCTL_PWRSW_DELAY);
2587 tw32_wait_f(GRC_LOCAL_CTRL,
2588 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2589 TG3_GRC_LCLCTL_PWRSW_DELAY);
2592 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2594 if (!tg3_flag(tp, IS_NIC))
2597 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2598 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2599 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2600 (GRC_LCLCTRL_GPIO_OE0 |
2601 GRC_LCLCTRL_GPIO_OE1 |
2602 GRC_LCLCTRL_GPIO_OE2 |
2603 GRC_LCLCTRL_GPIO_OUTPUT0 |
2604 GRC_LCLCTRL_GPIO_OUTPUT1),
2605 TG3_GRC_LCLCTL_PWRSW_DELAY);
2606 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2607 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2608 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2609 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2610 GRC_LCLCTRL_GPIO_OE1 |
2611 GRC_LCLCTRL_GPIO_OE2 |
2612 GRC_LCLCTRL_GPIO_OUTPUT0 |
2613 GRC_LCLCTRL_GPIO_OUTPUT1 |
2615 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2616 TG3_GRC_LCLCTL_PWRSW_DELAY);
2618 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2619 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2620 TG3_GRC_LCLCTL_PWRSW_DELAY);
2622 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2623 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2624 TG3_GRC_LCLCTL_PWRSW_DELAY);
2627 u32 grc_local_ctrl = 0;
2629 /* Workaround to prevent overdrawing Amps. */
2630 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2631 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2632 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2634 TG3_GRC_LCLCTL_PWRSW_DELAY);
2637 /* On 5753 and variants, GPIO2 cannot be used. */
2638 no_gpio2 = tp->nic_sram_data_cfg &
2639 NIC_SRAM_DATA_CFG_NO_GPIO2;
2641 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2642 GRC_LCLCTRL_GPIO_OE1 |
2643 GRC_LCLCTRL_GPIO_OE2 |
2644 GRC_LCLCTRL_GPIO_OUTPUT1 |
2645 GRC_LCLCTRL_GPIO_OUTPUT2;
2647 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2648 GRC_LCLCTRL_GPIO_OUTPUT2);
2650 tw32_wait_f(GRC_LOCAL_CTRL,
2651 tp->grc_local_ctrl | grc_local_ctrl,
2652 TG3_GRC_LCLCTL_PWRSW_DELAY);
2654 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2656 tw32_wait_f(GRC_LOCAL_CTRL,
2657 tp->grc_local_ctrl | grc_local_ctrl,
2658 TG3_GRC_LCLCTL_PWRSW_DELAY);
2661 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2662 tw32_wait_f(GRC_LOCAL_CTRL,
2663 tp->grc_local_ctrl | grc_local_ctrl,
2664 TG3_GRC_LCLCTL_PWRSW_DELAY);
2669 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2673 /* Serialize power state transitions */
2674 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2677 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2678 msg = TG3_GPIO_MSG_NEED_VAUX;
2680 msg = tg3_set_function_status(tp, msg);
2682 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2685 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2686 tg3_pwrsrc_switch_to_vaux(tp);
2688 tg3_pwrsrc_die_with_vmain(tp);
2691 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2694 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2696 bool need_vaux = false;
2698 /* The GPIOs do something completely different on 57765. */
2699 if (!tg3_flag(tp, IS_NIC) ||
2700 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2703 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2704 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2705 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2706 tg3_frob_aux_power_5717(tp, include_wol ?
2707 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2711 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2712 struct net_device *dev_peer;
2714 dev_peer = pci_get_drvdata(tp->pdev_peer);
2716 /* remove_one() may have been run on the peer. */
2718 struct tg3 *tp_peer = netdev_priv(dev_peer);
2720 if (tg3_flag(tp_peer, INIT_COMPLETE))
2723 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2724 tg3_flag(tp_peer, ENABLE_ASF))
2729 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2730 tg3_flag(tp, ENABLE_ASF))
2734 tg3_pwrsrc_switch_to_vaux(tp);
2736 tg3_pwrsrc_die_with_vmain(tp);
2739 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2741 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2743 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2744 if (speed != SPEED_10)
2746 } else if (speed == SPEED_10)
2752 static int tg3_setup_phy(struct tg3 *, int);
2753 static int tg3_halt_cpu(struct tg3 *, u32);
2755 static bool tg3_phy_power_bug(struct tg3 *tp)
2757 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
2762 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2771 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
2780 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2784 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2785 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2786 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2787 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2790 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2791 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2792 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2797 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2799 val = tr32(GRC_MISC_CFG);
2800 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2803 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2805 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2808 tg3_writephy(tp, MII_ADVERTISE, 0);
2809 tg3_writephy(tp, MII_BMCR,
2810 BMCR_ANENABLE | BMCR_ANRESTART);
2812 tg3_writephy(tp, MII_TG3_FET_TEST,
2813 phytest | MII_TG3_FET_SHADOW_EN);
2814 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2815 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2817 MII_TG3_FET_SHDW_AUXMODE4,
2820 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2823 } else if (do_low_power) {
2824 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2825 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2827 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2828 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2829 MII_TG3_AUXCTL_PCTL_VREG_11V;
2830 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
2833 /* The PHY should not be powered down on some chips because
2836 if (tg3_phy_power_bug(tp))
2839 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2840 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2841 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2842 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2843 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2844 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2847 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2850 /* tp->lock is held. */
2851 static int tg3_nvram_lock(struct tg3 *tp)
2853 if (tg3_flag(tp, NVRAM)) {
2856 if (tp->nvram_lock_cnt == 0) {
2857 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2858 for (i = 0; i < 8000; i++) {
2859 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2864 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2868 tp->nvram_lock_cnt++;
2873 /* tp->lock is held. */
2874 static void tg3_nvram_unlock(struct tg3 *tp)
2876 if (tg3_flag(tp, NVRAM)) {
2877 if (tp->nvram_lock_cnt > 0)
2878 tp->nvram_lock_cnt--;
2879 if (tp->nvram_lock_cnt == 0)
2880 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2884 /* tp->lock is held. */
2885 static void tg3_enable_nvram_access(struct tg3 *tp)
2887 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2888 u32 nvaccess = tr32(NVRAM_ACCESS);
2890 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2894 /* tp->lock is held. */
2895 static void tg3_disable_nvram_access(struct tg3 *tp)
2897 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2898 u32 nvaccess = tr32(NVRAM_ACCESS);
2900 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2904 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2905 u32 offset, u32 *val)
2910 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2913 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2914 EEPROM_ADDR_DEVID_MASK |
2916 tw32(GRC_EEPROM_ADDR,
2918 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2919 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2920 EEPROM_ADDR_ADDR_MASK) |
2921 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2923 for (i = 0; i < 1000; i++) {
2924 tmp = tr32(GRC_EEPROM_ADDR);
2926 if (tmp & EEPROM_ADDR_COMPLETE)
2930 if (!(tmp & EEPROM_ADDR_COMPLETE))
2933 tmp = tr32(GRC_EEPROM_DATA);
2936 * The data will always be opposite the native endian
2937 * format. Perform a blind byteswap to compensate.
2944 #define NVRAM_CMD_TIMEOUT 10000
2946 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2950 tw32(NVRAM_CMD, nvram_cmd);
2951 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2953 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2959 if (i == NVRAM_CMD_TIMEOUT)
2965 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2967 if (tg3_flag(tp, NVRAM) &&
2968 tg3_flag(tp, NVRAM_BUFFERED) &&
2969 tg3_flag(tp, FLASH) &&
2970 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
2971 (tp->nvram_jedecnum == JEDEC_ATMEL))
2973 addr = ((addr / tp->nvram_pagesize) <<
2974 ATMEL_AT45DB0X1B_PAGE_POS) +
2975 (addr % tp->nvram_pagesize);
2980 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2982 if (tg3_flag(tp, NVRAM) &&
2983 tg3_flag(tp, NVRAM_BUFFERED) &&
2984 tg3_flag(tp, FLASH) &&
2985 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
2986 (tp->nvram_jedecnum == JEDEC_ATMEL))
2988 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2989 tp->nvram_pagesize) +
2990 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2995 /* NOTE: Data read in from NVRAM is byteswapped according to
2996 * the byteswapping settings for all other register accesses.
2997 * tg3 devices are BE devices, so on a BE machine, the data
2998 * returned will be exactly as it is seen in NVRAM. On a LE
2999 * machine, the 32-bit value will be byteswapped.
3001 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3005 if (!tg3_flag(tp, NVRAM))
3006 return tg3_nvram_read_using_eeprom(tp, offset, val);
3008 offset = tg3_nvram_phys_addr(tp, offset);
3010 if (offset > NVRAM_ADDR_MSK)
3013 ret = tg3_nvram_lock(tp);
3017 tg3_enable_nvram_access(tp);
3019 tw32(NVRAM_ADDR, offset);
3020 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3021 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3024 *val = tr32(NVRAM_RDDATA);
3026 tg3_disable_nvram_access(tp);
3028 tg3_nvram_unlock(tp);
3033 /* Ensures NVRAM data is in bytestream format. */
3034 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
3037 int res = tg3_nvram_read(tp, offset, &v);
3039 *val = cpu_to_be32(v);
3043 #define RX_CPU_SCRATCH_BASE 0x30000
3044 #define RX_CPU_SCRATCH_SIZE 0x04000
3045 #define TX_CPU_SCRATCH_BASE 0x34000
3046 #define TX_CPU_SCRATCH_SIZE 0x04000
3048 /* tp->lock is held. */
3049 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
3053 BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3055 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3056 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3058 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3061 if (offset == RX_CPU_BASE) {
3062 for (i = 0; i < 10000; i++) {
3063 tw32(offset + CPU_STATE, 0xffffffff);
3064 tw32(offset + CPU_MODE, CPU_MODE_HALT);
3065 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3069 tw32(offset + CPU_STATE, 0xffffffff);
3070 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
3073 for (i = 0; i < 10000; i++) {
3074 tw32(offset + CPU_STATE, 0xffffffff);
3075 tw32(offset + CPU_MODE, CPU_MODE_HALT);
3076 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3082 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3083 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
3087 /* Clear firmware's nvram arbitration. */
3088 if (tg3_flag(tp, NVRAM))
3089 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3094 unsigned int fw_base;
3095 unsigned int fw_len;
3096 const __be32 *fw_data;
3099 /* tp->lock is held. */
3100 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3101 u32 cpu_scratch_base, int cpu_scratch_size,
3102 struct fw_info *info)
3104 int err, lock_err, i;
3105 void (*write_op)(struct tg3 *, u32, u32);
3107 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3109 "%s: Trying to load TX cpu firmware which is 5705\n",
3114 if (tg3_flag(tp, 5705_PLUS))
3115 write_op = tg3_write_mem;
3117 write_op = tg3_write_indirect_reg32;
3119 /* It is possible that bootcode is still loading at this point.
3120 * Get the nvram lock first before halting the cpu.
3122 lock_err = tg3_nvram_lock(tp);
3123 err = tg3_halt_cpu(tp, cpu_base);
3125 tg3_nvram_unlock(tp);
3129 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3130 write_op(tp, cpu_scratch_base + i, 0);
3131 tw32(cpu_base + CPU_STATE, 0xffffffff);
3132 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
3133 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
3134 write_op(tp, (cpu_scratch_base +
3135 (info->fw_base & 0xffff) +
3137 be32_to_cpu(info->fw_data[i]));
3145 /* tp->lock is held. */
3146 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3148 struct fw_info info;
3149 const __be32 *fw_data;
3152 fw_data = (void *)tp->fw->data;
3154 /* Firmware blob starts with version numbers, followed by
3155 start address and length. We are setting complete length.
3156 length = end_address_of_bss - start_address_of_text.
3157 Remainder is the blob to be loaded contiguously
3158 from start address. */
3160 info.fw_base = be32_to_cpu(fw_data[1]);
3161 info.fw_len = tp->fw->size - 12;
3162 info.fw_data = &fw_data[3];
3164 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3165 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3170 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3171 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3176 /* Now startup only the RX cpu. */
3177 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3178 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3180 for (i = 0; i < 5; i++) {
3181 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
3183 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3184 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3185 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3189 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3190 "should be %08x\n", __func__,
3191 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
3194 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3195 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
3200 /* tp->lock is held. */
3201 static int tg3_load_tso_firmware(struct tg3 *tp)
3203 struct fw_info info;
3204 const __be32 *fw_data;
3205 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3208 if (tg3_flag(tp, HW_TSO_1) ||
3209 tg3_flag(tp, HW_TSO_2) ||
3210 tg3_flag(tp, HW_TSO_3))
3213 fw_data = (void *)tp->fw->data;
3215 /* Firmware blob starts with version numbers, followed by
3216 start address and length. We are setting complete length.
3217 length = end_address_of_bss - start_address_of_text.
3218 Remainder is the blob to be loaded contiguously
3219 from start address. */
3221 info.fw_base = be32_to_cpu(fw_data[1]);
3222 cpu_scratch_size = tp->fw_len;
3223 info.fw_len = tp->fw->size - 12;
3224 info.fw_data = &fw_data[3];
3226 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
3227 cpu_base = RX_CPU_BASE;
3228 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3230 cpu_base = TX_CPU_BASE;
3231 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3232 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3235 err = tg3_load_firmware_cpu(tp, cpu_base,
3236 cpu_scratch_base, cpu_scratch_size,
3241 /* Now startup the cpu. */
3242 tw32(cpu_base + CPU_STATE, 0xffffffff);
3243 tw32_f(cpu_base + CPU_PC, info.fw_base);
3245 for (i = 0; i < 5; i++) {
3246 if (tr32(cpu_base + CPU_PC) == info.fw_base)
3248 tw32(cpu_base + CPU_STATE, 0xffffffff);
3249 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3250 tw32_f(cpu_base + CPU_PC, info.fw_base);
3255 "%s fails to set CPU PC, is %08x should be %08x\n",
3256 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
3259 tw32(cpu_base + CPU_STATE, 0xffffffff);
3260 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3265 /* tp->lock is held. */
3266 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
3268 u32 addr_high, addr_low;
3271 addr_high = ((tp->dev->dev_addr[0] << 8) |
3272 tp->dev->dev_addr[1]);
3273 addr_low = ((tp->dev->dev_addr[2] << 24) |
3274 (tp->dev->dev_addr[3] << 16) |
3275 (tp->dev->dev_addr[4] << 8) |
3276 (tp->dev->dev_addr[5] << 0));
3277 for (i = 0; i < 4; i++) {
3278 if (i == 1 && skip_mac_1)
3280 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
3281 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
3284 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3285 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
3286 for (i = 0; i < 12; i++) {
3287 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
3288 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
3292 addr_high = (tp->dev->dev_addr[0] +
3293 tp->dev->dev_addr[1] +
3294 tp->dev->dev_addr[2] +
3295 tp->dev->dev_addr[3] +
3296 tp->dev->dev_addr[4] +
3297 tp->dev->dev_addr[5]) &
3298 TX_BACKOFF_SEED_MASK;
3299 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3302 static void tg3_enable_register_access(struct tg3 *tp)
3305 * Make sure register accesses (indirect or otherwise) will function
3308 pci_write_config_dword(tp->pdev,
3309 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
3312 static int tg3_power_up(struct tg3 *tp)
3316 tg3_enable_register_access(tp);
3318 err = pci_set_power_state(tp->pdev, PCI_D0);
3320 /* Switch out of Vaux if it is a NIC */
3321 tg3_pwrsrc_switch_to_vmain(tp);
3323 netdev_err(tp->dev, "Transition to D0 failed\n");
3329 static int tg3_power_down_prepare(struct tg3 *tp)
3332 bool device_should_wake, do_low_power;
3334 tg3_enable_register_access(tp);
3336 /* Restore the CLKREQ setting. */
3337 if (tg3_flag(tp, CLKREQ_BUG)) {
3340 pci_read_config_word(tp->pdev,
3341 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
3343 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3344 pci_write_config_word(tp->pdev,
3345 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
3349 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
3350 tw32(TG3PCI_MISC_HOST_CTRL,
3351 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
3353 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
3354 tg3_flag(tp, WOL_ENABLE);
3356 if (tg3_flag(tp, USE_PHYLIB)) {
3357 do_low_power = false;
3358 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
3359 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3360 struct phy_device *phydev;
3361 u32 phyid, advertising;
3363 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
3365 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
3367 tp->link_config.orig_speed = phydev->speed;
3368 tp->link_config.orig_duplex = phydev->duplex;
3369 tp->link_config.orig_autoneg = phydev->autoneg;
3370 tp->link_config.orig_advertising = phydev->advertising;
3372 advertising = ADVERTISED_TP |
3374 ADVERTISED_Autoneg |
3375 ADVERTISED_10baseT_Half;
3377 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
3378 if (tg3_flag(tp, WOL_SPEED_100MB))
3380 ADVERTISED_100baseT_Half |
3381 ADVERTISED_100baseT_Full |
3382 ADVERTISED_10baseT_Full;
3384 advertising |= ADVERTISED_10baseT_Full;
3387 phydev->advertising = advertising;
3389 phy_start_aneg(phydev);
3391 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
3392 if (phyid != PHY_ID_BCMAC131) {
3393 phyid &= PHY_BCM_OUI_MASK;
3394 if (phyid == PHY_BCM_OUI_1 ||
3395 phyid == PHY_BCM_OUI_2 ||
3396 phyid == PHY_BCM_OUI_3)
3397 do_low_power = true;
3401 do_low_power = true;
3403 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3404 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
3405 tp->link_config.orig_speed = tp->link_config.speed;
3406 tp->link_config.orig_duplex = tp->link_config.duplex;
3407 tp->link_config.orig_autoneg = tp->link_config.autoneg;
3410 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
3411 tp->link_config.speed = SPEED_10;
3412 tp->link_config.duplex = DUPLEX_HALF;
3413 tp->link_config.autoneg = AUTONEG_ENABLE;
3414 tg3_setup_phy(tp, 0);
3418 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3421 val = tr32(GRC_VCPU_EXT_CTRL);
3422 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
3423 } else if (!tg3_flag(tp, ENABLE_ASF)) {
3427 for (i = 0; i < 200; i++) {
3428 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
3429 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
3434 if (tg3_flag(tp, WOL_CAP))
3435 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
3436 WOL_DRV_STATE_SHUTDOWN |
3440 if (device_should_wake) {
3443 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
3445 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
3446 tg3_phy_auxctl_write(tp,
3447 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
3448 MII_TG3_AUXCTL_PCTL_WOL_EN |
3449 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3450 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
3454 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3455 mac_mode = MAC_MODE_PORT_MODE_GMII;
3457 mac_mode = MAC_MODE_PORT_MODE_MII;
3459 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
3460 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3462 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
3463 SPEED_100 : SPEED_10;
3464 if (tg3_5700_link_polarity(tp, speed))
3465 mac_mode |= MAC_MODE_LINK_POLARITY;
3467 mac_mode &= ~MAC_MODE_LINK_POLARITY;
3470 mac_mode = MAC_MODE_PORT_MODE_TBI;
3473 if (!tg3_flag(tp, 5750_PLUS))
3474 tw32(MAC_LED_CTRL, tp->led_ctrl);
3476 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
3477 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
3478 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
3479 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
3481 if (tg3_flag(tp, ENABLE_APE))
3482 mac_mode |= MAC_MODE_APE_TX_EN |
3483 MAC_MODE_APE_RX_EN |
3484 MAC_MODE_TDE_ENABLE;
3486 tw32_f(MAC_MODE, mac_mode);
3489 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
3493 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
3494 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3495 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
3498 base_val = tp->pci_clock_ctrl;
3499 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
3500 CLOCK_CTRL_TXCLK_DISABLE);
3502 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
3503 CLOCK_CTRL_PWRDOWN_PLL133, 40);
3504 } else if (tg3_flag(tp, 5780_CLASS) ||
3505 tg3_flag(tp, CPMU_PRESENT) ||
3506 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3508 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
3509 u32 newbits1, newbits2;
3511 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3512 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3513 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
3514 CLOCK_CTRL_TXCLK_DISABLE |
3516 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
3517 } else if (tg3_flag(tp, 5705_PLUS)) {
3518 newbits1 = CLOCK_CTRL_625_CORE;
3519 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
3521 newbits1 = CLOCK_CTRL_ALTCLK;
3522 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
3525 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
3528 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
3531 if (!tg3_flag(tp, 5705_PLUS)) {
3534 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3535 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3536 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
3537 CLOCK_CTRL_TXCLK_DISABLE |
3538 CLOCK_CTRL_44MHZ_CORE);
3540 newbits3 = CLOCK_CTRL_44MHZ_CORE;
3543 tw32_wait_f(TG3PCI_CLOCK_CTRL,
3544 tp->pci_clock_ctrl | newbits3, 40);
3548 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
3549 tg3_power_down_phy(tp, do_low_power);
3551 tg3_frob_aux_power(tp, true);
3553 /* Workaround for unstable PLL clock */
3554 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
3555 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
3556 u32 val = tr32(0x7d00);
3558 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
3560 if (!tg3_flag(tp, ENABLE_ASF)) {
3563 err = tg3_nvram_lock(tp);
3564 tg3_halt_cpu(tp, RX_CPU_BASE);
3566 tg3_nvram_unlock(tp);
3570 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
3575 static void tg3_power_down(struct tg3 *tp)
3577 tg3_power_down_prepare(tp);
3579 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
3580 pci_set_power_state(tp->pdev, PCI_D3hot);
3583 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
3585 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
3586 case MII_TG3_AUX_STAT_10HALF:
3588 *duplex = DUPLEX_HALF;
3591 case MII_TG3_AUX_STAT_10FULL:
3593 *duplex = DUPLEX_FULL;
3596 case MII_TG3_AUX_STAT_100HALF:
3598 *duplex = DUPLEX_HALF;
3601 case MII_TG3_AUX_STAT_100FULL:
3603 *duplex = DUPLEX_FULL;
3606 case MII_TG3_AUX_STAT_1000HALF:
3607 *speed = SPEED_1000;
3608 *duplex = DUPLEX_HALF;
3611 case MII_TG3_AUX_STAT_1000FULL:
3612 *speed = SPEED_1000;
3613 *duplex = DUPLEX_FULL;
3617 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3618 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
3620 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
3624 *speed = SPEED_INVALID;
3625 *duplex = DUPLEX_INVALID;
3630 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
3635 new_adv = ADVERTISE_CSMA;
3636 if (advertise & ADVERTISED_10baseT_Half)
3637 new_adv |= ADVERTISE_10HALF;
3638 if (advertise & ADVERTISED_10baseT_Full)
3639 new_adv |= ADVERTISE_10FULL;
3640 if (advertise & ADVERTISED_100baseT_Half)
3641 new_adv |= ADVERTISE_100HALF;
3642 if (advertise & ADVERTISED_100baseT_Full)
3643 new_adv |= ADVERTISE_100FULL;
3645 new_adv |= tg3_advert_flowctrl_1000T(flowctrl);
3647 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
3651 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
3655 if (advertise & ADVERTISED_1000baseT_Half)
3656 new_adv |= ADVERTISE_1000HALF;
3657 if (advertise & ADVERTISED_1000baseT_Full)
3658 new_adv |= ADVERTISE_1000FULL;
3660 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3661 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
3662 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
3664 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
3668 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
3671 tw32(TG3_CPMU_EEE_MODE,
3672 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
3674 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
3679 /* Advertise 100-BaseTX EEE ability */
3680 if (advertise & ADVERTISED_100baseT_Full)
3681 val |= MDIO_AN_EEE_ADV_100TX;
3682 /* Advertise 1000-BaseT EEE ability */
3683 if (advertise & ADVERTISED_1000baseT_Full)
3684 val |= MDIO_AN_EEE_ADV_1000T;
3685 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3689 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
3691 case ASIC_REV_57765:
3693 /* If we advertised any eee advertisements above... */
3695 val = MII_TG3_DSP_TAP26_ALNOKO |
3696 MII_TG3_DSP_TAP26_RMRXSTO |
3697 MII_TG3_DSP_TAP26_OPCSINPT;
3698 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
3701 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
3702 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
3703 MII_TG3_DSP_CH34TP2_HIBW01);
3706 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
3715 static void tg3_phy_copper_begin(struct tg3 *tp)
3720 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
3721 new_adv = ADVERTISED_10baseT_Half |
3722 ADVERTISED_10baseT_Full;
3723 if (tg3_flag(tp, WOL_SPEED_100MB))
3724 new_adv |= ADVERTISED_100baseT_Half |
3725 ADVERTISED_100baseT_Full;
3727 tg3_phy_autoneg_cfg(tp, new_adv,
3728 FLOW_CTRL_TX | FLOW_CTRL_RX);
3729 } else if (tp->link_config.speed == SPEED_INVALID) {
3730 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
3731 tp->link_config.advertising &=
3732 ~(ADVERTISED_1000baseT_Half |
3733 ADVERTISED_1000baseT_Full);
3735 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
3736 tp->link_config.flowctrl);
3738 /* Asking for a specific link mode. */
3739 if (tp->link_config.speed == SPEED_1000) {
3740 if (tp->link_config.duplex == DUPLEX_FULL)
3741 new_adv = ADVERTISED_1000baseT_Full;
3743 new_adv = ADVERTISED_1000baseT_Half;
3744 } else if (tp->link_config.speed == SPEED_100) {
3745 if (tp->link_config.duplex == DUPLEX_FULL)
3746 new_adv = ADVERTISED_100baseT_Full;
3748 new_adv = ADVERTISED_100baseT_Half;
3750 if (tp->link_config.duplex == DUPLEX_FULL)
3751 new_adv = ADVERTISED_10baseT_Full;
3753 new_adv = ADVERTISED_10baseT_Half;
3756 tg3_phy_autoneg_cfg(tp, new_adv,
3757 tp->link_config.flowctrl);
3760 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3761 tp->link_config.speed != SPEED_INVALID) {
3762 u32 bmcr, orig_bmcr;
3764 tp->link_config.active_speed = tp->link_config.speed;
3765 tp->link_config.active_duplex = tp->link_config.duplex;
3768 switch (tp->link_config.speed) {
3774 bmcr |= BMCR_SPEED100;
3778 bmcr |= BMCR_SPEED1000;
3782 if (tp->link_config.duplex == DUPLEX_FULL)
3783 bmcr |= BMCR_FULLDPLX;
3785 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3786 (bmcr != orig_bmcr)) {
3787 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3788 for (i = 0; i < 1500; i++) {
3792 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3793 tg3_readphy(tp, MII_BMSR, &tmp))
3795 if (!(tmp & BMSR_LSTATUS)) {
3800 tg3_writephy(tp, MII_BMCR, bmcr);
3804 tg3_writephy(tp, MII_BMCR,
3805 BMCR_ANENABLE | BMCR_ANRESTART);
3809 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3813 /* Turn off tap power management. */
3814 /* Set Extended packet length bit */
3815 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
3817 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3818 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3819 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3820 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3821 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3828 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3830 u32 adv_reg, all_mask = 0;
3832 if (mask & ADVERTISED_10baseT_Half)
3833 all_mask |= ADVERTISE_10HALF;
3834 if (mask & ADVERTISED_10baseT_Full)
3835 all_mask |= ADVERTISE_10FULL;
3836 if (mask & ADVERTISED_100baseT_Half)
3837 all_mask |= ADVERTISE_100HALF;
3838 if (mask & ADVERTISED_100baseT_Full)
3839 all_mask |= ADVERTISE_100FULL;
3841 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3844 if ((adv_reg & ADVERTISE_ALL) != all_mask)
3847 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3851 if (mask & ADVERTISED_1000baseT_Half)
3852 all_mask |= ADVERTISE_1000HALF;
3853 if (mask & ADVERTISED_1000baseT_Full)
3854 all_mask |= ADVERTISE_1000FULL;
3856 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
3859 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
3860 if (tg3_ctrl != all_mask)
3867 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3871 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3874 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3875 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3877 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3878 if (curadv != reqadv)
3881 if (tg3_flag(tp, PAUSE_AUTONEG))
3882 tg3_readphy(tp, MII_LPA, rmtadv);
3884 /* Reprogram the advertisement register, even if it
3885 * does not affect the current link. If the link
3886 * gets renegotiated in the future, we can save an
3887 * additional renegotiation cycle by advertising
3888 * it correctly in the first place.
3890 if (curadv != reqadv) {
3891 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3892 ADVERTISE_PAUSE_ASYM);
3893 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3900 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3902 int current_link_up;
3904 u32 lcl_adv, rmt_adv;
3912 (MAC_STATUS_SYNC_CHANGED |
3913 MAC_STATUS_CFG_CHANGED |
3914 MAC_STATUS_MI_COMPLETION |
3915 MAC_STATUS_LNKSTATE_CHANGED));
3918 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3920 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3924 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
3926 /* Some third-party PHYs need to be reset on link going
3929 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3930 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3931 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3932 netif_carrier_ok(tp->dev)) {
3933 tg3_readphy(tp, MII_BMSR, &bmsr);
3934 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3935 !(bmsr & BMSR_LSTATUS))
3941 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3942 tg3_readphy(tp, MII_BMSR, &bmsr);
3943 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3944 !tg3_flag(tp, INIT_COMPLETE))
3947 if (!(bmsr & BMSR_LSTATUS)) {
3948 err = tg3_init_5401phy_dsp(tp);
3952 tg3_readphy(tp, MII_BMSR, &bmsr);
3953 for (i = 0; i < 1000; i++) {
3955 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3956 (bmsr & BMSR_LSTATUS)) {
3962 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3963 TG3_PHY_REV_BCM5401_B0 &&
3964 !(bmsr & BMSR_LSTATUS) &&
3965 tp->link_config.active_speed == SPEED_1000) {
3966 err = tg3_phy_reset(tp);
3968 err = tg3_init_5401phy_dsp(tp);
3973 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3974 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3975 /* 5701 {A0,B0} CRC bug workaround */
3976 tg3_writephy(tp, 0x15, 0x0a75);
3977 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3978 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3979 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3982 /* Clear pending interrupts... */
3983 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3984 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3986 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3987 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3988 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3989 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3991 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3992 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3993 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3994 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3995 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3997 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4000 current_link_up = 0;
4001 current_speed = SPEED_INVALID;
4002 current_duplex = DUPLEX_INVALID;
4004 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
4005 err = tg3_phy_auxctl_read(tp,
4006 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4008 if (!err && !(val & (1 << 10))) {
4009 tg3_phy_auxctl_write(tp,
4010 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4017 for (i = 0; i < 100; i++) {
4018 tg3_readphy(tp, MII_BMSR, &bmsr);
4019 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4020 (bmsr & BMSR_LSTATUS))
4025 if (bmsr & BMSR_LSTATUS) {
4028 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4029 for (i = 0; i < 2000; i++) {
4031 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4036 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4041 for (i = 0; i < 200; i++) {
4042 tg3_readphy(tp, MII_BMCR, &bmcr);
4043 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4045 if (bmcr && bmcr != 0x7fff)
4053 tp->link_config.active_speed = current_speed;
4054 tp->link_config.active_duplex = current_duplex;
4056 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4057 if ((bmcr & BMCR_ANENABLE) &&
4058 tg3_copper_is_advertising_all(tp,
4059 tp->link_config.advertising)) {
4060 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
4062 current_link_up = 1;
4065 if (!(bmcr & BMCR_ANENABLE) &&
4066 tp->link_config.speed == current_speed &&
4067 tp->link_config.duplex == current_duplex &&
4068 tp->link_config.flowctrl ==
4069 tp->link_config.active_flowctrl) {
4070 current_link_up = 1;
4074 if (current_link_up == 1 &&
4075 tp->link_config.active_duplex == DUPLEX_FULL)
4076 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4080 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4081 tg3_phy_copper_begin(tp);
4083 tg3_readphy(tp, MII_BMSR, &bmsr);
4084 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4085 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
4086 current_link_up = 1;
4089 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
4090 if (current_link_up == 1) {
4091 if (tp->link_config.active_speed == SPEED_100 ||
4092 tp->link_config.active_speed == SPEED_10)
4093 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4095 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4096 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
4097 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4099 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4101 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4102 if (tp->link_config.active_duplex == DUPLEX_HALF)
4103 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4105 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
4106 if (current_link_up == 1 &&
4107 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
4108 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
4110 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
4113 /* ??? Without this setting Netgear GA302T PHY does not
4114 * ??? send/receive packets...
4116 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
4117 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
4118 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
4119 tw32_f(MAC_MI_MODE, tp->mi_mode);
4123 tw32_f(MAC_MODE, tp->mac_mode);
4126 tg3_phy_eee_adjust(tp, current_link_up);
4128 if (tg3_flag(tp, USE_LINKCHG_REG)) {
4129 /* Polled via timer. */
4130 tw32_f(MAC_EVENT, 0);
4132 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4136 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
4137 current_link_up == 1 &&
4138 tp->link_config.active_speed == SPEED_1000 &&
4139 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
4142 (MAC_STATUS_SYNC_CHANGED |
4143 MAC_STATUS_CFG_CHANGED));
4146 NIC_SRAM_FIRMWARE_MBOX,
4147 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
4150 /* Prevent send BD corruption. */
4151 if (tg3_flag(tp, CLKREQ_BUG)) {
4152 u16 oldlnkctl, newlnkctl;
4154 pci_read_config_word(tp->pdev,
4155 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
4157 if (tp->link_config.active_speed == SPEED_100 ||
4158 tp->link_config.active_speed == SPEED_10)
4159 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
4161 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
4162 if (newlnkctl != oldlnkctl)
4163 pci_write_config_word(tp->pdev,
4164 pci_pcie_cap(tp->pdev) +
4165 PCI_EXP_LNKCTL, newlnkctl);
4168 if (current_link_up != netif_carrier_ok(tp->dev)) {
4169 if (current_link_up)
4170 netif_carrier_on(tp->dev);
4172 netif_carrier_off(tp->dev);
4173 tg3_link_report(tp);
4179 struct tg3_fiber_aneginfo {
4181 #define ANEG_STATE_UNKNOWN 0
4182 #define ANEG_STATE_AN_ENABLE 1
4183 #define ANEG_STATE_RESTART_INIT 2
4184 #define ANEG_STATE_RESTART 3
4185 #define ANEG_STATE_DISABLE_LINK_OK 4
4186 #define ANEG_STATE_ABILITY_DETECT_INIT 5
4187 #define ANEG_STATE_ABILITY_DETECT 6
4188 #define ANEG_STATE_ACK_DETECT_INIT 7
4189 #define ANEG_STATE_ACK_DETECT 8
4190 #define ANEG_STATE_COMPLETE_ACK_INIT 9
4191 #define ANEG_STATE_COMPLETE_ACK 10
4192 #define ANEG_STATE_IDLE_DETECT_INIT 11
4193 #define ANEG_STATE_IDLE_DETECT 12
4194 #define ANEG_STATE_LINK_OK 13
4195 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
4196 #define ANEG_STATE_NEXT_PAGE_WAIT 15
4199 #define MR_AN_ENABLE 0x00000001
4200 #define MR_RESTART_AN 0x00000002
4201 #define MR_AN_COMPLETE 0x00000004
4202 #define MR_PAGE_RX 0x00000008
4203 #define MR_NP_LOADED 0x00000010
4204 #define MR_TOGGLE_TX 0x00000020
4205 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
4206 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
4207 #define MR_LP_ADV_SYM_PAUSE 0x00000100
4208 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
4209 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
4210 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
4211 #define MR_LP_ADV_NEXT_PAGE 0x00001000
4212 #define MR_TOGGLE_RX 0x00002000
4213 #define MR_NP_RX 0x00004000
4215 #define MR_LINK_OK 0x80000000
4217 unsigned long link_time, cur_time;
4219 u32 ability_match_cfg;
4220 int ability_match_count;
4222 char ability_match, idle_match, ack_match;
4224 u32 txconfig, rxconfig;
4225 #define ANEG_CFG_NP 0x00000080
4226 #define ANEG_CFG_ACK 0x00000040
4227 #define ANEG_CFG_RF2 0x00000020
4228 #define ANEG_CFG_RF1 0x00000010
4229 #define ANEG_CFG_PS2 0x00000001
4230 #define ANEG_CFG_PS1 0x00008000
4231 #define ANEG_CFG_HD 0x00004000
4232 #define ANEG_CFG_FD 0x00002000
4233 #define ANEG_CFG_INVAL 0x00001f06
4238 #define ANEG_TIMER_ENAB 2
4239 #define ANEG_FAILED -1
4241 #define ANEG_STATE_SETTLE_TIME 10000
4243 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
4244 struct tg3_fiber_aneginfo *ap)
4247 unsigned long delta;
4251 if (ap->state == ANEG_STATE_UNKNOWN) {
4255 ap->ability_match_cfg = 0;
4256 ap->ability_match_count = 0;
4257 ap->ability_match = 0;
4263 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
4264 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
4266 if (rx_cfg_reg != ap->ability_match_cfg) {
4267 ap->ability_match_cfg = rx_cfg_reg;
4268 ap->ability_match = 0;
4269 ap->ability_match_count = 0;
4271 if (++ap->ability_match_count > 1) {
4272 ap->ability_match = 1;
4273 ap->ability_match_cfg = rx_cfg_reg;
4276 if (rx_cfg_reg & ANEG_CFG_ACK)
4284 ap->ability_match_cfg = 0;
4285 ap->ability_match_count = 0;
4286 ap->ability_match = 0;
4292 ap->rxconfig = rx_cfg_reg;
4295 switch (ap->state) {
4296 case ANEG_STATE_UNKNOWN:
4297 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
4298 ap->state = ANEG_STATE_AN_ENABLE;
4301 case ANEG_STATE_AN_ENABLE:
4302 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
4303 if (ap->flags & MR_AN_ENABLE) {
4306 ap->ability_match_cfg = 0;
4307 ap->ability_match_count = 0;
4308 ap->ability_match = 0;
4312 ap->state = ANEG_STATE_RESTART_INIT;
4314 ap->state = ANEG_STATE_DISABLE_LINK_OK;
4318 case ANEG_STATE_RESTART_INIT:
4319 ap->link_time = ap->cur_time;
4320 ap->flags &= ~(MR_NP_LOADED);
4322 tw32(MAC_TX_AUTO_NEG, 0);
4323 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4324 tw32_f(MAC_MODE, tp->mac_mode);
4327 ret = ANEG_TIMER_ENAB;
4328 ap->state = ANEG_STATE_RESTART;
4331 case ANEG_STATE_RESTART:
4332 delta = ap->cur_time - ap->link_time;
4333 if (delta > ANEG_STATE_SETTLE_TIME)
4334 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
4336 ret = ANEG_TIMER_ENAB;
4339 case ANEG_STATE_DISABLE_LINK_OK:
4343 case ANEG_STATE_ABILITY_DETECT_INIT:
4344 ap->flags &= ~(MR_TOGGLE_TX);
4345 ap->txconfig = ANEG_CFG_FD;
4346 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4347 if (flowctrl & ADVERTISE_1000XPAUSE)
4348 ap->txconfig |= ANEG_CFG_PS1;
4349 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4350 ap->txconfig |= ANEG_CFG_PS2;
4351 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
4352 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4353 tw32_f(MAC_MODE, tp->mac_mode);
4356 ap->state = ANEG_STATE_ABILITY_DETECT;
4359 case ANEG_STATE_ABILITY_DETECT:
4360 if (ap->ability_match != 0 && ap->rxconfig != 0)
4361 ap->state = ANEG_STATE_ACK_DETECT_INIT;
4364 case ANEG_STATE_ACK_DETECT_INIT:
4365 ap->txconfig |= ANEG_CFG_ACK;
4366 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
4367 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4368 tw32_f(MAC_MODE, tp->mac_mode);
4371 ap->state = ANEG_STATE_ACK_DETECT;
4374 case ANEG_STATE_ACK_DETECT:
4375 if (ap->ack_match != 0) {
4376 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
4377 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
4378 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
4380 ap->state = ANEG_STATE_AN_ENABLE;
4382 } else if (ap->ability_match != 0 &&
4383 ap->rxconfig == 0) {
4384 ap->state = ANEG_STATE_AN_ENABLE;
4388 case ANEG_STATE_COMPLETE_ACK_INIT:
4389 if (ap->rxconfig & ANEG_CFG_INVAL) {
4393 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
4394 MR_LP_ADV_HALF_DUPLEX |
4395 MR_LP_ADV_SYM_PAUSE |
4396 MR_LP_ADV_ASYM_PAUSE |
4397 MR_LP_ADV_REMOTE_FAULT1 |
4398 MR_LP_ADV_REMOTE_FAULT2 |
4399 MR_LP_ADV_NEXT_PAGE |
4402 if (ap->rxconfig & ANEG_CFG_FD)
4403 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
4404 if (ap->rxconfig & ANEG_CFG_HD)
4405 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
4406 if (ap->rxconfig & ANEG_CFG_PS1)
4407 ap->flags |= MR_LP_ADV_SYM_PAUSE;
4408 if (ap->rxconfig & ANEG_CFG_PS2)
4409 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
4410 if (ap->rxconfig & ANEG_CFG_RF1)
4411 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
4412 if (ap->rxconfig & ANEG_CFG_RF2)
4413 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
4414 if (ap->rxconfig & ANEG_CFG_NP)
4415 ap->flags |= MR_LP_ADV_NEXT_PAGE;
4417 ap->link_time = ap->cur_time;
4419 ap->flags ^= (MR_TOGGLE_TX);
4420 if (ap->rxconfig & 0x0008)
4421 ap->flags |= MR_TOGGLE_RX;
4422 if (ap->rxconfig & ANEG_CFG_NP)
4423 ap->flags |= MR_NP_RX;
4424 ap->flags |= MR_PAGE_RX;
4426 ap->state = ANEG_STATE_COMPLETE_ACK;
4427 ret = ANEG_TIMER_ENAB;
4430 case ANEG_STATE_COMPLETE_ACK:
4431 if (ap->ability_match != 0 &&
4432 ap->rxconfig == 0) {
4433 ap->state = ANEG_STATE_AN_ENABLE;
4436 delta = ap->cur_time - ap->link_time;
4437 if (delta > ANEG_STATE_SETTLE_TIME) {
4438 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
4439 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
4441 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
4442 !(ap->flags & MR_NP_RX)) {
4443 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
4451 case ANEG_STATE_IDLE_DETECT_INIT:
4452 ap->link_time = ap->cur_time;
4453 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
4454 tw32_f(MAC_MODE, tp->mac_mode);
4457 ap->state = ANEG_STATE_IDLE_DETECT;
4458 ret = ANEG_TIMER_ENAB;
4461 case ANEG_STATE_IDLE_DETECT:
4462 if (ap->ability_match != 0 &&
4463 ap->rxconfig == 0) {
4464 ap->state = ANEG_STATE_AN_ENABLE;
4467 delta = ap->cur_time - ap->link_time;
4468 if (delta > ANEG_STATE_SETTLE_TIME) {
4469 /* XXX another gem from the Broadcom driver :( */
4470 ap->state = ANEG_STATE_LINK_OK;
4474 case ANEG_STATE_LINK_OK:
4475 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
4479 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
4480 /* ??? unimplemented */
4483 case ANEG_STATE_NEXT_PAGE_WAIT:
4484 /* ??? unimplemented */
4495 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
4498 struct tg3_fiber_aneginfo aninfo;
4499 int status = ANEG_FAILED;
4503 tw32_f(MAC_TX_AUTO_NEG, 0);
4505 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
4506 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
4509 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
4512 memset(&aninfo, 0, sizeof(aninfo));
4513 aninfo.flags |= MR_AN_ENABLE;
4514 aninfo.state = ANEG_STATE_UNKNOWN;
4515 aninfo.cur_time = 0;
4517 while (++tick < 195000) {
4518 status = tg3_fiber_aneg_smachine(tp, &aninfo);
4519 if (status == ANEG_DONE || status == ANEG_FAILED)
4525 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
4526 tw32_f(MAC_MODE, tp->mac_mode);
4529 *txflags = aninfo.txconfig;
4530 *rxflags = aninfo.flags;
4532 if (status == ANEG_DONE &&
4533 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
4534 MR_LP_ADV_FULL_DUPLEX)))
4540 static void tg3_init_bcm8002(struct tg3 *tp)
4542 u32 mac_status = tr32(MAC_STATUS);
4545 /* Reset when initting first time or we have a link. */
4546 if (tg3_flag(tp, INIT_COMPLETE) &&
4547 !(mac_status & MAC_STATUS_PCS_SYNCED))
4550 /* Set PLL lock range. */
4551 tg3_writephy(tp, 0x16, 0x8007);
4554 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
4556 /* Wait for reset to complete. */
4557 /* XXX schedule_timeout() ... */
4558 for (i = 0; i < 500; i++)
4561 /* Config mode; select PMA/Ch 1 regs. */
4562 tg3_writephy(tp, 0x10, 0x8411);
4564 /* Enable auto-lock and comdet, select txclk for tx. */
4565 tg3_writephy(tp, 0x11, 0x0a10);
4567 tg3_writephy(tp, 0x18, 0x00a0);
4568 tg3_writephy(tp, 0x16, 0x41ff);
4570 /* Assert and deassert POR. */
4571 tg3_writephy(tp, 0x13, 0x0400);
4573 tg3_writephy(tp, 0x13, 0x0000);
4575 tg3_writephy(tp, 0x11, 0x0a50);
4577 tg3_writephy(tp, 0x11, 0x0a10);
4579 /* Wait for signal to stabilize */
4580 /* XXX schedule_timeout() ... */
4581 for (i = 0; i < 15000; i++)
4584 /* Deselect the channel register so we can read the PHYID
4587 tg3_writephy(tp, 0x10, 0x8011);
4590 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
4593 u32 sg_dig_ctrl, sg_dig_status;
4594 u32 serdes_cfg, expected_sg_dig_ctrl;
4595 int workaround, port_a;
4596 int current_link_up;
4599 expected_sg_dig_ctrl = 0;
4602 current_link_up = 0;
4604 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
4605 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
4607 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
4610 /* preserve bits 0-11,13,14 for signal pre-emphasis */
4611 /* preserve bits 20-23 for voltage regulator */
4612 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
4615 sg_dig_ctrl = tr32(SG_DIG_CTRL);
4617 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
4618 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
4620 u32 val = serdes_cfg;
4626 tw32_f(MAC_SERDES_CFG, val);
4629 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
4631 if (mac_status & MAC_STATUS_PCS_SYNCED) {
4632 tg3_setup_flow_control(tp, 0, 0);
4633 current_link_up = 1;
4638 /* Want auto-negotiation. */
4639 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
4641 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4642 if (flowctrl & ADVERTISE_1000XPAUSE)
4643 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
4644 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4645 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
4647 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
4648 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
4649 tp->serdes_counter &&
4650 ((mac_status & (MAC_STATUS_PCS_SYNCED |
4651 MAC_STATUS_RCVD_CFG)) ==
4652 MAC_STATUS_PCS_SYNCED)) {
4653 tp->serdes_counter--;
4654 current_link_up = 1;
4659 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
4660 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
4662 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
4664 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
4665 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4666 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
4667 MAC_STATUS_SIGNAL_DET)) {
4668 sg_dig_status = tr32(SG_DIG_STATUS);
4669 mac_status = tr32(MAC_STATUS);
4671 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
4672 (mac_status & MAC_STATUS_PCS_SYNCED)) {
4673 u32 local_adv = 0, remote_adv = 0;
4675 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
4676 local_adv |= ADVERTISE_1000XPAUSE;
4677 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
4678 local_adv |= ADVERTISE_1000XPSE_ASYM;
4680 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
4681 remote_adv |= LPA_1000XPAUSE;
4682 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
4683 remote_adv |= LPA_1000XPAUSE_ASYM;
4685 tg3_setup_flow_control(tp, local_adv, remote_adv);
4686 current_link_up = 1;
4687 tp->serdes_counter = 0;
4688 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4689 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
4690 if (tp->serdes_counter)
4691 tp->serdes_counter--;
4694 u32 val = serdes_cfg;
4701 tw32_f(MAC_SERDES_CFG, val);
4704 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
4707 /* Link parallel detection - link is up */
4708 /* only if we have PCS_SYNC and not */
4709 /* receiving config code words */
4710 mac_status = tr32(MAC_STATUS);
4711 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
4712 !(mac_status & MAC_STATUS_RCVD_CFG)) {
4713 tg3_setup_flow_control(tp, 0, 0);
4714 current_link_up = 1;
4716 TG3_PHYFLG_PARALLEL_DETECT;
4717 tp->serdes_counter =
4718 SERDES_PARALLEL_DET_TIMEOUT;
4720 goto restart_autoneg;
4724 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
4725 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4729 return current_link_up;
4732 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
4734 int current_link_up = 0;
4736 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
4739 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4740 u32 txflags, rxflags;
4743 if (fiber_autoneg(tp, &txflags, &rxflags)) {
4744 u32 local_adv = 0, remote_adv = 0;
4746 if (txflags & ANEG_CFG_PS1)
4747 local_adv |= ADVERTISE_1000XPAUSE;
4748 if (txflags & ANEG_CFG_PS2)
4749 local_adv |= ADVERTISE_1000XPSE_ASYM;
4751 if (rxflags & MR_LP_ADV_SYM_PAUSE)
4752 remote_adv |= LPA_1000XPAUSE;
4753 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
4754 remote_adv |= LPA_1000XPAUSE_ASYM;
4756 tg3_setup_flow_control(tp, local_adv, remote_adv);
4758 current_link_up = 1;
4760 for (i = 0; i < 30; i++) {
4763 (MAC_STATUS_SYNC_CHANGED |
4764 MAC_STATUS_CFG_CHANGED));
4766 if ((tr32(MAC_STATUS) &
4767 (MAC_STATUS_SYNC_CHANGED |
4768 MAC_STATUS_CFG_CHANGED)) == 0)
4772 mac_status = tr32(MAC_STATUS);
4773 if (current_link_up == 0 &&
4774 (mac_status & MAC_STATUS_PCS_SYNCED) &&
4775 !(mac_status & MAC_STATUS_RCVD_CFG))
4776 current_link_up = 1;
4778 tg3_setup_flow_control(tp, 0, 0);
4780 /* Forcing 1000FD link up. */
4781 current_link_up = 1;
4783 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4786 tw32_f(MAC_MODE, tp->mac_mode);
4791 return current_link_up;
4794 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4797 u16 orig_active_speed;
4798 u8 orig_active_duplex;
4800 int current_link_up;
4803 orig_pause_cfg = tp->link_config.active_flowctrl;
4804 orig_active_speed = tp->link_config.active_speed;
4805 orig_active_duplex = tp->link_config.active_duplex;
4807 if (!tg3_flag(tp, HW_AUTONEG) &&
4808 netif_carrier_ok(tp->dev) &&
4809 tg3_flag(tp, INIT_COMPLETE)) {
4810 mac_status = tr32(MAC_STATUS);
4811 mac_status &= (MAC_STATUS_PCS_SYNCED |
4812 MAC_STATUS_SIGNAL_DET |
4813 MAC_STATUS_CFG_CHANGED |
4814 MAC_STATUS_RCVD_CFG);
4815 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4816 MAC_STATUS_SIGNAL_DET)) {
4817 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4818 MAC_STATUS_CFG_CHANGED));
4823 tw32_f(MAC_TX_AUTO_NEG, 0);
4825 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4826 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4827 tw32_f(MAC_MODE, tp->mac_mode);
4830 if (tp->phy_id == TG3_PHY_ID_BCM8002)
4831 tg3_init_bcm8002(tp);
4833 /* Enable link change event even when serdes polling. */
4834 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4837 current_link_up = 0;
4838 mac_status = tr32(MAC_STATUS);
4840 if (tg3_flag(tp, HW_AUTONEG))
4841 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4843 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4845 tp->napi[0].hw_status->status =
4846 (SD_STATUS_UPDATED |
4847 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4849 for (i = 0; i < 100; i++) {
4850 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4851 MAC_STATUS_CFG_CHANGED));
4853 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4854 MAC_STATUS_CFG_CHANGED |
4855 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4859 mac_status = tr32(MAC_STATUS);
4860 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4861 current_link_up = 0;
4862 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4863 tp->serdes_counter == 0) {
4864 tw32_f(MAC_MODE, (tp->mac_mode |
4865 MAC_MODE_SEND_CONFIGS));
4867 tw32_f(MAC_MODE, tp->mac_mode);
4871 if (current_link_up == 1) {
4872 tp->link_config.active_speed = SPEED_1000;
4873 tp->link_config.active_duplex = DUPLEX_FULL;
4874 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4875 LED_CTRL_LNKLED_OVERRIDE |
4876 LED_CTRL_1000MBPS_ON));
4878 tp->link_config.active_speed = SPEED_INVALID;
4879 tp->link_config.active_duplex = DUPLEX_INVALID;
4880 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4881 LED_CTRL_LNKLED_OVERRIDE |
4882 LED_CTRL_TRAFFIC_OVERRIDE));
4885 if (current_link_up != netif_carrier_ok(tp->dev)) {
4886 if (current_link_up)
4887 netif_carrier_on(tp->dev);
4889 netif_carrier_off(tp->dev);
4890 tg3_link_report(tp);
4892 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4893 if (orig_pause_cfg != now_pause_cfg ||
4894 orig_active_speed != tp->link_config.active_speed ||
4895 orig_active_duplex != tp->link_config.active_duplex)
4896 tg3_link_report(tp);
4902 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4904 int current_link_up, err = 0;
4908 u32 local_adv, remote_adv;
4910 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4911 tw32_f(MAC_MODE, tp->mac_mode);
4917 (MAC_STATUS_SYNC_CHANGED |
4918 MAC_STATUS_CFG_CHANGED |
4919 MAC_STATUS_MI_COMPLETION |
4920 MAC_STATUS_LNKSTATE_CHANGED));
4926 current_link_up = 0;
4927 current_speed = SPEED_INVALID;
4928 current_duplex = DUPLEX_INVALID;
4930 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4931 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4932 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4933 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4934 bmsr |= BMSR_LSTATUS;
4936 bmsr &= ~BMSR_LSTATUS;
4939 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4941 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4942 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4943 /* do nothing, just check for link up at the end */
4944 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4947 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4948 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4949 ADVERTISE_1000XPAUSE |
4950 ADVERTISE_1000XPSE_ASYM |
4953 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4955 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4956 new_adv |= ADVERTISE_1000XHALF;
4957 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4958 new_adv |= ADVERTISE_1000XFULL;
4960 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4961 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4962 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4963 tg3_writephy(tp, MII_BMCR, bmcr);
4965 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4966 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4967 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4974 bmcr &= ~BMCR_SPEED1000;
4975 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4977 if (tp->link_config.duplex == DUPLEX_FULL)
4978 new_bmcr |= BMCR_FULLDPLX;
4980 if (new_bmcr != bmcr) {
4981 /* BMCR_SPEED1000 is a reserved bit that needs
4982 * to be set on write.
4984 new_bmcr |= BMCR_SPEED1000;
4986 /* Force a linkdown */
4987 if (netif_carrier_ok(tp->dev)) {
4990 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4991 adv &= ~(ADVERTISE_1000XFULL |
4992 ADVERTISE_1000XHALF |
4994 tg3_writephy(tp, MII_ADVERTISE, adv);
4995 tg3_writephy(tp, MII_BMCR, bmcr |
4999 netif_carrier_off(tp->dev);
5001 tg3_writephy(tp, MII_BMCR, new_bmcr);
5003 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5004 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5005 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
5007 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5008 bmsr |= BMSR_LSTATUS;
5010 bmsr &= ~BMSR_LSTATUS;
5012 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5016 if (bmsr & BMSR_LSTATUS) {
5017 current_speed = SPEED_1000;
5018 current_link_up = 1;
5019 if (bmcr & BMCR_FULLDPLX)
5020 current_duplex = DUPLEX_FULL;
5022 current_duplex = DUPLEX_HALF;
5027 if (bmcr & BMCR_ANENABLE) {
5030 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5031 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5032 common = local_adv & remote_adv;
5033 if (common & (ADVERTISE_1000XHALF |
5034 ADVERTISE_1000XFULL)) {
5035 if (common & ADVERTISE_1000XFULL)
5036 current_duplex = DUPLEX_FULL;
5038 current_duplex = DUPLEX_HALF;
5039 } else if (!tg3_flag(tp, 5780_CLASS)) {
5040 /* Link is up via parallel detect */
5042 current_link_up = 0;
5047 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
5048 tg3_setup_flow_control(tp, local_adv, remote_adv);
5050 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5051 if (tp->link_config.active_duplex == DUPLEX_HALF)
5052 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5054 tw32_f(MAC_MODE, tp->mac_mode);
5057 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5059 tp->link_config.active_speed = current_speed;
5060 tp->link_config.active_duplex = current_duplex;
5062 if (current_link_up != netif_carrier_ok(tp->dev)) {
5063 if (current_link_up)
5064 netif_carrier_on(tp->dev);
5066 netif_carrier_off(tp->dev);
5067 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5069 tg3_link_report(tp);
5074 static void tg3_serdes_parallel_detect(struct tg3 *tp)
5076 if (tp->serdes_counter) {
5077 /* Give autoneg time to complete. */
5078 tp->serdes_counter--;
5082 if (!netif_carrier_ok(tp->dev) &&
5083 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
5086 tg3_readphy(tp, MII_BMCR, &bmcr);
5087 if (bmcr & BMCR_ANENABLE) {
5090 /* Select shadow register 0x1f */
5091 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
5092 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
5094 /* Select expansion interrupt status register */
5095 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5096 MII_TG3_DSP_EXP1_INT_STAT);
5097 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5098 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5100 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
5101 /* We have signal detect and not receiving
5102 * config code words, link is up by parallel
5106 bmcr &= ~BMCR_ANENABLE;
5107 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5108 tg3_writephy(tp, MII_BMCR, bmcr);
5109 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
5112 } else if (netif_carrier_ok(tp->dev) &&
5113 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
5114 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5117 /* Select expansion interrupt status register */
5118 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5119 MII_TG3_DSP_EXP1_INT_STAT);
5120 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5124 /* Config code words received, turn on autoneg. */
5125 tg3_readphy(tp, MII_BMCR, &bmcr);
5126 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
5128 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5134 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
5139 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
5140 err = tg3_setup_fiber_phy(tp, force_reset);
5141 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
5142 err = tg3_setup_fiber_mii_phy(tp, force_reset);
5144 err = tg3_setup_copper_phy(tp, force_reset);
5146 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
5149 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
5150 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
5152 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
5157 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
5158 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
5159 tw32(GRC_MISC_CFG, val);
5162 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5163 (6 << TX_LENGTHS_IPG_SHIFT);
5164 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
5165 val |= tr32(MAC_TX_LENGTHS) &
5166 (TX_LENGTHS_JMB_FRM_LEN_MSK |
5167 TX_LENGTHS_CNT_DWN_VAL_MSK);
5169 if (tp->link_config.active_speed == SPEED_1000 &&
5170 tp->link_config.active_duplex == DUPLEX_HALF)
5171 tw32(MAC_TX_LENGTHS, val |
5172 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
5174 tw32(MAC_TX_LENGTHS, val |
5175 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5177 if (!tg3_flag(tp, 5705_PLUS)) {
5178 if (netif_carrier_ok(tp->dev)) {
5179 tw32(HOSTCC_STAT_COAL_TICKS,
5180 tp->coal.stats_block_coalesce_usecs);
5182 tw32(HOSTCC_STAT_COAL_TICKS, 0);
5186 if (tg3_flag(tp, ASPM_WORKAROUND)) {
5187 val = tr32(PCIE_PWR_MGMT_THRESH);
5188 if (!netif_carrier_ok(tp->dev))
5189 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
5192 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
5193 tw32(PCIE_PWR_MGMT_THRESH, val);
5199 static inline int tg3_irq_sync(struct tg3 *tp)
5201 return tp->irq_sync;
5204 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
5208 dst = (u32 *)((u8 *)dst + off);
5209 for (i = 0; i < len; i += sizeof(u32))
5210 *dst++ = tr32(off + i);
5213 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
5215 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
5216 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
5217 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
5218 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
5219 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
5220 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
5221 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
5222 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
5223 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
5224 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
5225 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
5226 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
5227 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
5228 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
5229 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
5230 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
5231 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
5232 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
5233 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
5235 if (tg3_flag(tp, SUPPORT_MSIX))
5236 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
5238 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
5239 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
5240 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
5241 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
5242 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
5243 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
5244 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
5245 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
5247 if (!tg3_flag(tp, 5705_PLUS)) {
5248 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
5249 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
5250 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
5253 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
5254 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
5255 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
5256 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
5257 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
5259 if (tg3_flag(tp, NVRAM))
5260 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
5263 static void tg3_dump_state(struct tg3 *tp)
5268 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
5270 netdev_err(tp->dev, "Failed allocating register dump buffer\n");
5274 if (tg3_flag(tp, PCI_EXPRESS)) {
5275 /* Read up to but not including private PCI registers */
5276 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
5277 regs[i / sizeof(u32)] = tr32(i);
5279 tg3_dump_legacy_regs(tp, regs);
5281 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
5282 if (!regs[i + 0] && !regs[i + 1] &&
5283 !regs[i + 2] && !regs[i + 3])
5286 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
5288 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
5293 for (i = 0; i < tp->irq_cnt; i++) {
5294 struct tg3_napi *tnapi = &tp->napi[i];
5296 /* SW status block */
5298 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
5300 tnapi->hw_status->status,
5301 tnapi->hw_status->status_tag,
5302 tnapi->hw_status->rx_jumbo_consumer,
5303 tnapi->hw_status->rx_consumer,
5304 tnapi->hw_status->rx_mini_consumer,
5305 tnapi->hw_status->idx[0].rx_producer,
5306 tnapi->hw_status->idx[0].tx_consumer);
5309 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
5311 tnapi->last_tag, tnapi->last_irq_tag,
5312 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
5314 tnapi->prodring.rx_std_prod_idx,
5315 tnapi->prodring.rx_std_cons_idx,
5316 tnapi->prodring.rx_jmb_prod_idx,
5317 tnapi->prodring.rx_jmb_cons_idx);
5321 /* This is called whenever we suspect that the system chipset is re-
5322 * ordering the sequence of MMIO to the tx send mailbox. The symptom
5323 * is bogus tx completions. We try to recover by setting the
5324 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
5327 static void tg3_tx_recover(struct tg3 *tp)
5329 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
5330 tp->write32_tx_mbox == tg3_write_indirect_mbox);
5332 netdev_warn(tp->dev,
5333 "The system may be re-ordering memory-mapped I/O "
5334 "cycles to the network device, attempting to recover. "
5335 "Please report the problem to the driver maintainer "
5336 "and include system chipset information.\n");
5338 spin_lock(&tp->lock);
5339 tg3_flag_set(tp, TX_RECOVERY_PENDING);
5340 spin_unlock(&tp->lock);
5343 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
5345 /* Tell compiler to fetch tx indices from memory. */
5347 return tnapi->tx_pending -
5348 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
5351 /* Tigon3 never reports partial packet sends. So we do not
5352 * need special logic to handle SKBs that have not had all
5353 * of their frags sent yet, like SunGEM does.
5355 static void tg3_tx(struct tg3_napi *tnapi)
5357 struct tg3 *tp = tnapi->tp;
5358 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
5359 u32 sw_idx = tnapi->tx_cons;
5360 struct netdev_queue *txq;
5361 int index = tnapi - tp->napi;
5363 if (tg3_flag(tp, ENABLE_TSS))
5366 txq = netdev_get_tx_queue(tp->dev, index);
5368 while (sw_idx != hw_idx) {
5369 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
5370 struct sk_buff *skb = ri->skb;
5373 if (unlikely(skb == NULL)) {
5378 pci_unmap_single(tp->pdev,
5379 dma_unmap_addr(ri, mapping),
5385 while (ri->fragmented) {
5386 ri->fragmented = false;
5387 sw_idx = NEXT_TX(sw_idx);
5388 ri = &tnapi->tx_buffers[sw_idx];
5391 sw_idx = NEXT_TX(sw_idx);
5393 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
5394 ri = &tnapi->tx_buffers[sw_idx];
5395 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
5398 pci_unmap_page(tp->pdev,
5399 dma_unmap_addr(ri, mapping),
5400 skb_frag_size(&skb_shinfo(skb)->frags[i]),
5403 while (ri->fragmented) {
5404 ri->fragmented = false;
5405 sw_idx = NEXT_TX(sw_idx);
5406 ri = &tnapi->tx_buffers[sw_idx];
5409 sw_idx = NEXT_TX(sw_idx);
5414 if (unlikely(tx_bug)) {
5420 tnapi->tx_cons = sw_idx;
5422 /* Need to make the tx_cons update visible to tg3_start_xmit()
5423 * before checking for netif_queue_stopped(). Without the
5424 * memory barrier, there is a small possibility that tg3_start_xmit()
5425 * will miss it and cause the queue to be stopped forever.
5429 if (unlikely(netif_tx_queue_stopped(txq) &&
5430 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
5431 __netif_tx_lock(txq, smp_processor_id());
5432 if (netif_tx_queue_stopped(txq) &&
5433 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
5434 netif_tx_wake_queue(txq);
5435 __netif_tx_unlock(txq);
5439 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
5444 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
5445 map_sz, PCI_DMA_FROMDEVICE);
5446 dev_kfree_skb_any(ri->skb);
5450 /* Returns size of skb allocated or < 0 on error.
5452 * We only need to fill in the address because the other members
5453 * of the RX descriptor are invariant, see tg3_init_rings.
5455 * Note the purposeful assymetry of cpu vs. chip accesses. For
5456 * posting buffers we only dirty the first cache line of the RX
5457 * descriptor (containing the address). Whereas for the RX status
5458 * buffers the cpu only reads the last cacheline of the RX descriptor
5459 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
5461 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
5462 u32 opaque_key, u32 dest_idx_unmasked)
5464 struct tg3_rx_buffer_desc *desc;
5465 struct ring_info *map;
5466 struct sk_buff *skb;
5468 int skb_size, dest_idx;
5470 switch (opaque_key) {
5471 case RXD_OPAQUE_RING_STD:
5472 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
5473 desc = &tpr->rx_std[dest_idx];
5474 map = &tpr->rx_std_buffers[dest_idx];
5475 skb_size = tp->rx_pkt_map_sz;
5478 case RXD_OPAQUE_RING_JUMBO:
5479 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
5480 desc = &tpr->rx_jmb[dest_idx].std;
5481 map = &tpr->rx_jmb_buffers[dest_idx];
5482 skb_size = TG3_RX_JMB_MAP_SZ;
5489 /* Do not overwrite any of the map or rp information
5490 * until we are sure we can commit to a new buffer.
5492 * Callers depend upon this behavior and assume that
5493 * we leave everything unchanged if we fail.
5495 skb = netdev_alloc_skb(tp->dev, skb_size + TG3_RX_OFFSET(tp));
5499 skb_reserve(skb, TG3_RX_OFFSET(tp));
5501 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
5502 PCI_DMA_FROMDEVICE);
5503 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5509 dma_unmap_addr_set(map, mapping, mapping);
5511 desc->addr_hi = ((u64)mapping >> 32);
5512 desc->addr_lo = ((u64)mapping & 0xffffffff);
5517 /* We only need to move over in the address because the other
5518 * members of the RX descriptor are invariant. See notes above
5519 * tg3_alloc_rx_skb for full details.
5521 static void tg3_recycle_rx(struct tg3_napi *tnapi,
5522 struct tg3_rx_prodring_set *dpr,
5523 u32 opaque_key, int src_idx,
5524 u32 dest_idx_unmasked)
5526 struct tg3 *tp = tnapi->tp;
5527 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
5528 struct ring_info *src_map, *dest_map;
5529 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
5532 switch (opaque_key) {
5533 case RXD_OPAQUE_RING_STD:
5534 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
5535 dest_desc = &dpr->rx_std[dest_idx];
5536 dest_map = &dpr->rx_std_buffers[dest_idx];
5537 src_desc = &spr->rx_std[src_idx];
5538 src_map = &spr->rx_std_buffers[src_idx];
5541 case RXD_OPAQUE_RING_JUMBO:
5542 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
5543 dest_desc = &dpr->rx_jmb[dest_idx].std;
5544 dest_map = &dpr->rx_jmb_buffers[dest_idx];
5545 src_desc = &spr->rx_jmb[src_idx].std;
5546 src_map = &spr->rx_jmb_buffers[src_idx];
5553 dest_map->skb = src_map->skb;
5554 dma_unmap_addr_set(dest_map, mapping,
5555 dma_unmap_addr(src_map, mapping));
5556 dest_desc->addr_hi = src_desc->addr_hi;
5557 dest_desc->addr_lo = src_desc->addr_lo;
5559 /* Ensure that the update to the skb happens after the physical
5560 * addresses have been transferred to the new BD location.
5564 src_map->skb = NULL;
5567 /* The RX ring scheme is composed of multiple rings which post fresh
5568 * buffers to the chip, and one special ring the chip uses to report
5569 * status back to the host.
5571 * The special ring reports the status of received packets to the
5572 * host. The chip does not write into the original descriptor the
5573 * RX buffer was obtained from. The chip simply takes the original
5574 * descriptor as provided by the host, updates the status and length
5575 * field, then writes this into the next status ring entry.
5577 * Each ring the host uses to post buffers to the chip is described
5578 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
5579 * it is first placed into the on-chip ram. When the packet's length
5580 * is known, it walks down the TG3_BDINFO entries to select the ring.
5581 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
5582 * which is within the range of the new packet's length is chosen.
5584 * The "separate ring for rx status" scheme may sound queer, but it makes
5585 * sense from a cache coherency perspective. If only the host writes
5586 * to the buffer post rings, and only the chip writes to the rx status
5587 * rings, then cache lines never move beyond shared-modified state.
5588 * If both the host and chip were to write into the same ring, cache line
5589 * eviction could occur since both entities want it in an exclusive state.
5591 static int tg3_rx(struct tg3_napi *tnapi, int budget)
5593 struct tg3 *tp = tnapi->tp;
5594 u32 work_mask, rx_std_posted = 0;
5595 u32 std_prod_idx, jmb_prod_idx;
5596 u32 sw_idx = tnapi->rx_rcb_ptr;
5599 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
5601 hw_idx = *(tnapi->rx_rcb_prod_idx);
5603 * We need to order the read of hw_idx and the read of
5604 * the opaque cookie.
5609 std_prod_idx = tpr->rx_std_prod_idx;
5610 jmb_prod_idx = tpr->rx_jmb_prod_idx;
5611 while (sw_idx != hw_idx && budget > 0) {
5612 struct ring_info *ri;
5613 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
5615 struct sk_buff *skb;
5616 dma_addr_t dma_addr;
5617 u32 opaque_key, desc_idx, *post_ptr;
5619 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
5620 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
5621 if (opaque_key == RXD_OPAQUE_RING_STD) {
5622 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
5623 dma_addr = dma_unmap_addr(ri, mapping);
5625 post_ptr = &std_prod_idx;
5627 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
5628 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
5629 dma_addr = dma_unmap_addr(ri, mapping);
5631 post_ptr = &jmb_prod_idx;
5633 goto next_pkt_nopost;
5635 work_mask |= opaque_key;
5637 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
5638 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
5640 tg3_recycle_rx(tnapi, tpr, opaque_key,
5641 desc_idx, *post_ptr);
5643 /* Other statistics kept track of by card. */
5648 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
5651 if (len > TG3_RX_COPY_THRESH(tp)) {
5654 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
5659 pci_unmap_single(tp->pdev, dma_addr, skb_size,
5660 PCI_DMA_FROMDEVICE);
5662 /* Ensure that the update to the skb happens
5663 * after the usage of the old DMA mapping.
5671 struct sk_buff *copy_skb;
5673 tg3_recycle_rx(tnapi, tpr, opaque_key,
5674 desc_idx, *post_ptr);
5676 copy_skb = netdev_alloc_skb(tp->dev, len +
5678 if (copy_skb == NULL)
5679 goto drop_it_no_recycle;
5681 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
5682 skb_put(copy_skb, len);
5683 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
5684 skb_copy_from_linear_data(skb, copy_skb->data, len);
5685 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
5687 /* We'll reuse the original ring buffer. */
5691 if ((tp->dev->features & NETIF_F_RXCSUM) &&
5692 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
5693 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
5694 >> RXD_TCPCSUM_SHIFT) == 0xffff))
5695 skb->ip_summed = CHECKSUM_UNNECESSARY;
5697 skb_checksum_none_assert(skb);
5699 skb->protocol = eth_type_trans(skb, tp->dev);
5701 if (len > (tp->dev->mtu + ETH_HLEN) &&
5702 skb->protocol != htons(ETH_P_8021Q)) {
5704 goto drop_it_no_recycle;
5707 if (desc->type_flags & RXD_FLAG_VLAN &&
5708 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
5709 __vlan_hwaccel_put_tag(skb,
5710 desc->err_vlan & RXD_VLAN_MASK);
5712 napi_gro_receive(&tnapi->napi, skb);
5720 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
5721 tpr->rx_std_prod_idx = std_prod_idx &
5722 tp->rx_std_ring_mask;
5723 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5724 tpr->rx_std_prod_idx);
5725 work_mask &= ~RXD_OPAQUE_RING_STD;
5730 sw_idx &= tp->rx_ret_ring_mask;
5732 /* Refresh hw_idx to see if there is new work */
5733 if (sw_idx == hw_idx) {
5734 hw_idx = *(tnapi->rx_rcb_prod_idx);
5739 /* ACK the status ring. */
5740 tnapi->rx_rcb_ptr = sw_idx;
5741 tw32_rx_mbox(tnapi->consmbox, sw_idx);
5743 /* Refill RX ring(s). */
5744 if (!tg3_flag(tp, ENABLE_RSS)) {
5745 if (work_mask & RXD_OPAQUE_RING_STD) {
5746 tpr->rx_std_prod_idx = std_prod_idx &
5747 tp->rx_std_ring_mask;
5748 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5749 tpr->rx_std_prod_idx);
5751 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
5752 tpr->rx_jmb_prod_idx = jmb_prod_idx &
5753 tp->rx_jmb_ring_mask;
5754 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5755 tpr->rx_jmb_prod_idx);
5758 } else if (work_mask) {
5759 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
5760 * updated before the producer indices can be updated.
5764 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
5765 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
5767 if (tnapi != &tp->napi[1])
5768 napi_schedule(&tp->napi[1].napi);
5774 static void tg3_poll_link(struct tg3 *tp)
5776 /* handle link change and other phy events */
5777 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
5778 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
5780 if (sblk->status & SD_STATUS_LINK_CHG) {
5781 sblk->status = SD_STATUS_UPDATED |
5782 (sblk->status & ~SD_STATUS_LINK_CHG);
5783 spin_lock(&tp->lock);
5784 if (tg3_flag(tp, USE_PHYLIB)) {
5786 (MAC_STATUS_SYNC_CHANGED |
5787 MAC_STATUS_CFG_CHANGED |
5788 MAC_STATUS_MI_COMPLETION |
5789 MAC_STATUS_LNKSTATE_CHANGED));
5792 tg3_setup_phy(tp, 0);
5793 spin_unlock(&tp->lock);
5798 static int tg3_rx_prodring_xfer(struct tg3 *tp,
5799 struct tg3_rx_prodring_set *dpr,
5800 struct tg3_rx_prodring_set *spr)
5802 u32 si, di, cpycnt, src_prod_idx;
5806 src_prod_idx = spr->rx_std_prod_idx;
5808 /* Make sure updates to the rx_std_buffers[] entries and the
5809 * standard producer index are seen in the correct order.
5813 if (spr->rx_std_cons_idx == src_prod_idx)
5816 if (spr->rx_std_cons_idx < src_prod_idx)
5817 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
5819 cpycnt = tp->rx_std_ring_mask + 1 -
5820 spr->rx_std_cons_idx;
5822 cpycnt = min(cpycnt,
5823 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
5825 si = spr->rx_std_cons_idx;
5826 di = dpr->rx_std_prod_idx;
5828 for (i = di; i < di + cpycnt; i++) {
5829 if (dpr->rx_std_buffers[i].skb) {
5839 /* Ensure that updates to the rx_std_buffers ring and the
5840 * shadowed hardware producer ring from tg3_recycle_skb() are
5841 * ordered correctly WRT the skb check above.
5845 memcpy(&dpr->rx_std_buffers[di],
5846 &spr->rx_std_buffers[si],
5847 cpycnt * sizeof(struct ring_info));
5849 for (i = 0; i < cpycnt; i++, di++, si++) {
5850 struct tg3_rx_buffer_desc *sbd, *dbd;
5851 sbd = &spr->rx_std[si];
5852 dbd = &dpr->rx_std[di];
5853 dbd->addr_hi = sbd->addr_hi;
5854 dbd->addr_lo = sbd->addr_lo;
5857 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
5858 tp->rx_std_ring_mask;
5859 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
5860 tp->rx_std_ring_mask;
5864 src_prod_idx = spr->rx_jmb_prod_idx;
5866 /* Make sure updates to the rx_jmb_buffers[] entries and
5867 * the jumbo producer index are seen in the correct order.
5871 if (spr->rx_jmb_cons_idx == src_prod_idx)
5874 if (spr->rx_jmb_cons_idx < src_prod_idx)
5875 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5877 cpycnt = tp->rx_jmb_ring_mask + 1 -
5878 spr->rx_jmb_cons_idx;
5880 cpycnt = min(cpycnt,
5881 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5883 si = spr->rx_jmb_cons_idx;
5884 di = dpr->rx_jmb_prod_idx;
5886 for (i = di; i < di + cpycnt; i++) {
5887 if (dpr->rx_jmb_buffers[i].skb) {
5897 /* Ensure that updates to the rx_jmb_buffers ring and the
5898 * shadowed hardware producer ring from tg3_recycle_skb() are
5899 * ordered correctly WRT the skb check above.
5903 memcpy(&dpr->rx_jmb_buffers[di],
5904 &spr->rx_jmb_buffers[si],
5905 cpycnt * sizeof(struct ring_info));
5907 for (i = 0; i < cpycnt; i++, di++, si++) {
5908 struct tg3_rx_buffer_desc *sbd, *dbd;
5909 sbd = &spr->rx_jmb[si].std;
5910 dbd = &dpr->rx_jmb[di].std;
5911 dbd->addr_hi = sbd->addr_hi;
5912 dbd->addr_lo = sbd->addr_lo;
5915 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5916 tp->rx_jmb_ring_mask;
5917 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5918 tp->rx_jmb_ring_mask;
5924 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5926 struct tg3 *tp = tnapi->tp;
5928 /* run TX completion thread */
5929 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5931 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
5935 if (!tnapi->rx_rcb_prod_idx)
5938 /* run RX thread, within the bounds set by NAPI.
5939 * All RX "locking" is done by ensuring outside
5940 * code synchronizes with tg3->napi.poll()
5942 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5943 work_done += tg3_rx(tnapi, budget - work_done);
5945 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
5946 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5948 u32 std_prod_idx = dpr->rx_std_prod_idx;
5949 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5951 for (i = 1; i < tp->irq_cnt; i++)
5952 err |= tg3_rx_prodring_xfer(tp, dpr,
5953 &tp->napi[i].prodring);
5957 if (std_prod_idx != dpr->rx_std_prod_idx)
5958 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5959 dpr->rx_std_prod_idx);
5961 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5962 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5963 dpr->rx_jmb_prod_idx);
5968 tw32_f(HOSTCC_MODE, tp->coal_now);
5974 static inline void tg3_reset_task_schedule(struct tg3 *tp)
5976 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
5977 schedule_work(&tp->reset_task);
5980 static inline void tg3_reset_task_cancel(struct tg3 *tp)
5982 cancel_work_sync(&tp->reset_task);
5983 tg3_flag_clear(tp, RESET_TASK_PENDING);
5986 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5988 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5989 struct tg3 *tp = tnapi->tp;
5991 struct tg3_hw_status *sblk = tnapi->hw_status;
5994 work_done = tg3_poll_work(tnapi, work_done, budget);
5996 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
5999 if (unlikely(work_done >= budget))
6002 /* tp->last_tag is used in tg3_int_reenable() below
6003 * to tell the hw how much work has been processed,
6004 * so we must read it before checking for more work.
6006 tnapi->last_tag = sblk->status_tag;
6007 tnapi->last_irq_tag = tnapi->last_tag;
6010 /* check for RX/TX work to do */
6011 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
6012 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
6013 napi_complete(napi);
6014 /* Reenable interrupts. */
6015 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
6024 /* work_done is guaranteed to be less than budget. */
6025 napi_complete(napi);
6026 tg3_reset_task_schedule(tp);
6030 static void tg3_process_error(struct tg3 *tp)
6033 bool real_error = false;
6035 if (tg3_flag(tp, ERROR_PROCESSED))
6038 /* Check Flow Attention register */
6039 val = tr32(HOSTCC_FLOW_ATTN);
6040 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
6041 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
6045 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
6046 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
6050 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
6051 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
6060 tg3_flag_set(tp, ERROR_PROCESSED);
6061 tg3_reset_task_schedule(tp);
6064 static int tg3_poll(struct napi_struct *napi, int budget)
6066 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
6067 struct tg3 *tp = tnapi->tp;
6069 struct tg3_hw_status *sblk = tnapi->hw_status;
6072 if (sblk->status & SD_STATUS_ERROR)
6073 tg3_process_error(tp);
6077 work_done = tg3_poll_work(tnapi, work_done, budget);
6079 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6082 if (unlikely(work_done >= budget))
6085 if (tg3_flag(tp, TAGGED_STATUS)) {
6086 /* tp->last_tag is used in tg3_int_reenable() below
6087 * to tell the hw how much work has been processed,
6088 * so we must read it before checking for more work.
6090 tnapi->last_tag = sblk->status_tag;
6091 tnapi->last_irq_tag = tnapi->last_tag;
6094 sblk->status &= ~SD_STATUS_UPDATED;
6096 if (likely(!tg3_has_work(tnapi))) {
6097 napi_complete(napi);
6098 tg3_int_reenable(tnapi);
6106 /* work_done is guaranteed to be less than budget. */
6107 napi_complete(napi);
6108 tg3_reset_task_schedule(tp);
6112 static void tg3_napi_disable(struct tg3 *tp)
6116 for (i = tp->irq_cnt - 1; i >= 0; i--)
6117 napi_disable(&tp->napi[i].napi);
6120 static void tg3_napi_enable(struct tg3 *tp)
6124 for (i = 0; i < tp->irq_cnt; i++)
6125 napi_enable(&tp->napi[i].napi);
6128 static void tg3_napi_init(struct tg3 *tp)
6132 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
6133 for (i = 1; i < tp->irq_cnt; i++)
6134 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
6137 static void tg3_napi_fini(struct tg3 *tp)
6141 for (i = 0; i < tp->irq_cnt; i++)
6142 netif_napi_del(&tp->napi[i].napi);
6145 static inline void tg3_netif_stop(struct tg3 *tp)
6147 tp->dev->trans_start = jiffies; /* prevent tx timeout */
6148 tg3_napi_disable(tp);
6149 netif_tx_disable(tp->dev);
6152 static inline void tg3_netif_start(struct tg3 *tp)
6154 /* NOTE: unconditional netif_tx_wake_all_queues is only
6155 * appropriate so long as all callers are assured to
6156 * have free tx slots (such as after tg3_init_hw)
6158 netif_tx_wake_all_queues(tp->dev);
6160 tg3_napi_enable(tp);
6161 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
6162 tg3_enable_ints(tp);
6165 static void tg3_irq_quiesce(struct tg3 *tp)
6169 BUG_ON(tp->irq_sync);
6174 for (i = 0; i < tp->irq_cnt; i++)
6175 synchronize_irq(tp->napi[i].irq_vec);
6178 /* Fully shutdown all tg3 driver activity elsewhere in the system.
6179 * If irq_sync is non-zero, then the IRQ handler must be synchronized
6180 * with as well. Most of the time, this is not necessary except when
6181 * shutting down the device.
6183 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
6185 spin_lock_bh(&tp->lock);
6187 tg3_irq_quiesce(tp);
6190 static inline void tg3_full_unlock(struct tg3 *tp)
6192 spin_unlock_bh(&tp->lock);
6195 /* One-shot MSI handler - Chip automatically disables interrupt
6196 * after sending MSI so driver doesn't have to do it.
6198 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
6200 struct tg3_napi *tnapi = dev_id;
6201 struct tg3 *tp = tnapi->tp;
6203 prefetch(tnapi->hw_status);
6205 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6207 if (likely(!tg3_irq_sync(tp)))
6208 napi_schedule(&tnapi->napi);
6213 /* MSI ISR - No need to check for interrupt sharing and no need to
6214 * flush status block and interrupt mailbox. PCI ordering rules
6215 * guarantee that MSI will arrive after the status block.
6217 static irqreturn_t tg3_msi(int irq, void *dev_id)
6219 struct tg3_napi *tnapi = dev_id;
6220 struct tg3 *tp = tnapi->tp;
6222 prefetch(tnapi->hw_status);
6224 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6226 * Writing any value to intr-mbox-0 clears PCI INTA# and
6227 * chip-internal interrupt pending events.
6228 * Writing non-zero to intr-mbox-0 additional tells the
6229 * NIC to stop sending us irqs, engaging "in-intr-handler"
6232 tw32_mailbox(tnapi->int_mbox, 0x00000001);
6233 if (likely(!tg3_irq_sync(tp)))
6234 napi_schedule(&tnapi->napi);
6236 return IRQ_RETVAL(1);
6239 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
6241 struct tg3_napi *tnapi = dev_id;
6242 struct tg3 *tp = tnapi->tp;
6243 struct tg3_hw_status *sblk = tnapi->hw_status;
6244 unsigned int handled = 1;
6246 /* In INTx mode, it is possible for the interrupt to arrive at
6247 * the CPU before the status block posted prior to the interrupt.
6248 * Reading the PCI State register will confirm whether the
6249 * interrupt is ours and will flush the status block.
6251 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
6252 if (tg3_flag(tp, CHIP_RESETTING) ||
6253 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6260 * Writing any value to intr-mbox-0 clears PCI INTA# and
6261 * chip-internal interrupt pending events.
6262 * Writing non-zero to intr-mbox-0 additional tells the
6263 * NIC to stop sending us irqs, engaging "in-intr-handler"
6266 * Flush the mailbox to de-assert the IRQ immediately to prevent
6267 * spurious interrupts. The flush impacts performance but
6268 * excessive spurious interrupts can be worse in some cases.
6270 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
6271 if (tg3_irq_sync(tp))
6273 sblk->status &= ~SD_STATUS_UPDATED;
6274 if (likely(tg3_has_work(tnapi))) {
6275 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6276 napi_schedule(&tnapi->napi);
6278 /* No work, shared interrupt perhaps? re-enable
6279 * interrupts, and flush that PCI write
6281 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
6285 return IRQ_RETVAL(handled);
6288 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
6290 struct tg3_napi *tnapi = dev_id;
6291 struct tg3 *tp = tnapi->tp;
6292 struct tg3_hw_status *sblk = tnapi->hw_status;
6293 unsigned int handled = 1;
6295 /* In INTx mode, it is possible for the interrupt to arrive at
6296 * the CPU before the status block posted prior to the interrupt.
6297 * Reading the PCI State register will confirm whether the
6298 * interrupt is ours and will flush the status block.
6300 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
6301 if (tg3_flag(tp, CHIP_RESETTING) ||
6302 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6309 * writing any value to intr-mbox-0 clears PCI INTA# and
6310 * chip-internal interrupt pending events.
6311 * writing non-zero to intr-mbox-0 additional tells the
6312 * NIC to stop sending us irqs, engaging "in-intr-handler"
6315 * Flush the mailbox to de-assert the IRQ immediately to prevent
6316 * spurious interrupts. The flush impacts performance but
6317 * excessive spurious interrupts can be worse in some cases.
6319 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
6322 * In a shared interrupt configuration, sometimes other devices'
6323 * interrupts will scream. We record the current status tag here
6324 * so that the above check can report that the screaming interrupts
6325 * are unhandled. Eventually they will be silenced.
6327 tnapi->last_irq_tag = sblk->status_tag;
6329 if (tg3_irq_sync(tp))
6332 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6334 napi_schedule(&tnapi->napi);
6337 return IRQ_RETVAL(handled);
6340 /* ISR for interrupt test */
6341 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
6343 struct tg3_napi *tnapi = dev_id;
6344 struct tg3 *tp = tnapi->tp;
6345 struct tg3_hw_status *sblk = tnapi->hw_status;
6347 if ((sblk->status & SD_STATUS_UPDATED) ||
6348 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6349 tg3_disable_ints(tp);
6350 return IRQ_RETVAL(1);
6352 return IRQ_RETVAL(0);
6355 static int tg3_init_hw(struct tg3 *, int);
6356 static int tg3_halt(struct tg3 *, int, int);
6358 /* Restart hardware after configuration changes, self-test, etc.
6359 * Invoked with tp->lock held.
6361 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
6362 __releases(tp->lock)
6363 __acquires(tp->lock)
6367 err = tg3_init_hw(tp, reset_phy);
6370 "Failed to re-initialize device, aborting\n");
6371 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6372 tg3_full_unlock(tp);
6373 del_timer_sync(&tp->timer);
6375 tg3_napi_enable(tp);
6377 tg3_full_lock(tp, 0);
6382 #ifdef CONFIG_NET_POLL_CONTROLLER
6383 static void tg3_poll_controller(struct net_device *dev)
6386 struct tg3 *tp = netdev_priv(dev);
6388 if (tg3_irq_sync(tp))
6391 for (i = 0; i < tp->irq_cnt; i++)
6392 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
6396 static void tg3_reset_task(struct work_struct *work)
6398 struct tg3 *tp = container_of(work, struct tg3, reset_task);
6401 tg3_full_lock(tp, 0);
6403 if (!netif_running(tp->dev)) {
6404 tg3_flag_clear(tp, RESET_TASK_PENDING);
6405 tg3_full_unlock(tp);
6409 tg3_full_unlock(tp);
6415 tg3_full_lock(tp, 1);
6417 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
6418 tp->write32_tx_mbox = tg3_write32_tx_mbox;
6419 tp->write32_rx_mbox = tg3_write_flush_reg32;
6420 tg3_flag_set(tp, MBOX_WRITE_REORDER);
6421 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
6424 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
6425 err = tg3_init_hw(tp, 1);
6429 tg3_netif_start(tp);
6432 tg3_full_unlock(tp);
6437 tg3_flag_clear(tp, RESET_TASK_PENDING);
6440 static void tg3_tx_timeout(struct net_device *dev)
6442 struct tg3 *tp = netdev_priv(dev);
6444 if (netif_msg_tx_err(tp)) {
6445 netdev_err(dev, "transmit timed out, resetting\n");
6449 tg3_reset_task_schedule(tp);
6452 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
6453 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
6455 u32 base = (u32) mapping & 0xffffffff;
6457 return (base > 0xffffdcc0) && (base + len + 8 < base);
6460 /* Test for DMA addresses > 40-bit */
6461 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
6464 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6465 if (tg3_flag(tp, 40BIT_DMA_BUG))
6466 return ((u64) mapping + len) > DMA_BIT_MASK(40);
6473 static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
6474 dma_addr_t mapping, u32 len, u32 flags,
6477 txbd->addr_hi = ((u64) mapping >> 32);
6478 txbd->addr_lo = ((u64) mapping & 0xffffffff);
6479 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
6480 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
6483 static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
6484 dma_addr_t map, u32 len, u32 flags,
6487 struct tg3 *tp = tnapi->tp;
6490 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
6493 if (tg3_4g_overflow_test(map, len))
6496 if (tg3_40bit_overflow_test(tp, map, len))
6499 if (tg3_flag(tp, 4K_FIFO_LIMIT)) {
6500 u32 prvidx = *entry;
6501 u32 tmp_flag = flags & ~TXD_FLAG_END;
6502 while (len > TG3_TX_BD_DMA_MAX && *budget) {
6503 u32 frag_len = TG3_TX_BD_DMA_MAX;
6504 len -= TG3_TX_BD_DMA_MAX;
6506 /* Avoid the 8byte DMA problem */
6508 len += TG3_TX_BD_DMA_MAX / 2;
6509 frag_len = TG3_TX_BD_DMA_MAX / 2;
6512 tnapi->tx_buffers[*entry].fragmented = true;
6514 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6515 frag_len, tmp_flag, mss, vlan);
6518 *entry = NEXT_TX(*entry);
6525 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6526 len, flags, mss, vlan);
6528 *entry = NEXT_TX(*entry);
6531 tnapi->tx_buffers[prvidx].fragmented = false;
6535 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6536 len, flags, mss, vlan);
6537 *entry = NEXT_TX(*entry);
6543 static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
6546 struct sk_buff *skb;
6547 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
6552 pci_unmap_single(tnapi->tp->pdev,
6553 dma_unmap_addr(txb, mapping),
6557 while (txb->fragmented) {
6558 txb->fragmented = false;
6559 entry = NEXT_TX(entry);
6560 txb = &tnapi->tx_buffers[entry];
6563 for (i = 0; i <= last; i++) {
6564 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6566 entry = NEXT_TX(entry);
6567 txb = &tnapi->tx_buffers[entry];
6569 pci_unmap_page(tnapi->tp->pdev,
6570 dma_unmap_addr(txb, mapping),
6571 skb_frag_size(frag), PCI_DMA_TODEVICE);
6573 while (txb->fragmented) {
6574 txb->fragmented = false;
6575 entry = NEXT_TX(entry);
6576 txb = &tnapi->tx_buffers[entry];
6581 /* Workaround 4GB and 40-bit hardware DMA bugs. */
6582 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
6583 struct sk_buff **pskb,
6584 u32 *entry, u32 *budget,
6585 u32 base_flags, u32 mss, u32 vlan)
6587 struct tg3 *tp = tnapi->tp;
6588 struct sk_buff *new_skb, *skb = *pskb;
6589 dma_addr_t new_addr = 0;
6592 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
6593 new_skb = skb_copy(skb, GFP_ATOMIC);
6595 int more_headroom = 4 - ((unsigned long)skb->data & 3);
6597 new_skb = skb_copy_expand(skb,
6598 skb_headroom(skb) + more_headroom,
6599 skb_tailroom(skb), GFP_ATOMIC);
6605 /* New SKB is guaranteed to be linear. */
6606 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
6608 /* Make sure the mapping succeeded */
6609 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
6610 dev_kfree_skb(new_skb);
6613 u32 save_entry = *entry;
6615 base_flags |= TXD_FLAG_END;
6617 tnapi->tx_buffers[*entry].skb = new_skb;
6618 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
6621 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
6622 new_skb->len, base_flags,
6624 tg3_tx_skb_unmap(tnapi, save_entry, -1);
6625 dev_kfree_skb(new_skb);
6636 static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
6638 /* Use GSO to workaround a rare TSO bug that may be triggered when the
6639 * TSO header is greater than 80 bytes.
6641 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
6643 struct sk_buff *segs, *nskb;
6644 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
6646 /* Estimate the number of fragments in the worst case */
6647 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
6648 netif_stop_queue(tp->dev);
6650 /* netif_tx_stop_queue() must be done before checking
6651 * checking tx index in tg3_tx_avail() below, because in
6652 * tg3_tx(), we update tx index before checking for
6653 * netif_tx_queue_stopped().
6656 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
6657 return NETDEV_TX_BUSY;
6659 netif_wake_queue(tp->dev);
6662 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
6664 goto tg3_tso_bug_end;
6670 tg3_start_xmit(nskb, tp->dev);
6676 return NETDEV_TX_OK;
6679 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
6680 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
6682 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
6684 struct tg3 *tp = netdev_priv(dev);
6685 u32 len, entry, base_flags, mss, vlan = 0;
6687 int i = -1, would_hit_hwbug;
6689 struct tg3_napi *tnapi;
6690 struct netdev_queue *txq;
6693 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
6694 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
6695 if (tg3_flag(tp, ENABLE_TSS))
6698 budget = tg3_tx_avail(tnapi);
6700 /* We are running in BH disabled context with netif_tx_lock
6701 * and TX reclaim runs via tp->napi.poll inside of a software
6702 * interrupt. Furthermore, IRQ processing runs lockless so we have
6703 * no IRQ context deadlocks to worry about either. Rejoice!
6705 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
6706 if (!netif_tx_queue_stopped(txq)) {
6707 netif_tx_stop_queue(txq);
6709 /* This is a hard error, log it. */
6711 "BUG! Tx Ring full when queue awake!\n");
6713 return NETDEV_TX_BUSY;
6716 entry = tnapi->tx_prod;
6718 if (skb->ip_summed == CHECKSUM_PARTIAL)
6719 base_flags |= TXD_FLAG_TCPUDP_CSUM;
6721 mss = skb_shinfo(skb)->gso_size;
6724 u32 tcp_opt_len, hdr_len;
6726 if (skb_header_cloned(skb) &&
6727 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6731 tcp_opt_len = tcp_optlen(skb);
6733 if (skb_is_gso_v6(skb)) {
6734 hdr_len = skb_headlen(skb) - ETH_HLEN;
6738 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
6739 hdr_len = ip_tcp_len + tcp_opt_len;
6742 iph->tot_len = htons(mss + hdr_len);
6745 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
6746 tg3_flag(tp, TSO_BUG))
6747 return tg3_tso_bug(tp, skb);
6749 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
6750 TXD_FLAG_CPU_POST_DMA);
6752 if (tg3_flag(tp, HW_TSO_1) ||
6753 tg3_flag(tp, HW_TSO_2) ||
6754 tg3_flag(tp, HW_TSO_3)) {
6755 tcp_hdr(skb)->check = 0;
6756 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
6758 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6763 if (tg3_flag(tp, HW_TSO_3)) {
6764 mss |= (hdr_len & 0xc) << 12;
6766 base_flags |= 0x00000010;
6767 base_flags |= (hdr_len & 0x3e0) << 5;
6768 } else if (tg3_flag(tp, HW_TSO_2))
6769 mss |= hdr_len << 9;
6770 else if (tg3_flag(tp, HW_TSO_1) ||
6771 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6772 if (tcp_opt_len || iph->ihl > 5) {
6775 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
6776 mss |= (tsflags << 11);
6779 if (tcp_opt_len || iph->ihl > 5) {
6782 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
6783 base_flags |= tsflags << 12;
6788 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
6789 !mss && skb->len > VLAN_ETH_FRAME_LEN)
6790 base_flags |= TXD_FLAG_JMB_PKT;
6792 if (vlan_tx_tag_present(skb)) {
6793 base_flags |= TXD_FLAG_VLAN;
6794 vlan = vlan_tx_tag_get(skb);
6797 len = skb_headlen(skb);
6799 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6800 if (pci_dma_mapping_error(tp->pdev, mapping))
6804 tnapi->tx_buffers[entry].skb = skb;
6805 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
6807 would_hit_hwbug = 0;
6809 if (tg3_flag(tp, 5701_DMA_BUG))
6810 would_hit_hwbug = 1;
6812 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
6813 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
6815 would_hit_hwbug = 1;
6816 /* Now loop through additional data fragments, and queue them. */
6817 } else if (skb_shinfo(skb)->nr_frags > 0) {
6820 if (!tg3_flag(tp, HW_TSO_1) &&
6821 !tg3_flag(tp, HW_TSO_2) &&
6822 !tg3_flag(tp, HW_TSO_3))
6825 last = skb_shinfo(skb)->nr_frags - 1;
6826 for (i = 0; i <= last; i++) {
6827 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6829 len = skb_frag_size(frag);
6830 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
6831 len, DMA_TO_DEVICE);
6833 tnapi->tx_buffers[entry].skb = NULL;
6834 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
6836 if (dma_mapping_error(&tp->pdev->dev, mapping))
6840 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
6842 ((i == last) ? TXD_FLAG_END : 0),
6844 would_hit_hwbug = 1;
6850 if (would_hit_hwbug) {
6851 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
6853 /* If the workaround fails due to memory/mapping
6854 * failure, silently drop this packet.
6856 entry = tnapi->tx_prod;
6857 budget = tg3_tx_avail(tnapi);
6858 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
6859 base_flags, mss, vlan))
6863 skb_tx_timestamp(skb);
6865 /* Packets are ready, update Tx producer idx local and on card. */
6866 tw32_tx_mbox(tnapi->prodmbox, entry);
6868 tnapi->tx_prod = entry;
6869 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
6870 netif_tx_stop_queue(txq);
6872 /* netif_tx_stop_queue() must be done before checking
6873 * checking tx index in tg3_tx_avail() below, because in
6874 * tg3_tx(), we update tx index before checking for
6875 * netif_tx_queue_stopped().
6878 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
6879 netif_tx_wake_queue(txq);
6883 return NETDEV_TX_OK;
6886 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
6887 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
6892 return NETDEV_TX_OK;
6895 static void tg3_mac_loopback(struct tg3 *tp, bool enable)
6898 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
6899 MAC_MODE_PORT_MODE_MASK);
6901 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
6903 if (!tg3_flag(tp, 5705_PLUS))
6904 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
6906 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
6907 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
6909 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
6911 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
6913 if (tg3_flag(tp, 5705_PLUS) ||
6914 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
6915 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
6916 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
6919 tw32(MAC_MODE, tp->mac_mode);
6923 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
6925 u32 val, bmcr, mac_mode, ptest = 0;
6927 tg3_phy_toggle_apd(tp, false);
6928 tg3_phy_toggle_automdix(tp, 0);
6930 if (extlpbk && tg3_phy_set_extloopbk(tp))
6933 bmcr = BMCR_FULLDPLX;
6938 bmcr |= BMCR_SPEED100;
6942 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
6944 bmcr |= BMCR_SPEED100;
6947 bmcr |= BMCR_SPEED1000;
6952 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
6953 tg3_readphy(tp, MII_CTRL1000, &val);
6954 val |= CTL1000_AS_MASTER |
6955 CTL1000_ENABLE_MASTER;
6956 tg3_writephy(tp, MII_CTRL1000, val);
6958 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
6959 MII_TG3_FET_PTEST_TRIM_2;
6960 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
6963 bmcr |= BMCR_LOOPBACK;
6965 tg3_writephy(tp, MII_BMCR, bmcr);
6967 /* The write needs to be flushed for the FETs */
6968 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
6969 tg3_readphy(tp, MII_BMCR, &bmcr);
6973 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
6974 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
6975 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
6976 MII_TG3_FET_PTEST_FRC_TX_LINK |
6977 MII_TG3_FET_PTEST_FRC_TX_LOCK);
6979 /* The write needs to be flushed for the AC131 */
6980 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
6983 /* Reset to prevent losing 1st rx packet intermittently */
6984 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
6985 tg3_flag(tp, 5780_CLASS)) {
6986 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6988 tw32_f(MAC_RX_MODE, tp->rx_mode);
6991 mac_mode = tp->mac_mode &
6992 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
6993 if (speed == SPEED_1000)
6994 mac_mode |= MAC_MODE_PORT_MODE_GMII;
6996 mac_mode |= MAC_MODE_PORT_MODE_MII;
6998 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
6999 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
7001 if (masked_phy_id == TG3_PHY_ID_BCM5401)
7002 mac_mode &= ~MAC_MODE_LINK_POLARITY;
7003 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
7004 mac_mode |= MAC_MODE_LINK_POLARITY;
7006 tg3_writephy(tp, MII_TG3_EXT_CTRL,
7007 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
7010 tw32(MAC_MODE, mac_mode);
7016 static void tg3_set_loopback(struct net_device *dev, u32 features)
7018 struct tg3 *tp = netdev_priv(dev);
7020 if (features & NETIF_F_LOOPBACK) {
7021 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
7024 spin_lock_bh(&tp->lock);
7025 tg3_mac_loopback(tp, true);
7026 netif_carrier_on(tp->dev);
7027 spin_unlock_bh(&tp->lock);
7028 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
7030 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
7033 spin_lock_bh(&tp->lock);
7034 tg3_mac_loopback(tp, false);
7035 /* Force link status check */
7036 tg3_setup_phy(tp, 1);
7037 spin_unlock_bh(&tp->lock);
7038 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
7042 static u32 tg3_fix_features(struct net_device *dev, u32 features)
7044 struct tg3 *tp = netdev_priv(dev);
7046 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
7047 features &= ~NETIF_F_ALL_TSO;
7052 static int tg3_set_features(struct net_device *dev, u32 features)
7054 u32 changed = dev->features ^ features;
7056 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
7057 tg3_set_loopback(dev, features);
7062 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
7067 if (new_mtu > ETH_DATA_LEN) {
7068 if (tg3_flag(tp, 5780_CLASS)) {
7069 netdev_update_features(dev);
7070 tg3_flag_clear(tp, TSO_CAPABLE);
7072 tg3_flag_set(tp, JUMBO_RING_ENABLE);
7075 if (tg3_flag(tp, 5780_CLASS)) {
7076 tg3_flag_set(tp, TSO_CAPABLE);
7077 netdev_update_features(dev);
7079 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
7083 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
7085 struct tg3 *tp = netdev_priv(dev);
7088 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
7091 if (!netif_running(dev)) {
7092 /* We'll just catch it later when the
7095 tg3_set_mtu(dev, tp, new_mtu);
7103 tg3_full_lock(tp, 1);
7105 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7107 tg3_set_mtu(dev, tp, new_mtu);
7109 err = tg3_restart_hw(tp, 0);
7112 tg3_netif_start(tp);
7114 tg3_full_unlock(tp);
7122 static void tg3_rx_prodring_free(struct tg3 *tp,
7123 struct tg3_rx_prodring_set *tpr)
7127 if (tpr != &tp->napi[0].prodring) {
7128 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
7129 i = (i + 1) & tp->rx_std_ring_mask)
7130 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
7133 if (tg3_flag(tp, JUMBO_CAPABLE)) {
7134 for (i = tpr->rx_jmb_cons_idx;
7135 i != tpr->rx_jmb_prod_idx;
7136 i = (i + 1) & tp->rx_jmb_ring_mask) {
7137 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
7145 for (i = 0; i <= tp->rx_std_ring_mask; i++)
7146 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
7149 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
7150 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
7151 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
7156 /* Initialize rx rings for packet processing.
7158 * The chip has been shut down and the driver detached from
7159 * the networking, so no interrupts or new tx packets will
7160 * end up in the driver. tp->{tx,}lock are held and thus
7163 static int tg3_rx_prodring_alloc(struct tg3 *tp,
7164 struct tg3_rx_prodring_set *tpr)
7166 u32 i, rx_pkt_dma_sz;
7168 tpr->rx_std_cons_idx = 0;
7169 tpr->rx_std_prod_idx = 0;
7170 tpr->rx_jmb_cons_idx = 0;
7171 tpr->rx_jmb_prod_idx = 0;
7173 if (tpr != &tp->napi[0].prodring) {
7174 memset(&tpr->rx_std_buffers[0], 0,
7175 TG3_RX_STD_BUFF_RING_SIZE(tp));
7176 if (tpr->rx_jmb_buffers)
7177 memset(&tpr->rx_jmb_buffers[0], 0,
7178 TG3_RX_JMB_BUFF_RING_SIZE(tp));
7182 /* Zero out all descriptors. */
7183 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
7185 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
7186 if (tg3_flag(tp, 5780_CLASS) &&
7187 tp->dev->mtu > ETH_DATA_LEN)
7188 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
7189 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7191 /* Initialize invariants of the rings, we only set this
7192 * stuff once. This works because the card does not
7193 * write into the rx buffer posting rings.
7195 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
7196 struct tg3_rx_buffer_desc *rxd;
7198 rxd = &tpr->rx_std[i];
7199 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
7200 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
7201 rxd->opaque = (RXD_OPAQUE_RING_STD |
7202 (i << RXD_OPAQUE_INDEX_SHIFT));
7205 /* Now allocate fresh SKBs for each rx ring. */
7206 for (i = 0; i < tp->rx_pending; i++) {
7207 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
7208 netdev_warn(tp->dev,
7209 "Using a smaller RX standard ring. Only "
7210 "%d out of %d buffers were allocated "
7211 "successfully\n", i, tp->rx_pending);
7219 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
7222 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
7224 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
7227 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
7228 struct tg3_rx_buffer_desc *rxd;
7230 rxd = &tpr->rx_jmb[i].std;
7231 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
7232 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
7234 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
7235 (i << RXD_OPAQUE_INDEX_SHIFT));
7238 for (i = 0; i < tp->rx_jumbo_pending; i++) {
7239 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
7240 netdev_warn(tp->dev,
7241 "Using a smaller RX jumbo ring. Only %d "
7242 "out of %d buffers were allocated "
7243 "successfully\n", i, tp->rx_jumbo_pending);
7246 tp->rx_jumbo_pending = i;
7255 tg3_rx_prodring_free(tp, tpr);
7259 static void tg3_rx_prodring_fini(struct tg3 *tp,
7260 struct tg3_rx_prodring_set *tpr)
7262 kfree(tpr->rx_std_buffers);
7263 tpr->rx_std_buffers = NULL;
7264 kfree(tpr->rx_jmb_buffers);
7265 tpr->rx_jmb_buffers = NULL;
7267 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
7268 tpr->rx_std, tpr->rx_std_mapping);
7272 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
7273 tpr->rx_jmb, tpr->rx_jmb_mapping);
7278 static int tg3_rx_prodring_init(struct tg3 *tp,
7279 struct tg3_rx_prodring_set *tpr)
7281 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
7283 if (!tpr->rx_std_buffers)
7286 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
7287 TG3_RX_STD_RING_BYTES(tp),
7288 &tpr->rx_std_mapping,
7293 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
7294 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
7296 if (!tpr->rx_jmb_buffers)
7299 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
7300 TG3_RX_JMB_RING_BYTES(tp),
7301 &tpr->rx_jmb_mapping,
7310 tg3_rx_prodring_fini(tp, tpr);
7314 /* Free up pending packets in all rx/tx rings.
7316 * The chip has been shut down and the driver detached from
7317 * the networking, so no interrupts or new tx packets will
7318 * end up in the driver. tp->{tx,}lock is not held and we are not
7319 * in an interrupt context and thus may sleep.
7321 static void tg3_free_rings(struct tg3 *tp)
7325 for (j = 0; j < tp->irq_cnt; j++) {
7326 struct tg3_napi *tnapi = &tp->napi[j];
7328 tg3_rx_prodring_free(tp, &tnapi->prodring);
7330 if (!tnapi->tx_buffers)
7333 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
7334 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
7339 tg3_tx_skb_unmap(tnapi, i,
7340 skb_shinfo(skb)->nr_frags - 1);
7342 dev_kfree_skb_any(skb);
7347 /* Initialize tx/rx rings for packet processing.
7349 * The chip has been shut down and the driver detached from
7350 * the networking, so no interrupts or new tx packets will
7351 * end up in the driver. tp->{tx,}lock are held and thus
7354 static int tg3_init_rings(struct tg3 *tp)
7358 /* Free up all the SKBs. */
7361 for (i = 0; i < tp->irq_cnt; i++) {
7362 struct tg3_napi *tnapi = &tp->napi[i];
7364 tnapi->last_tag = 0;
7365 tnapi->last_irq_tag = 0;
7366 tnapi->hw_status->status = 0;
7367 tnapi->hw_status->status_tag = 0;
7368 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7373 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
7375 tnapi->rx_rcb_ptr = 0;
7377 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
7379 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
7389 * Must not be invoked with interrupt sources disabled and
7390 * the hardware shutdown down.
7392 static void tg3_free_consistent(struct tg3 *tp)
7396 for (i = 0; i < tp->irq_cnt; i++) {
7397 struct tg3_napi *tnapi = &tp->napi[i];
7399 if (tnapi->tx_ring) {
7400 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
7401 tnapi->tx_ring, tnapi->tx_desc_mapping);
7402 tnapi->tx_ring = NULL;
7405 kfree(tnapi->tx_buffers);
7406 tnapi->tx_buffers = NULL;
7408 if (tnapi->rx_rcb) {
7409 dma_free_coherent(&tp->pdev->dev,
7410 TG3_RX_RCB_RING_BYTES(tp),
7412 tnapi->rx_rcb_mapping);
7413 tnapi->rx_rcb = NULL;
7416 tg3_rx_prodring_fini(tp, &tnapi->prodring);
7418 if (tnapi->hw_status) {
7419 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
7421 tnapi->status_mapping);
7422 tnapi->hw_status = NULL;
7427 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
7428 tp->hw_stats, tp->stats_mapping);
7429 tp->hw_stats = NULL;
7434 * Must not be invoked with interrupt sources disabled and
7435 * the hardware shutdown down. Can sleep.
7437 static int tg3_alloc_consistent(struct tg3 *tp)
7441 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
7442 sizeof(struct tg3_hw_stats),
7448 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
7450 for (i = 0; i < tp->irq_cnt; i++) {
7451 struct tg3_napi *tnapi = &tp->napi[i];
7452 struct tg3_hw_status *sblk;
7454 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
7456 &tnapi->status_mapping,
7458 if (!tnapi->hw_status)
7461 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7462 sblk = tnapi->hw_status;
7464 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
7467 /* If multivector TSS is enabled, vector 0 does not handle
7468 * tx interrupts. Don't allocate any resources for it.
7470 if ((!i && !tg3_flag(tp, ENABLE_TSS)) ||
7471 (i && tg3_flag(tp, ENABLE_TSS))) {
7472 tnapi->tx_buffers = kzalloc(
7473 sizeof(struct tg3_tx_ring_info) *
7474 TG3_TX_RING_SIZE, GFP_KERNEL);
7475 if (!tnapi->tx_buffers)
7478 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
7480 &tnapi->tx_desc_mapping,
7482 if (!tnapi->tx_ring)
7487 * When RSS is enabled, the status block format changes
7488 * slightly. The "rx_jumbo_consumer", "reserved",
7489 * and "rx_mini_consumer" members get mapped to the
7490 * other three rx return ring producer indexes.
7494 if (tg3_flag(tp, ENABLE_RSS)) {
7495 tnapi->rx_rcb_prod_idx = NULL;
7500 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
7503 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
7506 tnapi->rx_rcb_prod_idx = &sblk->reserved;
7509 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
7514 * If multivector RSS is enabled, vector 0 does not handle
7515 * rx or tx interrupts. Don't allocate any resources for it.
7517 if (!i && tg3_flag(tp, ENABLE_RSS))
7520 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
7521 TG3_RX_RCB_RING_BYTES(tp),
7522 &tnapi->rx_rcb_mapping,
7527 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
7533 tg3_free_consistent(tp);
7537 #define MAX_WAIT_CNT 1000
7539 /* To stop a block, clear the enable bit and poll till it
7540 * clears. tp->lock is held.
7542 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
7547 if (tg3_flag(tp, 5705_PLUS)) {
7554 /* We can't enable/disable these bits of the
7555 * 5705/5750, just say success.
7568 for (i = 0; i < MAX_WAIT_CNT; i++) {
7571 if ((val & enable_bit) == 0)
7575 if (i == MAX_WAIT_CNT && !silent) {
7576 dev_err(&tp->pdev->dev,
7577 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
7585 /* tp->lock is held. */
7586 static int tg3_abort_hw(struct tg3 *tp, int silent)
7590 tg3_disable_ints(tp);
7592 tp->rx_mode &= ~RX_MODE_ENABLE;
7593 tw32_f(MAC_RX_MODE, tp->rx_mode);
7596 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
7597 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
7598 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
7599 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
7600 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
7601 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
7603 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
7604 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
7605 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
7606 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
7607 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
7608 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
7609 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
7611 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
7612 tw32_f(MAC_MODE, tp->mac_mode);
7615 tp->tx_mode &= ~TX_MODE_ENABLE;
7616 tw32_f(MAC_TX_MODE, tp->tx_mode);
7618 for (i = 0; i < MAX_WAIT_CNT; i++) {
7620 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
7623 if (i >= MAX_WAIT_CNT) {
7624 dev_err(&tp->pdev->dev,
7625 "%s timed out, TX_MODE_ENABLE will not clear "
7626 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
7630 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
7631 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
7632 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
7634 tw32(FTQ_RESET, 0xffffffff);
7635 tw32(FTQ_RESET, 0x00000000);
7637 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
7638 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
7640 for (i = 0; i < tp->irq_cnt; i++) {
7641 struct tg3_napi *tnapi = &tp->napi[i];
7642 if (tnapi->hw_status)
7643 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7646 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
7651 /* Save PCI command register before chip reset */
7652 static void tg3_save_pci_state(struct tg3 *tp)
7654 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
7657 /* Restore PCI state after chip reset */
7658 static void tg3_restore_pci_state(struct tg3 *tp)
7662 /* Re-enable indirect register accesses. */
7663 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
7664 tp->misc_host_ctrl);
7666 /* Set MAX PCI retry to zero. */
7667 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
7668 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7669 tg3_flag(tp, PCIX_MODE))
7670 val |= PCISTATE_RETRY_SAME_DMA;
7671 /* Allow reads and writes to the APE register and memory space. */
7672 if (tg3_flag(tp, ENABLE_APE))
7673 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7674 PCISTATE_ALLOW_APE_SHMEM_WR |
7675 PCISTATE_ALLOW_APE_PSPACE_WR;
7676 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
7678 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
7680 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
7681 if (tg3_flag(tp, PCI_EXPRESS))
7682 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
7684 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
7685 tp->pci_cacheline_sz);
7686 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
7691 /* Make sure PCI-X relaxed ordering bit is clear. */
7692 if (tg3_flag(tp, PCIX_MODE)) {
7695 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7697 pcix_cmd &= ~PCI_X_CMD_ERO;
7698 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7702 if (tg3_flag(tp, 5780_CLASS)) {
7704 /* Chip reset on 5780 will reset MSI enable bit,
7705 * so need to restore it.
7707 if (tg3_flag(tp, USING_MSI)) {
7710 pci_read_config_word(tp->pdev,
7711 tp->msi_cap + PCI_MSI_FLAGS,
7713 pci_write_config_word(tp->pdev,
7714 tp->msi_cap + PCI_MSI_FLAGS,
7715 ctrl | PCI_MSI_FLAGS_ENABLE);
7716 val = tr32(MSGINT_MODE);
7717 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7722 /* tp->lock is held. */
7723 static int tg3_chip_reset(struct tg3 *tp)
7726 void (*write_op)(struct tg3 *, u32, u32);
7731 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7733 /* No matching tg3_nvram_unlock() after this because
7734 * chip reset below will undo the nvram lock.
7736 tp->nvram_lock_cnt = 0;
7738 /* GRC_MISC_CFG core clock reset will clear the memory
7739 * enable bit in PCI register 4 and the MSI enable bit
7740 * on some chips, so we save relevant registers here.
7742 tg3_save_pci_state(tp);
7744 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
7745 tg3_flag(tp, 5755_PLUS))
7746 tw32(GRC_FASTBOOT_PC, 0);
7749 * We must avoid the readl() that normally takes place.
7750 * It locks machines, causes machine checks, and other
7751 * fun things. So, temporarily disable the 5701
7752 * hardware workaround, while we do the reset.
7754 write_op = tp->write32;
7755 if (write_op == tg3_write_flush_reg32)
7756 tp->write32 = tg3_write32;
7758 /* Prevent the irq handler from reading or writing PCI registers
7759 * during chip reset when the memory enable bit in the PCI command
7760 * register may be cleared. The chip does not generate interrupt
7761 * at this time, but the irq handler may still be called due to irq
7762 * sharing or irqpoll.
7764 tg3_flag_set(tp, CHIP_RESETTING);
7765 for (i = 0; i < tp->irq_cnt; i++) {
7766 struct tg3_napi *tnapi = &tp->napi[i];
7767 if (tnapi->hw_status) {
7768 tnapi->hw_status->status = 0;
7769 tnapi->hw_status->status_tag = 0;
7771 tnapi->last_tag = 0;
7772 tnapi->last_irq_tag = 0;
7776 for (i = 0; i < tp->irq_cnt; i++)
7777 synchronize_irq(tp->napi[i].irq_vec);
7779 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7780 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7781 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7785 val = GRC_MISC_CFG_CORECLK_RESET;
7787 if (tg3_flag(tp, PCI_EXPRESS)) {
7788 /* Force PCIe 1.0a mode */
7789 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7790 !tg3_flag(tp, 57765_PLUS) &&
7791 tr32(TG3_PCIE_PHY_TSTCTL) ==
7792 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7793 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7795 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7796 tw32(GRC_MISC_CFG, (1 << 29));
7801 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7802 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7803 tw32(GRC_VCPU_EXT_CTRL,
7804 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7807 /* Manage gphy power for all CPMU absent PCIe devices. */
7808 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
7809 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
7811 tw32(GRC_MISC_CFG, val);
7813 /* restore 5701 hardware bug workaround write method */
7814 tp->write32 = write_op;
7816 /* Unfortunately, we have to delay before the PCI read back.
7817 * Some 575X chips even will not respond to a PCI cfg access
7818 * when the reset command is given to the chip.
7820 * How do these hardware designers expect things to work
7821 * properly if the PCI write is posted for a long period
7822 * of time? It is always necessary to have some method by
7823 * which a register read back can occur to push the write
7824 * out which does the reset.
7826 * For most tg3 variants the trick below was working.
7831 /* Flush PCI posted writes. The normal MMIO registers
7832 * are inaccessible at this time so this is the only
7833 * way to make this reliably (actually, this is no longer
7834 * the case, see above). I tried to use indirect
7835 * register read/write but this upset some 5701 variants.
7837 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7841 if (tg3_flag(tp, PCI_EXPRESS) && pci_pcie_cap(tp->pdev)) {
7844 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7848 /* Wait for link training to complete. */
7849 for (i = 0; i < 5000; i++)
7852 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7853 pci_write_config_dword(tp->pdev, 0xc4,
7854 cfg_val | (1 << 15));
7857 /* Clear the "no snoop" and "relaxed ordering" bits. */
7858 pci_read_config_word(tp->pdev,
7859 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
7861 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7862 PCI_EXP_DEVCTL_NOSNOOP_EN);
7864 * Older PCIe devices only support the 128 byte
7865 * MPS setting. Enforce the restriction.
7867 if (!tg3_flag(tp, CPMU_PRESENT))
7868 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7869 pci_write_config_word(tp->pdev,
7870 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
7873 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
7875 /* Clear error status */
7876 pci_write_config_word(tp->pdev,
7877 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVSTA,
7878 PCI_EXP_DEVSTA_CED |
7879 PCI_EXP_DEVSTA_NFED |
7880 PCI_EXP_DEVSTA_FED |
7881 PCI_EXP_DEVSTA_URD);
7884 tg3_restore_pci_state(tp);
7886 tg3_flag_clear(tp, CHIP_RESETTING);
7887 tg3_flag_clear(tp, ERROR_PROCESSED);
7890 if (tg3_flag(tp, 5780_CLASS))
7891 val = tr32(MEMARB_MODE);
7892 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7894 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7896 tw32(0x5000, 0x400);
7899 tw32(GRC_MODE, tp->grc_mode);
7901 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7904 tw32(0xc4, val | (1 << 15));
7907 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7908 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7909 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7910 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7911 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7912 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7915 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7916 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7918 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7919 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7924 tw32_f(MAC_MODE, val);
7927 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7929 err = tg3_poll_fw(tp);
7935 if (tg3_flag(tp, PCI_EXPRESS) &&
7936 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7937 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7938 !tg3_flag(tp, 57765_PLUS)) {
7941 tw32(0x7c00, val | (1 << 25));
7944 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
7945 val = tr32(TG3_CPMU_CLCK_ORIDE);
7946 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
7949 /* Reprobe ASF enable state. */
7950 tg3_flag_clear(tp, ENABLE_ASF);
7951 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
7952 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7953 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7956 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7957 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7958 tg3_flag_set(tp, ENABLE_ASF);
7959 tp->last_event_jiffies = jiffies;
7960 if (tg3_flag(tp, 5750_PLUS))
7961 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
7968 /* tp->lock is held. */
7969 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7975 tg3_write_sig_pre_reset(tp, kind);
7977 tg3_abort_hw(tp, silent);
7978 err = tg3_chip_reset(tp);
7980 __tg3_set_mac_addr(tp, 0);
7982 tg3_write_sig_legacy(tp, kind);
7983 tg3_write_sig_post_reset(tp, kind);
7991 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7993 struct tg3 *tp = netdev_priv(dev);
7994 struct sockaddr *addr = p;
7995 int err = 0, skip_mac_1 = 0;
7997 if (!is_valid_ether_addr(addr->sa_data))
8000 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
8002 if (!netif_running(dev))
8005 if (tg3_flag(tp, ENABLE_ASF)) {
8006 u32 addr0_high, addr0_low, addr1_high, addr1_low;
8008 addr0_high = tr32(MAC_ADDR_0_HIGH);
8009 addr0_low = tr32(MAC_ADDR_0_LOW);
8010 addr1_high = tr32(MAC_ADDR_1_HIGH);
8011 addr1_low = tr32(MAC_ADDR_1_LOW);
8013 /* Skip MAC addr 1 if ASF is using it. */
8014 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
8015 !(addr1_high == 0 && addr1_low == 0))
8018 spin_lock_bh(&tp->lock);
8019 __tg3_set_mac_addr(tp, skip_mac_1);
8020 spin_unlock_bh(&tp->lock);
8025 /* tp->lock is held. */
8026 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
8027 dma_addr_t mapping, u32 maxlen_flags,
8031 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
8032 ((u64) mapping >> 32));
8034 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
8035 ((u64) mapping & 0xffffffff));
8037 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
8040 if (!tg3_flag(tp, 5705_PLUS))
8042 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
8046 static void __tg3_set_rx_mode(struct net_device *);
8047 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
8051 if (!tg3_flag(tp, ENABLE_TSS)) {
8052 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
8053 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
8054 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
8056 tw32(HOSTCC_TXCOL_TICKS, 0);
8057 tw32(HOSTCC_TXMAX_FRAMES, 0);
8058 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
8061 if (!tg3_flag(tp, ENABLE_RSS)) {
8062 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
8063 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
8064 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
8066 tw32(HOSTCC_RXCOL_TICKS, 0);
8067 tw32(HOSTCC_RXMAX_FRAMES, 0);
8068 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
8071 if (!tg3_flag(tp, 5705_PLUS)) {
8072 u32 val = ec->stats_block_coalesce_usecs;
8074 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
8075 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
8077 if (!netif_carrier_ok(tp->dev))
8080 tw32(HOSTCC_STAT_COAL_TICKS, val);
8083 for (i = 0; i < tp->irq_cnt - 1; i++) {
8086 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
8087 tw32(reg, ec->rx_coalesce_usecs);
8088 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
8089 tw32(reg, ec->rx_max_coalesced_frames);
8090 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
8091 tw32(reg, ec->rx_max_coalesced_frames_irq);
8093 if (tg3_flag(tp, ENABLE_TSS)) {
8094 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
8095 tw32(reg, ec->tx_coalesce_usecs);
8096 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
8097 tw32(reg, ec->tx_max_coalesced_frames);
8098 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
8099 tw32(reg, ec->tx_max_coalesced_frames_irq);
8103 for (; i < tp->irq_max - 1; i++) {
8104 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
8105 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
8106 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
8108 if (tg3_flag(tp, ENABLE_TSS)) {
8109 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
8110 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
8111 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
8116 /* tp->lock is held. */
8117 static void tg3_rings_reset(struct tg3 *tp)
8120 u32 stblk, txrcb, rxrcb, limit;
8121 struct tg3_napi *tnapi = &tp->napi[0];
8123 /* Disable all transmit rings but the first. */
8124 if (!tg3_flag(tp, 5705_PLUS))
8125 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
8126 else if (tg3_flag(tp, 5717_PLUS))
8127 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
8128 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8129 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
8131 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
8133 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
8134 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
8135 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
8136 BDINFO_FLAGS_DISABLED);
8139 /* Disable all receive return rings but the first. */
8140 if (tg3_flag(tp, 5717_PLUS))
8141 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
8142 else if (!tg3_flag(tp, 5705_PLUS))
8143 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
8144 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8145 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8146 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
8148 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
8150 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
8151 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
8152 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
8153 BDINFO_FLAGS_DISABLED);
8155 /* Disable interrupts */
8156 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
8157 tp->napi[0].chk_msi_cnt = 0;
8158 tp->napi[0].last_rx_cons = 0;
8159 tp->napi[0].last_tx_cons = 0;
8161 /* Zero mailbox registers. */
8162 if (tg3_flag(tp, SUPPORT_MSIX)) {
8163 for (i = 1; i < tp->irq_max; i++) {
8164 tp->napi[i].tx_prod = 0;
8165 tp->napi[i].tx_cons = 0;
8166 if (tg3_flag(tp, ENABLE_TSS))
8167 tw32_mailbox(tp->napi[i].prodmbox, 0);
8168 tw32_rx_mbox(tp->napi[i].consmbox, 0);
8169 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
8170 tp->napi[i].chk_msi_cnt = 0;
8171 tp->napi[i].last_rx_cons = 0;
8172 tp->napi[i].last_tx_cons = 0;
8174 if (!tg3_flag(tp, ENABLE_TSS))
8175 tw32_mailbox(tp->napi[0].prodmbox, 0);
8177 tp->napi[0].tx_prod = 0;
8178 tp->napi[0].tx_cons = 0;
8179 tw32_mailbox(tp->napi[0].prodmbox, 0);
8180 tw32_rx_mbox(tp->napi[0].consmbox, 0);
8183 /* Make sure the NIC-based send BD rings are disabled. */
8184 if (!tg3_flag(tp, 5705_PLUS)) {
8185 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
8186 for (i = 0; i < 16; i++)
8187 tw32_tx_mbox(mbox + i * 8, 0);
8190 txrcb = NIC_SRAM_SEND_RCB;
8191 rxrcb = NIC_SRAM_RCV_RET_RCB;
8193 /* Clear status block in ram. */
8194 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8196 /* Set status block DMA address */
8197 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8198 ((u64) tnapi->status_mapping >> 32));
8199 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8200 ((u64) tnapi->status_mapping & 0xffffffff));
8202 if (tnapi->tx_ring) {
8203 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
8204 (TG3_TX_RING_SIZE <<
8205 BDINFO_FLAGS_MAXLEN_SHIFT),
8206 NIC_SRAM_TX_BUFFER_DESC);
8207 txrcb += TG3_BDINFO_SIZE;
8210 if (tnapi->rx_rcb) {
8211 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
8212 (tp->rx_ret_ring_mask + 1) <<
8213 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
8214 rxrcb += TG3_BDINFO_SIZE;
8217 stblk = HOSTCC_STATBLCK_RING1;
8219 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
8220 u64 mapping = (u64)tnapi->status_mapping;
8221 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
8222 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
8224 /* Clear status block in ram. */
8225 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8227 if (tnapi->tx_ring) {
8228 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
8229 (TG3_TX_RING_SIZE <<
8230 BDINFO_FLAGS_MAXLEN_SHIFT),
8231 NIC_SRAM_TX_BUFFER_DESC);
8232 txrcb += TG3_BDINFO_SIZE;
8235 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
8236 ((tp->rx_ret_ring_mask + 1) <<
8237 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
8240 rxrcb += TG3_BDINFO_SIZE;
8244 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
8246 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
8248 if (!tg3_flag(tp, 5750_PLUS) ||
8249 tg3_flag(tp, 5780_CLASS) ||
8250 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
8251 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8252 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
8253 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8254 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8255 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
8257 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
8259 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
8260 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
8262 val = min(nic_rep_thresh, host_rep_thresh);
8263 tw32(RCVBDI_STD_THRESH, val);
8265 if (tg3_flag(tp, 57765_PLUS))
8266 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
8268 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
8271 if (!tg3_flag(tp, 5705_PLUS))
8272 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
8274 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717;
8276 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
8278 val = min(bdcache_maxcnt / 2, host_rep_thresh);
8279 tw32(RCVBDI_JUMBO_THRESH, val);
8281 if (tg3_flag(tp, 57765_PLUS))
8282 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
8285 /* tp->lock is held. */
8286 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8288 u32 val, rdmac_mode;
8290 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
8292 tg3_disable_ints(tp);
8296 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
8298 if (tg3_flag(tp, INIT_COMPLETE))
8299 tg3_abort_hw(tp, 1);
8301 /* Enable MAC control of LPI */
8302 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
8303 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
8304 TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
8305 TG3_CPMU_EEE_LNKIDL_UART_IDL);
8307 tw32_f(TG3_CPMU_EEE_CTRL,
8308 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
8310 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
8311 TG3_CPMU_EEEMD_LPI_IN_TX |
8312 TG3_CPMU_EEEMD_LPI_IN_RX |
8313 TG3_CPMU_EEEMD_EEE_ENABLE;
8315 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8316 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
8318 if (tg3_flag(tp, ENABLE_APE))
8319 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
8321 tw32_f(TG3_CPMU_EEE_MODE, val);
8323 tw32_f(TG3_CPMU_EEE_DBTMR1,
8324 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
8325 TG3_CPMU_DBTMR1_LNKIDLE_2047US);
8327 tw32_f(TG3_CPMU_EEE_DBTMR2,
8328 TG3_CPMU_DBTMR2_APE_TX_2047US |
8329 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
8335 err = tg3_chip_reset(tp);
8339 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
8341 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
8342 val = tr32(TG3_CPMU_CTRL);
8343 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
8344 tw32(TG3_CPMU_CTRL, val);
8346 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8347 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8348 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8349 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8351 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
8352 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
8353 val |= CPMU_LNK_AWARE_MACCLK_6_25;
8354 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
8356 val = tr32(TG3_CPMU_HST_ACC);
8357 val &= ~CPMU_HST_ACC_MACCLK_MASK;
8358 val |= CPMU_HST_ACC_MACCLK_6_25;
8359 tw32(TG3_CPMU_HST_ACC, val);
8362 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
8363 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
8364 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
8365 PCIE_PWR_MGMT_L1_THRESH_4MS;
8366 tw32(PCIE_PWR_MGMT_THRESH, val);
8368 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
8369 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
8371 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
8373 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
8374 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
8377 if (tg3_flag(tp, L1PLLPD_EN)) {
8378 u32 grc_mode = tr32(GRC_MODE);
8380 /* Access the lower 1K of PL PCIE block registers. */
8381 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8382 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8384 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
8385 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
8386 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
8388 tw32(GRC_MODE, grc_mode);
8391 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
8392 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
8393 u32 grc_mode = tr32(GRC_MODE);
8395 /* Access the lower 1K of PL PCIE block registers. */
8396 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8397 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8399 val = tr32(TG3_PCIE_TLDLPL_PORT +
8400 TG3_PCIE_PL_LO_PHYCTL5);
8401 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
8402 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
8404 tw32(GRC_MODE, grc_mode);
8407 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) {
8408 u32 grc_mode = tr32(GRC_MODE);
8410 /* Access the lower 1K of DL PCIE block registers. */
8411 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8412 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
8414 val = tr32(TG3_PCIE_TLDLPL_PORT +
8415 TG3_PCIE_DL_LO_FTSMAX);
8416 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
8417 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
8418 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
8420 tw32(GRC_MODE, grc_mode);
8423 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8424 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8425 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8426 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8429 /* This works around an issue with Athlon chipsets on
8430 * B3 tigon3 silicon. This bit has no effect on any
8431 * other revision. But do not set this on PCI Express
8432 * chips and don't even touch the clocks if the CPMU is present.
8434 if (!tg3_flag(tp, CPMU_PRESENT)) {
8435 if (!tg3_flag(tp, PCI_EXPRESS))
8436 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
8437 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
8440 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
8441 tg3_flag(tp, PCIX_MODE)) {
8442 val = tr32(TG3PCI_PCISTATE);
8443 val |= PCISTATE_RETRY_SAME_DMA;
8444 tw32(TG3PCI_PCISTATE, val);
8447 if (tg3_flag(tp, ENABLE_APE)) {
8448 /* Allow reads and writes to the
8449 * APE register and memory space.
8451 val = tr32(TG3PCI_PCISTATE);
8452 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8453 PCISTATE_ALLOW_APE_SHMEM_WR |
8454 PCISTATE_ALLOW_APE_PSPACE_WR;
8455 tw32(TG3PCI_PCISTATE, val);
8458 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
8459 /* Enable some hw fixes. */
8460 val = tr32(TG3PCI_MSI_DATA);
8461 val |= (1 << 26) | (1 << 28) | (1 << 29);
8462 tw32(TG3PCI_MSI_DATA, val);
8465 /* Descriptor ring init may make accesses to the
8466 * NIC SRAM area to setup the TX descriptors, so we
8467 * can only do this after the hardware has been
8468 * successfully reset.
8470 err = tg3_init_rings(tp);
8474 if (tg3_flag(tp, 57765_PLUS)) {
8475 val = tr32(TG3PCI_DMA_RW_CTRL) &
8476 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
8477 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
8478 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
8479 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
8480 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8481 val |= DMA_RWCTRL_TAGGED_STAT_WA;
8482 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
8483 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
8484 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
8485 /* This value is determined during the probe time DMA
8486 * engine test, tg3_test_dma.
8488 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
8491 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
8492 GRC_MODE_4X_NIC_SEND_RINGS |
8493 GRC_MODE_NO_TX_PHDR_CSUM |
8494 GRC_MODE_NO_RX_PHDR_CSUM);
8495 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
8497 /* Pseudo-header checksum is done by hardware logic and not
8498 * the offload processers, so make the chip do the pseudo-
8499 * header checksums on receive. For transmit it is more
8500 * convenient to do the pseudo-header checksum in software
8501 * as Linux does that on transmit for us in all cases.
8503 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
8507 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
8509 /* Setup the timer prescalar register. Clock is always 66Mhz. */
8510 val = tr32(GRC_MISC_CFG);
8512 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
8513 tw32(GRC_MISC_CFG, val);
8515 /* Initialize MBUF/DESC pool. */
8516 if (tg3_flag(tp, 5750_PLUS)) {
8518 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
8519 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
8520 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8521 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
8523 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
8524 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
8525 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
8526 } else if (tg3_flag(tp, TSO_CAPABLE)) {
8529 fw_len = tp->fw_len;
8530 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
8531 tw32(BUFMGR_MB_POOL_ADDR,
8532 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
8533 tw32(BUFMGR_MB_POOL_SIZE,
8534 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
8537 if (tp->dev->mtu <= ETH_DATA_LEN) {
8538 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8539 tp->bufmgr_config.mbuf_read_dma_low_water);
8540 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8541 tp->bufmgr_config.mbuf_mac_rx_low_water);
8542 tw32(BUFMGR_MB_HIGH_WATER,
8543 tp->bufmgr_config.mbuf_high_water);
8545 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8546 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8547 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8548 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8549 tw32(BUFMGR_MB_HIGH_WATER,
8550 tp->bufmgr_config.mbuf_high_water_jumbo);
8552 tw32(BUFMGR_DMA_LOW_WATER,
8553 tp->bufmgr_config.dma_low_water);
8554 tw32(BUFMGR_DMA_HIGH_WATER,
8555 tp->bufmgr_config.dma_high_water);
8557 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8558 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8559 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
8560 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8561 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
8562 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0)
8563 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
8564 tw32(BUFMGR_MODE, val);
8565 for (i = 0; i < 2000; i++) {
8566 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8571 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
8575 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8576 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
8578 tg3_setup_rxbd_thresholds(tp);
8580 /* Initialize TG3_BDINFO's at:
8581 * RCVDBDI_STD_BD: standard eth size rx ring
8582 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
8583 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
8586 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
8587 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
8588 * ring attribute flags
8589 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
8591 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8592 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8594 * The size of each ring is fixed in the firmware, but the location is
8597 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8598 ((u64) tpr->rx_std_mapping >> 32));
8599 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8600 ((u64) tpr->rx_std_mapping & 0xffffffff));
8601 if (!tg3_flag(tp, 5717_PLUS))
8602 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8603 NIC_SRAM_RX_BUFFER_DESC);
8605 /* Disable the mini ring */
8606 if (!tg3_flag(tp, 5705_PLUS))
8607 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8608 BDINFO_FLAGS_DISABLED);
8610 /* Program the jumbo buffer descriptor ring control
8611 * blocks on those devices that have them.
8613 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
8614 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
8616 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
8617 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8618 ((u64) tpr->rx_jmb_mapping >> 32));
8619 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8620 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
8621 val = TG3_RX_JMB_RING_SIZE(tp) <<
8622 BDINFO_FLAGS_MAXLEN_SHIFT;
8623 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8624 val | BDINFO_FLAGS_USE_EXT_RECV);
8625 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
8626 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8627 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8628 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
8630 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8631 BDINFO_FLAGS_DISABLED);
8634 if (tg3_flag(tp, 57765_PLUS)) {
8635 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8636 val = TG3_RX_STD_MAX_SIZE_5700;
8638 val = TG3_RX_STD_MAX_SIZE_5717;
8639 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8640 val |= (TG3_RX_STD_DMA_SZ << 2);
8642 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
8644 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
8646 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
8648 tpr->rx_std_prod_idx = tp->rx_pending;
8649 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
8651 tpr->rx_jmb_prod_idx =
8652 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
8653 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
8655 tg3_rings_reset(tp);
8657 /* Initialize MAC address and backoff seed. */
8658 __tg3_set_mac_addr(tp, 0);
8660 /* MTU + ethernet header + FCS + optional VLAN tag */
8661 tw32(MAC_RX_MTU_SIZE,
8662 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
8664 /* The slot time is changed by tg3_setup_phy if we
8665 * run at gigabit with half duplex.
8667 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8668 (6 << TX_LENGTHS_IPG_SHIFT) |
8669 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
8671 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8672 val |= tr32(MAC_TX_LENGTHS) &
8673 (TX_LENGTHS_JMB_FRM_LEN_MSK |
8674 TX_LENGTHS_CNT_DWN_VAL_MSK);
8676 tw32(MAC_TX_LENGTHS, val);
8678 /* Receive rules. */
8679 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8680 tw32(RCVLPC_CONFIG, 0x0181);
8682 /* Calculate RDMAC_MODE setting early, we need it to determine
8683 * the RCVLPC_STATE_ENABLE mask.
8685 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8686 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8687 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8688 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8689 RDMAC_MODE_LNGREAD_ENAB);
8691 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8692 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8694 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8695 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8696 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8697 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8698 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8699 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8701 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8702 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8703 if (tg3_flag(tp, TSO_CAPABLE) &&
8704 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8705 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8706 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8707 !tg3_flag(tp, IS_5788)) {
8708 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8712 if (tg3_flag(tp, PCI_EXPRESS))
8713 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8715 if (tg3_flag(tp, HW_TSO_1) ||
8716 tg3_flag(tp, HW_TSO_2) ||
8717 tg3_flag(tp, HW_TSO_3))
8718 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8720 if (tg3_flag(tp, 57765_PLUS) ||
8721 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8722 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8723 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8725 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8726 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
8728 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8729 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8730 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8731 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8732 tg3_flag(tp, 57765_PLUS)) {
8733 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8734 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8735 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8736 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
8737 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
8738 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
8739 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
8740 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
8741 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
8743 tw32(TG3_RDMA_RSRVCTRL_REG,
8744 val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8747 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8748 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8749 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8750 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8751 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8752 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8755 /* Receive/send statistics. */
8756 if (tg3_flag(tp, 5750_PLUS)) {
8757 val = tr32(RCVLPC_STATS_ENABLE);
8758 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8759 tw32(RCVLPC_STATS_ENABLE, val);
8760 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8761 tg3_flag(tp, TSO_CAPABLE)) {
8762 val = tr32(RCVLPC_STATS_ENABLE);
8763 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8764 tw32(RCVLPC_STATS_ENABLE, val);
8766 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8768 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8769 tw32(SNDDATAI_STATSENAB, 0xffffff);
8770 tw32(SNDDATAI_STATSCTRL,
8771 (SNDDATAI_SCTRL_ENABLE |
8772 SNDDATAI_SCTRL_FASTUPD));
8774 /* Setup host coalescing engine. */
8775 tw32(HOSTCC_MODE, 0);
8776 for (i = 0; i < 2000; i++) {
8777 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8782 __tg3_set_coalesce(tp, &tp->coal);
8784 if (!tg3_flag(tp, 5705_PLUS)) {
8785 /* Status/statistics block address. See tg3_timer,
8786 * the tg3_periodic_fetch_stats call there, and
8787 * tg3_get_stats to see how this works for 5705/5750 chips.
8789 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8790 ((u64) tp->stats_mapping >> 32));
8791 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8792 ((u64) tp->stats_mapping & 0xffffffff));
8793 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8795 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8797 /* Clear statistics and status block memory areas */
8798 for (i = NIC_SRAM_STATS_BLK;
8799 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8801 tg3_write_mem(tp, i, 0);
8806 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8808 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8809 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8810 if (!tg3_flag(tp, 5705_PLUS))
8811 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8813 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8814 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8815 /* reset to prevent losing 1st rx packet intermittently */
8816 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8820 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8821 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
8822 MAC_MODE_FHDE_ENABLE;
8823 if (tg3_flag(tp, ENABLE_APE))
8824 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8825 if (!tg3_flag(tp, 5705_PLUS) &&
8826 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8827 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8828 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8829 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8832 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8833 * If TG3_FLAG_IS_NIC is zero, we should read the
8834 * register to preserve the GPIO settings for LOMs. The GPIOs,
8835 * whether used as inputs or outputs, are set by boot code after
8838 if (!tg3_flag(tp, IS_NIC)) {
8841 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8842 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8843 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8845 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8846 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8847 GRC_LCLCTRL_GPIO_OUTPUT3;
8849 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8850 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8852 tp->grc_local_ctrl &= ~gpio_mask;
8853 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8855 /* GPIO1 must be driven high for eeprom write protect */
8856 if (tg3_flag(tp, EEPROM_WRITE_PROT))
8857 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8858 GRC_LCLCTRL_GPIO_OUTPUT1);
8860 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8863 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) {
8864 val = tr32(MSGINT_MODE);
8865 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8866 if (!tg3_flag(tp, 1SHOT_MSI))
8867 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
8868 tw32(MSGINT_MODE, val);
8871 if (!tg3_flag(tp, 5705_PLUS)) {
8872 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8876 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8877 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8878 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8879 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8880 WDMAC_MODE_LNGREAD_ENAB);
8882 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8883 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8884 if (tg3_flag(tp, TSO_CAPABLE) &&
8885 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8886 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8888 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8889 !tg3_flag(tp, IS_5788)) {
8890 val |= WDMAC_MODE_RX_ACCEL;
8894 /* Enable host coalescing bug fix */
8895 if (tg3_flag(tp, 5755_PLUS))
8896 val |= WDMAC_MODE_STATUS_TAG_FIX;
8898 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8899 val |= WDMAC_MODE_BURST_ALL_DATA;
8901 tw32_f(WDMAC_MODE, val);
8904 if (tg3_flag(tp, PCIX_MODE)) {
8907 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8909 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8910 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8911 pcix_cmd |= PCI_X_CMD_READ_2K;
8912 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8913 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8914 pcix_cmd |= PCI_X_CMD_READ_2K;
8916 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8920 tw32_f(RDMAC_MODE, rdmac_mode);
8923 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8924 if (!tg3_flag(tp, 5705_PLUS))
8925 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8927 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8929 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8931 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8933 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8934 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8935 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
8936 if (tg3_flag(tp, LRG_PROD_RING_CAP))
8937 val |= RCVDBDI_MODE_LRG_RING_SZ;
8938 tw32(RCVDBDI_MODE, val);
8939 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8940 if (tg3_flag(tp, HW_TSO_1) ||
8941 tg3_flag(tp, HW_TSO_2) ||
8942 tg3_flag(tp, HW_TSO_3))
8943 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8944 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8945 if (tg3_flag(tp, ENABLE_TSS))
8946 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8947 tw32(SNDBDI_MODE, val);
8948 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8950 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8951 err = tg3_load_5701_a0_firmware_fix(tp);
8956 if (tg3_flag(tp, TSO_CAPABLE)) {
8957 err = tg3_load_tso_firmware(tp);
8962 tp->tx_mode = TX_MODE_ENABLE;
8964 if (tg3_flag(tp, 5755_PLUS) ||
8965 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8966 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8968 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8969 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
8970 tp->tx_mode &= ~val;
8971 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
8974 tw32_f(MAC_TX_MODE, tp->tx_mode);
8977 if (tg3_flag(tp, ENABLE_RSS)) {
8979 u32 reg = MAC_RSS_INDIR_TBL_0;
8981 if (tp->irq_cnt == 2) {
8982 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i += 8) {
8989 while (i < TG3_RSS_INDIR_TBL_SIZE) {
8990 val = i % (tp->irq_cnt - 1);
8992 for (; i % 8; i++) {
8994 val |= (i % (tp->irq_cnt - 1));
9001 /* Setup the "secret" hash key. */
9002 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
9003 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
9004 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
9005 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
9006 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
9007 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
9008 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
9009 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
9010 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
9011 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
9014 tp->rx_mode = RX_MODE_ENABLE;
9015 if (tg3_flag(tp, 5755_PLUS))
9016 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
9018 if (tg3_flag(tp, ENABLE_RSS))
9019 tp->rx_mode |= RX_MODE_RSS_ENABLE |
9020 RX_MODE_RSS_ITBL_HASH_BITS_7 |
9021 RX_MODE_RSS_IPV6_HASH_EN |
9022 RX_MODE_RSS_TCP_IPV6_HASH_EN |
9023 RX_MODE_RSS_IPV4_HASH_EN |
9024 RX_MODE_RSS_TCP_IPV4_HASH_EN;
9026 tw32_f(MAC_RX_MODE, tp->rx_mode);
9029 tw32(MAC_LED_CTRL, tp->led_ctrl);
9031 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
9032 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9033 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9036 tw32_f(MAC_RX_MODE, tp->rx_mode);
9039 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9040 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
9041 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
9042 /* Set drive transmission level to 1.2V */
9043 /* only if the signal pre-emphasis bit is not set */
9044 val = tr32(MAC_SERDES_CFG);
9047 tw32(MAC_SERDES_CFG, val);
9049 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
9050 tw32(MAC_SERDES_CFG, 0x616000);
9053 /* Prevent chip from dropping frames when flow control
9056 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
9060 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
9062 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9063 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
9064 /* Use hardware link auto-negotiation */
9065 tg3_flag_set(tp, HW_AUTONEG);
9068 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
9069 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
9072 tmp = tr32(SERDES_RX_CTRL);
9073 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
9074 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
9075 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
9076 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9079 if (!tg3_flag(tp, USE_PHYLIB)) {
9080 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
9081 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
9082 tp->link_config.speed = tp->link_config.orig_speed;
9083 tp->link_config.duplex = tp->link_config.orig_duplex;
9084 tp->link_config.autoneg = tp->link_config.orig_autoneg;
9087 err = tg3_setup_phy(tp, 0);
9091 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9092 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
9095 /* Clear CRC stats. */
9096 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
9097 tg3_writephy(tp, MII_TG3_TEST1,
9098 tmp | MII_TG3_TEST1_CRC_EN);
9099 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
9104 __tg3_set_rx_mode(tp->dev);
9106 /* Initialize receive rules. */
9107 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
9108 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
9109 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
9110 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
9112 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
9116 if (tg3_flag(tp, ENABLE_ASF))
9120 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
9122 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
9124 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
9126 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
9128 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
9130 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
9132 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
9134 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
9136 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
9138 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
9140 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
9142 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
9144 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
9146 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
9154 if (tg3_flag(tp, ENABLE_APE))
9155 /* Write our heartbeat update interval to APE. */
9156 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
9157 APE_HOST_HEARTBEAT_INT_DISABLE);
9159 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
9164 /* Called at device open time to get the chip ready for
9165 * packet processing. Invoked with tp->lock held.
9167 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
9169 tg3_switch_clocks(tp);
9171 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
9173 return tg3_reset_hw(tp, reset_phy);
9176 #define TG3_STAT_ADD32(PSTAT, REG) \
9177 do { u32 __val = tr32(REG); \
9178 (PSTAT)->low += __val; \
9179 if ((PSTAT)->low < __val) \
9180 (PSTAT)->high += 1; \
9183 static void tg3_periodic_fetch_stats(struct tg3 *tp)
9185 struct tg3_hw_stats *sp = tp->hw_stats;
9187 if (!netif_carrier_ok(tp->dev))
9190 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
9191 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
9192 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
9193 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
9194 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
9195 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
9196 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
9197 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
9198 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
9199 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
9200 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
9201 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
9202 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
9204 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
9205 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
9206 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
9207 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
9208 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
9209 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
9210 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
9211 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
9212 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
9213 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
9214 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
9215 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
9216 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
9217 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
9219 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
9220 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
9221 tp->pci_chip_rev_id != CHIPREV_ID_5719_A0 &&
9222 tp->pci_chip_rev_id != CHIPREV_ID_5720_A0) {
9223 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
9225 u32 val = tr32(HOSTCC_FLOW_ATTN);
9226 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
9228 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
9229 sp->rx_discards.low += val;
9230 if (sp->rx_discards.low < val)
9231 sp->rx_discards.high += 1;
9233 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
9235 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
9238 static void tg3_chk_missed_msi(struct tg3 *tp)
9242 for (i = 0; i < tp->irq_cnt; i++) {
9243 struct tg3_napi *tnapi = &tp->napi[i];
9245 if (tg3_has_work(tnapi)) {
9246 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
9247 tnapi->last_tx_cons == tnapi->tx_cons) {
9248 if (tnapi->chk_msi_cnt < 1) {
9249 tnapi->chk_msi_cnt++;
9255 tnapi->chk_msi_cnt = 0;
9256 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
9257 tnapi->last_tx_cons = tnapi->tx_cons;
9261 static void tg3_timer(unsigned long __opaque)
9263 struct tg3 *tp = (struct tg3 *) __opaque;
9265 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
9268 spin_lock(&tp->lock);
9270 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
9271 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
9272 tg3_chk_missed_msi(tp);
9274 if (!tg3_flag(tp, TAGGED_STATUS)) {
9275 /* All of this garbage is because when using non-tagged
9276 * IRQ status the mailbox/status_block protocol the chip
9277 * uses with the cpu is race prone.
9279 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
9280 tw32(GRC_LOCAL_CTRL,
9281 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
9283 tw32(HOSTCC_MODE, tp->coalesce_mode |
9284 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
9287 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
9288 spin_unlock(&tp->lock);
9289 tg3_reset_task_schedule(tp);
9294 /* This part only runs once per second. */
9295 if (!--tp->timer_counter) {
9296 if (tg3_flag(tp, 5705_PLUS))
9297 tg3_periodic_fetch_stats(tp);
9299 if (tp->setlpicnt && !--tp->setlpicnt)
9300 tg3_phy_eee_enable(tp);
9302 if (tg3_flag(tp, USE_LINKCHG_REG)) {
9306 mac_stat = tr32(MAC_STATUS);
9309 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
9310 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
9312 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
9316 tg3_setup_phy(tp, 0);
9317 } else if (tg3_flag(tp, POLL_SERDES)) {
9318 u32 mac_stat = tr32(MAC_STATUS);
9321 if (netif_carrier_ok(tp->dev) &&
9322 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
9325 if (!netif_carrier_ok(tp->dev) &&
9326 (mac_stat & (MAC_STATUS_PCS_SYNCED |
9327 MAC_STATUS_SIGNAL_DET))) {
9331 if (!tp->serdes_counter) {
9334 ~MAC_MODE_PORT_MODE_MASK));
9336 tw32_f(MAC_MODE, tp->mac_mode);
9339 tg3_setup_phy(tp, 0);
9341 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
9342 tg3_flag(tp, 5780_CLASS)) {
9343 tg3_serdes_parallel_detect(tp);
9346 tp->timer_counter = tp->timer_multiplier;
9349 /* Heartbeat is only sent once every 2 seconds.
9351 * The heartbeat is to tell the ASF firmware that the host
9352 * driver is still alive. In the event that the OS crashes,
9353 * ASF needs to reset the hardware to free up the FIFO space
9354 * that may be filled with rx packets destined for the host.
9355 * If the FIFO is full, ASF will no longer function properly.
9357 * Unintended resets have been reported on real time kernels
9358 * where the timer doesn't run on time. Netpoll will also have
9361 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
9362 * to check the ring condition when the heartbeat is expiring
9363 * before doing the reset. This will prevent most unintended
9366 if (!--tp->asf_counter) {
9367 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
9368 tg3_wait_for_event_ack(tp);
9370 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
9371 FWCMD_NICDRV_ALIVE3);
9372 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
9373 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
9374 TG3_FW_UPDATE_TIMEOUT_SEC);
9376 tg3_generate_fw_event(tp);
9378 tp->asf_counter = tp->asf_multiplier;
9381 spin_unlock(&tp->lock);
9384 tp->timer.expires = jiffies + tp->timer_offset;
9385 add_timer(&tp->timer);
9388 static int tg3_request_irq(struct tg3 *tp, int irq_num)
9391 unsigned long flags;
9393 struct tg3_napi *tnapi = &tp->napi[irq_num];
9395 if (tp->irq_cnt == 1)
9396 name = tp->dev->name;
9398 name = &tnapi->irq_lbl[0];
9399 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
9400 name[IFNAMSIZ-1] = 0;
9403 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
9405 if (tg3_flag(tp, 1SHOT_MSI))
9410 if (tg3_flag(tp, TAGGED_STATUS))
9411 fn = tg3_interrupt_tagged;
9412 flags = IRQF_SHARED;
9415 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
9418 static int tg3_test_interrupt(struct tg3 *tp)
9420 struct tg3_napi *tnapi = &tp->napi[0];
9421 struct net_device *dev = tp->dev;
9422 int err, i, intr_ok = 0;
9425 if (!netif_running(dev))
9428 tg3_disable_ints(tp);
9430 free_irq(tnapi->irq_vec, tnapi);
9433 * Turn off MSI one shot mode. Otherwise this test has no
9434 * observable way to know whether the interrupt was delivered.
9436 if (tg3_flag(tp, 57765_PLUS)) {
9437 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
9438 tw32(MSGINT_MODE, val);
9441 err = request_irq(tnapi->irq_vec, tg3_test_isr,
9442 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
9446 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
9447 tg3_enable_ints(tp);
9449 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9452 for (i = 0; i < 5; i++) {
9453 u32 int_mbox, misc_host_ctrl;
9455 int_mbox = tr32_mailbox(tnapi->int_mbox);
9456 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
9458 if ((int_mbox != 0) ||
9459 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
9464 if (tg3_flag(tp, 57765_PLUS) &&
9465 tnapi->hw_status->status_tag != tnapi->last_tag)
9466 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
9471 tg3_disable_ints(tp);
9473 free_irq(tnapi->irq_vec, tnapi);
9475 err = tg3_request_irq(tp, 0);
9481 /* Reenable MSI one shot mode. */
9482 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
9483 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
9484 tw32(MSGINT_MODE, val);
9492 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
9493 * successfully restored
9495 static int tg3_test_msi(struct tg3 *tp)
9500 if (!tg3_flag(tp, USING_MSI))
9503 /* Turn off SERR reporting in case MSI terminates with Master
9506 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9507 pci_write_config_word(tp->pdev, PCI_COMMAND,
9508 pci_cmd & ~PCI_COMMAND_SERR);
9510 err = tg3_test_interrupt(tp);
9512 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9517 /* other failures */
9521 /* MSI test failed, go back to INTx mode */
9522 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
9523 "to INTx mode. Please report this failure to the PCI "
9524 "maintainer and include system chipset information\n");
9526 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9528 pci_disable_msi(tp->pdev);
9530 tg3_flag_clear(tp, USING_MSI);
9531 tp->napi[0].irq_vec = tp->pdev->irq;
9533 err = tg3_request_irq(tp, 0);
9537 /* Need to reset the chip because the MSI cycle may have terminated
9538 * with Master Abort.
9540 tg3_full_lock(tp, 1);
9542 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9543 err = tg3_init_hw(tp, 1);
9545 tg3_full_unlock(tp);
9548 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9553 static int tg3_request_firmware(struct tg3 *tp)
9555 const __be32 *fw_data;
9557 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
9558 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
9563 fw_data = (void *)tp->fw->data;
9565 /* Firmware blob starts with version numbers, followed by
9566 * start address and _full_ length including BSS sections
9567 * (which must be longer than the actual data, of course
9570 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
9571 if (tp->fw_len < (tp->fw->size - 12)) {
9572 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
9573 tp->fw_len, tp->fw_needed);
9574 release_firmware(tp->fw);
9579 /* We no longer need firmware; we have it. */
9580 tp->fw_needed = NULL;
9584 static bool tg3_enable_msix(struct tg3 *tp)
9586 int i, rc, cpus = num_online_cpus();
9587 struct msix_entry msix_ent[tp->irq_max];
9590 /* Just fallback to the simpler MSI mode. */
9594 * We want as many rx rings enabled as there are cpus.
9595 * The first MSIX vector only deals with link interrupts, etc,
9596 * so we add one to the number of vectors we are requesting.
9598 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
9600 for (i = 0; i < tp->irq_max; i++) {
9601 msix_ent[i].entry = i;
9602 msix_ent[i].vector = 0;
9605 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
9608 } else if (rc != 0) {
9609 if (pci_enable_msix(tp->pdev, msix_ent, rc))
9611 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
9616 for (i = 0; i < tp->irq_max; i++)
9617 tp->napi[i].irq_vec = msix_ent[i].vector;
9619 netif_set_real_num_tx_queues(tp->dev, 1);
9620 rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
9621 if (netif_set_real_num_rx_queues(tp->dev, rc)) {
9622 pci_disable_msix(tp->pdev);
9626 if (tp->irq_cnt > 1) {
9627 tg3_flag_set(tp, ENABLE_RSS);
9629 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
9630 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
9631 tg3_flag_set(tp, ENABLE_TSS);
9632 netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
9639 static void tg3_ints_init(struct tg3 *tp)
9641 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
9642 !tg3_flag(tp, TAGGED_STATUS)) {
9643 /* All MSI supporting chips should support tagged
9644 * status. Assert that this is the case.
9646 netdev_warn(tp->dev,
9647 "MSI without TAGGED_STATUS? Not using MSI\n");
9651 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
9652 tg3_flag_set(tp, USING_MSIX);
9653 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
9654 tg3_flag_set(tp, USING_MSI);
9656 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
9657 u32 msi_mode = tr32(MSGINT_MODE);
9658 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
9659 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
9660 if (!tg3_flag(tp, 1SHOT_MSI))
9661 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
9662 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9665 if (!tg3_flag(tp, USING_MSIX)) {
9667 tp->napi[0].irq_vec = tp->pdev->irq;
9668 netif_set_real_num_tx_queues(tp->dev, 1);
9669 netif_set_real_num_rx_queues(tp->dev, 1);
9673 static void tg3_ints_fini(struct tg3 *tp)
9675 if (tg3_flag(tp, USING_MSIX))
9676 pci_disable_msix(tp->pdev);
9677 else if (tg3_flag(tp, USING_MSI))
9678 pci_disable_msi(tp->pdev);
9679 tg3_flag_clear(tp, USING_MSI);
9680 tg3_flag_clear(tp, USING_MSIX);
9681 tg3_flag_clear(tp, ENABLE_RSS);
9682 tg3_flag_clear(tp, ENABLE_TSS);
9685 static int tg3_open(struct net_device *dev)
9687 struct tg3 *tp = netdev_priv(dev);
9690 if (tp->fw_needed) {
9691 err = tg3_request_firmware(tp);
9692 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9696 netdev_warn(tp->dev, "TSO capability disabled\n");
9697 tg3_flag_clear(tp, TSO_CAPABLE);
9698 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
9699 netdev_notice(tp->dev, "TSO capability restored\n");
9700 tg3_flag_set(tp, TSO_CAPABLE);
9704 netif_carrier_off(tp->dev);
9706 err = tg3_power_up(tp);
9710 tg3_full_lock(tp, 0);
9712 tg3_disable_ints(tp);
9713 tg3_flag_clear(tp, INIT_COMPLETE);
9715 tg3_full_unlock(tp);
9718 * Setup interrupts first so we know how
9719 * many NAPI resources to allocate
9723 /* The placement of this call is tied
9724 * to the setup and use of Host TX descriptors.
9726 err = tg3_alloc_consistent(tp);
9732 tg3_napi_enable(tp);
9734 for (i = 0; i < tp->irq_cnt; i++) {
9735 struct tg3_napi *tnapi = &tp->napi[i];
9736 err = tg3_request_irq(tp, i);
9738 for (i--; i >= 0; i--) {
9739 tnapi = &tp->napi[i];
9740 free_irq(tnapi->irq_vec, tnapi);
9746 tg3_full_lock(tp, 0);
9748 err = tg3_init_hw(tp, 1);
9750 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9753 if (tg3_flag(tp, TAGGED_STATUS) &&
9754 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
9755 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765)
9756 tp->timer_offset = HZ;
9758 tp->timer_offset = HZ / 10;
9760 BUG_ON(tp->timer_offset > HZ);
9761 tp->timer_counter = tp->timer_multiplier =
9762 (HZ / tp->timer_offset);
9763 tp->asf_counter = tp->asf_multiplier =
9764 ((HZ / tp->timer_offset) * 2);
9766 init_timer(&tp->timer);
9767 tp->timer.expires = jiffies + tp->timer_offset;
9768 tp->timer.data = (unsigned long) tp;
9769 tp->timer.function = tg3_timer;
9772 tg3_full_unlock(tp);
9777 if (tg3_flag(tp, USING_MSI)) {
9778 err = tg3_test_msi(tp);
9781 tg3_full_lock(tp, 0);
9782 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9784 tg3_full_unlock(tp);
9789 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
9790 u32 val = tr32(PCIE_TRANSACTION_CFG);
9792 tw32(PCIE_TRANSACTION_CFG,
9793 val | PCIE_TRANS_CFG_1SHOT_MSI);
9799 tg3_full_lock(tp, 0);
9801 add_timer(&tp->timer);
9802 tg3_flag_set(tp, INIT_COMPLETE);
9803 tg3_enable_ints(tp);
9805 tg3_full_unlock(tp);
9807 netif_tx_start_all_queues(dev);
9810 * Reset loopback feature if it was turned on while the device was down
9811 * make sure that it's installed properly now.
9813 if (dev->features & NETIF_F_LOOPBACK)
9814 tg3_set_loopback(dev, dev->features);
9819 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9820 struct tg3_napi *tnapi = &tp->napi[i];
9821 free_irq(tnapi->irq_vec, tnapi);
9825 tg3_napi_disable(tp);
9827 tg3_free_consistent(tp);
9831 tg3_frob_aux_power(tp, false);
9832 pci_set_power_state(tp->pdev, PCI_D3hot);
9836 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9837 struct rtnl_link_stats64 *);
9838 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9840 static int tg3_close(struct net_device *dev)
9843 struct tg3 *tp = netdev_priv(dev);
9845 tg3_napi_disable(tp);
9846 tg3_reset_task_cancel(tp);
9848 netif_tx_stop_all_queues(dev);
9850 del_timer_sync(&tp->timer);
9854 tg3_full_lock(tp, 1);
9856 tg3_disable_ints(tp);
9858 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9860 tg3_flag_clear(tp, INIT_COMPLETE);
9862 tg3_full_unlock(tp);
9864 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9865 struct tg3_napi *tnapi = &tp->napi[i];
9866 free_irq(tnapi->irq_vec, tnapi);
9871 tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9873 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9874 sizeof(tp->estats_prev));
9878 tg3_free_consistent(tp);
9882 netif_carrier_off(tp->dev);
9887 static inline u64 get_stat64(tg3_stat64_t *val)
9889 return ((u64)val->high << 32) | ((u64)val->low);
9892 static u64 calc_crc_errors(struct tg3 *tp)
9894 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9896 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9897 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9898 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9901 spin_lock_bh(&tp->lock);
9902 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9903 tg3_writephy(tp, MII_TG3_TEST1,
9904 val | MII_TG3_TEST1_CRC_EN);
9905 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9908 spin_unlock_bh(&tp->lock);
9910 tp->phy_crc_errors += val;
9912 return tp->phy_crc_errors;
9915 return get_stat64(&hw_stats->rx_fcs_errors);
9918 #define ESTAT_ADD(member) \
9919 estats->member = old_estats->member + \
9920 get_stat64(&hw_stats->member)
9922 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9924 struct tg3_ethtool_stats *estats = &tp->estats;
9925 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9926 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9931 ESTAT_ADD(rx_octets);
9932 ESTAT_ADD(rx_fragments);
9933 ESTAT_ADD(rx_ucast_packets);
9934 ESTAT_ADD(rx_mcast_packets);
9935 ESTAT_ADD(rx_bcast_packets);
9936 ESTAT_ADD(rx_fcs_errors);
9937 ESTAT_ADD(rx_align_errors);
9938 ESTAT_ADD(rx_xon_pause_rcvd);
9939 ESTAT_ADD(rx_xoff_pause_rcvd);
9940 ESTAT_ADD(rx_mac_ctrl_rcvd);
9941 ESTAT_ADD(rx_xoff_entered);
9942 ESTAT_ADD(rx_frame_too_long_errors);
9943 ESTAT_ADD(rx_jabbers);
9944 ESTAT_ADD(rx_undersize_packets);
9945 ESTAT_ADD(rx_in_length_errors);
9946 ESTAT_ADD(rx_out_length_errors);
9947 ESTAT_ADD(rx_64_or_less_octet_packets);
9948 ESTAT_ADD(rx_65_to_127_octet_packets);
9949 ESTAT_ADD(rx_128_to_255_octet_packets);
9950 ESTAT_ADD(rx_256_to_511_octet_packets);
9951 ESTAT_ADD(rx_512_to_1023_octet_packets);
9952 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9953 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9954 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9955 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9956 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9958 ESTAT_ADD(tx_octets);
9959 ESTAT_ADD(tx_collisions);
9960 ESTAT_ADD(tx_xon_sent);
9961 ESTAT_ADD(tx_xoff_sent);
9962 ESTAT_ADD(tx_flow_control);
9963 ESTAT_ADD(tx_mac_errors);
9964 ESTAT_ADD(tx_single_collisions);
9965 ESTAT_ADD(tx_mult_collisions);
9966 ESTAT_ADD(tx_deferred);
9967 ESTAT_ADD(tx_excessive_collisions);
9968 ESTAT_ADD(tx_late_collisions);
9969 ESTAT_ADD(tx_collide_2times);
9970 ESTAT_ADD(tx_collide_3times);
9971 ESTAT_ADD(tx_collide_4times);
9972 ESTAT_ADD(tx_collide_5times);
9973 ESTAT_ADD(tx_collide_6times);
9974 ESTAT_ADD(tx_collide_7times);
9975 ESTAT_ADD(tx_collide_8times);
9976 ESTAT_ADD(tx_collide_9times);
9977 ESTAT_ADD(tx_collide_10times);
9978 ESTAT_ADD(tx_collide_11times);
9979 ESTAT_ADD(tx_collide_12times);
9980 ESTAT_ADD(tx_collide_13times);
9981 ESTAT_ADD(tx_collide_14times);
9982 ESTAT_ADD(tx_collide_15times);
9983 ESTAT_ADD(tx_ucast_packets);
9984 ESTAT_ADD(tx_mcast_packets);
9985 ESTAT_ADD(tx_bcast_packets);
9986 ESTAT_ADD(tx_carrier_sense_errors);
9987 ESTAT_ADD(tx_discards);
9988 ESTAT_ADD(tx_errors);
9990 ESTAT_ADD(dma_writeq_full);
9991 ESTAT_ADD(dma_write_prioq_full);
9992 ESTAT_ADD(rxbds_empty);
9993 ESTAT_ADD(rx_discards);
9994 ESTAT_ADD(rx_errors);
9995 ESTAT_ADD(rx_threshold_hit);
9997 ESTAT_ADD(dma_readq_full);
9998 ESTAT_ADD(dma_read_prioq_full);
9999 ESTAT_ADD(tx_comp_queue_full);
10001 ESTAT_ADD(ring_set_send_prod_index);
10002 ESTAT_ADD(ring_status_update);
10003 ESTAT_ADD(nic_irqs);
10004 ESTAT_ADD(nic_avoided_irqs);
10005 ESTAT_ADD(nic_tx_threshold_hit);
10007 ESTAT_ADD(mbuf_lwm_thresh_hit);
10012 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
10013 struct rtnl_link_stats64 *stats)
10015 struct tg3 *tp = netdev_priv(dev);
10016 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
10017 struct tg3_hw_stats *hw_stats = tp->hw_stats;
10022 stats->rx_packets = old_stats->rx_packets +
10023 get_stat64(&hw_stats->rx_ucast_packets) +
10024 get_stat64(&hw_stats->rx_mcast_packets) +
10025 get_stat64(&hw_stats->rx_bcast_packets);
10027 stats->tx_packets = old_stats->tx_packets +
10028 get_stat64(&hw_stats->tx_ucast_packets) +
10029 get_stat64(&hw_stats->tx_mcast_packets) +
10030 get_stat64(&hw_stats->tx_bcast_packets);
10032 stats->rx_bytes = old_stats->rx_bytes +
10033 get_stat64(&hw_stats->rx_octets);
10034 stats->tx_bytes = old_stats->tx_bytes +
10035 get_stat64(&hw_stats->tx_octets);
10037 stats->rx_errors = old_stats->rx_errors +
10038 get_stat64(&hw_stats->rx_errors);
10039 stats->tx_errors = old_stats->tx_errors +
10040 get_stat64(&hw_stats->tx_errors) +
10041 get_stat64(&hw_stats->tx_mac_errors) +
10042 get_stat64(&hw_stats->tx_carrier_sense_errors) +
10043 get_stat64(&hw_stats->tx_discards);
10045 stats->multicast = old_stats->multicast +
10046 get_stat64(&hw_stats->rx_mcast_packets);
10047 stats->collisions = old_stats->collisions +
10048 get_stat64(&hw_stats->tx_collisions);
10050 stats->rx_length_errors = old_stats->rx_length_errors +
10051 get_stat64(&hw_stats->rx_frame_too_long_errors) +
10052 get_stat64(&hw_stats->rx_undersize_packets);
10054 stats->rx_over_errors = old_stats->rx_over_errors +
10055 get_stat64(&hw_stats->rxbds_empty);
10056 stats->rx_frame_errors = old_stats->rx_frame_errors +
10057 get_stat64(&hw_stats->rx_align_errors);
10058 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
10059 get_stat64(&hw_stats->tx_discards);
10060 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
10061 get_stat64(&hw_stats->tx_carrier_sense_errors);
10063 stats->rx_crc_errors = old_stats->rx_crc_errors +
10064 calc_crc_errors(tp);
10066 stats->rx_missed_errors = old_stats->rx_missed_errors +
10067 get_stat64(&hw_stats->rx_discards);
10069 stats->rx_dropped = tp->rx_dropped;
10070 stats->tx_dropped = tp->tx_dropped;
10075 static inline u32 calc_crc(unsigned char *buf, int len)
10083 for (j = 0; j < len; j++) {
10086 for (k = 0; k < 8; k++) {
10099 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
10101 /* accept or reject all multicast frames */
10102 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
10103 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
10104 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
10105 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
10108 static void __tg3_set_rx_mode(struct net_device *dev)
10110 struct tg3 *tp = netdev_priv(dev);
10113 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
10114 RX_MODE_KEEP_VLAN_TAG);
10116 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
10117 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
10120 if (!tg3_flag(tp, ENABLE_ASF))
10121 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
10124 if (dev->flags & IFF_PROMISC) {
10125 /* Promiscuous mode. */
10126 rx_mode |= RX_MODE_PROMISC;
10127 } else if (dev->flags & IFF_ALLMULTI) {
10128 /* Accept all multicast. */
10129 tg3_set_multi(tp, 1);
10130 } else if (netdev_mc_empty(dev)) {
10131 /* Reject all multicast. */
10132 tg3_set_multi(tp, 0);
10134 /* Accept one or more multicast(s). */
10135 struct netdev_hw_addr *ha;
10136 u32 mc_filter[4] = { 0, };
10141 netdev_for_each_mc_addr(ha, dev) {
10142 crc = calc_crc(ha->addr, ETH_ALEN);
10144 regidx = (bit & 0x60) >> 5;
10146 mc_filter[regidx] |= (1 << bit);
10149 tw32(MAC_HASH_REG_0, mc_filter[0]);
10150 tw32(MAC_HASH_REG_1, mc_filter[1]);
10151 tw32(MAC_HASH_REG_2, mc_filter[2]);
10152 tw32(MAC_HASH_REG_3, mc_filter[3]);
10155 if (rx_mode != tp->rx_mode) {
10156 tp->rx_mode = rx_mode;
10157 tw32_f(MAC_RX_MODE, rx_mode);
10162 static void tg3_set_rx_mode(struct net_device *dev)
10164 struct tg3 *tp = netdev_priv(dev);
10166 if (!netif_running(dev))
10169 tg3_full_lock(tp, 0);
10170 __tg3_set_rx_mode(dev);
10171 tg3_full_unlock(tp);
10174 static int tg3_get_regs_len(struct net_device *dev)
10176 return TG3_REG_BLK_SIZE;
10179 static void tg3_get_regs(struct net_device *dev,
10180 struct ethtool_regs *regs, void *_p)
10182 struct tg3 *tp = netdev_priv(dev);
10186 memset(_p, 0, TG3_REG_BLK_SIZE);
10188 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10191 tg3_full_lock(tp, 0);
10193 tg3_dump_legacy_regs(tp, (u32 *)_p);
10195 tg3_full_unlock(tp);
10198 static int tg3_get_eeprom_len(struct net_device *dev)
10200 struct tg3 *tp = netdev_priv(dev);
10202 return tp->nvram_size;
10205 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
10207 struct tg3 *tp = netdev_priv(dev);
10210 u32 i, offset, len, b_offset, b_count;
10213 if (tg3_flag(tp, NO_NVRAM))
10216 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10219 offset = eeprom->offset;
10223 eeprom->magic = TG3_EEPROM_MAGIC;
10226 /* adjustments to start on required 4 byte boundary */
10227 b_offset = offset & 3;
10228 b_count = 4 - b_offset;
10229 if (b_count > len) {
10230 /* i.e. offset=1 len=2 */
10233 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
10236 memcpy(data, ((char *)&val) + b_offset, b_count);
10239 eeprom->len += b_count;
10242 /* read bytes up to the last 4 byte boundary */
10243 pd = &data[eeprom->len];
10244 for (i = 0; i < (len - (len & 3)); i += 4) {
10245 ret = tg3_nvram_read_be32(tp, offset + i, &val);
10250 memcpy(pd + i, &val, 4);
10255 /* read last bytes not ending on 4 byte boundary */
10256 pd = &data[eeprom->len];
10258 b_offset = offset + len - b_count;
10259 ret = tg3_nvram_read_be32(tp, b_offset, &val);
10262 memcpy(pd, &val, b_count);
10263 eeprom->len += b_count;
10268 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
10270 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
10272 struct tg3 *tp = netdev_priv(dev);
10274 u32 offset, len, b_offset, odd_len;
10278 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10281 if (tg3_flag(tp, NO_NVRAM) ||
10282 eeprom->magic != TG3_EEPROM_MAGIC)
10285 offset = eeprom->offset;
10288 if ((b_offset = (offset & 3))) {
10289 /* adjustments to start on required 4 byte boundary */
10290 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
10301 /* adjustments to end on required 4 byte boundary */
10303 len = (len + 3) & ~3;
10304 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
10310 if (b_offset || odd_len) {
10311 buf = kmalloc(len, GFP_KERNEL);
10315 memcpy(buf, &start, 4);
10317 memcpy(buf+len-4, &end, 4);
10318 memcpy(buf + b_offset, data, eeprom->len);
10321 ret = tg3_nvram_write_block(tp, offset, len, buf);
10329 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10331 struct tg3 *tp = netdev_priv(dev);
10333 if (tg3_flag(tp, USE_PHYLIB)) {
10334 struct phy_device *phydev;
10335 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10337 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10338 return phy_ethtool_gset(phydev, cmd);
10341 cmd->supported = (SUPPORTED_Autoneg);
10343 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
10344 cmd->supported |= (SUPPORTED_1000baseT_Half |
10345 SUPPORTED_1000baseT_Full);
10347 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
10348 cmd->supported |= (SUPPORTED_100baseT_Half |
10349 SUPPORTED_100baseT_Full |
10350 SUPPORTED_10baseT_Half |
10351 SUPPORTED_10baseT_Full |
10353 cmd->port = PORT_TP;
10355 cmd->supported |= SUPPORTED_FIBRE;
10356 cmd->port = PORT_FIBRE;
10359 cmd->advertising = tp->link_config.advertising;
10360 if (tg3_flag(tp, PAUSE_AUTONEG)) {
10361 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
10362 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
10363 cmd->advertising |= ADVERTISED_Pause;
10365 cmd->advertising |= ADVERTISED_Pause |
10366 ADVERTISED_Asym_Pause;
10368 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
10369 cmd->advertising |= ADVERTISED_Asym_Pause;
10372 if (netif_running(dev)) {
10373 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
10374 cmd->duplex = tp->link_config.active_duplex;
10376 ethtool_cmd_speed_set(cmd, SPEED_INVALID);
10377 cmd->duplex = DUPLEX_INVALID;
10379 cmd->phy_address = tp->phy_addr;
10380 cmd->transceiver = XCVR_INTERNAL;
10381 cmd->autoneg = tp->link_config.autoneg;
10387 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10389 struct tg3 *tp = netdev_priv(dev);
10390 u32 speed = ethtool_cmd_speed(cmd);
10392 if (tg3_flag(tp, USE_PHYLIB)) {
10393 struct phy_device *phydev;
10394 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10396 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10397 return phy_ethtool_sset(phydev, cmd);
10400 if (cmd->autoneg != AUTONEG_ENABLE &&
10401 cmd->autoneg != AUTONEG_DISABLE)
10404 if (cmd->autoneg == AUTONEG_DISABLE &&
10405 cmd->duplex != DUPLEX_FULL &&
10406 cmd->duplex != DUPLEX_HALF)
10409 if (cmd->autoneg == AUTONEG_ENABLE) {
10410 u32 mask = ADVERTISED_Autoneg |
10412 ADVERTISED_Asym_Pause;
10414 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
10415 mask |= ADVERTISED_1000baseT_Half |
10416 ADVERTISED_1000baseT_Full;
10418 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
10419 mask |= ADVERTISED_100baseT_Half |
10420 ADVERTISED_100baseT_Full |
10421 ADVERTISED_10baseT_Half |
10422 ADVERTISED_10baseT_Full |
10425 mask |= ADVERTISED_FIBRE;
10427 if (cmd->advertising & ~mask)
10430 mask &= (ADVERTISED_1000baseT_Half |
10431 ADVERTISED_1000baseT_Full |
10432 ADVERTISED_100baseT_Half |
10433 ADVERTISED_100baseT_Full |
10434 ADVERTISED_10baseT_Half |
10435 ADVERTISED_10baseT_Full);
10437 cmd->advertising &= mask;
10439 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
10440 if (speed != SPEED_1000)
10443 if (cmd->duplex != DUPLEX_FULL)
10446 if (speed != SPEED_100 &&
10452 tg3_full_lock(tp, 0);
10454 tp->link_config.autoneg = cmd->autoneg;
10455 if (cmd->autoneg == AUTONEG_ENABLE) {
10456 tp->link_config.advertising = (cmd->advertising |
10457 ADVERTISED_Autoneg);
10458 tp->link_config.speed = SPEED_INVALID;
10459 tp->link_config.duplex = DUPLEX_INVALID;
10461 tp->link_config.advertising = 0;
10462 tp->link_config.speed = speed;
10463 tp->link_config.duplex = cmd->duplex;
10466 tp->link_config.orig_speed = tp->link_config.speed;
10467 tp->link_config.orig_duplex = tp->link_config.duplex;
10468 tp->link_config.orig_autoneg = tp->link_config.autoneg;
10470 if (netif_running(dev))
10471 tg3_setup_phy(tp, 1);
10473 tg3_full_unlock(tp);
10478 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
10480 struct tg3 *tp = netdev_priv(dev);
10482 strcpy(info->driver, DRV_MODULE_NAME);
10483 strcpy(info->version, DRV_MODULE_VERSION);
10484 strcpy(info->fw_version, tp->fw_ver);
10485 strcpy(info->bus_info, pci_name(tp->pdev));
10488 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10490 struct tg3 *tp = netdev_priv(dev);
10492 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
10493 wol->supported = WAKE_MAGIC;
10495 wol->supported = 0;
10497 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
10498 wol->wolopts = WAKE_MAGIC;
10499 memset(&wol->sopass, 0, sizeof(wol->sopass));
10502 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10504 struct tg3 *tp = netdev_priv(dev);
10505 struct device *dp = &tp->pdev->dev;
10507 if (wol->wolopts & ~WAKE_MAGIC)
10509 if ((wol->wolopts & WAKE_MAGIC) &&
10510 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
10513 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
10515 spin_lock_bh(&tp->lock);
10516 if (device_may_wakeup(dp))
10517 tg3_flag_set(tp, WOL_ENABLE);
10519 tg3_flag_clear(tp, WOL_ENABLE);
10520 spin_unlock_bh(&tp->lock);
10525 static u32 tg3_get_msglevel(struct net_device *dev)
10527 struct tg3 *tp = netdev_priv(dev);
10528 return tp->msg_enable;
10531 static void tg3_set_msglevel(struct net_device *dev, u32 value)
10533 struct tg3 *tp = netdev_priv(dev);
10534 tp->msg_enable = value;
10537 static int tg3_nway_reset(struct net_device *dev)
10539 struct tg3 *tp = netdev_priv(dev);
10542 if (!netif_running(dev))
10545 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10548 if (tg3_flag(tp, USE_PHYLIB)) {
10549 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10551 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
10555 spin_lock_bh(&tp->lock);
10557 tg3_readphy(tp, MII_BMCR, &bmcr);
10558 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10559 ((bmcr & BMCR_ANENABLE) ||
10560 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
10561 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10565 spin_unlock_bh(&tp->lock);
10571 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10573 struct tg3 *tp = netdev_priv(dev);
10575 ering->rx_max_pending = tp->rx_std_ring_mask;
10576 if (tg3_flag(tp, JUMBO_RING_ENABLE))
10577 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
10579 ering->rx_jumbo_max_pending = 0;
10581 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10583 ering->rx_pending = tp->rx_pending;
10584 if (tg3_flag(tp, JUMBO_RING_ENABLE))
10585 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10587 ering->rx_jumbo_pending = 0;
10589 ering->tx_pending = tp->napi[0].tx_pending;
10592 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10594 struct tg3 *tp = netdev_priv(dev);
10595 int i, irq_sync = 0, err = 0;
10597 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
10598 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
10599 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10600 (ering->tx_pending <= MAX_SKB_FRAGS) ||
10601 (tg3_flag(tp, TSO_BUG) &&
10602 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10605 if (netif_running(dev)) {
10607 tg3_netif_stop(tp);
10611 tg3_full_lock(tp, irq_sync);
10613 tp->rx_pending = ering->rx_pending;
10615 if (tg3_flag(tp, MAX_RXPEND_64) &&
10616 tp->rx_pending > 63)
10617 tp->rx_pending = 63;
10618 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10620 for (i = 0; i < tp->irq_max; i++)
10621 tp->napi[i].tx_pending = ering->tx_pending;
10623 if (netif_running(dev)) {
10624 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10625 err = tg3_restart_hw(tp, 1);
10627 tg3_netif_start(tp);
10630 tg3_full_unlock(tp);
10632 if (irq_sync && !err)
10638 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10640 struct tg3 *tp = netdev_priv(dev);
10642 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
10644 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10645 epause->rx_pause = 1;
10647 epause->rx_pause = 0;
10649 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10650 epause->tx_pause = 1;
10652 epause->tx_pause = 0;
10655 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10657 struct tg3 *tp = netdev_priv(dev);
10660 if (tg3_flag(tp, USE_PHYLIB)) {
10662 struct phy_device *phydev;
10664 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10666 if (!(phydev->supported & SUPPORTED_Pause) ||
10667 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10668 (epause->rx_pause != epause->tx_pause)))
10671 tp->link_config.flowctrl = 0;
10672 if (epause->rx_pause) {
10673 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10675 if (epause->tx_pause) {
10676 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10677 newadv = ADVERTISED_Pause;
10679 newadv = ADVERTISED_Pause |
10680 ADVERTISED_Asym_Pause;
10681 } else if (epause->tx_pause) {
10682 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10683 newadv = ADVERTISED_Asym_Pause;
10687 if (epause->autoneg)
10688 tg3_flag_set(tp, PAUSE_AUTONEG);
10690 tg3_flag_clear(tp, PAUSE_AUTONEG);
10692 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
10693 u32 oldadv = phydev->advertising &
10694 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10695 if (oldadv != newadv) {
10696 phydev->advertising &=
10697 ~(ADVERTISED_Pause |
10698 ADVERTISED_Asym_Pause);
10699 phydev->advertising |= newadv;
10700 if (phydev->autoneg) {
10702 * Always renegotiate the link to
10703 * inform our link partner of our
10704 * flow control settings, even if the
10705 * flow control is forced. Let
10706 * tg3_adjust_link() do the final
10707 * flow control setup.
10709 return phy_start_aneg(phydev);
10713 if (!epause->autoneg)
10714 tg3_setup_flow_control(tp, 0, 0);
10716 tp->link_config.orig_advertising &=
10717 ~(ADVERTISED_Pause |
10718 ADVERTISED_Asym_Pause);
10719 tp->link_config.orig_advertising |= newadv;
10724 if (netif_running(dev)) {
10725 tg3_netif_stop(tp);
10729 tg3_full_lock(tp, irq_sync);
10731 if (epause->autoneg)
10732 tg3_flag_set(tp, PAUSE_AUTONEG);
10734 tg3_flag_clear(tp, PAUSE_AUTONEG);
10735 if (epause->rx_pause)
10736 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10738 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10739 if (epause->tx_pause)
10740 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10742 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10744 if (netif_running(dev)) {
10745 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10746 err = tg3_restart_hw(tp, 1);
10748 tg3_netif_start(tp);
10751 tg3_full_unlock(tp);
10757 static int tg3_get_sset_count(struct net_device *dev, int sset)
10761 return TG3_NUM_TEST;
10763 return TG3_NUM_STATS;
10765 return -EOPNOTSUPP;
10769 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10771 switch (stringset) {
10773 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
10776 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
10779 WARN_ON(1); /* we need a WARN() */
10784 static int tg3_set_phys_id(struct net_device *dev,
10785 enum ethtool_phys_id_state state)
10787 struct tg3 *tp = netdev_priv(dev);
10789 if (!netif_running(tp->dev))
10793 case ETHTOOL_ID_ACTIVE:
10794 return 1; /* cycle on/off once per second */
10796 case ETHTOOL_ID_ON:
10797 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10798 LED_CTRL_1000MBPS_ON |
10799 LED_CTRL_100MBPS_ON |
10800 LED_CTRL_10MBPS_ON |
10801 LED_CTRL_TRAFFIC_OVERRIDE |
10802 LED_CTRL_TRAFFIC_BLINK |
10803 LED_CTRL_TRAFFIC_LED);
10806 case ETHTOOL_ID_OFF:
10807 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10808 LED_CTRL_TRAFFIC_OVERRIDE);
10811 case ETHTOOL_ID_INACTIVE:
10812 tw32(MAC_LED_CTRL, tp->led_ctrl);
10819 static void tg3_get_ethtool_stats(struct net_device *dev,
10820 struct ethtool_stats *estats, u64 *tmp_stats)
10822 struct tg3 *tp = netdev_priv(dev);
10823 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10826 static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
10830 u32 offset = 0, len = 0;
10833 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
10836 if (magic == TG3_EEPROM_MAGIC) {
10837 for (offset = TG3_NVM_DIR_START;
10838 offset < TG3_NVM_DIR_END;
10839 offset += TG3_NVM_DIRENT_SIZE) {
10840 if (tg3_nvram_read(tp, offset, &val))
10843 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
10844 TG3_NVM_DIRTYPE_EXTVPD)
10848 if (offset != TG3_NVM_DIR_END) {
10849 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
10850 if (tg3_nvram_read(tp, offset + 4, &offset))
10853 offset = tg3_nvram_logical_addr(tp, offset);
10857 if (!offset || !len) {
10858 offset = TG3_NVM_VPD_OFF;
10859 len = TG3_NVM_VPD_LEN;
10862 buf = kmalloc(len, GFP_KERNEL);
10866 if (magic == TG3_EEPROM_MAGIC) {
10867 for (i = 0; i < len; i += 4) {
10868 /* The data is in little-endian format in NVRAM.
10869 * Use the big-endian read routines to preserve
10870 * the byte order as it exists in NVRAM.
10872 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
10878 unsigned int pos = 0;
10880 ptr = (u8 *)&buf[0];
10881 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
10882 cnt = pci_read_vpd(tp->pdev, pos,
10884 if (cnt == -ETIMEDOUT || cnt == -EINTR)
10902 #define NVRAM_TEST_SIZE 0x100
10903 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10904 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10905 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10906 #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
10907 #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
10908 #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
10909 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10910 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10912 static int tg3_test_nvram(struct tg3 *tp)
10914 u32 csum, magic, len;
10916 int i, j, k, err = 0, size;
10918 if (tg3_flag(tp, NO_NVRAM))
10921 if (tg3_nvram_read(tp, 0, &magic) != 0)
10924 if (magic == TG3_EEPROM_MAGIC)
10925 size = NVRAM_TEST_SIZE;
10926 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10927 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10928 TG3_EEPROM_SB_FORMAT_1) {
10929 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10930 case TG3_EEPROM_SB_REVISION_0:
10931 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10933 case TG3_EEPROM_SB_REVISION_2:
10934 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10936 case TG3_EEPROM_SB_REVISION_3:
10937 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10939 case TG3_EEPROM_SB_REVISION_4:
10940 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
10942 case TG3_EEPROM_SB_REVISION_5:
10943 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
10945 case TG3_EEPROM_SB_REVISION_6:
10946 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
10953 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10954 size = NVRAM_SELFBOOT_HW_SIZE;
10958 buf = kmalloc(size, GFP_KERNEL);
10963 for (i = 0, j = 0; i < size; i += 4, j++) {
10964 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10971 /* Selfboot format */
10972 magic = be32_to_cpu(buf[0]);
10973 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10974 TG3_EEPROM_MAGIC_FW) {
10975 u8 *buf8 = (u8 *) buf, csum8 = 0;
10977 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10978 TG3_EEPROM_SB_REVISION_2) {
10979 /* For rev 2, the csum doesn't include the MBA. */
10980 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10982 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10985 for (i = 0; i < size; i++)
10998 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10999 TG3_EEPROM_MAGIC_HW) {
11000 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
11001 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
11002 u8 *buf8 = (u8 *) buf;
11004 /* Separate the parity bits and the data bytes. */
11005 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
11006 if ((i == 0) || (i == 8)) {
11010 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
11011 parity[k++] = buf8[i] & msk;
11013 } else if (i == 16) {
11017 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
11018 parity[k++] = buf8[i] & msk;
11021 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
11022 parity[k++] = buf8[i] & msk;
11025 data[j++] = buf8[i];
11029 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
11030 u8 hw8 = hweight8(data[i]);
11032 if ((hw8 & 0x1) && parity[i])
11034 else if (!(hw8 & 0x1) && !parity[i])
11043 /* Bootstrap checksum at offset 0x10 */
11044 csum = calc_crc((unsigned char *) buf, 0x10);
11045 if (csum != le32_to_cpu(buf[0x10/4]))
11048 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
11049 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
11050 if (csum != le32_to_cpu(buf[0xfc/4]))
11055 buf = tg3_vpd_readblock(tp, &len);
11059 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
11061 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
11065 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
11068 i += PCI_VPD_LRDT_TAG_SIZE;
11069 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
11070 PCI_VPD_RO_KEYWORD_CHKSUM);
11074 j += PCI_VPD_INFO_FLD_HDR_SIZE;
11076 for (i = 0; i <= j; i++)
11077 csum8 += ((u8 *)buf)[i];
11091 #define TG3_SERDES_TIMEOUT_SEC 2
11092 #define TG3_COPPER_TIMEOUT_SEC 6
11094 static int tg3_test_link(struct tg3 *tp)
11098 if (!netif_running(tp->dev))
11101 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
11102 max = TG3_SERDES_TIMEOUT_SEC;
11104 max = TG3_COPPER_TIMEOUT_SEC;
11106 for (i = 0; i < max; i++) {
11107 if (netif_carrier_ok(tp->dev))
11110 if (msleep_interruptible(1000))
11117 /* Only test the commonly used registers */
11118 static int tg3_test_registers(struct tg3 *tp)
11120 int i, is_5705, is_5750;
11121 u32 offset, read_mask, write_mask, val, save_val, read_val;
11125 #define TG3_FL_5705 0x1
11126 #define TG3_FL_NOT_5705 0x2
11127 #define TG3_FL_NOT_5788 0x4
11128 #define TG3_FL_NOT_5750 0x8
11132 /* MAC Control Registers */
11133 { MAC_MODE, TG3_FL_NOT_5705,
11134 0x00000000, 0x00ef6f8c },
11135 { MAC_MODE, TG3_FL_5705,
11136 0x00000000, 0x01ef6b8c },
11137 { MAC_STATUS, TG3_FL_NOT_5705,
11138 0x03800107, 0x00000000 },
11139 { MAC_STATUS, TG3_FL_5705,
11140 0x03800100, 0x00000000 },
11141 { MAC_ADDR_0_HIGH, 0x0000,
11142 0x00000000, 0x0000ffff },
11143 { MAC_ADDR_0_LOW, 0x0000,
11144 0x00000000, 0xffffffff },
11145 { MAC_RX_MTU_SIZE, 0x0000,
11146 0x00000000, 0x0000ffff },
11147 { MAC_TX_MODE, 0x0000,
11148 0x00000000, 0x00000070 },
11149 { MAC_TX_LENGTHS, 0x0000,
11150 0x00000000, 0x00003fff },
11151 { MAC_RX_MODE, TG3_FL_NOT_5705,
11152 0x00000000, 0x000007fc },
11153 { MAC_RX_MODE, TG3_FL_5705,
11154 0x00000000, 0x000007dc },
11155 { MAC_HASH_REG_0, 0x0000,
11156 0x00000000, 0xffffffff },
11157 { MAC_HASH_REG_1, 0x0000,
11158 0x00000000, 0xffffffff },
11159 { MAC_HASH_REG_2, 0x0000,
11160 0x00000000, 0xffffffff },
11161 { MAC_HASH_REG_3, 0x0000,
11162 0x00000000, 0xffffffff },
11164 /* Receive Data and Receive BD Initiator Control Registers. */
11165 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
11166 0x00000000, 0xffffffff },
11167 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
11168 0x00000000, 0xffffffff },
11169 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
11170 0x00000000, 0x00000003 },
11171 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
11172 0x00000000, 0xffffffff },
11173 { RCVDBDI_STD_BD+0, 0x0000,
11174 0x00000000, 0xffffffff },
11175 { RCVDBDI_STD_BD+4, 0x0000,
11176 0x00000000, 0xffffffff },
11177 { RCVDBDI_STD_BD+8, 0x0000,
11178 0x00000000, 0xffff0002 },
11179 { RCVDBDI_STD_BD+0xc, 0x0000,
11180 0x00000000, 0xffffffff },
11182 /* Receive BD Initiator Control Registers. */
11183 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
11184 0x00000000, 0xffffffff },
11185 { RCVBDI_STD_THRESH, TG3_FL_5705,
11186 0x00000000, 0x000003ff },
11187 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
11188 0x00000000, 0xffffffff },
11190 /* Host Coalescing Control Registers. */
11191 { HOSTCC_MODE, TG3_FL_NOT_5705,
11192 0x00000000, 0x00000004 },
11193 { HOSTCC_MODE, TG3_FL_5705,
11194 0x00000000, 0x000000f6 },
11195 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
11196 0x00000000, 0xffffffff },
11197 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
11198 0x00000000, 0x000003ff },
11199 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
11200 0x00000000, 0xffffffff },
11201 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
11202 0x00000000, 0x000003ff },
11203 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
11204 0x00000000, 0xffffffff },
11205 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
11206 0x00000000, 0x000000ff },
11207 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
11208 0x00000000, 0xffffffff },
11209 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
11210 0x00000000, 0x000000ff },
11211 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
11212 0x00000000, 0xffffffff },
11213 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
11214 0x00000000, 0xffffffff },
11215 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
11216 0x00000000, 0xffffffff },
11217 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
11218 0x00000000, 0x000000ff },
11219 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
11220 0x00000000, 0xffffffff },
11221 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
11222 0x00000000, 0x000000ff },
11223 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
11224 0x00000000, 0xffffffff },
11225 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
11226 0x00000000, 0xffffffff },
11227 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
11228 0x00000000, 0xffffffff },
11229 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
11230 0x00000000, 0xffffffff },
11231 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
11232 0x00000000, 0xffffffff },
11233 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
11234 0xffffffff, 0x00000000 },
11235 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
11236 0xffffffff, 0x00000000 },
11238 /* Buffer Manager Control Registers. */
11239 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
11240 0x00000000, 0x007fff80 },
11241 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
11242 0x00000000, 0x007fffff },
11243 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
11244 0x00000000, 0x0000003f },
11245 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
11246 0x00000000, 0x000001ff },
11247 { BUFMGR_MB_HIGH_WATER, 0x0000,
11248 0x00000000, 0x000001ff },
11249 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
11250 0xffffffff, 0x00000000 },
11251 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
11252 0xffffffff, 0x00000000 },
11254 /* Mailbox Registers */
11255 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
11256 0x00000000, 0x000001ff },
11257 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
11258 0x00000000, 0x000001ff },
11259 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
11260 0x00000000, 0x000007ff },
11261 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
11262 0x00000000, 0x000001ff },
11264 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
11267 is_5705 = is_5750 = 0;
11268 if (tg3_flag(tp, 5705_PLUS)) {
11270 if (tg3_flag(tp, 5750_PLUS))
11274 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
11275 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
11278 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
11281 if (tg3_flag(tp, IS_5788) &&
11282 (reg_tbl[i].flags & TG3_FL_NOT_5788))
11285 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
11288 offset = (u32) reg_tbl[i].offset;
11289 read_mask = reg_tbl[i].read_mask;
11290 write_mask = reg_tbl[i].write_mask;
11292 /* Save the original register content */
11293 save_val = tr32(offset);
11295 /* Determine the read-only value. */
11296 read_val = save_val & read_mask;
11298 /* Write zero to the register, then make sure the read-only bits
11299 * are not changed and the read/write bits are all zeros.
11303 val = tr32(offset);
11305 /* Test the read-only and read/write bits. */
11306 if (((val & read_mask) != read_val) || (val & write_mask))
11309 /* Write ones to all the bits defined by RdMask and WrMask, then
11310 * make sure the read-only bits are not changed and the
11311 * read/write bits are all ones.
11313 tw32(offset, read_mask | write_mask);
11315 val = tr32(offset);
11317 /* Test the read-only bits. */
11318 if ((val & read_mask) != read_val)
11321 /* Test the read/write bits. */
11322 if ((val & write_mask) != write_mask)
11325 tw32(offset, save_val);
11331 if (netif_msg_hw(tp))
11332 netdev_err(tp->dev,
11333 "Register test failed at offset %x\n", offset);
11334 tw32(offset, save_val);
11338 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
11340 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
11344 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
11345 for (j = 0; j < len; j += 4) {
11348 tg3_write_mem(tp, offset + j, test_pattern[i]);
11349 tg3_read_mem(tp, offset + j, &val);
11350 if (val != test_pattern[i])
11357 static int tg3_test_memory(struct tg3 *tp)
11359 static struct mem_entry {
11362 } mem_tbl_570x[] = {
11363 { 0x00000000, 0x00b50},
11364 { 0x00002000, 0x1c000},
11365 { 0xffffffff, 0x00000}
11366 }, mem_tbl_5705[] = {
11367 { 0x00000100, 0x0000c},
11368 { 0x00000200, 0x00008},
11369 { 0x00004000, 0x00800},
11370 { 0x00006000, 0x01000},
11371 { 0x00008000, 0x02000},
11372 { 0x00010000, 0x0e000},
11373 { 0xffffffff, 0x00000}
11374 }, mem_tbl_5755[] = {
11375 { 0x00000200, 0x00008},
11376 { 0x00004000, 0x00800},
11377 { 0x00006000, 0x00800},
11378 { 0x00008000, 0x02000},
11379 { 0x00010000, 0x0c000},
11380 { 0xffffffff, 0x00000}
11381 }, mem_tbl_5906[] = {
11382 { 0x00000200, 0x00008},
11383 { 0x00004000, 0x00400},
11384 { 0x00006000, 0x00400},
11385 { 0x00008000, 0x01000},
11386 { 0x00010000, 0x01000},
11387 { 0xffffffff, 0x00000}
11388 }, mem_tbl_5717[] = {
11389 { 0x00000200, 0x00008},
11390 { 0x00010000, 0x0a000},
11391 { 0x00020000, 0x13c00},
11392 { 0xffffffff, 0x00000}
11393 }, mem_tbl_57765[] = {
11394 { 0x00000200, 0x00008},
11395 { 0x00004000, 0x00800},
11396 { 0x00006000, 0x09800},
11397 { 0x00010000, 0x0a000},
11398 { 0xffffffff, 0x00000}
11400 struct mem_entry *mem_tbl;
11404 if (tg3_flag(tp, 5717_PLUS))
11405 mem_tbl = mem_tbl_5717;
11406 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11407 mem_tbl = mem_tbl_57765;
11408 else if (tg3_flag(tp, 5755_PLUS))
11409 mem_tbl = mem_tbl_5755;
11410 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11411 mem_tbl = mem_tbl_5906;
11412 else if (tg3_flag(tp, 5705_PLUS))
11413 mem_tbl = mem_tbl_5705;
11415 mem_tbl = mem_tbl_570x;
11417 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
11418 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
11426 #define TG3_TSO_MSS 500
11428 #define TG3_TSO_IP_HDR_LEN 20
11429 #define TG3_TSO_TCP_HDR_LEN 20
11430 #define TG3_TSO_TCP_OPT_LEN 12
11432 static const u8 tg3_tso_header[] = {
11434 0x45, 0x00, 0x00, 0x00,
11435 0x00, 0x00, 0x40, 0x00,
11436 0x40, 0x06, 0x00, 0x00,
11437 0x0a, 0x00, 0x00, 0x01,
11438 0x0a, 0x00, 0x00, 0x02,
11439 0x0d, 0x00, 0xe0, 0x00,
11440 0x00, 0x00, 0x01, 0x00,
11441 0x00, 0x00, 0x02, 0x00,
11442 0x80, 0x10, 0x10, 0x00,
11443 0x14, 0x09, 0x00, 0x00,
11444 0x01, 0x01, 0x08, 0x0a,
11445 0x11, 0x11, 0x11, 0x11,
11446 0x11, 0x11, 0x11, 0x11,
11449 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
11451 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
11452 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
11454 struct sk_buff *skb, *rx_skb;
11457 int num_pkts, tx_len, rx_len, i, err;
11458 struct tg3_rx_buffer_desc *desc;
11459 struct tg3_napi *tnapi, *rnapi;
11460 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
11462 tnapi = &tp->napi[0];
11463 rnapi = &tp->napi[0];
11464 if (tp->irq_cnt > 1) {
11465 if (tg3_flag(tp, ENABLE_RSS))
11466 rnapi = &tp->napi[1];
11467 if (tg3_flag(tp, ENABLE_TSS))
11468 tnapi = &tp->napi[1];
11470 coal_now = tnapi->coal_now | rnapi->coal_now;
11475 skb = netdev_alloc_skb(tp->dev, tx_len);
11479 tx_data = skb_put(skb, tx_len);
11480 memcpy(tx_data, tp->dev->dev_addr, 6);
11481 memset(tx_data + 6, 0x0, 8);
11483 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
11485 if (tso_loopback) {
11486 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
11488 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
11489 TG3_TSO_TCP_OPT_LEN;
11491 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
11492 sizeof(tg3_tso_header));
11495 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
11496 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
11498 /* Set the total length field in the IP header */
11499 iph->tot_len = htons((u16)(mss + hdr_len));
11501 base_flags = (TXD_FLAG_CPU_PRE_DMA |
11502 TXD_FLAG_CPU_POST_DMA);
11504 if (tg3_flag(tp, HW_TSO_1) ||
11505 tg3_flag(tp, HW_TSO_2) ||
11506 tg3_flag(tp, HW_TSO_3)) {
11508 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
11509 th = (struct tcphdr *)&tx_data[val];
11512 base_flags |= TXD_FLAG_TCPUDP_CSUM;
11514 if (tg3_flag(tp, HW_TSO_3)) {
11515 mss |= (hdr_len & 0xc) << 12;
11516 if (hdr_len & 0x10)
11517 base_flags |= 0x00000010;
11518 base_flags |= (hdr_len & 0x3e0) << 5;
11519 } else if (tg3_flag(tp, HW_TSO_2))
11520 mss |= hdr_len << 9;
11521 else if (tg3_flag(tp, HW_TSO_1) ||
11522 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
11523 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
11525 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
11528 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
11531 data_off = ETH_HLEN;
11534 for (i = data_off; i < tx_len; i++)
11535 tx_data[i] = (u8) (i & 0xff);
11537 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
11538 if (pci_dma_mapping_error(tp->pdev, map)) {
11539 dev_kfree_skb(skb);
11543 val = tnapi->tx_prod;
11544 tnapi->tx_buffers[val].skb = skb;
11545 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
11547 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11552 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
11554 budget = tg3_tx_avail(tnapi);
11555 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
11556 base_flags | TXD_FLAG_END, mss, 0)) {
11557 tnapi->tx_buffers[val].skb = NULL;
11558 dev_kfree_skb(skb);
11564 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
11565 tr32_mailbox(tnapi->prodmbox);
11569 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
11570 for (i = 0; i < 35; i++) {
11571 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11576 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
11577 rx_idx = rnapi->hw_status->idx[0].rx_producer;
11578 if ((tx_idx == tnapi->tx_prod) &&
11579 (rx_idx == (rx_start_idx + num_pkts)))
11583 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
11584 dev_kfree_skb(skb);
11586 if (tx_idx != tnapi->tx_prod)
11589 if (rx_idx != rx_start_idx + num_pkts)
11593 while (rx_idx != rx_start_idx) {
11594 desc = &rnapi->rx_rcb[rx_start_idx++];
11595 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
11596 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
11598 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
11599 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
11602 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
11605 if (!tso_loopback) {
11606 if (rx_len != tx_len)
11609 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
11610 if (opaque_key != RXD_OPAQUE_RING_STD)
11613 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
11616 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
11617 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
11618 >> RXD_TCPCSUM_SHIFT != 0xffff) {
11622 if (opaque_key == RXD_OPAQUE_RING_STD) {
11623 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
11624 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
11626 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
11627 rx_skb = tpr->rx_jmb_buffers[desc_idx].skb;
11628 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
11633 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
11634 PCI_DMA_FROMDEVICE);
11636 for (i = data_off; i < rx_len; i++, val++) {
11637 if (*(rx_skb->data + i) != (u8) (val & 0xff))
11644 /* tg3_free_rings will unmap and free the rx_skb */
11649 #define TG3_STD_LOOPBACK_FAILED 1
11650 #define TG3_JMB_LOOPBACK_FAILED 2
11651 #define TG3_TSO_LOOPBACK_FAILED 4
11652 #define TG3_LOOPBACK_FAILED \
11653 (TG3_STD_LOOPBACK_FAILED | \
11654 TG3_JMB_LOOPBACK_FAILED | \
11655 TG3_TSO_LOOPBACK_FAILED)
11657 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
11662 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
11663 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11665 if (!netif_running(tp->dev)) {
11666 data[0] = TG3_LOOPBACK_FAILED;
11667 data[1] = TG3_LOOPBACK_FAILED;
11669 data[2] = TG3_LOOPBACK_FAILED;
11673 err = tg3_reset_hw(tp, 1);
11675 data[0] = TG3_LOOPBACK_FAILED;
11676 data[1] = TG3_LOOPBACK_FAILED;
11678 data[2] = TG3_LOOPBACK_FAILED;
11682 if (tg3_flag(tp, ENABLE_RSS)) {
11685 /* Reroute all rx packets to the 1st queue */
11686 for (i = MAC_RSS_INDIR_TBL_0;
11687 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
11691 /* HW errata - mac loopback fails in some cases on 5780.
11692 * Normal traffic and PHY loopback are not affected by
11693 * errata. Also, the MAC loopback test is deprecated for
11694 * all newer ASIC revisions.
11696 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
11697 !tg3_flag(tp, CPMU_PRESENT)) {
11698 tg3_mac_loopback(tp, true);
11700 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
11701 data[0] |= TG3_STD_LOOPBACK_FAILED;
11703 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11704 tg3_run_loopback(tp, 9000 + ETH_HLEN, false))
11705 data[0] |= TG3_JMB_LOOPBACK_FAILED;
11707 tg3_mac_loopback(tp, false);
11710 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11711 !tg3_flag(tp, USE_PHYLIB)) {
11714 tg3_phy_lpbk_set(tp, 0, false);
11716 /* Wait for link */
11717 for (i = 0; i < 100; i++) {
11718 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
11723 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
11724 data[1] |= TG3_STD_LOOPBACK_FAILED;
11725 if (tg3_flag(tp, TSO_CAPABLE) &&
11726 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
11727 data[1] |= TG3_TSO_LOOPBACK_FAILED;
11728 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11729 tg3_run_loopback(tp, 9000 + ETH_HLEN, false))
11730 data[1] |= TG3_JMB_LOOPBACK_FAILED;
11733 tg3_phy_lpbk_set(tp, 0, true);
11735 /* All link indications report up, but the hardware
11736 * isn't really ready for about 20 msec. Double it
11741 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
11742 data[2] |= TG3_STD_LOOPBACK_FAILED;
11743 if (tg3_flag(tp, TSO_CAPABLE) &&
11744 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
11745 data[2] |= TG3_TSO_LOOPBACK_FAILED;
11746 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11747 tg3_run_loopback(tp, 9000 + ETH_HLEN, false))
11748 data[2] |= TG3_JMB_LOOPBACK_FAILED;
11751 /* Re-enable gphy autopowerdown. */
11752 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11753 tg3_phy_toggle_apd(tp, true);
11756 err = (data[0] | data[1] | data[2]) ? -EIO : 0;
11759 tp->phy_flags |= eee_cap;
11764 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11767 struct tg3 *tp = netdev_priv(dev);
11768 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
11770 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
11771 tg3_power_up(tp)) {
11772 etest->flags |= ETH_TEST_FL_FAILED;
11773 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
11777 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11779 if (tg3_test_nvram(tp) != 0) {
11780 etest->flags |= ETH_TEST_FL_FAILED;
11783 if (!doextlpbk && tg3_test_link(tp)) {
11784 etest->flags |= ETH_TEST_FL_FAILED;
11787 if (etest->flags & ETH_TEST_FL_OFFLINE) {
11788 int err, err2 = 0, irq_sync = 0;
11790 if (netif_running(dev)) {
11792 tg3_netif_stop(tp);
11796 tg3_full_lock(tp, irq_sync);
11798 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11799 err = tg3_nvram_lock(tp);
11800 tg3_halt_cpu(tp, RX_CPU_BASE);
11801 if (!tg3_flag(tp, 5705_PLUS))
11802 tg3_halt_cpu(tp, TX_CPU_BASE);
11804 tg3_nvram_unlock(tp);
11806 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
11809 if (tg3_test_registers(tp) != 0) {
11810 etest->flags |= ETH_TEST_FL_FAILED;
11814 if (tg3_test_memory(tp) != 0) {
11815 etest->flags |= ETH_TEST_FL_FAILED;
11820 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
11822 if (tg3_test_loopback(tp, &data[4], doextlpbk))
11823 etest->flags |= ETH_TEST_FL_FAILED;
11825 tg3_full_unlock(tp);
11827 if (tg3_test_interrupt(tp) != 0) {
11828 etest->flags |= ETH_TEST_FL_FAILED;
11832 tg3_full_lock(tp, 0);
11834 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11835 if (netif_running(dev)) {
11836 tg3_flag_set(tp, INIT_COMPLETE);
11837 err2 = tg3_restart_hw(tp, 1);
11839 tg3_netif_start(tp);
11842 tg3_full_unlock(tp);
11844 if (irq_sync && !err2)
11847 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11848 tg3_power_down(tp);
11852 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11854 struct mii_ioctl_data *data = if_mii(ifr);
11855 struct tg3 *tp = netdev_priv(dev);
11858 if (tg3_flag(tp, USE_PHYLIB)) {
11859 struct phy_device *phydev;
11860 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11862 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11863 return phy_mii_ioctl(phydev, ifr, cmd);
11868 data->phy_id = tp->phy_addr;
11871 case SIOCGMIIREG: {
11874 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11875 break; /* We have no PHY */
11877 if (!netif_running(dev))
11880 spin_lock_bh(&tp->lock);
11881 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11882 spin_unlock_bh(&tp->lock);
11884 data->val_out = mii_regval;
11890 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11891 break; /* We have no PHY */
11893 if (!netif_running(dev))
11896 spin_lock_bh(&tp->lock);
11897 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11898 spin_unlock_bh(&tp->lock);
11906 return -EOPNOTSUPP;
11909 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11911 struct tg3 *tp = netdev_priv(dev);
11913 memcpy(ec, &tp->coal, sizeof(*ec));
11917 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11919 struct tg3 *tp = netdev_priv(dev);
11920 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11921 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11923 if (!tg3_flag(tp, 5705_PLUS)) {
11924 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11925 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11926 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11927 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11930 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11931 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11932 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11933 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11934 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11935 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11936 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11937 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11938 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11939 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11942 /* No rx interrupts will be generated if both are zero */
11943 if ((ec->rx_coalesce_usecs == 0) &&
11944 (ec->rx_max_coalesced_frames == 0))
11947 /* No tx interrupts will be generated if both are zero */
11948 if ((ec->tx_coalesce_usecs == 0) &&
11949 (ec->tx_max_coalesced_frames == 0))
11952 /* Only copy relevant parameters, ignore all others. */
11953 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11954 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11955 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11956 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11957 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11958 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11959 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11960 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11961 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11963 if (netif_running(dev)) {
11964 tg3_full_lock(tp, 0);
11965 __tg3_set_coalesce(tp, &tp->coal);
11966 tg3_full_unlock(tp);
11971 static const struct ethtool_ops tg3_ethtool_ops = {
11972 .get_settings = tg3_get_settings,
11973 .set_settings = tg3_set_settings,
11974 .get_drvinfo = tg3_get_drvinfo,
11975 .get_regs_len = tg3_get_regs_len,
11976 .get_regs = tg3_get_regs,
11977 .get_wol = tg3_get_wol,
11978 .set_wol = tg3_set_wol,
11979 .get_msglevel = tg3_get_msglevel,
11980 .set_msglevel = tg3_set_msglevel,
11981 .nway_reset = tg3_nway_reset,
11982 .get_link = ethtool_op_get_link,
11983 .get_eeprom_len = tg3_get_eeprom_len,
11984 .get_eeprom = tg3_get_eeprom,
11985 .set_eeprom = tg3_set_eeprom,
11986 .get_ringparam = tg3_get_ringparam,
11987 .set_ringparam = tg3_set_ringparam,
11988 .get_pauseparam = tg3_get_pauseparam,
11989 .set_pauseparam = tg3_set_pauseparam,
11990 .self_test = tg3_self_test,
11991 .get_strings = tg3_get_strings,
11992 .set_phys_id = tg3_set_phys_id,
11993 .get_ethtool_stats = tg3_get_ethtool_stats,
11994 .get_coalesce = tg3_get_coalesce,
11995 .set_coalesce = tg3_set_coalesce,
11996 .get_sset_count = tg3_get_sset_count,
11999 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
12001 u32 cursize, val, magic;
12003 tp->nvram_size = EEPROM_CHIP_SIZE;
12005 if (tg3_nvram_read(tp, 0, &magic) != 0)
12008 if ((magic != TG3_EEPROM_MAGIC) &&
12009 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
12010 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
12014 * Size the chip by reading offsets at increasing powers of two.
12015 * When we encounter our validation signature, we know the addressing
12016 * has wrapped around, and thus have our chip size.
12020 while (cursize < tp->nvram_size) {
12021 if (tg3_nvram_read(tp, cursize, &val) != 0)
12030 tp->nvram_size = cursize;
12033 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
12037 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
12040 /* Selfboot format */
12041 if (val != TG3_EEPROM_MAGIC) {
12042 tg3_get_eeprom_size(tp);
12046 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
12048 /* This is confusing. We want to operate on the
12049 * 16-bit value at offset 0xf2. The tg3_nvram_read()
12050 * call will read from NVRAM and byteswap the data
12051 * according to the byteswapping settings for all
12052 * other register accesses. This ensures the data we
12053 * want will always reside in the lower 16-bits.
12054 * However, the data in NVRAM is in LE format, which
12055 * means the data from the NVRAM read will always be
12056 * opposite the endianness of the CPU. The 16-bit
12057 * byteswap then brings the data to CPU endianness.
12059 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
12063 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12066 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
12070 nvcfg1 = tr32(NVRAM_CFG1);
12071 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
12072 tg3_flag_set(tp, FLASH);
12074 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12075 tw32(NVRAM_CFG1, nvcfg1);
12078 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12079 tg3_flag(tp, 5780_CLASS)) {
12080 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
12081 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
12082 tp->nvram_jedecnum = JEDEC_ATMEL;
12083 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
12084 tg3_flag_set(tp, NVRAM_BUFFERED);
12086 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
12087 tp->nvram_jedecnum = JEDEC_ATMEL;
12088 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
12090 case FLASH_VENDOR_ATMEL_EEPROM:
12091 tp->nvram_jedecnum = JEDEC_ATMEL;
12092 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12093 tg3_flag_set(tp, NVRAM_BUFFERED);
12095 case FLASH_VENDOR_ST:
12096 tp->nvram_jedecnum = JEDEC_ST;
12097 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
12098 tg3_flag_set(tp, NVRAM_BUFFERED);
12100 case FLASH_VENDOR_SAIFUN:
12101 tp->nvram_jedecnum = JEDEC_SAIFUN;
12102 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
12104 case FLASH_VENDOR_SST_SMALL:
12105 case FLASH_VENDOR_SST_LARGE:
12106 tp->nvram_jedecnum = JEDEC_SST;
12107 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
12111 tp->nvram_jedecnum = JEDEC_ATMEL;
12112 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
12113 tg3_flag_set(tp, NVRAM_BUFFERED);
12117 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
12119 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
12120 case FLASH_5752PAGE_SIZE_256:
12121 tp->nvram_pagesize = 256;
12123 case FLASH_5752PAGE_SIZE_512:
12124 tp->nvram_pagesize = 512;
12126 case FLASH_5752PAGE_SIZE_1K:
12127 tp->nvram_pagesize = 1024;
12129 case FLASH_5752PAGE_SIZE_2K:
12130 tp->nvram_pagesize = 2048;
12132 case FLASH_5752PAGE_SIZE_4K:
12133 tp->nvram_pagesize = 4096;
12135 case FLASH_5752PAGE_SIZE_264:
12136 tp->nvram_pagesize = 264;
12138 case FLASH_5752PAGE_SIZE_528:
12139 tp->nvram_pagesize = 528;
12144 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
12148 nvcfg1 = tr32(NVRAM_CFG1);
12150 /* NVRAM protection for TPM */
12151 if (nvcfg1 & (1 << 27))
12152 tg3_flag_set(tp, PROTECTED_NVRAM);
12154 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12155 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
12156 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
12157 tp->nvram_jedecnum = JEDEC_ATMEL;
12158 tg3_flag_set(tp, NVRAM_BUFFERED);
12160 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12161 tp->nvram_jedecnum = JEDEC_ATMEL;
12162 tg3_flag_set(tp, NVRAM_BUFFERED);
12163 tg3_flag_set(tp, FLASH);
12165 case FLASH_5752VENDOR_ST_M45PE10:
12166 case FLASH_5752VENDOR_ST_M45PE20:
12167 case FLASH_5752VENDOR_ST_M45PE40:
12168 tp->nvram_jedecnum = JEDEC_ST;
12169 tg3_flag_set(tp, NVRAM_BUFFERED);
12170 tg3_flag_set(tp, FLASH);
12174 if (tg3_flag(tp, FLASH)) {
12175 tg3_nvram_get_pagesize(tp, nvcfg1);
12177 /* For eeprom, set pagesize to maximum eeprom size */
12178 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12180 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12181 tw32(NVRAM_CFG1, nvcfg1);
12185 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
12187 u32 nvcfg1, protect = 0;
12189 nvcfg1 = tr32(NVRAM_CFG1);
12191 /* NVRAM protection for TPM */
12192 if (nvcfg1 & (1 << 27)) {
12193 tg3_flag_set(tp, PROTECTED_NVRAM);
12197 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
12199 case FLASH_5755VENDOR_ATMEL_FLASH_1:
12200 case FLASH_5755VENDOR_ATMEL_FLASH_2:
12201 case FLASH_5755VENDOR_ATMEL_FLASH_3:
12202 case FLASH_5755VENDOR_ATMEL_FLASH_5:
12203 tp->nvram_jedecnum = JEDEC_ATMEL;
12204 tg3_flag_set(tp, NVRAM_BUFFERED);
12205 tg3_flag_set(tp, FLASH);
12206 tp->nvram_pagesize = 264;
12207 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
12208 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
12209 tp->nvram_size = (protect ? 0x3e200 :
12210 TG3_NVRAM_SIZE_512KB);
12211 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
12212 tp->nvram_size = (protect ? 0x1f200 :
12213 TG3_NVRAM_SIZE_256KB);
12215 tp->nvram_size = (protect ? 0x1f200 :
12216 TG3_NVRAM_SIZE_128KB);
12218 case FLASH_5752VENDOR_ST_M45PE10:
12219 case FLASH_5752VENDOR_ST_M45PE20:
12220 case FLASH_5752VENDOR_ST_M45PE40:
12221 tp->nvram_jedecnum = JEDEC_ST;
12222 tg3_flag_set(tp, NVRAM_BUFFERED);
12223 tg3_flag_set(tp, FLASH);
12224 tp->nvram_pagesize = 256;
12225 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
12226 tp->nvram_size = (protect ?
12227 TG3_NVRAM_SIZE_64KB :
12228 TG3_NVRAM_SIZE_128KB);
12229 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
12230 tp->nvram_size = (protect ?
12231 TG3_NVRAM_SIZE_64KB :
12232 TG3_NVRAM_SIZE_256KB);
12234 tp->nvram_size = (protect ?
12235 TG3_NVRAM_SIZE_128KB :
12236 TG3_NVRAM_SIZE_512KB);
12241 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
12245 nvcfg1 = tr32(NVRAM_CFG1);
12247 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12248 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
12249 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
12250 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
12251 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
12252 tp->nvram_jedecnum = JEDEC_ATMEL;
12253 tg3_flag_set(tp, NVRAM_BUFFERED);
12254 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12256 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12257 tw32(NVRAM_CFG1, nvcfg1);
12259 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12260 case FLASH_5755VENDOR_ATMEL_FLASH_1:
12261 case FLASH_5755VENDOR_ATMEL_FLASH_2:
12262 case FLASH_5755VENDOR_ATMEL_FLASH_3:
12263 tp->nvram_jedecnum = JEDEC_ATMEL;
12264 tg3_flag_set(tp, NVRAM_BUFFERED);
12265 tg3_flag_set(tp, FLASH);
12266 tp->nvram_pagesize = 264;
12268 case FLASH_5752VENDOR_ST_M45PE10:
12269 case FLASH_5752VENDOR_ST_M45PE20:
12270 case FLASH_5752VENDOR_ST_M45PE40:
12271 tp->nvram_jedecnum = JEDEC_ST;
12272 tg3_flag_set(tp, NVRAM_BUFFERED);
12273 tg3_flag_set(tp, FLASH);
12274 tp->nvram_pagesize = 256;
12279 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
12281 u32 nvcfg1, protect = 0;
12283 nvcfg1 = tr32(NVRAM_CFG1);
12285 /* NVRAM protection for TPM */
12286 if (nvcfg1 & (1 << 27)) {
12287 tg3_flag_set(tp, PROTECTED_NVRAM);
12291 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
12293 case FLASH_5761VENDOR_ATMEL_ADB021D:
12294 case FLASH_5761VENDOR_ATMEL_ADB041D:
12295 case FLASH_5761VENDOR_ATMEL_ADB081D:
12296 case FLASH_5761VENDOR_ATMEL_ADB161D:
12297 case FLASH_5761VENDOR_ATMEL_MDB021D:
12298 case FLASH_5761VENDOR_ATMEL_MDB041D:
12299 case FLASH_5761VENDOR_ATMEL_MDB081D:
12300 case FLASH_5761VENDOR_ATMEL_MDB161D:
12301 tp->nvram_jedecnum = JEDEC_ATMEL;
12302 tg3_flag_set(tp, NVRAM_BUFFERED);
12303 tg3_flag_set(tp, FLASH);
12304 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12305 tp->nvram_pagesize = 256;
12307 case FLASH_5761VENDOR_ST_A_M45PE20:
12308 case FLASH_5761VENDOR_ST_A_M45PE40:
12309 case FLASH_5761VENDOR_ST_A_M45PE80:
12310 case FLASH_5761VENDOR_ST_A_M45PE16:
12311 case FLASH_5761VENDOR_ST_M_M45PE20:
12312 case FLASH_5761VENDOR_ST_M_M45PE40:
12313 case FLASH_5761VENDOR_ST_M_M45PE80:
12314 case FLASH_5761VENDOR_ST_M_M45PE16:
12315 tp->nvram_jedecnum = JEDEC_ST;
12316 tg3_flag_set(tp, NVRAM_BUFFERED);
12317 tg3_flag_set(tp, FLASH);
12318 tp->nvram_pagesize = 256;
12323 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
12326 case FLASH_5761VENDOR_ATMEL_ADB161D:
12327 case FLASH_5761VENDOR_ATMEL_MDB161D:
12328 case FLASH_5761VENDOR_ST_A_M45PE16:
12329 case FLASH_5761VENDOR_ST_M_M45PE16:
12330 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
12332 case FLASH_5761VENDOR_ATMEL_ADB081D:
12333 case FLASH_5761VENDOR_ATMEL_MDB081D:
12334 case FLASH_5761VENDOR_ST_A_M45PE80:
12335 case FLASH_5761VENDOR_ST_M_M45PE80:
12336 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12338 case FLASH_5761VENDOR_ATMEL_ADB041D:
12339 case FLASH_5761VENDOR_ATMEL_MDB041D:
12340 case FLASH_5761VENDOR_ST_A_M45PE40:
12341 case FLASH_5761VENDOR_ST_M_M45PE40:
12342 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12344 case FLASH_5761VENDOR_ATMEL_ADB021D:
12345 case FLASH_5761VENDOR_ATMEL_MDB021D:
12346 case FLASH_5761VENDOR_ST_A_M45PE20:
12347 case FLASH_5761VENDOR_ST_M_M45PE20:
12348 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12354 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
12356 tp->nvram_jedecnum = JEDEC_ATMEL;
12357 tg3_flag_set(tp, NVRAM_BUFFERED);
12358 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12361 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
12365 nvcfg1 = tr32(NVRAM_CFG1);
12367 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12368 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
12369 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
12370 tp->nvram_jedecnum = JEDEC_ATMEL;
12371 tg3_flag_set(tp, NVRAM_BUFFERED);
12372 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12374 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12375 tw32(NVRAM_CFG1, nvcfg1);
12377 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12378 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
12379 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
12380 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
12381 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
12382 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
12383 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
12384 tp->nvram_jedecnum = JEDEC_ATMEL;
12385 tg3_flag_set(tp, NVRAM_BUFFERED);
12386 tg3_flag_set(tp, FLASH);
12388 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12389 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12390 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
12391 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
12392 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12394 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
12395 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
12396 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12398 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
12399 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
12400 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12404 case FLASH_5752VENDOR_ST_M45PE10:
12405 case FLASH_5752VENDOR_ST_M45PE20:
12406 case FLASH_5752VENDOR_ST_M45PE40:
12407 tp->nvram_jedecnum = JEDEC_ST;
12408 tg3_flag_set(tp, NVRAM_BUFFERED);
12409 tg3_flag_set(tp, FLASH);
12411 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12412 case FLASH_5752VENDOR_ST_M45PE10:
12413 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12415 case FLASH_5752VENDOR_ST_M45PE20:
12416 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12418 case FLASH_5752VENDOR_ST_M45PE40:
12419 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12424 tg3_flag_set(tp, NO_NVRAM);
12428 tg3_nvram_get_pagesize(tp, nvcfg1);
12429 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12430 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12434 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
12438 nvcfg1 = tr32(NVRAM_CFG1);
12440 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12441 case FLASH_5717VENDOR_ATMEL_EEPROM:
12442 case FLASH_5717VENDOR_MICRO_EEPROM:
12443 tp->nvram_jedecnum = JEDEC_ATMEL;
12444 tg3_flag_set(tp, NVRAM_BUFFERED);
12445 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12447 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12448 tw32(NVRAM_CFG1, nvcfg1);
12450 case FLASH_5717VENDOR_ATMEL_MDB011D:
12451 case FLASH_5717VENDOR_ATMEL_ADB011B:
12452 case FLASH_5717VENDOR_ATMEL_ADB011D:
12453 case FLASH_5717VENDOR_ATMEL_MDB021D:
12454 case FLASH_5717VENDOR_ATMEL_ADB021B:
12455 case FLASH_5717VENDOR_ATMEL_ADB021D:
12456 case FLASH_5717VENDOR_ATMEL_45USPT:
12457 tp->nvram_jedecnum = JEDEC_ATMEL;
12458 tg3_flag_set(tp, NVRAM_BUFFERED);
12459 tg3_flag_set(tp, FLASH);
12461 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12462 case FLASH_5717VENDOR_ATMEL_MDB021D:
12463 /* Detect size with tg3_nvram_get_size() */
12465 case FLASH_5717VENDOR_ATMEL_ADB021B:
12466 case FLASH_5717VENDOR_ATMEL_ADB021D:
12467 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12470 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12474 case FLASH_5717VENDOR_ST_M_M25PE10:
12475 case FLASH_5717VENDOR_ST_A_M25PE10:
12476 case FLASH_5717VENDOR_ST_M_M45PE10:
12477 case FLASH_5717VENDOR_ST_A_M45PE10:
12478 case FLASH_5717VENDOR_ST_M_M25PE20:
12479 case FLASH_5717VENDOR_ST_A_M25PE20:
12480 case FLASH_5717VENDOR_ST_M_M45PE20:
12481 case FLASH_5717VENDOR_ST_A_M45PE20:
12482 case FLASH_5717VENDOR_ST_25USPT:
12483 case FLASH_5717VENDOR_ST_45USPT:
12484 tp->nvram_jedecnum = JEDEC_ST;
12485 tg3_flag_set(tp, NVRAM_BUFFERED);
12486 tg3_flag_set(tp, FLASH);
12488 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12489 case FLASH_5717VENDOR_ST_M_M25PE20:
12490 case FLASH_5717VENDOR_ST_M_M45PE20:
12491 /* Detect size with tg3_nvram_get_size() */
12493 case FLASH_5717VENDOR_ST_A_M25PE20:
12494 case FLASH_5717VENDOR_ST_A_M45PE20:
12495 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12498 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12503 tg3_flag_set(tp, NO_NVRAM);
12507 tg3_nvram_get_pagesize(tp, nvcfg1);
12508 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12509 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12512 static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
12514 u32 nvcfg1, nvmpinstrp;
12516 nvcfg1 = tr32(NVRAM_CFG1);
12517 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
12519 switch (nvmpinstrp) {
12520 case FLASH_5720_EEPROM_HD:
12521 case FLASH_5720_EEPROM_LD:
12522 tp->nvram_jedecnum = JEDEC_ATMEL;
12523 tg3_flag_set(tp, NVRAM_BUFFERED);
12525 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12526 tw32(NVRAM_CFG1, nvcfg1);
12527 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
12528 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12530 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
12532 case FLASH_5720VENDOR_M_ATMEL_DB011D:
12533 case FLASH_5720VENDOR_A_ATMEL_DB011B:
12534 case FLASH_5720VENDOR_A_ATMEL_DB011D:
12535 case FLASH_5720VENDOR_M_ATMEL_DB021D:
12536 case FLASH_5720VENDOR_A_ATMEL_DB021B:
12537 case FLASH_5720VENDOR_A_ATMEL_DB021D:
12538 case FLASH_5720VENDOR_M_ATMEL_DB041D:
12539 case FLASH_5720VENDOR_A_ATMEL_DB041B:
12540 case FLASH_5720VENDOR_A_ATMEL_DB041D:
12541 case FLASH_5720VENDOR_M_ATMEL_DB081D:
12542 case FLASH_5720VENDOR_A_ATMEL_DB081D:
12543 case FLASH_5720VENDOR_ATMEL_45USPT:
12544 tp->nvram_jedecnum = JEDEC_ATMEL;
12545 tg3_flag_set(tp, NVRAM_BUFFERED);
12546 tg3_flag_set(tp, FLASH);
12548 switch (nvmpinstrp) {
12549 case FLASH_5720VENDOR_M_ATMEL_DB021D:
12550 case FLASH_5720VENDOR_A_ATMEL_DB021B:
12551 case FLASH_5720VENDOR_A_ATMEL_DB021D:
12552 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12554 case FLASH_5720VENDOR_M_ATMEL_DB041D:
12555 case FLASH_5720VENDOR_A_ATMEL_DB041B:
12556 case FLASH_5720VENDOR_A_ATMEL_DB041D:
12557 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12559 case FLASH_5720VENDOR_M_ATMEL_DB081D:
12560 case FLASH_5720VENDOR_A_ATMEL_DB081D:
12561 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12564 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12568 case FLASH_5720VENDOR_M_ST_M25PE10:
12569 case FLASH_5720VENDOR_M_ST_M45PE10:
12570 case FLASH_5720VENDOR_A_ST_M25PE10:
12571 case FLASH_5720VENDOR_A_ST_M45PE10:
12572 case FLASH_5720VENDOR_M_ST_M25PE20:
12573 case FLASH_5720VENDOR_M_ST_M45PE20:
12574 case FLASH_5720VENDOR_A_ST_M25PE20:
12575 case FLASH_5720VENDOR_A_ST_M45PE20:
12576 case FLASH_5720VENDOR_M_ST_M25PE40:
12577 case FLASH_5720VENDOR_M_ST_M45PE40:
12578 case FLASH_5720VENDOR_A_ST_M25PE40:
12579 case FLASH_5720VENDOR_A_ST_M45PE40:
12580 case FLASH_5720VENDOR_M_ST_M25PE80:
12581 case FLASH_5720VENDOR_M_ST_M45PE80:
12582 case FLASH_5720VENDOR_A_ST_M25PE80:
12583 case FLASH_5720VENDOR_A_ST_M45PE80:
12584 case FLASH_5720VENDOR_ST_25USPT:
12585 case FLASH_5720VENDOR_ST_45USPT:
12586 tp->nvram_jedecnum = JEDEC_ST;
12587 tg3_flag_set(tp, NVRAM_BUFFERED);
12588 tg3_flag_set(tp, FLASH);
12590 switch (nvmpinstrp) {
12591 case FLASH_5720VENDOR_M_ST_M25PE20:
12592 case FLASH_5720VENDOR_M_ST_M45PE20:
12593 case FLASH_5720VENDOR_A_ST_M25PE20:
12594 case FLASH_5720VENDOR_A_ST_M45PE20:
12595 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12597 case FLASH_5720VENDOR_M_ST_M25PE40:
12598 case FLASH_5720VENDOR_M_ST_M45PE40:
12599 case FLASH_5720VENDOR_A_ST_M25PE40:
12600 case FLASH_5720VENDOR_A_ST_M45PE40:
12601 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12603 case FLASH_5720VENDOR_M_ST_M25PE80:
12604 case FLASH_5720VENDOR_M_ST_M45PE80:
12605 case FLASH_5720VENDOR_A_ST_M25PE80:
12606 case FLASH_5720VENDOR_A_ST_M45PE80:
12607 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12610 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12615 tg3_flag_set(tp, NO_NVRAM);
12619 tg3_nvram_get_pagesize(tp, nvcfg1);
12620 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12621 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12624 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
12625 static void __devinit tg3_nvram_init(struct tg3 *tp)
12627 tw32_f(GRC_EEPROM_ADDR,
12628 (EEPROM_ADDR_FSM_RESET |
12629 (EEPROM_DEFAULT_CLOCK_PERIOD <<
12630 EEPROM_ADDR_CLKPERD_SHIFT)));
12634 /* Enable seeprom accesses. */
12635 tw32_f(GRC_LOCAL_CTRL,
12636 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
12639 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12640 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
12641 tg3_flag_set(tp, NVRAM);
12643 if (tg3_nvram_lock(tp)) {
12644 netdev_warn(tp->dev,
12645 "Cannot get nvram lock, %s failed\n",
12649 tg3_enable_nvram_access(tp);
12651 tp->nvram_size = 0;
12653 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12654 tg3_get_5752_nvram_info(tp);
12655 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12656 tg3_get_5755_nvram_info(tp);
12657 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12658 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12659 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12660 tg3_get_5787_nvram_info(tp);
12661 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
12662 tg3_get_5761_nvram_info(tp);
12663 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12664 tg3_get_5906_nvram_info(tp);
12665 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12666 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12667 tg3_get_57780_nvram_info(tp);
12668 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12669 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
12670 tg3_get_5717_nvram_info(tp);
12671 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
12672 tg3_get_5720_nvram_info(tp);
12674 tg3_get_nvram_info(tp);
12676 if (tp->nvram_size == 0)
12677 tg3_get_nvram_size(tp);
12679 tg3_disable_nvram_access(tp);
12680 tg3_nvram_unlock(tp);
12683 tg3_flag_clear(tp, NVRAM);
12684 tg3_flag_clear(tp, NVRAM_BUFFERED);
12686 tg3_get_eeprom_size(tp);
12690 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
12691 u32 offset, u32 len, u8 *buf)
12696 for (i = 0; i < len; i += 4) {
12702 memcpy(&data, buf + i, 4);
12705 * The SEEPROM interface expects the data to always be opposite
12706 * the native endian format. We accomplish this by reversing
12707 * all the operations that would have been performed on the
12708 * data from a call to tg3_nvram_read_be32().
12710 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
12712 val = tr32(GRC_EEPROM_ADDR);
12713 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
12715 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
12717 tw32(GRC_EEPROM_ADDR, val |
12718 (0 << EEPROM_ADDR_DEVID_SHIFT) |
12719 (addr & EEPROM_ADDR_ADDR_MASK) |
12720 EEPROM_ADDR_START |
12721 EEPROM_ADDR_WRITE);
12723 for (j = 0; j < 1000; j++) {
12724 val = tr32(GRC_EEPROM_ADDR);
12726 if (val & EEPROM_ADDR_COMPLETE)
12730 if (!(val & EEPROM_ADDR_COMPLETE)) {
12739 /* offset and length are dword aligned */
12740 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
12744 u32 pagesize = tp->nvram_pagesize;
12745 u32 pagemask = pagesize - 1;
12749 tmp = kmalloc(pagesize, GFP_KERNEL);
12755 u32 phy_addr, page_off, size;
12757 phy_addr = offset & ~pagemask;
12759 for (j = 0; j < pagesize; j += 4) {
12760 ret = tg3_nvram_read_be32(tp, phy_addr + j,
12761 (__be32 *) (tmp + j));
12768 page_off = offset & pagemask;
12775 memcpy(tmp + page_off, buf, size);
12777 offset = offset + (pagesize - page_off);
12779 tg3_enable_nvram_access(tp);
12782 * Before we can erase the flash page, we need
12783 * to issue a special "write enable" command.
12785 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12787 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12790 /* Erase the target page */
12791 tw32(NVRAM_ADDR, phy_addr);
12793 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
12794 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
12796 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12799 /* Issue another write enable to start the write. */
12800 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12802 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12805 for (j = 0; j < pagesize; j += 4) {
12808 data = *((__be32 *) (tmp + j));
12810 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12812 tw32(NVRAM_ADDR, phy_addr + j);
12814 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
12818 nvram_cmd |= NVRAM_CMD_FIRST;
12819 else if (j == (pagesize - 4))
12820 nvram_cmd |= NVRAM_CMD_LAST;
12822 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12829 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12830 tg3_nvram_exec_cmd(tp, nvram_cmd);
12837 /* offset and length are dword aligned */
12838 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12843 for (i = 0; i < len; i += 4, offset += 4) {
12844 u32 page_off, phy_addr, nvram_cmd;
12847 memcpy(&data, buf + i, 4);
12848 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12850 page_off = offset % tp->nvram_pagesize;
12852 phy_addr = tg3_nvram_phys_addr(tp, offset);
12854 tw32(NVRAM_ADDR, phy_addr);
12856 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12858 if (page_off == 0 || i == 0)
12859 nvram_cmd |= NVRAM_CMD_FIRST;
12860 if (page_off == (tp->nvram_pagesize - 4))
12861 nvram_cmd |= NVRAM_CMD_LAST;
12863 if (i == (len - 4))
12864 nvram_cmd |= NVRAM_CMD_LAST;
12866 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12867 !tg3_flag(tp, 5755_PLUS) &&
12868 (tp->nvram_jedecnum == JEDEC_ST) &&
12869 (nvram_cmd & NVRAM_CMD_FIRST)) {
12871 if ((ret = tg3_nvram_exec_cmd(tp,
12872 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12877 if (!tg3_flag(tp, FLASH)) {
12878 /* We always do complete word writes to eeprom. */
12879 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12882 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12888 /* offset and length are dword aligned */
12889 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12893 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
12894 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12895 ~GRC_LCLCTRL_GPIO_OUTPUT1);
12899 if (!tg3_flag(tp, NVRAM)) {
12900 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12904 ret = tg3_nvram_lock(tp);
12908 tg3_enable_nvram_access(tp);
12909 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
12910 tw32(NVRAM_WRITE1, 0x406);
12912 grc_mode = tr32(GRC_MODE);
12913 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12915 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
12916 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12919 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12923 grc_mode = tr32(GRC_MODE);
12924 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12926 tg3_disable_nvram_access(tp);
12927 tg3_nvram_unlock(tp);
12930 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
12931 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12938 struct subsys_tbl_ent {
12939 u16 subsys_vendor, subsys_devid;
12943 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
12944 /* Broadcom boards. */
12945 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12946 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
12947 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12948 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
12949 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12950 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
12951 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12952 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12953 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12954 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
12955 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12956 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
12957 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12958 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12959 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12960 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
12961 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12962 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
12963 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12964 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
12965 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12966 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
12969 { TG3PCI_SUBVENDOR_ID_3COM,
12970 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
12971 { TG3PCI_SUBVENDOR_ID_3COM,
12972 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
12973 { TG3PCI_SUBVENDOR_ID_3COM,
12974 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12975 { TG3PCI_SUBVENDOR_ID_3COM,
12976 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12977 { TG3PCI_SUBVENDOR_ID_3COM,
12978 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12981 { TG3PCI_SUBVENDOR_ID_DELL,
12982 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12983 { TG3PCI_SUBVENDOR_ID_DELL,
12984 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12985 { TG3PCI_SUBVENDOR_ID_DELL,
12986 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12987 { TG3PCI_SUBVENDOR_ID_DELL,
12988 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12990 /* Compaq boards. */
12991 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12992 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12993 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12994 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12995 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12996 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12997 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12998 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12999 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13000 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
13003 { TG3PCI_SUBVENDOR_ID_IBM,
13004 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
13007 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
13011 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
13012 if ((subsys_id_to_phy_id[i].subsys_vendor ==
13013 tp->pdev->subsystem_vendor) &&
13014 (subsys_id_to_phy_id[i].subsys_devid ==
13015 tp->pdev->subsystem_device))
13016 return &subsys_id_to_phy_id[i];
13021 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
13025 tp->phy_id = TG3_PHY_ID_INVALID;
13026 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13028 /* Assume an onboard device and WOL capable by default. */
13029 tg3_flag_set(tp, EEPROM_WRITE_PROT);
13030 tg3_flag_set(tp, WOL_CAP);
13032 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13033 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
13034 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13035 tg3_flag_set(tp, IS_NIC);
13037 val = tr32(VCPU_CFGSHDW);
13038 if (val & VCPU_CFGSHDW_ASPM_DBNC)
13039 tg3_flag_set(tp, ASPM_WORKAROUND);
13040 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
13041 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
13042 tg3_flag_set(tp, WOL_ENABLE);
13043 device_set_wakeup_enable(&tp->pdev->dev, true);
13048 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
13049 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
13050 u32 nic_cfg, led_cfg;
13051 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
13052 int eeprom_phy_serdes = 0;
13054 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
13055 tp->nic_sram_data_cfg = nic_cfg;
13057 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
13058 ver >>= NIC_SRAM_DATA_VER_SHIFT;
13059 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13060 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13061 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 &&
13062 (ver > 0) && (ver < 0x100))
13063 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
13065 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
13066 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
13068 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
13069 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
13070 eeprom_phy_serdes = 1;
13072 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
13073 if (nic_phy_id != 0) {
13074 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
13075 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
13077 eeprom_phy_id = (id1 >> 16) << 10;
13078 eeprom_phy_id |= (id2 & 0xfc00) << 16;
13079 eeprom_phy_id |= (id2 & 0x03ff) << 0;
13083 tp->phy_id = eeprom_phy_id;
13084 if (eeprom_phy_serdes) {
13085 if (!tg3_flag(tp, 5705_PLUS))
13086 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13088 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
13091 if (tg3_flag(tp, 5750_PLUS))
13092 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
13093 SHASTA_EXT_LED_MODE_MASK);
13095 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
13099 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
13100 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13103 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
13104 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
13107 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
13108 tp->led_ctrl = LED_CTRL_MODE_MAC;
13110 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
13111 * read on some older 5700/5701 bootcode.
13113 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
13115 GET_ASIC_REV(tp->pci_chip_rev_id) ==
13117 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13121 case SHASTA_EXT_LED_SHARED:
13122 tp->led_ctrl = LED_CTRL_MODE_SHARED;
13123 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
13124 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
13125 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
13126 LED_CTRL_MODE_PHY_2);
13129 case SHASTA_EXT_LED_MAC:
13130 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
13133 case SHASTA_EXT_LED_COMBO:
13134 tp->led_ctrl = LED_CTRL_MODE_COMBO;
13135 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
13136 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
13137 LED_CTRL_MODE_PHY_2);
13142 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13143 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
13144 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
13145 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
13147 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
13148 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13150 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
13151 tg3_flag_set(tp, EEPROM_WRITE_PROT);
13152 if ((tp->pdev->subsystem_vendor ==
13153 PCI_VENDOR_ID_ARIMA) &&
13154 (tp->pdev->subsystem_device == 0x205a ||
13155 tp->pdev->subsystem_device == 0x2063))
13156 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13158 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13159 tg3_flag_set(tp, IS_NIC);
13162 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
13163 tg3_flag_set(tp, ENABLE_ASF);
13164 if (tg3_flag(tp, 5750_PLUS))
13165 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
13168 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
13169 tg3_flag(tp, 5750_PLUS))
13170 tg3_flag_set(tp, ENABLE_APE);
13172 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
13173 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
13174 tg3_flag_clear(tp, WOL_CAP);
13176 if (tg3_flag(tp, WOL_CAP) &&
13177 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
13178 tg3_flag_set(tp, WOL_ENABLE);
13179 device_set_wakeup_enable(&tp->pdev->dev, true);
13182 if (cfg2 & (1 << 17))
13183 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
13185 /* serdes signal pre-emphasis in register 0x590 set by */
13186 /* bootcode if bit 18 is set */
13187 if (cfg2 & (1 << 18))
13188 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
13190 if ((tg3_flag(tp, 57765_PLUS) ||
13191 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13192 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
13193 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
13194 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
13196 if (tg3_flag(tp, PCI_EXPRESS) &&
13197 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13198 !tg3_flag(tp, 57765_PLUS)) {
13201 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
13202 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
13203 tg3_flag_set(tp, ASPM_WORKAROUND);
13206 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
13207 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
13208 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
13209 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
13210 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
13211 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
13214 if (tg3_flag(tp, WOL_CAP))
13215 device_set_wakeup_enable(&tp->pdev->dev,
13216 tg3_flag(tp, WOL_ENABLE));
13218 device_set_wakeup_capable(&tp->pdev->dev, false);
13221 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
13226 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
13227 tw32(OTP_CTRL, cmd);
13229 /* Wait for up to 1 ms for command to execute. */
13230 for (i = 0; i < 100; i++) {
13231 val = tr32(OTP_STATUS);
13232 if (val & OTP_STATUS_CMD_DONE)
13237 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
13240 /* Read the gphy configuration from the OTP region of the chip. The gphy
13241 * configuration is a 32-bit value that straddles the alignment boundary.
13242 * We do two 32-bit reads and then shift and merge the results.
13244 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
13246 u32 bhalf_otp, thalf_otp;
13248 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
13250 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
13253 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
13255 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
13258 thalf_otp = tr32(OTP_READ_DATA);
13260 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
13262 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
13265 bhalf_otp = tr32(OTP_READ_DATA);
13267 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
13270 static void __devinit tg3_phy_init_link_config(struct tg3 *tp)
13272 u32 adv = ADVERTISED_Autoneg |
13275 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
13276 adv |= ADVERTISED_1000baseT_Half |
13277 ADVERTISED_1000baseT_Full;
13279 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13280 adv |= ADVERTISED_100baseT_Half |
13281 ADVERTISED_100baseT_Full |
13282 ADVERTISED_10baseT_Half |
13283 ADVERTISED_10baseT_Full |
13286 adv |= ADVERTISED_FIBRE;
13288 tp->link_config.advertising = adv;
13289 tp->link_config.speed = SPEED_INVALID;
13290 tp->link_config.duplex = DUPLEX_INVALID;
13291 tp->link_config.autoneg = AUTONEG_ENABLE;
13292 tp->link_config.active_speed = SPEED_INVALID;
13293 tp->link_config.active_duplex = DUPLEX_INVALID;
13294 tp->link_config.orig_speed = SPEED_INVALID;
13295 tp->link_config.orig_duplex = DUPLEX_INVALID;
13296 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13299 static int __devinit tg3_phy_probe(struct tg3 *tp)
13301 u32 hw_phy_id_1, hw_phy_id_2;
13302 u32 hw_phy_id, hw_phy_id_masked;
13305 /* flow control autonegotiation is default behavior */
13306 tg3_flag_set(tp, PAUSE_AUTONEG);
13307 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13309 if (tg3_flag(tp, USE_PHYLIB))
13310 return tg3_phy_init(tp);
13312 /* Reading the PHY ID register can conflict with ASF
13313 * firmware access to the PHY hardware.
13316 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
13317 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
13319 /* Now read the physical PHY_ID from the chip and verify
13320 * that it is sane. If it doesn't look good, we fall back
13321 * to either the hard-coded table based PHY_ID and failing
13322 * that the value found in the eeprom area.
13324 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
13325 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
13327 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
13328 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
13329 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
13331 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
13334 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
13335 tp->phy_id = hw_phy_id;
13336 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
13337 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13339 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
13341 if (tp->phy_id != TG3_PHY_ID_INVALID) {
13342 /* Do nothing, phy ID already set up in
13343 * tg3_get_eeprom_hw_cfg().
13346 struct subsys_tbl_ent *p;
13348 /* No eeprom signature? Try the hardcoded
13349 * subsys device table.
13351 p = tg3_lookup_by_subsys(tp);
13355 tp->phy_id = p->phy_id;
13357 tp->phy_id == TG3_PHY_ID_BCM8002)
13358 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13362 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
13363 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13364 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 ||
13365 (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
13366 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
13367 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
13368 tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
13369 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
13371 tg3_phy_init_link_config(tp);
13373 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
13374 !tg3_flag(tp, ENABLE_APE) &&
13375 !tg3_flag(tp, ENABLE_ASF)) {
13378 tg3_readphy(tp, MII_BMSR, &bmsr);
13379 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
13380 (bmsr & BMSR_LSTATUS))
13381 goto skip_phy_reset;
13383 err = tg3_phy_reset(tp);
13387 tg3_phy_set_wirespeed(tp);
13389 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13390 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13391 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
13392 if (!tg3_copper_is_advertising_all(tp, mask)) {
13393 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
13394 tp->link_config.flowctrl);
13396 tg3_writephy(tp, MII_BMCR,
13397 BMCR_ANENABLE | BMCR_ANRESTART);
13402 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
13403 err = tg3_init_5401phy_dsp(tp);
13407 err = tg3_init_5401phy_dsp(tp);
13413 static void __devinit tg3_read_vpd(struct tg3 *tp)
13416 unsigned int block_end, rosize, len;
13420 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
13424 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
13426 goto out_not_found;
13428 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
13429 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
13430 i += PCI_VPD_LRDT_TAG_SIZE;
13432 if (block_end > vpdlen)
13433 goto out_not_found;
13435 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13436 PCI_VPD_RO_KEYWORD_MFR_ID);
13438 len = pci_vpd_info_field_size(&vpd_data[j]);
13440 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13441 if (j + len > block_end || len != 4 ||
13442 memcmp(&vpd_data[j], "1028", 4))
13445 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13446 PCI_VPD_RO_KEYWORD_VENDOR0);
13450 len = pci_vpd_info_field_size(&vpd_data[j]);
13452 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13453 if (j + len > block_end)
13456 if (len >= sizeof(tp->fw_ver))
13457 len = sizeof(tp->fw_ver) - 1;
13458 memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
13459 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
13464 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13465 PCI_VPD_RO_KEYWORD_PARTNO);
13467 goto out_not_found;
13469 len = pci_vpd_info_field_size(&vpd_data[i]);
13471 i += PCI_VPD_INFO_FLD_HDR_SIZE;
13472 if (len > TG3_BPN_SIZE ||
13473 (len + i) > vpdlen)
13474 goto out_not_found;
13476 memcpy(tp->board_part_number, &vpd_data[i], len);
13480 if (tp->board_part_number[0])
13484 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13485 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
13486 strcpy(tp->board_part_number, "BCM5717");
13487 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
13488 strcpy(tp->board_part_number, "BCM5718");
13491 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
13492 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
13493 strcpy(tp->board_part_number, "BCM57780");
13494 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
13495 strcpy(tp->board_part_number, "BCM57760");
13496 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
13497 strcpy(tp->board_part_number, "BCM57790");
13498 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
13499 strcpy(tp->board_part_number, "BCM57788");
13502 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13503 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
13504 strcpy(tp->board_part_number, "BCM57761");
13505 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
13506 strcpy(tp->board_part_number, "BCM57765");
13507 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
13508 strcpy(tp->board_part_number, "BCM57781");
13509 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
13510 strcpy(tp->board_part_number, "BCM57785");
13511 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
13512 strcpy(tp->board_part_number, "BCM57791");
13513 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13514 strcpy(tp->board_part_number, "BCM57795");
13517 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13518 strcpy(tp->board_part_number, "BCM95906");
13521 strcpy(tp->board_part_number, "none");
13525 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
13529 if (tg3_nvram_read(tp, offset, &val) ||
13530 (val & 0xfc000000) != 0x0c000000 ||
13531 tg3_nvram_read(tp, offset + 4, &val) ||
13538 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
13540 u32 val, offset, start, ver_offset;
13542 bool newver = false;
13544 if (tg3_nvram_read(tp, 0xc, &offset) ||
13545 tg3_nvram_read(tp, 0x4, &start))
13548 offset = tg3_nvram_logical_addr(tp, offset);
13550 if (tg3_nvram_read(tp, offset, &val))
13553 if ((val & 0xfc000000) == 0x0c000000) {
13554 if (tg3_nvram_read(tp, offset + 4, &val))
13561 dst_off = strlen(tp->fw_ver);
13564 if (TG3_VER_SIZE - dst_off < 16 ||
13565 tg3_nvram_read(tp, offset + 8, &ver_offset))
13568 offset = offset + ver_offset - start;
13569 for (i = 0; i < 16; i += 4) {
13571 if (tg3_nvram_read_be32(tp, offset + i, &v))
13574 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
13579 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
13582 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
13583 TG3_NVM_BCVER_MAJSFT;
13584 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
13585 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
13586 "v%d.%02d", major, minor);
13590 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
13592 u32 val, major, minor;
13594 /* Use native endian representation */
13595 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
13598 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
13599 TG3_NVM_HWSB_CFG1_MAJSFT;
13600 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
13601 TG3_NVM_HWSB_CFG1_MINSFT;
13603 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
13606 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
13608 u32 offset, major, minor, build;
13610 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
13612 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
13615 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
13616 case TG3_EEPROM_SB_REVISION_0:
13617 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
13619 case TG3_EEPROM_SB_REVISION_2:
13620 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
13622 case TG3_EEPROM_SB_REVISION_3:
13623 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
13625 case TG3_EEPROM_SB_REVISION_4:
13626 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
13628 case TG3_EEPROM_SB_REVISION_5:
13629 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
13631 case TG3_EEPROM_SB_REVISION_6:
13632 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
13638 if (tg3_nvram_read(tp, offset, &val))
13641 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
13642 TG3_EEPROM_SB_EDH_BLD_SHFT;
13643 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
13644 TG3_EEPROM_SB_EDH_MAJ_SHFT;
13645 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
13647 if (minor > 99 || build > 26)
13650 offset = strlen(tp->fw_ver);
13651 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
13652 " v%d.%02d", major, minor);
13655 offset = strlen(tp->fw_ver);
13656 if (offset < TG3_VER_SIZE - 1)
13657 tp->fw_ver[offset] = 'a' + build - 1;
13661 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
13663 u32 val, offset, start;
13666 for (offset = TG3_NVM_DIR_START;
13667 offset < TG3_NVM_DIR_END;
13668 offset += TG3_NVM_DIRENT_SIZE) {
13669 if (tg3_nvram_read(tp, offset, &val))
13672 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
13676 if (offset == TG3_NVM_DIR_END)
13679 if (!tg3_flag(tp, 5705_PLUS))
13680 start = 0x08000000;
13681 else if (tg3_nvram_read(tp, offset - 4, &start))
13684 if (tg3_nvram_read(tp, offset + 4, &offset) ||
13685 !tg3_fw_img_is_valid(tp, offset) ||
13686 tg3_nvram_read(tp, offset + 8, &val))
13689 offset += val - start;
13691 vlen = strlen(tp->fw_ver);
13693 tp->fw_ver[vlen++] = ',';
13694 tp->fw_ver[vlen++] = ' ';
13696 for (i = 0; i < 4; i++) {
13698 if (tg3_nvram_read_be32(tp, offset, &v))
13701 offset += sizeof(v);
13703 if (vlen > TG3_VER_SIZE - sizeof(v)) {
13704 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
13708 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
13713 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
13719 if (!tg3_flag(tp, ENABLE_APE) || !tg3_flag(tp, ENABLE_ASF))
13722 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
13723 if (apedata != APE_SEG_SIG_MAGIC)
13726 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
13727 if (!(apedata & APE_FW_STATUS_READY))
13730 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
13732 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
13733 tg3_flag_set(tp, APE_HAS_NCSI);
13739 vlen = strlen(tp->fw_ver);
13741 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
13743 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
13744 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
13745 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
13746 (apedata & APE_FW_VERSION_BLDMSK));
13749 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
13752 bool vpd_vers = false;
13754 if (tp->fw_ver[0] != 0)
13757 if (tg3_flag(tp, NO_NVRAM)) {
13758 strcat(tp->fw_ver, "sb");
13762 if (tg3_nvram_read(tp, 0, &val))
13765 if (val == TG3_EEPROM_MAGIC)
13766 tg3_read_bc_ver(tp);
13767 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
13768 tg3_read_sb_ver(tp, val);
13769 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
13770 tg3_read_hwsb_ver(tp);
13777 if (tg3_flag(tp, ENABLE_APE)) {
13778 if (tg3_flag(tp, ENABLE_ASF))
13779 tg3_read_dash_ver(tp);
13780 } else if (tg3_flag(tp, ENABLE_ASF)) {
13781 tg3_read_mgmtfw_ver(tp);
13785 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
13788 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
13790 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13792 if (tg3_flag(tp, LRG_PROD_RING_CAP))
13793 return TG3_RX_RET_MAX_SIZE_5717;
13794 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
13795 return TG3_RX_RET_MAX_SIZE_5700;
13797 return TG3_RX_RET_MAX_SIZE_5705;
13800 static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
13801 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
13802 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
13803 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
13807 static int __devinit tg3_get_invariants(struct tg3 *tp)
13810 u32 pci_state_reg, grc_misc_cfg;
13815 /* Force memory write invalidate off. If we leave it on,
13816 * then on 5700_BX chips we have to enable a workaround.
13817 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13818 * to match the cacheline size. The Broadcom driver have this
13819 * workaround but turns MWI off all the times so never uses
13820 * it. This seems to suggest that the workaround is insufficient.
13822 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13823 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
13824 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13826 /* Important! -- Make sure register accesses are byteswapped
13827 * correctly. Also, for those chips that require it, make
13828 * sure that indirect register accesses are enabled before
13829 * the first operation.
13831 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13833 tp->misc_host_ctrl |= (misc_ctrl_reg &
13834 MISC_HOST_CTRL_CHIPREV);
13835 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13836 tp->misc_host_ctrl);
13838 tp->pci_chip_rev_id = (misc_ctrl_reg >>
13839 MISC_HOST_CTRL_CHIPREV_SHIFT);
13840 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
13841 u32 prod_id_asic_rev;
13843 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
13844 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
13845 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
13846 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720)
13847 pci_read_config_dword(tp->pdev,
13848 TG3PCI_GEN2_PRODID_ASICREV,
13849 &prod_id_asic_rev);
13850 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13851 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13852 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13853 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13854 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13855 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13856 pci_read_config_dword(tp->pdev,
13857 TG3PCI_GEN15_PRODID_ASICREV,
13858 &prod_id_asic_rev);
13860 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
13861 &prod_id_asic_rev);
13863 tp->pci_chip_rev_id = prod_id_asic_rev;
13866 /* Wrong chip ID in 5752 A0. This code can be removed later
13867 * as A0 is not in production.
13869 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13870 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13872 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13873 * we need to disable memory and use config. cycles
13874 * only to access all registers. The 5702/03 chips
13875 * can mistakenly decode the special cycles from the
13876 * ICH chipsets as memory write cycles, causing corruption
13877 * of register and memory space. Only certain ICH bridges
13878 * will drive special cycles with non-zero data during the
13879 * address phase which can fall within the 5703's address
13880 * range. This is not an ICH bug as the PCI spec allows
13881 * non-zero address during special cycles. However, only
13882 * these ICH bridges are known to drive non-zero addresses
13883 * during special cycles.
13885 * Since special cycles do not cross PCI bridges, we only
13886 * enable this workaround if the 5703 is on the secondary
13887 * bus of these ICH bridges.
13889 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13890 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13891 static struct tg3_dev_id {
13895 } ich_chipsets[] = {
13896 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13898 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13900 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13902 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13906 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13907 struct pci_dev *bridge = NULL;
13909 while (pci_id->vendor != 0) {
13910 bridge = pci_get_device(pci_id->vendor, pci_id->device,
13916 if (pci_id->rev != PCI_ANY_ID) {
13917 if (bridge->revision > pci_id->rev)
13920 if (bridge->subordinate &&
13921 (bridge->subordinate->number ==
13922 tp->pdev->bus->number)) {
13923 tg3_flag_set(tp, ICH_WORKAROUND);
13924 pci_dev_put(bridge);
13930 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13931 static struct tg3_dev_id {
13934 } bridge_chipsets[] = {
13935 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13936 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13939 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13940 struct pci_dev *bridge = NULL;
13942 while (pci_id->vendor != 0) {
13943 bridge = pci_get_device(pci_id->vendor,
13950 if (bridge->subordinate &&
13951 (bridge->subordinate->number <=
13952 tp->pdev->bus->number) &&
13953 (bridge->subordinate->subordinate >=
13954 tp->pdev->bus->number)) {
13955 tg3_flag_set(tp, 5701_DMA_BUG);
13956 pci_dev_put(bridge);
13962 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13963 * DMA addresses > 40-bit. This bridge may have other additional
13964 * 57xx devices behind it in some 4-port NIC designs for example.
13965 * Any tg3 device found behind the bridge will also need the 40-bit
13968 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13969 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13970 tg3_flag_set(tp, 5780_CLASS);
13971 tg3_flag_set(tp, 40BIT_DMA_BUG);
13972 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13974 struct pci_dev *bridge = NULL;
13977 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13978 PCI_DEVICE_ID_SERVERWORKS_EPB,
13980 if (bridge && bridge->subordinate &&
13981 (bridge->subordinate->number <=
13982 tp->pdev->bus->number) &&
13983 (bridge->subordinate->subordinate >=
13984 tp->pdev->bus->number)) {
13985 tg3_flag_set(tp, 40BIT_DMA_BUG);
13986 pci_dev_put(bridge);
13992 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13993 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)
13994 tp->pdev_peer = tg3_find_peer(tp);
13996 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13997 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13998 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13999 tg3_flag_set(tp, 5717_PLUS);
14001 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
14002 tg3_flag(tp, 5717_PLUS))
14003 tg3_flag_set(tp, 57765_PLUS);
14005 /* Intentionally exclude ASIC_REV_5906 */
14006 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14007 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
14008 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14009 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14010 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14011 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14012 tg3_flag(tp, 57765_PLUS))
14013 tg3_flag_set(tp, 5755_PLUS);
14015 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
14016 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
14017 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
14018 tg3_flag(tp, 5755_PLUS) ||
14019 tg3_flag(tp, 5780_CLASS))
14020 tg3_flag_set(tp, 5750_PLUS);
14022 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14023 tg3_flag(tp, 5750_PLUS))
14024 tg3_flag_set(tp, 5705_PLUS);
14026 /* Determine TSO capabilities */
14027 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0)
14028 ; /* Do nothing. HW bug. */
14029 else if (tg3_flag(tp, 57765_PLUS))
14030 tg3_flag_set(tp, HW_TSO_3);
14031 else if (tg3_flag(tp, 5755_PLUS) ||
14032 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14033 tg3_flag_set(tp, HW_TSO_2);
14034 else if (tg3_flag(tp, 5750_PLUS)) {
14035 tg3_flag_set(tp, HW_TSO_1);
14036 tg3_flag_set(tp, TSO_BUG);
14037 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
14038 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
14039 tg3_flag_clear(tp, TSO_BUG);
14040 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14041 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14042 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
14043 tg3_flag_set(tp, TSO_BUG);
14044 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
14045 tp->fw_needed = FIRMWARE_TG3TSO5;
14047 tp->fw_needed = FIRMWARE_TG3TSO;
14050 /* Selectively allow TSO based on operating conditions */
14051 if (tg3_flag(tp, HW_TSO_1) ||
14052 tg3_flag(tp, HW_TSO_2) ||
14053 tg3_flag(tp, HW_TSO_3) ||
14055 /* For firmware TSO, assume ASF is disabled.
14056 * We'll disable TSO later if we discover ASF
14057 * is enabled in tg3_get_eeprom_hw_cfg().
14059 tg3_flag_set(tp, TSO_CAPABLE);
14061 tg3_flag_clear(tp, TSO_CAPABLE);
14062 tg3_flag_clear(tp, TSO_BUG);
14063 tp->fw_needed = NULL;
14066 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14067 tp->fw_needed = FIRMWARE_TG3;
14071 if (tg3_flag(tp, 5750_PLUS)) {
14072 tg3_flag_set(tp, SUPPORT_MSI);
14073 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
14074 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
14075 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
14076 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
14077 tp->pdev_peer == tp->pdev))
14078 tg3_flag_clear(tp, SUPPORT_MSI);
14080 if (tg3_flag(tp, 5755_PLUS) ||
14081 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14082 tg3_flag_set(tp, 1SHOT_MSI);
14085 if (tg3_flag(tp, 57765_PLUS)) {
14086 tg3_flag_set(tp, SUPPORT_MSIX);
14087 tp->irq_max = TG3_IRQ_MAX_VECS;
14091 if (tg3_flag(tp, 5755_PLUS) ||
14092 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14093 tg3_flag_set(tp, SHORT_DMA_BUG);
14095 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
14096 tg3_flag_set(tp, 4K_FIFO_LIMIT);
14098 if (tg3_flag(tp, 5717_PLUS))
14099 tg3_flag_set(tp, LRG_PROD_RING_CAP);
14101 if (tg3_flag(tp, 57765_PLUS) &&
14102 tp->pci_chip_rev_id != CHIPREV_ID_5719_A0)
14103 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
14105 if (!tg3_flag(tp, 5705_PLUS) ||
14106 tg3_flag(tp, 5780_CLASS) ||
14107 tg3_flag(tp, USE_JUMBO_BDFLAG))
14108 tg3_flag_set(tp, JUMBO_CAPABLE);
14110 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
14113 if (pci_is_pcie(tp->pdev)) {
14116 tg3_flag_set(tp, PCI_EXPRESS);
14118 tp->pcie_readrq = 4096;
14119 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14120 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14121 tp->pcie_readrq = 2048;
14123 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
14125 pci_read_config_word(tp->pdev,
14126 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
14128 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
14129 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
14131 tg3_flag_clear(tp, HW_TSO_2);
14132 tg3_flag_clear(tp, TSO_CAPABLE);
14134 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14135 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14136 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
14137 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
14138 tg3_flag_set(tp, CLKREQ_BUG);
14139 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
14140 tg3_flag_set(tp, L1PLLPD_EN);
14142 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
14143 /* BCM5785 devices are effectively PCIe devices, and should
14144 * follow PCIe codepaths, but do not have a PCIe capabilities
14147 tg3_flag_set(tp, PCI_EXPRESS);
14148 } else if (!tg3_flag(tp, 5705_PLUS) ||
14149 tg3_flag(tp, 5780_CLASS)) {
14150 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
14151 if (!tp->pcix_cap) {
14152 dev_err(&tp->pdev->dev,
14153 "Cannot find PCI-X capability, aborting\n");
14157 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
14158 tg3_flag_set(tp, PCIX_MODE);
14161 /* If we have an AMD 762 or VIA K8T800 chipset, write
14162 * reordering to the mailbox registers done by the host
14163 * controller can cause major troubles. We read back from
14164 * every mailbox register write to force the writes to be
14165 * posted to the chip in order.
14167 if (pci_dev_present(tg3_write_reorder_chipsets) &&
14168 !tg3_flag(tp, PCI_EXPRESS))
14169 tg3_flag_set(tp, MBOX_WRITE_REORDER);
14171 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
14172 &tp->pci_cacheline_sz);
14173 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
14174 &tp->pci_lat_timer);
14175 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
14176 tp->pci_lat_timer < 64) {
14177 tp->pci_lat_timer = 64;
14178 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
14179 tp->pci_lat_timer);
14182 /* Important! -- It is critical that the PCI-X hw workaround
14183 * situation is decided before the first MMIO register access.
14185 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
14186 /* 5700 BX chips need to have their TX producer index
14187 * mailboxes written twice to workaround a bug.
14189 tg3_flag_set(tp, TXD_MBOX_HWBUG);
14191 /* If we are in PCI-X mode, enable register write workaround.
14193 * The workaround is to use indirect register accesses
14194 * for all chip writes not to mailbox registers.
14196 if (tg3_flag(tp, PCIX_MODE)) {
14199 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
14201 /* The chip can have it's power management PCI config
14202 * space registers clobbered due to this bug.
14203 * So explicitly force the chip into D0 here.
14205 pci_read_config_dword(tp->pdev,
14206 tp->pm_cap + PCI_PM_CTRL,
14208 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
14209 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
14210 pci_write_config_dword(tp->pdev,
14211 tp->pm_cap + PCI_PM_CTRL,
14214 /* Also, force SERR#/PERR# in PCI command. */
14215 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
14216 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
14217 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
14221 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
14222 tg3_flag_set(tp, PCI_HIGH_SPEED);
14223 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
14224 tg3_flag_set(tp, PCI_32BIT);
14226 /* Chip-specific fixup from Broadcom driver */
14227 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
14228 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
14229 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
14230 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
14233 /* Default fast path register access methods */
14234 tp->read32 = tg3_read32;
14235 tp->write32 = tg3_write32;
14236 tp->read32_mbox = tg3_read32;
14237 tp->write32_mbox = tg3_write32;
14238 tp->write32_tx_mbox = tg3_write32;
14239 tp->write32_rx_mbox = tg3_write32;
14241 /* Various workaround register access methods */
14242 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
14243 tp->write32 = tg3_write_indirect_reg32;
14244 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
14245 (tg3_flag(tp, PCI_EXPRESS) &&
14246 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
14248 * Back to back register writes can cause problems on these
14249 * chips, the workaround is to read back all reg writes
14250 * except those to mailbox regs.
14252 * See tg3_write_indirect_reg32().
14254 tp->write32 = tg3_write_flush_reg32;
14257 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
14258 tp->write32_tx_mbox = tg3_write32_tx_mbox;
14259 if (tg3_flag(tp, MBOX_WRITE_REORDER))
14260 tp->write32_rx_mbox = tg3_write_flush_reg32;
14263 if (tg3_flag(tp, ICH_WORKAROUND)) {
14264 tp->read32 = tg3_read_indirect_reg32;
14265 tp->write32 = tg3_write_indirect_reg32;
14266 tp->read32_mbox = tg3_read_indirect_mbox;
14267 tp->write32_mbox = tg3_write_indirect_mbox;
14268 tp->write32_tx_mbox = tg3_write_indirect_mbox;
14269 tp->write32_rx_mbox = tg3_write_indirect_mbox;
14274 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
14275 pci_cmd &= ~PCI_COMMAND_MEMORY;
14276 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
14278 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14279 tp->read32_mbox = tg3_read32_mbox_5906;
14280 tp->write32_mbox = tg3_write32_mbox_5906;
14281 tp->write32_tx_mbox = tg3_write32_mbox_5906;
14282 tp->write32_rx_mbox = tg3_write32_mbox_5906;
14285 if (tp->write32 == tg3_write_indirect_reg32 ||
14286 (tg3_flag(tp, PCIX_MODE) &&
14287 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14288 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
14289 tg3_flag_set(tp, SRAM_USE_CONFIG);
14291 /* The memory arbiter has to be enabled in order for SRAM accesses
14292 * to succeed. Normally on powerup the tg3 chip firmware will make
14293 * sure it is enabled, but other entities such as system netboot
14294 * code might disable it.
14296 val = tr32(MEMARB_MODE);
14297 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
14299 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
14300 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14301 tg3_flag(tp, 5780_CLASS)) {
14302 if (tg3_flag(tp, PCIX_MODE)) {
14303 pci_read_config_dword(tp->pdev,
14304 tp->pcix_cap + PCI_X_STATUS,
14306 tp->pci_fn = val & 0x7;
14308 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
14309 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
14310 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
14311 NIC_SRAM_CPMUSTAT_SIG) {
14312 tp->pci_fn = val & TG3_CPMU_STATUS_FMSK_5717;
14313 tp->pci_fn = tp->pci_fn ? 1 : 0;
14315 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14316 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
14317 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
14318 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
14319 NIC_SRAM_CPMUSTAT_SIG) {
14320 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
14321 TG3_CPMU_STATUS_FSHFT_5719;
14325 /* Get eeprom hw config before calling tg3_set_power_state().
14326 * In particular, the TG3_FLAG_IS_NIC flag must be
14327 * determined before calling tg3_set_power_state() so that
14328 * we know whether or not to switch out of Vaux power.
14329 * When the flag is set, it means that GPIO1 is used for eeprom
14330 * write protect and also implies that it is a LOM where GPIOs
14331 * are not used to switch power.
14333 tg3_get_eeprom_hw_cfg(tp);
14335 if (tp->fw_needed && tg3_flag(tp, ENABLE_ASF)) {
14336 tg3_flag_clear(tp, TSO_CAPABLE);
14337 tg3_flag_clear(tp, TSO_BUG);
14338 tp->fw_needed = NULL;
14341 if (tg3_flag(tp, ENABLE_APE)) {
14342 /* Allow reads and writes to the
14343 * APE register and memory space.
14345 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
14346 PCISTATE_ALLOW_APE_SHMEM_WR |
14347 PCISTATE_ALLOW_APE_PSPACE_WR;
14348 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
14351 tg3_ape_lock_init(tp);
14354 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14355 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14356 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14357 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14358 tg3_flag(tp, 57765_PLUS))
14359 tg3_flag_set(tp, CPMU_PRESENT);
14361 /* Set up tp->grc_local_ctrl before calling
14362 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
14363 * will bring 5700's external PHY out of reset.
14364 * It is also used as eeprom write protect on LOMs.
14366 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
14367 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14368 tg3_flag(tp, EEPROM_WRITE_PROT))
14369 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
14370 GRC_LCLCTRL_GPIO_OUTPUT1);
14371 /* Unused GPIO3 must be driven as output on 5752 because there
14372 * are no pull-up resistors on unused GPIO pins.
14374 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
14375 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
14377 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14378 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14379 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
14380 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
14382 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
14383 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
14384 /* Turn off the debug UART. */
14385 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
14386 if (tg3_flag(tp, IS_NIC))
14387 /* Keep VMain power. */
14388 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
14389 GRC_LCLCTRL_GPIO_OUTPUT0;
14392 /* Switch out of Vaux if it is a NIC */
14393 tg3_pwrsrc_switch_to_vmain(tp);
14395 /* Derive initial jumbo mode from MTU assigned in
14396 * ether_setup() via the alloc_etherdev() call
14398 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
14399 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14401 /* Determine WakeOnLan speed to use. */
14402 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14403 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
14404 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
14405 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
14406 tg3_flag_clear(tp, WOL_SPEED_100MB);
14408 tg3_flag_set(tp, WOL_SPEED_100MB);
14411 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14412 tp->phy_flags |= TG3_PHYFLG_IS_FET;
14414 /* A few boards don't want Ethernet@WireSpeed phy feature */
14415 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14416 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14417 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
14418 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
14419 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
14420 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
14421 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
14423 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
14424 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
14425 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
14426 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
14427 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
14429 if (tg3_flag(tp, 5705_PLUS) &&
14430 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
14431 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
14432 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
14433 !tg3_flag(tp, 57765_PLUS)) {
14434 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14435 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
14436 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14437 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
14438 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
14439 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
14440 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
14441 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
14442 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
14444 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
14447 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14448 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
14449 tp->phy_otp = tg3_read_otp_phycfg(tp);
14450 if (tp->phy_otp == 0)
14451 tp->phy_otp = TG3_OTP_DEFAULT;
14454 if (tg3_flag(tp, CPMU_PRESENT))
14455 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
14457 tp->mi_mode = MAC_MI_MODE_BASE;
14459 tp->coalesce_mode = 0;
14460 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
14461 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
14462 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
14464 /* Set these bits to enable statistics workaround. */
14465 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14466 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
14467 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) {
14468 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
14469 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
14472 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14473 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14474 tg3_flag_set(tp, USE_PHYLIB);
14476 err = tg3_mdio_init(tp);
14480 /* Initialize data/descriptor byte/word swapping. */
14481 val = tr32(GRC_MODE);
14482 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14483 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
14484 GRC_MODE_WORD_SWAP_B2HRX_DATA |
14485 GRC_MODE_B2HRX_ENABLE |
14486 GRC_MODE_HTX2B_ENABLE |
14487 GRC_MODE_HOST_STACKUP);
14489 val &= GRC_MODE_HOST_STACKUP;
14491 tw32(GRC_MODE, val | tp->grc_mode);
14493 tg3_switch_clocks(tp);
14495 /* Clear this out for sanity. */
14496 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
14498 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
14500 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
14501 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
14502 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
14504 if (chiprevid == CHIPREV_ID_5701_A0 ||
14505 chiprevid == CHIPREV_ID_5701_B0 ||
14506 chiprevid == CHIPREV_ID_5701_B2 ||
14507 chiprevid == CHIPREV_ID_5701_B5) {
14508 void __iomem *sram_base;
14510 /* Write some dummy words into the SRAM status block
14511 * area, see if it reads back correctly. If the return
14512 * value is bad, force enable the PCIX workaround.
14514 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
14516 writel(0x00000000, sram_base);
14517 writel(0x00000000, sram_base + 4);
14518 writel(0xffffffff, sram_base + 4);
14519 if (readl(sram_base) != 0x00000000)
14520 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
14525 tg3_nvram_init(tp);
14527 grc_misc_cfg = tr32(GRC_MISC_CFG);
14528 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
14530 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14531 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
14532 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
14533 tg3_flag_set(tp, IS_5788);
14535 if (!tg3_flag(tp, IS_5788) &&
14536 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
14537 tg3_flag_set(tp, TAGGED_STATUS);
14538 if (tg3_flag(tp, TAGGED_STATUS)) {
14539 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
14540 HOSTCC_MODE_CLRTICK_TXBD);
14542 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
14543 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
14544 tp->misc_host_ctrl);
14547 /* Preserve the APE MAC_MODE bits */
14548 if (tg3_flag(tp, ENABLE_APE))
14549 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
14553 /* these are limited to 10/100 only */
14554 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
14555 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
14556 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14557 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14558 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
14559 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
14560 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
14561 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14562 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
14563 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
14564 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
14565 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
14566 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
14567 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
14568 (tp->phy_flags & TG3_PHYFLG_IS_FET))
14569 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
14571 err = tg3_phy_probe(tp);
14573 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
14574 /* ... but do not return immediately ... */
14579 tg3_read_fw_ver(tp);
14581 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
14582 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14584 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14585 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14587 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14590 /* 5700 {AX,BX} chips have a broken status block link
14591 * change bit implementation, so we must use the
14592 * status register in those cases.
14594 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14595 tg3_flag_set(tp, USE_LINKCHG_REG);
14597 tg3_flag_clear(tp, USE_LINKCHG_REG);
14599 /* The led_ctrl is set during tg3_phy_probe, here we might
14600 * have to force the link status polling mechanism based
14601 * upon subsystem IDs.
14603 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
14604 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14605 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
14606 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14607 tg3_flag_set(tp, USE_LINKCHG_REG);
14610 /* For all SERDES we poll the MAC status register. */
14611 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
14612 tg3_flag_set(tp, POLL_SERDES);
14614 tg3_flag_clear(tp, POLL_SERDES);
14616 tp->rx_offset = NET_IP_ALIGN;
14617 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
14618 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14619 tg3_flag(tp, PCIX_MODE)) {
14621 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
14622 tp->rx_copy_thresh = ~(u16)0;
14626 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
14627 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
14628 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
14630 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
14632 /* Increment the rx prod index on the rx std ring by at most
14633 * 8 for these chips to workaround hw errata.
14635 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
14636 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
14637 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
14638 tp->rx_std_max_post = 8;
14640 if (tg3_flag(tp, ASPM_WORKAROUND))
14641 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
14642 PCIE_PWR_MGMT_L1_THRESH_MSK;
14647 #ifdef CONFIG_SPARC
14648 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
14650 struct net_device *dev = tp->dev;
14651 struct pci_dev *pdev = tp->pdev;
14652 struct device_node *dp = pci_device_to_OF_node(pdev);
14653 const unsigned char *addr;
14656 addr = of_get_property(dp, "local-mac-address", &len);
14657 if (addr && len == 6) {
14658 memcpy(dev->dev_addr, addr, 6);
14659 memcpy(dev->perm_addr, dev->dev_addr, 6);
14665 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
14667 struct net_device *dev = tp->dev;
14669 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
14670 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
14675 static int __devinit tg3_get_device_address(struct tg3 *tp)
14677 struct net_device *dev = tp->dev;
14678 u32 hi, lo, mac_offset;
14681 #ifdef CONFIG_SPARC
14682 if (!tg3_get_macaddr_sparc(tp))
14687 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14688 tg3_flag(tp, 5780_CLASS)) {
14689 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
14691 if (tg3_nvram_lock(tp))
14692 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
14694 tg3_nvram_unlock(tp);
14695 } else if (tg3_flag(tp, 5717_PLUS)) {
14696 if (tp->pci_fn & 1)
14698 if (tp->pci_fn > 1)
14699 mac_offset += 0x18c;
14700 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14703 /* First try to get it from MAC address mailbox. */
14704 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
14705 if ((hi >> 16) == 0x484b) {
14706 dev->dev_addr[0] = (hi >> 8) & 0xff;
14707 dev->dev_addr[1] = (hi >> 0) & 0xff;
14709 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
14710 dev->dev_addr[2] = (lo >> 24) & 0xff;
14711 dev->dev_addr[3] = (lo >> 16) & 0xff;
14712 dev->dev_addr[4] = (lo >> 8) & 0xff;
14713 dev->dev_addr[5] = (lo >> 0) & 0xff;
14715 /* Some old bootcode may report a 0 MAC address in SRAM */
14716 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
14719 /* Next, try NVRAM. */
14720 if (!tg3_flag(tp, NO_NVRAM) &&
14721 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
14722 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
14723 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
14724 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
14726 /* Finally just fetch it out of the MAC control regs. */
14728 hi = tr32(MAC_ADDR_0_HIGH);
14729 lo = tr32(MAC_ADDR_0_LOW);
14731 dev->dev_addr[5] = lo & 0xff;
14732 dev->dev_addr[4] = (lo >> 8) & 0xff;
14733 dev->dev_addr[3] = (lo >> 16) & 0xff;
14734 dev->dev_addr[2] = (lo >> 24) & 0xff;
14735 dev->dev_addr[1] = hi & 0xff;
14736 dev->dev_addr[0] = (hi >> 8) & 0xff;
14740 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
14741 #ifdef CONFIG_SPARC
14742 if (!tg3_get_default_macaddr_sparc(tp))
14747 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
14751 #define BOUNDARY_SINGLE_CACHELINE 1
14752 #define BOUNDARY_MULTI_CACHELINE 2
14754 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
14756 int cacheline_size;
14760 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
14762 cacheline_size = 1024;
14764 cacheline_size = (int) byte * 4;
14766 /* On 5703 and later chips, the boundary bits have no
14769 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14770 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14771 !tg3_flag(tp, PCI_EXPRESS))
14774 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
14775 goal = BOUNDARY_MULTI_CACHELINE;
14777 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
14778 goal = BOUNDARY_SINGLE_CACHELINE;
14784 if (tg3_flag(tp, 57765_PLUS)) {
14785 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
14792 /* PCI controllers on most RISC systems tend to disconnect
14793 * when a device tries to burst across a cache-line boundary.
14794 * Therefore, letting tg3 do so just wastes PCI bandwidth.
14796 * Unfortunately, for PCI-E there are only limited
14797 * write-side controls for this, and thus for reads
14798 * we will still get the disconnects. We'll also waste
14799 * these PCI cycles for both read and write for chips
14800 * other than 5700 and 5701 which do not implement the
14803 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
14804 switch (cacheline_size) {
14809 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14810 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
14811 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
14813 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14814 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14819 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
14820 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
14824 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14825 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14828 } else if (tg3_flag(tp, PCI_EXPRESS)) {
14829 switch (cacheline_size) {
14833 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14834 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14835 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
14841 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14842 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
14846 switch (cacheline_size) {
14848 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14849 val |= (DMA_RWCTRL_READ_BNDRY_16 |
14850 DMA_RWCTRL_WRITE_BNDRY_16);
14855 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14856 val |= (DMA_RWCTRL_READ_BNDRY_32 |
14857 DMA_RWCTRL_WRITE_BNDRY_32);
14862 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14863 val |= (DMA_RWCTRL_READ_BNDRY_64 |
14864 DMA_RWCTRL_WRITE_BNDRY_64);
14869 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14870 val |= (DMA_RWCTRL_READ_BNDRY_128 |
14871 DMA_RWCTRL_WRITE_BNDRY_128);
14876 val |= (DMA_RWCTRL_READ_BNDRY_256 |
14877 DMA_RWCTRL_WRITE_BNDRY_256);
14880 val |= (DMA_RWCTRL_READ_BNDRY_512 |
14881 DMA_RWCTRL_WRITE_BNDRY_512);
14885 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
14886 DMA_RWCTRL_WRITE_BNDRY_1024);
14895 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
14897 struct tg3_internal_buffer_desc test_desc;
14898 u32 sram_dma_descs;
14901 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
14903 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
14904 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
14905 tw32(RDMAC_STATUS, 0);
14906 tw32(WDMAC_STATUS, 0);
14908 tw32(BUFMGR_MODE, 0);
14909 tw32(FTQ_RESET, 0);
14911 test_desc.addr_hi = ((u64) buf_dma) >> 32;
14912 test_desc.addr_lo = buf_dma & 0xffffffff;
14913 test_desc.nic_mbuf = 0x00002100;
14914 test_desc.len = size;
14917 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
14918 * the *second* time the tg3 driver was getting loaded after an
14921 * Broadcom tells me:
14922 * ...the DMA engine is connected to the GRC block and a DMA
14923 * reset may affect the GRC block in some unpredictable way...
14924 * The behavior of resets to individual blocks has not been tested.
14926 * Broadcom noted the GRC reset will also reset all sub-components.
14929 test_desc.cqid_sqid = (13 << 8) | 2;
14931 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
14934 test_desc.cqid_sqid = (16 << 8) | 7;
14936 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
14939 test_desc.flags = 0x00000005;
14941 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
14944 val = *(((u32 *)&test_desc) + i);
14945 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
14946 sram_dma_descs + (i * sizeof(u32)));
14947 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
14949 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
14952 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
14954 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
14957 for (i = 0; i < 40; i++) {
14961 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14963 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14964 if ((val & 0xffff) == sram_dma_descs) {
14975 #define TEST_BUFFER_SIZE 0x2000
14977 static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
14978 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14982 static int __devinit tg3_test_dma(struct tg3 *tp)
14984 dma_addr_t buf_dma;
14985 u32 *buf, saved_dma_rwctrl;
14988 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
14989 &buf_dma, GFP_KERNEL);
14995 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14996 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14998 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
15000 if (tg3_flag(tp, 57765_PLUS))
15003 if (tg3_flag(tp, PCI_EXPRESS)) {
15004 /* DMA read watermark not used on PCIE */
15005 tp->dma_rwctrl |= 0x00180000;
15006 } else if (!tg3_flag(tp, PCIX_MODE)) {
15007 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
15008 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
15009 tp->dma_rwctrl |= 0x003f0000;
15011 tp->dma_rwctrl |= 0x003f000f;
15013 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
15014 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
15015 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
15016 u32 read_water = 0x7;
15018 /* If the 5704 is behind the EPB bridge, we can
15019 * do the less restrictive ONE_DMA workaround for
15020 * better performance.
15022 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
15023 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
15024 tp->dma_rwctrl |= 0x8000;
15025 else if (ccval == 0x6 || ccval == 0x7)
15026 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
15028 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
15030 /* Set bit 23 to enable PCIX hw bug fix */
15032 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
15033 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
15035 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
15036 /* 5780 always in PCIX mode */
15037 tp->dma_rwctrl |= 0x00144000;
15038 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
15039 /* 5714 always in PCIX mode */
15040 tp->dma_rwctrl |= 0x00148000;
15042 tp->dma_rwctrl |= 0x001b000f;
15046 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
15047 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
15048 tp->dma_rwctrl &= 0xfffffff0;
15050 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
15051 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
15052 /* Remove this if it causes problems for some boards. */
15053 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
15055 /* On 5700/5701 chips, we need to set this bit.
15056 * Otherwise the chip will issue cacheline transactions
15057 * to streamable DMA memory with not all the byte
15058 * enables turned on. This is an error on several
15059 * RISC PCI controllers, in particular sparc64.
15061 * On 5703/5704 chips, this bit has been reassigned
15062 * a different meaning. In particular, it is used
15063 * on those chips to enable a PCI-X workaround.
15065 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
15068 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15071 /* Unneeded, already done by tg3_get_invariants. */
15072 tg3_switch_clocks(tp);
15075 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
15076 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
15079 /* It is best to perform DMA test with maximum write burst size
15080 * to expose the 5700/5701 write DMA bug.
15082 saved_dma_rwctrl = tp->dma_rwctrl;
15083 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15084 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15089 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
15092 /* Send the buffer to the chip. */
15093 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
15095 dev_err(&tp->pdev->dev,
15096 "%s: Buffer write failed. err = %d\n",
15102 /* validate data reached card RAM correctly. */
15103 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
15105 tg3_read_mem(tp, 0x2100 + (i*4), &val);
15106 if (le32_to_cpu(val) != p[i]) {
15107 dev_err(&tp->pdev->dev,
15108 "%s: Buffer corrupted on device! "
15109 "(%d != %d)\n", __func__, val, i);
15110 /* ret = -ENODEV here? */
15115 /* Now read it back. */
15116 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
15118 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
15119 "err = %d\n", __func__, ret);
15124 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
15128 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
15129 DMA_RWCTRL_WRITE_BNDRY_16) {
15130 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15131 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
15132 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15135 dev_err(&tp->pdev->dev,
15136 "%s: Buffer corrupted on read back! "
15137 "(%d != %d)\n", __func__, p[i], i);
15143 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
15149 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
15150 DMA_RWCTRL_WRITE_BNDRY_16) {
15151 /* DMA test passed without adjusting DMA boundary,
15152 * now look for chipsets that are known to expose the
15153 * DMA bug without failing the test.
15155 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
15156 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15157 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
15159 /* Safe to use the calculated DMA boundary. */
15160 tp->dma_rwctrl = saved_dma_rwctrl;
15163 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15167 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
15172 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
15174 if (tg3_flag(tp, 57765_PLUS)) {
15175 tp->bufmgr_config.mbuf_read_dma_low_water =
15176 DEFAULT_MB_RDMA_LOW_WATER_5705;
15177 tp->bufmgr_config.mbuf_mac_rx_low_water =
15178 DEFAULT_MB_MACRX_LOW_WATER_57765;
15179 tp->bufmgr_config.mbuf_high_water =
15180 DEFAULT_MB_HIGH_WATER_57765;
15182 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15183 DEFAULT_MB_RDMA_LOW_WATER_5705;
15184 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15185 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
15186 tp->bufmgr_config.mbuf_high_water_jumbo =
15187 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
15188 } else if (tg3_flag(tp, 5705_PLUS)) {
15189 tp->bufmgr_config.mbuf_read_dma_low_water =
15190 DEFAULT_MB_RDMA_LOW_WATER_5705;
15191 tp->bufmgr_config.mbuf_mac_rx_low_water =
15192 DEFAULT_MB_MACRX_LOW_WATER_5705;
15193 tp->bufmgr_config.mbuf_high_water =
15194 DEFAULT_MB_HIGH_WATER_5705;
15195 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
15196 tp->bufmgr_config.mbuf_mac_rx_low_water =
15197 DEFAULT_MB_MACRX_LOW_WATER_5906;
15198 tp->bufmgr_config.mbuf_high_water =
15199 DEFAULT_MB_HIGH_WATER_5906;
15202 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15203 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
15204 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15205 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
15206 tp->bufmgr_config.mbuf_high_water_jumbo =
15207 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
15209 tp->bufmgr_config.mbuf_read_dma_low_water =
15210 DEFAULT_MB_RDMA_LOW_WATER;
15211 tp->bufmgr_config.mbuf_mac_rx_low_water =
15212 DEFAULT_MB_MACRX_LOW_WATER;
15213 tp->bufmgr_config.mbuf_high_water =
15214 DEFAULT_MB_HIGH_WATER;
15216 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15217 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
15218 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15219 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
15220 tp->bufmgr_config.mbuf_high_water_jumbo =
15221 DEFAULT_MB_HIGH_WATER_JUMBO;
15224 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
15225 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
15228 static char * __devinit tg3_phy_string(struct tg3 *tp)
15230 switch (tp->phy_id & TG3_PHY_ID_MASK) {
15231 case TG3_PHY_ID_BCM5400: return "5400";
15232 case TG3_PHY_ID_BCM5401: return "5401";
15233 case TG3_PHY_ID_BCM5411: return "5411";
15234 case TG3_PHY_ID_BCM5701: return "5701";
15235 case TG3_PHY_ID_BCM5703: return "5703";
15236 case TG3_PHY_ID_BCM5704: return "5704";
15237 case TG3_PHY_ID_BCM5705: return "5705";
15238 case TG3_PHY_ID_BCM5750: return "5750";
15239 case TG3_PHY_ID_BCM5752: return "5752";
15240 case TG3_PHY_ID_BCM5714: return "5714";
15241 case TG3_PHY_ID_BCM5780: return "5780";
15242 case TG3_PHY_ID_BCM5755: return "5755";
15243 case TG3_PHY_ID_BCM5787: return "5787";
15244 case TG3_PHY_ID_BCM5784: return "5784";
15245 case TG3_PHY_ID_BCM5756: return "5722/5756";
15246 case TG3_PHY_ID_BCM5906: return "5906";
15247 case TG3_PHY_ID_BCM5761: return "5761";
15248 case TG3_PHY_ID_BCM5718C: return "5718C";
15249 case TG3_PHY_ID_BCM5718S: return "5718S";
15250 case TG3_PHY_ID_BCM57765: return "57765";
15251 case TG3_PHY_ID_BCM5719C: return "5719C";
15252 case TG3_PHY_ID_BCM5720C: return "5720C";
15253 case TG3_PHY_ID_BCM8002: return "8002/serdes";
15254 case 0: return "serdes";
15255 default: return "unknown";
15259 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
15261 if (tg3_flag(tp, PCI_EXPRESS)) {
15262 strcpy(str, "PCI Express");
15264 } else if (tg3_flag(tp, PCIX_MODE)) {
15265 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
15267 strcpy(str, "PCIX:");
15269 if ((clock_ctrl == 7) ||
15270 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
15271 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
15272 strcat(str, "133MHz");
15273 else if (clock_ctrl == 0)
15274 strcat(str, "33MHz");
15275 else if (clock_ctrl == 2)
15276 strcat(str, "50MHz");
15277 else if (clock_ctrl == 4)
15278 strcat(str, "66MHz");
15279 else if (clock_ctrl == 6)
15280 strcat(str, "100MHz");
15282 strcpy(str, "PCI:");
15283 if (tg3_flag(tp, PCI_HIGH_SPEED))
15284 strcat(str, "66MHz");
15286 strcat(str, "33MHz");
15288 if (tg3_flag(tp, PCI_32BIT))
15289 strcat(str, ":32-bit");
15291 strcat(str, ":64-bit");
15295 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
15297 struct pci_dev *peer;
15298 unsigned int func, devnr = tp->pdev->devfn & ~7;
15300 for (func = 0; func < 8; func++) {
15301 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15302 if (peer && peer != tp->pdev)
15306 /* 5704 can be configured in single-port mode, set peer to
15307 * tp->pdev in that case.
15315 * We don't need to keep the refcount elevated; there's no way
15316 * to remove one half of this device without removing the other
15323 static void __devinit tg3_init_coal(struct tg3 *tp)
15325 struct ethtool_coalesce *ec = &tp->coal;
15327 memset(ec, 0, sizeof(*ec));
15328 ec->cmd = ETHTOOL_GCOALESCE;
15329 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
15330 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
15331 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
15332 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
15333 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
15334 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
15335 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
15336 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
15337 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
15339 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
15340 HOSTCC_MODE_CLRTICK_TXBD)) {
15341 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
15342 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
15343 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
15344 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
15347 if (tg3_flag(tp, 5705_PLUS)) {
15348 ec->rx_coalesce_usecs_irq = 0;
15349 ec->tx_coalesce_usecs_irq = 0;
15350 ec->stats_block_coalesce_usecs = 0;
15354 static const struct net_device_ops tg3_netdev_ops = {
15355 .ndo_open = tg3_open,
15356 .ndo_stop = tg3_close,
15357 .ndo_start_xmit = tg3_start_xmit,
15358 .ndo_get_stats64 = tg3_get_stats64,
15359 .ndo_validate_addr = eth_validate_addr,
15360 .ndo_set_rx_mode = tg3_set_rx_mode,
15361 .ndo_set_mac_address = tg3_set_mac_addr,
15362 .ndo_do_ioctl = tg3_ioctl,
15363 .ndo_tx_timeout = tg3_tx_timeout,
15364 .ndo_change_mtu = tg3_change_mtu,
15365 .ndo_fix_features = tg3_fix_features,
15366 .ndo_set_features = tg3_set_features,
15367 #ifdef CONFIG_NET_POLL_CONTROLLER
15368 .ndo_poll_controller = tg3_poll_controller,
15372 static int __devinit tg3_init_one(struct pci_dev *pdev,
15373 const struct pci_device_id *ent)
15375 struct net_device *dev;
15377 int i, err, pm_cap;
15378 u32 sndmbx, rcvmbx, intmbx;
15380 u64 dma_mask, persist_dma_mask;
15383 printk_once(KERN_INFO "%s\n", version);
15385 err = pci_enable_device(pdev);
15387 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
15391 err = pci_request_regions(pdev, DRV_MODULE_NAME);
15393 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
15394 goto err_out_disable_pdev;
15397 pci_set_master(pdev);
15399 /* Find power-management capability. */
15400 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
15402 dev_err(&pdev->dev,
15403 "Cannot find Power Management capability, aborting\n");
15405 goto err_out_free_res;
15408 err = pci_set_power_state(pdev, PCI_D0);
15410 dev_err(&pdev->dev, "Transition to D0 failed, aborting\n");
15411 goto err_out_free_res;
15414 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
15416 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
15418 goto err_out_power_down;
15421 SET_NETDEV_DEV(dev, &pdev->dev);
15423 tp = netdev_priv(dev);
15426 tp->pm_cap = pm_cap;
15427 tp->rx_mode = TG3_DEF_RX_MODE;
15428 tp->tx_mode = TG3_DEF_TX_MODE;
15432 tp->msg_enable = tg3_debug;
15434 tp->msg_enable = TG3_DEF_MSG_ENABLE;
15436 /* The word/byte swap controls here control register access byte
15437 * swapping. DMA data byte swapping is controlled in the GRC_MODE
15440 tp->misc_host_ctrl =
15441 MISC_HOST_CTRL_MASK_PCI_INT |
15442 MISC_HOST_CTRL_WORD_SWAP |
15443 MISC_HOST_CTRL_INDIR_ACCESS |
15444 MISC_HOST_CTRL_PCISTATE_RW;
15446 /* The NONFRM (non-frame) byte/word swap controls take effect
15447 * on descriptor entries, anything which isn't packet data.
15449 * The StrongARM chips on the board (one for tx, one for rx)
15450 * are running in big-endian mode.
15452 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
15453 GRC_MODE_WSWAP_NONFRM_DATA);
15454 #ifdef __BIG_ENDIAN
15455 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
15457 spin_lock_init(&tp->lock);
15458 spin_lock_init(&tp->indirect_lock);
15459 INIT_WORK(&tp->reset_task, tg3_reset_task);
15461 tp->regs = pci_ioremap_bar(pdev, BAR_0);
15463 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
15465 goto err_out_free_dev;
15468 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
15469 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
15470 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
15471 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
15472 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15473 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
15474 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
15475 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) {
15476 tg3_flag_set(tp, ENABLE_APE);
15477 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
15478 if (!tp->aperegs) {
15479 dev_err(&pdev->dev,
15480 "Cannot map APE registers, aborting\n");
15482 goto err_out_iounmap;
15486 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
15487 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
15489 dev->ethtool_ops = &tg3_ethtool_ops;
15490 dev->watchdog_timeo = TG3_TX_TIMEOUT;
15491 dev->netdev_ops = &tg3_netdev_ops;
15492 dev->irq = pdev->irq;
15494 err = tg3_get_invariants(tp);
15496 dev_err(&pdev->dev,
15497 "Problem fetching invariants of chip, aborting\n");
15498 goto err_out_apeunmap;
15501 /* The EPB bridge inside 5714, 5715, and 5780 and any
15502 * device behind the EPB cannot support DMA addresses > 40-bit.
15503 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
15504 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
15505 * do DMA address check in tg3_start_xmit().
15507 if (tg3_flag(tp, IS_5788))
15508 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
15509 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
15510 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
15511 #ifdef CONFIG_HIGHMEM
15512 dma_mask = DMA_BIT_MASK(64);
15515 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
15517 /* Configure DMA attributes. */
15518 if (dma_mask > DMA_BIT_MASK(32)) {
15519 err = pci_set_dma_mask(pdev, dma_mask);
15521 features |= NETIF_F_HIGHDMA;
15522 err = pci_set_consistent_dma_mask(pdev,
15525 dev_err(&pdev->dev, "Unable to obtain 64 bit "
15526 "DMA for consistent allocations\n");
15527 goto err_out_apeunmap;
15531 if (err || dma_mask == DMA_BIT_MASK(32)) {
15532 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
15534 dev_err(&pdev->dev,
15535 "No usable DMA configuration, aborting\n");
15536 goto err_out_apeunmap;
15540 tg3_init_bufmgr_config(tp);
15542 features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
15544 /* 5700 B0 chips do not support checksumming correctly due
15545 * to hardware bugs.
15547 if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) {
15548 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
15550 if (tg3_flag(tp, 5755_PLUS))
15551 features |= NETIF_F_IPV6_CSUM;
15554 /* TSO is on by default on chips that support hardware TSO.
15555 * Firmware TSO on older chips gives lower performance, so it
15556 * is off by default, but can be enabled using ethtool.
15558 if ((tg3_flag(tp, HW_TSO_1) ||
15559 tg3_flag(tp, HW_TSO_2) ||
15560 tg3_flag(tp, HW_TSO_3)) &&
15561 (features & NETIF_F_IP_CSUM))
15562 features |= NETIF_F_TSO;
15563 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
15564 if (features & NETIF_F_IPV6_CSUM)
15565 features |= NETIF_F_TSO6;
15566 if (tg3_flag(tp, HW_TSO_3) ||
15567 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
15568 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
15569 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
15570 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
15571 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
15572 features |= NETIF_F_TSO_ECN;
15575 dev->features |= features;
15576 dev->vlan_features |= features;
15579 * Add loopback capability only for a subset of devices that support
15580 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
15581 * loopback for the remaining devices.
15583 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
15584 !tg3_flag(tp, CPMU_PRESENT))
15585 /* Add the loopback capability */
15586 features |= NETIF_F_LOOPBACK;
15588 dev->hw_features |= features;
15590 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
15591 !tg3_flag(tp, TSO_CAPABLE) &&
15592 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
15593 tg3_flag_set(tp, MAX_RXPEND_64);
15594 tp->rx_pending = 63;
15597 err = tg3_get_device_address(tp);
15599 dev_err(&pdev->dev,
15600 "Could not obtain valid ethernet address, aborting\n");
15601 goto err_out_apeunmap;
15605 * Reset chip in case UNDI or EFI driver did not shutdown
15606 * DMA self test will enable WDMAC and we'll see (spurious)
15607 * pending DMA on the PCI bus at that point.
15609 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
15610 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
15611 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
15612 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15615 err = tg3_test_dma(tp);
15617 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
15618 goto err_out_apeunmap;
15621 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
15622 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
15623 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
15624 for (i = 0; i < tp->irq_max; i++) {
15625 struct tg3_napi *tnapi = &tp->napi[i];
15628 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
15630 tnapi->int_mbox = intmbx;
15636 tnapi->consmbox = rcvmbx;
15637 tnapi->prodmbox = sndmbx;
15640 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
15642 tnapi->coal_now = HOSTCC_MODE_NOW;
15644 if (!tg3_flag(tp, SUPPORT_MSIX))
15648 * If we support MSIX, we'll be using RSS. If we're using
15649 * RSS, the first vector only handles link interrupts and the
15650 * remaining vectors handle rx and tx interrupts. Reuse the
15651 * mailbox values for the next iteration. The values we setup
15652 * above are still useful for the single vectored mode.
15667 pci_set_drvdata(pdev, dev);
15669 if (tg3_flag(tp, 5717_PLUS)) {
15670 /* Resume a low-power mode */
15671 tg3_frob_aux_power(tp, false);
15674 err = register_netdev(dev);
15676 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
15677 goto err_out_apeunmap;
15680 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
15681 tp->board_part_number,
15682 tp->pci_chip_rev_id,
15683 tg3_bus_string(tp, str),
15686 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
15687 struct phy_device *phydev;
15688 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
15690 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
15691 phydev->drv->name, dev_name(&phydev->dev));
15695 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
15696 ethtype = "10/100Base-TX";
15697 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
15698 ethtype = "1000Base-SX";
15700 ethtype = "10/100/1000Base-T";
15702 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
15703 "(WireSpeed[%d], EEE[%d])\n",
15704 tg3_phy_string(tp), ethtype,
15705 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
15706 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
15709 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
15710 (dev->features & NETIF_F_RXCSUM) != 0,
15711 tg3_flag(tp, USE_LINKCHG_REG) != 0,
15712 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
15713 tg3_flag(tp, ENABLE_ASF) != 0,
15714 tg3_flag(tp, TSO_CAPABLE) != 0);
15715 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
15717 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
15718 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
15720 pci_save_state(pdev);
15726 iounmap(tp->aperegs);
15727 tp->aperegs = NULL;
15739 err_out_power_down:
15740 pci_set_power_state(pdev, PCI_D3hot);
15743 pci_release_regions(pdev);
15745 err_out_disable_pdev:
15746 pci_disable_device(pdev);
15747 pci_set_drvdata(pdev, NULL);
15751 static void __devexit tg3_remove_one(struct pci_dev *pdev)
15753 struct net_device *dev = pci_get_drvdata(pdev);
15756 struct tg3 *tp = netdev_priv(dev);
15759 release_firmware(tp->fw);
15761 tg3_reset_task_cancel(tp);
15763 if (tg3_flag(tp, USE_PHYLIB)) {
15768 unregister_netdev(dev);
15770 iounmap(tp->aperegs);
15771 tp->aperegs = NULL;
15778 pci_release_regions(pdev);
15779 pci_disable_device(pdev);
15780 pci_set_drvdata(pdev, NULL);
15784 #ifdef CONFIG_PM_SLEEP
15785 static int tg3_suspend(struct device *device)
15787 struct pci_dev *pdev = to_pci_dev(device);
15788 struct net_device *dev = pci_get_drvdata(pdev);
15789 struct tg3 *tp = netdev_priv(dev);
15792 if (!netif_running(dev))
15795 tg3_reset_task_cancel(tp);
15797 tg3_netif_stop(tp);
15799 del_timer_sync(&tp->timer);
15801 tg3_full_lock(tp, 1);
15802 tg3_disable_ints(tp);
15803 tg3_full_unlock(tp);
15805 netif_device_detach(dev);
15807 tg3_full_lock(tp, 0);
15808 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15809 tg3_flag_clear(tp, INIT_COMPLETE);
15810 tg3_full_unlock(tp);
15812 err = tg3_power_down_prepare(tp);
15816 tg3_full_lock(tp, 0);
15818 tg3_flag_set(tp, INIT_COMPLETE);
15819 err2 = tg3_restart_hw(tp, 1);
15823 tp->timer.expires = jiffies + tp->timer_offset;
15824 add_timer(&tp->timer);
15826 netif_device_attach(dev);
15827 tg3_netif_start(tp);
15830 tg3_full_unlock(tp);
15839 static int tg3_resume(struct device *device)
15841 struct pci_dev *pdev = to_pci_dev(device);
15842 struct net_device *dev = pci_get_drvdata(pdev);
15843 struct tg3 *tp = netdev_priv(dev);
15846 if (!netif_running(dev))
15849 netif_device_attach(dev);
15851 tg3_full_lock(tp, 0);
15853 tg3_flag_set(tp, INIT_COMPLETE);
15854 err = tg3_restart_hw(tp, 1);
15858 tp->timer.expires = jiffies + tp->timer_offset;
15859 add_timer(&tp->timer);
15861 tg3_netif_start(tp);
15864 tg3_full_unlock(tp);
15872 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
15873 #define TG3_PM_OPS (&tg3_pm_ops)
15877 #define TG3_PM_OPS NULL
15879 #endif /* CONFIG_PM_SLEEP */
15882 * tg3_io_error_detected - called when PCI error is detected
15883 * @pdev: Pointer to PCI device
15884 * @state: The current pci connection state
15886 * This function is called after a PCI bus error affecting
15887 * this device has been detected.
15889 static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
15890 pci_channel_state_t state)
15892 struct net_device *netdev = pci_get_drvdata(pdev);
15893 struct tg3 *tp = netdev_priv(netdev);
15894 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
15896 netdev_info(netdev, "PCI I/O error detected\n");
15900 if (!netif_running(netdev))
15905 tg3_netif_stop(tp);
15907 del_timer_sync(&tp->timer);
15909 /* Want to make sure that the reset task doesn't run */
15910 tg3_reset_task_cancel(tp);
15911 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
15913 netif_device_detach(netdev);
15915 /* Clean up software state, even if MMIO is blocked */
15916 tg3_full_lock(tp, 0);
15917 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
15918 tg3_full_unlock(tp);
15921 if (state == pci_channel_io_perm_failure)
15922 err = PCI_ERS_RESULT_DISCONNECT;
15924 pci_disable_device(pdev);
15932 * tg3_io_slot_reset - called after the pci bus has been reset.
15933 * @pdev: Pointer to PCI device
15935 * Restart the card from scratch, as if from a cold-boot.
15936 * At this point, the card has exprienced a hard reset,
15937 * followed by fixups by BIOS, and has its config space
15938 * set up identically to what it was at cold boot.
15940 static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
15942 struct net_device *netdev = pci_get_drvdata(pdev);
15943 struct tg3 *tp = netdev_priv(netdev);
15944 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
15949 if (pci_enable_device(pdev)) {
15950 netdev_err(netdev, "Cannot re-enable PCI device after reset.\n");
15954 pci_set_master(pdev);
15955 pci_restore_state(pdev);
15956 pci_save_state(pdev);
15958 if (!netif_running(netdev)) {
15959 rc = PCI_ERS_RESULT_RECOVERED;
15963 err = tg3_power_up(tp);
15967 rc = PCI_ERS_RESULT_RECOVERED;
15976 * tg3_io_resume - called when traffic can start flowing again.
15977 * @pdev: Pointer to PCI device
15979 * This callback is called when the error recovery driver tells
15980 * us that its OK to resume normal operation.
15982 static void tg3_io_resume(struct pci_dev *pdev)
15984 struct net_device *netdev = pci_get_drvdata(pdev);
15985 struct tg3 *tp = netdev_priv(netdev);
15990 if (!netif_running(netdev))
15993 tg3_full_lock(tp, 0);
15994 tg3_flag_set(tp, INIT_COMPLETE);
15995 err = tg3_restart_hw(tp, 1);
15996 tg3_full_unlock(tp);
15998 netdev_err(netdev, "Cannot restart hardware after reset.\n");
16002 netif_device_attach(netdev);
16004 tp->timer.expires = jiffies + tp->timer_offset;
16005 add_timer(&tp->timer);
16007 tg3_netif_start(tp);
16015 static struct pci_error_handlers tg3_err_handler = {
16016 .error_detected = tg3_io_error_detected,
16017 .slot_reset = tg3_io_slot_reset,
16018 .resume = tg3_io_resume
16021 static struct pci_driver tg3_driver = {
16022 .name = DRV_MODULE_NAME,
16023 .id_table = tg3_pci_tbl,
16024 .probe = tg3_init_one,
16025 .remove = __devexit_p(tg3_remove_one),
16026 .err_handler = &tg3_err_handler,
16027 .driver.pm = TG3_PM_OPS,
16030 static int __init tg3_init(void)
16032 return pci_register_driver(&tg3_driver);
16035 static void __exit tg3_cleanup(void)
16037 pci_unregister_driver(&tg3_driver);
16040 module_init(tg3_init);
16041 module_exit(tg3_cleanup);