drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

   1 /* Copyright 2008-2012 Broadcom Corporation
   2  *
   3  * Unless you and Broadcom execute a separate written software license
   4  * agreement governing use of this software, this software is licensed to you
   5  * under the terms of the GNU General Public License version 2, available
   6  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
   7  *
   8  * Notwithstanding the above, under no circumstances may you combine this
   9  * software in any way with any other Broadcom software provided under a
  10  * license other than the GPL, without Broadcom's express prior written
  11  * consent.
  12  *
  13  * Written by Yaniv Rosner
  14  *
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/delay.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/mutex.h>
  26
  27 #include "bnx2x.h"
  28 #include "bnx2x_cmn.h"
  29
  30 /********************************************************/
  31 #define ETH_HLEN                        14
  32 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
  33 #define ETH_OVREHEAD                    (ETH_HLEN + 8 + 8)
  34 #define ETH_MIN_PACKET_SIZE             60
  35 #define ETH_MAX_PACKET_SIZE             1500
  36 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
  37 #define MDIO_ACCESS_TIMEOUT             1000
  38 #define WC_LANE_MAX                     4
  39 #define I2C_SWITCH_WIDTH                2
  40 #define I2C_BSC0                        0
  41 #define I2C_BSC1                        1
  42 #define I2C_WA_RETRY_CNT                3
  43 #define MCPR_IMC_COMMAND_READ_OP        1
  44 #define MCPR_IMC_COMMAND_WRITE_OP       2
  45
  46 /* LED Blink rate that will achieve ~15.9Hz */
  47 #define LED_BLINK_RATE_VAL_E3           354
  48 #define LED_BLINK_RATE_VAL_E1X_E2       480
  49 /***********************************************************/
  50 /*                      Shortcut definitions               */
  51 /***********************************************************/
  52
  53 #define NIG_LATCH_BC_ENABLE_MI_INT 0
  54
  55 #define NIG_STATUS_EMAC0_MI_INT \
  56                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
  57 #define NIG_STATUS_XGXS0_LINK10G \
  58                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
  59 #define NIG_STATUS_XGXS0_LINK_STATUS \
  60                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
  61 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
  62                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
  63 #define NIG_STATUS_SERDES0_LINK_STATUS \
  64                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
  65 #define NIG_MASK_MI_INT \
  66                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
  67 #define NIG_MASK_XGXS0_LINK10G \
  68                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
  69 #define NIG_MASK_XGXS0_LINK_STATUS \
  70                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
  71 #define NIG_MASK_SERDES0_LINK_STATUS \
  72                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
  73
  74 #define MDIO_AN_CL73_OR_37_COMPLETE \
  75                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
  76                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
  77
  78 #define XGXS_RESET_BITS \
  79         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
  80          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
  81          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
  82          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
  83          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
  84
  85 #define SERDES_RESET_BITS \
  86         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
  87          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
  88          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
  89          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
  90
  91 #define AUTONEG_CL37            SHARED_HW_CFG_AN_ENABLE_CL37
  92 #define AUTONEG_CL73            SHARED_HW_CFG_AN_ENABLE_CL73
  93 #define AUTONEG_BAM             SHARED_HW_CFG_AN_ENABLE_BAM
  94 #define AUTONEG_PARALLEL \
  95                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
  96 #define AUTONEG_SGMII_FIBER_AUTODET \
  97                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
  98 #define AUTONEG_REMOTE_PHY      SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
  99
 100 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
 101                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
 102 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
 103                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
 104 #define GP_STATUS_SPEED_MASK \
 105                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
 106 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
 107 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
 108 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
 109 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
 110 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
 111 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
 112 #define GP_STATUS_10G_HIG \
 113                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
 114 #define GP_STATUS_10G_CX4 \
 115                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
 116 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
 117 #define GP_STATUS_10G_KX4 \
 118                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
 119 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
 120 #define GP_STATUS_10G_XFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
 121 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
 122 #define GP_STATUS_10G_SFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
 123 #define LINK_10THD              LINK_STATUS_SPEED_AND_DUPLEX_10THD
 124 #define LINK_10TFD              LINK_STATUS_SPEED_AND_DUPLEX_10TFD
 125 #define LINK_100TXHD            LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
 126 #define LINK_100T4              LINK_STATUS_SPEED_AND_DUPLEX_100T4
 127 #define LINK_100TXFD            LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
 128 #define LINK_1000THD            LINK_STATUS_SPEED_AND_DUPLEX_1000THD
 129 #define LINK_1000TFD            LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
 130 #define LINK_1000XFD            LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
 131 #define LINK_2500THD            LINK_STATUS_SPEED_AND_DUPLEX_2500THD
 132 #define LINK_2500TFD            LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
 133 #define LINK_2500XFD            LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
 134 #define LINK_10GTFD             LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
 135 #define LINK_10GXFD             LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
 136 #define LINK_20GTFD             LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
 137 #define LINK_20GXFD             LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
 138
 139
 140
 141 #define SFP_EEPROM_CON_TYPE_ADDR                0x2
 142         #define SFP_EEPROM_CON_TYPE_VAL_LC      0x7
 143         #define SFP_EEPROM_CON_TYPE_VAL_COPPER  0x21
 144
 145
 146 #define SFP_EEPROM_COMP_CODE_ADDR               0x3
 147         #define SFP_EEPROM_COMP_CODE_SR_MASK    (1<<4)
 148         #define SFP_EEPROM_COMP_CODE_LR_MASK    (1<<5)
 149         #define SFP_EEPROM_COMP_CODE_LRM_MASK   (1<<6)
 150
 151 #define SFP_EEPROM_FC_TX_TECH_ADDR              0x8
 152         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
 153         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE  0x8
 154
 155 #define SFP_EEPROM_OPTIONS_ADDR                 0x40
 156         #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
 157 #define SFP_EEPROM_OPTIONS_SIZE                 2
 158
 159 #define EDC_MODE_LINEAR                         0x0022
 160 #define EDC_MODE_LIMITING                               0x0044
 161 #define EDC_MODE_PASSIVE_DAC                    0x0055
 162
 163 /* BRB default for class 0 E2 */
 164 #define DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR      170
 165 #define DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR               250
 166 #define DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR               10
 167 #define DEFAULT0_E2_BRB_MAC_FULL_XON_THR                50
 168
 169 /* BRB thresholds for E2*/
 170 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE             170
 171 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE         0
 172
 173 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE              250
 174 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE          0
 175
 176 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE              10
 177 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE          90
 178
 179 #define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE                       50
 180 #define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE           250
 181
 182 /* BRB default for class 0 E3A0 */
 183 #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR    290
 184 #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR     410
 185 #define DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR     10
 186 #define DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR      50
 187
 188 /* BRB thresholds for E3A0 */
 189 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE           290
 190 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE               0
 191
 192 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE            410
 193 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE                0
 194
 195 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE            10
 196 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE                170
 197
 198 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE             50
 199 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE         410
 200
 201 /* BRB default for E3B0 */
 202 #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR    330
 203 #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR     490
 204 #define DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR     15
 205 #define DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR      55
 206
 207 /* BRB thresholds for E3B0 2 port mode*/
 208 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE                1025
 209 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE    0
 210
 211 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE         1025
 212 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE     0
 213
 214 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE         10
 215 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE     1025
 216
 217 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE          50
 218 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE      1025
 219
 220 /* only for E3B0*/
 221 #define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR                        1025
 222 #define PFC_E3B0_2P_BRB_FULL_LB_XON_THR                 1025
 223
 224 /* Lossy +Lossless GUARANTIED == GUART */
 225 #define PFC_E3B0_2P_MIX_PAUSE_LB_GUART                  284
 226 /* Lossless +Lossless*/
 227 #define PFC_E3B0_2P_PAUSE_LB_GUART                      236
 228 /* Lossy +Lossy*/
 229 #define PFC_E3B0_2P_NON_PAUSE_LB_GUART                  342
 230
 231 /* Lossy +Lossless*/
 232 #define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART               284
 233 /* Lossless +Lossless*/
 234 #define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART           236
 235 /* Lossy +Lossy*/
 236 #define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART               336
 237 #define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST                80
 238
 239 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART             0
 240 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST                0
 241
 242 /* BRB thresholds for E3B0 4 port mode */
 243 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE                304
 244 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE    0
 245
 246 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE         384
 247 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE     0
 248
 249 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE         10
 250 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE     304
 251
 252 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE          50
 253 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE      384
 254
 255 /* only for E3B0*/
 256 #define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR                        304
 257 #define PFC_E3B0_4P_BRB_FULL_LB_XON_THR                 384
 258 #define PFC_E3B0_4P_LB_GUART            120
 259
 260 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART             120
 261 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST        80
 262
 263 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART             80
 264 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST        120
 265
 266 /* Pause defines*/
 267 #define DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR                       330
 268 #define DEFAULT_E3B0_BRB_FULL_LB_XON_THR                        490
 269 #define DEFAULT_E3B0_LB_GUART           40
 270
 271 #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART            40
 272 #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST       0
 273
 274 #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART            40
 275 #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST       0
 276
 277 /* ETS defines*/
 278 #define DCBX_INVALID_COS                                        (0xFF)
 279
 280 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND         (0x5000)
 281 #define ETS_BW_LIMIT_CREDIT_WEIGHT              (0x5000)
 282 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS             (1360)
 283 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS                   (2720)
 284 #define ETS_E3B0_PBF_MIN_W_VAL                          (10000)
 285
 286 #define MAX_PACKET_SIZE                                 (9700)
 287 #define WC_UC_TIMEOUT                                   100
 288 #define MAX_KR_LINK_RETRY                               4
 289
 290 /**********************************************************/
 291 /*                     INTERFACE                          */
 292 /**********************************************************/
 293
 294 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 295         bnx2x_cl45_write(_bp, _phy, \
 296                 (_phy)->def_md_devad, \
 297                 (_bank + (_addr & 0xf)), \
 298                 _val)
 299
 300 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 301         bnx2x_cl45_read(_bp, _phy, \
 302                 (_phy)->def_md_devad, \
 303                 (_bank + (_addr & 0xf)), \
 304                 _val)
 305
 306 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
 307 {
 308         u32 val = REG_RD(bp, reg);
 309
 310         val |= bits;
 311         REG_WR(bp, reg, val);
 312         return val;
 313 }
 314
 315 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
 316 {
 317         u32 val = REG_RD(bp, reg);
 318
 319         val &= ~bits;
 320         REG_WR(bp, reg, val);
 321         return val;
 322 }
 323
 324 /******************************************************************/
 325 /*                      EPIO/GPIO section                         */
 326 /******************************************************************/
 327 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
 328 {
 329         u32 epio_mask, gp_oenable;
 330         *en = 0;
 331         /* Sanity check */
 332         if (epio_pin > 31) {
 333                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
 334                 return;
 335         }
 336
 337         epio_mask = 1 << epio_pin;
 338         /* Set this EPIO to output */
 339         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 340         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
 341
 342         *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
 343 }
 344 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
 345 {
 346         u32 epio_mask, gp_output, gp_oenable;
 347
 348         /* Sanity check */
 349         if (epio_pin > 31) {
 350                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
 351                 return;
 352         }
 353         DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
 354         epio_mask = 1 << epio_pin;
 355         /* Set this EPIO to output */
 356         gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
 357         if (en)
 358                 gp_output |= epio_mask;
 359         else
 360                 gp_output &= ~epio_mask;
 361
 362         REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
 363
 364         /* Set the value for this EPIO */
 365         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 366         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
 367 }
 368
 369 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
 370 {
 371         if (pin_cfg == PIN_CFG_NA)
 372                 return;
 373         if (pin_cfg >= PIN_CFG_EPIO0) {
 374                 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 375         } else {
 376                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 377                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 378                 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
 379         }
 380 }
 381
 382 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
 383 {
 384         if (pin_cfg == PIN_CFG_NA)
 385                 return -EINVAL;
 386         if (pin_cfg >= PIN_CFG_EPIO0) {
 387                 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 388         } else {
 389                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 390                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 391                 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
 392         }
 393         return 0;
 394
 395 }
 396 /******************************************************************/
 397 /*                              ETS section                       */
 398 /******************************************************************/
 399 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
 400 {
 401         /* ETS disabled configuration*/
 402         struct bnx2x *bp = params->bp;
 403
 404         DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
 405
 406         /* mapping between entry  priority to client number (0,1,2 -debug and
 407          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 408          * 3bits client num.
 409          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 410          * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
 411          */
 412
 413         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
 414         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
 415          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 416          * COS0 entry, 4 - COS1 entry.
 417          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 418          * bit4   bit3    bit2   bit1     bit0
 419          * MCP and debug are strict
 420          */
 421
 422         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 423         /* defines which entries (clients) are subjected to WFQ arbitration */
 424         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 425         /* For strict priority entries defines the number of consecutive
 426          * slots for the highest priority.
 427          */
 428         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 429         /* mapping between the CREDIT_WEIGHT registers and actual client
 430          * numbers
 431          */
 432         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
 433         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
 434         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
 435
 436         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
 437         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
 438         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
 439         /* ETS mode disable */
 440         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 441         /* If ETS mode is enabled (there is no strict priority) defines a WFQ
 442          * weight for COS0/COS1.
 443          */
 444         REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
 445         REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
 446         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
 447         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
 448         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
 449         /* Defines the number of consecutive slots for the strict priority */
 450         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 451 }
 452 /******************************************************************************
 453 * Description:
 454 *       Getting min_w_val will be set according to line speed .
 455 *.
 456 ******************************************************************************/
 457 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
 458 {
 459         u32 min_w_val = 0;
 460         /* Calculate min_w_val.*/
 461         if (vars->link_up) {
 462                 if (vars->line_speed == SPEED_20000)
 463                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 464                 else
 465                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
 466         } else
 467                 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 468         /* If the link isn't up (static configuration for example ) The
 469          * link will be according to 20GBPS.
 470          */
 471         return min_w_val;
 472 }
 473 /******************************************************************************
 474 * Description:
 475 *       Getting credit upper bound form min_w_val.
 476 *.
 477 ******************************************************************************/
 478 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
 479 {
 480         const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
 481                                                 MAX_PACKET_SIZE);
 482         return credit_upper_bound;
 483 }
 484 /******************************************************************************
 485 * Description:
 486 *       Set credit upper bound for NIG.
 487 *.
 488 ******************************************************************************/
 489 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
 490         const struct link_params *params,
 491         const u32 min_w_val)
 492 {
 493         struct bnx2x *bp = params->bp;
 494         const u8 port = params->port;
 495         const u32 credit_upper_bound =
 496             bnx2x_ets_get_credit_upper_bound(min_w_val);
 497
 498         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
 499                 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
 500         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
 501                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
 502         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
 503                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
 504         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
 505                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
 506         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
 507                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
 508         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
 509                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
 510
 511         if (!port) {
 512                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
 513                         credit_upper_bound);
 514                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
 515                         credit_upper_bound);
 516                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
 517                         credit_upper_bound);
 518         }
 519 }
 520 /******************************************************************************
 521 * Description:
 522 *       Will return the NIG ETS registers to init values.Except
 523 *       credit_upper_bound.
 524 *       That isn't used in this configuration (No WFQ is enabled) and will be
 525 *       configured acording to spec
 526 *.
 527 ******************************************************************************/
 528 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
 529                                         const struct link_vars *vars)
 530 {
 531         struct bnx2x *bp = params->bp;
 532         const u8 port = params->port;
 533         const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
 534         /* Mapping between entry  priority to client number (0,1,2 -debug and
 535          * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
 536          * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
 537          * reset value or init tool
 538          */
 539         if (port) {
 540                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
 541                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
 542         } else {
 543                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
 544                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
 545         }
 546         /* For strict priority entries defines the number of consecutive
 547          * slots for the highest priority.
 548          */
 549         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
 550                    NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 551         /* Mapping between the CREDIT_WEIGHT registers and actual client
 552          * numbers
 553          */
 554         if (port) {
 555                 /*Port 1 has 6 COS*/
 556                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
 557                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
 558         } else {
 559                 /*Port 0 has 9 COS*/
 560                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
 561                        0x43210876);
 562                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
 563         }
 564
 565         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
 566          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 567          * COS0 entry, 4 - COS1 entry.
 568          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 569          * bit4   bit3    bit2   bit1     bit0
 570          * MCP and debug are strict
 571          */
 572         if (port)
 573                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
 574         else
 575                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
 576         /* defines which entries (clients) are subjected to WFQ arbitration */
 577         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 578                    NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 579
 580         /* Please notice the register address are note continuous and a
 581          * for here is note appropriate.In 2 port mode port0 only COS0-5
 582          * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
 583          * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
 584          * are never used for WFQ
 585          */
 586         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 587                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
 588         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 589                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
 590         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 591                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
 592         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
 593                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
 594         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
 595                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
 596         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
 597                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
 598         if (!port) {
 599                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
 600                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
 601                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
 602         }
 603
 604         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
 605 }
 606 /******************************************************************************
 607 * Description:
 608 *       Set credit upper bound for PBF.
 609 *.
 610 ******************************************************************************/
 611 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
 612         const struct link_params *params,
 613         const u32 min_w_val)
 614 {
 615         struct bnx2x *bp = params->bp;
 616         const u32 credit_upper_bound =
 617             bnx2x_ets_get_credit_upper_bound(min_w_val);
 618         const u8 port = params->port;
 619         u32 base_upper_bound = 0;
 620         u8 max_cos = 0;
 621         u8 i = 0;
 622         /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
 623          * port mode port1 has COS0-2 that can be used for WFQ.
 624          */
 625         if (!port) {
 626                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
 627                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 628         } else {
 629                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
 630                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 631         }
 632
 633         for (i = 0; i < max_cos; i++)
 634                 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
 635 }
 636
 637 /******************************************************************************
 638 * Description:
 639 *       Will return the PBF ETS registers to init values.Except
 640 *       credit_upper_bound.
 641 *       That isn't used in this configuration (No WFQ is enabled) and will be
 642 *       configured acording to spec
 643 *.
 644 ******************************************************************************/
 645 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
 646 {
 647         struct bnx2x *bp = params->bp;
 648         const u8 port = params->port;
 649         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
 650         u8 i = 0;
 651         u32 base_weight = 0;
 652         u8 max_cos = 0;
 653
 654         /* Mapping between entry  priority to client number 0 - COS0
 655          * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
 656          * TODO_ETS - Should be done by reset value or init tool
 657          */
 658         if (port)
 659                 /*  0x688 (|011|0 10|00 1|000) */
 660                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
 661         else
 662                 /*  (10 1|100 |011|0 10|00 1|000) */
 663                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
 664
 665         /* TODO_ETS - Should be done by reset value or init tool */
 666         if (port)
 667                 /* 0x688 (|011|0 10|00 1|000)*/
 668                 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
 669         else
 670         /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
 671         REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
 672
 673         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
 674                    PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
 675
 676
 677         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 678                    PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
 679
 680         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 681                    PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
 682         /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
 683          * In 4 port mode port1 has COS0-2 that can be used for WFQ.
 684          */
 685         if (!port) {
 686                 base_weight = PBF_REG_COS0_WEIGHT_P0;
 687                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 688         } else {
 689                 base_weight = PBF_REG_COS0_WEIGHT_P1;
 690                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 691         }
 692
 693         for (i = 0; i < max_cos; i++)
 694                 REG_WR(bp, base_weight + (0x4 * i), 0);
 695
 696         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
 697 }
 698 /******************************************************************************
 699 * Description:
 700 *       E3B0 disable will return basicly the values to init values.
 701 *.
 702 ******************************************************************************/
 703 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
 704                                    const struct link_vars *vars)
 705 {
 706         struct bnx2x *bp = params->bp;
 707
 708         if (!CHIP_IS_E3B0(bp)) {
 709                 DP(NETIF_MSG_LINK,
 710                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
 711                 return -EINVAL;
 712         }
 713
 714         bnx2x_ets_e3b0_nig_disabled(params, vars);
 715
 716         bnx2x_ets_e3b0_pbf_disabled(params);
 717
 718         return 0;
 719 }
 720
 721 /******************************************************************************
 722 * Description:
 723 *       Disable will return basicly the values to init values.
 724 *
 725 ******************************************************************************/
 726 int bnx2x_ets_disabled(struct link_params *params,
 727                       struct link_vars *vars)
 728 {
 729         struct bnx2x *bp = params->bp;
 730         int bnx2x_status = 0;
 731
 732         if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
 733                 bnx2x_ets_e2e3a0_disabled(params);
 734         else if (CHIP_IS_E3B0(bp))
 735                 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
 736         else {
 737                 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
 738                 return -EINVAL;
 739         }
 740
 741         return bnx2x_status;
 742 }
 743
 744 /******************************************************************************
 745 * Description
 746 *       Set the COS mappimg to SP and BW until this point all the COS are not
 747 *       set as SP or BW.
 748 ******************************************************************************/
 749 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
 750                                   const struct bnx2x_ets_params *ets_params,
 751                                   const u8 cos_sp_bitmap,
 752                                   const u8 cos_bw_bitmap)
 753 {
 754         struct bnx2x *bp = params->bp;
 755         const u8 port = params->port;
 756         const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
 757         const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
 758         const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
 759         const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
 760
 761         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
 762                NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
 763
 764         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 765                PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
 766
 767         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 768                NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
 769                nig_cli_subject2wfq_bitmap);
 770
 771         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 772                PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
 773                pbf_cli_subject2wfq_bitmap);
 774
 775         return 0;
 776 }
 777
 778 /******************************************************************************
 779 * Description:
 780 *       This function is needed because NIG ARB_CREDIT_WEIGHT_X are
 781 *       not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
 782 ******************************************************************************/
 783 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
 784                                      const u8 cos_entry,
 785                                      const u32 min_w_val_nig,
 786                                      const u32 min_w_val_pbf,
 787                                      const u16 total_bw,
 788                                      const u8 bw,
 789                                      const u8 port)
 790 {
 791         u32 nig_reg_adress_crd_weight = 0;
 792         u32 pbf_reg_adress_crd_weight = 0;
 793         /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
 794         const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
 795         const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
 796
 797         switch (cos_entry) {
 798         case 0:
 799             nig_reg_adress_crd_weight =
 800                  (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 801                      NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
 802              pbf_reg_adress_crd_weight = (port) ?
 803                  PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
 804              break;
 805         case 1:
 806              nig_reg_adress_crd_weight = (port) ?
 807                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 808                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
 809              pbf_reg_adress_crd_weight = (port) ?
 810                  PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
 811              break;
 812         case 2:
 813              nig_reg_adress_crd_weight = (port) ?
 814                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 815                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
 816
 817                  pbf_reg_adress_crd_weight = (port) ?
 818                      PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
 819              break;
 820         case 3:
 821             if (port)
 822                         return -EINVAL;
 823              nig_reg_adress_crd_weight =
 824                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
 825              pbf_reg_adress_crd_weight =
 826                  PBF_REG_COS3_WEIGHT_P0;
 827              break;
 828         case 4:
 829             if (port)
 830                 return -EINVAL;
 831              nig_reg_adress_crd_weight =
 832                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
 833              pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
 834              break;
 835         case 5:
 836             if (port)
 837                 return -EINVAL;
 838              nig_reg_adress_crd_weight =
 839                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
 840              pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
 841              break;
 842         }
 843
 844         REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
 845
 846         REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
 847
 848         return 0;
 849 }
 850 /******************************************************************************
 851 * Description:
 852 *       Calculate the total BW.A value of 0 isn't legal.
 853 *
 854 ******************************************************************************/
 855 static int bnx2x_ets_e3b0_get_total_bw(
 856         const struct link_params *params,
 857         struct bnx2x_ets_params *ets_params,
 858         u16 *total_bw)
 859 {
 860         struct bnx2x *bp = params->bp;
 861         u8 cos_idx = 0;
 862         u8 is_bw_cos_exist = 0;
 863
 864         *total_bw = 0 ;
 865         /* Calculate total BW requested */
 866         for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
 867                 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) {
 868                         is_bw_cos_exist = 1;
 869                         if (!ets_params->cos[cos_idx].params.bw_params.bw) {
 870                                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
 871                                                    "was set to 0\n");
 872                                 /* This is to prevent a state when ramrods
 873                                  * can't be sent
 874                                  */
 875                                 ets_params->cos[cos_idx].params.bw_params.bw
 876                                          = 1;
 877                         }
 878                         *total_bw +=
 879                                 ets_params->cos[cos_idx].params.bw_params.bw;
 880                 }
 881         }
 882
 883         /* Check total BW is valid */
 884         if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
 885                 if (*total_bw == 0) {
 886                         DP(NETIF_MSG_LINK,
 887                            "bnx2x_ets_E3B0_config total BW shouldn't be 0\n");
 888                         return -EINVAL;
 889                 }
 890                 DP(NETIF_MSG_LINK,
 891                    "bnx2x_ets_E3B0_config total BW should be 100\n");
 892                 /* We can handle a case whre the BW isn't 100 this can happen
 893                  * if the TC are joined.
 894                  */
 895         }
 896         return 0;
 897 }
 898
 899 /******************************************************************************
 900 * Description:
 901 *       Invalidate all the sp_pri_to_cos.
 902 *
 903 ******************************************************************************/
 904 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
 905 {
 906         u8 pri = 0;
 907         for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
 908                 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
 909 }
 910 /******************************************************************************
 911 * Description:
 912 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 913 *       according to sp_pri_to_cos.
 914 *
 915 ******************************************************************************/
 916 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
 917                                             u8 *sp_pri_to_cos, const u8 pri,
 918                                             const u8 cos_entry)
 919 {
 920         struct bnx2x *bp = params->bp;
 921         const u8 port = params->port;
 922         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
 923                 DCBX_E3B0_MAX_NUM_COS_PORT0;
 924
 925         if (pri >= max_num_of_cos) {
 926                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 927                    "parameter Illegal strict priority\n");
 928             return -EINVAL;
 929         }
 930
 931         if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
 932                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 933                                    "parameter There can't be two COS's with "
 934                                    "the same strict pri\n");
 935                 return -EINVAL;
 936         }
 937
 938         sp_pri_to_cos[pri] = cos_entry;
 939         return 0;
 940
 941 }
 942
 943 /******************************************************************************
 944 * Description:
 945 *       Returns the correct value according to COS and priority in
 946 *       the sp_pri_cli register.
 947 *
 948 ******************************************************************************/
 949 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
 950                                          const u8 pri_set,
 951                                          const u8 pri_offset,
 952                                          const u8 entry_size)
 953 {
 954         u64 pri_cli_nig = 0;
 955         pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
 956                                                     (pri_set + pri_offset));
 957
 958         return pri_cli_nig;
 959 }
 960 /******************************************************************************
 961 * Description:
 962 *       Returns the correct value according to COS and priority in the
 963 *       sp_pri_cli register for NIG.
 964 *
 965 ******************************************************************************/
 966 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
 967 {
 968         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
 969         const u8 nig_cos_offset = 3;
 970         const u8 nig_pri_offset = 3;
 971
 972         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
 973                 nig_pri_offset, 4);
 974
 975 }
 976 /******************************************************************************
 977 * Description:
 978 *       Returns the correct value according to COS and priority in the
 979 *       sp_pri_cli register for PBF.
 980 *
 981 ******************************************************************************/
 982 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
 983 {
 984         const u8 pbf_cos_offset = 0;
 985         const u8 pbf_pri_offset = 0;
 986
 987         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
 988                 pbf_pri_offset, 3);
 989
 990 }
 991
 992 /******************************************************************************
 993 * Description:
 994 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 995 *       according to sp_pri_to_cos.(which COS has higher priority)
 996 *
 997 ******************************************************************************/
 998 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
 999                                              u8 *sp_pri_to_cos)
1000 {
1001         struct bnx2x *bp = params->bp;
1002         u8 i = 0;
1003         const u8 port = params->port;
1004         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1005         u64 pri_cli_nig = 0x210;
1006         u32 pri_cli_pbf = 0x0;
1007         u8 pri_set = 0;
1008         u8 pri_bitmask = 0;
1009         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1010                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1011
1012         u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
1013
1014         /* Set all the strict priority first */
1015         for (i = 0; i < max_num_of_cos; i++) {
1016                 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1017                         if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) {
1018                                 DP(NETIF_MSG_LINK,
1019                                            "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1020                                            "invalid cos entry\n");
1021                                 return -EINVAL;
1022                         }
1023
1024                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1025                             sp_pri_to_cos[i], pri_set);
1026
1027                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1028                             sp_pri_to_cos[i], pri_set);
1029                         pri_bitmask = 1 << sp_pri_to_cos[i];
1030                         /* COS is used remove it from bitmap.*/
1031                         if (!(pri_bitmask & cos_bit_to_set)) {
1032                                 DP(NETIF_MSG_LINK,
1033                                         "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1034                                         "invalid There can't be two COS's with"
1035                                         " the same strict pri\n");
1036                                 return -EINVAL;
1037                         }
1038                         cos_bit_to_set &= ~pri_bitmask;
1039                         pri_set++;
1040                 }
1041         }
1042
1043         /* Set all the Non strict priority i= COS*/
1044         for (i = 0; i < max_num_of_cos; i++) {
1045                 pri_bitmask = 1 << i;
1046                 /* Check if COS was already used for SP */
1047                 if (pri_bitmask & cos_bit_to_set) {
1048                         /* COS wasn't used for SP */
1049                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1050                             i, pri_set);
1051
1052                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1053                             i, pri_set);
1054                         /* COS is used remove it from bitmap.*/
1055                         cos_bit_to_set &= ~pri_bitmask;
1056                         pri_set++;
1057                 }
1058         }
1059
1060         if (pri_set != max_num_of_cos) {
1061                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1062                                    "entries were set\n");
1063                 return -EINVAL;
1064         }
1065
1066         if (port) {
1067                 /* Only 6 usable clients*/
1068                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1069                        (u32)pri_cli_nig);
1070
1071                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1072         } else {
1073                 /* Only 9 usable clients*/
1074                 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1075                 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1076
1077                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1078                        pri_cli_nig_lsb);
1079                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1080                        pri_cli_nig_msb);
1081
1082                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1083         }
1084         return 0;
1085 }
1086
1087 /******************************************************************************
1088 * Description:
1089 *       Configure the COS to ETS according to BW and SP settings.
1090 ******************************************************************************/
1091 int bnx2x_ets_e3b0_config(const struct link_params *params,
1092                          const struct link_vars *vars,
1093                          struct bnx2x_ets_params *ets_params)
1094 {
1095         struct bnx2x *bp = params->bp;
1096         int bnx2x_status = 0;
1097         const u8 port = params->port;
1098         u16 total_bw = 0;
1099         const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1100         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1101         u8 cos_bw_bitmap = 0;
1102         u8 cos_sp_bitmap = 0;
1103         u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1104         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1105                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1106         u8 cos_entry = 0;
1107
1108         if (!CHIP_IS_E3B0(bp)) {
1109                 DP(NETIF_MSG_LINK,
1110                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
1111                 return -EINVAL;
1112         }
1113
1114         if ((ets_params->num_of_cos > max_num_of_cos)) {
1115                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1116                                    "isn't supported\n");
1117                 return -EINVAL;
1118         }
1119
1120         /* Prepare sp strict priority parameters*/
1121         bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1122
1123         /* Prepare BW parameters*/
1124         bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1125                                                    &total_bw);
1126         if (bnx2x_status) {
1127                 DP(NETIF_MSG_LINK,
1128                    "bnx2x_ets_E3B0_config get_total_bw failed\n");
1129                 return -EINVAL;
1130         }
1131
1132         /* Upper bound is set according to current link speed (min_w_val
1133          * should be the same for upper bound and COS credit val).
1134          */
1135         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1136         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1137
1138
1139         for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1140                 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1141                         cos_bw_bitmap |= (1 << cos_entry);
1142                         /* The function also sets the BW in HW(not the mappin
1143                          * yet)
1144                          */
1145                         bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1146                                 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1147                                 total_bw,
1148                                 ets_params->cos[cos_entry].params.bw_params.bw,
1149                                  port);
1150                 } else if (bnx2x_cos_state_strict ==
1151                         ets_params->cos[cos_entry].state){
1152                         cos_sp_bitmap |= (1 << cos_entry);
1153
1154                         bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1155                                 params,
1156                                 sp_pri_to_cos,
1157                                 ets_params->cos[cos_entry].params.sp_params.pri,
1158                                 cos_entry);
1159
1160                 } else {
1161                         DP(NETIF_MSG_LINK,
1162                            "bnx2x_ets_e3b0_config cos state not valid\n");
1163                         return -EINVAL;
1164                 }
1165                 if (bnx2x_status) {
1166                         DP(NETIF_MSG_LINK,
1167                            "bnx2x_ets_e3b0_config set cos bw failed\n");
1168                         return bnx2x_status;
1169                 }
1170         }
1171
1172         /* Set SP register (which COS has higher priority) */
1173         bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1174                                                          sp_pri_to_cos);
1175
1176         if (bnx2x_status) {
1177                 DP(NETIF_MSG_LINK,
1178                    "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
1179                 return bnx2x_status;
1180         }
1181
1182         /* Set client mapping of BW and strict */
1183         bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1184                                               cos_sp_bitmap,
1185                                               cos_bw_bitmap);
1186
1187         if (bnx2x_status) {
1188                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1189                 return bnx2x_status;
1190         }
1191         return 0;
1192 }
1193 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1194 {
1195         /* ETS disabled configuration */
1196         struct bnx2x *bp = params->bp;
1197         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1198         /* Defines which entries (clients) are subjected to WFQ arbitration
1199          * COS0 0x8
1200          * COS1 0x10
1201          */
1202         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1203         /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
1204          * client numbers (WEIGHT_0 does not actually have to represent
1205          * client 0)
1206          *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1207          *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
1208          */
1209         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1210
1211         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1212                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1213         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1214                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1215
1216         /* ETS mode enabled*/
1217         REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1218
1219         /* Defines the number of consecutive slots for the strict priority */
1220         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1221         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1222          * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
1223          * entry, 4 - COS1 entry.
1224          * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1225          * bit4   bit3    bit2     bit1    bit0
1226          * MCP and debug are strict
1227          */
1228         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1229
1230         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1231         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1232                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1233         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1234                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1235 }
1236
1237 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1238                         const u32 cos1_bw)
1239 {
1240         /* ETS disabled configuration*/
1241         struct bnx2x *bp = params->bp;
1242         const u32 total_bw = cos0_bw + cos1_bw;
1243         u32 cos0_credit_weight = 0;
1244         u32 cos1_credit_weight = 0;
1245
1246         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1247
1248         if ((!total_bw) ||
1249             (!cos0_bw) ||
1250             (!cos1_bw)) {
1251                 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1252                 return;
1253         }
1254
1255         cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1256                 total_bw;
1257         cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1258                 total_bw;
1259
1260         bnx2x_ets_bw_limit_common(params);
1261
1262         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1263         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1264
1265         REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1266         REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1267 }
1268
1269 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1270 {
1271         /* ETS disabled configuration*/
1272         struct bnx2x *bp = params->bp;
1273         u32 val = 0;
1274
1275         DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1276         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1277          * as strict.  Bits 0,1,2 - debug and management entries,
1278          * 3 - COS0 entry, 4 - COS1 entry.
1279          *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1280          *  bit4   bit3   bit2      bit1     bit0
1281          * MCP and debug are strict
1282          */
1283         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1284         /* For strict priority entries defines the number of consecutive slots
1285          * for the highest priority.
1286          */
1287         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1288         /* ETS mode disable */
1289         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1290         /* Defines the number of consecutive slots for the strict priority */
1291         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1292
1293         /* Defines the number of consecutive slots for the strict priority */
1294         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1295
1296         /* Mapping between entry  priority to client number (0,1,2 -debug and
1297          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1298          * 3bits client num.
1299          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1300          * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
1301          * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
1302          */
1303         val = (!strict_cos) ? 0x2318 : 0x22E0;
1304         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1305
1306         return 0;
1307 }
1308
1309 /******************************************************************/
1310 /*                      EEE section                                */
1311 /******************************************************************/
1312 static u8 bnx2x_eee_has_cap(struct link_params *params)
1313 {
1314         struct bnx2x *bp = params->bp;
1315
1316         if (REG_RD(bp, params->shmem2_base) <=
1317                    offsetof(struct shmem2_region, eee_status[params->port]))
1318                 return 0;
1319
1320         return 1;
1321 }
1322
1323 static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer)
1324 {
1325         switch (nvram_mode) {
1326         case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
1327                 *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME;
1328                 break;
1329         case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
1330                 *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME;
1331                 break;
1332         case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
1333                 *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME;
1334                 break;
1335         default:
1336                 *idle_timer = 0;
1337                 break;
1338         }
1339
1340         return 0;
1341 }
1342
1343 static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode)
1344 {
1345         switch (idle_timer) {
1346         case EEE_MODE_NVRAM_BALANCED_TIME:
1347                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
1348                 break;
1349         case EEE_MODE_NVRAM_AGGRESSIVE_TIME:
1350                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
1351                 break;
1352         case EEE_MODE_NVRAM_LATENCY_TIME:
1353                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
1354                 break;
1355         default:
1356                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
1357                 break;
1358         }
1359
1360         return 0;
1361 }
1362
1363 static u32 bnx2x_eee_calc_timer(struct link_params *params)
1364 {
1365         u32 eee_mode, eee_idle;
1366         struct bnx2x *bp = params->bp;
1367
1368         if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) {
1369                 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
1370                         /* time value in eee_mode --> used directly*/
1371                         eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK;
1372                 } else {
1373                         /* hsi value in eee_mode --> time */
1374                         if (bnx2x_eee_nvram_to_time(params->eee_mode &
1375                                                     EEE_MODE_NVRAM_MASK,
1376                                                     &eee_idle))
1377                                 return 0;
1378                 }
1379         } else {
1380                 /* hsi values in nvram --> time*/
1381                 eee_mode = ((REG_RD(bp, params->shmem_base +
1382                                     offsetof(struct shmem_region, dev_info.
1383                                     port_feature_config[params->port].
1384                                     eee_power_mode)) &
1385                              PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
1386                             PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
1387
1388                 if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle))
1389                         return 0;
1390         }
1391
1392         return eee_idle;
1393 }
1394
1395
1396 /******************************************************************/
1397 /*                      PFC section                               */
1398 /******************************************************************/
1399 static void bnx2x_update_pfc_xmac(struct link_params *params,
1400                                   struct link_vars *vars,
1401                                   u8 is_lb)
1402 {
1403         struct bnx2x *bp = params->bp;
1404         u32 xmac_base;
1405         u32 pause_val, pfc0_val, pfc1_val;
1406
1407         /* XMAC base adrr */
1408         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1409
1410         /* Initialize pause and pfc registers */
1411         pause_val = 0x18000;
1412         pfc0_val = 0xFFFF8000;
1413         pfc1_val = 0x2;
1414
1415         /* No PFC support */
1416         if (!(params->feature_config_flags &
1417               FEATURE_CONFIG_PFC_ENABLED)) {
1418
1419                 /* RX flow control - Process pause frame in receive direction
1420                  */
1421                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1422                         pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1423
1424                 /* TX flow control - Send pause packet when buffer is full */
1425                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1426                         pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1427         } else {/* PFC support */
1428                 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1429                         XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1430                         XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1431                         XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1432                         XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1433                 /* Write pause and PFC registers */
1434                 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1435                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1436                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1437                 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1438
1439         }
1440
1441         /* Write pause and PFC registers */
1442         REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1443         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1444         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1445
1446
1447         /* Set MAC address for source TX Pause/PFC frames */
1448         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1449                ((params->mac_addr[2] << 24) |
1450                 (params->mac_addr[3] << 16) |
1451                 (params->mac_addr[4] << 8) |
1452                 (params->mac_addr[5])));
1453         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1454                ((params->mac_addr[0] << 8) |
1455                 (params->mac_addr[1])));
1456
1457         udelay(30);
1458 }
1459
1460
1461 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
1462                                     u32 pfc_frames_sent[2],
1463                                     u32 pfc_frames_received[2])
1464 {
1465         /* Read pfc statistic */
1466         struct bnx2x *bp = params->bp;
1467         u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1468         u32 val_xon = 0;
1469         u32 val_xoff = 0;
1470
1471         DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
1472
1473         /* PFC received frames */
1474         val_xoff = REG_RD(bp, emac_base +
1475                                 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1476         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
1477         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1478         val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
1479
1480         pfc_frames_received[0] = val_xon + val_xoff;
1481
1482         /* PFC received sent */
1483         val_xoff = REG_RD(bp, emac_base +
1484                                 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1485         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
1486         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1487         val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
1488
1489         pfc_frames_sent[0] = val_xon + val_xoff;
1490 }
1491
1492 /* Read pfc statistic*/
1493 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1494                          u32 pfc_frames_sent[2],
1495                          u32 pfc_frames_received[2])
1496 {
1497         /* Read pfc statistic */
1498         struct bnx2x *bp = params->bp;
1499
1500         DP(NETIF_MSG_LINK, "pfc statistic\n");
1501
1502         if (!vars->link_up)
1503                 return;
1504
1505         if (vars->mac_type == MAC_TYPE_EMAC) {
1506                 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n");
1507                 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
1508                                         pfc_frames_received);
1509         }
1510 }
1511 /******************************************************************/
1512 /*                      MAC/PBF section                           */
1513 /******************************************************************/
1514 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port)
1515 {
1516         u32 mode, emac_base;
1517         /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1518          * (a value of 49==0x31) and make sure that the AUTO poll is off
1519          */
1520
1521         if (CHIP_IS_E2(bp))
1522                 emac_base = GRCBASE_EMAC0;
1523         else
1524                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1525         mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1526         mode &= ~(EMAC_MDIO_MODE_AUTO_POLL |
1527                   EMAC_MDIO_MODE_CLOCK_CNT);
1528         if (USES_WARPCORE(bp))
1529                 mode |= (74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1530         else
1531                 mode |= (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1532
1533         mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1534         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, mode);
1535
1536         udelay(40);
1537 }
1538 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1539 {
1540         u32 port4mode_ovwr_val;
1541         /* Check 4-port override enabled */
1542         port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1543         if (port4mode_ovwr_val & (1<<0)) {
1544                 /* Return 4-port mode override value */
1545                 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1546         }
1547         /* Return 4-port mode from input pin */
1548         return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1549 }
1550
1551 static void bnx2x_emac_init(struct link_params *params,
1552                             struct link_vars *vars)
1553 {
1554         /* reset and unreset the emac core */
1555         struct bnx2x *bp = params->bp;
1556         u8 port = params->port;
1557         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1558         u32 val;
1559         u16 timeout;
1560
1561         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1562                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1563         udelay(5);
1564         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1565                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1566
1567         /* init emac - use read-modify-write */
1568         /* self clear reset */
1569         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1570         EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1571
1572         timeout = 200;
1573         do {
1574                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1575                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1576                 if (!timeout) {
1577                         DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1578                         return;
1579                 }
1580                 timeout--;
1581         } while (val & EMAC_MODE_RESET);
1582         bnx2x_set_mdio_clk(bp, params->chip_id, port);
1583         /* Set mac address */
1584         val = ((params->mac_addr[0] << 8) |
1585                 params->mac_addr[1]);
1586         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1587
1588         val = ((params->mac_addr[2] << 24) |
1589                (params->mac_addr[3] << 16) |
1590                (params->mac_addr[4] << 8) |
1591                 params->mac_addr[5]);
1592         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1593 }
1594
1595 static void bnx2x_set_xumac_nig(struct link_params *params,
1596                                 u16 tx_pause_en,
1597                                 u8 enable)
1598 {
1599         struct bnx2x *bp = params->bp;
1600
1601         REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1602                enable);
1603         REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1604                enable);
1605         REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1606                NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1607 }
1608
1609 static void bnx2x_umac_disable(struct link_params *params)
1610 {
1611         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1612         struct bnx2x *bp = params->bp;
1613         if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &
1614                    (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1615                 return;
1616
1617         /* Disable RX and TX */
1618         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, 0);
1619 }
1620
1621 static void bnx2x_umac_enable(struct link_params *params,
1622                             struct link_vars *vars, u8 lb)
1623 {
1624         u32 val;
1625         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1626         struct bnx2x *bp = params->bp;
1627         /* Reset UMAC */
1628         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1629                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1630         usleep_range(1000, 1000);
1631
1632         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1633                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1634
1635         DP(NETIF_MSG_LINK, "enabling UMAC\n");
1636
1637         /* This register opens the gate for the UMAC despite its name */
1638         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1639
1640         val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1641                 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1642                 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1643                 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1644         switch (vars->line_speed) {
1645         case SPEED_10:
1646                 val |= (0<<2);
1647                 break;
1648         case SPEED_100:
1649                 val |= (1<<2);
1650                 break;
1651         case SPEED_1000:
1652                 val |= (2<<2);
1653                 break;
1654         case SPEED_2500:
1655                 val |= (3<<2);
1656                 break;
1657         default:
1658                 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1659                                vars->line_speed);
1660                 break;
1661         }
1662         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1663                 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1664
1665         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1666                 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1667
1668         if (vars->duplex == DUPLEX_HALF)
1669                 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
1670
1671         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1672         udelay(50);
1673
1674         /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1675         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1676                ((params->mac_addr[2] << 24) |
1677                 (params->mac_addr[3] << 16) |
1678                 (params->mac_addr[4] << 8) |
1679                 (params->mac_addr[5])));
1680         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1681                ((params->mac_addr[0] << 8) |
1682                 (params->mac_addr[1])));
1683
1684         /* Enable RX and TX */
1685         val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1686         val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1687                 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1688         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1689         udelay(50);
1690
1691         /* Remove SW Reset */
1692         val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1693
1694         /* Check loopback mode */
1695         if (lb)
1696                 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1697         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1698
1699         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1700          * length used by the MAC receive logic to check frames.
1701          */
1702         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1703         bnx2x_set_xumac_nig(params,
1704                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1705         vars->mac_type = MAC_TYPE_UMAC;
1706
1707 }
1708
1709 /* Define the XMAC mode */
1710 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1711 {
1712         struct bnx2x *bp = params->bp;
1713         u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1714
1715         /* In 4-port mode, need to set the mode only once, so if XMAC is
1716          * already out of reset, it means the mode has already been set,
1717          * and it must not* reset the XMAC again, since it controls both
1718          * ports of the path
1719          */
1720
1721         if ((CHIP_NUM(bp) == CHIP_NUM_57840) &&
1722             (REG_RD(bp, MISC_REG_RESET_REG_2) &
1723              MISC_REGISTERS_RESET_REG_2_XMAC)) {
1724                 DP(NETIF_MSG_LINK,
1725                    "XMAC already out of reset in 4-port mode\n");
1726                 return;
1727         }
1728
1729         /* Hard reset */
1730         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1731                MISC_REGISTERS_RESET_REG_2_XMAC);
1732         usleep_range(1000, 1000);
1733
1734         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1735                MISC_REGISTERS_RESET_REG_2_XMAC);
1736         if (is_port4mode) {
1737                 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1738
1739                 /* Set the number of ports on the system side to up to 2 */
1740                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1741
1742                 /* Set the number of ports on the Warp Core to 10G */
1743                 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1744         } else {
1745                 /* Set the number of ports on the system side to 1 */
1746                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1747                 if (max_speed == SPEED_10000) {
1748                         DP(NETIF_MSG_LINK,
1749                            "Init XMAC to 10G x 1 port per path\n");
1750                         /* Set the number of ports on the Warp Core to 10G */
1751                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1752                 } else {
1753                         DP(NETIF_MSG_LINK,
1754                            "Init XMAC to 20G x 2 ports per path\n");
1755                         /* Set the number of ports on the Warp Core to 20G */
1756                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1757                 }
1758         }
1759         /* Soft reset */
1760         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1761                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1762         usleep_range(1000, 1000);
1763
1764         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1765                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1766
1767 }
1768
1769 static void bnx2x_xmac_disable(struct link_params *params)
1770 {
1771         u8 port = params->port;
1772         struct bnx2x *bp = params->bp;
1773         u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1774
1775         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1776             MISC_REGISTERS_RESET_REG_2_XMAC) {
1777                 /* Send an indication to change the state in the NIG back to XON
1778                  * Clearing this bit enables the next set of this bit to get
1779                  * rising edge
1780                  */
1781                 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1782                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1783                        (pfc_ctrl & ~(1<<1)));
1784                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1785                        (pfc_ctrl | (1<<1)));
1786                 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1787                 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 0);
1788         }
1789 }
1790
1791 static int bnx2x_xmac_enable(struct link_params *params,
1792                              struct link_vars *vars, u8 lb)
1793 {
1794         u32 val, xmac_base;
1795         struct bnx2x *bp = params->bp;
1796         DP(NETIF_MSG_LINK, "enabling XMAC\n");
1797
1798         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1799
1800         bnx2x_xmac_init(params, vars->line_speed);
1801
1802         /* This register determines on which events the MAC will assert
1803          * error on the i/f to the NIG along w/ EOP.
1804          */
1805
1806         /* This register tells the NIG whether to send traffic to UMAC
1807          * or XMAC
1808          */
1809         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1810
1811         /* Set Max packet size */
1812         REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1813
1814         /* CRC append for Tx packets */
1815         REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1816
1817         /* update PFC */
1818         bnx2x_update_pfc_xmac(params, vars, 0);
1819
1820         if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1821                 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n");
1822                 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
1823                 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
1824         } else {
1825                 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
1826         }
1827
1828         /* Enable TX and RX */
1829         val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1830
1831         /* Check loopback mode */
1832         if (lb)
1833                 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1834         REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1835         bnx2x_set_xumac_nig(params,
1836                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1837
1838         vars->mac_type = MAC_TYPE_XMAC;
1839
1840         return 0;
1841 }
1842
1843 static int bnx2x_emac_enable(struct link_params *params,
1844                              struct link_vars *vars, u8 lb)
1845 {
1846         struct bnx2x *bp = params->bp;
1847         u8 port = params->port;
1848         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1849         u32 val;
1850
1851         DP(NETIF_MSG_LINK, "enabling EMAC\n");
1852
1853         /* Disable BMAC */
1854         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1855                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1856
1857         /* enable emac and not bmac */
1858         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1859
1860         /* ASIC */
1861         if (vars->phy_flags & PHY_XGXS_FLAG) {
1862                 u32 ser_lane = ((params->lane_config &
1863                                  PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1864                                 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1865
1866                 DP(NETIF_MSG_LINK, "XGXS\n");
1867                 /* select the master lanes (out of 0-3) */
1868                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1869                 /* select XGXS */
1870                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1871
1872         } else { /* SerDes */
1873                 DP(NETIF_MSG_LINK, "SerDes\n");
1874                 /* select SerDes */
1875                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1876         }
1877
1878         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1879                       EMAC_RX_MODE_RESET);
1880         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1881                       EMAC_TX_MODE_RESET);
1882
1883         if (CHIP_REV_IS_SLOW(bp)) {
1884                 /* config GMII mode */
1885                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1886                 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
1887         } else { /* ASIC */
1888                 /* pause enable/disable */
1889                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1890                                EMAC_RX_MODE_FLOW_EN);
1891
1892                 bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
1893                                (EMAC_TX_MODE_EXT_PAUSE_EN |
1894                                 EMAC_TX_MODE_FLOW_EN));
1895                 if (!(params->feature_config_flags &
1896                       FEATURE_CONFIG_PFC_ENABLED)) {
1897                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1898                                 bnx2x_bits_en(bp, emac_base +
1899                                               EMAC_REG_EMAC_RX_MODE,
1900                                               EMAC_RX_MODE_FLOW_EN);
1901
1902                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1903                                 bnx2x_bits_en(bp, emac_base +
1904                                               EMAC_REG_EMAC_TX_MODE,
1905                                               (EMAC_TX_MODE_EXT_PAUSE_EN |
1906                                                EMAC_TX_MODE_FLOW_EN));
1907                 } else
1908                         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1909                                       EMAC_TX_MODE_FLOW_EN);
1910         }
1911
1912         /* KEEP_VLAN_TAG, promiscuous */
1913         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1914         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1915
1916         /* Setting this bit causes MAC control frames (except for pause
1917          * frames) to be passed on for processing. This setting has no
1918          * affect on the operation of the pause frames. This bit effects
1919          * all packets regardless of RX Parser packet sorting logic.
1920          * Turn the PFC off to make sure we are in Xon state before
1921          * enabling it.
1922          */
1923         EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1924         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1925                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1926                 /* Enable PFC again */
1927                 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1928                         EMAC_REG_RX_PFC_MODE_RX_EN |
1929                         EMAC_REG_RX_PFC_MODE_TX_EN |
1930                         EMAC_REG_RX_PFC_MODE_PRIORITIES);
1931
1932                 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1933                         ((0x0101 <<
1934                           EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1935                          (0x00ff <<
1936                           EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1937                 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1938         }
1939         EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1940
1941         /* Set Loopback */
1942         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1943         if (lb)
1944                 val |= 0x810;
1945         else
1946                 val &= ~0x810;
1947         EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1948
1949         /* enable emac */
1950         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1951
1952         /* enable emac for jumbo packets */
1953         EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1954                 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1955                  (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1956
1957         /* strip CRC */
1958         REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1959
1960         /* disable the NIG in/out to the bmac */
1961         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1962         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1963         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1964
1965         /* enable the NIG in/out to the emac */
1966         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1967         val = 0;
1968         if ((params->feature_config_flags &
1969               FEATURE_CONFIG_PFC_ENABLED) ||
1970             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1971                 val = 1;
1972
1973         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1974         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1975
1976         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1977
1978         vars->mac_type = MAC_TYPE_EMAC;
1979         return 0;
1980 }
1981
1982 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1983                                    struct link_vars *vars)
1984 {
1985         u32 wb_data[2];
1986         struct bnx2x *bp = params->bp;
1987         u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1988                 NIG_REG_INGRESS_BMAC0_MEM;
1989
1990         u32 val = 0x14;
1991         if ((!(params->feature_config_flags &
1992               FEATURE_CONFIG_PFC_ENABLED)) &&
1993                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1994                 /* Enable BigMAC to react on received Pause packets */
1995                 val |= (1<<5);
1996         wb_data[0] = val;
1997         wb_data[1] = 0;
1998         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1999
2000         /* tx control */
2001         val = 0xc0;
2002         if (!(params->feature_config_flags &
2003               FEATURE_CONFIG_PFC_ENABLED) &&
2004                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2005                 val |= 0x800000;
2006         wb_data[0] = val;
2007         wb_data[1] = 0;
2008         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
2009 }
2010
2011 static void bnx2x_update_pfc_bmac2(struct link_params *params,
2012                                    struct link_vars *vars,
2013                                    u8 is_lb)
2014 {
2015         /* Set rx control: Strip CRC and enable BigMAC to relay
2016          * control packets to the system as well
2017          */
2018         u32 wb_data[2];
2019         struct bnx2x *bp = params->bp;
2020         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
2021                 NIG_REG_INGRESS_BMAC0_MEM;
2022         u32 val = 0x14;
2023
2024         if ((!(params->feature_config_flags &
2025               FEATURE_CONFIG_PFC_ENABLED)) &&
2026                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
2027                 /* Enable BigMAC to react on received Pause packets */
2028                 val |= (1<<5);
2029         wb_data[0] = val;
2030         wb_data[1] = 0;
2031         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
2032         udelay(30);
2033
2034         /* Tx control */
2035         val = 0xc0;
2036         if (!(params->feature_config_flags &
2037                                 FEATURE_CONFIG_PFC_ENABLED) &&
2038             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2039                 val |= 0x800000;
2040         wb_data[0] = val;
2041         wb_data[1] = 0;
2042         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
2043
2044         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
2045                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
2046                 /* Enable PFC RX & TX & STATS and set 8 COS  */
2047                 wb_data[0] = 0x0;
2048                 wb_data[0] |= (1<<0);  /* RX */
2049                 wb_data[0] |= (1<<1);  /* TX */
2050                 wb_data[0] |= (1<<2);  /* Force initial Xon */
2051                 wb_data[0] |= (1<<3);  /* 8 cos */
2052                 wb_data[0] |= (1<<5);  /* STATS */
2053                 wb_data[1] = 0;
2054                 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
2055                             wb_data, 2);
2056                 /* Clear the force Xon */
2057                 wb_data[0] &= ~(1<<2);
2058         } else {
2059                 DP(NETIF_MSG_LINK, "PFC is disabled\n");
2060                 /* disable PFC RX & TX & STATS and set 8 COS */
2061                 wb_data[0] = 0x8;
2062                 wb_data[1] = 0;
2063         }
2064
2065         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2066
2067         /* Set Time (based unit is 512 bit time) between automatic
2068          * re-sending of PP packets amd enable automatic re-send of
2069          * Per-Priroity Packet as long as pp_gen is asserted and
2070          * pp_disable is low.
2071          */
2072         val = 0x8000;
2073         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2074                 val |= (1<<16); /* enable automatic re-send */
2075
2076         wb_data[0] = val;
2077         wb_data[1] = 0;
2078         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
2079                     wb_data, 2);
2080
2081         /* mac control */
2082         val = 0x3; /* Enable RX and TX */
2083         if (is_lb) {
2084                 val |= 0x4; /* Local loopback */
2085                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2086         }
2087         /* When PFC enabled, Pass pause frames towards the NIG. */
2088         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2089                 val |= ((1<<6)|(1<<5));
2090
2091         wb_data[0] = val;
2092         wb_data[1] = 0;
2093         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2094 }
2095
2096 /* PFC BRB internal port configuration params */
2097 struct bnx2x_pfc_brb_threshold_val {
2098         u32 pause_xoff;
2099         u32 pause_xon;
2100         u32 full_xoff;
2101         u32 full_xon;
2102 };
2103
2104 struct bnx2x_pfc_brb_e3b0_val {
2105         u32 per_class_guaranty_mode;
2106         u32 lb_guarantied_hyst;
2107         u32 full_lb_xoff_th;
2108         u32 full_lb_xon_threshold;
2109         u32 lb_guarantied;
2110         u32 mac_0_class_t_guarantied;
2111         u32 mac_0_class_t_guarantied_hyst;
2112         u32 mac_1_class_t_guarantied;
2113         u32 mac_1_class_t_guarantied_hyst;
2114 };
2115
2116 struct bnx2x_pfc_brb_th_val {
2117         struct bnx2x_pfc_brb_threshold_val pauseable_th;
2118         struct bnx2x_pfc_brb_threshold_val non_pauseable_th;
2119         struct bnx2x_pfc_brb_threshold_val default_class0;
2120         struct bnx2x_pfc_brb_threshold_val default_class1;
2121
2122 };
2123 static int bnx2x_pfc_brb_get_config_params(
2124                                 struct link_params *params,
2125                                 struct bnx2x_pfc_brb_th_val *config_val)
2126 {
2127         struct bnx2x *bp = params->bp;
2128         DP(NETIF_MSG_LINK, "Setting PFC BRB configuration\n");
2129
2130         config_val->default_class1.pause_xoff = 0;
2131         config_val->default_class1.pause_xon = 0;
2132         config_val->default_class1.full_xoff = 0;
2133         config_val->default_class1.full_xon = 0;
2134
2135         if (CHIP_IS_E2(bp)) {
2136                 /* Class0 defaults */
2137                 config_val->default_class0.pause_xoff =
2138                         DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR;
2139                 config_val->default_class0.pause_xon =
2140                         DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR;
2141                 config_val->default_class0.full_xoff =
2142                         DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR;
2143                 config_val->default_class0.full_xon =
2144                         DEFAULT0_E2_BRB_MAC_FULL_XON_THR;
2145                 /* Pause able*/
2146                 config_val->pauseable_th.pause_xoff =
2147                         PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2148                 config_val->pauseable_th.pause_xon =
2149                         PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE;
2150                 config_val->pauseable_th.full_xoff =
2151                         PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
2152                 config_val->pauseable_th.full_xon =
2153                         PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
2154                 /* non pause able*/
2155                 config_val->non_pauseable_th.pause_xoff =
2156                         PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2157                 config_val->non_pauseable_th.pause_xon =
2158                         PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2159                 config_val->non_pauseable_th.full_xoff =
2160                         PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2161                 config_val->non_pauseable_th.full_xon =
2162                         PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2163         } else if (CHIP_IS_E3A0(bp)) {
2164                 /* Class0 defaults */
2165                 config_val->default_class0.pause_xoff =
2166                         DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR;
2167                 config_val->default_class0.pause_xon =
2168                         DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR;
2169                 config_val->default_class0.full_xoff =
2170                         DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR;
2171                 config_val->default_class0.full_xon =
2172                         DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR;
2173                 /* Pause able */
2174                 config_val->pauseable_th.pause_xoff =
2175                         PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2176                 config_val->pauseable_th.pause_xon =
2177                         PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE;
2178                 config_val->pauseable_th.full_xoff =
2179                         PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
2180                 config_val->pauseable_th.full_xon =
2181                         PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
2182                 /* non pause able*/
2183                 config_val->non_pauseable_th.pause_xoff =
2184                         PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2185                 config_val->non_pauseable_th.pause_xon =
2186                         PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2187                 config_val->non_pauseable_th.full_xoff =
2188                         PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2189                 config_val->non_pauseable_th.full_xon =
2190                         PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2191         } else if (CHIP_IS_E3B0(bp)) {
2192                 /* Class0 defaults */
2193                 config_val->default_class0.pause_xoff =
2194                         DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR;
2195                 config_val->default_class0.pause_xon =
2196                     DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR;
2197                 config_val->default_class0.full_xoff =
2198                     DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR;
2199                 config_val->default_class0.full_xon =
2200                     DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR;
2201
2202                 if (params->phy[INT_PHY].flags &
2203                     FLAGS_4_PORT_MODE) {
2204                         config_val->pauseable_th.pause_xoff =
2205                                 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2206                         config_val->pauseable_th.pause_xon =
2207                                 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2208                         config_val->pauseable_th.full_xoff =
2209                                 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2210                         config_val->pauseable_th.full_xon =
2211                                 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
2212                         /* non pause able*/
2213                         config_val->non_pauseable_th.pause_xoff =
2214                         PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2215                         config_val->non_pauseable_th.pause_xon =
2216                         PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2217                         config_val->non_pauseable_th.full_xoff =
2218                         PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2219                         config_val->non_pauseable_th.full_xon =
2220                         PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2221                 } else {
2222                         config_val->pauseable_th.pause_xoff =
2223                                 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2224                         config_val->pauseable_th.pause_xon =
2225                                 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2226                         config_val->pauseable_th.full_xoff =
2227                                 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2228                         config_val->pauseable_th.full_xon =
2229                                 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
2230                         /* non pause able*/
2231                         config_val->non_pauseable_th.pause_xoff =
2232                                 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2233                         config_val->non_pauseable_th.pause_xon =
2234                                 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2235                         config_val->non_pauseable_th.full_xoff =
2236                                 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2237                         config_val->non_pauseable_th.full_xon =
2238                                 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2239                 }
2240         } else
2241             return -EINVAL;
2242
2243         return 0;
2244 }
2245
2246 static void bnx2x_pfc_brb_get_e3b0_config_params(
2247                 struct link_params *params,
2248                 struct bnx2x_pfc_brb_e3b0_val
2249                 *e3b0_val,
2250                 struct bnx2x_nig_brb_pfc_port_params *pfc_params,
2251                 const u8 pfc_enabled)
2252 {
2253         if (pfc_enabled && pfc_params) {
2254                 e3b0_val->per_class_guaranty_mode = 1;
2255                 e3b0_val->lb_guarantied_hyst = 80;
2256
2257                 if (params->phy[INT_PHY].flags &
2258                     FLAGS_4_PORT_MODE) {
2259                         e3b0_val->full_lb_xoff_th =
2260                                 PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR;
2261                         e3b0_val->full_lb_xon_threshold =
2262                                 PFC_E3B0_4P_BRB_FULL_LB_XON_THR;
2263                         e3b0_val->lb_guarantied =
2264                                 PFC_E3B0_4P_LB_GUART;
2265                         e3b0_val->mac_0_class_t_guarantied =
2266                                 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART;
2267                         e3b0_val->mac_0_class_t_guarantied_hyst =
2268                                 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST;
2269                         e3b0_val->mac_1_class_t_guarantied =
2270                                 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART;
2271                         e3b0_val->mac_1_class_t_guarantied_hyst =
2272                                 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST;
2273                 } else {
2274                         e3b0_val->full_lb_xoff_th =
2275                                 PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR;
2276                         e3b0_val->full_lb_xon_threshold =
2277                                 PFC_E3B0_2P_BRB_FULL_LB_XON_THR;
2278                         e3b0_val->mac_0_class_t_guarantied_hyst =
2279                                 PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST;
2280                         e3b0_val->mac_1_class_t_guarantied =
2281                                 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART;
2282                         e3b0_val->mac_1_class_t_guarantied_hyst =
2283                                 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST;
2284
2285                         if (pfc_params->cos0_pauseable !=
2286                                 pfc_params->cos1_pauseable) {
2287                                 /* nonpauseable= Lossy + pauseable = Lossless*/
2288                                 e3b0_val->lb_guarantied =
2289                                         PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
2290                                 e3b0_val->mac_0_class_t_guarantied =
2291                                PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART;
2292                         } else if (pfc_params->cos0_pauseable) {
2293                                 /* Lossless +Lossless*/
2294                                 e3b0_val->lb_guarantied =
2295                                         PFC_E3B0_2P_PAUSE_LB_GUART;
2296                                 e3b0_val->mac_0_class_t_guarantied =
2297                                    PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART;
2298                         } else {
2299                                 /* Lossy +Lossy*/
2300                                 e3b0_val->lb_guarantied =
2301                                         PFC_E3B0_2P_NON_PAUSE_LB_GUART;
2302                                 e3b0_val->mac_0_class_t_guarantied =
2303                                PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART;
2304                         }
2305                 }
2306         } else {
2307                 e3b0_val->per_class_guaranty_mode = 0;
2308                 e3b0_val->lb_guarantied_hyst = 0;
2309                 e3b0_val->full_lb_xoff_th =
2310                         DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR;
2311                 e3b0_val->full_lb_xon_threshold =
2312                         DEFAULT_E3B0_BRB_FULL_LB_XON_THR;
2313                 e3b0_val->lb_guarantied =
2314                         DEFAULT_E3B0_LB_GUART;
2315                 e3b0_val->mac_0_class_t_guarantied =
2316                         DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART;
2317                 e3b0_val->mac_0_class_t_guarantied_hyst =
2318                         DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST;
2319                 e3b0_val->mac_1_class_t_guarantied =
2320                         DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART;
2321                 e3b0_val->mac_1_class_t_guarantied_hyst =
2322                         DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST;
2323         }
2324 }
2325 static int bnx2x_update_pfc_brb(struct link_params *params,
2326                                 struct link_vars *vars,
2327                                 struct bnx2x_nig_brb_pfc_port_params
2328                                 *pfc_params)
2329 {
2330         struct bnx2x *bp = params->bp;
2331         struct bnx2x_pfc_brb_th_val config_val = { {0} };
2332         struct bnx2x_pfc_brb_threshold_val *reg_th_config =
2333                 &config_val.pauseable_th;
2334         struct bnx2x_pfc_brb_e3b0_val e3b0_val = {0};
2335         const int set_pfc = params->feature_config_flags &
2336                 FEATURE_CONFIG_PFC_ENABLED;
2337         const u8 pfc_enabled = (set_pfc && pfc_params);
2338         int bnx2x_status = 0;
2339         u8 port = params->port;
2340
2341         /* default - pause configuration */
2342         reg_th_config = &config_val.pauseable_th;
2343         bnx2x_status = bnx2x_pfc_brb_get_config_params(params, &config_val);
2344         if (bnx2x_status)
2345                 return bnx2x_status;
2346
2347         if (pfc_enabled) {
2348                 /* First COS */
2349                 if (pfc_params->cos0_pauseable)
2350                         reg_th_config = &config_val.pauseable_th;
2351                 else
2352                         reg_th_config = &config_val.non_pauseable_th;
2353         } else
2354                 reg_th_config = &config_val.default_class0;
2355         /* The number of free blocks below which the pause signal to class 0
2356          * of MAC #n is asserted. n=0,1
2357          */
2358         REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 :
2359                BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
2360                reg_th_config->pause_xoff);
2361         /* The number of free blocks above which the pause signal to class 0
2362          * of MAC #n is de-asserted. n=0,1
2363          */
2364         REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 :
2365                BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon);
2366         /* The number of free blocks below which the full signal to class 0
2367          * of MAC #n is asserted. n=0,1
2368          */
2369         REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 :
2370                BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff);
2371         /* The number of free blocks above which the full signal to class 0
2372          * of MAC #n is de-asserted. n=0,1
2373          */
2374         REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 :
2375                BRB1_REG_FULL_0_XON_THRESHOLD_0 , reg_th_config->full_xon);
2376
2377         if (pfc_enabled) {
2378                 /* Second COS */
2379                 if (pfc_params->cos1_pauseable)
2380                         reg_th_config = &config_val.pauseable_th;
2381                 else
2382                         reg_th_config = &config_val.non_pauseable_th;
2383         } else
2384                 reg_th_config = &config_val.default_class1;
2385         /* The number of free blocks below which the pause signal to
2386          * class 1 of MAC #n is asserted. n=0,1
2387          */
2388         REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 :
2389                BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
2390                reg_th_config->pause_xoff);
2391
2392         /* The number of free blocks above which the pause signal to
2393          * class 1 of MAC #n is de-asserted. n=0,1
2394          */
2395         REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 :
2396                BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
2397                reg_th_config->pause_xon);
2398         /* The number of free blocks below which the full signal to
2399          * class 1 of MAC #n is asserted. n=0,1
2400          */
2401         REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 :
2402                BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
2403                reg_th_config->full_xoff);
2404         /* The number of free blocks above which the full signal to
2405          * class 1 of MAC #n is de-asserted. n=0,1
2406          */
2407         REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 :
2408                BRB1_REG_FULL_1_XON_THRESHOLD_0,
2409                reg_th_config->full_xon);
2410
2411         if (CHIP_IS_E3B0(bp)) {
2412                 bnx2x_pfc_brb_get_e3b0_config_params(
2413                         params,
2414                         &e3b0_val,
2415                         pfc_params,
2416                         pfc_enabled);
2417
2418                 REG_WR(bp, BRB1_REG_PER_CLASS_GUARANTY_MODE,
2419                            e3b0_val.per_class_guaranty_mode);
2420
2421                 /* The hysteresis on the guarantied buffer space for the Lb
2422                  * port before signaling XON.
2423                  */
2424                 REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST,
2425                            e3b0_val.lb_guarantied_hyst);
2426
2427                 /* The number of free blocks below which the full signal to the
2428                  * LB port is asserted.
2429                  */
2430                 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD,
2431                        e3b0_val.full_lb_xoff_th);
2432                 /* The number of free blocks above which the full signal to the
2433                  * LB port is de-asserted.
2434                  */
2435                 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD,
2436                        e3b0_val.full_lb_xon_threshold);
2437                 /* The number of blocks guarantied for the MAC #n port. n=0,1
2438                  */
2439
2440                 /* The number of blocks guarantied for the LB port. */
2441                 REG_WR(bp, BRB1_REG_LB_GUARANTIED,
2442                        e3b0_val.lb_guarantied);
2443
2444                 /* The number of blocks guarantied for the MAC #n port. */
2445                 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0,
2446                        2 * e3b0_val.mac_0_class_t_guarantied);
2447                 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1,
2448                        2 * e3b0_val.mac_1_class_t_guarantied);
2449                 /* The number of blocks guarantied for class #t in MAC0. t=0,1
2450                  */
2451                 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED,
2452                        e3b0_val.mac_0_class_t_guarantied);
2453                 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED,
2454                        e3b0_val.mac_0_class_t_guarantied);
2455                 /* The hysteresis on the guarantied buffer space for class in
2456                  * MAC0.  t=0,1
2457                  */
2458                 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST,
2459                        e3b0_val.mac_0_class_t_guarantied_hyst);
2460                 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST,
2461                        e3b0_val.mac_0_class_t_guarantied_hyst);
2462
2463                 /* The number of blocks guarantied for class #t in MAC1.t=0,1
2464                  */
2465                 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED,
2466                        e3b0_val.mac_1_class_t_guarantied);
2467                 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED,
2468                        e3b0_val.mac_1_class_t_guarantied);
2469                 /* The hysteresis on the guarantied buffer space for class #t
2470                  * in MAC1.  t=0,1
2471                  */
2472                 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST,
2473                        e3b0_val.mac_1_class_t_guarantied_hyst);
2474                 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST,
2475                        e3b0_val.mac_1_class_t_guarantied_hyst);
2476         }
2477
2478         return bnx2x_status;
2479 }
2480
2481 /******************************************************************************
2482 * Description:
2483 *  This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2484 *  not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2485 ******************************************************************************/
2486 int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2487                                               u8 cos_entry,
2488                                               u32 priority_mask, u8 port)
2489 {
2490         u32 nig_reg_rx_priority_mask_add = 0;
2491
2492         switch (cos_entry) {
2493         case 0:
2494              nig_reg_rx_priority_mask_add = (port) ?
2495                  NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2496                  NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2497              break;
2498         case 1:
2499             nig_reg_rx_priority_mask_add = (port) ?
2500                 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2501                 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2502             break;
2503         case 2:
2504             nig_reg_rx_priority_mask_add = (port) ?
2505                 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2506                 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2507             break;
2508         case 3:
2509             if (port)
2510                 return -EINVAL;
2511             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2512             break;
2513         case 4:
2514             if (port)
2515                 return -EINVAL;
2516             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2517             break;
2518         case 5:
2519             if (port)
2520                 return -EINVAL;
2521             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2522             break;
2523         }
2524
2525         REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2526
2527         return 0;
2528 }
2529 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2530 {
2531         struct bnx2x *bp = params->bp;
2532
2533         REG_WR(bp, params->shmem_base +
2534                offsetof(struct shmem_region,
2535                         port_mb[params->port].link_status), link_status);
2536 }
2537
2538 static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status)
2539 {
2540         struct bnx2x *bp = params->bp;
2541
2542         if (bnx2x_eee_has_cap(params))
2543                 REG_WR(bp, params->shmem2_base +
2544                        offsetof(struct shmem2_region,
2545                                 eee_status[params->port]), eee_status);
2546 }
2547
2548 static void bnx2x_update_pfc_nig(struct link_params *params,
2549                 struct link_vars *vars,
2550                 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2551 {
2552         u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2553         u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
2554         u32 pkt_priority_to_cos = 0;
2555         struct bnx2x *bp = params->bp;
2556         u8 port = params->port;
2557
2558         int set_pfc = params->feature_config_flags &
2559                 FEATURE_CONFIG_PFC_ENABLED;
2560         DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2561
2562         /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2563          * MAC control frames (that are not pause packets)
2564          * will be forwarded to the XCM.
2565          */
2566         xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :
2567                           NIG_REG_LLH0_XCM_MASK);
2568         /* NIG params will override non PFC params, since it's possible to
2569          * do transition from PFC to SAFC
2570          */
2571         if (set_pfc) {
2572                 pause_enable = 0;
2573                 llfc_out_en = 0;
2574                 llfc_enable = 0;
2575                 if (CHIP_IS_E3(bp))
2576                         ppp_enable = 0;
2577                 else
2578                 ppp_enable = 1;
2579                 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2580                                      NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2581                 xcm_out_en = 0;
2582                 hwpfc_enable = 1;
2583         } else  {
2584                 if (nig_params) {
2585                         llfc_out_en = nig_params->llfc_out_en;
2586                         llfc_enable = nig_params->llfc_enable;
2587                         pause_enable = nig_params->pause_enable;
2588                 } else  /* Default non PFC mode - PAUSE */
2589                         pause_enable = 1;
2590
2591                 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2592                         NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2593                 xcm_out_en = 1;
2594         }
2595
2596         if (CHIP_IS_E3(bp))
2597                 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2598                        NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2599         REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2600                NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2601         REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2602                NIG_REG_LLFC_ENABLE_0, llfc_enable);
2603         REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2604                NIG_REG_PAUSE_ENABLE_0, pause_enable);
2605
2606         REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2607                NIG_REG_PPP_ENABLE_0, ppp_enable);
2608
2609         REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2610                NIG_REG_LLH0_XCM_MASK, xcm_mask);
2611
2612         REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2613                NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2614
2615         /* output enable for RX_XCM # IF */
2616         REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN :
2617                NIG_REG_XCM0_OUT_EN, xcm_out_en);
2618
2619         /* HW PFC TX enable */
2620         REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE :
2621                NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
2622
2623         if (nig_params) {
2624                 u8 i = 0;
2625                 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2626
2627                 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2628                         bnx2x_pfc_nig_rx_priority_mask(bp, i,
2629                 nig_params->rx_cos_priority_mask[i], port);
2630
2631                 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2632                        NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2633                        nig_params->llfc_high_priority_classes);
2634
2635                 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2636                        NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2637                        nig_params->llfc_low_priority_classes);
2638         }
2639         REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2640                NIG_REG_P0_PKT_PRIORITY_TO_COS,
2641                pkt_priority_to_cos);
2642 }
2643
2644 int bnx2x_update_pfc(struct link_params *params,
2645                       struct link_vars *vars,
2646                       struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2647 {
2648         /* The PFC and pause are orthogonal to one another, meaning when
2649          * PFC is enabled, the pause are disabled, and when PFC is
2650          * disabled, pause are set according to the pause result.
2651          */
2652         u32 val;
2653         struct bnx2x *bp = params->bp;
2654         int bnx2x_status = 0;
2655         u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2656
2657         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2658                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2659         else
2660                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2661
2662         bnx2x_update_mng(params, vars->link_status);
2663
2664         /* update NIG params */
2665         bnx2x_update_pfc_nig(params, vars, pfc_params);
2666
2667         /* update BRB params */
2668         bnx2x_status = bnx2x_update_pfc_brb(params, vars, pfc_params);
2669         if (bnx2x_status)
2670                 return bnx2x_status;
2671
2672         if (!vars->link_up)
2673                 return bnx2x_status;
2674
2675         DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2676         if (CHIP_IS_E3(bp))
2677                 bnx2x_update_pfc_xmac(params, vars, 0);
2678         else {
2679                 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2680                 if ((val &
2681                      (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2682                     == 0) {
2683                         DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2684                         bnx2x_emac_enable(params, vars, 0);
2685                         return bnx2x_status;
2686                 }
2687                 if (CHIP_IS_E2(bp))
2688                         bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2689                 else
2690                         bnx2x_update_pfc_bmac1(params, vars);
2691
2692                 val = 0;
2693                 if ((params->feature_config_flags &
2694                      FEATURE_CONFIG_PFC_ENABLED) ||
2695                     (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2696                         val = 1;
2697                 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2698         }
2699         return bnx2x_status;
2700 }
2701
2702
2703 static int bnx2x_bmac1_enable(struct link_params *params,
2704                               struct link_vars *vars,
2705                               u8 is_lb)
2706 {
2707         struct bnx2x *bp = params->bp;
2708         u8 port = params->port;
2709         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2710                                NIG_REG_INGRESS_BMAC0_MEM;
2711         u32 wb_data[2];
2712         u32 val;
2713
2714         DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2715
2716         /* XGXS control */
2717         wb_data[0] = 0x3c;
2718         wb_data[1] = 0;
2719         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2720                     wb_data, 2);
2721
2722         /* tx MAC SA */
2723         wb_data[0] = ((params->mac_addr[2] << 24) |
2724                        (params->mac_addr[3] << 16) |
2725                        (params->mac_addr[4] << 8) |
2726                         params->mac_addr[5]);
2727         wb_data[1] = ((params->mac_addr[0] << 8) |
2728                         params->mac_addr[1]);
2729         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2730
2731         /* mac control */
2732         val = 0x3;
2733         if (is_lb) {
2734                 val |= 0x4;
2735                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2736         }
2737         wb_data[0] = val;
2738         wb_data[1] = 0;
2739         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2740
2741         /* set rx mtu */
2742         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2743         wb_data[1] = 0;
2744         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2745
2746         bnx2x_update_pfc_bmac1(params, vars);
2747
2748         /* set tx mtu */
2749         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2750         wb_data[1] = 0;
2751         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2752
2753         /* set cnt max size */
2754         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2755         wb_data[1] = 0;
2756         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2757
2758         /* configure safc */
2759         wb_data[0] = 0x1000200;
2760         wb_data[1] = 0;
2761         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2762                     wb_data, 2);
2763
2764         return 0;
2765 }
2766
2767 static int bnx2x_bmac2_enable(struct link_params *params,
2768                               struct link_vars *vars,
2769                               u8 is_lb)
2770 {
2771         struct bnx2x *bp = params->bp;
2772         u8 port = params->port;
2773         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2774                                NIG_REG_INGRESS_BMAC0_MEM;
2775         u32 wb_data[2];
2776
2777         DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2778
2779         wb_data[0] = 0;
2780         wb_data[1] = 0;
2781         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2782         udelay(30);
2783
2784         /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2785         wb_data[0] = 0x3c;
2786         wb_data[1] = 0;
2787         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2788                     wb_data, 2);
2789
2790         udelay(30);
2791
2792         /* tx MAC SA */
2793         wb_data[0] = ((params->mac_addr[2] << 24) |
2794                        (params->mac_addr[3] << 16) |
2795                        (params->mac_addr[4] << 8) |
2796                         params->mac_addr[5]);
2797         wb_data[1] = ((params->mac_addr[0] << 8) |
2798                         params->mac_addr[1]);
2799         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2800                     wb_data, 2);
2801
2802         udelay(30);
2803
2804         /* Configure SAFC */
2805         wb_data[0] = 0x1000200;
2806         wb_data[1] = 0;
2807         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2808                     wb_data, 2);
2809         udelay(30);
2810
2811         /* set rx mtu */
2812         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2813         wb_data[1] = 0;
2814         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2815         udelay(30);
2816
2817         /* set tx mtu */
2818         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2819         wb_data[1] = 0;
2820         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2821         udelay(30);
2822         /* set cnt max size */
2823         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2824         wb_data[1] = 0;
2825         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2826         udelay(30);
2827         bnx2x_update_pfc_bmac2(params, vars, is_lb);
2828
2829         return 0;
2830 }
2831
2832 static int bnx2x_bmac_enable(struct link_params *params,
2833                              struct link_vars *vars,
2834                              u8 is_lb)
2835 {
2836         int rc = 0;
2837         u8 port = params->port;
2838         struct bnx2x *bp = params->bp;
2839         u32 val;
2840         /* reset and unreset the BigMac */
2841         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2842                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2843         msleep(1);
2844
2845         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2846                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2847
2848         /* enable access for bmac registers */
2849         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2850
2851         /* Enable BMAC according to BMAC type*/
2852         if (CHIP_IS_E2(bp))
2853                 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2854         else
2855                 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2856         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2857         REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2858         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2859         val = 0;
2860         if ((params->feature_config_flags &
2861               FEATURE_CONFIG_PFC_ENABLED) ||
2862             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2863                 val = 1;
2864         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2865         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2866         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2867         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2868         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2869         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2870
2871         vars->mac_type = MAC_TYPE_BMAC;
2872         return rc;
2873 }
2874
2875 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
2876 {
2877         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2878                         NIG_REG_INGRESS_BMAC0_MEM;
2879         u32 wb_data[2];
2880         u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2881
2882         /* Only if the bmac is out of reset */
2883         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2884                         (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2885             nig_bmac_enable) {
2886
2887                 if (CHIP_IS_E2(bp)) {
2888                         /* Clear Rx Enable bit in BMAC_CONTROL register */
2889                         REG_RD_DMAE(bp, bmac_addr +
2890                                     BIGMAC2_REGISTER_BMAC_CONTROL,
2891                                     wb_data, 2);
2892                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2893                         REG_WR_DMAE(bp, bmac_addr +
2894                                     BIGMAC2_REGISTER_BMAC_CONTROL,
2895                                     wb_data, 2);
2896                 } else {
2897                         /* Clear Rx Enable bit in BMAC_CONTROL register */
2898                         REG_RD_DMAE(bp, bmac_addr +
2899                                         BIGMAC_REGISTER_BMAC_CONTROL,
2900                                         wb_data, 2);
2901                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2902                         REG_WR_DMAE(bp, bmac_addr +
2903                                         BIGMAC_REGISTER_BMAC_CONTROL,
2904                                         wb_data, 2);
2905                 }
2906                 msleep(1);
2907         }
2908 }
2909
2910 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2911                             u32 line_speed)
2912 {
2913         struct bnx2x *bp = params->bp;
2914         u8 port = params->port;
2915         u32 init_crd, crd;
2916         u32 count = 1000;
2917
2918         /* disable port */
2919         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2920
2921         /* wait for init credit */
2922         init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2923         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2924         DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
2925
2926         while ((init_crd != crd) && count) {
2927                 msleep(5);
2928
2929                 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2930                 count--;
2931         }
2932         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2933         if (init_crd != crd) {
2934                 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2935                           init_crd, crd);
2936                 return -EINVAL;
2937         }
2938
2939         if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2940             line_speed == SPEED_10 ||
2941             line_speed == SPEED_100 ||
2942             line_speed == SPEED_1000 ||
2943             line_speed == SPEED_2500) {
2944                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2945                 /* update threshold */
2946                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2947                 /* update init credit */
2948                 init_crd = 778;         /* (800-18-4) */
2949
2950         } else {
2951                 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2952                               ETH_OVREHEAD)/16;
2953                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2954                 /* update threshold */
2955                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2956                 /* update init credit */
2957                 switch (line_speed) {
2958                 case SPEED_10000:
2959                         init_crd = thresh + 553 - 22;
2960                         break;
2961                 default:
2962                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2963                                   line_speed);
2964                         return -EINVAL;
2965                 }
2966         }
2967         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2968         DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2969                  line_speed, init_crd);
2970
2971         /* probe the credit changes */
2972         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2973         msleep(5);
2974         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2975
2976         /* enable port */
2977         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2978         return 0;
2979 }
2980
2981 /**
2982  * bnx2x_get_emac_base - retrive emac base address
2983  *
2984  * @bp:                 driver handle
2985  * @mdc_mdio_access:    access type
2986  * @port:               port id
2987  *
2988  * This function selects the MDC/MDIO access (through emac0 or
2989  * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2990  * phy has a default access mode, which could also be overridden
2991  * by nvram configuration. This parameter, whether this is the
2992  * default phy configuration, or the nvram overrun
2993  * configuration, is passed here as mdc_mdio_access and selects
2994  * the emac_base for the CL45 read/writes operations
2995  */
2996 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2997                                u32 mdc_mdio_access, u8 port)
2998 {
2999         u32 emac_base = 0;
3000         switch (mdc_mdio_access) {
3001         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
3002                 break;
3003         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
3004                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
3005                         emac_base = GRCBASE_EMAC1;
3006                 else
3007                         emac_base = GRCBASE_EMAC0;
3008                 break;
3009         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
3010                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
3011                         emac_base = GRCBASE_EMAC0;
3012                 else
3013                         emac_base = GRCBASE_EMAC1;
3014                 break;
3015         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
3016                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3017                 break;
3018         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
3019                 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
3020                 break;
3021         default:
3022                 break;
3023         }
3024         return emac_base;
3025
3026 }
3027
3028 /******************************************************************/
3029 /*                      CL22 access functions                     */
3030 /******************************************************************/
3031 static int bnx2x_cl22_write(struct bnx2x *bp,
3032                                        struct bnx2x_phy *phy,
3033                                        u16 reg, u16 val)
3034 {
3035         u32 tmp, mode;
3036         u8 i;
3037         int rc = 0;
3038         /* Switch to CL22 */
3039         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
3040         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
3041                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
3042
3043         /* address */
3044         tmp = ((phy->addr << 21) | (reg << 16) | val |
3045                EMAC_MDIO_COMM_COMMAND_WRITE_22 |
3046                EMAC_MDIO_COMM_START_BUSY);
3047         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3048
3049         for (i = 0; i < 50; i++) {
3050                 udelay(10);
3051
3052                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3053                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3054                         udelay(5);
3055                         break;
3056                 }
3057         }
3058         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3059                 DP(NETIF_MSG_LINK, "write phy register failed\n");
3060                 rc = -EFAULT;
3061         }
3062         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
3063         return rc;
3064 }
3065
3066 static int bnx2x_cl22_read(struct bnx2x *bp,
3067                                       struct bnx2x_phy *phy,
3068                                       u16 reg, u16 *ret_val)
3069 {
3070         u32 val, mode;
3071         u16 i;
3072         int rc = 0;
3073
3074         /* Switch to CL22 */
3075         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
3076         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
3077                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
3078
3079         /* address */
3080         val = ((phy->addr << 21) | (reg << 16) |
3081                EMAC_MDIO_COMM_COMMAND_READ_22 |
3082                EMAC_MDIO_COMM_START_BUSY);
3083         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3084
3085         for (i = 0; i < 50; i++) {
3086                 udelay(10);
3087
3088                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3089                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3090                         *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
3091                         udelay(5);
3092                         break;
3093                 }
3094         }
3095         if (val & EMAC_MDIO_COMM_START_BUSY) {
3096                 DP(NETIF_MSG_LINK, "read phy register failed\n");
3097
3098                 *ret_val = 0;
3099                 rc = -EFAULT;
3100         }
3101         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
3102         return rc;
3103 }
3104
3105 /******************************************************************/
3106 /*                      CL45 access functions                     */
3107 /******************************************************************/
3108 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
3109                            u8 devad, u16 reg, u16 *ret_val)
3110 {
3111         u32 val;
3112         u16 i;
3113         int rc = 0;
3114         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3115                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3116                               EMAC_MDIO_STATUS_10MB);
3117         /* address */
3118         val = ((phy->addr << 21) | (devad << 16) | reg |
3119                EMAC_MDIO_COMM_COMMAND_ADDRESS |
3120                EMAC_MDIO_COMM_START_BUSY);
3121         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3122
3123         for (i = 0; i < 50; i++) {
3124                 udelay(10);
3125
3126                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3127                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3128                         udelay(5);
3129                         break;
3130                 }
3131         }
3132         if (val & EMAC_MDIO_COMM_START_BUSY) {
3133                 DP(NETIF_MSG_LINK, "read phy register failed\n");
3134                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
3135                 *ret_val = 0;
3136                 rc = -EFAULT;
3137         } else {
3138                 /* data */
3139                 val = ((phy->addr << 21) | (devad << 16) |
3140                        EMAC_MDIO_COMM_COMMAND_READ_45 |
3141                        EMAC_MDIO_COMM_START_BUSY);
3142                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3143
3144                 for (i = 0; i < 50; i++) {
3145                         udelay(10);
3146
3147                         val = REG_RD(bp, phy->mdio_ctrl +
3148                                      EMAC_REG_EMAC_MDIO_COMM);
3149                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3150                                 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
3151                                 break;
3152                         }
3153                 }
3154                 if (val & EMAC_MDIO_COMM_START_BUSY) {
3155                         DP(NETIF_MSG_LINK, "read phy register failed\n");
3156                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
3157                         *ret_val = 0;
3158                         rc = -EFAULT;
3159                 }
3160         }
3161         /* Work around for E3 A0 */
3162         if (phy->flags & FLAGS_MDC_MDIO_WA) {
3163                 phy->flags ^= FLAGS_DUMMY_READ;
3164                 if (phy->flags & FLAGS_DUMMY_READ) {
3165                         u16 temp_val;
3166                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3167                 }
3168         }
3169
3170         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3171                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3172                                EMAC_MDIO_STATUS_10MB);
3173         return rc;
3174 }
3175
3176 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3177                             u8 devad, u16 reg, u16 val)
3178 {
3179         u32 tmp;
3180         u8 i;
3181         int rc = 0;
3182         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3183                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3184                               EMAC_MDIO_STATUS_10MB);
3185
3186         /* address */
3187         tmp = ((phy->addr << 21) | (devad << 16) | reg |
3188                EMAC_MDIO_COMM_COMMAND_ADDRESS |
3189                EMAC_MDIO_COMM_START_BUSY);
3190         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3191
3192         for (i = 0; i < 50; i++) {
3193                 udelay(10);
3194
3195                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3196                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3197                         udelay(5);
3198                         break;
3199                 }
3200         }
3201         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3202                 DP(NETIF_MSG_LINK, "write phy register failed\n");
3203                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
3204                 rc = -EFAULT;
3205         } else {
3206                 /* data */
3207                 tmp = ((phy->addr << 21) | (devad << 16) | val |
3208                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
3209                        EMAC_MDIO_COMM_START_BUSY);
3210                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3211
3212                 for (i = 0; i < 50; i++) {
3213                         udelay(10);
3214
3215                         tmp = REG_RD(bp, phy->mdio_ctrl +
3216                                      EMAC_REG_EMAC_MDIO_COMM);
3217                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3218                                 udelay(5);
3219                                 break;
3220                         }
3221                 }
3222                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3223                         DP(NETIF_MSG_LINK, "write phy register failed\n");
3224                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
3225                         rc = -EFAULT;
3226                 }
3227         }
3228         /* Work around for E3 A0 */
3229         if (phy->flags & FLAGS_MDC_MDIO_WA) {
3230                 phy->flags ^= FLAGS_DUMMY_READ;
3231                 if (phy->flags & FLAGS_DUMMY_READ) {
3232                         u16 temp_val;
3233                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3234                 }
3235         }
3236         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3237                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3238                                EMAC_MDIO_STATUS_10MB);
3239         return rc;
3240 }
3241 /******************************************************************/
3242 /*                      BSC access functions from E3              */
3243 /******************************************************************/
3244 static void bnx2x_bsc_module_sel(struct link_params *params)
3245 {
3246         int idx;
3247         u32 board_cfg, sfp_ctrl;
3248         u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3249         struct bnx2x *bp = params->bp;
3250         u8 port = params->port;
3251         /* Read I2C output PINs */
3252         board_cfg = REG_RD(bp, params->shmem_base +
3253                            offsetof(struct shmem_region,
3254                                     dev_info.shared_hw_config.board));
3255         i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3256         i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3257                         SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3258
3259         /* Read I2C output value */
3260         sfp_ctrl = REG_RD(bp, params->shmem_base +
3261                           offsetof(struct shmem_region,
3262                                  dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3263         i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3264         i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3265         DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3266         for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3267                 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3268 }
3269
3270 static int bnx2x_bsc_read(struct link_params *params,
3271                           struct bnx2x_phy *phy,
3272                           u8 sl_devid,
3273                           u16 sl_addr,
3274                           u8 lc_addr,
3275                           u8 xfer_cnt,
3276                           u32 *data_array)
3277 {
3278         u32 val, i;
3279         int rc = 0;
3280         struct bnx2x *bp = params->bp;
3281
3282         if ((sl_devid != 0xa0) && (sl_devid != 0xa2)) {
3283                 DP(NETIF_MSG_LINK, "invalid sl_devid 0x%x\n", sl_devid);
3284                 return -EINVAL;
3285         }
3286
3287         if (xfer_cnt > 16) {
3288                 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3289                                         xfer_cnt);
3290                 return -EINVAL;
3291         }
3292         bnx2x_bsc_module_sel(params);
3293
3294         xfer_cnt = 16 - lc_addr;
3295
3296         /* enable the engine */
3297         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3298         val |= MCPR_IMC_COMMAND_ENABLE;
3299         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3300
3301         /* program slave device ID */
3302         val = (sl_devid << 16) | sl_addr;
3303         REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3304
3305         /* start xfer with 0 byte to update the address pointer ???*/
3306         val = (MCPR_IMC_COMMAND_ENABLE) |
3307               (MCPR_IMC_COMMAND_WRITE_OP <<
3308                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3309                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3310         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3311
3312         /* poll for completion */
3313         i = 0;
3314         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3315         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3316                 udelay(10);
3317                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3318                 if (i++ > 1000) {
3319                         DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3320                                                                 i);
3321                         rc = -EFAULT;
3322                         break;
3323                 }
3324         }
3325         if (rc == -EFAULT)
3326                 return rc;
3327
3328         /* start xfer with read op */
3329         val = (MCPR_IMC_COMMAND_ENABLE) |
3330                 (MCPR_IMC_COMMAND_READ_OP <<
3331                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3332                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3333                   (xfer_cnt);
3334         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3335
3336         /* poll for completion */
3337         i = 0;
3338         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3339         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3340                 udelay(10);
3341                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3342                 if (i++ > 1000) {
3343                         DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3344                         rc = -EFAULT;
3345                         break;
3346                 }
3347         }
3348         if (rc == -EFAULT)
3349                 return rc;
3350
3351         for (i = (lc_addr >> 2); i < 4; i++) {
3352                 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3353 #ifdef __BIG_ENDIAN
3354                 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3355                                 ((data_array[i] & 0x0000ff00) << 8) |
3356                                 ((data_array[i] & 0x00ff0000) >> 8) |
3357                                 ((data_array[i] & 0xff000000) >> 24);
3358 #endif
3359         }
3360         return rc;
3361 }
3362
3363 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3364                                      u8 devad, u16 reg, u16 or_val)
3365 {
3366         u16 val;
3367         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3368         bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3369 }
3370
3371 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3372                    u8 devad, u16 reg, u16 *ret_val)
3373 {
3374         u8 phy_index;
3375         /* Probe for the phy according to the given phy_addr, and execute
3376          * the read request on it
3377          */
3378         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3379                 if (params->phy[phy_index].addr == phy_addr) {
3380                         return bnx2x_cl45_read(params->bp,
3381                                                &params->phy[phy_index], devad,
3382                                                reg, ret_val);
3383                 }
3384         }
3385         return -EINVAL;
3386 }
3387
3388 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3389                     u8 devad, u16 reg, u16 val)
3390 {
3391         u8 phy_index;
3392         /* Probe for the phy according to the given phy_addr, and execute
3393          * the write request on it
3394          */
3395         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3396                 if (params->phy[phy_index].addr == phy_addr) {
3397                         return bnx2x_cl45_write(params->bp,
3398                                                 &params->phy[phy_index], devad,
3399                                                 reg, val);
3400                 }
3401         }
3402         return -EINVAL;
3403 }
3404 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3405                                   struct link_params *params)
3406 {
3407         u8 lane = 0;
3408         struct bnx2x *bp = params->bp;
3409         u32 path_swap, path_swap_ovr;
3410         u8 path, port;
3411
3412         path = BP_PATH(bp);
3413         port = params->port;
3414
3415         if (bnx2x_is_4_port_mode(bp)) {
3416                 u32 port_swap, port_swap_ovr;
3417
3418                 /* Figure out path swap value */
3419                 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3420                 if (path_swap_ovr & 0x1)
3421                         path_swap = (path_swap_ovr & 0x2);
3422                 else
3423                         path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3424
3425                 if (path_swap)
3426                         path = path ^ 1;
3427
3428                 /* Figure out port swap value */
3429                 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3430                 if (port_swap_ovr & 0x1)
3431                         port_swap = (port_swap_ovr & 0x2);
3432                 else
3433                         port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3434
3435                 if (port_swap)
3436                         port = port ^ 1;
3437
3438                 lane = (port<<1) + path;
3439         } else { /* two port mode - no port swap */
3440
3441                 /* Figure out path swap value */
3442                 path_swap_ovr =
3443                         REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3444                 if (path_swap_ovr & 0x1) {
3445                         path_swap = (path_swap_ovr & 0x2);
3446                 } else {
3447                         path_swap =
3448                                 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3449                 }
3450                 if (path_swap)
3451                         path = path ^ 1;
3452
3453                 lane = path << 1 ;
3454         }
3455         return lane;
3456 }
3457
3458 static void bnx2x_set_aer_mmd(struct link_params *params,
3459                               struct bnx2x_phy *phy)
3460 {
3461         u32 ser_lane;
3462         u16 offset, aer_val;
3463         struct bnx2x *bp = params->bp;
3464         ser_lane = ((params->lane_config &
3465                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3466                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3467
3468         offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3469                 (phy->addr + ser_lane) : 0;
3470
3471         if (USES_WARPCORE(bp)) {
3472                 aer_val = bnx2x_get_warpcore_lane(phy, params);
3473                 /* In Dual-lane mode, two lanes are joined together,
3474                  * so in order to configure them, the AER broadcast method is
3475                  * used here.
3476                  * 0x200 is the broadcast address for lanes 0,1
3477                  * 0x201 is the broadcast address for lanes 2,3
3478                  */
3479                 if (phy->flags & FLAGS_WC_DUAL_MODE)
3480                         aer_val = (aer_val >> 1) | 0x200;
3481         } else if (CHIP_IS_E2(bp))
3482                 aer_val = 0x3800 + offset - 1;
3483         else
3484                 aer_val = 0x3800 + offset;
3485
3486         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3487                           MDIO_AER_BLOCK_AER_REG, aer_val);
3488
3489 }
3490
3491 /******************************************************************/
3492 /*                      Internal phy section                      */
3493 /******************************************************************/
3494
3495 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3496 {
3497         u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3498
3499         /* Set Clause 22 */
3500         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3501         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3502         udelay(500);
3503         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3504         udelay(500);
3505          /* Set Clause 45 */
3506         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3507 }
3508
3509 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3510 {
3511         u32 val;
3512
3513         DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3514
3515         val = SERDES_RESET_BITS << (port*16);
3516
3517         /* reset and unreset the SerDes/XGXS */
3518         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3519         udelay(500);
3520         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3521
3522         bnx2x_set_serdes_access(bp, port);
3523
3524         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3525                DEFAULT_PHY_DEV_ADDR);
3526 }
3527
3528 static void bnx2x_xgxs_deassert(struct link_params *params)
3529 {
3530         struct bnx2x *bp = params->bp;
3531         u8 port;
3532         u32 val;
3533         DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3534         port = params->port;
3535
3536         val = XGXS_RESET_BITS << (port*16);
3537
3538         /* reset and unreset the SerDes/XGXS */
3539         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3540         udelay(500);
3541         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3542
3543         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
3544         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
3545                params->phy[INT_PHY].def_md_devad);
3546 }
3547
3548 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3549                                      struct link_params *params, u16 *ieee_fc)
3550 {
3551         struct bnx2x *bp = params->bp;
3552         *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3553         /* Resolve pause mode and advertisement Please refer to Table
3554          * 28B-3 of the 802.3ab-1999 spec
3555          */
3556
3557         switch (phy->req_flow_ctrl) {
3558         case BNX2X_FLOW_CTRL_AUTO:
3559                 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
3560                         *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3561                 else
3562                         *ieee_fc |=
3563                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3564                 break;
3565
3566         case BNX2X_FLOW_CTRL_TX:
3567                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3568                 break;
3569
3570         case BNX2X_FLOW_CTRL_RX:
3571         case BNX2X_FLOW_CTRL_BOTH:
3572                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3573                 break;
3574
3575         case BNX2X_FLOW_CTRL_NONE:
3576         default:
3577                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3578                 break;
3579         }
3580         DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3581 }
3582
3583 static void set_phy_vars(struct link_params *params,
3584                          struct link_vars *vars)
3585 {
3586         struct bnx2x *bp = params->bp;
3587         u8 actual_phy_idx, phy_index, link_cfg_idx;
3588         u8 phy_config_swapped = params->multi_phy_config &
3589                         PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3590         for (phy_index = INT_PHY; phy_index < params->num_phys;
3591               phy_index++) {
3592                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3593                 actual_phy_idx = phy_index;
3594                 if (phy_config_swapped) {
3595                         if (phy_index == EXT_PHY1)
3596                                 actual_phy_idx = EXT_PHY2;
3597                         else if (phy_index == EXT_PHY2)
3598                                 actual_phy_idx = EXT_PHY1;
3599                 }
3600                 params->phy[actual_phy_idx].req_flow_ctrl =
3601                         params->req_flow_ctrl[link_cfg_idx];
3602
3603                 params->phy[actual_phy_idx].req_line_speed =
3604                         params->req_line_speed[link_cfg_idx];
3605
3606                 params->phy[actual_phy_idx].speed_cap_mask =
3607                         params->speed_cap_mask[link_cfg_idx];
3608
3609                 params->phy[actual_phy_idx].req_duplex =
3610                         params->req_duplex[link_cfg_idx];
3611
3612                 if (params->req_line_speed[link_cfg_idx] ==
3613                     SPEED_AUTO_NEG)
3614                         vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3615
3616                 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3617                            " speed_cap_mask %x\n",
3618                            params->phy[actual_phy_idx].req_flow_ctrl,
3619                            params->phy[actual_phy_idx].req_line_speed,
3620                            params->phy[actual_phy_idx].speed_cap_mask);
3621         }
3622 }
3623
3624 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3625                                     struct bnx2x_phy *phy,
3626                                     struct link_vars *vars)
3627 {
3628         u16 val;
3629         struct bnx2x *bp = params->bp;
3630         /* read modify write pause advertizing */
3631         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3632
3633         val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3634
3635         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3636         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3637         if ((vars->ieee_fc &
3638             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3639             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3640                 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3641         }
3642         if ((vars->ieee_fc &
3643             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3644             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3645                 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3646         }
3647         DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3648         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3649 }
3650
3651 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3652 {                                               /*  LD      LP   */
3653         switch (pause_result) {                 /* ASYM P ASYM P */
3654         case 0xb:                               /*   1  0   1  1 */
3655                 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3656                 break;
3657
3658         case 0xe:                               /*   1  1   1  0 */
3659                 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3660                 break;
3661
3662         case 0x5:                               /*   0  1   0  1 */
3663         case 0x7:                               /*   0  1   1  1 */
3664         case 0xd:                               /*   1  1   0  1 */
3665         case 0xf:                               /*   1  1   1  1 */
3666                 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3667                 break;
3668
3669         default:
3670                 break;
3671         }
3672         if (pause_result & (1<<0))
3673                 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3674         if (pause_result & (1<<1))
3675                 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3676
3677 }
3678
3679 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
3680                                         struct link_params *params,
3681                                         struct link_vars *vars)
3682 {
3683         u16 ld_pause;           /* local */
3684         u16 lp_pause;           /* link partner */
3685         u16 pause_result;
3686         struct bnx2x *bp = params->bp;
3687         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3688                 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause);
3689                 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause);
3690         } else if (CHIP_IS_E3(bp) &&
3691                 SINGLE_MEDIA_DIRECT(params)) {
3692                 u8 lane = bnx2x_get_warpcore_lane(phy, params);
3693                 u16 gp_status, gp_mask;
3694                 bnx2x_cl45_read(bp, phy,
3695                                 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
3696                                 &gp_status);
3697                 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
3698                            MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3699                         lane;
3700                 if ((gp_status & gp_mask) == gp_mask) {
3701                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3702                                         MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3703                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3704                                         MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3705                 } else {
3706                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3707                                         MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3708                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3709                                         MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3710                         ld_pause = ((ld_pause &
3711                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3712                                     << 3);
3713                         lp_pause = ((lp_pause &
3714                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3715                                     << 3);
3716                 }
3717         } else {
3718                 bnx2x_cl45_read(bp, phy,
3719                                 MDIO_AN_DEVAD,
3720                                 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3721                 bnx2x_cl45_read(bp, phy,
3722                                 MDIO_AN_DEVAD,
3723                                 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3724         }
3725         pause_result = (ld_pause &
3726                         MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3727         pause_result |= (lp_pause &
3728                          MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3729         DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result);
3730         bnx2x_pause_resolve(vars, pause_result);
3731
3732 }
3733
3734 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3735                                    struct link_params *params,
3736                                    struct link_vars *vars)
3737 {
3738         u8 ret = 0;
3739         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3740         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
3741                 /* Update the advertised flow-controled of LD/LP in AN */
3742                 if (phy->req_line_speed == SPEED_AUTO_NEG)
3743                         bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3744                 /* But set the flow-control result as the requested one */
3745                 vars->flow_ctrl = phy->req_flow_ctrl;
3746         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
3747                 vars->flow_ctrl = params->req_fc_auto_adv;
3748         else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3749                 ret = 1;
3750                 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3751         }
3752         return ret;
3753 }
3754 /******************************************************************/
3755 /*                      Warpcore section                          */
3756 /******************************************************************/
3757 /* The init_internal_warpcore should mirror the xgxs,
3758  * i.e. reset the lane (if needed), set aer for the
3759  * init configuration, and set/clear SGMII flag. Internal
3760  * phy init is done purely in phy_init stage.
3761  */
3762 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3763                                         struct link_params *params,
3764                                         struct link_vars *vars) {
3765         u16 val16 = 0, lane, bam37 = 0;
3766         struct bnx2x *bp = params->bp;
3767         DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3768         /* Set to default registers that may be overriden by 10G force */
3769         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3770                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7);
3771         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3772                          MDIO_WC_REG_PAR_DET_10G_CTRL, 0);
3773         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3774                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0);
3775         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3776                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0xff);
3777         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3778                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0x5555);
3779         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3780                          MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0);
3781         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3782                          MDIO_WC_REG_RX66_CONTROL, 0x7415);
3783         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3784                          MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190);
3785         /* Disable Autoneg: re-enable it after adv is done. */
3786         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3787                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0);
3788
3789         /* Check adding advertisement for 1G KX */
3790         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3791              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3792             (vars->line_speed == SPEED_1000)) {
3793                 u16 sd_digital;
3794                 val16 |= (1<<5);
3795
3796                 /* Enable CL37 1G Parallel Detect */
3797                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3798                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &sd_digital);
3799                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3800                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3801                                  (sd_digital | 0x1));
3802
3803                 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3804         }
3805         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3806              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3807             (vars->line_speed ==  SPEED_10000)) {
3808                 /* Check adding advertisement for 10G KR */
3809                 val16 |= (1<<7);
3810                 /* Enable 10G Parallel Detect */
3811                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3812                                 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3813
3814                 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3815         }
3816
3817         /* Set Transmit PMD settings */
3818         lane = bnx2x_get_warpcore_lane(phy, params);
3819         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3820                       MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3821                      ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3822                       (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3823                       (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3824         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3825                          MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3826                          0x03f0);
3827         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3828                          MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3829                          0x03f0);
3830
3831         /* Advertised speeds */
3832         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3833                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, val16);
3834
3835         /* Advertised and set FEC (Forward Error Correction) */
3836         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3837                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3838                          (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3839                           MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3840
3841         /* Enable CL37 BAM */
3842         if (REG_RD(bp, params->shmem_base +
3843                    offsetof(struct shmem_region, dev_info.
3844                             port_hw_config[params->port].default_cfg)) &
3845             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3846                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3847                                 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, &bam37);
3848                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3849                         MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, bam37 | 1);
3850                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3851         }
3852
3853         /* Advertise pause */
3854         bnx2x_ext_phy_set_pause(params, phy, vars);
3855         /* Set KR Autoneg Work-Around flag for Warpcore version older than D108
3856          */
3857         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3858                         MDIO_WC_REG_UC_INFO_B1_VERSION, &val16);
3859         if (val16 < 0xd108) {
3860                 DP(NETIF_MSG_LINK, "Enable AN KR work-around\n");
3861                 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3862         }
3863         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3864                         MDIO_WC_REG_DIGITAL5_MISC7, &val16);
3865
3866         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3867                          MDIO_WC_REG_DIGITAL5_MISC7, val16 | 0x100);
3868
3869         /* Over 1G - AN local device user page 1 */
3870         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3871                         MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3872
3873         /* Enable Autoneg */
3874         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3875                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
3876
3877 }
3878
3879 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3880                                       struct link_params *params,
3881                                       struct link_vars *vars)
3882 {
3883         struct bnx2x *bp = params->bp;
3884         u16 val;
3885
3886         /* Disable Autoneg */
3887         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3888                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7);
3889
3890         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3891                          MDIO_WC_REG_PAR_DET_10G_CTRL, 0);
3892
3893         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3894                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0x3f00);
3895
3896         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3897                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0);
3898
3899         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3900                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3901
3902         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3903                         MDIO_WC_REG_DIGITAL3_UP1, 0x1);
3904
3905         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3906                          MDIO_WC_REG_DIGITAL5_MISC7, 0xa);
3907
3908         /* Disable CL36 PCS Tx */
3909         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3910                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0x0);
3911
3912         /* Double Wide Single Data Rate @ pll rate */
3913         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3914                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0xFFFF);
3915
3916         /* Leave cl72 training enable, needed for KR */
3917         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3918                 MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150,
3919                 0x2);
3920
3921         /* Leave CL72 enabled */
3922         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3923                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3924                          &val);
3925         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3926                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3927                          val | 0x3800);
3928
3929         /* Set speed via PMA/PMD register */
3930         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3931                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3932
3933         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3934                          MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3935
3936         /* Enable encoded forced speed */
3937         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3938                          MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3939
3940         /* Turn TX scramble payload only the 64/66 scrambler */
3941         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3942                          MDIO_WC_REG_TX66_CONTROL, 0x9);
3943
3944         /* Turn RX scramble payload only the 64/66 scrambler */
3945         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3946                                  MDIO_WC_REG_RX66_CONTROL, 0xF9);
3947
3948         /* set and clear loopback to cause a reset to 64/66 decoder */
3949         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3950                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3951         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3952                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3953
3954 }
3955
3956 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3957                                        struct link_params *params,
3958                                        u8 is_xfi)
3959 {
3960         struct bnx2x *bp = params->bp;
3961         u16 misc1_val, tap_val, tx_driver_val, lane, val;
3962         /* Hold rxSeqStart */
3963         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3964                         MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3965         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3966                          MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val | 0x8000));
3967
3968         /* Hold tx_fifo_reset */
3969         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3970                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3971         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3972                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, (val | 0x1));
3973
3974         /* Disable CL73 AN */
3975         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3976
3977         /* Disable 100FX Enable and Auto-Detect */
3978         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3979                         MDIO_WC_REG_FX100_CTRL1, &val);
3980         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3981                          MDIO_WC_REG_FX100_CTRL1, (val & 0xFFFA));
3982
3983         /* Disable 100FX Idle detect */
3984         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3985                         MDIO_WC_REG_FX100_CTRL3, &val);
3986         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3987                          MDIO_WC_REG_FX100_CTRL3, (val | 0x0080));
3988
3989         /* Set Block address to Remote PHY & Clear forced_speed[5] */
3990         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3991                         MDIO_WC_REG_DIGITAL4_MISC3, &val);
3992         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3993                          MDIO_WC_REG_DIGITAL4_MISC3, (val & 0xFF7F));
3994
3995         /* Turn off auto-detect & fiber mode */
3996         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3997                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3998         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3999                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4000                          (val & 0xFFEE));
4001
4002         /* Set filter_force_link, disable_false_link and parallel_detect */
4003         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4004                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
4005         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4006                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4007                          ((val | 0x0006) & 0xFFFE));
4008
4009         /* Set XFI / SFI */
4010         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4011                         MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
4012
4013         misc1_val &= ~(0x1f);
4014
4015         if (is_xfi) {
4016                 misc1_val |= 0x5;
4017                 tap_val = ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
4018                            (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
4019                            (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
4020                 tx_driver_val =
4021                       ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
4022                        (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
4023                        (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
4024
4025         } else {
4026                 misc1_val |= 0x9;
4027                 tap_val = ((0x0f << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
4028                            (0x2b << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
4029                            (0x02 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
4030                 tx_driver_val =
4031                       ((0x03 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
4032                        (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
4033                        (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
4034         }
4035         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4036                          MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
4037
4038         /* Set Transmit PMD settings */
4039         lane = bnx2x_get_warpcore_lane(phy, params);
4040         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4041                          MDIO_WC_REG_TX_FIR_TAP,
4042                          tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
4043         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4044                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4045                          tx_driver_val);
4046
4047         /* Enable fiber mode, enable and invert sig_det */
4048         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4049                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
4050         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4051                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, val | 0xd);
4052
4053         /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
4054         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4055                         MDIO_WC_REG_DIGITAL4_MISC3, &val);
4056         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4057                          MDIO_WC_REG_DIGITAL4_MISC3, val | 0x8080);
4058
4059         /* Enable LPI pass through */
4060         DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n");
4061         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4062                          MDIO_WC_REG_EEE_COMBO_CONTROL0,
4063                          0x7c);
4064         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4065                                  MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
4066
4067         /* 10G XFI Full Duplex */
4068         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4069                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
4070
4071         /* Release tx_fifo_reset */
4072         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4073                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
4074         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4075                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, val & 0xFFFE);
4076
4077         /* Release rxSeqStart */
4078         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4079                         MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
4080         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4081                          MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val & 0x7FFF));
4082 }
4083
4084 static void bnx2x_warpcore_set_20G_KR2(struct bnx2x *bp,
4085                                        struct bnx2x_phy *phy)
4086 {
4087         DP(NETIF_MSG_LINK, "KR2 still not supported !!!\n");
4088 }
4089
4090 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
4091                                          struct bnx2x_phy *phy,
4092                                          u16 lane)
4093 {
4094         /* Rx0 anaRxControl1G */
4095         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4096                          MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4097
4098         /* Rx2 anaRxControl1G */
4099         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4100                          MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4101
4102         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4103                          MDIO_WC_REG_RX66_SCW0, 0xE070);
4104
4105         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4106                          MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4107
4108         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4109                          MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4110
4111         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4112                          MDIO_WC_REG_RX66_SCW3, 0x8090);
4113
4114         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4115                          MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4116
4117         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4118                          MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4119
4120         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4121                          MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
4122
4123         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4124                          MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
4125
4126         /* Serdes Digital Misc1 */
4127         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4128                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
4129
4130         /* Serdes Digital4 Misc3 */
4131         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4132                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
4133
4134         /* Set Transmit PMD settings */
4135         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4136                          MDIO_WC_REG_TX_FIR_TAP,
4137                         ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
4138                          (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
4139                          (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET) |
4140                          MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4141         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4142                       MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4143                      ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
4144                       (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
4145                       (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
4146 }
4147
4148 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
4149                                            struct link_params *params,
4150                                            u8 fiber_mode,
4151                                            u8 always_autoneg)
4152 {
4153         struct bnx2x *bp = params->bp;
4154         u16 val16, digctrl_kx1, digctrl_kx2;
4155
4156         /* Clear XFI clock comp in non-10G single lane mode. */
4157         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4158                         MDIO_WC_REG_RX66_CONTROL, &val16);
4159         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4160                          MDIO_WC_REG_RX66_CONTROL, val16 & ~(3<<13));
4161
4162         if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) {
4163                 /* SGMII Autoneg */
4164                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4165                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4166                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4167                                  MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4168                                  val16 | 0x1000);
4169                 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
4170         } else {
4171                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4172                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4173                 val16 &= 0xcebf;
4174                 switch (phy->req_line_speed) {
4175                 case SPEED_10:
4176                         break;
4177                 case SPEED_100:
4178                         val16 |= 0x2000;
4179                         break;
4180                 case SPEED_1000:
4181                         val16 |= 0x0040;
4182                         break;
4183                 default:
4184                         DP(NETIF_MSG_LINK,
4185                            "Speed not supported: 0x%x\n", phy->req_line_speed);
4186                         return;
4187                 }
4188
4189                 if (phy->req_duplex == DUPLEX_FULL)
4190                         val16 |= 0x0100;
4191
4192                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4193                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
4194
4195                 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
4196                                phy->req_line_speed);
4197                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4198                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4199                 DP(NETIF_MSG_LINK, "  (readback) %x\n", val16);
4200         }
4201
4202         /* SGMII Slave mode and disable signal detect */
4203         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4204                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
4205         if (fiber_mode)
4206                 digctrl_kx1 = 1;
4207         else
4208                 digctrl_kx1 &= 0xff4a;
4209
4210         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4211                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4212                         digctrl_kx1);
4213
4214         /* Turn off parallel detect */
4215         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4216                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
4217         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4218                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4219                         (digctrl_kx2 & ~(1<<2)));
4220
4221         /* Re-enable parallel detect */
4222         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4223                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4224                         (digctrl_kx2 | (1<<2)));
4225
4226         /* Enable autodet */
4227         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4228                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4229                         (digctrl_kx1 | 0x10));
4230 }
4231
4232 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4233                                       struct bnx2x_phy *phy,
4234                                       u8 reset)
4235 {
4236         u16 val;
4237         /* Take lane out of reset after configuration is finished */
4238         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4239                         MDIO_WC_REG_DIGITAL5_MISC6, &val);
4240         if (reset)
4241                 val |= 0xC000;
4242         else
4243                 val &= 0x3FFF;
4244         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4245                          MDIO_WC_REG_DIGITAL5_MISC6, val);
4246         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4247                          MDIO_WC_REG_DIGITAL5_MISC6, &val);
4248 }
4249 /* Clear SFI/XFI link settings registers */
4250 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4251                                       struct link_params *params,
4252                                       u16 lane)
4253 {
4254         struct bnx2x *bp = params->bp;
4255         u16 val16;
4256
4257         /* Set XFI clock comp as default. */
4258         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4259                         MDIO_WC_REG_RX66_CONTROL, &val16);
4260         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4261                          MDIO_WC_REG_RX66_CONTROL, val16 | (3<<13));
4262
4263         bnx2x_warpcore_reset_lane(bp, phy, 1);
4264         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
4265         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4266                          MDIO_WC_REG_FX100_CTRL1, 0x014a);
4267         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4268                          MDIO_WC_REG_FX100_CTRL3, 0x0800);
4269         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4270                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8008);
4271         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4272                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x0195);
4273         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4274                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x0007);
4275         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4276                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x0002);
4277         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4278                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000);
4279         lane = bnx2x_get_warpcore_lane(phy, params);
4280         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4281                          MDIO_WC_REG_TX_FIR_TAP, 0x0000);
4282         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4283                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4284         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4285                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
4286         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4287                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140);
4288         bnx2x_warpcore_reset_lane(bp, phy, 0);
4289 }
4290
4291 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4292                                                 u32 chip_id,
4293                                                 u32 shmem_base, u8 port,
4294                                                 u8 *gpio_num, u8 *gpio_port)
4295 {
4296         u32 cfg_pin;
4297         *gpio_num = 0;
4298         *gpio_port = 0;
4299         if (CHIP_IS_E3(bp)) {
4300                 cfg_pin = (REG_RD(bp, shmem_base +
4301                                 offsetof(struct shmem_region,
4302                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4303                                 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4304                                 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4305
4306                 /* Should not happen. This function called upon interrupt
4307                  * triggered by GPIO ( since EPIO can only generate interrupts
4308                  * to MCP).
4309                  * So if this function was called and none of the GPIOs was set,
4310                  * it means the shit hit the fan.
4311                  */
4312                 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4313                     (cfg_pin > PIN_CFG_GPIO3_P1)) {
4314                         DP(NETIF_MSG_LINK,
4315                            "ERROR: Invalid cfg pin %x for module detect indication\n",
4316                            cfg_pin);
4317                         return -EINVAL;
4318                 }
4319
4320                 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4321                 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4322         } else {
4323                 *gpio_num = MISC_REGISTERS_GPIO_3;
4324                 *gpio_port = port;
4325         }
4326         DP(NETIF_MSG_LINK, "MOD_ABS int GPIO%d_P%d\n", *gpio_num, *gpio_port);
4327         return 0;
4328 }
4329
4330 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4331                                        struct link_params *params)
4332 {
4333         struct bnx2x *bp = params->bp;
4334         u8 gpio_num, gpio_port;
4335         u32 gpio_val;
4336         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4337                                       params->shmem_base, params->port,
4338                                       &gpio_num, &gpio_port) != 0)
4339                 return 0;
4340         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4341
4342         /* Call the handling function in case module is detected */
4343         if (gpio_val == 0)
4344                 return 1;
4345         else
4346                 return 0;
4347 }
4348 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy,
4349                                         struct link_params *params)
4350 {
4351         u16 gp2_status_reg0, lane;
4352         struct bnx2x *bp = params->bp;
4353
4354         lane = bnx2x_get_warpcore_lane(phy, params);
4355
4356         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4357                                  &gp2_status_reg0);
4358
4359         return (gp2_status_reg0 >> (8+lane)) & 0x1;
4360 }
4361
4362 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4363                                        struct link_params *params,
4364                                        struct link_vars *vars)
4365 {
4366         struct bnx2x *bp = params->bp;
4367         u32 serdes_net_if;
4368         u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4369         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4370
4371         vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4372
4373         if (!vars->turn_to_run_wc_rt)
4374                 return;
4375
4376         /* return if there is no link partner */
4377         if (!(bnx2x_warpcore_get_sigdet(phy, params))) {
4378                 DP(NETIF_MSG_LINK, "bnx2x_warpcore_get_sigdet false\n");
4379                 return;
4380         }
4381
4382         if (vars->rx_tx_asic_rst) {
4383                 serdes_net_if = (REG_RD(bp, params->shmem_base +
4384                                 offsetof(struct shmem_region, dev_info.
4385                                 port_hw_config[params->port].default_cfg)) &
4386                                 PORT_HW_CFG_NET_SERDES_IF_MASK);
4387
4388                 switch (serdes_net_if) {
4389                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4390                         /* Do we get link yet? */
4391                         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1,
4392                                                                 &gp_status1);
4393                         lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
4394                                 /*10G KR*/
4395                         lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
4396
4397                         DP(NETIF_MSG_LINK,
4398                                 "gp_status1 0x%x\n", gp_status1);
4399
4400                         if (lnkup_kr || lnkup) {
4401                                         vars->rx_tx_asic_rst = 0;
4402                                         DP(NETIF_MSG_LINK,
4403                                         "link up, rx_tx_asic_rst 0x%x\n",
4404                                         vars->rx_tx_asic_rst);
4405                         } else {
4406                                 /* Reset the lane to see if link comes up.*/
4407                                 bnx2x_warpcore_reset_lane(bp, phy, 1);
4408                                 bnx2x_warpcore_reset_lane(bp, phy, 0);
4409
4410                                 /* restart Autoneg */
4411                                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4412                                         MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4413
4414                                 vars->rx_tx_asic_rst--;
4415                                 DP(NETIF_MSG_LINK, "0x%x retry left\n",
4416                                 vars->rx_tx_asic_rst);
4417                         }
4418                         break;
4419
4420                 default:
4421                         break;
4422                 }
4423
4424         } /*params->rx_tx_asic_rst*/
4425
4426 }
4427 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4428                                        struct link_params *params,
4429                                        struct link_vars *vars)
4430 {
4431         struct bnx2x *bp = params->bp;
4432         u32 serdes_net_if;
4433         u8 fiber_mode;
4434         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4435         serdes_net_if = (REG_RD(bp, params->shmem_base +
4436                          offsetof(struct shmem_region, dev_info.
4437                                   port_hw_config[params->port].default_cfg)) &
4438                          PORT_HW_CFG_NET_SERDES_IF_MASK);
4439         DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4440                            "serdes_net_if = 0x%x\n",
4441                        vars->line_speed, serdes_net_if);
4442         bnx2x_set_aer_mmd(params, phy);
4443
4444         vars->phy_flags |= PHY_XGXS_FLAG;
4445         if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4446             (phy->req_line_speed &&
4447              ((phy->req_line_speed == SPEED_100) ||
4448               (phy->req_line_speed == SPEED_10)))) {
4449                 vars->phy_flags |= PHY_SGMII_FLAG;
4450                 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4451                 bnx2x_warpcore_clear_regs(phy, params, lane);
4452                 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1);
4453         } else {
4454                 switch (serdes_net_if) {
4455                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4456                         /* Enable KR Auto Neg */
4457                         if (params->loopback_mode != LOOPBACK_EXT)
4458                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4459                         else {
4460                                 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4461                                 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4462                         }
4463                         break;
4464
4465                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4466                         bnx2x_warpcore_clear_regs(phy, params, lane);
4467                         if (vars->line_speed == SPEED_10000) {
4468                                 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4469                                 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4470                         } else {
4471                                 if (SINGLE_MEDIA_DIRECT(params)) {
4472                                         DP(NETIF_MSG_LINK, "1G Fiber\n");
4473                                         fiber_mode = 1;
4474                                 } else {
4475                                         DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4476                                         fiber_mode = 0;
4477                                 }
4478                                 bnx2x_warpcore_set_sgmii_speed(phy,
4479                                                                 params,
4480                                                                 fiber_mode,
4481                                                                 0);
4482                         }
4483
4484                         break;
4485
4486                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4487
4488                         bnx2x_warpcore_clear_regs(phy, params, lane);
4489                         if (vars->line_speed == SPEED_10000) {
4490                                 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4491                                 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4492                         } else if (vars->line_speed == SPEED_1000) {
4493                                 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4494                                 bnx2x_warpcore_set_sgmii_speed(
4495                                                 phy, params, 1, 0);
4496                         }
4497                         /* Issue Module detection */
4498                         if (bnx2x_is_sfp_module_plugged(phy, params))
4499                                 bnx2x_sfp_module_detection(phy, params);
4500                         break;
4501
4502                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4503                         if (vars->line_speed != SPEED_20000) {
4504                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4505                                 return;
4506                         }
4507                         DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4508                         bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4509                         /* Issue Module detection */
4510
4511                         bnx2x_sfp_module_detection(phy, params);
4512                         break;
4513
4514                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4515                         if (vars->line_speed != SPEED_20000) {
4516                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4517                                 return;
4518                         }
4519                         DP(NETIF_MSG_LINK, "Setting 20G KR2\n");
4520                         bnx2x_warpcore_set_20G_KR2(bp, phy);
4521                         break;
4522
4523                 default:
4524                         DP(NETIF_MSG_LINK,
4525                            "Unsupported Serdes Net Interface 0x%x\n",
4526                            serdes_net_if);
4527                         return;
4528                 }
4529         }
4530
4531         /* Take lane out of reset after configuration is finished */
4532         bnx2x_warpcore_reset_lane(bp, phy, 0);
4533         DP(NETIF_MSG_LINK, "Exit config init\n");
4534 }
4535
4536 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4537                                          struct bnx2x_phy *phy,
4538                                          u8 tx_en)
4539 {
4540         struct bnx2x *bp = params->bp;
4541         u32 cfg_pin;
4542         u8 port = params->port;
4543
4544         cfg_pin = REG_RD(bp, params->shmem_base +
4545                                 offsetof(struct shmem_region,
4546                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4547                                 PORT_HW_CFG_TX_LASER_MASK;
4548         /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4549         DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4550         /* For 20G, the expected pin to be used is 3 pins after the current */
4551
4552         bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4553         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4554                 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4555 }
4556
4557 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4558                                       struct link_params *params)
4559 {
4560         struct bnx2x *bp = params->bp;
4561         u16 val16;
4562         bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4563         bnx2x_set_mdio_clk(bp, params->chip_id, params->port);
4564         bnx2x_set_aer_mmd(params, phy);
4565         /* Global register */
4566         bnx2x_warpcore_reset_lane(bp, phy, 1);
4567
4568         /* Clear loopback settings (if any) */
4569         /* 10G & 20G */
4570         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4571                         MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4572         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4573                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 &
4574                          0xBFFF);
4575
4576         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4577                         MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4578         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4579                         MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 & 0xfffe);
4580
4581         /* Update those 1-copy registers */
4582         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4583                           MDIO_AER_BLOCK_AER_REG, 0);
4584         /* Enable 1G MDIO (1-copy) */
4585         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4586                         MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4587                         &val16);
4588         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4589                          MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4590                          val16 & ~0x10);
4591
4592         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4593                         MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4594         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4595                          MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4596                          val16 & 0xff00);
4597
4598 }
4599
4600 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4601                                         struct link_params *params)
4602 {
4603         struct bnx2x *bp = params->bp;
4604         u16 val16;
4605         u32 lane;
4606         DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4607                        params->loopback_mode, phy->req_line_speed);
4608
4609         if (phy->req_line_speed < SPEED_10000) {
4610                 /* 10/100/1000 */
4611
4612                 /* Update those 1-copy registers */
4613                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4614                                   MDIO_AER_BLOCK_AER_REG, 0);
4615                 /* Enable 1G MDIO (1-copy) */
4616                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4617                                 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4618                                 &val16);
4619                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4620                                 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4621                                 val16 | 0x10);
4622                 /* Set 1G loopback based on lane (1-copy) */
4623                 lane = bnx2x_get_warpcore_lane(phy, params);
4624                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4625                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4626                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4627                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4628                                 val16 | (1<<lane));
4629
4630                 /* Switch back to 4-copy registers */
4631                 bnx2x_set_aer_mmd(params, phy);
4632         } else {
4633                 /* 10G & 20G */
4634                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4635                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4636                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4637                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
4638                                  0x4000);
4639
4640                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4641                                 MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4642                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4643                                 MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 | 0x1);
4644         }
4645 }
4646
4647
4648 void bnx2x_sync_link(struct link_params *params,
4649                            struct link_vars *vars)
4650 {
4651         struct bnx2x *bp = params->bp;
4652         u8 link_10g_plus;
4653         if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4654                 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4655         vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4656         if (vars->link_up) {
4657                 DP(NETIF_MSG_LINK, "phy link up\n");
4658
4659                 vars->phy_link_up = 1;
4660                 vars->duplex = DUPLEX_FULL;
4661                 switch (vars->link_status &
4662                         LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4663                 case LINK_10THD:
4664                         vars->duplex = DUPLEX_HALF;
4665                         /* Fall thru */
4666                 case LINK_10TFD:
4667                         vars->line_speed = SPEED_10;
4668                         break;
4669
4670                 case LINK_100TXHD:
4671                         vars->duplex = DUPLEX_HALF;
4672                         /* Fall thru */
4673                 case LINK_100T4:
4674                 case LINK_100TXFD:
4675                         vars->line_speed = SPEED_100;
4676                         break;
4677
4678                 case LINK_1000THD:
4679                         vars->duplex = DUPLEX_HALF;
4680                         /* Fall thru */
4681                 case LINK_1000TFD:
4682                         vars->line_speed = SPEED_1000;
4683                         break;
4684
4685                 case LINK_2500THD:
4686                         vars->duplex = DUPLEX_HALF;
4687                         /* Fall thru */
4688                 case LINK_2500TFD:
4689                         vars->line_speed = SPEED_2500;
4690                         break;
4691
4692                 case LINK_10GTFD:
4693                         vars->line_speed = SPEED_10000;
4694                         break;
4695                 case LINK_20GTFD:
4696                         vars->line_speed = SPEED_20000;
4697                         break;
4698                 default:
4699                         break;
4700                 }
4701                 vars->flow_ctrl = 0;
4702                 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4703                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4704
4705                 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4706                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4707
4708                 if (!vars->flow_ctrl)
4709                         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4710
4711                 if (vars->line_speed &&
4712                     ((vars->line_speed == SPEED_10) ||
4713                      (vars->line_speed == SPEED_100))) {
4714                         vars->phy_flags |= PHY_SGMII_FLAG;
4715                 } else {
4716                         vars->phy_flags &= ~PHY_SGMII_FLAG;
4717                 }
4718                 if (vars->line_speed &&
4719                     USES_WARPCORE(bp) &&
4720                     (vars->line_speed == SPEED_1000))
4721                         vars->phy_flags |= PHY_SGMII_FLAG;
4722                 /* anything 10 and over uses the bmac */
4723                 link_10g_plus = (vars->line_speed >= SPEED_10000);
4724
4725                 if (link_10g_plus) {
4726                         if (USES_WARPCORE(bp))
4727                                 vars->mac_type = MAC_TYPE_XMAC;
4728                         else
4729                                 vars->mac_type = MAC_TYPE_BMAC;
4730                 } else {
4731                         if (USES_WARPCORE(bp))
4732                                 vars->mac_type = MAC_TYPE_UMAC;
4733                         else
4734                                 vars->mac_type = MAC_TYPE_EMAC;
4735                 }
4736         } else { /* link down */
4737                 DP(NETIF_MSG_LINK, "phy link down\n");
4738
4739                 vars->phy_link_up = 0;
4740
4741                 vars->line_speed = 0;
4742                 vars->duplex = DUPLEX_FULL;
4743                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4744
4745                 /* indicate no mac active */
4746                 vars->mac_type = MAC_TYPE_NONE;
4747                 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4748                         vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4749                 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
4750                         vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
4751         }
4752 }
4753
4754 void bnx2x_link_status_update(struct link_params *params,
4755                               struct link_vars *vars)
4756 {
4757         struct bnx2x *bp = params->bp;
4758         u8 port = params->port;
4759         u32 sync_offset, media_types;
4760         /* Update PHY configuration */
4761         set_phy_vars(params, vars);
4762
4763         vars->link_status = REG_RD(bp, params->shmem_base +
4764                                    offsetof(struct shmem_region,
4765                                             port_mb[port].link_status));
4766
4767         vars->phy_flags = PHY_XGXS_FLAG;
4768         bnx2x_sync_link(params, vars);
4769         /* Sync media type */
4770         sync_offset = params->shmem_base +
4771                         offsetof(struct shmem_region,
4772                                  dev_info.port_hw_config[port].media_type);
4773         media_types = REG_RD(bp, sync_offset);
4774
4775         params->phy[INT_PHY].media_type =
4776                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4777                 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4778         params->phy[EXT_PHY1].media_type =
4779                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4780                 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4781         params->phy[EXT_PHY2].media_type =
4782                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4783                 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4784         DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4785
4786         /* Sync AEU offset */
4787         sync_offset = params->shmem_base +
4788                         offsetof(struct shmem_region,
4789                                  dev_info.port_hw_config[port].aeu_int_mask);
4790
4791         vars->aeu_int_mask = REG_RD(bp, sync_offset);
4792
4793         /* Sync PFC status */
4794         if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4795                 params->feature_config_flags |=
4796                                         FEATURE_CONFIG_PFC_ENABLED;
4797         else
4798                 params->feature_config_flags &=
4799                                         ~FEATURE_CONFIG_PFC_ENABLED;
4800
4801         DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x int_mask 0x%x\n",
4802                  vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4803         DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
4804                  vars->line_speed, vars->duplex, vars->flow_ctrl);
4805 }
4806
4807 static void bnx2x_set_master_ln(struct link_params *params,
4808                                 struct bnx2x_phy *phy)
4809 {
4810         struct bnx2x *bp = params->bp;
4811         u16 new_master_ln, ser_lane;
4812         ser_lane = ((params->lane_config &
4813                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4814                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4815
4816         /* set the master_ln for AN */
4817         CL22_RD_OVER_CL45(bp, phy,
4818                           MDIO_REG_BANK_XGXS_BLOCK2,
4819                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4820                           &new_master_ln);
4821
4822         CL22_WR_OVER_CL45(bp, phy,
4823                           MDIO_REG_BANK_XGXS_BLOCK2 ,
4824                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4825                           (new_master_ln | ser_lane));
4826 }
4827
4828 static int bnx2x_reset_unicore(struct link_params *params,
4829                                struct bnx2x_phy *phy,
4830                                u8 set_serdes)
4831 {
4832         struct bnx2x *bp = params->bp;
4833         u16 mii_control;
4834         u16 i;
4835         CL22_RD_OVER_CL45(bp, phy,
4836                           MDIO_REG_BANK_COMBO_IEEE0,
4837                           MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4838
4839         /* reset the unicore */
4840         CL22_WR_OVER_CL45(bp, phy,
4841                           MDIO_REG_BANK_COMBO_IEEE0,
4842                           MDIO_COMBO_IEEE0_MII_CONTROL,
4843                           (mii_control |
4844                            MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4845         if (set_serdes)
4846                 bnx2x_set_serdes_access(bp, params->port);
4847
4848         /* wait for the reset to self clear */
4849         for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4850                 udelay(5);
4851
4852                 /* the reset erased the previous bank value */
4853                 CL22_RD_OVER_CL45(bp, phy,
4854                                   MDIO_REG_BANK_COMBO_IEEE0,
4855                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4856                                   &mii_control);
4857
4858                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4859                         udelay(5);
4860                         return 0;
4861                 }
4862         }
4863
4864         netdev_err(bp->dev,  "Warning: PHY was not initialized,"
4865                               " Port %d\n",
4866                          params->port);
4867         DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4868         return -EINVAL;
4869
4870 }
4871
4872 static void bnx2x_set_swap_lanes(struct link_params *params,
4873                                  struct bnx2x_phy *phy)
4874 {
4875         struct bnx2x *bp = params->bp;
4876         /* Each two bits represents a lane number:
4877          * No swap is 0123 => 0x1b no need to enable the swap
4878          */
4879         u16 rx_lane_swap, tx_lane_swap;
4880
4881         rx_lane_swap = ((params->lane_config &
4882                          PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4883                         PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4884         tx_lane_swap = ((params->lane_config &
4885                          PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4886                         PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4887
4888         if (rx_lane_swap != 0x1b) {
4889                 CL22_WR_OVER_CL45(bp, phy,
4890                                   MDIO_REG_BANK_XGXS_BLOCK2,
4891                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4892                                   (rx_lane_swap |
4893                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4894                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4895         } else {
4896                 CL22_WR_OVER_CL45(bp, phy,
4897                                   MDIO_REG_BANK_XGXS_BLOCK2,
4898                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4899         }
4900
4901         if (tx_lane_swap != 0x1b) {
4902                 CL22_WR_OVER_CL45(bp, phy,
4903                                   MDIO_REG_BANK_XGXS_BLOCK2,
4904                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4905                                   (tx_lane_swap |
4906                                    MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4907         } else {
4908                 CL22_WR_OVER_CL45(bp, phy,
4909                                   MDIO_REG_BANK_XGXS_BLOCK2,
4910                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4911         }
4912 }
4913
4914 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4915                                          struct link_params *params)
4916 {
4917         struct bnx2x *bp = params->bp;
4918         u16 control2;
4919         CL22_RD_OVER_CL45(bp, phy,
4920                           MDIO_REG_BANK_SERDES_DIGITAL,
4921                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4922                           &control2);
4923         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4924                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4925         else
4926                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4927         DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4928                 phy->speed_cap_mask, control2);
4929         CL22_WR_OVER_CL45(bp, phy,
4930                           MDIO_REG_BANK_SERDES_DIGITAL,
4931                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4932                           control2);
4933
4934         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4935              (phy->speed_cap_mask &
4936                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4937                 DP(NETIF_MSG_LINK, "XGXS\n");
4938
4939                 CL22_WR_OVER_CL45(bp, phy,
4940                                  MDIO_REG_BANK_10G_PARALLEL_DETECT,
4941                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4942                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4943
4944                 CL22_RD_OVER_CL45(bp, phy,
4945                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4946                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4947                                   &control2);
4948
4949
4950                 control2 |=
4951                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4952
4953                 CL22_WR_OVER_CL45(bp, phy,
4954                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4955                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4956                                   control2);
4957
4958                 /* Disable parallel detection of HiG */
4959                 CL22_WR_OVER_CL45(bp, phy,
4960                                   MDIO_REG_BANK_XGXS_BLOCK2,
4961                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4962                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4963                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4964         }
4965 }
4966
4967 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
4968                               struct link_params *params,
4969                               struct link_vars *vars,
4970                               u8 enable_cl73)
4971 {
4972         struct bnx2x *bp = params->bp;
4973         u16 reg_val;
4974
4975         /* CL37 Autoneg */
4976         CL22_RD_OVER_CL45(bp, phy,
4977                           MDIO_REG_BANK_COMBO_IEEE0,
4978                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4979
4980         /* CL37 Autoneg Enabled */
4981         if (vars->line_speed == SPEED_AUTO_NEG)
4982                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4983         else /* CL37 Autoneg Disabled */
4984                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4985                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4986
4987         CL22_WR_OVER_CL45(bp, phy,
4988                           MDIO_REG_BANK_COMBO_IEEE0,
4989                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4990
4991         /* Enable/Disable Autodetection */
4992
4993         CL22_RD_OVER_CL45(bp, phy,
4994                           MDIO_REG_BANK_SERDES_DIGITAL,
4995                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
4996         reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
4997                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
4998         reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
4999         if (vars->line_speed == SPEED_AUTO_NEG)
5000                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5001         else
5002                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5003
5004         CL22_WR_OVER_CL45(bp, phy,
5005                           MDIO_REG_BANK_SERDES_DIGITAL,
5006                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
5007
5008         /* Enable TetonII and BAM autoneg */
5009         CL22_RD_OVER_CL45(bp, phy,
5010                           MDIO_REG_BANK_BAM_NEXT_PAGE,
5011                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5012                           &reg_val);
5013         if (vars->line_speed == SPEED_AUTO_NEG) {
5014                 /* Enable BAM aneg Mode and TetonII aneg Mode */
5015                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5016                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5017         } else {
5018                 /* TetonII and BAM Autoneg Disabled */
5019                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5020                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5021         }
5022         CL22_WR_OVER_CL45(bp, phy,
5023                           MDIO_REG_BANK_BAM_NEXT_PAGE,
5024                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5025                           reg_val);
5026
5027         if (enable_cl73) {
5028                 /* Enable Cl73 FSM status bits */
5029                 CL22_WR_OVER_CL45(bp, phy,
5030                                   MDIO_REG_BANK_CL73_USERB0,
5031                                   MDIO_CL73_USERB0_CL73_UCTRL,
5032                                   0xe);
5033
5034                 /* Enable BAM Station Manager*/
5035                 CL22_WR_OVER_CL45(bp, phy,
5036                         MDIO_REG_BANK_CL73_USERB0,
5037                         MDIO_CL73_USERB0_CL73_BAM_CTRL1,
5038                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
5039                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
5040                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
5041
5042                 /* Advertise CL73 link speeds */
5043                 CL22_RD_OVER_CL45(bp, phy,
5044                                   MDIO_REG_BANK_CL73_IEEEB1,
5045                                   MDIO_CL73_IEEEB1_AN_ADV2,
5046                                   &reg_val);
5047                 if (phy->speed_cap_mask &
5048                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5049                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
5050                 if (phy->speed_cap_mask &
5051                     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5052                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
5053
5054                 CL22_WR_OVER_CL45(bp, phy,
5055                                   MDIO_REG_BANK_CL73_IEEEB1,
5056                                   MDIO_CL73_IEEEB1_AN_ADV2,
5057                                   reg_val);
5058
5059                 /* CL73 Autoneg Enabled */
5060                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
5061
5062         } else /* CL73 Autoneg Disabled */
5063                 reg_val = 0;
5064
5065         CL22_WR_OVER_CL45(bp, phy,
5066                           MDIO_REG_BANK_CL73_IEEEB0,
5067                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
5068 }
5069
5070 /* program SerDes, forced speed */
5071 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
5072                                  struct link_params *params,
5073                                  struct link_vars *vars)
5074 {
5075         struct bnx2x *bp = params->bp;
5076         u16 reg_val;
5077
5078         /* program duplex, disable autoneg and sgmii*/
5079         CL22_RD_OVER_CL45(bp, phy,
5080                           MDIO_REG_BANK_COMBO_IEEE0,
5081                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
5082         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
5083                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5084                      MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
5085         if (phy->req_duplex == DUPLEX_FULL)
5086                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5087         CL22_WR_OVER_CL45(bp, phy,
5088                           MDIO_REG_BANK_COMBO_IEEE0,
5089                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5090
5091         /* Program speed
5092          *  - needed only if the speed is greater than 1G (2.5G or 10G)
5093          */
5094         CL22_RD_OVER_CL45(bp, phy,
5095                           MDIO_REG_BANK_SERDES_DIGITAL,
5096                           MDIO_SERDES_DIGITAL_MISC1, &reg_val);
5097         /* clearing the speed value before setting the right speed */
5098         DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5099
5100         reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
5101                      MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5102
5103         if (!((vars->line_speed == SPEED_1000) ||
5104               (vars->line_speed == SPEED_100) ||
5105               (vars->line_speed == SPEED_10))) {
5106
5107                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
5108                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5109                 if (vars->line_speed == SPEED_10000)
5110                         reg_val |=
5111                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5112         }
5113
5114         CL22_WR_OVER_CL45(bp, phy,
5115                           MDIO_REG_BANK_SERDES_DIGITAL,
5116                           MDIO_SERDES_DIGITAL_MISC1, reg_val);
5117
5118 }
5119
5120 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
5121                                               struct link_params *params)
5122 {
5123         struct bnx2x *bp = params->bp;
5124         u16 val = 0;
5125
5126         /* set extended capabilities */
5127         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
5128                 val |= MDIO_OVER_1G_UP1_2_5G;
5129         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5130                 val |= MDIO_OVER_1G_UP1_10G;
5131         CL22_WR_OVER_CL45(bp, phy,
5132                           MDIO_REG_BANK_OVER_1G,
5133                           MDIO_OVER_1G_UP1, val);
5134
5135         CL22_WR_OVER_CL45(bp, phy,
5136                           MDIO_REG_BANK_OVER_1G,
5137                           MDIO_OVER_1G_UP3, 0x400);
5138 }
5139
5140 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
5141                                               struct link_params *params,
5142                                               u16 ieee_fc)
5143 {
5144         struct bnx2x *bp = params->bp;
5145         u16 val;
5146         /* for AN, we are always publishing full duplex */
5147
5148         CL22_WR_OVER_CL45(bp, phy,
5149                           MDIO_REG_BANK_COMBO_IEEE0,
5150                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
5151         CL22_RD_OVER_CL45(bp, phy,
5152                           MDIO_REG_BANK_CL73_IEEEB1,
5153                           MDIO_CL73_IEEEB1_AN_ADV1, &val);
5154         val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
5155         val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
5156         CL22_WR_OVER_CL45(bp, phy,
5157                           MDIO_REG_BANK_CL73_IEEEB1,
5158                           MDIO_CL73_IEEEB1_AN_ADV1, val);
5159 }
5160
5161 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
5162                                   struct link_params *params,
5163                                   u8 enable_cl73)
5164 {
5165         struct bnx2x *bp = params->bp;
5166         u16 mii_control;
5167
5168         DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
5169         /* Enable and restart BAM/CL37 aneg */
5170
5171         if (enable_cl73) {
5172                 CL22_RD_OVER_CL45(bp, phy,
5173                                   MDIO_REG_BANK_CL73_IEEEB0,
5174                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5175                                   &mii_control);
5176
5177                 CL22_WR_OVER_CL45(bp, phy,
5178                                   MDIO_REG_BANK_CL73_IEEEB0,
5179                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5180                                   (mii_control |
5181                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5182                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5183         } else {
5184
5185                 CL22_RD_OVER_CL45(bp, phy,
5186                                   MDIO_REG_BANK_COMBO_IEEE0,
5187                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5188                                   &mii_control);
5189                 DP(NETIF_MSG_LINK,
5190                          "bnx2x_restart_autoneg mii_control before = 0x%x\n",
5191                          mii_control);
5192                 CL22_WR_OVER_CL45(bp, phy,
5193                                   MDIO_REG_BANK_COMBO_IEEE0,
5194                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5195                                   (mii_control |
5196                                    MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5197                                    MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
5198         }
5199 }
5200
5201 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5202                                            struct link_params *params,
5203                                            struct link_vars *vars)
5204 {
5205         struct bnx2x *bp = params->bp;
5206         u16 control1;
5207
5208         /* in SGMII mode, the unicore is always slave */
5209
5210         CL22_RD_OVER_CL45(bp, phy,
5211                           MDIO_REG_BANK_SERDES_DIGITAL,
5212                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5213                           &control1);
5214         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
5215         /* set sgmii mode (and not fiber) */
5216         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
5217                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5218                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
5219         CL22_WR_OVER_CL45(bp, phy,
5220                           MDIO_REG_BANK_SERDES_DIGITAL,
5221                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5222                           control1);
5223
5224         /* if forced speed */
5225         if (!(vars->line_speed == SPEED_AUTO_NEG)) {
5226                 /* set speed, disable autoneg */
5227                 u16 mii_control;
5228
5229                 CL22_RD_OVER_CL45(bp, phy,
5230                                   MDIO_REG_BANK_COMBO_IEEE0,
5231                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5232                                   &mii_control);
5233                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5234                                  MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5235                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5236
5237                 switch (vars->line_speed) {
5238                 case SPEED_100:
5239                         mii_control |=
5240                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5241                         break;
5242                 case SPEED_1000:
5243                         mii_control |=
5244                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5245                         break;
5246                 case SPEED_10:
5247                         /* there is nothing to set for 10M */
5248                         break;
5249                 default:
5250                         /* invalid speed for SGMII */
5251                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5252                                   vars->line_speed);
5253                         break;
5254                 }
5255
5256                 /* setting the full duplex */
5257                 if (phy->req_duplex == DUPLEX_FULL)
5258                         mii_control |=
5259                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5260                 CL22_WR_OVER_CL45(bp, phy,
5261                                   MDIO_REG_BANK_COMBO_IEEE0,
5262                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5263                                   mii_control);
5264
5265         } else { /* AN mode */
5266                 /* enable and restart AN */
5267                 bnx2x_restart_autoneg(phy, params, 0);
5268         }
5269 }
5270
5271 /* Link management
5272  */
5273 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
5274                                              struct link_params *params)
5275 {
5276         struct bnx2x *bp = params->bp;
5277         u16 pd_10g, status2_1000x;
5278         if (phy->req_line_speed != SPEED_AUTO_NEG)
5279                 return 0;
5280         CL22_RD_OVER_CL45(bp, phy,
5281                           MDIO_REG_BANK_SERDES_DIGITAL,
5282                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5283                           &status2_1000x);
5284         CL22_RD_OVER_CL45(bp, phy,
5285                           MDIO_REG_BANK_SERDES_DIGITAL,
5286                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5287                           &status2_1000x);
5288         if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5289                 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5290                          params->port);
5291                 return 1;
5292         }
5293
5294         CL22_RD_OVER_CL45(bp, phy,
5295                           MDIO_REG_BANK_10G_PARALLEL_DETECT,
5296                           MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5297                           &pd_10g);
5298
5299         if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5300                 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5301                          params->port);
5302                 return 1;
5303         }
5304         return 0;
5305 }
5306
5307 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy,
5308                                 struct link_params *params,
5309                                 struct link_vars *vars,
5310                                 u32 gp_status)
5311 {
5312         u16 ld_pause;   /* local driver */
5313         u16 lp_pause;   /* link partner */
5314         u16 pause_result;
5315         struct bnx2x *bp = params->bp;
5316         if ((gp_status &
5317              (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5318               MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5319             (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5320              MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5321
5322                 CL22_RD_OVER_CL45(bp, phy,
5323                                   MDIO_REG_BANK_CL73_IEEEB1,
5324                                   MDIO_CL73_IEEEB1_AN_ADV1,
5325                                   &ld_pause);
5326                 CL22_RD_OVER_CL45(bp, phy,
5327                                   MDIO_REG_BANK_CL73_IEEEB1,
5328                                   MDIO_CL73_IEEEB1_AN_LP_ADV1,
5329                                   &lp_pause);
5330                 pause_result = (ld_pause &
5331                                 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
5332                 pause_result |= (lp_pause &
5333                                  MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
5334                 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result);
5335         } else {
5336                 CL22_RD_OVER_CL45(bp, phy,
5337                                   MDIO_REG_BANK_COMBO_IEEE0,
5338                                   MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5339                                   &ld_pause);
5340                 CL22_RD_OVER_CL45(bp, phy,
5341                         MDIO_REG_BANK_COMBO_IEEE0,
5342                         MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5343                         &lp_pause);
5344                 pause_result = (ld_pause &
5345                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5346                 pause_result |= (lp_pause &
5347                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5348                 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result);
5349         }
5350         bnx2x_pause_resolve(vars, pause_result);
5351
5352 }
5353
5354 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5355                                     struct link_params *params,
5356                                     struct link_vars *vars,
5357                                     u32 gp_status)
5358 {
5359         struct bnx2x *bp = params->bp;
5360         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5361
5362         /* resolve from gp_status in case of AN complete and not sgmii */
5363         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
5364                 /* Update the advertised flow-controled of LD/LP in AN */
5365                 if (phy->req_line_speed == SPEED_AUTO_NEG)
5366                         bnx2x_update_adv_fc(phy, params, vars, gp_status);
5367                 /* But set the flow-control result as the requested one */
5368                 vars->flow_ctrl = phy->req_flow_ctrl;
5369         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
5370                 vars->flow_ctrl = params->req_fc_auto_adv;
5371         else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5372                  (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5373                 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5374                         vars->flow_ctrl = params->req_fc_auto_adv;
5375                         return;
5376                 }
5377                 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5378         }
5379         DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5380 }
5381
5382 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5383                                          struct link_params *params)
5384 {
5385         struct bnx2x *bp = params->bp;
5386         u16 rx_status, ustat_val, cl37_fsm_received;
5387         DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5388         /* Step 1: Make sure signal is detected */
5389         CL22_RD_OVER_CL45(bp, phy,
5390                           MDIO_REG_BANK_RX0,
5391                           MDIO_RX0_RX_STATUS,
5392                           &rx_status);
5393         if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5394             (MDIO_RX0_RX_STATUS_SIGDET)) {
5395                 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5396                              "rx_status(0x80b0) = 0x%x\n", rx_status);
5397                 CL22_WR_OVER_CL45(bp, phy,
5398                                   MDIO_REG_BANK_CL73_IEEEB0,
5399                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5400                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5401                 return;
5402         }
5403         /* Step 2: Check CL73 state machine */
5404         CL22_RD_OVER_CL45(bp, phy,
5405                           MDIO_REG_BANK_CL73_USERB0,
5406                           MDIO_CL73_USERB0_CL73_USTAT1,
5407                           &ustat_val);
5408         if ((ustat_val &
5409              (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5410               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5411             (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5412               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5413                 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5414                              "ustat_val(0x8371) = 0x%x\n", ustat_val);
5415                 return;
5416         }
5417         /* Step 3: Check CL37 Message Pages received to indicate LP
5418          * supports only CL37
5419          */
5420         CL22_RD_OVER_CL45(bp, phy,
5421                           MDIO_REG_BANK_REMOTE_PHY,
5422                           MDIO_REMOTE_PHY_MISC_RX_STATUS,
5423                           &cl37_fsm_received);
5424         if ((cl37_fsm_received &
5425              (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5426              MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5427             (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5428               MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5429                 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5430                              "misc_rx_status(0x8330) = 0x%x\n",
5431                          cl37_fsm_received);
5432                 return;
5433         }
5434         /* The combined cl37/cl73 fsm state information indicating that
5435          * we are connected to a device which does not support cl73, but
5436          * does support cl37 BAM. In this case we disable cl73 and
5437          * restart cl37 auto-neg
5438          */
5439
5440         /* Disable CL73 */
5441         CL22_WR_OVER_CL45(bp, phy,
5442                           MDIO_REG_BANK_CL73_IEEEB0,
5443                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5444                           0);
5445         /* Restart CL37 autoneg */
5446         bnx2x_restart_autoneg(phy, params, 0);
5447         DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5448 }
5449
5450 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5451                                   struct link_params *params,
5452                                   struct link_vars *vars,
5453                                   u32 gp_status)
5454 {
5455         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5456                 vars->link_status |=
5457                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5458
5459         if (bnx2x_direct_parallel_detect_used(phy, params))
5460                 vars->link_status |=
5461                         LINK_STATUS_PARALLEL_DETECTION_USED;
5462 }
5463 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5464                                      struct link_params *params,
5465                                       struct link_vars *vars,
5466                                       u16 is_link_up,
5467                                       u16 speed_mask,
5468                                       u16 is_duplex)
5469 {
5470         struct bnx2x *bp = params->bp;
5471         if (phy->req_line_speed == SPEED_AUTO_NEG)
5472                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5473         if (is_link_up) {
5474                 DP(NETIF_MSG_LINK, "phy link up\n");
5475
5476                 vars->phy_link_up = 1;
5477                 vars->link_status |= LINK_STATUS_LINK_UP;
5478
5479                 switch (speed_mask) {
5480                 case GP_STATUS_10M:
5481                         vars->line_speed = SPEED_10;
5482                         if (vars->duplex == DUPLEX_FULL)
5483                                 vars->link_status |= LINK_10TFD;
5484                         else
5485                                 vars->link_status |= LINK_10THD;
5486                         break;
5487
5488                 case GP_STATUS_100M:
5489                         vars->line_speed = SPEED_100;
5490                         if (vars->duplex == DUPLEX_FULL)
5491                                 vars->link_status |= LINK_100TXFD;
5492                         else
5493                                 vars->link_status |= LINK_100TXHD;
5494                         break;
5495
5496                 case GP_STATUS_1G:
5497                 case GP_STATUS_1G_KX:
5498                         vars->line_speed = SPEED_1000;
5499                         if (vars->duplex == DUPLEX_FULL)
5500                                 vars->link_status |= LINK_1000TFD;
5501                         else
5502                                 vars->link_status |= LINK_1000THD;
5503                         break;
5504
5505                 case GP_STATUS_2_5G:
5506                         vars->line_speed = SPEED_2500;
5507                         if (vars->duplex == DUPLEX_FULL)
5508                                 vars->link_status |= LINK_2500TFD;
5509                         else
5510                                 vars->link_status |= LINK_2500THD;
5511                         break;
5512
5513                 case GP_STATUS_5G:
5514                 case GP_STATUS_6G:
5515                         DP(NETIF_MSG_LINK,
5516                                  "link speed unsupported  gp_status 0x%x\n",
5517                                   speed_mask);
5518                         return -EINVAL;
5519
5520                 case GP_STATUS_10G_KX4:
5521                 case GP_STATUS_10G_HIG:
5522                 case GP_STATUS_10G_CX4:
5523                 case GP_STATUS_10G_KR:
5524                 case GP_STATUS_10G_SFI:
5525                 case GP_STATUS_10G_XFI:
5526                         vars->line_speed = SPEED_10000;
5527                         vars->link_status |= LINK_10GTFD;
5528                         break;
5529                 case GP_STATUS_20G_DXGXS:
5530                         vars->line_speed = SPEED_20000;
5531                         vars->link_status |= LINK_20GTFD;
5532                         break;
5533                 default:
5534                         DP(NETIF_MSG_LINK,
5535                                   "link speed unsupported gp_status 0x%x\n",
5536                                   speed_mask);
5537                         return -EINVAL;
5538                 }
5539         } else { /* link_down */
5540                 DP(NETIF_MSG_LINK, "phy link down\n");
5541
5542                 vars->phy_link_up = 0;
5543
5544                 vars->duplex = DUPLEX_FULL;
5545                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5546                 vars->mac_type = MAC_TYPE_NONE;
5547         }
5548         DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5549                     vars->phy_link_up, vars->line_speed);
5550         return 0;
5551 }
5552
5553 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5554                                       struct link_params *params,
5555                                       struct link_vars *vars)
5556 {
5557         struct bnx2x *bp = params->bp;
5558
5559         u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5560         int rc = 0;
5561
5562         /* Read gp_status */
5563         CL22_RD_OVER_CL45(bp, phy,
5564                           MDIO_REG_BANK_GP_STATUS,
5565                           MDIO_GP_STATUS_TOP_AN_STATUS1,
5566                           &gp_status);
5567         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5568                 duplex = DUPLEX_FULL;
5569         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5570                 link_up = 1;
5571         speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5572         DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5573                        gp_status, link_up, speed_mask);
5574         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5575                                          duplex);
5576         if (rc == -EINVAL)
5577                 return rc;
5578
5579         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5580                 if (SINGLE_MEDIA_DIRECT(params)) {
5581                         bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5582                         if (phy->req_line_speed == SPEED_AUTO_NEG)
5583                                 bnx2x_xgxs_an_resolve(phy, params, vars,
5584                                                       gp_status);
5585                 }
5586         } else { /* link_down */
5587                 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5588                     SINGLE_MEDIA_DIRECT(params)) {
5589                         /* Check signal is detected */
5590                         bnx2x_check_fallback_to_cl37(phy, params);
5591                 }
5592         }
5593
5594         /* Read LP advertised speeds*/
5595         if (SINGLE_MEDIA_DIRECT(params) &&
5596             (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
5597                 u16 val;
5598
5599                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1,
5600                                   MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
5601
5602                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5603                         vars->link_status |=
5604                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5605                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5606                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5607                         vars->link_status |=
5608                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5609
5610                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G,
5611                                   MDIO_OVER_1G_LP_UP1, &val);
5612
5613                 if (val & MDIO_OVER_1G_UP1_2_5G)
5614                         vars->link_status |=
5615                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5616                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5617                         vars->link_status |=
5618                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5619         }
5620
5621         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5622                    vars->duplex, vars->flow_ctrl, vars->link_status);
5623         return rc;
5624 }
5625
5626 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5627                                      struct link_params *params,
5628                                      struct link_vars *vars)
5629 {
5630         struct bnx2x *bp = params->bp;
5631         u8 lane;
5632         u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5633         int rc = 0;
5634         lane = bnx2x_get_warpcore_lane(phy, params);
5635         /* Read gp_status */
5636         if (phy->req_line_speed > SPEED_10000) {
5637                 u16 temp_link_up;
5638                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5639                                 1, &temp_link_up);
5640                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5641                                 1, &link_up);
5642                 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5643                                temp_link_up, link_up);
5644                 link_up &= (1<<2);
5645                 if (link_up)
5646                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5647         } else {
5648                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5649                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);
5650                 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5651                 /* Check for either KR or generic link up. */
5652                 gp_status1 = ((gp_status1 >> 8) & 0xf) |
5653                         ((gp_status1 >> 12) & 0xf);
5654                 link_up = gp_status1 & (1 << lane);
5655                 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5656                         u16 pd, gp_status4;
5657                         if (phy->req_line_speed == SPEED_AUTO_NEG) {
5658                                 /* Check Autoneg complete */
5659                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5660                                                 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5661                                                 &gp_status4);
5662                                 if (gp_status4 & ((1<<12)<<lane))
5663                                         vars->link_status |=
5664                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5665
5666                                 /* Check parallel detect used */
5667                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5668                                                 MDIO_WC_REG_PAR_DET_10G_STATUS,
5669                                                 &pd);
5670                                 if (pd & (1<<15))
5671                                         vars->link_status |=
5672                                         LINK_STATUS_PARALLEL_DETECTION_USED;
5673                         }
5674                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5675                 }
5676         }
5677
5678         if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
5679             SINGLE_MEDIA_DIRECT(params)) {
5680                 u16 val;
5681
5682                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5683                                 MDIO_AN_REG_LP_AUTO_NEG2, &val);
5684
5685                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5686                         vars->link_status |=
5687                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5688                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5689                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5690                         vars->link_status |=
5691                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5692
5693                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5694                                 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
5695
5696                 if (val & MDIO_OVER_1G_UP1_2_5G)
5697                         vars->link_status |=
5698                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5699                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5700                         vars->link_status |=
5701                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5702
5703         }
5704
5705
5706         if (lane < 2) {
5707                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5708                                 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5709         } else {
5710                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5711                                 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5712         }
5713         DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5714
5715         if ((lane & 1) == 0)
5716                 gp_speed <<= 8;
5717         gp_speed &= 0x3f00;
5718
5719
5720         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5721                                          duplex);
5722
5723         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5724                    vars->duplex, vars->flow_ctrl, vars->link_status);
5725         return rc;
5726 }
5727 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5728 {
5729         struct bnx2x *bp = params->bp;
5730         struct bnx2x_phy *phy = &params->phy[INT_PHY];
5731         u16 lp_up2;
5732         u16 tx_driver;
5733         u16 bank;
5734
5735         /* read precomp */
5736         CL22_RD_OVER_CL45(bp, phy,
5737                           MDIO_REG_BANK_OVER_1G,
5738                           MDIO_OVER_1G_LP_UP2, &lp_up2);
5739
5740         /* bits [10:7] at lp_up2, positioned at [15:12] */
5741         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5742                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5743                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5744
5745         if (lp_up2 == 0)
5746                 return;
5747
5748         for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5749               bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5750                 CL22_RD_OVER_CL45(bp, phy,
5751                                   bank,
5752                                   MDIO_TX0_TX_DRIVER, &tx_driver);
5753
5754                 /* replace tx_driver bits [15:12] */
5755                 if (lp_up2 !=
5756                     (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5757                         tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5758                         tx_driver |= lp_up2;
5759                         CL22_WR_OVER_CL45(bp, phy,
5760                                           bank,
5761                                           MDIO_TX0_TX_DRIVER, tx_driver);
5762                 }
5763         }
5764 }
5765
5766 static int bnx2x_emac_program(struct link_params *params,
5767                               struct link_vars *vars)
5768 {
5769         struct bnx2x *bp = params->bp;
5770         u8 port = params->port;
5771         u16 mode = 0;
5772
5773         DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5774         bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5775                        EMAC_REG_EMAC_MODE,
5776                        (EMAC_MODE_25G_MODE |
5777                         EMAC_MODE_PORT_MII_10M |
5778                         EMAC_MODE_HALF_DUPLEX));
5779         switch (vars->line_speed) {
5780         case SPEED_10:
5781                 mode |= EMAC_MODE_PORT_MII_10M;
5782                 break;
5783
5784         case SPEED_100:
5785                 mode |= EMAC_MODE_PORT_MII;
5786                 break;
5787
5788         case SPEED_1000:
5789                 mode |= EMAC_MODE_PORT_GMII;
5790                 break;
5791
5792         case SPEED_2500:
5793                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5794                 break;
5795
5796         default:
5797                 /* 10G not valid for EMAC */
5798                 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5799                            vars->line_speed);
5800                 return -EINVAL;
5801         }
5802
5803         if (vars->duplex == DUPLEX_HALF)
5804                 mode |= EMAC_MODE_HALF_DUPLEX;
5805         bnx2x_bits_en(bp,
5806                       GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5807                       mode);
5808
5809         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5810         return 0;
5811 }
5812
5813 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5814                                   struct link_params *params)
5815 {
5816
5817         u16 bank, i = 0;
5818         struct bnx2x *bp = params->bp;
5819
5820         for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5821               bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5822                         CL22_WR_OVER_CL45(bp, phy,
5823                                           bank,
5824                                           MDIO_RX0_RX_EQ_BOOST,
5825                                           phy->rx_preemphasis[i]);
5826         }
5827
5828         for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5829                       bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5830                         CL22_WR_OVER_CL45(bp, phy,
5831                                           bank,
5832                                           MDIO_TX0_TX_DRIVER,
5833                                           phy->tx_preemphasis[i]);
5834         }
5835 }
5836
5837 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5838                                    struct link_params *params,
5839                                    struct link_vars *vars)
5840 {
5841         struct bnx2x *bp = params->bp;
5842         u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5843                           (params->loopback_mode == LOOPBACK_XGXS));
5844         if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5845                 if (SINGLE_MEDIA_DIRECT(params) &&
5846                     (params->feature_config_flags &
5847                      FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5848                         bnx2x_set_preemphasis(phy, params);
5849
5850                 /* forced speed requested? */
5851                 if (vars->line_speed != SPEED_AUTO_NEG ||
5852                     (SINGLE_MEDIA_DIRECT(params) &&
5853                      params->loopback_mode == LOOPBACK_EXT)) {
5854                         DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5855
5856                         /* disable autoneg */
5857                         bnx2x_set_autoneg(phy, params, vars, 0);
5858
5859                         /* program speed and duplex */
5860                         bnx2x_program_serdes(phy, params, vars);
5861
5862                 } else { /* AN_mode */
5863                         DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5864
5865                         /* AN enabled */
5866                         bnx2x_set_brcm_cl37_advertisement(phy, params);
5867
5868                         /* program duplex & pause advertisement (for aneg) */
5869                         bnx2x_set_ieee_aneg_advertisement(phy, params,
5870                                                           vars->ieee_fc);
5871
5872                         /* enable autoneg */
5873                         bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5874
5875                         /* enable and restart AN */
5876                         bnx2x_restart_autoneg(phy, params, enable_cl73);
5877                 }
5878
5879         } else { /* SGMII mode */
5880                 DP(NETIF_MSG_LINK, "SGMII\n");
5881
5882                 bnx2x_initialize_sgmii_process(phy, params, vars);
5883         }
5884 }
5885
5886 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5887                           struct link_params *params,
5888                           struct link_vars *vars)
5889 {
5890         int rc;
5891         vars->phy_flags |= PHY_XGXS_FLAG;
5892         if ((phy->req_line_speed &&
5893              ((phy->req_line_speed == SPEED_100) ||
5894               (phy->req_line_speed == SPEED_10))) ||
5895             (!phy->req_line_speed &&
5896              (phy->speed_cap_mask >=
5897               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5898              (phy->speed_cap_mask <
5899               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5900             (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5901                 vars->phy_flags |= PHY_SGMII_FLAG;
5902         else
5903                 vars->phy_flags &= ~PHY_SGMII_FLAG;
5904
5905         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5906         bnx2x_set_aer_mmd(params, phy);
5907         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5908                 bnx2x_set_master_ln(params, phy);
5909
5910         rc = bnx2x_reset_unicore(params, phy, 0);
5911         /* reset the SerDes and wait for reset bit return low */
5912         if (rc != 0)
5913                 return rc;
5914
5915         bnx2x_set_aer_mmd(params, phy);
5916         /* setting the masterLn_def again after the reset */
5917         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5918                 bnx2x_set_master_ln(params, phy);
5919                 bnx2x_set_swap_lanes(params, phy);
5920         }
5921
5922         return rc;
5923 }
5924
5925 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
5926                                      struct bnx2x_phy *phy,
5927                                      struct link_params *params)
5928 {
5929         u16 cnt, ctrl;
5930         /* Wait for soft reset to get cleared up to 1 sec */
5931         for (cnt = 0; cnt < 1000; cnt++) {
5932                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
5933                         bnx2x_cl22_read(bp, phy,
5934                                 MDIO_PMA_REG_CTRL, &ctrl);
5935                 else
5936                         bnx2x_cl45_read(bp, phy,
5937                                 MDIO_PMA_DEVAD,
5938                                 MDIO_PMA_REG_CTRL, &ctrl);
5939                 if (!(ctrl & (1<<15)))
5940                         break;
5941                 msleep(1);
5942         }
5943
5944         if (cnt == 1000)
5945                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
5946                                       " Port %d\n",
5947                          params->port);
5948         DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
5949         return cnt;
5950 }
5951
5952 static void bnx2x_link_int_enable(struct link_params *params)
5953 {
5954         u8 port = params->port;
5955         u32 mask;
5956         struct bnx2x *bp = params->bp;
5957
5958         /* Setting the status to report on link up for either XGXS or SerDes */
5959         if (CHIP_IS_E3(bp)) {
5960                 mask = NIG_MASK_XGXS0_LINK_STATUS;
5961                 if (!(SINGLE_MEDIA_DIRECT(params)))
5962                         mask |= NIG_MASK_MI_INT;
5963         } else if (params->switch_cfg == SWITCH_CFG_10G) {
5964                 mask = (NIG_MASK_XGXS0_LINK10G |
5965                         NIG_MASK_XGXS0_LINK_STATUS);
5966                 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5967                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5968                         params->phy[INT_PHY].type !=
5969                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5970                         mask |= NIG_MASK_MI_INT;
5971                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
5972                 }
5973
5974         } else { /* SerDes */
5975                 mask = NIG_MASK_SERDES0_LINK_STATUS;
5976                 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
5977                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5978                         params->phy[INT_PHY].type !=
5979                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
5980                         mask |= NIG_MASK_MI_INT;
5981                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
5982                 }
5983         }
5984         bnx2x_bits_en(bp,
5985                       NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
5986                       mask);
5987
5988         DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
5989                  (params->switch_cfg == SWITCH_CFG_10G),
5990                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
5991         DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
5992                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
5993                  REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
5994                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
5995         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
5996            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
5997            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
5998 }
5999
6000 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
6001                                      u8 exp_mi_int)
6002 {
6003         u32 latch_status = 0;
6004
6005         /* Disable the MI INT ( external phy int ) by writing 1 to the
6006          * status register. Link down indication is high-active-signal,
6007          * so in this case we need to write the status to clear the XOR
6008          */
6009         /* Read Latched signals */
6010         latch_status = REG_RD(bp,
6011                                     NIG_REG_LATCH_STATUS_0 + port*8);
6012         DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
6013         /* Handle only those with latched-signal=up.*/
6014         if (exp_mi_int)
6015                 bnx2x_bits_en(bp,
6016                               NIG_REG_STATUS_INTERRUPT_PORT0
6017                               + port*4,
6018                               NIG_STATUS_EMAC0_MI_INT);
6019         else
6020                 bnx2x_bits_dis(bp,
6021                                NIG_REG_STATUS_INTERRUPT_PORT0
6022                                + port*4,
6023                                NIG_STATUS_EMAC0_MI_INT);
6024
6025         if (latch_status & 1) {
6026
6027                 /* For all latched-signal=up : Re-Arm Latch signals */
6028                 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
6029                        (latch_status & 0xfffe) | (latch_status & 1));
6030         }
6031         /* For all latched-signal=up,Write original_signal to status */
6032 }
6033
6034 static void bnx2x_link_int_ack(struct link_params *params,
6035                                struct link_vars *vars, u8 is_10g_plus)
6036 {
6037         struct bnx2x *bp = params->bp;
6038         u8 port = params->port;
6039         u32 mask;
6040         /* First reset all status we assume only one line will be
6041          * change at a time
6042          */
6043         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6044                        (NIG_STATUS_XGXS0_LINK10G |
6045                         NIG_STATUS_XGXS0_LINK_STATUS |
6046                         NIG_STATUS_SERDES0_LINK_STATUS));
6047         if (vars->phy_link_up) {
6048                 if (USES_WARPCORE(bp))
6049                         mask = NIG_STATUS_XGXS0_LINK_STATUS;
6050                 else {
6051                         if (is_10g_plus)
6052                                 mask = NIG_STATUS_XGXS0_LINK10G;
6053                         else if (params->switch_cfg == SWITCH_CFG_10G) {
6054                                 /* Disable the link interrupt by writing 1 to
6055                                  * the relevant lane in the status register
6056                                  */
6057                                 u32 ser_lane =
6058                                         ((params->lane_config &
6059                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6060                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
6061                                 mask = ((1 << ser_lane) <<
6062                                        NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
6063                         } else
6064                                 mask = NIG_STATUS_SERDES0_LINK_STATUS;
6065                 }
6066                 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
6067                                mask);
6068                 bnx2x_bits_en(bp,
6069                               NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6070                               mask);
6071         }
6072 }
6073
6074 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
6075 {
6076         u8 *str_ptr = str;
6077         u32 mask = 0xf0000000;
6078         u8 shift = 8*4;
6079         u8 digit;
6080         u8 remove_leading_zeros = 1;
6081         if (*len < 10) {
6082                 /* Need more than 10chars for this format */
6083                 *str_ptr = '\0';
6084                 (*len)--;
6085                 return -EINVAL;
6086         }
6087         while (shift > 0) {
6088
6089                 shift -= 4;
6090                 digit = ((num & mask) >> shift);
6091                 if (digit == 0 && remove_leading_zeros) {
6092                         mask = mask >> 4;
6093                         continue;
6094                 } else if (digit < 0xa)
6095                         *str_ptr = digit + '0';
6096                 else
6097                         *str_ptr = digit - 0xa + 'a';
6098                 remove_leading_zeros = 0;
6099                 str_ptr++;
6100                 (*len)--;
6101                 mask = mask >> 4;
6102                 if (shift == 4*4) {
6103                         *str_ptr = '.';
6104                         str_ptr++;
6105                         (*len)--;
6106                         remove_leading_zeros = 1;
6107                 }
6108         }
6109         return 0;
6110 }
6111
6112
6113 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6114 {
6115         str[0] = '\0';
6116         (*len)--;
6117         return 0;
6118 }
6119
6120 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
6121                                  u16 len)
6122 {
6123         struct bnx2x *bp;
6124         u32 spirom_ver = 0;
6125         int status = 0;
6126         u8 *ver_p = version;
6127         u16 remain_len = len;
6128         if (version == NULL || params == NULL)
6129                 return -EINVAL;
6130         bp = params->bp;
6131
6132         /* Extract first external phy*/
6133         version[0] = '\0';
6134         spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
6135
6136         if (params->phy[EXT_PHY1].format_fw_ver) {
6137                 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
6138                                                               ver_p,
6139                                                               &remain_len);
6140                 ver_p += (len - remain_len);
6141         }
6142         if ((params->num_phys == MAX_PHYS) &&
6143             (params->phy[EXT_PHY2].ver_addr != 0)) {
6144                 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
6145                 if (params->phy[EXT_PHY2].format_fw_ver) {
6146                         *ver_p = '/';
6147                         ver_p++;
6148                         remain_len--;
6149                         status |= params->phy[EXT_PHY2].format_fw_ver(
6150                                 spirom_ver,
6151                                 ver_p,
6152                                 &remain_len);
6153                         ver_p = version + (len - remain_len);
6154                 }
6155         }
6156         *ver_p = '\0';
6157         return status;
6158 }
6159
6160 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
6161                                     struct link_params *params)
6162 {
6163         u8 port = params->port;
6164         struct bnx2x *bp = params->bp;
6165
6166         if (phy->req_line_speed != SPEED_1000) {
6167                 u32 md_devad = 0;
6168
6169                 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
6170
6171                 if (!CHIP_IS_E3(bp)) {
6172                         /* change the uni_phy_addr in the nig */
6173                         md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
6174                                                port*0x18));
6175
6176                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6177                                0x5);
6178                 }
6179
6180                 bnx2x_cl45_write(bp, phy,
6181                                  5,
6182                                  (MDIO_REG_BANK_AER_BLOCK +
6183                                   (MDIO_AER_BLOCK_AER_REG & 0xf)),
6184                                  0x2800);
6185
6186                 bnx2x_cl45_write(bp, phy,
6187                                  5,
6188                                  (MDIO_REG_BANK_CL73_IEEEB0 +
6189                                   (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
6190                                  0x6041);
6191                 msleep(200);
6192                 /* set aer mmd back */
6193                 bnx2x_set_aer_mmd(params, phy);
6194
6195                 if (!CHIP_IS_E3(bp)) {
6196                         /* and md_devad */
6197                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6198                                md_devad);
6199                 }
6200         } else {
6201                 u16 mii_ctrl;
6202                 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
6203                 bnx2x_cl45_read(bp, phy, 5,
6204                                 (MDIO_REG_BANK_COMBO_IEEE0 +
6205                                 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6206                                 &mii_ctrl);
6207                 bnx2x_cl45_write(bp, phy, 5,
6208                                  (MDIO_REG_BANK_COMBO_IEEE0 +
6209                                  (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6210                                  mii_ctrl |
6211                                  MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6212         }
6213 }
6214
6215 int bnx2x_set_led(struct link_params *params,
6216                   struct link_vars *vars, u8 mode, u32 speed)
6217 {
6218         u8 port = params->port;
6219         u16 hw_led_mode = params->hw_led_mode;
6220         int rc = 0;
6221         u8 phy_idx;
6222         u32 tmp;
6223         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6224         struct bnx2x *bp = params->bp;
6225         DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
6226         DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
6227                  speed, hw_led_mode);
6228         /* In case */
6229         for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
6230                 if (params->phy[phy_idx].set_link_led) {
6231                         params->phy[phy_idx].set_link_led(
6232                                 &params->phy[phy_idx], params, mode);
6233                 }
6234         }
6235
6236         switch (mode) {
6237         case LED_MODE_FRONT_PANEL_OFF:
6238         case LED_MODE_OFF:
6239                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
6240                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6241                        SHARED_HW_CFG_LED_MAC1);
6242
6243                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6244                 if (params->phy[EXT_PHY1].type ==
6245                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6246                         tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
6247                                 EMAC_LED_100MB_OVERRIDE |
6248                                 EMAC_LED_10MB_OVERRIDE);
6249                 else
6250                         tmp |= EMAC_LED_OVERRIDE;
6251
6252                 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp);
6253                 break;
6254
6255         case LED_MODE_OPER:
6256                 /* For all other phys, OPER mode is same as ON, so in case
6257                  * link is down, do nothing
6258                  */
6259                 if (!vars->link_up)
6260                         break;
6261         case LED_MODE_ON:
6262                 if (((params->phy[EXT_PHY1].type ==
6263                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6264                          (params->phy[EXT_PHY1].type ==
6265                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6266                     CHIP_IS_E2(bp) && params->num_phys == 2) {
6267                         /* This is a work-around for E2+8727 Configurations */
6268                         if (mode == LED_MODE_ON ||
6269                                 speed == SPEED_10000){
6270                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6271                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6272
6273                                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6274                                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6275                                         (tmp | EMAC_LED_OVERRIDE));
6276                                 /* Return here without enabling traffic
6277                                  * LED blink and setting rate in ON mode.
6278                                  * In oper mode, enabling LED blink
6279                                  * and setting rate is needed.
6280                                  */
6281                                 if (mode == LED_MODE_ON)
6282                                         return rc;
6283                         }
6284                 } else if (SINGLE_MEDIA_DIRECT(params)) {
6285                         /* This is a work-around for HW issue found when link
6286                          * is up in CL73
6287                          */
6288                         if ((!CHIP_IS_E3(bp)) ||
6289                             (CHIP_IS_E3(bp) &&
6290                              mode == LED_MODE_ON))
6291                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6292
6293                         if (CHIP_IS_E1x(bp) ||
6294                             CHIP_IS_E2(bp) ||
6295                             (mode == LED_MODE_ON))
6296                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6297                         else
6298                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6299                                        hw_led_mode);
6300                 } else if ((params->phy[EXT_PHY1].type ==
6301                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6302                            (mode == LED_MODE_ON)) {
6303                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6304                         tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6305                         EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp |
6306                                 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE);
6307                         /* Break here; otherwise, it'll disable the
6308                          * intended override.
6309                          */
6310                         break;
6311                 } else
6312                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6313                                hw_led_mode);
6314
6315                 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
6316                 /* Set blinking rate to ~15.9Hz */
6317                 if (CHIP_IS_E3(bp))
6318                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6319                                LED_BLINK_RATE_VAL_E3);
6320                 else
6321                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6322                                LED_BLINK_RATE_VAL_E1X_E2);
6323                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
6324                        port*4, 1);
6325                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6326                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6327                         (tmp & (~EMAC_LED_OVERRIDE)));
6328
6329                 if (CHIP_IS_E1(bp) &&
6330                     ((speed == SPEED_2500) ||
6331                      (speed == SPEED_1000) ||
6332                      (speed == SPEED_100) ||
6333                      (speed == SPEED_10))) {
6334                         /* For speeds less than 10G LED scheme is different */
6335                         REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
6336                                + port*4, 1);
6337                         REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
6338                                port*4, 0);
6339                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
6340                                port*4, 1);
6341                 }
6342                 break;
6343
6344         default:
6345                 rc = -EINVAL;
6346                 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
6347                          mode);
6348                 break;
6349         }
6350         return rc;
6351
6352 }
6353
6354 /* This function comes to reflect the actual link state read DIRECTLY from the
6355  * HW
6356  */
6357 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
6358                     u8 is_serdes)
6359 {
6360         struct bnx2x *bp = params->bp;
6361         u16 gp_status = 0, phy_index = 0;
6362         u8 ext_phy_link_up = 0, serdes_phy_type;
6363         struct link_vars temp_vars;
6364         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
6365
6366         if (CHIP_IS_E3(bp)) {
6367                 u16 link_up;
6368                 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6369                     > SPEED_10000) {
6370                         /* Check 20G link */
6371                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6372                                         1, &link_up);
6373                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6374                                         1, &link_up);
6375                         link_up &= (1<<2);
6376                 } else {
6377                         /* Check 10G link and below*/
6378                         u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6379                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6380                                         MDIO_WC_REG_GP2_STATUS_GP_2_1,
6381                                         &gp_status);
6382                         gp_status = ((gp_status >> 8) & 0xf) |
6383                                 ((gp_status >> 12) & 0xf);
6384                         link_up = gp_status & (1 << lane);
6385                 }
6386                 if (!link_up)
6387                         return -ESRCH;
6388         } else {
6389                 CL22_RD_OVER_CL45(bp, int_phy,
6390                           MDIO_REG_BANK_GP_STATUS,
6391                           MDIO_GP_STATUS_TOP_AN_STATUS1,
6392                           &gp_status);
6393         /* link is up only if both local phy and external phy are up */
6394         if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6395                 return -ESRCH;
6396         }
6397         /* In XGXS loopback mode, do not check external PHY */
6398         if (params->loopback_mode == LOOPBACK_XGXS)
6399                 return 0;
6400
6401         switch (params->num_phys) {
6402         case 1:
6403                 /* No external PHY */
6404                 return 0;
6405         case 2:
6406                 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6407                         &params->phy[EXT_PHY1],
6408                         params, &temp_vars);
6409                 break;
6410         case 3: /* Dual Media */
6411                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6412                       phy_index++) {
6413                         serdes_phy_type = ((params->phy[phy_index].media_type ==
6414                                             ETH_PHY_SFP_FIBER) ||
6415                                            (params->phy[phy_index].media_type ==
6416                                             ETH_PHY_XFP_FIBER) ||
6417                                            (params->phy[phy_index].media_type ==
6418                                             ETH_PHY_DA_TWINAX));
6419
6420                         if (is_serdes != serdes_phy_type)
6421                                 continue;
6422                         if (params->phy[phy_index].read_status) {
6423                                 ext_phy_link_up |=
6424                                         params->phy[phy_index].read_status(
6425                                                 &params->phy[phy_index],
6426                                                 params, &temp_vars);
6427                         }
6428                 }
6429                 break;
6430         }
6431         if (ext_phy_link_up)
6432                 return 0;
6433         return -ESRCH;
6434 }
6435
6436 static int bnx2x_link_initialize(struct link_params *params,
6437                                  struct link_vars *vars)
6438 {
6439         int rc = 0;
6440         u8 phy_index, non_ext_phy;
6441         struct bnx2x *bp = params->bp;
6442         /* In case of external phy existence, the line speed would be the
6443          * line speed linked up by the external phy. In case it is direct
6444          * only, then the line_speed during initialization will be
6445          * equal to the req_line_speed
6446          */
6447         vars->line_speed = params->phy[INT_PHY].req_line_speed;
6448
6449         /* Initialize the internal phy in case this is a direct board
6450          * (no external phys), or this board has external phy which requires
6451          * to first.
6452          */
6453         if (!USES_WARPCORE(bp))
6454                 bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
6455         /* init ext phy and enable link state int */
6456         non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6457                        (params->loopback_mode == LOOPBACK_XGXS));
6458
6459         if (non_ext_phy ||
6460             (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6461             (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6462                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
6463                 if (vars->line_speed == SPEED_AUTO_NEG &&
6464                     (CHIP_IS_E1x(bp) ||
6465                      CHIP_IS_E2(bp)))
6466                         bnx2x_set_parallel_detection(phy, params);
6467                         if (params->phy[INT_PHY].config_init)
6468                                 params->phy[INT_PHY].config_init(phy,
6469                                                                  params,
6470                                                                  vars);
6471         }
6472
6473         /* Init external phy*/
6474         if (non_ext_phy) {
6475                 if (params->phy[INT_PHY].supported &
6476                     SUPPORTED_FIBRE)
6477                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6478         } else {
6479                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6480                       phy_index++) {
6481                         /* No need to initialize second phy in case of first
6482                          * phy only selection. In case of second phy, we do
6483                          * need to initialize the first phy, since they are
6484                          * connected.
6485                          */
6486                         if (params->phy[phy_index].supported &
6487                             SUPPORTED_FIBRE)
6488                                 vars->link_status |= LINK_STATUS_SERDES_LINK;
6489
6490                         if (phy_index == EXT_PHY2 &&
6491                             (bnx2x_phy_selection(params) ==
6492                              PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6493                                 DP(NETIF_MSG_LINK,
6494                                    "Not initializing second phy\n");
6495                                 continue;
6496                         }
6497                         params->phy[phy_index].config_init(
6498                                 &params->phy[phy_index],
6499                                 params, vars);
6500                 }
6501         }
6502         /* Reset the interrupt indication after phy was initialized */
6503         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6504                        params->port*4,
6505                        (NIG_STATUS_XGXS0_LINK10G |
6506                         NIG_STATUS_XGXS0_LINK_STATUS |
6507                         NIG_STATUS_SERDES0_LINK_STATUS |
6508                         NIG_MASK_MI_INT));
6509         return rc;
6510 }
6511
6512 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6513                                  struct link_params *params)
6514 {
6515         /* reset the SerDes/XGXS */
6516         REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6517                (0x1ff << (params->port*16)));
6518 }
6519
6520 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6521                                         struct link_params *params)
6522 {
6523         struct bnx2x *bp = params->bp;
6524         u8 gpio_port;
6525         /* HW reset */
6526         if (CHIP_IS_E2(bp))
6527                 gpio_port = BP_PATH(bp);
6528         else
6529                 gpio_port = params->port;
6530         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6531                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6532                        gpio_port);
6533         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6534                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6535                        gpio_port);
6536         DP(NETIF_MSG_LINK, "reset external PHY\n");
6537 }
6538
6539 static int bnx2x_update_link_down(struct link_params *params,
6540                                   struct link_vars *vars)
6541 {
6542         struct bnx2x *bp = params->bp;
6543         u8 port = params->port;
6544
6545         DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6546         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6547         vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6548         /* indicate no mac active */
6549         vars->mac_type = MAC_TYPE_NONE;
6550
6551         /* update shared memory */
6552         vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK |
6553                                LINK_STATUS_LINK_UP |
6554                                LINK_STATUS_PHYSICAL_LINK_FLAG |
6555                                LINK_STATUS_AUTO_NEGOTIATE_COMPLETE |
6556                                LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK |
6557                                LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK |
6558                                LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK |
6559                                LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE |
6560                                LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE);
6561         vars->line_speed = 0;
6562         bnx2x_update_mng(params, vars->link_status);
6563
6564         /* activate nig drain */
6565         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6566
6567         /* disable emac */
6568         if (!CHIP_IS_E3(bp))
6569                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6570
6571         msleep(10);
6572         /* reset BigMac/Xmac */
6573         if (CHIP_IS_E1x(bp) ||
6574             CHIP_IS_E2(bp)) {
6575                 bnx2x_bmac_rx_disable(bp, params->port);
6576                 REG_WR(bp, GRCBASE_MISC +
6577                        MISC_REGISTERS_RESET_REG_2_CLEAR,
6578                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6579         }
6580         if (CHIP_IS_E3(bp)) {
6581                 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
6582                        0);
6583                 REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 0);
6584                 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
6585                        0);
6586                 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
6587                                       SHMEM_EEE_ACTIVE_BIT);
6588
6589                 bnx2x_update_mng_eee(params, vars->eee_status);
6590                 bnx2x_xmac_disable(params);
6591                 bnx2x_umac_disable(params);
6592         }
6593
6594         return 0;
6595 }
6596
6597 static int bnx2x_update_link_up(struct link_params *params,
6598                                 struct link_vars *vars,
6599                                 u8 link_10g)
6600 {
6601         struct bnx2x *bp = params->bp;
6602         u8 phy_idx, port = params->port;
6603         int rc = 0;
6604
6605         vars->link_status |= (LINK_STATUS_LINK_UP |
6606                               LINK_STATUS_PHYSICAL_LINK_FLAG);
6607         vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6608
6609         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6610                 vars->link_status |=
6611                         LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6612
6613         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6614                 vars->link_status |=
6615                         LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6616         if (USES_WARPCORE(bp)) {
6617                 if (link_10g) {
6618                         if (bnx2x_xmac_enable(params, vars, 0) ==
6619                             -ESRCH) {
6620                                 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6621                                 vars->link_up = 0;
6622                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6623                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6624                         }
6625                 } else
6626                         bnx2x_umac_enable(params, vars, 0);
6627                 bnx2x_set_led(params, vars,
6628                               LED_MODE_OPER, vars->line_speed);
6629
6630                 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
6631                     (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
6632                         DP(NETIF_MSG_LINK, "Enabling LPI assertion\n");
6633                         REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
6634                                (params->port << 2), 1);
6635                         REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1);
6636                         REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 +
6637                                (params->port << 2), 0xfc20);
6638                 }
6639         }
6640         if ((CHIP_IS_E1x(bp) ||
6641              CHIP_IS_E2(bp))) {
6642                 if (link_10g) {
6643                         if (bnx2x_bmac_enable(params, vars, 0) ==
6644                             -ESRCH) {
6645                                 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6646                                 vars->link_up = 0;
6647                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6648                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6649                         }
6650
6651                         bnx2x_set_led(params, vars,
6652                                       LED_MODE_OPER, SPEED_10000);
6653                 } else {
6654                         rc = bnx2x_emac_program(params, vars);
6655                         bnx2x_emac_enable(params, vars, 0);
6656
6657                         /* AN complete? */
6658                         if ((vars->link_status &
6659                              LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6660                             && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6661                             SINGLE_MEDIA_DIRECT(params))
6662                                 bnx2x_set_gmii_tx_driver(params);
6663                 }
6664         }
6665
6666         /* PBF - link up */
6667         if (CHIP_IS_E1x(bp))
6668                 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6669                                        vars->line_speed);
6670
6671         /* disable drain */
6672         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6673
6674         /* update shared memory */
6675         bnx2x_update_mng(params, vars->link_status);
6676         bnx2x_update_mng_eee(params, vars->eee_status);
6677         /* Check remote fault */
6678         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
6679                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
6680                         bnx2x_check_half_open_conn(params, vars, 0);
6681                         break;
6682                 }
6683         }
6684         msleep(20);
6685         return rc;
6686 }
6687 /* The bnx2x_link_update function should be called upon link
6688  * interrupt.
6689  * Link is considered up as follows:
6690  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6691  *   to be up
6692  * - SINGLE_MEDIA - The link between the 577xx and the external
6693  *   phy (XGXS) need to up as well as the external link of the
6694  *   phy (PHY_EXT1)
6695  * - DUAL_MEDIA - The link between the 577xx and the first
6696  *   external phy needs to be up, and at least one of the 2
6697  *   external phy link must be up.
6698  */
6699 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6700 {
6701         struct bnx2x *bp = params->bp;
6702         struct link_vars phy_vars[MAX_PHYS];
6703         u8 port = params->port;
6704         u8 link_10g_plus, phy_index;
6705         u8 ext_phy_link_up = 0, cur_link_up;
6706         int rc = 0;
6707         u8 is_mi_int = 0;
6708         u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6709         u8 active_external_phy = INT_PHY;
6710         vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6711         for (phy_index = INT_PHY; phy_index < params->num_phys;
6712               phy_index++) {
6713                 phy_vars[phy_index].flow_ctrl = 0;
6714                 phy_vars[phy_index].link_status = 0;
6715                 phy_vars[phy_index].line_speed = 0;
6716                 phy_vars[phy_index].duplex = DUPLEX_FULL;
6717                 phy_vars[phy_index].phy_link_up = 0;
6718                 phy_vars[phy_index].link_up = 0;
6719                 phy_vars[phy_index].fault_detected = 0;
6720                 /* different consideration, since vars holds inner state */
6721                 phy_vars[phy_index].eee_status = vars->eee_status;
6722         }
6723
6724         if (USES_WARPCORE(bp))
6725                 bnx2x_set_aer_mmd(params, &params->phy[INT_PHY]);
6726
6727         DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6728                  port, (vars->phy_flags & PHY_XGXS_FLAG),
6729                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6730
6731         is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6732                                 port*0x18) > 0);
6733         DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6734                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6735                  is_mi_int,
6736                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6737
6738         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6739           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6740           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6741
6742         /* disable emac */
6743         if (!CHIP_IS_E3(bp))
6744                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6745
6746         /* Step 1:
6747          * Check external link change only for external phys, and apply
6748          * priority selection between them in case the link on both phys
6749          * is up. Note that instead of the common vars, a temporary
6750          * vars argument is used since each phy may have different link/
6751          * speed/duplex result
6752          */
6753         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6754               phy_index++) {
6755                 struct bnx2x_phy *phy = &params->phy[phy_index];
6756                 if (!phy->read_status)
6757                         continue;
6758                 /* Read link status and params of this ext phy */
6759                 cur_link_up = phy->read_status(phy, params,
6760                                                &phy_vars[phy_index]);
6761                 if (cur_link_up) {
6762                         DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6763                                    phy_index);
6764                 } else {
6765                         DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6766                                    phy_index);
6767                         continue;
6768                 }
6769
6770                 if (!ext_phy_link_up) {
6771                         ext_phy_link_up = 1;
6772                         active_external_phy = phy_index;
6773                 } else {
6774                         switch (bnx2x_phy_selection(params)) {
6775                         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6776                         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6777                         /* In this option, the first PHY makes sure to pass the
6778                          * traffic through itself only.
6779                          * Its not clear how to reset the link on the second phy
6780                          */
6781                                 active_external_phy = EXT_PHY1;
6782                                 break;
6783                         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6784                         /* In this option, the first PHY makes sure to pass the
6785                          * traffic through the second PHY.
6786                          */
6787                                 active_external_phy = EXT_PHY2;
6788                                 break;
6789                         default:
6790                         /* Link indication on both PHYs with the following cases
6791                          * is invalid:
6792                          * - FIRST_PHY means that second phy wasn't initialized,
6793                          * hence its link is expected to be down
6794                          * - SECOND_PHY means that first phy should not be able
6795                          * to link up by itself (using configuration)
6796                          * - DEFAULT should be overriden during initialiazation
6797                          */
6798                                 DP(NETIF_MSG_LINK, "Invalid link indication"
6799                                            "mpc=0x%x. DISABLING LINK !!!\n",
6800                                            params->multi_phy_config);
6801                                 ext_phy_link_up = 0;
6802                                 break;
6803                         }
6804                 }
6805         }
6806         prev_line_speed = vars->line_speed;
6807         /* Step 2:
6808          * Read the status of the internal phy. In case of
6809          * DIRECT_SINGLE_MEDIA board, this link is the external link,
6810          * otherwise this is the link between the 577xx and the first
6811          * external phy
6812          */
6813         if (params->phy[INT_PHY].read_status)
6814                 params->phy[INT_PHY].read_status(
6815                         &params->phy[INT_PHY],
6816                         params, vars);
6817         /* The INT_PHY flow control reside in the vars. This include the
6818          * case where the speed or flow control are not set to AUTO.
6819          * Otherwise, the active external phy flow control result is set
6820          * to the vars. The ext_phy_line_speed is needed to check if the
6821          * speed is different between the internal phy and external phy.
6822          * This case may be result of intermediate link speed change.
6823          */
6824         if (active_external_phy > INT_PHY) {
6825                 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6826                 /* Link speed is taken from the XGXS. AN and FC result from
6827                  * the external phy.
6828                  */
6829                 vars->link_status |= phy_vars[active_external_phy].link_status;
6830
6831                 /* if active_external_phy is first PHY and link is up - disable
6832                  * disable TX on second external PHY
6833                  */
6834                 if (active_external_phy == EXT_PHY1) {
6835                         if (params->phy[EXT_PHY2].phy_specific_func) {
6836                                 DP(NETIF_MSG_LINK,
6837                                    "Disabling TX on EXT_PHY2\n");
6838                                 params->phy[EXT_PHY2].phy_specific_func(
6839                                         &params->phy[EXT_PHY2],
6840                                         params, DISABLE_TX);
6841                         }
6842                 }
6843
6844                 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6845                 vars->duplex = phy_vars[active_external_phy].duplex;
6846                 if (params->phy[active_external_phy].supported &
6847                     SUPPORTED_FIBRE)
6848                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6849                 else
6850                         vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6851
6852                 vars->eee_status = phy_vars[active_external_phy].eee_status;
6853
6854                 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6855                            active_external_phy);
6856         }
6857
6858         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6859               phy_index++) {
6860                 if (params->phy[phy_index].flags &
6861                     FLAGS_REARM_LATCH_SIGNAL) {
6862                         bnx2x_rearm_latch_signal(bp, port,
6863                                                  phy_index ==
6864                                                  active_external_phy);
6865                         break;
6866                 }
6867         }
6868         DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6869                    " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6870                    vars->link_status, ext_phy_line_speed);
6871         /* Upon link speed change set the NIG into drain mode. Comes to
6872          * deals with possible FIFO glitch due to clk change when speed
6873          * is decreased without link down indicator
6874          */
6875
6876         if (vars->phy_link_up) {
6877                 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6878                     (ext_phy_line_speed != vars->line_speed)) {
6879                         DP(NETIF_MSG_LINK, "Internal link speed %d is"
6880                                    " different than the external"
6881                                    " link speed %d\n", vars->line_speed,
6882                                    ext_phy_line_speed);
6883                         vars->phy_link_up = 0;
6884                 } else if (prev_line_speed != vars->line_speed) {
6885                         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6886                                0);
6887                         msleep(1);
6888                 }
6889         }
6890
6891         /* anything 10 and over uses the bmac */
6892         link_10g_plus = (vars->line_speed >= SPEED_10000);
6893
6894         bnx2x_link_int_ack(params, vars, link_10g_plus);
6895
6896         /* In case external phy link is up, and internal link is down
6897          * (not initialized yet probably after link initialization, it
6898          * needs to be initialized.
6899          * Note that after link down-up as result of cable plug, the xgxs
6900          * link would probably become up again without the need
6901          * initialize it
6902          */
6903         if (!(SINGLE_MEDIA_DIRECT(params))) {
6904                 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6905                            " init_preceding = %d\n", ext_phy_link_up,
6906                            vars->phy_link_up,
6907                            params->phy[EXT_PHY1].flags &
6908                            FLAGS_INIT_XGXS_FIRST);
6909                 if (!(params->phy[EXT_PHY1].flags &
6910                       FLAGS_INIT_XGXS_FIRST)
6911                     && ext_phy_link_up && !vars->phy_link_up) {
6912                         vars->line_speed = ext_phy_line_speed;
6913                         if (vars->line_speed < SPEED_1000)
6914                                 vars->phy_flags |= PHY_SGMII_FLAG;
6915                         else
6916                                 vars->phy_flags &= ~PHY_SGMII_FLAG;
6917
6918                         if (params->phy[INT_PHY].config_init)
6919                                 params->phy[INT_PHY].config_init(
6920                                         &params->phy[INT_PHY], params,
6921                                                 vars);
6922                 }
6923         }
6924         /* Link is up only if both local phy and external phy (in case of
6925          * non-direct board) are up and no fault detected on active PHY.
6926          */
6927         vars->link_up = (vars->phy_link_up &&
6928                          (ext_phy_link_up ||
6929                           SINGLE_MEDIA_DIRECT(params)) &&
6930                          (phy_vars[active_external_phy].fault_detected == 0));
6931
6932         /* Update the PFC configuration in case it was changed */
6933         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
6934                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
6935         else
6936                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
6937
6938         if (vars->link_up)
6939                 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
6940         else
6941                 rc = bnx2x_update_link_down(params, vars);
6942
6943         /* Update MCP link status was changed */
6944         if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX)
6945                 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
6946
6947         return rc;
6948 }
6949
6950 /*****************************************************************************/
6951 /*                          External Phy section                             */
6952 /*****************************************************************************/
6953 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
6954 {
6955         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6956                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6957         msleep(1);
6958         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6959                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6960 }
6961
6962 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
6963                                       u32 spirom_ver, u32 ver_addr)
6964 {
6965         DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
6966                  (u16)(spirom_ver>>16), (u16)spirom_ver, port);
6967
6968         if (ver_addr)
6969                 REG_WR(bp, ver_addr, spirom_ver);
6970 }
6971
6972 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
6973                                       struct bnx2x_phy *phy,
6974                                       u8 port)
6975 {
6976         u16 fw_ver1, fw_ver2;
6977
6978         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6979                         MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6980         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6981                         MDIO_PMA_REG_ROM_VER2, &fw_ver2);
6982         bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
6983                                   phy->ver_addr);
6984 }
6985
6986 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
6987                                        struct bnx2x_phy *phy,
6988                                        struct link_vars *vars)
6989 {
6990         u16 val;
6991         bnx2x_cl45_read(bp, phy,
6992                         MDIO_AN_DEVAD,
6993                         MDIO_AN_REG_STATUS, &val);
6994         bnx2x_cl45_read(bp, phy,
6995                         MDIO_AN_DEVAD,
6996                         MDIO_AN_REG_STATUS, &val);
6997         if (val & (1<<5))
6998                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6999         if ((val & (1<<0)) == 0)
7000                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
7001 }
7002
7003 /******************************************************************/
7004 /*              common BCM8073/BCM8727 PHY SECTION                */
7005 /******************************************************************/
7006 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
7007                                   struct link_params *params,
7008                                   struct link_vars *vars)
7009 {
7010         struct bnx2x *bp = params->bp;
7011         if (phy->req_line_speed == SPEED_10 ||
7012             phy->req_line_speed == SPEED_100) {
7013                 vars->flow_ctrl = phy->req_flow_ctrl;
7014                 return;
7015         }
7016
7017         if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
7018             (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
7019                 u16 pause_result;
7020                 u16 ld_pause;           /* local */
7021                 u16 lp_pause;           /* link partner */
7022                 bnx2x_cl45_read(bp, phy,
7023                                 MDIO_AN_DEVAD,
7024                                 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
7025
7026                 bnx2x_cl45_read(bp, phy,
7027                                 MDIO_AN_DEVAD,
7028                                 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
7029                 pause_result = (ld_pause &
7030                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
7031                 pause_result |= (lp_pause &
7032                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
7033
7034                 bnx2x_pause_resolve(vars, pause_result);
7035                 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
7036                            pause_result);
7037         }
7038 }
7039 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
7040                                              struct bnx2x_phy *phy,
7041                                              u8 port)
7042 {
7043         u32 count = 0;
7044         u16 fw_ver1, fw_msgout;
7045         int rc = 0;
7046
7047         /* Boot port from external ROM  */
7048         /* EDC grst */
7049         bnx2x_cl45_write(bp, phy,
7050                          MDIO_PMA_DEVAD,
7051                          MDIO_PMA_REG_GEN_CTRL,
7052                          0x0001);
7053
7054         /* ucode reboot and rst */
7055         bnx2x_cl45_write(bp, phy,
7056                          MDIO_PMA_DEVAD,
7057                          MDIO_PMA_REG_GEN_CTRL,
7058                          0x008c);
7059
7060         bnx2x_cl45_write(bp, phy,
7061                          MDIO_PMA_DEVAD,
7062                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
7063
7064         /* Reset internal microprocessor */
7065         bnx2x_cl45_write(bp, phy,
7066                          MDIO_PMA_DEVAD,
7067                          MDIO_PMA_REG_GEN_CTRL,
7068                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
7069
7070         /* Release srst bit */
7071         bnx2x_cl45_write(bp, phy,
7072                          MDIO_PMA_DEVAD,
7073                          MDIO_PMA_REG_GEN_CTRL,
7074                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
7075
7076         /* Delay 100ms per the PHY specifications */
7077         msleep(100);
7078
7079         /* 8073 sometimes taking longer to download */
7080         do {
7081                 count++;
7082                 if (count > 300) {
7083                         DP(NETIF_MSG_LINK,
7084                                  "bnx2x_8073_8727_external_rom_boot port %x:"
7085                                  "Download failed. fw version = 0x%x\n",
7086                                  port, fw_ver1);
7087                         rc = -EINVAL;
7088                         break;
7089                 }
7090
7091                 bnx2x_cl45_read(bp, phy,
7092                                 MDIO_PMA_DEVAD,
7093                                 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7094                 bnx2x_cl45_read(bp, phy,
7095                                 MDIO_PMA_DEVAD,
7096                                 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
7097
7098                 msleep(1);
7099         } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
7100                         ((fw_msgout & 0xff) != 0x03 && (phy->type ==
7101                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
7102
7103         /* Clear ser_boot_ctl bit */
7104         bnx2x_cl45_write(bp, phy,
7105                          MDIO_PMA_DEVAD,
7106                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
7107         bnx2x_save_bcm_spirom_ver(bp, phy, port);
7108
7109         DP(NETIF_MSG_LINK,
7110                  "bnx2x_8073_8727_external_rom_boot port %x:"
7111                  "Download complete. fw version = 0x%x\n",
7112                  port, fw_ver1);
7113
7114         return rc;
7115 }
7116
7117 /******************************************************************/
7118 /*                      BCM8073 PHY SECTION                       */
7119 /******************************************************************/
7120 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
7121 {
7122         /* This is only required for 8073A1, version 102 only */
7123         u16 val;
7124
7125         /* Read 8073 HW revision*/
7126         bnx2x_cl45_read(bp, phy,
7127                         MDIO_PMA_DEVAD,
7128                         MDIO_PMA_REG_8073_CHIP_REV, &val);
7129
7130         if (val != 1) {
7131                 /* No need to workaround in 8073 A1 */
7132                 return 0;
7133         }
7134
7135         bnx2x_cl45_read(bp, phy,
7136                         MDIO_PMA_DEVAD,
7137                         MDIO_PMA_REG_ROM_VER2, &val);
7138
7139         /* SNR should be applied only for version 0x102 */
7140         if (val != 0x102)
7141                 return 0;
7142
7143         return 1;
7144 }
7145
7146 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
7147 {
7148         u16 val, cnt, cnt1 ;
7149
7150         bnx2x_cl45_read(bp, phy,
7151                         MDIO_PMA_DEVAD,
7152                         MDIO_PMA_REG_8073_CHIP_REV, &val);
7153
7154         if (val > 0) {
7155                 /* No need to workaround in 8073 A1 */
7156                 return 0;
7157         }
7158         /* XAUI workaround in 8073 A0: */
7159
7160         /* After loading the boot ROM and restarting Autoneg, poll
7161          * Dev1, Reg $C820:
7162          */
7163
7164         for (cnt = 0; cnt < 1000; cnt++) {
7165                 bnx2x_cl45_read(bp, phy,
7166                                 MDIO_PMA_DEVAD,
7167                                 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7168                                 &val);
7169                   /* If bit [14] = 0 or bit [13] = 0, continue on with
7170                    * system initialization (XAUI work-around not required, as
7171                    * these bits indicate 2.5G or 1G link up).
7172                    */
7173                 if (!(val & (1<<14)) || !(val & (1<<13))) {
7174                         DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
7175                         return 0;
7176                 } else if (!(val & (1<<15))) {
7177                         DP(NETIF_MSG_LINK, "bit 15 went off\n");
7178                         /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7179                          * MSB (bit15) goes to 1 (indicating that the XAUI
7180                          * workaround has completed), then continue on with
7181                          * system initialization.
7182                          */
7183                         for (cnt1 = 0; cnt1 < 1000; cnt1++) {
7184                                 bnx2x_cl45_read(bp, phy,
7185                                         MDIO_PMA_DEVAD,
7186                                         MDIO_PMA_REG_8073_XAUI_WA, &val);
7187                                 if (val & (1<<15)) {
7188                                         DP(NETIF_MSG_LINK,
7189                                           "XAUI workaround has completed\n");
7190                                         return 0;
7191                                  }
7192                                  msleep(3);
7193                         }
7194                         break;
7195                 }
7196                 msleep(3);
7197         }
7198         DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
7199         return -EINVAL;
7200 }
7201
7202 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
7203 {
7204         /* Force KR or KX */
7205         bnx2x_cl45_write(bp, phy,
7206                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
7207         bnx2x_cl45_write(bp, phy,
7208                          MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
7209         bnx2x_cl45_write(bp, phy,
7210                          MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
7211         bnx2x_cl45_write(bp, phy,
7212                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
7213 }
7214
7215 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
7216                                       struct bnx2x_phy *phy,
7217                                       struct link_vars *vars)
7218 {
7219         u16 cl37_val;
7220         struct bnx2x *bp = params->bp;
7221         bnx2x_cl45_read(bp, phy,
7222                         MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
7223
7224         cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7225         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
7226         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
7227         if ((vars->ieee_fc &
7228             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7229             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7230                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
7231         }
7232         if ((vars->ieee_fc &
7233             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7234             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7235                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
7236         }
7237         if ((vars->ieee_fc &
7238             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7239             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7240                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7241         }
7242         DP(NETIF_MSG_LINK,
7243                  "Ext phy AN advertize cl37 0x%x\n", cl37_val);
7244
7245         bnx2x_cl45_write(bp, phy,
7246                          MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
7247         msleep(500);
7248 }
7249
7250 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
7251                                   struct link_params *params,
7252                                   struct link_vars *vars)
7253 {
7254         struct bnx2x *bp = params->bp;
7255         u16 val = 0, tmp1;
7256         u8 gpio_port;
7257         DP(NETIF_MSG_LINK, "Init 8073\n");
7258
7259         if (CHIP_IS_E2(bp))
7260                 gpio_port = BP_PATH(bp);
7261         else
7262                 gpio_port = params->port;
7263         /* Restore normal power mode*/
7264         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7265                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7266
7267         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7268                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7269
7270         /* enable LASI */
7271         bnx2x_cl45_write(bp, phy,
7272                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
7273         bnx2x_cl45_write(bp, phy,
7274                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,  0x0004);
7275
7276         bnx2x_8073_set_pause_cl37(params, phy, vars);
7277
7278         bnx2x_cl45_read(bp, phy,
7279                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
7280
7281         bnx2x_cl45_read(bp, phy,
7282                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
7283
7284         DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
7285
7286         /* Swap polarity if required - Must be done only in non-1G mode */
7287         if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7288                 /* Configure the 8073 to swap _P and _N of the KR lines */
7289                 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
7290                 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7291                 bnx2x_cl45_read(bp, phy,
7292                                 MDIO_PMA_DEVAD,
7293                                 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
7294                 bnx2x_cl45_write(bp, phy,
7295                                  MDIO_PMA_DEVAD,
7296                                  MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7297                                  (val | (3<<9)));
7298         }
7299
7300
7301         /* Enable CL37 BAM */
7302         if (REG_RD(bp, params->shmem_base +
7303                          offsetof(struct shmem_region, dev_info.
7304                                   port_hw_config[params->port].default_cfg)) &
7305             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
7306
7307                 bnx2x_cl45_read(bp, phy,
7308                                 MDIO_AN_DEVAD,
7309                                 MDIO_AN_REG_8073_BAM, &val);
7310                 bnx2x_cl45_write(bp, phy,
7311                                  MDIO_AN_DEVAD,
7312                                  MDIO_AN_REG_8073_BAM, val | 1);
7313                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
7314         }
7315         if (params->loopback_mode == LOOPBACK_EXT) {
7316                 bnx2x_807x_force_10G(bp, phy);
7317                 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
7318                 return 0;
7319         } else {
7320                 bnx2x_cl45_write(bp, phy,
7321                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
7322         }
7323         if (phy->req_line_speed != SPEED_AUTO_NEG) {
7324                 if (phy->req_line_speed == SPEED_10000) {
7325                         val = (1<<7);
7326                 } else if (phy->req_line_speed ==  SPEED_2500) {
7327                         val = (1<<5);
7328                         /* Note that 2.5G works only when used with 1G
7329                          * advertisement
7330                          */
7331                 } else
7332                         val = (1<<5);
7333         } else {
7334                 val = 0;
7335                 if (phy->speed_cap_mask &
7336                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7337                         val |= (1<<7);
7338
7339                 /* Note that 2.5G works only when used with 1G advertisement */
7340                 if (phy->speed_cap_mask &
7341                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
7342                          PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7343                         val |= (1<<5);
7344                 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
7345         }
7346
7347         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
7348         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
7349
7350         if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
7351              (phy->req_line_speed == SPEED_AUTO_NEG)) ||
7352             (phy->req_line_speed == SPEED_2500)) {
7353                 u16 phy_ver;
7354                 /* Allow 2.5G for A1 and above */
7355                 bnx2x_cl45_read(bp, phy,
7356                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
7357                                 &phy_ver);
7358                 DP(NETIF_MSG_LINK, "Add 2.5G\n");
7359                 if (phy_ver > 0)
7360                         tmp1 |= 1;
7361                 else
7362                         tmp1 &= 0xfffe;
7363         } else {
7364                 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
7365                 tmp1 &= 0xfffe;
7366         }
7367
7368         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
7369         /* Add support for CL37 (passive mode) II */
7370
7371         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
7372         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
7373                          (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
7374                                   0x20 : 0x40)));
7375
7376         /* Add support for CL37 (passive mode) III */
7377         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
7378
7379         /* The SNR will improve about 2db by changing BW and FEE main
7380          * tap. Rest commands are executed after link is up
7381          * Change FFE main cursor to 5 in EDC register
7382          */
7383         if (bnx2x_8073_is_snr_needed(bp, phy))
7384                 bnx2x_cl45_write(bp, phy,
7385                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7386                                  0xFB0C);
7387
7388         /* Enable FEC (Forware Error Correction) Request in the AN */
7389         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7390         tmp1 |= (1<<15);
7391         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7392
7393         bnx2x_ext_phy_set_pause(params, phy, vars);
7394
7395         /* Restart autoneg */
7396         msleep(500);
7397         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7398         DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7399                    ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7400         return 0;
7401 }
7402
7403 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7404                                  struct link_params *params,
7405                                  struct link_vars *vars)
7406 {
7407         struct bnx2x *bp = params->bp;
7408         u8 link_up = 0;
7409         u16 val1, val2;
7410         u16 link_status = 0;
7411         u16 an1000_status = 0;
7412
7413         bnx2x_cl45_read(bp, phy,
7414                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7415
7416         DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7417
7418         /* clear the interrupt LASI status register */
7419         bnx2x_cl45_read(bp, phy,
7420                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7421         bnx2x_cl45_read(bp, phy,
7422                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7423         DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7424         /* Clear MSG-OUT */
7425         bnx2x_cl45_read(bp, phy,
7426                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7427
7428         /* Check the LASI */
7429         bnx2x_cl45_read(bp, phy,
7430                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7431
7432         DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7433
7434         /* Check the link status */
7435         bnx2x_cl45_read(bp, phy,
7436                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7437         DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7438
7439         bnx2x_cl45_read(bp, phy,
7440                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7441         bnx2x_cl45_read(bp, phy,
7442                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7443         link_up = ((val1 & 4) == 4);
7444         DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7445
7446         if (link_up &&
7447              ((phy->req_line_speed != SPEED_10000))) {
7448                 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7449                         return 0;
7450         }
7451         bnx2x_cl45_read(bp, phy,
7452                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7453         bnx2x_cl45_read(bp, phy,
7454                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7455
7456         /* Check the link status on 1.1.2 */
7457         bnx2x_cl45_read(bp, phy,
7458                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7459         bnx2x_cl45_read(bp, phy,
7460                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7461         DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7462                    "an_link_status=0x%x\n", val2, val1, an1000_status);
7463
7464         link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7465         if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7466                 /* The SNR will improve about 2dbby changing the BW and FEE main
7467                  * tap. The 1st write to change FFE main tap is set before
7468                  * restart AN. Change PLL Bandwidth in EDC register
7469                  */
7470                 bnx2x_cl45_write(bp, phy,
7471                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7472                                  0x26BC);
7473
7474                 /* Change CDR Bandwidth in EDC register */
7475                 bnx2x_cl45_write(bp, phy,
7476                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7477                                  0x0333);
7478         }
7479         bnx2x_cl45_read(bp, phy,
7480                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7481                         &link_status);
7482
7483         /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7484         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7485                 link_up = 1;
7486                 vars->line_speed = SPEED_10000;
7487                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7488                            params->port);
7489         } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7490                 link_up = 1;
7491                 vars->line_speed = SPEED_2500;
7492                 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7493                            params->port);
7494         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7495                 link_up = 1;
7496                 vars->line_speed = SPEED_1000;
7497                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7498                            params->port);
7499         } else {
7500                 link_up = 0;
7501                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7502                            params->port);
7503         }
7504
7505         if (link_up) {
7506                 /* Swap polarity if required */
7507                 if (params->lane_config &
7508                     PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7509                         /* Configure the 8073 to swap P and N of the KR lines */
7510                         bnx2x_cl45_read(bp, phy,
7511                                         MDIO_XS_DEVAD,
7512                                         MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7513                         /* Set bit 3 to invert Rx in 1G mode and clear this bit
7514                          * when it`s in 10G mode.
7515                          */
7516                         if (vars->line_speed == SPEED_1000) {
7517                                 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7518                                               "the 8073\n");
7519                                 val1 |= (1<<3);
7520                         } else
7521                                 val1 &= ~(1<<3);
7522
7523                         bnx2x_cl45_write(bp, phy,
7524                                          MDIO_XS_DEVAD,
7525                                          MDIO_XS_REG_8073_RX_CTRL_PCIE,
7526                                          val1);
7527                 }
7528                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7529                 bnx2x_8073_resolve_fc(phy, params, vars);
7530                 vars->duplex = DUPLEX_FULL;
7531         }
7532
7533         if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
7534                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
7535                                 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
7536
7537                 if (val1 & (1<<5))
7538                         vars->link_status |=
7539                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7540                 if (val1 & (1<<7))
7541                         vars->link_status |=
7542                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7543         }
7544
7545         return link_up;
7546 }
7547
7548 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7549                                   struct link_params *params)
7550 {
7551         struct bnx2x *bp = params->bp;
7552         u8 gpio_port;
7553         if (CHIP_IS_E2(bp))
7554                 gpio_port = BP_PATH(bp);
7555         else
7556                 gpio_port = params->port;
7557         DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7558            gpio_port);
7559         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7560                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
7561                        gpio_port);
7562 }
7563
7564 /******************************************************************/
7565 /*                      BCM8705 PHY SECTION                       */
7566 /******************************************************************/
7567 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7568                                   struct link_params *params,
7569                                   struct link_vars *vars)
7570 {
7571         struct bnx2x *bp = params->bp;
7572         DP(NETIF_MSG_LINK, "init 8705\n");
7573         /* Restore normal power mode*/
7574         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7575                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7576         /* HW reset */
7577         bnx2x_ext_phy_hw_reset(bp, params->port);
7578         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7579         bnx2x_wait_reset_complete(bp, phy, params);
7580
7581         bnx2x_cl45_write(bp, phy,
7582                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7583         bnx2x_cl45_write(bp, phy,
7584                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7585         bnx2x_cl45_write(bp, phy,
7586                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7587         bnx2x_cl45_write(bp, phy,
7588                          MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7589         /* BCM8705 doesn't have microcode, hence the 0 */
7590         bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7591         return 0;
7592 }
7593
7594 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7595                                  struct link_params *params,
7596                                  struct link_vars *vars)
7597 {
7598         u8 link_up = 0;
7599         u16 val1, rx_sd;
7600         struct bnx2x *bp = params->bp;
7601         DP(NETIF_MSG_LINK, "read status 8705\n");
7602         bnx2x_cl45_read(bp, phy,
7603                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7604         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7605
7606         bnx2x_cl45_read(bp, phy,
7607                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7608         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7609
7610         bnx2x_cl45_read(bp, phy,
7611                       MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7612
7613         bnx2x_cl45_read(bp, phy,
7614                       MDIO_PMA_DEVAD, 0xc809, &val1);
7615         bnx2x_cl45_read(bp, phy,
7616                       MDIO_PMA_DEVAD, 0xc809, &val1);
7617
7618         DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7619         link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7620         if (link_up) {
7621                 vars->line_speed = SPEED_10000;
7622                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7623         }
7624         return link_up;
7625 }
7626
7627 /******************************************************************/
7628 /*                      SFP+ module Section                       */
7629 /******************************************************************/
7630 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7631                                            struct bnx2x_phy *phy,
7632                                            u8 pmd_dis)
7633 {
7634         struct bnx2x *bp = params->bp;
7635         /* Disable transmitter only for bootcodes which can enable it afterwards
7636          * (for D3 link)
7637          */
7638         if (pmd_dis) {
7639                 if (params->feature_config_flags &
7640                      FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7641                         DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7642                 else {
7643                         DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7644                         return;
7645                 }
7646         } else
7647                 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7648         bnx2x_cl45_write(bp, phy,
7649                          MDIO_PMA_DEVAD,
7650                          MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7651 }
7652
7653 static u8 bnx2x_get_gpio_port(struct link_params *params)
7654 {
7655         u8 gpio_port;
7656         u32 swap_val, swap_override;
7657         struct bnx2x *bp = params->bp;
7658         if (CHIP_IS_E2(bp))
7659                 gpio_port = BP_PATH(bp);
7660         else
7661                 gpio_port = params->port;
7662         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7663         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7664         return gpio_port ^ (swap_val && swap_override);
7665 }
7666
7667 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7668                                            struct bnx2x_phy *phy,
7669                                            u8 tx_en)
7670 {
7671         u16 val;
7672         u8 port = params->port;
7673         struct bnx2x *bp = params->bp;
7674         u32 tx_en_mode;
7675
7676         /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7677         tx_en_mode = REG_RD(bp, params->shmem_base +
7678                             offsetof(struct shmem_region,
7679                                      dev_info.port_hw_config[port].sfp_ctrl)) &
7680                 PORT_HW_CFG_TX_LASER_MASK;
7681         DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7682                            "mode = %x\n", tx_en, port, tx_en_mode);
7683         switch (tx_en_mode) {
7684         case PORT_HW_CFG_TX_LASER_MDIO:
7685
7686                 bnx2x_cl45_read(bp, phy,
7687                                 MDIO_PMA_DEVAD,
7688                                 MDIO_PMA_REG_PHY_IDENTIFIER,
7689                                 &val);
7690
7691                 if (tx_en)
7692                         val &= ~(1<<15);
7693                 else
7694                         val |= (1<<15);
7695
7696                 bnx2x_cl45_write(bp, phy,
7697                                  MDIO_PMA_DEVAD,
7698                                  MDIO_PMA_REG_PHY_IDENTIFIER,
7699                                  val);
7700         break;
7701         case PORT_HW_CFG_TX_LASER_GPIO0:
7702         case PORT_HW_CFG_TX_LASER_GPIO1:
7703         case PORT_HW_CFG_TX_LASER_GPIO2:
7704         case PORT_HW_CFG_TX_LASER_GPIO3:
7705         {
7706                 u16 gpio_pin;
7707                 u8 gpio_port, gpio_mode;
7708                 if (tx_en)
7709                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7710                 else
7711                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7712
7713                 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7714                 gpio_port = bnx2x_get_gpio_port(params);
7715                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7716                 break;
7717         }
7718         default:
7719                 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7720                 break;
7721         }
7722 }
7723
7724 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7725                                       struct bnx2x_phy *phy,
7726                                       u8 tx_en)
7727 {
7728         struct bnx2x *bp = params->bp;
7729         DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7730         if (CHIP_IS_E3(bp))
7731                 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7732         else
7733                 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7734 }
7735
7736 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7737                                              struct link_params *params,
7738                                              u16 addr, u8 byte_cnt, u8 *o_buf)
7739 {
7740         struct bnx2x *bp = params->bp;
7741         u16 val = 0;
7742         u16 i;
7743         if (byte_cnt > 16) {
7744                 DP(NETIF_MSG_LINK,
7745                    "Reading from eeprom is limited to 0xf\n");
7746                 return -EINVAL;
7747         }
7748         /* Set the read command byte count */
7749         bnx2x_cl45_write(bp, phy,
7750                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7751                          (byte_cnt | 0xa000));
7752
7753         /* Set the read command address */
7754         bnx2x_cl45_write(bp, phy,
7755                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7756                          addr);
7757
7758         /* Activate read command */
7759         bnx2x_cl45_write(bp, phy,
7760                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7761                          0x2c0f);
7762
7763         /* Wait up to 500us for command complete status */
7764         for (i = 0; i < 100; i++) {
7765                 bnx2x_cl45_read(bp, phy,
7766                                 MDIO_PMA_DEVAD,
7767                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7768                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7769                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7770                         break;
7771                 udelay(5);
7772         }
7773
7774         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7775                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7776                 DP(NETIF_MSG_LINK,
7777                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7778                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7779                 return -EINVAL;
7780         }
7781
7782         /* Read the buffer */
7783         for (i = 0; i < byte_cnt; i++) {
7784                 bnx2x_cl45_read(bp, phy,
7785                                 MDIO_PMA_DEVAD,
7786                                 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7787                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7788         }
7789
7790         for (i = 0; i < 100; i++) {
7791                 bnx2x_cl45_read(bp, phy,
7792                                 MDIO_PMA_DEVAD,
7793                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7794                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7795                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7796                         return 0;
7797                 msleep(1);
7798         }
7799         return -EINVAL;
7800 }
7801
7802 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7803                                                  struct link_params *params,
7804                                                  u16 addr, u8 byte_cnt,
7805                                                  u8 *o_buf)
7806 {
7807         int rc = 0;
7808         u8 i, j = 0, cnt = 0;
7809         u32 data_array[4];
7810         u16 addr32;
7811         struct bnx2x *bp = params->bp;
7812         if (byte_cnt > 16) {
7813                 DP(NETIF_MSG_LINK,
7814                    "Reading from eeprom is limited to 16 bytes\n");
7815                 return -EINVAL;
7816         }
7817
7818         /* 4 byte aligned address */
7819         addr32 = addr & (~0x3);
7820         do {
7821                 rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt,
7822                                     data_array);
7823         } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7824
7825         if (rc == 0) {
7826                 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7827                         o_buf[j] = *((u8 *)data_array + i);
7828                         j++;
7829                 }
7830         }
7831
7832         return rc;
7833 }
7834
7835 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7836                                              struct link_params *params,
7837                                              u16 addr, u8 byte_cnt, u8 *o_buf)
7838 {
7839         struct bnx2x *bp = params->bp;
7840         u16 val, i;
7841
7842         if (byte_cnt > 16) {
7843                 DP(NETIF_MSG_LINK,
7844                    "Reading from eeprom is limited to 0xf\n");
7845                 return -EINVAL;
7846         }
7847
7848         /* Need to read from 1.8000 to clear it */
7849         bnx2x_cl45_read(bp, phy,
7850                         MDIO_PMA_DEVAD,
7851                         MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7852                         &val);
7853
7854         /* Set the read command byte count */
7855         bnx2x_cl45_write(bp, phy,
7856                          MDIO_PMA_DEVAD,
7857                          MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7858                          ((byte_cnt < 2) ? 2 : byte_cnt));
7859
7860         /* Set the read command address */
7861         bnx2x_cl45_write(bp, phy,
7862                          MDIO_PMA_DEVAD,
7863                          MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7864                          addr);
7865         /* Set the destination address */
7866         bnx2x_cl45_write(bp, phy,
7867                          MDIO_PMA_DEVAD,
7868                          0x8004,
7869                          MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7870
7871         /* Activate read command */
7872         bnx2x_cl45_write(bp, phy,
7873                          MDIO_PMA_DEVAD,
7874                          MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7875                          0x8002);
7876         /* Wait appropriate time for two-wire command to finish before
7877          * polling the status register
7878          */
7879         msleep(1);
7880
7881         /* Wait up to 500us for command complete status */
7882         for (i = 0; i < 100; i++) {
7883                 bnx2x_cl45_read(bp, phy,
7884                                 MDIO_PMA_DEVAD,
7885                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7886                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7887                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7888                         break;
7889                 udelay(5);
7890         }
7891
7892         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7893                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7894                 DP(NETIF_MSG_LINK,
7895                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7896                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7897                 return -EFAULT;
7898         }
7899
7900         /* Read the buffer */
7901         for (i = 0; i < byte_cnt; i++) {
7902                 bnx2x_cl45_read(bp, phy,
7903                                 MDIO_PMA_DEVAD,
7904                                 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
7905                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7906         }
7907
7908         for (i = 0; i < 100; i++) {
7909                 bnx2x_cl45_read(bp, phy,
7910                                 MDIO_PMA_DEVAD,
7911                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7912                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7913                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7914                         return 0;
7915                 msleep(1);
7916         }
7917
7918         return -EINVAL;
7919 }
7920
7921 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7922                                  struct link_params *params, u16 addr,
7923                                  u8 byte_cnt, u8 *o_buf)
7924 {
7925         int rc = -EINVAL;
7926         switch (phy->type) {
7927         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7928                 rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
7929                                                        byte_cnt, o_buf);
7930         break;
7931         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7932         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7933                 rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
7934                                                        byte_cnt, o_buf);
7935         break;
7936         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7937                 rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr,
7938                                                            byte_cnt, o_buf);
7939         break;
7940         }
7941         return rc;
7942 }
7943
7944 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
7945                               struct link_params *params,
7946                               u16 *edc_mode)
7947 {
7948         struct bnx2x *bp = params->bp;
7949         u32 sync_offset = 0, phy_idx, media_types;
7950         u8 val, check_limiting_mode = 0;
7951         *edc_mode = EDC_MODE_LIMITING;
7952
7953         phy->media_type = ETH_PHY_UNSPECIFIED;
7954         /* First check for copper cable */
7955         if (bnx2x_read_sfp_module_eeprom(phy,
7956                                          params,
7957                                          SFP_EEPROM_CON_TYPE_ADDR,
7958                                          1,
7959                                          &val) != 0) {
7960                 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
7961                 return -EINVAL;
7962         }
7963
7964         switch (val) {
7965         case SFP_EEPROM_CON_TYPE_VAL_COPPER:
7966         {
7967                 u8 copper_module_type;
7968                 phy->media_type = ETH_PHY_DA_TWINAX;
7969                 /* Check if its active cable (includes SFP+ module)
7970                  * of passive cable
7971                  */
7972                 if (bnx2x_read_sfp_module_eeprom(phy,
7973                                                params,
7974                                                SFP_EEPROM_FC_TX_TECH_ADDR,
7975                                                1,
7976                                                &copper_module_type) != 0) {
7977                         DP(NETIF_MSG_LINK,
7978                                 "Failed to read copper-cable-type"
7979                                 " from SFP+ EEPROM\n");
7980                         return -EINVAL;
7981                 }
7982
7983                 if (copper_module_type &
7984                     SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
7985                         DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
7986                         check_limiting_mode = 1;
7987                 } else if (copper_module_type &
7988                         SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
7989                                 DP(NETIF_MSG_LINK,
7990                                    "Passive Copper cable detected\n");
7991                                 *edc_mode =
7992                                       EDC_MODE_PASSIVE_DAC;
7993                 } else {
7994                         DP(NETIF_MSG_LINK,
7995                            "Unknown copper-cable-type 0x%x !!!\n",
7996                            copper_module_type);
7997                         return -EINVAL;
7998                 }
7999                 break;
8000         }
8001         case SFP_EEPROM_CON_TYPE_VAL_LC:
8002                 phy->media_type = ETH_PHY_SFP_FIBER;
8003                 DP(NETIF_MSG_LINK, "Optic module detected\n");
8004                 check_limiting_mode = 1;
8005                 break;
8006         default:
8007                 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
8008                          val);
8009                 return -EINVAL;
8010         }
8011         sync_offset = params->shmem_base +
8012                 offsetof(struct shmem_region,
8013                          dev_info.port_hw_config[params->port].media_type);
8014         media_types = REG_RD(bp, sync_offset);
8015         /* Update media type for non-PMF sync */
8016         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
8017                 if (&(params->phy[phy_idx]) == phy) {
8018                         media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
8019                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8020                         media_types |= ((phy->media_type &
8021                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
8022                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8023                         break;
8024                 }
8025         }
8026         REG_WR(bp, sync_offset, media_types);
8027         if (check_limiting_mode) {
8028                 u8 options[SFP_EEPROM_OPTIONS_SIZE];
8029                 if (bnx2x_read_sfp_module_eeprom(phy,
8030                                                  params,
8031                                                  SFP_EEPROM_OPTIONS_ADDR,
8032                                                  SFP_EEPROM_OPTIONS_SIZE,
8033                                                  options) != 0) {
8034                         DP(NETIF_MSG_LINK,
8035                            "Failed to read Option field from module EEPROM\n");
8036                         return -EINVAL;
8037                 }
8038                 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
8039                         *edc_mode = EDC_MODE_LINEAR;
8040                 else
8041                         *edc_mode = EDC_MODE_LIMITING;
8042         }
8043         DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
8044         return 0;
8045 }
8046 /* This function read the relevant field from the module (SFP+), and verify it
8047  * is compliant with this board
8048  */
8049 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
8050                                    struct link_params *params)
8051 {
8052         struct bnx2x *bp = params->bp;
8053         u32 val, cmd;
8054         u32 fw_resp, fw_cmd_param;
8055         char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
8056         char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
8057         phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
8058         val = REG_RD(bp, params->shmem_base +
8059                          offsetof(struct shmem_region, dev_info.
8060                                   port_feature_config[params->port].config));
8061         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8062             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
8063                 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
8064                 return 0;
8065         }
8066
8067         if (params->feature_config_flags &
8068             FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
8069                 /* Use specific phy request */
8070                 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
8071         } else if (params->feature_config_flags &
8072                    FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
8073                 /* Use first phy request only in case of non-dual media*/
8074                 if (DUAL_MEDIA(params)) {
8075                         DP(NETIF_MSG_LINK,
8076                            "FW does not support OPT MDL verification\n");
8077                         return -EINVAL;
8078                 }
8079                 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
8080         } else {
8081                 /* No support in OPT MDL detection */
8082                 DP(NETIF_MSG_LINK,
8083                    "FW does not support OPT MDL verification\n");
8084                 return -EINVAL;
8085         }
8086
8087         fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
8088         fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
8089         if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
8090                 DP(NETIF_MSG_LINK, "Approved module\n");
8091                 return 0;
8092         }
8093
8094         /* format the warning message */
8095         if (bnx2x_read_sfp_module_eeprom(phy,
8096                                          params,
8097                                          SFP_EEPROM_VENDOR_NAME_ADDR,
8098                                          SFP_EEPROM_VENDOR_NAME_SIZE,
8099                                          (u8 *)vendor_name))
8100                 vendor_name[0] = '\0';
8101         else
8102                 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
8103         if (bnx2x_read_sfp_module_eeprom(phy,
8104                                          params,
8105                                          SFP_EEPROM_PART_NO_ADDR,
8106                                          SFP_EEPROM_PART_NO_SIZE,
8107                                          (u8 *)vendor_pn))
8108                 vendor_pn[0] = '\0';
8109         else
8110                 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
8111
8112         netdev_err(bp->dev,  "Warning: Unqualified SFP+ module detected,"
8113                               " Port %d from %s part number %s\n",
8114                          params->port, vendor_name, vendor_pn);
8115         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8116             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
8117                 phy->flags |= FLAGS_SFP_NOT_APPROVED;
8118         return -EINVAL;
8119 }
8120
8121 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
8122                                                  struct link_params *params)
8123
8124 {
8125         u8 val;
8126         struct bnx2x *bp = params->bp;
8127         u16 timeout;
8128         /* Initialization time after hot-plug may take up to 300ms for
8129          * some phys type ( e.g. JDSU )
8130          */
8131
8132         for (timeout = 0; timeout < 60; timeout++) {
8133                 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
8134                     == 0) {
8135                         DP(NETIF_MSG_LINK,
8136                            "SFP+ module initialization took %d ms\n",
8137                            timeout * 5);
8138                         return 0;
8139                 }
8140                 msleep(5);
8141         }
8142         return -EINVAL;
8143 }
8144
8145 static void bnx2x_8727_power_module(struct bnx2x *bp,
8146                                     struct bnx2x_phy *phy,
8147                                     u8 is_power_up) {
8148         /* Make sure GPIOs are not using for LED mode */
8149         u16 val;
8150         /* In the GPIO register, bit 4 is use to determine if the GPIOs are
8151          * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
8152          * output
8153          * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
8154          * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
8155          * where the 1st bit is the over-current(only input), and 2nd bit is
8156          * for power( only output )
8157          *
8158          * In case of NOC feature is disabled and power is up, set GPIO control
8159          *  as input to enable listening of over-current indication
8160          */
8161         if (phy->flags & FLAGS_NOC)
8162                 return;
8163         if (is_power_up)
8164                 val = (1<<4);
8165         else
8166                 /* Set GPIO control to OUTPUT, and set the power bit
8167                  * to according to the is_power_up
8168                  */
8169                 val = (1<<1);
8170
8171         bnx2x_cl45_write(bp, phy,
8172                          MDIO_PMA_DEVAD,
8173                          MDIO_PMA_REG_8727_GPIO_CTRL,
8174                          val);
8175 }
8176
8177 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
8178                                         struct bnx2x_phy *phy,
8179                                         u16 edc_mode)
8180 {
8181         u16 cur_limiting_mode;
8182
8183         bnx2x_cl45_read(bp, phy,
8184                         MDIO_PMA_DEVAD,
8185                         MDIO_PMA_REG_ROM_VER2,
8186                         &cur_limiting_mode);
8187         DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
8188                  cur_limiting_mode);
8189
8190         if (edc_mode == EDC_MODE_LIMITING) {
8191                 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
8192                 bnx2x_cl45_write(bp, phy,
8193                                  MDIO_PMA_DEVAD,
8194                                  MDIO_PMA_REG_ROM_VER2,
8195                                  EDC_MODE_LIMITING);
8196         } else { /* LRM mode ( default )*/
8197
8198                 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
8199
8200                 /* Changing to LRM mode takes quite few seconds. So do it only
8201                  * if current mode is limiting (default is LRM)
8202                  */
8203                 if (cur_limiting_mode != EDC_MODE_LIMITING)
8204                         return 0;
8205
8206                 bnx2x_cl45_write(bp, phy,
8207                                  MDIO_PMA_DEVAD,
8208                                  MDIO_PMA_REG_LRM_MODE,
8209                                  0);
8210                 bnx2x_cl45_write(bp, phy,
8211                                  MDIO_PMA_DEVAD,
8212                                  MDIO_PMA_REG_ROM_VER2,
8213                                  0x128);
8214                 bnx2x_cl45_write(bp, phy,
8215                                  MDIO_PMA_DEVAD,
8216                                  MDIO_PMA_REG_MISC_CTRL0,
8217                                  0x4008);
8218                 bnx2x_cl45_write(bp, phy,
8219                                  MDIO_PMA_DEVAD,
8220                                  MDIO_PMA_REG_LRM_MODE,
8221                                  0xaaaa);
8222         }
8223         return 0;
8224 }
8225
8226 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
8227                                         struct bnx2x_phy *phy,
8228                                         u16 edc_mode)
8229 {
8230         u16 phy_identifier;
8231         u16 rom_ver2_val;
8232         bnx2x_cl45_read(bp, phy,
8233                         MDIO_PMA_DEVAD,
8234                         MDIO_PMA_REG_PHY_IDENTIFIER,
8235                         &phy_identifier);
8236
8237         bnx2x_cl45_write(bp, phy,
8238                          MDIO_PMA_DEVAD,
8239                          MDIO_PMA_REG_PHY_IDENTIFIER,
8240                          (phy_identifier & ~(1<<9)));
8241
8242         bnx2x_cl45_read(bp, phy,
8243                         MDIO_PMA_DEVAD,
8244                         MDIO_PMA_REG_ROM_VER2,
8245                         &rom_ver2_val);
8246         /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8247         bnx2x_cl45_write(bp, phy,
8248                          MDIO_PMA_DEVAD,
8249                          MDIO_PMA_REG_ROM_VER2,
8250                          (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
8251
8252         bnx2x_cl45_write(bp, phy,
8253                          MDIO_PMA_DEVAD,
8254                          MDIO_PMA_REG_PHY_IDENTIFIER,
8255                          (phy_identifier | (1<<9)));
8256
8257         return 0;
8258 }
8259
8260 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
8261                                      struct link_params *params,
8262                                      u32 action)
8263 {
8264         struct bnx2x *bp = params->bp;
8265
8266         switch (action) {
8267         case DISABLE_TX:
8268                 bnx2x_sfp_set_transmitter(params, phy, 0);
8269                 break;
8270         case ENABLE_TX:
8271                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
8272                         bnx2x_sfp_set_transmitter(params, phy, 1);
8273                 break;
8274         default:
8275                 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
8276                    action);
8277                 return;
8278         }
8279 }
8280
8281 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
8282                                            u8 gpio_mode)
8283 {
8284         struct bnx2x *bp = params->bp;
8285
8286         u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
8287                             offsetof(struct shmem_region,
8288                         dev_info.port_hw_config[params->port].sfp_ctrl)) &
8289                 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8290         switch (fault_led_gpio) {
8291         case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
8292                 return;
8293         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
8294         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
8295         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
8296         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
8297         {
8298                 u8 gpio_port = bnx2x_get_gpio_port(params);
8299                 u16 gpio_pin = fault_led_gpio -
8300                         PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8301                 DP(NETIF_MSG_LINK, "Set fault module-detected led "
8302                                    "pin %x port %x mode %x\n",
8303                                gpio_pin, gpio_port, gpio_mode);
8304                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
8305         }
8306         break;
8307         default:
8308                 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
8309                                fault_led_gpio);
8310         }
8311 }
8312
8313 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
8314                                           u8 gpio_mode)
8315 {
8316         u32 pin_cfg;
8317         u8 port = params->port;
8318         struct bnx2x *bp = params->bp;
8319         pin_cfg = (REG_RD(bp, params->shmem_base +
8320                          offsetof(struct shmem_region,
8321                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
8322                 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8323                 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8324         DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
8325                        gpio_mode, pin_cfg);
8326         bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
8327 }
8328
8329 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
8330                                            u8 gpio_mode)
8331 {
8332         struct bnx2x *bp = params->bp;
8333         DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
8334         if (CHIP_IS_E3(bp)) {
8335                 /* Low ==> if SFP+ module is supported otherwise
8336                  * High ==> if SFP+ module is not on the approved vendor list
8337                  */
8338                 bnx2x_set_e3_module_fault_led(params, gpio_mode);
8339         } else
8340                 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
8341 }
8342
8343 static void bnx2x_warpcore_power_module(struct link_params *params,
8344                                         struct bnx2x_phy *phy,
8345                                         u8 power)
8346 {
8347         u32 pin_cfg;
8348         struct bnx2x *bp = params->bp;
8349
8350         pin_cfg = (REG_RD(bp, params->shmem_base +
8351                           offsetof(struct shmem_region,
8352                         dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
8353                         PORT_HW_CFG_E3_PWR_DIS_MASK) >>
8354                         PORT_HW_CFG_E3_PWR_DIS_SHIFT;
8355
8356         if (pin_cfg == PIN_CFG_NA)
8357                 return;
8358         DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
8359                        power, pin_cfg);
8360         /* Low ==> corresponding SFP+ module is powered
8361          * high ==> the SFP+ module is powered down
8362          */
8363         bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
8364 }
8365
8366 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
8367                                     struct link_params *params)
8368 {
8369         struct bnx2x *bp = params->bp;
8370         bnx2x_warpcore_power_module(params, phy, 0);
8371         /* Put Warpcore in low power mode */
8372         REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e);
8373
8374         /* Put LCPLL in low power mode */
8375         REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1);
8376         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8377         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
8378 }
8379
8380 static void bnx2x_power_sfp_module(struct link_params *params,
8381                                    struct bnx2x_phy *phy,
8382                                    u8 power)
8383 {
8384         struct bnx2x *bp = params->bp;
8385         DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
8386
8387         switch (phy->type) {
8388         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8389         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8390                 bnx2x_8727_power_module(params->bp, phy, power);
8391                 break;
8392         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8393                 bnx2x_warpcore_power_module(params, phy, power);
8394                 break;
8395         default:
8396                 break;
8397         }
8398 }
8399 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8400                                              struct bnx2x_phy *phy,
8401                                              u16 edc_mode)
8402 {
8403         u16 val = 0;
8404         u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8405         struct bnx2x *bp = params->bp;
8406
8407         u8 lane = bnx2x_get_warpcore_lane(phy, params);
8408         /* This is a global register which controls all lanes */
8409         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8410                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8411         val &= ~(0xf << (lane << 2));
8412
8413         switch (edc_mode) {
8414         case EDC_MODE_LINEAR:
8415         case EDC_MODE_LIMITING:
8416                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8417                 break;
8418         case EDC_MODE_PASSIVE_DAC:
8419                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8420                 break;
8421         default:
8422                 break;
8423         }
8424
8425         val |= (mode << (lane << 2));
8426         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8427                          MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8428         /* A must read */
8429         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8430                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8431
8432         /* Restart microcode to re-read the new mode */
8433         bnx2x_warpcore_reset_lane(bp, phy, 1);
8434         bnx2x_warpcore_reset_lane(bp, phy, 0);
8435
8436 }
8437
8438 static void bnx2x_set_limiting_mode(struct link_params *params,
8439                                     struct bnx2x_phy *phy,
8440                                     u16 edc_mode)
8441 {
8442         switch (phy->type) {
8443         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8444                 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8445                 break;
8446         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8447         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8448                 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8449                 break;
8450         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8451                 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8452                 break;
8453         }
8454 }
8455
8456 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8457                                struct link_params *params)
8458 {
8459         struct bnx2x *bp = params->bp;
8460         u16 edc_mode;
8461         int rc = 0;
8462
8463         u32 val = REG_RD(bp, params->shmem_base +
8464                              offsetof(struct shmem_region, dev_info.
8465                                      port_feature_config[params->port].config));
8466
8467         DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8468                  params->port);
8469         /* Power up module */
8470         bnx2x_power_sfp_module(params, phy, 1);
8471         if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8472                 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8473                 return -EINVAL;
8474         } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8475                 /* check SFP+ module compatibility */
8476                 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8477                 rc = -EINVAL;
8478                 /* Turn on fault module-detected led */
8479                 bnx2x_set_sfp_module_fault_led(params,
8480                                                MISC_REGISTERS_GPIO_HIGH);
8481
8482                 /* Check if need to power down the SFP+ module */
8483                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8484                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8485                         DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8486                         bnx2x_power_sfp_module(params, phy, 0);
8487                         return rc;
8488                 }
8489         } else {
8490                 /* Turn off fault module-detected led */
8491                 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8492         }
8493
8494         /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8495          * is done automatically
8496          */
8497         bnx2x_set_limiting_mode(params, phy, edc_mode);
8498
8499         /* Enable transmit for this module if the module is approved, or
8500          * if unapproved modules should also enable the Tx laser
8501          */
8502         if (rc == 0 ||
8503             (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8504             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8505                 bnx2x_sfp_set_transmitter(params, phy, 1);
8506         else
8507                 bnx2x_sfp_set_transmitter(params, phy, 0);
8508
8509         return rc;
8510 }
8511
8512 void bnx2x_handle_module_detect_int(struct link_params *params)
8513 {
8514         struct bnx2x *bp = params->bp;
8515         struct bnx2x_phy *phy;
8516         u32 gpio_val;
8517         u8 gpio_num, gpio_port;
8518         if (CHIP_IS_E3(bp))
8519                 phy = &params->phy[INT_PHY];
8520         else
8521                 phy = &params->phy[EXT_PHY1];
8522
8523         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8524                                       params->port, &gpio_num, &gpio_port) ==
8525             -EINVAL) {
8526                 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8527                 return;
8528         }
8529
8530         /* Set valid module led off */
8531         bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8532
8533         /* Get current gpio val reflecting module plugged in / out*/
8534         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8535
8536         /* Call the handling function in case module is detected */
8537         if (gpio_val == 0) {
8538                 bnx2x_power_sfp_module(params, phy, 1);
8539                 bnx2x_set_gpio_int(bp, gpio_num,
8540                                    MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8541                                    gpio_port);
8542                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
8543                         bnx2x_sfp_module_detection(phy, params);
8544                 else
8545                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8546         } else {
8547                 u32 val = REG_RD(bp, params->shmem_base +
8548                                  offsetof(struct shmem_region, dev_info.
8549                                           port_feature_config[params->port].
8550                                           config));
8551                 bnx2x_set_gpio_int(bp, gpio_num,
8552                                    MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8553                                    gpio_port);
8554                 /* Module was plugged out.
8555                  * Disable transmit for this module
8556                  */
8557                 phy->media_type = ETH_PHY_NOT_PRESENT;
8558                 if (((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8559                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) ||
8560                     CHIP_IS_E3(bp))
8561                         bnx2x_sfp_set_transmitter(params, phy, 0);
8562         }
8563 }
8564
8565 /******************************************************************/
8566 /*              Used by 8706 and 8727                             */
8567 /******************************************************************/
8568 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8569                                  struct bnx2x_phy *phy,
8570                                  u16 alarm_status_offset,
8571                                  u16 alarm_ctrl_offset)
8572 {
8573         u16 alarm_status, val;
8574         bnx2x_cl45_read(bp, phy,
8575                         MDIO_PMA_DEVAD, alarm_status_offset,
8576                         &alarm_status);
8577         bnx2x_cl45_read(bp, phy,
8578                         MDIO_PMA_DEVAD, alarm_status_offset,
8579                         &alarm_status);
8580         /* Mask or enable the fault event. */
8581         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8582         if (alarm_status & (1<<0))
8583                 val &= ~(1<<0);
8584         else
8585                 val |= (1<<0);
8586         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8587 }
8588 /******************************************************************/
8589 /*              common BCM8706/BCM8726 PHY SECTION                */
8590 /******************************************************************/
8591 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8592                                       struct link_params *params,
8593                                       struct link_vars *vars)
8594 {
8595         u8 link_up = 0;
8596         u16 val1, val2, rx_sd, pcs_status;
8597         struct bnx2x *bp = params->bp;
8598         DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8599         /* Clear RX Alarm*/
8600         bnx2x_cl45_read(bp, phy,
8601                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8602
8603         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8604                              MDIO_PMA_LASI_TXCTRL);
8605
8606         /* clear LASI indication*/
8607         bnx2x_cl45_read(bp, phy,
8608                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8609         bnx2x_cl45_read(bp, phy,
8610                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8611         DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8612
8613         bnx2x_cl45_read(bp, phy,
8614                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8615         bnx2x_cl45_read(bp, phy,
8616                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8617         bnx2x_cl45_read(bp, phy,
8618                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8619         bnx2x_cl45_read(bp, phy,
8620                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8621
8622         DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8623                         " link_status 0x%x\n", rx_sd, pcs_status, val2);
8624         /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8625          * are set, or if the autoneg bit 1 is set
8626          */
8627         link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8628         if (link_up) {
8629                 if (val2 & (1<<1))
8630                         vars->line_speed = SPEED_1000;
8631                 else
8632                         vars->line_speed = SPEED_10000;
8633                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8634                 vars->duplex = DUPLEX_FULL;
8635         }
8636
8637         /* Capture 10G link fault. Read twice to clear stale value. */
8638         if (vars->line_speed == SPEED_10000) {
8639                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8640                             MDIO_PMA_LASI_TXSTAT, &val1);
8641                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8642                             MDIO_PMA_LASI_TXSTAT, &val1);
8643                 if (val1 & (1<<0))
8644                         vars->fault_detected = 1;
8645         }
8646
8647         return link_up;
8648 }
8649
8650 /******************************************************************/
8651 /*                      BCM8706 PHY SECTION                       */
8652 /******************************************************************/
8653 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8654                                  struct link_params *params,
8655                                  struct link_vars *vars)
8656 {
8657         u32 tx_en_mode;
8658         u16 cnt, val, tmp1;
8659         struct bnx2x *bp = params->bp;
8660
8661         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8662                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8663         /* HW reset */
8664         bnx2x_ext_phy_hw_reset(bp, params->port);
8665         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8666         bnx2x_wait_reset_complete(bp, phy, params);
8667
8668         /* Wait until fw is loaded */
8669         for (cnt = 0; cnt < 100; cnt++) {
8670                 bnx2x_cl45_read(bp, phy,
8671                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8672                 if (val)
8673                         break;
8674                 msleep(10);
8675         }
8676         DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8677         if ((params->feature_config_flags &
8678              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8679                 u8 i;
8680                 u16 reg;
8681                 for (i = 0; i < 4; i++) {
8682                         reg = MDIO_XS_8706_REG_BANK_RX0 +
8683                                 i*(MDIO_XS_8706_REG_BANK_RX1 -
8684                                    MDIO_XS_8706_REG_BANK_RX0);
8685                         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8686                         /* Clear first 3 bits of the control */
8687                         val &= ~0x7;
8688                         /* Set control bits according to configuration */
8689                         val |= (phy->rx_preemphasis[i] & 0x7);
8690                         DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8691                                    " reg 0x%x <-- val 0x%x\n", reg, val);
8692                         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8693                 }
8694         }
8695         /* Force speed */
8696         if (phy->req_line_speed == SPEED_10000) {
8697                 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8698
8699                 bnx2x_cl45_write(bp, phy,
8700                                  MDIO_PMA_DEVAD,
8701                                  MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8702                 bnx2x_cl45_write(bp, phy,
8703                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8704                                  0);
8705                 /* Arm LASI for link and Tx fault. */
8706                 bnx2x_cl45_write(bp, phy,
8707                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8708         } else {
8709                 /* Force 1Gbps using autoneg with 1G advertisement */
8710
8711                 /* Allow CL37 through CL73 */
8712                 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8713                 bnx2x_cl45_write(bp, phy,
8714                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8715
8716                 /* Enable Full-Duplex advertisement on CL37 */
8717                 bnx2x_cl45_write(bp, phy,
8718                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8719                 /* Enable CL37 AN */
8720                 bnx2x_cl45_write(bp, phy,
8721                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8722                 /* 1G support */
8723                 bnx2x_cl45_write(bp, phy,
8724                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8725
8726                 /* Enable clause 73 AN */
8727                 bnx2x_cl45_write(bp, phy,
8728                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8729                 bnx2x_cl45_write(bp, phy,
8730                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8731                                  0x0400);
8732                 bnx2x_cl45_write(bp, phy,
8733                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8734                                  0x0004);
8735         }
8736         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8737
8738         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8739          * power mode, if TX Laser is disabled
8740          */
8741
8742         tx_en_mode = REG_RD(bp, params->shmem_base +
8743                             offsetof(struct shmem_region,
8744                                 dev_info.port_hw_config[params->port].sfp_ctrl))
8745                         & PORT_HW_CFG_TX_LASER_MASK;
8746
8747         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8748                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8749                 bnx2x_cl45_read(bp, phy,
8750                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8751                 tmp1 |= 0x1;
8752                 bnx2x_cl45_write(bp, phy,
8753                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8754         }
8755
8756         return 0;
8757 }
8758
8759 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8760                                   struct link_params *params,
8761                                   struct link_vars *vars)
8762 {
8763         return bnx2x_8706_8726_read_status(phy, params, vars);
8764 }
8765
8766 /******************************************************************/
8767 /*                      BCM8726 PHY SECTION                       */
8768 /******************************************************************/
8769 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8770                                        struct link_params *params)
8771 {
8772         struct bnx2x *bp = params->bp;
8773         DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8774         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8775 }
8776
8777 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8778                                          struct link_params *params)
8779 {
8780         struct bnx2x *bp = params->bp;
8781         /* Need to wait 100ms after reset */
8782         msleep(100);
8783
8784         /* Micro controller re-boot */
8785         bnx2x_cl45_write(bp, phy,
8786                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8787
8788         /* Set soft reset */
8789         bnx2x_cl45_write(bp, phy,
8790                          MDIO_PMA_DEVAD,
8791                          MDIO_PMA_REG_GEN_CTRL,
8792                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8793
8794         bnx2x_cl45_write(bp, phy,
8795                          MDIO_PMA_DEVAD,
8796                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8797
8798         bnx2x_cl45_write(bp, phy,
8799                          MDIO_PMA_DEVAD,
8800                          MDIO_PMA_REG_GEN_CTRL,
8801                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8802
8803         /* wait for 150ms for microcode load */
8804         msleep(150);
8805
8806         /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8807         bnx2x_cl45_write(bp, phy,
8808                          MDIO_PMA_DEVAD,
8809                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8810
8811         msleep(200);
8812         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8813 }
8814
8815 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
8816                                  struct link_params *params,
8817                                  struct link_vars *vars)
8818 {
8819         struct bnx2x *bp = params->bp;
8820         u16 val1;
8821         u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
8822         if (link_up) {
8823                 bnx2x_cl45_read(bp, phy,
8824                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8825                                 &val1);
8826                 if (val1 & (1<<15)) {
8827                         DP(NETIF_MSG_LINK, "Tx is disabled\n");
8828                         link_up = 0;
8829                         vars->line_speed = 0;
8830                 }
8831         }
8832         return link_up;
8833 }
8834
8835
8836 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
8837                                   struct link_params *params,
8838                                   struct link_vars *vars)
8839 {
8840         struct bnx2x *bp = params->bp;
8841         DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
8842
8843         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
8844         bnx2x_wait_reset_complete(bp, phy, params);
8845
8846         bnx2x_8726_external_rom_boot(phy, params);
8847
8848         /* Need to call module detected on initialization since the module
8849          * detection triggered by actual module insertion might occur before
8850          * driver is loaded, and when driver is loaded, it reset all
8851          * registers, including the transmitter
8852          */
8853         bnx2x_sfp_module_detection(phy, params);
8854
8855         if (phy->req_line_speed == SPEED_1000) {
8856                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8857                 bnx2x_cl45_write(bp, phy,
8858                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8859                 bnx2x_cl45_write(bp, phy,
8860                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8861                 bnx2x_cl45_write(bp, phy,
8862                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
8863                 bnx2x_cl45_write(bp, phy,
8864                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8865                                  0x400);
8866         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8867                    (phy->speed_cap_mask &
8868                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
8869                    ((phy->speed_cap_mask &
8870                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8871                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8872                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8873                 /* Set Flow control */
8874                 bnx2x_ext_phy_set_pause(params, phy, vars);
8875                 bnx2x_cl45_write(bp, phy,
8876                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
8877                 bnx2x_cl45_write(bp, phy,
8878                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8879                 bnx2x_cl45_write(bp, phy,
8880                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
8881                 bnx2x_cl45_write(bp, phy,
8882                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8883                 bnx2x_cl45_write(bp, phy,
8884                                 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8885                 /* Enable RX-ALARM control to receive interrupt for 1G speed
8886                  * change
8887                  */
8888                 bnx2x_cl45_write(bp, phy,
8889                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
8890                 bnx2x_cl45_write(bp, phy,
8891                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8892                                  0x400);
8893
8894         } else { /* Default 10G. Set only LASI control */
8895                 bnx2x_cl45_write(bp, phy,
8896                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
8897         }
8898
8899         /* Set TX PreEmphasis if needed */
8900         if ((params->feature_config_flags &
8901              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8902                 DP(NETIF_MSG_LINK,
8903                    "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
8904                          phy->tx_preemphasis[0],
8905                          phy->tx_preemphasis[1]);
8906                 bnx2x_cl45_write(bp, phy,
8907                                  MDIO_PMA_DEVAD,
8908                                  MDIO_PMA_REG_8726_TX_CTRL1,
8909                                  phy->tx_preemphasis[0]);
8910
8911                 bnx2x_cl45_write(bp, phy,
8912                                  MDIO_PMA_DEVAD,
8913                                  MDIO_PMA_REG_8726_TX_CTRL2,
8914                                  phy->tx_preemphasis[1]);
8915         }
8916
8917         return 0;
8918
8919 }
8920
8921 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
8922                                   struct link_params *params)
8923 {
8924         struct bnx2x *bp = params->bp;
8925         DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
8926         /* Set serial boot control for external load */
8927         bnx2x_cl45_write(bp, phy,
8928                          MDIO_PMA_DEVAD,
8929                          MDIO_PMA_REG_GEN_CTRL, 0x0001);
8930 }
8931
8932 /******************************************************************/
8933 /*                      BCM8727 PHY SECTION                       */
8934 /******************************************************************/
8935
8936 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
8937                                     struct link_params *params, u8 mode)
8938 {
8939         struct bnx2x *bp = params->bp;
8940         u16 led_mode_bitmask = 0;
8941         u16 gpio_pins_bitmask = 0;
8942         u16 val;
8943         /* Only NOC flavor requires to set the LED specifically */
8944         if (!(phy->flags & FLAGS_NOC))
8945                 return;
8946         switch (mode) {
8947         case LED_MODE_FRONT_PANEL_OFF:
8948         case LED_MODE_OFF:
8949                 led_mode_bitmask = 0;
8950                 gpio_pins_bitmask = 0x03;
8951                 break;
8952         case LED_MODE_ON:
8953                 led_mode_bitmask = 0;
8954                 gpio_pins_bitmask = 0x02;
8955                 break;
8956         case LED_MODE_OPER:
8957                 led_mode_bitmask = 0x60;
8958                 gpio_pins_bitmask = 0x11;
8959                 break;
8960         }
8961         bnx2x_cl45_read(bp, phy,
8962                         MDIO_PMA_DEVAD,
8963                         MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8964                         &val);
8965         val &= 0xff8f;
8966         val |= led_mode_bitmask;
8967         bnx2x_cl45_write(bp, phy,
8968                          MDIO_PMA_DEVAD,
8969                          MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8970                          val);
8971         bnx2x_cl45_read(bp, phy,
8972                         MDIO_PMA_DEVAD,
8973                         MDIO_PMA_REG_8727_GPIO_CTRL,
8974                         &val);
8975         val &= 0xffe0;
8976         val |= gpio_pins_bitmask;
8977         bnx2x_cl45_write(bp, phy,
8978                          MDIO_PMA_DEVAD,
8979                          MDIO_PMA_REG_8727_GPIO_CTRL,
8980                          val);
8981 }
8982 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
8983                                 struct link_params *params) {
8984         u32 swap_val, swap_override;
8985         u8 port;
8986         /* The PHY reset is controlled by GPIO 1. Fake the port number
8987          * to cancel the swap done in set_gpio()
8988          */
8989         struct bnx2x *bp = params->bp;
8990         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8991         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8992         port = (swap_val && swap_override) ^ 1;
8993         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
8994                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
8995 }
8996
8997 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
8998                                   struct link_params *params,
8999                                   struct link_vars *vars)
9000 {
9001         u32 tx_en_mode;
9002         u16 tmp1, val, mod_abs, tmp2;
9003         u16 rx_alarm_ctrl_val;
9004         u16 lasi_ctrl_val;
9005         struct bnx2x *bp = params->bp;
9006         /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
9007
9008         bnx2x_wait_reset_complete(bp, phy, params);
9009         rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
9010         /* Should be 0x6 to enable XS on Tx side. */
9011         lasi_ctrl_val = 0x0006;
9012
9013         DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
9014         /* enable LASI */
9015         bnx2x_cl45_write(bp, phy,
9016                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9017                          rx_alarm_ctrl_val);
9018         bnx2x_cl45_write(bp, phy,
9019                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
9020                          0);
9021         bnx2x_cl45_write(bp, phy,
9022                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, lasi_ctrl_val);
9023
9024         /* Initially configure MOD_ABS to interrupt when module is
9025          * presence( bit 8)
9026          */
9027         bnx2x_cl45_read(bp, phy,
9028                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9029         /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
9030          * When the EDC is off it locks onto a reference clock and avoids
9031          * becoming 'lost'
9032          */
9033         mod_abs &= ~(1<<8);
9034         if (!(phy->flags & FLAGS_NOC))
9035                 mod_abs &= ~(1<<9);
9036         bnx2x_cl45_write(bp, phy,
9037                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9038
9039
9040         /* Enable/Disable PHY transmitter output */
9041         bnx2x_set_disable_pmd_transmit(params, phy, 0);
9042
9043         /* Make MOD_ABS give interrupt on change */
9044         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9045                         &val);
9046         val |= (1<<12);
9047         if (phy->flags & FLAGS_NOC)
9048                 val |= (3<<5);
9049
9050         /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
9051          * status which reflect SFP+ module over-current
9052          */
9053         if (!(phy->flags & FLAGS_NOC))
9054                 val &= 0xff8f; /* Reset bits 4-6 */
9055         bnx2x_cl45_write(bp, phy,
9056                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
9057
9058         bnx2x_8727_power_module(bp, phy, 1);
9059
9060         bnx2x_cl45_read(bp, phy,
9061                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
9062
9063         bnx2x_cl45_read(bp, phy,
9064                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
9065
9066         /* Set option 1G speed */
9067         if (phy->req_line_speed == SPEED_1000) {
9068                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9069                 bnx2x_cl45_write(bp, phy,
9070                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9071                 bnx2x_cl45_write(bp, phy,
9072                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9073                 bnx2x_cl45_read(bp, phy,
9074                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
9075                 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
9076                 /* Power down the XAUI until link is up in case of dual-media
9077                  * and 1G
9078                  */
9079                 if (DUAL_MEDIA(params)) {
9080                         bnx2x_cl45_read(bp, phy,
9081                                         MDIO_PMA_DEVAD,
9082                                         MDIO_PMA_REG_8727_PCS_GP, &val);
9083                         val |= (3<<10);
9084                         bnx2x_cl45_write(bp, phy,
9085                                          MDIO_PMA_DEVAD,
9086                                          MDIO_PMA_REG_8727_PCS_GP, val);
9087                 }
9088         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9089                    ((phy->speed_cap_mask &
9090                      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
9091                    ((phy->speed_cap_mask &
9092                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9093                    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9094
9095                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9096                 bnx2x_cl45_write(bp, phy,
9097                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
9098                 bnx2x_cl45_write(bp, phy,
9099                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
9100         } else {
9101                 /* Since the 8727 has only single reset pin, need to set the 10G
9102                  * registers although it is default
9103                  */
9104                 bnx2x_cl45_write(bp, phy,
9105                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
9106                                  0x0020);
9107                 bnx2x_cl45_write(bp, phy,
9108                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
9109                 bnx2x_cl45_write(bp, phy,
9110                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
9111                 bnx2x_cl45_write(bp, phy,
9112                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
9113                                  0x0008);
9114         }
9115
9116         /* Set 2-wire transfer rate of SFP+ module EEPROM
9117          * to 100Khz since some DACs(direct attached cables) do
9118          * not work at 400Khz.
9119          */
9120         bnx2x_cl45_write(bp, phy,
9121                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
9122                          0xa001);
9123
9124         /* Set TX PreEmphasis if needed */
9125         if ((params->feature_config_flags &
9126              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9127                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9128                            phy->tx_preemphasis[0],
9129                            phy->tx_preemphasis[1]);
9130                 bnx2x_cl45_write(bp, phy,
9131                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
9132                                  phy->tx_preemphasis[0]);
9133
9134                 bnx2x_cl45_write(bp, phy,
9135                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
9136                                  phy->tx_preemphasis[1]);
9137         }
9138
9139         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
9140          * power mode, if TX Laser is disabled
9141          */
9142         tx_en_mode = REG_RD(bp, params->shmem_base +
9143                             offsetof(struct shmem_region,
9144                                 dev_info.port_hw_config[params->port].sfp_ctrl))
9145                         & PORT_HW_CFG_TX_LASER_MASK;
9146
9147         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9148
9149                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
9150                 bnx2x_cl45_read(bp, phy,
9151                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
9152                 tmp2 |= 0x1000;
9153                 tmp2 &= 0xFFEF;
9154                 bnx2x_cl45_write(bp, phy,
9155                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
9156                 bnx2x_cl45_read(bp, phy,
9157                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9158                                 &tmp2);
9159                 bnx2x_cl45_write(bp, phy,
9160                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9161                                  (tmp2 & 0x7fff));
9162         }
9163
9164         return 0;
9165 }
9166
9167 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9168                                       struct link_params *params)
9169 {
9170         struct bnx2x *bp = params->bp;
9171         u16 mod_abs, rx_alarm_status;
9172         u32 val = REG_RD(bp, params->shmem_base +
9173                              offsetof(struct shmem_region, dev_info.
9174                                       port_feature_config[params->port].
9175                                       config));
9176         bnx2x_cl45_read(bp, phy,
9177                         MDIO_PMA_DEVAD,
9178                         MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9179         if (mod_abs & (1<<8)) {
9180
9181                 /* Module is absent */
9182                 DP(NETIF_MSG_LINK,
9183                    "MOD_ABS indication show module is absent\n");
9184                 phy->media_type = ETH_PHY_NOT_PRESENT;
9185                 /* 1. Set mod_abs to detect next module
9186                  *    presence event
9187                  * 2. Set EDC off by setting OPTXLOS signal input to low
9188                  *    (bit 9).
9189                  *    When the EDC is off it locks onto a reference clock and
9190                  *    avoids becoming 'lost'.
9191                  */
9192                 mod_abs &= ~(1<<8);
9193                 if (!(phy->flags & FLAGS_NOC))
9194                         mod_abs &= ~(1<<9);
9195                 bnx2x_cl45_write(bp, phy,
9196                                  MDIO_PMA_DEVAD,
9197                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9198
9199                 /* Clear RX alarm since it stays up as long as
9200                  * the mod_abs wasn't changed
9201                  */
9202                 bnx2x_cl45_read(bp, phy,
9203                                 MDIO_PMA_DEVAD,
9204                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9205
9206         } else {
9207                 /* Module is present */
9208                 DP(NETIF_MSG_LINK,
9209                    "MOD_ABS indication show module is present\n");
9210                 /* First disable transmitter, and if the module is ok, the
9211                  * module_detection will enable it
9212                  * 1. Set mod_abs to detect next module absent event ( bit 8)
9213                  * 2. Restore the default polarity of the OPRXLOS signal and
9214                  * this signal will then correctly indicate the presence or
9215                  * absence of the Rx signal. (bit 9)
9216                  */
9217                 mod_abs |= (1<<8);
9218                 if (!(phy->flags & FLAGS_NOC))
9219                         mod_abs |= (1<<9);
9220                 bnx2x_cl45_write(bp, phy,
9221                                  MDIO_PMA_DEVAD,
9222                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9223
9224                 /* Clear RX alarm since it stays up as long as the mod_abs
9225                  * wasn't changed. This is need to be done before calling the
9226                  * module detection, otherwise it will clear* the link update
9227                  * alarm
9228                  */
9229                 bnx2x_cl45_read(bp, phy,
9230                                 MDIO_PMA_DEVAD,
9231                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9232
9233
9234                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9235                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
9236                         bnx2x_sfp_set_transmitter(params, phy, 0);
9237
9238                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
9239                         bnx2x_sfp_module_detection(phy, params);
9240                 else
9241                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
9242         }
9243
9244         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
9245                    rx_alarm_status);
9246         /* No need to check link status in case of module plugged in/out */
9247 }
9248
9249 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9250                                  struct link_params *params,
9251                                  struct link_vars *vars)
9252
9253 {
9254         struct bnx2x *bp = params->bp;
9255         u8 link_up = 0, oc_port = params->port;
9256         u16 link_status = 0;
9257         u16 rx_alarm_status, lasi_ctrl, val1;
9258
9259         /* If PHY is not initialized, do not check link status */
9260         bnx2x_cl45_read(bp, phy,
9261                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9262                         &lasi_ctrl);
9263         if (!lasi_ctrl)
9264                 return 0;
9265
9266         /* Check the LASI on Rx */
9267         bnx2x_cl45_read(bp, phy,
9268                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
9269                         &rx_alarm_status);
9270         vars->line_speed = 0;
9271         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);
9272
9273         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
9274                              MDIO_PMA_LASI_TXCTRL);
9275
9276         bnx2x_cl45_read(bp, phy,
9277                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9278
9279         DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
9280
9281         /* Clear MSG-OUT */
9282         bnx2x_cl45_read(bp, phy,
9283                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
9284
9285         /* If a module is present and there is need to check
9286          * for over current
9287          */
9288         if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
9289                 /* Check over-current using 8727 GPIO0 input*/
9290                 bnx2x_cl45_read(bp, phy,
9291                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
9292                                 &val1);
9293
9294                 if ((val1 & (1<<8)) == 0) {
9295                         if (!CHIP_IS_E1x(bp))
9296                                 oc_port = BP_PATH(bp) + (params->port << 1);
9297                         DP(NETIF_MSG_LINK,
9298                            "8727 Power fault has been detected on port %d\n",
9299                            oc_port);
9300                         netdev_err(bp->dev, "Error: Power fault on Port %d has "
9301                                             "been detected and the power to "
9302                                             "that SFP+ module has been removed "
9303                                             "to prevent failure of the card. "
9304                                             "Please remove the SFP+ module and "
9305                                             "restart the system to clear this "
9306                                             "error.\n",
9307                          oc_port);
9308                         /* Disable all RX_ALARMs except for mod_abs */
9309                         bnx2x_cl45_write(bp, phy,
9310                                          MDIO_PMA_DEVAD,
9311                                          MDIO_PMA_LASI_RXCTRL, (1<<5));
9312
9313                         bnx2x_cl45_read(bp, phy,
9314                                         MDIO_PMA_DEVAD,
9315                                         MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9316                         /* Wait for module_absent_event */
9317                         val1 |= (1<<8);
9318                         bnx2x_cl45_write(bp, phy,
9319                                          MDIO_PMA_DEVAD,
9320                                          MDIO_PMA_REG_PHY_IDENTIFIER, val1);
9321                         /* Clear RX alarm */
9322                         bnx2x_cl45_read(bp, phy,
9323                                 MDIO_PMA_DEVAD,
9324                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9325                         return 0;
9326                 }
9327         } /* Over current check */
9328
9329         /* When module absent bit is set, check module */
9330         if (rx_alarm_status & (1<<5)) {
9331                 bnx2x_8727_handle_mod_abs(phy, params);
9332                 /* Enable all mod_abs and link detection bits */
9333                 bnx2x_cl45_write(bp, phy,
9334                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9335                                  ((1<<5) | (1<<2)));
9336         }
9337
9338         if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
9339                 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n");
9340                 bnx2x_sfp_set_transmitter(params, phy, 1);
9341         } else {
9342                 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9343                 return 0;
9344         }
9345
9346         bnx2x_cl45_read(bp, phy,
9347                         MDIO_PMA_DEVAD,
9348                         MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
9349
9350         /* Bits 0..2 --> speed detected,
9351          * Bits 13..15--> link is down
9352          */
9353         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
9354                 link_up = 1;
9355                 vars->line_speed = SPEED_10000;
9356                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
9357                            params->port);
9358         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
9359                 link_up = 1;
9360                 vars->line_speed = SPEED_1000;
9361                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
9362                            params->port);
9363         } else {
9364                 link_up = 0;
9365                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
9366                            params->port);
9367         }
9368
9369         /* Capture 10G link fault. */
9370         if (vars->line_speed == SPEED_10000) {
9371                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9372                             MDIO_PMA_LASI_TXSTAT, &val1);
9373
9374                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9375                             MDIO_PMA_LASI_TXSTAT, &val1);
9376
9377                 if (val1 & (1<<0)) {
9378                         vars->fault_detected = 1;
9379                 }
9380         }
9381
9382         if (link_up) {
9383                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9384                 vars->duplex = DUPLEX_FULL;
9385                 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9386         }
9387
9388         if ((DUAL_MEDIA(params)) &&
9389             (phy->req_line_speed == SPEED_1000)) {
9390                 bnx2x_cl45_read(bp, phy,
9391                                 MDIO_PMA_DEVAD,
9392                                 MDIO_PMA_REG_8727_PCS_GP, &val1);
9393                 /* In case of dual-media board and 1G, power up the XAUI side,
9394                  * otherwise power it down. For 10G it is done automatically
9395                  */
9396                 if (link_up)
9397                         val1 &= ~(3<<10);
9398                 else
9399                         val1 |= (3<<10);
9400                 bnx2x_cl45_write(bp, phy,
9401                                  MDIO_PMA_DEVAD,
9402                                  MDIO_PMA_REG_8727_PCS_GP, val1);
9403         }
9404         return link_up;
9405 }
9406
9407 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9408                                   struct link_params *params)
9409 {
9410         struct bnx2x *bp = params->bp;
9411
9412         /* Enable/Disable PHY transmitter output */
9413         bnx2x_set_disable_pmd_transmit(params, phy, 1);
9414
9415         /* Disable Transmitter */
9416         bnx2x_sfp_set_transmitter(params, phy, 0);
9417         /* Clear LASI */
9418         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9419
9420 }
9421
9422 /******************************************************************/
9423 /*              BCM8481/BCM84823/BCM84833 PHY SECTION             */
9424 /******************************************************************/
9425 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9426                                             struct bnx2x *bp,
9427                                             u8 port)
9428 {
9429         u16 val, fw_ver1, fw_ver2, cnt;
9430
9431         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9432                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
9433                 bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff,
9434                                 phy->ver_addr);
9435         } else {
9436                 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9437                 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9438                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
9439                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9440                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
9441                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
9442                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
9443
9444                 for (cnt = 0; cnt < 100; cnt++) {
9445                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9446                         if (val & 1)
9447                                 break;
9448                         udelay(5);
9449                 }
9450                 if (cnt == 100) {
9451                         DP(NETIF_MSG_LINK, "Unable to read 848xx "
9452                                         "phy fw version(1)\n");
9453                         bnx2x_save_spirom_version(bp, port, 0,
9454                                                   phy->ver_addr);
9455                         return;
9456                 }
9457
9458
9459                 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9460                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9461                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9462                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9463                 for (cnt = 0; cnt < 100; cnt++) {
9464                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9465                         if (val & 1)
9466                                 break;
9467                         udelay(5);
9468                 }
9469                 if (cnt == 100) {
9470                         DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw "
9471                                         "version(2)\n");
9472                         bnx2x_save_spirom_version(bp, port, 0,
9473                                                   phy->ver_addr);
9474                         return;
9475                 }
9476
9477                 /* lower 16 bits of the register SPI_FW_STATUS */
9478                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9479                 /* upper 16 bits of register SPI_FW_STATUS */
9480                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9481
9482                 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9483                                           phy->ver_addr);
9484         }
9485
9486 }
9487 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9488                                 struct bnx2x_phy *phy)
9489 {
9490         u16 val, offset;
9491
9492         /* PHYC_CTL_LED_CTL */
9493         bnx2x_cl45_read(bp, phy,
9494                         MDIO_PMA_DEVAD,
9495                         MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9496         val &= 0xFE00;
9497         val |= 0x0092;
9498
9499         bnx2x_cl45_write(bp, phy,
9500                          MDIO_PMA_DEVAD,
9501                          MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9502
9503         bnx2x_cl45_write(bp, phy,
9504                          MDIO_PMA_DEVAD,
9505                          MDIO_PMA_REG_8481_LED1_MASK,
9506                          0x80);
9507
9508         bnx2x_cl45_write(bp, phy,
9509                          MDIO_PMA_DEVAD,
9510                          MDIO_PMA_REG_8481_LED2_MASK,
9511                          0x18);
9512
9513         /* Select activity source by Tx and Rx, as suggested by PHY AE */
9514         bnx2x_cl45_write(bp, phy,
9515                          MDIO_PMA_DEVAD,
9516                          MDIO_PMA_REG_8481_LED3_MASK,
9517                          0x0006);
9518
9519         /* Select the closest activity blink rate to that in 10/100/1000 */
9520         bnx2x_cl45_write(bp, phy,
9521                         MDIO_PMA_DEVAD,
9522                         MDIO_PMA_REG_8481_LED3_BLINK,
9523                         0);
9524
9525         /* Configure the blink rate to ~15.9 Hz */
9526         bnx2x_cl45_write(bp, phy,
9527                         MDIO_PMA_DEVAD,
9528                         MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9529                         MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ);
9530
9531         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9532                 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9533         else
9534                 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9535
9536         bnx2x_cl45_read(bp, phy,
9537                         MDIO_PMA_DEVAD, offset, &val);
9538         val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/
9539         bnx2x_cl45_write(bp, phy,
9540                          MDIO_PMA_DEVAD, offset, val);
9541
9542         /* 'Interrupt Mask' */
9543         bnx2x_cl45_write(bp, phy,
9544                          MDIO_AN_DEVAD,
9545                          0xFFFB, 0xFFFD);
9546 }
9547
9548 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9549                                        struct link_params *params,
9550                                        struct link_vars *vars)
9551 {
9552         struct bnx2x *bp = params->bp;
9553         u16 autoneg_val, an_1000_val, an_10_100_val, an_10g_val;
9554
9555         if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9556                 /* Save spirom version */
9557                 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9558         }
9559         /* This phy uses the NIG latch mechanism since link indication
9560          * arrives through its LED4 and not via its LASI signal, so we
9561          * get steady signal instead of clear on read
9562          */
9563         bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9564                       1 << NIG_LATCH_BC_ENABLE_MI_INT);
9565
9566         bnx2x_cl45_write(bp, phy,
9567                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9568
9569         bnx2x_848xx_set_led(bp, phy);
9570
9571         /* set 1000 speed advertisement */
9572         bnx2x_cl45_read(bp, phy,
9573                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9574                         &an_1000_val);
9575
9576         bnx2x_ext_phy_set_pause(params, phy, vars);
9577         bnx2x_cl45_read(bp, phy,
9578                         MDIO_AN_DEVAD,
9579                         MDIO_AN_REG_8481_LEGACY_AN_ADV,
9580                         &an_10_100_val);
9581         bnx2x_cl45_read(bp, phy,
9582                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9583                         &autoneg_val);
9584         /* Disable forced speed */
9585         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9586         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9587
9588         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9589              (phy->speed_cap_mask &
9590              PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9591             (phy->req_line_speed == SPEED_1000)) {
9592                 an_1000_val |= (1<<8);
9593                 autoneg_val |= (1<<9 | 1<<12);
9594                 if (phy->req_duplex == DUPLEX_FULL)
9595                         an_1000_val |= (1<<9);
9596                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9597         } else
9598                 an_1000_val &= ~((1<<8) | (1<<9));
9599
9600         bnx2x_cl45_write(bp, phy,
9601                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9602                          an_1000_val);
9603
9604         /* set 100 speed advertisement */
9605         if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9606              (phy->speed_cap_mask &
9607               (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
9608                PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))) {
9609                 an_10_100_val |= (1<<7);
9610                 /* Enable autoneg and restart autoneg for legacy speeds */
9611                 autoneg_val |= (1<<9 | 1<<12);
9612
9613                 if (phy->req_duplex == DUPLEX_FULL)
9614                         an_10_100_val |= (1<<8);
9615                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
9616         }
9617         /* set 10 speed advertisement */
9618         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9619              (phy->speed_cap_mask &
9620               (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
9621                PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
9622              (phy->supported &
9623               (SUPPORTED_10baseT_Half |
9624                SUPPORTED_10baseT_Full)))) {
9625                 an_10_100_val |= (1<<5);
9626                 autoneg_val |= (1<<9 | 1<<12);
9627                 if (phy->req_duplex == DUPLEX_FULL)
9628                         an_10_100_val |= (1<<6);
9629                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
9630         }
9631
9632         /* Only 10/100 are allowed to work in FORCE mode */
9633         if ((phy->req_line_speed == SPEED_100) &&
9634             (phy->supported &
9635              (SUPPORTED_100baseT_Half |
9636               SUPPORTED_100baseT_Full))) {
9637                 autoneg_val |= (1<<13);
9638                 /* Enabled AUTO-MDIX when autoneg is disabled */
9639                 bnx2x_cl45_write(bp, phy,
9640                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9641                                  (1<<15 | 1<<9 | 7<<0));
9642                 /* The PHY needs this set even for forced link. */
9643                 an_10_100_val |= (1<<8) | (1<<7);
9644                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9645         }
9646         if ((phy->req_line_speed == SPEED_10) &&
9647             (phy->supported &
9648              (SUPPORTED_10baseT_Half |
9649               SUPPORTED_10baseT_Full))) {
9650                 /* Enabled AUTO-MDIX when autoneg is disabled */
9651                 bnx2x_cl45_write(bp, phy,
9652                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9653                                  (1<<15 | 1<<9 | 7<<0));
9654                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9655         }
9656
9657         bnx2x_cl45_write(bp, phy,
9658                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9659                          an_10_100_val);
9660
9661         if (phy->req_duplex == DUPLEX_FULL)
9662                 autoneg_val |= (1<<8);
9663
9664         /* Always write this if this is not 84833.
9665          * For 84833, write it only when it's a forced speed.
9666          */
9667         if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9668                 ((autoneg_val & (1<<12)) == 0))
9669                 bnx2x_cl45_write(bp, phy,
9670                          MDIO_AN_DEVAD,
9671                          MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9672
9673         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9674             (phy->speed_cap_mask &
9675              PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9676                 (phy->req_line_speed == SPEED_10000)) {
9677                         DP(NETIF_MSG_LINK, "Advertising 10G\n");
9678                         /* Restart autoneg for 10G*/
9679
9680                         bnx2x_cl45_read(bp, phy,
9681                                         MDIO_AN_DEVAD,
9682                                         MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9683                                         &an_10g_val);
9684                         bnx2x_cl45_write(bp, phy,
9685                                          MDIO_AN_DEVAD,
9686                                          MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9687                                          an_10g_val | 0x1000);
9688                         bnx2x_cl45_write(bp, phy,
9689                                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9690                                          0x3200);
9691         } else
9692                 bnx2x_cl45_write(bp, phy,
9693                                  MDIO_AN_DEVAD,
9694                                  MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9695                                  1);
9696
9697         return 0;
9698 }
9699
9700 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9701                                   struct link_params *params,
9702                                   struct link_vars *vars)
9703 {
9704         struct bnx2x *bp = params->bp;
9705         /* Restore normal power mode*/
9706         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9707                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9708
9709         /* HW reset */
9710         bnx2x_ext_phy_hw_reset(bp, params->port);
9711         bnx2x_wait_reset_complete(bp, phy, params);
9712
9713         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9714         return bnx2x_848xx_cmn_config_init(phy, params, vars);
9715 }
9716
9717 #define PHY84833_CMDHDLR_WAIT 300
9718 #define PHY84833_CMDHDLR_MAX_ARGS 5
9719 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
9720                                    struct link_params *params,
9721                    u16 fw_cmd,
9722                    u16 cmd_args[], int argc)
9723 {
9724         int idx;
9725         u16 val;
9726         struct bnx2x *bp = params->bp;
9727         /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9728         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9729                         MDIO_84833_CMD_HDLR_STATUS,
9730                         PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9731         for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9732                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9733                                 MDIO_84833_CMD_HDLR_STATUS, &val);
9734                 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
9735                         break;
9736                 msleep(1);
9737         }
9738         if (idx >= PHY84833_CMDHDLR_WAIT) {
9739                 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
9740                 return -EINVAL;
9741         }
9742
9743         /* Prepare argument(s) and issue command */
9744         for (idx = 0; idx < argc; idx++) {
9745                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9746                                 MDIO_84833_CMD_HDLR_DATA1 + idx,
9747                                 cmd_args[idx]);
9748         }
9749         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9750                         MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
9751         for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9752                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9753                                 MDIO_84833_CMD_HDLR_STATUS, &val);
9754                 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
9755                         (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
9756                         break;
9757                 msleep(1);
9758         }
9759         if ((idx >= PHY84833_CMDHDLR_WAIT) ||
9760                 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
9761                 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
9762                 return -EINVAL;
9763         }
9764         /* Gather returning data */
9765         for (idx = 0; idx < argc; idx++) {
9766                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9767                                 MDIO_84833_CMD_HDLR_DATA1 + idx,
9768                                 &cmd_args[idx]);
9769         }
9770         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9771                         MDIO_84833_CMD_HDLR_STATUS,
9772                         PHY84833_STATUS_CMD_CLEAR_COMPLETE);
9773         return 0;
9774 }
9775
9776
9777 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9778                                    struct link_params *params,
9779                                    struct link_vars *vars)
9780 {
9781         u32 pair_swap;
9782         u16 data[PHY84833_CMDHDLR_MAX_ARGS];
9783         int status;
9784         struct bnx2x *bp = params->bp;
9785
9786         /* Check for configuration. */
9787         pair_swap = REG_RD(bp, params->shmem_base +
9788                            offsetof(struct shmem_region,
9789                         dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9790                 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9791
9792         if (pair_swap == 0)
9793                 return 0;
9794
9795         /* Only the second argument is used for this command */
9796         data[1] = (u16)pair_swap;
9797
9798         status = bnx2x_84833_cmd_hdlr(phy, params,
9799                 PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS);
9800         if (status == 0)
9801                 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]);
9802
9803         return status;
9804 }
9805
9806 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
9807                                       u32 shmem_base_path[],
9808                                       u32 chip_id)
9809 {
9810         u32 reset_pin[2];
9811         u32 idx;
9812         u8 reset_gpios;
9813         if (CHIP_IS_E3(bp)) {
9814                 /* Assume that these will be GPIOs, not EPIOs. */
9815                 for (idx = 0; idx < 2; idx++) {
9816                         /* Map config param to register bit. */
9817                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9818                                 offsetof(struct shmem_region,
9819                                 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9820                         reset_pin[idx] = (reset_pin[idx] &
9821                                 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9822                                 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9823                         reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9824                         reset_pin[idx] = (1 << reset_pin[idx]);
9825                 }
9826                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9827         } else {
9828                 /* E2, look from diff place of shmem. */
9829                 for (idx = 0; idx < 2; idx++) {
9830                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9831                                 offsetof(struct shmem_region,
9832                                 dev_info.port_hw_config[0].default_cfg));
9833                         reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9834                         reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9835                         reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9836                         reset_pin[idx] = (1 << reset_pin[idx]);
9837                 }
9838                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9839         }
9840
9841         return reset_gpios;
9842 }
9843
9844 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
9845                                 struct link_params *params)
9846 {
9847         struct bnx2x *bp = params->bp;
9848         u8 reset_gpios;
9849         u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
9850                                 offsetof(struct shmem2_region,
9851                                 other_shmem_base_addr));
9852
9853         u32 shmem_base_path[2];
9854
9855         /* Work around for 84833 LED failure inside RESET status */
9856         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
9857                 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9858                 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
9859         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
9860                 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
9861                 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
9862
9863         shmem_base_path[0] = params->shmem_base;
9864         shmem_base_path[1] = other_shmem_base_addr;
9865
9866         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
9867                                                   params->chip_id);
9868
9869         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9870         udelay(10);
9871         DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
9872                 reset_gpios);
9873
9874         return 0;
9875 }
9876
9877 static int bnx2x_8483x_eee_timers(struct link_params *params,
9878                                    struct link_vars *vars)
9879 {
9880         u32 eee_idle = 0, eee_mode;
9881         struct bnx2x *bp = params->bp;
9882
9883         eee_idle = bnx2x_eee_calc_timer(params);
9884
9885         if (eee_idle) {
9886                 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
9887                        eee_idle);
9888         } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) &&
9889                    (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) &&
9890                    (params->eee_mode & EEE_MODE_OUTPUT_TIME)) {
9891                 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n");
9892                 return -EINVAL;
9893         }
9894
9895         vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
9896         if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
9897                 /* eee_idle in 1u --> eee_status in 16u */
9898                 eee_idle >>= 4;
9899                 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
9900                                     SHMEM_EEE_TIME_OUTPUT_BIT;
9901         } else {
9902                 if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode))
9903                         return -EINVAL;
9904                 vars->eee_status |= eee_mode;
9905         }
9906
9907         return 0;
9908 }
9909
9910 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy,
9911                                    struct link_params *params,
9912                                    struct link_vars *vars)
9913 {
9914         int rc;
9915         struct bnx2x *bp = params->bp;
9916         u16 cmd_args = 0;
9917
9918         DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n");
9919
9920         /* Make Certain LPI is disabled */
9921         REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
9922         REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 0);
9923
9924         /* Prevent Phy from working in EEE and advertising it */
9925         rc = bnx2x_84833_cmd_hdlr(phy, params,
9926                 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
9927         if (rc != 0) {
9928                 DP(NETIF_MSG_LINK, "EEE disable failed.\n");
9929                 return rc;
9930         }
9931
9932         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0);
9933         vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
9934
9935         return 0;
9936 }
9937
9938 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy,
9939                                    struct link_params *params,
9940                                    struct link_vars *vars)
9941 {
9942         int rc;
9943         struct bnx2x *bp = params->bp;
9944         u16 cmd_args = 1;
9945
9946         DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n");
9947
9948         rc = bnx2x_84833_cmd_hdlr(phy, params,
9949                 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
9950         if (rc != 0) {
9951                 DP(NETIF_MSG_LINK, "EEE enable failed.\n");
9952                 return rc;
9953         }
9954
9955         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x8);
9956
9957         /* Mask events preventing LPI generation */
9958         REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
9959
9960         vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
9961         vars->eee_status |= (SHMEM_EEE_10G_ADV << SHMEM_EEE_ADV_STATUS_SHIFT);
9962
9963         return 0;
9964 }
9965
9966 #define PHY84833_CONSTANT_LATENCY 1193
9967 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
9968                                    struct link_params *params,
9969                                    struct link_vars *vars)
9970 {
9971         struct bnx2x *bp = params->bp;
9972         u8 port, initialize = 1;
9973         u16 val;
9974         u32 actual_phy_selection, cms_enable;
9975         u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
9976         int rc = 0;
9977
9978         msleep(1);
9979
9980         if (!(CHIP_IS_E1(bp)))
9981                 port = BP_PATH(bp);
9982         else
9983                 port = params->port;
9984
9985         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9986                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9987                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
9988                                port);
9989         } else {
9990                 /* MDIO reset */
9991                 bnx2x_cl45_write(bp, phy,
9992                                 MDIO_PMA_DEVAD,
9993                                 MDIO_PMA_REG_CTRL, 0x8000);
9994         }
9995
9996         bnx2x_wait_reset_complete(bp, phy, params);
9997
9998         /* Wait for GPHY to come out of reset */
9999         msleep(50);
10000         if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
10001                 /* BCM84823 requires that XGXS links up first @ 10G for normal
10002                  * behavior.
10003                  */
10004                 u16 temp;
10005                 temp = vars->line_speed;
10006                 vars->line_speed = SPEED_10000;
10007                 bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
10008                 bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
10009                 vars->line_speed = temp;
10010         }
10011
10012         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10013                         MDIO_CTL_REG_84823_MEDIA, &val);
10014         val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10015                  MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
10016                  MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
10017                  MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
10018                  MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
10019
10020         if (CHIP_IS_E3(bp)) {
10021                 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10022                          MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
10023         } else {
10024                 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
10025                         MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
10026         }
10027
10028         actual_phy_selection = bnx2x_phy_selection(params);
10029
10030         switch (actual_phy_selection) {
10031         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
10032                 /* Do nothing. Essentially this is like the priority copper */
10033                 break;
10034         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
10035                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
10036                 break;
10037         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
10038                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
10039                 break;
10040         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
10041                 /* Do nothing here. The first PHY won't be initialized at all */
10042                 break;
10043         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
10044                 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
10045                 initialize = 0;
10046                 break;
10047         }
10048         if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
10049                 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
10050
10051         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10052                          MDIO_CTL_REG_84823_MEDIA, val);
10053         DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
10054                    params->multi_phy_config, val);
10055
10056         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
10057                 bnx2x_84833_pair_swap_cfg(phy, params, vars);
10058
10059                 /* Keep AutogrEEEn disabled. */
10060                 cmd_args[0] = 0x0;
10061                 cmd_args[1] = 0x0;
10062                 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
10063                 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
10064                 rc = bnx2x_84833_cmd_hdlr(phy, params,
10065                         PHY84833_CMD_SET_EEE_MODE, cmd_args,
10066                         PHY84833_CMDHDLR_MAX_ARGS);
10067                 if (rc != 0)
10068                         DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
10069         }
10070         if (initialize)
10071                 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
10072         else
10073                 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
10074         /* 84833 PHY has a better feature and doesn't need to support this. */
10075         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10076                 cms_enable = REG_RD(bp, params->shmem_base +
10077                         offsetof(struct shmem_region,
10078                         dev_info.port_hw_config[params->port].default_cfg)) &
10079                         PORT_HW_CFG_ENABLE_CMS_MASK;
10080
10081                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10082                                 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
10083                 if (cms_enable)
10084                         val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
10085                 else
10086                         val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
10087                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10088                                  MDIO_CTL_REG_84823_USER_CTRL_REG, val);
10089         }
10090
10091         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10092                         MDIO_84833_TOP_CFG_FW_REV, &val);
10093
10094         /* Configure EEE support */
10095         if ((val >= MDIO_84833_TOP_CFG_FW_EEE) && bnx2x_eee_has_cap(params)) {
10096                 phy->flags |= FLAGS_EEE_10GBT;
10097                 vars->eee_status |= SHMEM_EEE_10G_ADV <<
10098                                     SHMEM_EEE_SUPPORTED_SHIFT;
10099                 /* Propogate params' bits --> vars (for migration exposure) */
10100                 if (params->eee_mode & EEE_MODE_ENABLE_LPI)
10101                         vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
10102                 else
10103                         vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
10104
10105                 if (params->eee_mode & EEE_MODE_ADV_LPI)
10106                         vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
10107                 else
10108                         vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
10109
10110                 rc = bnx2x_8483x_eee_timers(params, vars);
10111                 if (rc != 0) {
10112                         DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10113                         bnx2x_8483x_disable_eee(phy, params, vars);
10114                         return rc;
10115                 }
10116
10117                 if ((params->req_duplex[actual_phy_selection] == DUPLEX_FULL) &&
10118                     (params->eee_mode & EEE_MODE_ADV_LPI) &&
10119                     (bnx2x_eee_calc_timer(params) ||
10120                      !(params->eee_mode & EEE_MODE_ENABLE_LPI)))
10121                         rc = bnx2x_8483x_enable_eee(phy, params, vars);
10122                 else
10123                         rc = bnx2x_8483x_disable_eee(phy, params, vars);
10124                 if (rc != 0) {
10125                         DP(NETIF_MSG_LINK, "Failed to set EEE advertisment\n");
10126                         return rc;
10127                 }
10128         } else {
10129                 phy->flags &= ~FLAGS_EEE_10GBT;
10130                 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
10131         }
10132
10133         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
10134                 /* Bring PHY out of super isolate mode as the final step. */
10135                 bnx2x_cl45_read(bp, phy,
10136                                 MDIO_CTL_DEVAD,
10137                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
10138                 val &= ~MDIO_84833_SUPER_ISOLATE;
10139                 bnx2x_cl45_write(bp, phy,
10140                                 MDIO_CTL_DEVAD,
10141                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
10142         }
10143         return rc;
10144 }
10145
10146 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
10147                                   struct link_params *params,
10148                                   struct link_vars *vars)
10149 {
10150         struct bnx2x *bp = params->bp;
10151         u16 val, val1, val2;
10152         u8 link_up = 0;
10153
10154
10155         /* Check 10G-BaseT link status */
10156         /* Check PMD signal ok */
10157         bnx2x_cl45_read(bp, phy,
10158                         MDIO_AN_DEVAD, 0xFFFA, &val1);
10159         bnx2x_cl45_read(bp, phy,
10160                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
10161                         &val2);
10162         DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
10163
10164         /* Check link 10G */
10165         if (val2 & (1<<11)) {
10166                 vars->line_speed = SPEED_10000;
10167                 vars->duplex = DUPLEX_FULL;
10168                 link_up = 1;
10169                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10170         } else { /* Check Legacy speed link */
10171                 u16 legacy_status, legacy_speed;
10172
10173                 /* Enable expansion register 0x42 (Operation mode status) */
10174                 bnx2x_cl45_write(bp, phy,
10175                                  MDIO_AN_DEVAD,
10176                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
10177
10178                 /* Get legacy speed operation status */
10179                 bnx2x_cl45_read(bp, phy,
10180                                 MDIO_AN_DEVAD,
10181                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
10182                                 &legacy_status);
10183
10184                 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
10185                    legacy_status);
10186                 link_up = ((legacy_status & (1<<11)) == (1<<11));
10187                 if (link_up) {
10188                         legacy_speed = (legacy_status & (3<<9));
10189                         if (legacy_speed == (0<<9))
10190                                 vars->line_speed = SPEED_10;
10191                         else if (legacy_speed == (1<<9))
10192                                 vars->line_speed = SPEED_100;
10193                         else if (legacy_speed == (2<<9))
10194                                 vars->line_speed = SPEED_1000;
10195                         else /* Should not happen */
10196                                 vars->line_speed = 0;
10197
10198                         if (legacy_status & (1<<8))
10199                                 vars->duplex = DUPLEX_FULL;
10200                         else
10201                                 vars->duplex = DUPLEX_HALF;
10202
10203                         DP(NETIF_MSG_LINK,
10204                            "Link is up in %dMbps, is_duplex_full= %d\n",
10205                            vars->line_speed,
10206                            (vars->duplex == DUPLEX_FULL));
10207                         /* Check legacy speed AN resolution */
10208                         bnx2x_cl45_read(bp, phy,
10209                                         MDIO_AN_DEVAD,
10210                                         MDIO_AN_REG_8481_LEGACY_MII_STATUS,
10211                                         &val);
10212                         if (val & (1<<5))
10213                                 vars->link_status |=
10214                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10215                         bnx2x_cl45_read(bp, phy,
10216                                         MDIO_AN_DEVAD,
10217                                         MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
10218                                         &val);
10219                         if ((val & (1<<0)) == 0)
10220                                 vars->link_status |=
10221                                         LINK_STATUS_PARALLEL_DETECTION_USED;
10222                 }
10223         }
10224         if (link_up) {
10225                 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
10226                            vars->line_speed);
10227                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10228
10229                 /* Read LP advertised speeds */
10230                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10231                                 MDIO_AN_REG_CL37_FC_LP, &val);
10232                 if (val & (1<<5))
10233                         vars->link_status |=
10234                                 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10235                 if (val & (1<<6))
10236                         vars->link_status |=
10237                                 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10238                 if (val & (1<<7))
10239                         vars->link_status |=
10240                                 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10241                 if (val & (1<<8))
10242                         vars->link_status |=
10243                                 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10244                 if (val & (1<<9))
10245                         vars->link_status |=
10246                                 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10247
10248                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10249                                 MDIO_AN_REG_1000T_STATUS, &val);
10250
10251                 if (val & (1<<10))
10252                         vars->link_status |=
10253                                 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10254                 if (val & (1<<11))
10255                         vars->link_status |=
10256                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10257
10258                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10259                                 MDIO_AN_REG_MASTER_STATUS, &val);
10260
10261                 if (val & (1<<11))
10262                         vars->link_status |=
10263                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10264
10265                 /* Determine if EEE was negotiated */
10266                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
10267                         u32 eee_shmem = 0;
10268
10269                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10270                                         MDIO_AN_REG_EEE_ADV, &val1);
10271                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10272                                         MDIO_AN_REG_LP_EEE_ADV, &val2);
10273                         if ((val1 & val2) & 0x8) {
10274                                 DP(NETIF_MSG_LINK, "EEE negotiated\n");
10275                                 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
10276                         }
10277
10278                         if (val2 & 0x12)
10279                                 eee_shmem |= SHMEM_EEE_100M_ADV;
10280                         if (val2 & 0x4)
10281                                 eee_shmem |= SHMEM_EEE_1G_ADV;
10282                         if (val2 & 0x68)
10283                                 eee_shmem |= SHMEM_EEE_10G_ADV;
10284
10285                         vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
10286                         vars->eee_status |= (eee_shmem <<
10287                                              SHMEM_EEE_LP_ADV_STATUS_SHIFT);
10288                 }
10289         }
10290
10291         return link_up;
10292 }
10293
10294
10295 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
10296 {
10297         int status = 0;
10298         u32 spirom_ver;
10299         spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
10300         status = bnx2x_format_ver(spirom_ver, str, len);
10301         return status;
10302 }
10303
10304 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
10305                                 struct link_params *params)
10306 {
10307         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10308                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
10309         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10310                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
10311 }
10312
10313 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
10314                                         struct link_params *params)
10315 {
10316         bnx2x_cl45_write(params->bp, phy,
10317                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
10318         bnx2x_cl45_write(params->bp, phy,
10319                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
10320 }
10321
10322 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
10323                                    struct link_params *params)
10324 {
10325         struct bnx2x *bp = params->bp;
10326         u8 port;
10327         u16 val16;
10328
10329         if (!(CHIP_IS_E1x(bp)))
10330                 port = BP_PATH(bp);
10331         else
10332                 port = params->port;
10333
10334         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10335                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10336                                MISC_REGISTERS_GPIO_OUTPUT_LOW,
10337                                port);
10338         } else {
10339                 bnx2x_cl45_read(bp, phy,
10340                                 MDIO_CTL_DEVAD,
10341                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
10342                 val16 |= MDIO_84833_SUPER_ISOLATE;
10343                 bnx2x_cl45_write(bp, phy,
10344                                  MDIO_CTL_DEVAD,
10345                                  MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
10346         }
10347 }
10348
10349 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
10350                                      struct link_params *params, u8 mode)
10351 {
10352         struct bnx2x *bp = params->bp;
10353         u16 val;
10354         u8 port;
10355
10356         if (!(CHIP_IS_E1x(bp)))
10357                 port = BP_PATH(bp);
10358         else
10359                 port = params->port;
10360
10361         switch (mode) {
10362         case LED_MODE_OFF:
10363
10364                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
10365
10366                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10367                     SHARED_HW_CFG_LED_EXTPHY1) {
10368
10369                         /* Set LED masks */
10370                         bnx2x_cl45_write(bp, phy,
10371                                         MDIO_PMA_DEVAD,
10372                                         MDIO_PMA_REG_8481_LED1_MASK,
10373                                         0x0);
10374
10375                         bnx2x_cl45_write(bp, phy,
10376                                         MDIO_PMA_DEVAD,
10377                                         MDIO_PMA_REG_8481_LED2_MASK,
10378                                         0x0);
10379
10380                         bnx2x_cl45_write(bp, phy,
10381                                         MDIO_PMA_DEVAD,
10382                                         MDIO_PMA_REG_8481_LED3_MASK,
10383                                         0x0);
10384
10385                         bnx2x_cl45_write(bp, phy,
10386                                         MDIO_PMA_DEVAD,
10387                                         MDIO_PMA_REG_8481_LED5_MASK,
10388                                         0x0);
10389
10390                 } else {
10391                         bnx2x_cl45_write(bp, phy,
10392                                          MDIO_PMA_DEVAD,
10393                                          MDIO_PMA_REG_8481_LED1_MASK,
10394                                          0x0);
10395                 }
10396                 break;
10397         case LED_MODE_FRONT_PANEL_OFF:
10398
10399                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
10400                    port);
10401
10402                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10403                     SHARED_HW_CFG_LED_EXTPHY1) {
10404
10405                         /* Set LED masks */
10406                         bnx2x_cl45_write(bp, phy,
10407                                          MDIO_PMA_DEVAD,
10408                                          MDIO_PMA_REG_8481_LED1_MASK,
10409                                          0x0);
10410
10411                         bnx2x_cl45_write(bp, phy,
10412                                          MDIO_PMA_DEVAD,
10413                                          MDIO_PMA_REG_8481_LED2_MASK,
10414                                          0x0);
10415
10416                         bnx2x_cl45_write(bp, phy,
10417                                          MDIO_PMA_DEVAD,
10418                                          MDIO_PMA_REG_8481_LED3_MASK,
10419                                          0x0);
10420
10421                         bnx2x_cl45_write(bp, phy,
10422                                          MDIO_PMA_DEVAD,
10423                                          MDIO_PMA_REG_8481_LED5_MASK,
10424                                          0x20);
10425
10426                 } else {
10427                         bnx2x_cl45_write(bp, phy,
10428                                          MDIO_PMA_DEVAD,
10429                                          MDIO_PMA_REG_8481_LED1_MASK,
10430                                          0x0);
10431                 }
10432                 break;
10433         case LED_MODE_ON:
10434
10435                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
10436
10437                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10438                     SHARED_HW_CFG_LED_EXTPHY1) {
10439                         /* Set control reg */
10440                         bnx2x_cl45_read(bp, phy,
10441                                         MDIO_PMA_DEVAD,
10442                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10443                                         &val);
10444                         val &= 0x8000;
10445                         val |= 0x2492;
10446
10447                         bnx2x_cl45_write(bp, phy,
10448                                          MDIO_PMA_DEVAD,
10449                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10450                                          val);
10451
10452                         /* Set LED masks */
10453                         bnx2x_cl45_write(bp, phy,
10454                                          MDIO_PMA_DEVAD,
10455                                          MDIO_PMA_REG_8481_LED1_MASK,
10456                                          0x0);
10457
10458                         bnx2x_cl45_write(bp, phy,
10459                                          MDIO_PMA_DEVAD,
10460                                          MDIO_PMA_REG_8481_LED2_MASK,
10461                                          0x20);
10462
10463                         bnx2x_cl45_write(bp, phy,
10464                                          MDIO_PMA_DEVAD,
10465                                          MDIO_PMA_REG_8481_LED3_MASK,
10466                                          0x20);
10467
10468                         bnx2x_cl45_write(bp, phy,
10469                                          MDIO_PMA_DEVAD,
10470                                          MDIO_PMA_REG_8481_LED5_MASK,
10471                                          0x0);
10472                 } else {
10473                         bnx2x_cl45_write(bp, phy,
10474                                          MDIO_PMA_DEVAD,
10475                                          MDIO_PMA_REG_8481_LED1_MASK,
10476                                          0x20);
10477                 }
10478                 break;
10479
10480         case LED_MODE_OPER:
10481
10482                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
10483
10484                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10485                     SHARED_HW_CFG_LED_EXTPHY1) {
10486
10487                         /* Set control reg */
10488                         bnx2x_cl45_read(bp, phy,
10489                                         MDIO_PMA_DEVAD,
10490                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10491                                         &val);
10492
10493                         if (!((val &
10494                                MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10495                           >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
10496                                 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
10497                                 bnx2x_cl45_write(bp, phy,
10498                                                  MDIO_PMA_DEVAD,
10499                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
10500                                                  0xa492);
10501                         }
10502
10503                         /* Set LED masks */
10504                         bnx2x_cl45_write(bp, phy,
10505                                          MDIO_PMA_DEVAD,
10506                                          MDIO_PMA_REG_8481_LED1_MASK,
10507                                          0x10);
10508
10509                         bnx2x_cl45_write(bp, phy,
10510                                          MDIO_PMA_DEVAD,
10511                                          MDIO_PMA_REG_8481_LED2_MASK,
10512                                          0x80);
10513
10514                         bnx2x_cl45_write(bp, phy,
10515                                          MDIO_PMA_DEVAD,
10516                                          MDIO_PMA_REG_8481_LED3_MASK,
10517                                          0x98);
10518
10519                         bnx2x_cl45_write(bp, phy,
10520                                          MDIO_PMA_DEVAD,
10521                                          MDIO_PMA_REG_8481_LED5_MASK,
10522                                          0x40);
10523
10524                 } else {
10525                         bnx2x_cl45_write(bp, phy,
10526                                          MDIO_PMA_DEVAD,
10527                                          MDIO_PMA_REG_8481_LED1_MASK,
10528                                          0x80);
10529
10530                         /* Tell LED3 to blink on source */
10531                         bnx2x_cl45_read(bp, phy,
10532                                         MDIO_PMA_DEVAD,
10533                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10534                                         &val);
10535                         val &= ~(7<<6);
10536                         val |= (1<<6); /* A83B[8:6]= 1 */
10537                         bnx2x_cl45_write(bp, phy,
10538                                          MDIO_PMA_DEVAD,
10539                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10540                                          val);
10541                 }
10542                 break;
10543         }
10544
10545         /* This is a workaround for E3+84833 until autoneg
10546          * restart is fixed in f/w
10547          */
10548         if (CHIP_IS_E3(bp)) {
10549                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
10550                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10551         }
10552 }
10553
10554 /******************************************************************/
10555 /*                      54618SE PHY SECTION                       */
10556 /******************************************************************/
10557 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10558                                                struct link_params *params,
10559                                                struct link_vars *vars)
10560 {
10561         struct bnx2x *bp = params->bp;
10562         u8 port;
10563         u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10564         u32 cfg_pin;
10565
10566         DP(NETIF_MSG_LINK, "54618SE cfg init\n");
10567         usleep_range(1000, 1000);
10568
10569         /* This works with E3 only, no need to check the chip
10570          * before determining the port.
10571          */
10572         port = params->port;
10573
10574         cfg_pin = (REG_RD(bp, params->shmem_base +
10575                         offsetof(struct shmem_region,
10576                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10577                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10578                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10579
10580         /* Drive pin high to bring the GPHY out of reset. */
10581         bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10582
10583         /* wait for GPHY to reset */
10584         msleep(50);
10585
10586         /* reset phy */
10587         bnx2x_cl22_write(bp, phy,
10588                          MDIO_PMA_REG_CTRL, 0x8000);
10589         bnx2x_wait_reset_complete(bp, phy, params);
10590
10591         /* Wait for GPHY to reset */
10592         msleep(50);
10593
10594         /* Configure LED4: set to INTR (0x6). */
10595         /* Accessing shadow register 0xe. */
10596         bnx2x_cl22_write(bp, phy,
10597                         MDIO_REG_GPHY_SHADOW,
10598                         MDIO_REG_GPHY_SHADOW_LED_SEL2);
10599         bnx2x_cl22_read(bp, phy,
10600                         MDIO_REG_GPHY_SHADOW,
10601                         &temp);
10602         temp &= ~(0xf << 4);
10603         temp |= (0x6 << 4);
10604         bnx2x_cl22_write(bp, phy,
10605                         MDIO_REG_GPHY_SHADOW,
10606                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10607         /* Configure INTR based on link status change. */
10608         bnx2x_cl22_write(bp, phy,
10609                         MDIO_REG_INTR_MASK,
10610                         ~MDIO_REG_INTR_MASK_LINK_STATUS);
10611
10612         /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10613         bnx2x_cl22_write(bp, phy,
10614                         MDIO_REG_GPHY_SHADOW,
10615                         MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10616         bnx2x_cl22_read(bp, phy,
10617                         MDIO_REG_GPHY_SHADOW,
10618                         &temp);
10619         temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10620         bnx2x_cl22_write(bp, phy,
10621                         MDIO_REG_GPHY_SHADOW,
10622                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10623
10624         /* Set up fc */
10625         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10626         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10627         fc_val = 0;
10628         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10629                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10630                 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10631
10632         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10633                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10634                 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10635
10636         /* read all advertisement */
10637         bnx2x_cl22_read(bp, phy,
10638                         0x09,
10639                         &an_1000_val);
10640
10641         bnx2x_cl22_read(bp, phy,
10642                         0x04,
10643                         &an_10_100_val);
10644
10645         bnx2x_cl22_read(bp, phy,
10646                         MDIO_PMA_REG_CTRL,
10647                         &autoneg_val);
10648
10649         /* Disable forced speed */
10650         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10651         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10652                            (1<<11));
10653
10654         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10655                         (phy->speed_cap_mask &
10656                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10657                         (phy->req_line_speed == SPEED_1000)) {
10658                 an_1000_val |= (1<<8);
10659                 autoneg_val |= (1<<9 | 1<<12);
10660                 if (phy->req_duplex == DUPLEX_FULL)
10661                         an_1000_val |= (1<<9);
10662                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10663         } else
10664                 an_1000_val &= ~((1<<8) | (1<<9));
10665
10666         bnx2x_cl22_write(bp, phy,
10667                         0x09,
10668                         an_1000_val);
10669         bnx2x_cl22_read(bp, phy,
10670                         0x09,
10671                         &an_1000_val);
10672
10673         /* set 100 speed advertisement */
10674         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10675                         (phy->speed_cap_mask &
10676                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
10677                         PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10678                 an_10_100_val |= (1<<7);
10679                 /* Enable autoneg and restart autoneg for legacy speeds */
10680                 autoneg_val |= (1<<9 | 1<<12);
10681
10682                 if (phy->req_duplex == DUPLEX_FULL)
10683                         an_10_100_val |= (1<<8);
10684                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
10685         }
10686
10687         /* set 10 speed advertisement */
10688         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10689                         (phy->speed_cap_mask &
10690                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
10691                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10692                 an_10_100_val |= (1<<5);
10693                 autoneg_val |= (1<<9 | 1<<12);
10694                 if (phy->req_duplex == DUPLEX_FULL)
10695                         an_10_100_val |= (1<<6);
10696                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
10697         }
10698
10699         /* Only 10/100 are allowed to work in FORCE mode */
10700         if (phy->req_line_speed == SPEED_100) {
10701                 autoneg_val |= (1<<13);
10702                 /* Enabled AUTO-MDIX when autoneg is disabled */
10703                 bnx2x_cl22_write(bp, phy,
10704                                 0x18,
10705                                 (1<<15 | 1<<9 | 7<<0));
10706                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10707         }
10708         if (phy->req_line_speed == SPEED_10) {
10709                 /* Enabled AUTO-MDIX when autoneg is disabled */
10710                 bnx2x_cl22_write(bp, phy,
10711                                 0x18,
10712                                 (1<<15 | 1<<9 | 7<<0));
10713                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10714         }
10715
10716         /* Check if we should turn on Auto-GrEEEn */
10717         bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &temp);
10718         if (temp == MDIO_REG_GPHY_ID_54618SE) {
10719                 if (params->feature_config_flags &
10720                     FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10721                         temp = 6;
10722                         DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10723                 } else {
10724                         temp = 0;
10725                         DP(NETIF_MSG_LINK, "Disabling Auto-GrEEEn\n");
10726                 }
10727                 bnx2x_cl22_write(bp, phy,
10728                                  MDIO_REG_GPHY_CL45_ADDR_REG, MDIO_AN_DEVAD);
10729                 bnx2x_cl22_write(bp, phy,
10730                                  MDIO_REG_GPHY_CL45_DATA_REG,
10731                                  MDIO_REG_GPHY_EEE_ADV);
10732                 bnx2x_cl22_write(bp, phy,
10733                                  MDIO_REG_GPHY_CL45_ADDR_REG,
10734                                  (0x1 << 14) | MDIO_AN_DEVAD);
10735                 bnx2x_cl22_write(bp, phy,
10736                                  MDIO_REG_GPHY_CL45_DATA_REG,
10737                                  temp);
10738         }
10739
10740         bnx2x_cl22_write(bp, phy,
10741                         0x04,
10742                         an_10_100_val | fc_val);
10743
10744         if (phy->req_duplex == DUPLEX_FULL)
10745                 autoneg_val |= (1<<8);
10746
10747         bnx2x_cl22_write(bp, phy,
10748                         MDIO_PMA_REG_CTRL, autoneg_val);
10749
10750         return 0;
10751 }
10752
10753
10754 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy,
10755                                        struct link_params *params, u8 mode)
10756 {
10757         struct bnx2x *bp = params->bp;
10758         u16 temp;
10759
10760         bnx2x_cl22_write(bp, phy,
10761                 MDIO_REG_GPHY_SHADOW,
10762                 MDIO_REG_GPHY_SHADOW_LED_SEL1);
10763         bnx2x_cl22_read(bp, phy,
10764                 MDIO_REG_GPHY_SHADOW,
10765                 &temp);
10766         temp &= 0xff00;
10767
10768         DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode);
10769         switch (mode) {
10770         case LED_MODE_FRONT_PANEL_OFF:
10771         case LED_MODE_OFF:
10772                 temp |= 0x00ee;
10773                 break;
10774         case LED_MODE_OPER:
10775                 temp |= 0x0001;
10776                 break;
10777         case LED_MODE_ON:
10778                 temp |= 0x00ff;
10779                 break;
10780         default:
10781                 break;
10782         }
10783         bnx2x_cl22_write(bp, phy,
10784                 MDIO_REG_GPHY_SHADOW,
10785                 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10786         return;
10787 }
10788
10789
10790 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10791                                      struct link_params *params)
10792 {
10793         struct bnx2x *bp = params->bp;
10794         u32 cfg_pin;
10795         u8 port;
10796
10797         /* In case of no EPIO routed to reset the GPHY, put it
10798          * in low power mode.
10799          */
10800         bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
10801         /* This works with E3 only, no need to check the chip
10802          * before determining the port.
10803          */
10804         port = params->port;
10805         cfg_pin = (REG_RD(bp, params->shmem_base +
10806                         offsetof(struct shmem_region,
10807                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10808                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10809                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10810
10811         /* Drive pin low to put GPHY in reset. */
10812         bnx2x_set_cfg_pin(bp, cfg_pin, 0);
10813 }
10814
10815 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
10816                                     struct link_params *params,
10817                                     struct link_vars *vars)
10818 {
10819         struct bnx2x *bp = params->bp;
10820         u16 val;
10821         u8 link_up = 0;
10822         u16 legacy_status, legacy_speed;
10823
10824         /* Get speed operation status */
10825         bnx2x_cl22_read(bp, phy,
10826                         0x19,
10827                         &legacy_status);
10828         DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
10829
10830         /* Read status to clear the PHY interrupt. */
10831         bnx2x_cl22_read(bp, phy,
10832                         MDIO_REG_INTR_STATUS,
10833                         &val);
10834
10835         link_up = ((legacy_status & (1<<2)) == (1<<2));
10836
10837         if (link_up) {
10838                 legacy_speed = (legacy_status & (7<<8));
10839                 if (legacy_speed == (7<<8)) {
10840                         vars->line_speed = SPEED_1000;
10841                         vars->duplex = DUPLEX_FULL;
10842                 } else if (legacy_speed == (6<<8)) {
10843                         vars->line_speed = SPEED_1000;
10844                         vars->duplex = DUPLEX_HALF;
10845                 } else if (legacy_speed == (5<<8)) {
10846                         vars->line_speed = SPEED_100;
10847                         vars->duplex = DUPLEX_FULL;
10848                 }
10849                 /* Omitting 100Base-T4 for now */
10850                 else if (legacy_speed == (3<<8)) {
10851                         vars->line_speed = SPEED_100;
10852                         vars->duplex = DUPLEX_HALF;
10853                 } else if (legacy_speed == (2<<8)) {
10854                         vars->line_speed = SPEED_10;
10855                         vars->duplex = DUPLEX_FULL;
10856                 } else if (legacy_speed == (1<<8)) {
10857                         vars->line_speed = SPEED_10;
10858                         vars->duplex = DUPLEX_HALF;
10859                 } else /* Should not happen */
10860                         vars->line_speed = 0;
10861
10862                 DP(NETIF_MSG_LINK,
10863                    "Link is up in %dMbps, is_duplex_full= %d\n",
10864                    vars->line_speed,
10865                    (vars->duplex == DUPLEX_FULL));
10866
10867                 /* Check legacy speed AN resolution */
10868                 bnx2x_cl22_read(bp, phy,
10869                                 0x01,
10870                                 &val);
10871                 if (val & (1<<5))
10872                         vars->link_status |=
10873                                 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10874                 bnx2x_cl22_read(bp, phy,
10875                                 0x06,
10876                                 &val);
10877                 if ((val & (1<<0)) == 0)
10878                         vars->link_status |=
10879                                 LINK_STATUS_PARALLEL_DETECTION_USED;
10880
10881                 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
10882                            vars->line_speed);
10883
10884                 /* Report whether EEE is resolved. */
10885                 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &val);
10886                 if (val == MDIO_REG_GPHY_ID_54618SE) {
10887                         if (vars->link_status &
10888                             LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
10889                                 val = 0;
10890                         else {
10891                                 bnx2x_cl22_write(bp, phy,
10892                                         MDIO_REG_GPHY_CL45_ADDR_REG,
10893                                         MDIO_AN_DEVAD);
10894                                 bnx2x_cl22_write(bp, phy,
10895                                         MDIO_REG_GPHY_CL45_DATA_REG,
10896                                         MDIO_REG_GPHY_EEE_RESOLVED);
10897                                 bnx2x_cl22_write(bp, phy,
10898                                         MDIO_REG_GPHY_CL45_ADDR_REG,
10899                                         (0x1 << 14) | MDIO_AN_DEVAD);
10900                                 bnx2x_cl22_read(bp, phy,
10901                                         MDIO_REG_GPHY_CL45_DATA_REG,
10902                                         &val);
10903                         }
10904                         DP(NETIF_MSG_LINK, "EEE resolution: 0x%x\n", val);
10905                 }
10906
10907                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10908
10909                 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
10910                         /* Report LP advertised speeds */
10911                         bnx2x_cl22_read(bp, phy, 0x5, &val);
10912
10913                         if (val & (1<<5))
10914                                 vars->link_status |=
10915                                   LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10916                         if (val & (1<<6))
10917                                 vars->link_status |=
10918                                   LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10919                         if (val & (1<<7))
10920                                 vars->link_status |=
10921                                   LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10922                         if (val & (1<<8))
10923                                 vars->link_status |=
10924                                   LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10925                         if (val & (1<<9))
10926                                 vars->link_status |=
10927                                   LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10928
10929                         bnx2x_cl22_read(bp, phy, 0xa, &val);
10930                         if (val & (1<<10))
10931                                 vars->link_status |=
10932                                   LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10933                         if (val & (1<<11))
10934                                 vars->link_status |=
10935                                   LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10936                 }
10937         }
10938         return link_up;
10939 }
10940
10941 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
10942                                           struct link_params *params)
10943 {
10944         struct bnx2x *bp = params->bp;
10945         u16 val;
10946         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10947
10948         DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
10949
10950         /* Enable master/slave manual mmode and set to master */
10951         /* mii write 9 [bits set 11 12] */
10952         bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
10953
10954         /* forced 1G and disable autoneg */
10955         /* set val [mii read 0] */
10956         /* set val [expr $val & [bits clear 6 12 13]] */
10957         /* set val [expr $val | [bits set 6 8]] */
10958         /* mii write 0 $val */
10959         bnx2x_cl22_read(bp, phy, 0x00, &val);
10960         val &= ~((1<<6) | (1<<12) | (1<<13));
10961         val |= (1<<6) | (1<<8);
10962         bnx2x_cl22_write(bp, phy, 0x00, val);
10963
10964         /* Set external loopback and Tx using 6dB coding */
10965         /* mii write 0x18 7 */
10966         /* set val [mii read 0x18] */
10967         /* mii write 0x18 [expr $val | [bits set 10 15]] */
10968         bnx2x_cl22_write(bp, phy, 0x18, 7);
10969         bnx2x_cl22_read(bp, phy, 0x18, &val);
10970         bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
10971
10972         /* This register opens the gate for the UMAC despite its name */
10973         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
10974
10975         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10976          * length used by the MAC receive logic to check frames.
10977          */
10978         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
10979 }
10980
10981 /******************************************************************/
10982 /*                      SFX7101 PHY SECTION                       */
10983 /******************************************************************/
10984 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
10985                                        struct link_params *params)
10986 {
10987         struct bnx2x *bp = params->bp;
10988         /* SFX7101_XGXS_TEST1 */
10989         bnx2x_cl45_write(bp, phy,
10990                          MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
10991 }
10992
10993 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
10994                                   struct link_params *params,
10995                                   struct link_vars *vars)
10996 {
10997         u16 fw_ver1, fw_ver2, val;
10998         struct bnx2x *bp = params->bp;
10999         DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
11000
11001         /* Restore normal power mode*/
11002         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11003                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
11004         /* HW reset */
11005         bnx2x_ext_phy_hw_reset(bp, params->port);
11006         bnx2x_wait_reset_complete(bp, phy, params);
11007
11008         bnx2x_cl45_write(bp, phy,
11009                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
11010         DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
11011         bnx2x_cl45_write(bp, phy,
11012                          MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
11013
11014         bnx2x_ext_phy_set_pause(params, phy, vars);
11015         /* Restart autoneg */
11016         bnx2x_cl45_read(bp, phy,
11017                         MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
11018         val |= 0x200;
11019         bnx2x_cl45_write(bp, phy,
11020                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
11021
11022         /* Save spirom version */
11023         bnx2x_cl45_read(bp, phy,
11024                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
11025
11026         bnx2x_cl45_read(bp, phy,
11027                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
11028         bnx2x_save_spirom_version(bp, params->port,
11029                                   (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
11030         return 0;
11031 }
11032
11033 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
11034                                  struct link_params *params,
11035                                  struct link_vars *vars)
11036 {
11037         struct bnx2x *bp = params->bp;
11038         u8 link_up;
11039         u16 val1, val2;
11040         bnx2x_cl45_read(bp, phy,
11041                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
11042         bnx2x_cl45_read(bp, phy,
11043                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
11044         DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
11045                    val2, val1);
11046         bnx2x_cl45_read(bp, phy,
11047                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
11048         bnx2x_cl45_read(bp, phy,
11049                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
11050         DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
11051                    val2, val1);
11052         link_up = ((val1 & 4) == 4);
11053         /* if link is up print the AN outcome of the SFX7101 PHY */
11054         if (link_up) {
11055                 bnx2x_cl45_read(bp, phy,
11056                                 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
11057                                 &val2);
11058                 vars->line_speed = SPEED_10000;
11059                 vars->duplex = DUPLEX_FULL;
11060                 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
11061                            val2, (val2 & (1<<14)));
11062                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
11063                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11064
11065                 /* read LP advertised speeds */
11066                 if (val2 & (1<<11))
11067                         vars->link_status |=
11068                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
11069         }
11070         return link_up;
11071 }
11072
11073 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
11074 {
11075         if (*len < 5)
11076                 return -EINVAL;
11077         str[0] = (spirom_ver & 0xFF);
11078         str[1] = (spirom_ver & 0xFF00) >> 8;
11079         str[2] = (spirom_ver & 0xFF0000) >> 16;
11080         str[3] = (spirom_ver & 0xFF000000) >> 24;
11081         str[4] = '\0';
11082         *len -= 5;
11083         return 0;
11084 }
11085
11086 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
11087 {
11088         u16 val, cnt;
11089
11090         bnx2x_cl45_read(bp, phy,
11091                         MDIO_PMA_DEVAD,
11092                         MDIO_PMA_REG_7101_RESET, &val);
11093
11094         for (cnt = 0; cnt < 10; cnt++) {
11095                 msleep(50);
11096                 /* Writes a self-clearing reset */
11097                 bnx2x_cl45_write(bp, phy,
11098                                  MDIO_PMA_DEVAD,
11099                                  MDIO_PMA_REG_7101_RESET,
11100                                  (val | (1<<15)));
11101                 /* Wait for clear */
11102                 bnx2x_cl45_read(bp, phy,
11103                                 MDIO_PMA_DEVAD,
11104                                 MDIO_PMA_REG_7101_RESET, &val);
11105
11106                 if ((val & (1<<15)) == 0)
11107                         break;
11108         }
11109 }
11110
11111 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
11112                                 struct link_params *params) {
11113         /* Low power mode is controlled by GPIO 2 */
11114         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
11115                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11116         /* The PHY reset is controlled by GPIO 1 */
11117         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
11118                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11119 }
11120
11121 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
11122                                     struct link_params *params, u8 mode)
11123 {
11124         u16 val = 0;
11125         struct bnx2x *bp = params->bp;
11126         switch (mode) {
11127         case LED_MODE_FRONT_PANEL_OFF:
11128         case LED_MODE_OFF:
11129                 val = 2;
11130                 break;
11131         case LED_MODE_ON:
11132                 val = 1;
11133                 break;
11134         case LED_MODE_OPER:
11135                 val = 0;
11136                 break;
11137         }
11138         bnx2x_cl45_write(bp, phy,
11139                          MDIO_PMA_DEVAD,
11140                          MDIO_PMA_REG_7107_LINK_LED_CNTL,
11141                          val);
11142 }
11143
11144 /******************************************************************/
11145 /*                      STATIC PHY DECLARATION                    */
11146 /******************************************************************/
11147
11148 static struct bnx2x_phy phy_null = {
11149         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
11150         .addr           = 0,
11151         .def_md_devad   = 0,
11152         .flags          = FLAGS_INIT_XGXS_FIRST,
11153         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11154         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11155         .mdio_ctrl      = 0,
11156         .supported      = 0,
11157         .media_type     = ETH_PHY_NOT_PRESENT,
11158         .ver_addr       = 0,
11159         .req_flow_ctrl  = 0,
11160         .req_line_speed = 0,
11161         .speed_cap_mask = 0,
11162         .req_duplex     = 0,
11163         .rsrv           = 0,
11164         .config_init    = (config_init_t)NULL,
11165         .read_status    = (read_status_t)NULL,
11166         .link_reset     = (link_reset_t)NULL,
11167         .config_loopback = (config_loopback_t)NULL,
11168         .format_fw_ver  = (format_fw_ver_t)NULL,
11169         .hw_reset       = (hw_reset_t)NULL,
11170         .set_link_led   = (set_link_led_t)NULL,
11171         .phy_specific_func = (phy_specific_func_t)NULL
11172 };
11173
11174 static struct bnx2x_phy phy_serdes = {
11175         .type           = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
11176         .addr           = 0xff,
11177         .def_md_devad   = 0,
11178         .flags          = 0,
11179         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11180         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11181         .mdio_ctrl      = 0,
11182         .supported      = (SUPPORTED_10baseT_Half |
11183                            SUPPORTED_10baseT_Full |
11184                            SUPPORTED_100baseT_Half |
11185                            SUPPORTED_100baseT_Full |
11186                            SUPPORTED_1000baseT_Full |
11187                            SUPPORTED_2500baseX_Full |
11188                            SUPPORTED_TP |
11189                            SUPPORTED_Autoneg |
11190                            SUPPORTED_Pause |
11191                            SUPPORTED_Asym_Pause),
11192         .media_type     = ETH_PHY_BASE_T,
11193         .ver_addr       = 0,
11194         .req_flow_ctrl  = 0,
11195         .req_line_speed = 0,
11196         .speed_cap_mask = 0,
11197         .req_duplex     = 0,
11198         .rsrv           = 0,
11199         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
11200         .read_status    = (read_status_t)bnx2x_link_settings_status,
11201         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
11202         .config_loopback = (config_loopback_t)NULL,
11203         .format_fw_ver  = (format_fw_ver_t)NULL,
11204         .hw_reset       = (hw_reset_t)NULL,
11205         .set_link_led   = (set_link_led_t)NULL,
11206         .phy_specific_func = (phy_specific_func_t)NULL
11207 };
11208
11209 static struct bnx2x_phy phy_xgxs = {
11210         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11211         .addr           = 0xff,
11212         .def_md_devad   = 0,
11213         .flags          = 0,
11214         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11215         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11216         .mdio_ctrl      = 0,
11217         .supported      = (SUPPORTED_10baseT_Half |
11218                            SUPPORTED_10baseT_Full |
11219                            SUPPORTED_100baseT_Half |
11220                            SUPPORTED_100baseT_Full |
11221                            SUPPORTED_1000baseT_Full |
11222                            SUPPORTED_2500baseX_Full |
11223                            SUPPORTED_10000baseT_Full |
11224                            SUPPORTED_FIBRE |
11225                            SUPPORTED_Autoneg |
11226                            SUPPORTED_Pause |
11227                            SUPPORTED_Asym_Pause),
11228         .media_type     = ETH_PHY_CX4,
11229         .ver_addr       = 0,
11230         .req_flow_ctrl  = 0,
11231         .req_line_speed = 0,
11232         .speed_cap_mask = 0,
11233         .req_duplex     = 0,
11234         .rsrv           = 0,
11235         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
11236         .read_status    = (read_status_t)bnx2x_link_settings_status,
11237         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
11238         .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
11239         .format_fw_ver  = (format_fw_ver_t)NULL,
11240         .hw_reset       = (hw_reset_t)NULL,
11241         .set_link_led   = (set_link_led_t)NULL,
11242         .phy_specific_func = (phy_specific_func_t)NULL
11243 };
11244 static struct bnx2x_phy phy_warpcore = {
11245         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11246         .addr           = 0xff,
11247         .def_md_devad   = 0,
11248         .flags          = (FLAGS_HW_LOCK_REQUIRED |
11249                            FLAGS_TX_ERROR_CHECK),
11250         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11251         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11252         .mdio_ctrl      = 0,
11253         .supported      = (SUPPORTED_10baseT_Half |
11254                            SUPPORTED_10baseT_Full |
11255                            SUPPORTED_100baseT_Half |
11256                            SUPPORTED_100baseT_Full |
11257                            SUPPORTED_1000baseT_Full |
11258                            SUPPORTED_10000baseT_Full |
11259                            SUPPORTED_20000baseKR2_Full |
11260                            SUPPORTED_20000baseMLD2_Full |
11261                            SUPPORTED_FIBRE |
11262                            SUPPORTED_Autoneg |
11263                            SUPPORTED_Pause |
11264                            SUPPORTED_Asym_Pause),
11265         .media_type     = ETH_PHY_UNSPECIFIED,
11266         .ver_addr       = 0,
11267         .req_flow_ctrl  = 0,
11268         .req_line_speed = 0,
11269         .speed_cap_mask = 0,
11270         /* req_duplex = */0,
11271         /* rsrv = */0,
11272         .config_init    = (config_init_t)bnx2x_warpcore_config_init,
11273         .read_status    = (read_status_t)bnx2x_warpcore_read_status,
11274         .link_reset     = (link_reset_t)bnx2x_warpcore_link_reset,
11275         .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
11276         .format_fw_ver  = (format_fw_ver_t)NULL,
11277         .hw_reset       = (hw_reset_t)bnx2x_warpcore_hw_reset,
11278         .set_link_led   = (set_link_led_t)NULL,
11279         .phy_specific_func = (phy_specific_func_t)NULL
11280 };
11281
11282
11283 static struct bnx2x_phy phy_7101 = {
11284         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
11285         .addr           = 0xff,
11286         .def_md_devad   = 0,
11287         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
11288         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11289         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11290         .mdio_ctrl      = 0,
11291         .supported      = (SUPPORTED_10000baseT_Full |
11292                            SUPPORTED_TP |
11293                            SUPPORTED_Autoneg |
11294                            SUPPORTED_Pause |
11295                            SUPPORTED_Asym_Pause),
11296         .media_type     = ETH_PHY_BASE_T,
11297         .ver_addr       = 0,
11298         .req_flow_ctrl  = 0,
11299         .req_line_speed = 0,
11300         .speed_cap_mask = 0,
11301         .req_duplex     = 0,
11302         .rsrv           = 0,
11303         .config_init    = (config_init_t)bnx2x_7101_config_init,
11304         .read_status    = (read_status_t)bnx2x_7101_read_status,
11305         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11306         .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
11307         .format_fw_ver  = (format_fw_ver_t)bnx2x_7101_format_ver,
11308         .hw_reset       = (hw_reset_t)bnx2x_7101_hw_reset,
11309         .set_link_led   = (set_link_led_t)bnx2x_7101_set_link_led,
11310         .phy_specific_func = (phy_specific_func_t)NULL
11311 };
11312 static struct bnx2x_phy phy_8073 = {
11313         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
11314         .addr           = 0xff,
11315         .def_md_devad   = 0,
11316         .flags          = FLAGS_HW_LOCK_REQUIRED,
11317         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11318         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11319         .mdio_ctrl      = 0,
11320         .supported      = (SUPPORTED_10000baseT_Full |
11321                            SUPPORTED_2500baseX_Full |
11322                            SUPPORTED_1000baseT_Full |
11323                            SUPPORTED_FIBRE |
11324                            SUPPORTED_Autoneg |
11325                            SUPPORTED_Pause |
11326                            SUPPORTED_Asym_Pause),
11327         .media_type     = ETH_PHY_KR,
11328         .ver_addr       = 0,
11329         .req_flow_ctrl  = 0,
11330         .req_line_speed = 0,
11331         .speed_cap_mask = 0,
11332         .req_duplex     = 0,
11333         .rsrv           = 0,
11334         .config_init    = (config_init_t)bnx2x_8073_config_init,
11335         .read_status    = (read_status_t)bnx2x_8073_read_status,
11336         .link_reset     = (link_reset_t)bnx2x_8073_link_reset,
11337         .config_loopback = (config_loopback_t)NULL,
11338         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11339         .hw_reset       = (hw_reset_t)NULL,
11340         .set_link_led   = (set_link_led_t)NULL,
11341         .phy_specific_func = (phy_specific_func_t)NULL
11342 };
11343 static struct bnx2x_phy phy_8705 = {
11344         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
11345         .addr           = 0xff,
11346         .def_md_devad   = 0,
11347         .flags          = FLAGS_INIT_XGXS_FIRST,
11348         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11349         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11350         .mdio_ctrl      = 0,
11351         .supported      = (SUPPORTED_10000baseT_Full |
11352                            SUPPORTED_FIBRE |
11353                            SUPPORTED_Pause |
11354                            SUPPORTED_Asym_Pause),
11355         .media_type     = ETH_PHY_XFP_FIBER,
11356         .ver_addr       = 0,
11357         .req_flow_ctrl  = 0,
11358         .req_line_speed = 0,
11359         .speed_cap_mask = 0,
11360         .req_duplex     = 0,
11361         .rsrv           = 0,
11362         .config_init    = (config_init_t)bnx2x_8705_config_init,
11363         .read_status    = (read_status_t)bnx2x_8705_read_status,
11364         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11365         .config_loopback = (config_loopback_t)NULL,
11366         .format_fw_ver  = (format_fw_ver_t)bnx2x_null_format_ver,
11367         .hw_reset       = (hw_reset_t)NULL,
11368         .set_link_led   = (set_link_led_t)NULL,
11369         .phy_specific_func = (phy_specific_func_t)NULL
11370 };
11371 static struct bnx2x_phy phy_8706 = {
11372         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
11373         .addr           = 0xff,
11374         .def_md_devad   = 0,
11375         .flags          = FLAGS_INIT_XGXS_FIRST,
11376         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11377         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11378         .mdio_ctrl      = 0,
11379         .supported      = (SUPPORTED_10000baseT_Full |
11380                            SUPPORTED_1000baseT_Full |
11381                            SUPPORTED_FIBRE |
11382                            SUPPORTED_Pause |
11383                            SUPPORTED_Asym_Pause),
11384         .media_type     = ETH_PHY_SFP_FIBER,
11385         .ver_addr       = 0,
11386         .req_flow_ctrl  = 0,
11387         .req_line_speed = 0,
11388         .speed_cap_mask = 0,
11389         .req_duplex     = 0,
11390         .rsrv           = 0,
11391         .config_init    = (config_init_t)bnx2x_8706_config_init,
11392         .read_status    = (read_status_t)bnx2x_8706_read_status,
11393         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11394         .config_loopback = (config_loopback_t)NULL,
11395         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11396         .hw_reset       = (hw_reset_t)NULL,
11397         .set_link_led   = (set_link_led_t)NULL,
11398         .phy_specific_func = (phy_specific_func_t)NULL
11399 };
11400
11401 static struct bnx2x_phy phy_8726 = {
11402         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
11403         .addr           = 0xff,
11404         .def_md_devad   = 0,
11405         .flags          = (FLAGS_HW_LOCK_REQUIRED |
11406                            FLAGS_INIT_XGXS_FIRST |
11407                            FLAGS_TX_ERROR_CHECK),
11408         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11409         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11410         .mdio_ctrl      = 0,
11411         .supported      = (SUPPORTED_10000baseT_Full |
11412                            SUPPORTED_1000baseT_Full |
11413                            SUPPORTED_Autoneg |
11414                            SUPPORTED_FIBRE |
11415                            SUPPORTED_Pause |
11416                            SUPPORTED_Asym_Pause),
11417         .media_type     = ETH_PHY_NOT_PRESENT,
11418         .ver_addr       = 0,
11419         .req_flow_ctrl  = 0,
11420         .req_line_speed = 0,
11421         .speed_cap_mask = 0,
11422         .req_duplex     = 0,
11423         .rsrv           = 0,
11424         .config_init    = (config_init_t)bnx2x_8726_config_init,
11425         .read_status    = (read_status_t)bnx2x_8726_read_status,
11426         .link_reset     = (link_reset_t)bnx2x_8726_link_reset,
11427         .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
11428         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11429         .hw_reset       = (hw_reset_t)NULL,
11430         .set_link_led   = (set_link_led_t)NULL,
11431         .phy_specific_func = (phy_specific_func_t)NULL
11432 };
11433
11434 static struct bnx2x_phy phy_8727 = {
11435         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
11436         .addr           = 0xff,
11437         .def_md_devad   = 0,
11438         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11439                            FLAGS_TX_ERROR_CHECK),
11440         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11441         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11442         .mdio_ctrl      = 0,
11443         .supported      = (SUPPORTED_10000baseT_Full |
11444                            SUPPORTED_1000baseT_Full |
11445                            SUPPORTED_FIBRE |
11446                            SUPPORTED_Pause |
11447                            SUPPORTED_Asym_Pause),
11448         .media_type     = ETH_PHY_NOT_PRESENT,
11449         .ver_addr       = 0,
11450         .req_flow_ctrl  = 0,
11451         .req_line_speed = 0,
11452         .speed_cap_mask = 0,
11453         .req_duplex     = 0,
11454         .rsrv           = 0,
11455         .config_init    = (config_init_t)bnx2x_8727_config_init,
11456         .read_status    = (read_status_t)bnx2x_8727_read_status,
11457         .link_reset     = (link_reset_t)bnx2x_8727_link_reset,
11458         .config_loopback = (config_loopback_t)NULL,
11459         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11460         .hw_reset       = (hw_reset_t)bnx2x_8727_hw_reset,
11461         .set_link_led   = (set_link_led_t)bnx2x_8727_set_link_led,
11462         .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
11463 };
11464 static struct bnx2x_phy phy_8481 = {
11465         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
11466         .addr           = 0xff,
11467         .def_md_devad   = 0,
11468         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
11469                           FLAGS_REARM_LATCH_SIGNAL,
11470         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11471         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11472         .mdio_ctrl      = 0,
11473         .supported      = (SUPPORTED_10baseT_Half |
11474                            SUPPORTED_10baseT_Full |
11475                            SUPPORTED_100baseT_Half |
11476                            SUPPORTED_100baseT_Full |
11477                            SUPPORTED_1000baseT_Full |
11478                            SUPPORTED_10000baseT_Full |
11479                            SUPPORTED_TP |
11480                            SUPPORTED_Autoneg |
11481                            SUPPORTED_Pause |
11482                            SUPPORTED_Asym_Pause),
11483         .media_type     = ETH_PHY_BASE_T,
11484         .ver_addr       = 0,
11485         .req_flow_ctrl  = 0,
11486         .req_line_speed = 0,
11487         .speed_cap_mask = 0,
11488         .req_duplex     = 0,
11489         .rsrv           = 0,
11490         .config_init    = (config_init_t)bnx2x_8481_config_init,
11491         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11492         .link_reset     = (link_reset_t)bnx2x_8481_link_reset,
11493         .config_loopback = (config_loopback_t)NULL,
11494         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11495         .hw_reset       = (hw_reset_t)bnx2x_8481_hw_reset,
11496         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11497         .phy_specific_func = (phy_specific_func_t)NULL
11498 };
11499
11500 static struct bnx2x_phy phy_84823 = {
11501         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
11502         .addr           = 0xff,
11503         .def_md_devad   = 0,
11504         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11505                            FLAGS_REARM_LATCH_SIGNAL |
11506                            FLAGS_TX_ERROR_CHECK),
11507         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11508         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11509         .mdio_ctrl      = 0,
11510         .supported      = (SUPPORTED_10baseT_Half |
11511                            SUPPORTED_10baseT_Full |
11512                            SUPPORTED_100baseT_Half |
11513                            SUPPORTED_100baseT_Full |
11514                            SUPPORTED_1000baseT_Full |
11515                            SUPPORTED_10000baseT_Full |
11516                            SUPPORTED_TP |
11517                            SUPPORTED_Autoneg |
11518                            SUPPORTED_Pause |
11519                            SUPPORTED_Asym_Pause),
11520         .media_type     = ETH_PHY_BASE_T,
11521         .ver_addr       = 0,
11522         .req_flow_ctrl  = 0,
11523         .req_line_speed = 0,
11524         .speed_cap_mask = 0,
11525         .req_duplex     = 0,
11526         .rsrv           = 0,
11527         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11528         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11529         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11530         .config_loopback = (config_loopback_t)NULL,
11531         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11532         .hw_reset       = (hw_reset_t)NULL,
11533         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11534         .phy_specific_func = (phy_specific_func_t)NULL
11535 };
11536
11537 static struct bnx2x_phy phy_84833 = {
11538         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
11539         .addr           = 0xff,
11540         .def_md_devad   = 0,
11541         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11542                            FLAGS_REARM_LATCH_SIGNAL |
11543                            FLAGS_TX_ERROR_CHECK |
11544                            FLAGS_EEE_10GBT),
11545         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11546         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11547         .mdio_ctrl      = 0,
11548         .supported      = (SUPPORTED_100baseT_Half |
11549                            SUPPORTED_100baseT_Full |
11550                            SUPPORTED_1000baseT_Full |
11551                            SUPPORTED_10000baseT_Full |
11552                            SUPPORTED_TP |
11553                            SUPPORTED_Autoneg |
11554                            SUPPORTED_Pause |
11555                            SUPPORTED_Asym_Pause),
11556         .media_type     = ETH_PHY_BASE_T,
11557         .ver_addr       = 0,
11558         .req_flow_ctrl  = 0,
11559         .req_line_speed = 0,
11560         .speed_cap_mask = 0,
11561         .req_duplex     = 0,
11562         .rsrv           = 0,
11563         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11564         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11565         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11566         .config_loopback = (config_loopback_t)NULL,
11567         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11568         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11569         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11570         .phy_specific_func = (phy_specific_func_t)NULL
11571 };
11572
11573 static struct bnx2x_phy phy_54618se = {
11574         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
11575         .addr           = 0xff,
11576         .def_md_devad   = 0,
11577         .flags          = FLAGS_INIT_XGXS_FIRST,
11578         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11579         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11580         .mdio_ctrl      = 0,
11581         .supported      = (SUPPORTED_10baseT_Half |
11582                            SUPPORTED_10baseT_Full |
11583                            SUPPORTED_100baseT_Half |
11584                            SUPPORTED_100baseT_Full |
11585                            SUPPORTED_1000baseT_Full |
11586                            SUPPORTED_TP |
11587                            SUPPORTED_Autoneg |
11588                            SUPPORTED_Pause |
11589                            SUPPORTED_Asym_Pause),
11590         .media_type     = ETH_PHY_BASE_T,
11591         .ver_addr       = 0,
11592         .req_flow_ctrl  = 0,
11593         .req_line_speed = 0,
11594         .speed_cap_mask = 0,
11595         /* req_duplex = */0,
11596         /* rsrv = */0,
11597         .config_init    = (config_init_t)bnx2x_54618se_config_init,
11598         .read_status    = (read_status_t)bnx2x_54618se_read_status,
11599         .link_reset     = (link_reset_t)bnx2x_54618se_link_reset,
11600         .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
11601         .format_fw_ver  = (format_fw_ver_t)NULL,
11602         .hw_reset       = (hw_reset_t)NULL,
11603         .set_link_led   = (set_link_led_t)bnx2x_5461x_set_link_led,
11604         .phy_specific_func = (phy_specific_func_t)NULL
11605 };
11606 /*****************************************************************/
11607 /*                                                               */
11608 /* Populate the phy according. Main function: bnx2x_populate_phy   */
11609 /*                                                               */
11610 /*****************************************************************/
11611
11612 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
11613                                      struct bnx2x_phy *phy, u8 port,
11614                                      u8 phy_index)
11615 {
11616         /* Get the 4 lanes xgxs config rx and tx */
11617         u32 rx = 0, tx = 0, i;
11618         for (i = 0; i < 2; i++) {
11619                 /* INT_PHY and EXT_PHY1 share the same value location in
11620                  * the shmem. When num_phys is greater than 1, than this value
11621                  * applies only to EXT_PHY1
11622                  */
11623                 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
11624                         rx = REG_RD(bp, shmem_base +
11625                                     offsetof(struct shmem_region,
11626                           dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
11627
11628                         tx = REG_RD(bp, shmem_base +
11629                                     offsetof(struct shmem_region,
11630                           dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
11631                 } else {
11632                         rx = REG_RD(bp, shmem_base +
11633                                     offsetof(struct shmem_region,
11634                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11635
11636                         tx = REG_RD(bp, shmem_base +
11637                                     offsetof(struct shmem_region,
11638                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11639                 }
11640
11641                 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
11642                 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11643
11644                 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
11645                 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11646         }
11647 }
11648
11649 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11650                                     u8 phy_index, u8 port)
11651 {
11652         u32 ext_phy_config = 0;
11653         switch (phy_index) {
11654         case EXT_PHY1:
11655                 ext_phy_config = REG_RD(bp, shmem_base +
11656                                               offsetof(struct shmem_region,
11657                         dev_info.port_hw_config[port].external_phy_config));
11658                 break;
11659         case EXT_PHY2:
11660                 ext_phy_config = REG_RD(bp, shmem_base +
11661                                               offsetof(struct shmem_region,
11662                         dev_info.port_hw_config[port].external_phy_config2));
11663                 break;
11664         default:
11665                 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11666                 return -EINVAL;
11667         }
11668
11669         return ext_phy_config;
11670 }
11671 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11672                                   struct bnx2x_phy *phy)
11673 {
11674         u32 phy_addr;
11675         u32 chip_id;
11676         u32 switch_cfg = (REG_RD(bp, shmem_base +
11677                                        offsetof(struct shmem_region,
11678                         dev_info.port_feature_config[port].link_config)) &
11679                           PORT_FEATURE_CONNECTED_SWITCH_MASK);
11680         chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
11681                 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
11682
11683         DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11684         if (USES_WARPCORE(bp)) {
11685                 u32 serdes_net_if;
11686                 phy_addr = REG_RD(bp,
11687                                   MISC_REG_WC0_CTRL_PHY_ADDR);
11688                 *phy = phy_warpcore;
11689                 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11690                         phy->flags |= FLAGS_4_PORT_MODE;
11691                 else
11692                         phy->flags &= ~FLAGS_4_PORT_MODE;
11693                         /* Check Dual mode */
11694                 serdes_net_if = (REG_RD(bp, shmem_base +
11695                                         offsetof(struct shmem_region, dev_info.
11696                                         port_hw_config[port].default_cfg)) &
11697                                  PORT_HW_CFG_NET_SERDES_IF_MASK);
11698                 /* Set the appropriate supported and flags indications per
11699                  * interface type of the chip
11700                  */
11701                 switch (serdes_net_if) {
11702                 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11703                         phy->supported &= (SUPPORTED_10baseT_Half |
11704                                            SUPPORTED_10baseT_Full |
11705                                            SUPPORTED_100baseT_Half |
11706                                            SUPPORTED_100baseT_Full |
11707                                            SUPPORTED_1000baseT_Full |
11708                                            SUPPORTED_FIBRE |
11709                                            SUPPORTED_Autoneg |
11710                                            SUPPORTED_Pause |
11711                                            SUPPORTED_Asym_Pause);
11712                         phy->media_type = ETH_PHY_BASE_T;
11713                         break;
11714                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11715                         phy->media_type = ETH_PHY_XFP_FIBER;
11716                         break;
11717                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11718                         phy->supported &= (SUPPORTED_1000baseT_Full |
11719                                            SUPPORTED_10000baseT_Full |
11720                                            SUPPORTED_FIBRE |
11721                                            SUPPORTED_Pause |
11722                                            SUPPORTED_Asym_Pause);
11723                         phy->media_type = ETH_PHY_SFP_FIBER;
11724                         break;
11725                 case PORT_HW_CFG_NET_SERDES_IF_KR:
11726                         phy->media_type = ETH_PHY_KR;
11727                         phy->supported &= (SUPPORTED_1000baseT_Full |
11728                                            SUPPORTED_10000baseT_Full |
11729                                            SUPPORTED_FIBRE |
11730                                            SUPPORTED_Autoneg |
11731                                            SUPPORTED_Pause |
11732                                            SUPPORTED_Asym_Pause);
11733                         break;
11734                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11735                         phy->media_type = ETH_PHY_KR;
11736                         phy->flags |= FLAGS_WC_DUAL_MODE;
11737                         phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11738                                            SUPPORTED_FIBRE |
11739                                            SUPPORTED_Pause |
11740                                            SUPPORTED_Asym_Pause);
11741                         break;
11742                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11743                         phy->media_type = ETH_PHY_KR;
11744                         phy->flags |= FLAGS_WC_DUAL_MODE;
11745                         phy->supported &= (SUPPORTED_20000baseKR2_Full |
11746                                            SUPPORTED_FIBRE |
11747                                            SUPPORTED_Pause |
11748                                            SUPPORTED_Asym_Pause);
11749                         break;
11750                 default:
11751                         DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
11752                                        serdes_net_if);
11753                         break;
11754                 }
11755
11756                 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
11757                  * was not set as expected. For B0, ECO will be enabled so there
11758                  * won't be an issue there
11759                  */
11760                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11761                         phy->flags |= FLAGS_MDC_MDIO_WA;
11762                 else
11763                         phy->flags |= FLAGS_MDC_MDIO_WA_B0;
11764         } else {
11765                 switch (switch_cfg) {
11766                 case SWITCH_CFG_1G:
11767                         phy_addr = REG_RD(bp,
11768                                           NIG_REG_SERDES0_CTRL_PHY_ADDR +
11769                                           port * 0x10);
11770                         *phy = phy_serdes;
11771                         break;
11772                 case SWITCH_CFG_10G:
11773                         phy_addr = REG_RD(bp,
11774                                           NIG_REG_XGXS0_CTRL_PHY_ADDR +
11775                                           port * 0x18);
11776                         *phy = phy_xgxs;
11777                         break;
11778                 default:
11779                         DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
11780                         return -EINVAL;
11781                 }
11782         }
11783         phy->addr = (u8)phy_addr;
11784         phy->mdio_ctrl = bnx2x_get_emac_base(bp,
11785                                             SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11786                                             port);
11787         if (CHIP_IS_E2(bp))
11788                 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
11789         else
11790                 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
11791
11792         DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
11793                    port, phy->addr, phy->mdio_ctrl);
11794
11795         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
11796         return 0;
11797 }
11798
11799 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
11800                                   u8 phy_index,
11801                                   u32 shmem_base,
11802                                   u32 shmem2_base,
11803                                   u8 port,
11804                                   struct bnx2x_phy *phy)
11805 {
11806         u32 ext_phy_config, phy_type, config2;
11807         u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11808         ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
11809                                                   phy_index, port);
11810         phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11811         /* Select the phy type */
11812         switch (phy_type) {
11813         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
11814                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
11815                 *phy = phy_8073;
11816                 break;
11817         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
11818                 *phy = phy_8705;
11819                 break;
11820         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
11821                 *phy = phy_8706;
11822                 break;
11823         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
11824                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11825                 *phy = phy_8726;
11826                 break;
11827         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
11828                 /* BCM8727_NOC => BCM8727 no over current */
11829                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11830                 *phy = phy_8727;
11831                 phy->flags |= FLAGS_NOC;
11832                 break;
11833         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
11834         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
11835                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11836                 *phy = phy_8727;
11837                 break;
11838         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
11839                 *phy = phy_8481;
11840                 break;
11841         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
11842                 *phy = phy_84823;
11843                 break;
11844         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
11845                 *phy = phy_84833;
11846                 break;
11847         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
11848         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
11849                 *phy = phy_54618se;
11850                 break;
11851         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
11852                 *phy = phy_7101;
11853                 break;
11854         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
11855                 *phy = phy_null;
11856                 return -EINVAL;
11857         default:
11858                 *phy = phy_null;
11859                 /* In case external PHY wasn't found */
11860                 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
11861                     (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11862                         return -EINVAL;
11863                 return 0;
11864         }
11865
11866         phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
11867         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
11868
11869         /* The shmem address of the phy version is located on different
11870          * structures. In case this structure is too old, do not set
11871          * the address
11872          */
11873         config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
11874                                         dev_info.shared_hw_config.config2));
11875         if (phy_index == EXT_PHY1) {
11876                 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
11877                                 port_mb[port].ext_phy_fw_version);
11878
11879                 /* Check specific mdc mdio settings */
11880                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
11881                         mdc_mdio_access = config2 &
11882                         SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
11883         } else {
11884                 u32 size = REG_RD(bp, shmem2_base);
11885
11886                 if (size >
11887                     offsetof(struct shmem2_region, ext_phy_fw_version2)) {
11888                         phy->ver_addr = shmem2_base +
11889                             offsetof(struct shmem2_region,
11890                                      ext_phy_fw_version2[port]);
11891                 }
11892                 /* Check specific mdc mdio settings */
11893                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
11894                         mdc_mdio_access = (config2 &
11895                         SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
11896                         (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
11897                          SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
11898         }
11899         phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
11900
11901         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
11902             (phy->ver_addr)) {
11903                 /* Remove 100Mb link supported for BCM84833 when phy fw
11904                  * version lower than or equal to 1.39
11905                  */
11906                 u32 raw_ver = REG_RD(bp, phy->ver_addr);
11907                 if (((raw_ver & 0x7F) <= 39) &&
11908                     (((raw_ver & 0xF80) >> 7) <= 1))
11909                         phy->supported &= ~(SUPPORTED_100baseT_Half |
11910                                             SUPPORTED_100baseT_Full);
11911         }
11912
11913         /* In case mdc/mdio_access of the external phy is different than the
11914          * mdc/mdio access of the XGXS, a HW lock must be taken in each access
11915          * to prevent one port interfere with another port's CL45 operations.
11916          */
11917         if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
11918                 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
11919         DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
11920                    phy_type, port, phy_index);
11921         DP(NETIF_MSG_LINK, "             addr=0x%x, mdio_ctl=0x%x\n",
11922                    phy->addr, phy->mdio_ctrl);
11923         return 0;
11924 }
11925
11926 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
11927                               u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
11928 {
11929         int status = 0;
11930         phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
11931         if (phy_index == INT_PHY)
11932                 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
11933         status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
11934                                         port, phy);
11935         return status;
11936 }
11937
11938 static void bnx2x_phy_def_cfg(struct link_params *params,
11939                               struct bnx2x_phy *phy,
11940                               u8 phy_index)
11941 {
11942         struct bnx2x *bp = params->bp;
11943         u32 link_config;
11944         /* Populate the default phy configuration for MF mode */
11945         if (phy_index == EXT_PHY2) {
11946                 link_config = REG_RD(bp, params->shmem_base +
11947                                      offsetof(struct shmem_region, dev_info.
11948                         port_feature_config[params->port].link_config2));
11949                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11950                                              offsetof(struct shmem_region,
11951                                                       dev_info.
11952                         port_hw_config[params->port].speed_capability_mask2));
11953         } else {
11954                 link_config = REG_RD(bp, params->shmem_base +
11955                                      offsetof(struct shmem_region, dev_info.
11956                                 port_feature_config[params->port].link_config));
11957                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11958                                              offsetof(struct shmem_region,
11959                                                       dev_info.
11960                         port_hw_config[params->port].speed_capability_mask));
11961         }
11962         DP(NETIF_MSG_LINK,
11963            "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
11964            phy_index, link_config, phy->speed_cap_mask);
11965
11966         phy->req_duplex = DUPLEX_FULL;
11967         switch (link_config  & PORT_FEATURE_LINK_SPEED_MASK) {
11968         case PORT_FEATURE_LINK_SPEED_10M_HALF:
11969                 phy->req_duplex = DUPLEX_HALF;
11970         case PORT_FEATURE_LINK_SPEED_10M_FULL:
11971                 phy->req_line_speed = SPEED_10;
11972                 break;
11973         case PORT_FEATURE_LINK_SPEED_100M_HALF:
11974                 phy->req_duplex = DUPLEX_HALF;
11975         case PORT_FEATURE_LINK_SPEED_100M_FULL:
11976                 phy->req_line_speed = SPEED_100;
11977                 break;
11978         case PORT_FEATURE_LINK_SPEED_1G:
11979                 phy->req_line_speed = SPEED_1000;
11980                 break;
11981         case PORT_FEATURE_LINK_SPEED_2_5G:
11982                 phy->req_line_speed = SPEED_2500;
11983                 break;
11984         case PORT_FEATURE_LINK_SPEED_10G_CX4:
11985                 phy->req_line_speed = SPEED_10000;
11986                 break;
11987         default:
11988                 phy->req_line_speed = SPEED_AUTO_NEG;
11989                 break;
11990         }
11991
11992         switch (link_config  & PORT_FEATURE_FLOW_CONTROL_MASK) {
11993         case PORT_FEATURE_FLOW_CONTROL_AUTO:
11994                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
11995                 break;
11996         case PORT_FEATURE_FLOW_CONTROL_TX:
11997                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
11998                 break;
11999         case PORT_FEATURE_FLOW_CONTROL_RX:
12000                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
12001                 break;
12002         case PORT_FEATURE_FLOW_CONTROL_BOTH:
12003                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
12004                 break;
12005         default:
12006                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12007                 break;
12008         }
12009 }
12010
12011 u32 bnx2x_phy_selection(struct link_params *params)
12012 {
12013         u32 phy_config_swapped, prio_cfg;
12014         u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
12015
12016         phy_config_swapped = params->multi_phy_config &
12017                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12018
12019         prio_cfg = params->multi_phy_config &
12020                         PORT_HW_CFG_PHY_SELECTION_MASK;
12021
12022         if (phy_config_swapped) {
12023                 switch (prio_cfg) {
12024                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
12025                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
12026                      break;
12027                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
12028                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
12029                      break;
12030                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
12031                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
12032                      break;
12033                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
12034                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
12035                      break;
12036                 }
12037         } else
12038                 return_cfg = prio_cfg;
12039
12040         return return_cfg;
12041 }
12042
12043
12044 int bnx2x_phy_probe(struct link_params *params)
12045 {
12046         u8 phy_index, actual_phy_idx;
12047         u32 phy_config_swapped, sync_offset, media_types;
12048         struct bnx2x *bp = params->bp;
12049         struct bnx2x_phy *phy;
12050         params->num_phys = 0;
12051         DP(NETIF_MSG_LINK, "Begin phy probe\n");
12052         phy_config_swapped = params->multi_phy_config &
12053                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12054
12055         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12056               phy_index++) {
12057                 actual_phy_idx = phy_index;
12058                 if (phy_config_swapped) {
12059                         if (phy_index == EXT_PHY1)
12060                                 actual_phy_idx = EXT_PHY2;
12061                         else if (phy_index == EXT_PHY2)
12062                                 actual_phy_idx = EXT_PHY1;
12063                 }
12064                 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
12065                                " actual_phy_idx %x\n", phy_config_swapped,
12066                            phy_index, actual_phy_idx);
12067                 phy = &params->phy[actual_phy_idx];
12068                 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
12069                                        params->shmem2_base, params->port,
12070                                        phy) != 0) {
12071                         params->num_phys = 0;
12072                         DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
12073                                    phy_index);
12074                         for (phy_index = INT_PHY;
12075                               phy_index < MAX_PHYS;
12076                               phy_index++)
12077                                 *phy = phy_null;
12078                         return -EINVAL;
12079                 }
12080                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
12081                         break;
12082
12083                 if (params->feature_config_flags &
12084                     FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
12085                         phy->flags &= ~FLAGS_TX_ERROR_CHECK;
12086
12087                 sync_offset = params->shmem_base +
12088                         offsetof(struct shmem_region,
12089                         dev_info.port_hw_config[params->port].media_type);
12090                 media_types = REG_RD(bp, sync_offset);
12091
12092                 /* Update media type for non-PMF sync only for the first time
12093                  * In case the media type changes afterwards, it will be updated
12094                  * using the update_status function
12095                  */
12096                 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
12097                                     (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12098                                      actual_phy_idx))) == 0) {
12099                         media_types |= ((phy->media_type &
12100                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
12101                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12102                                  actual_phy_idx));
12103                 }
12104                 REG_WR(bp, sync_offset, media_types);
12105
12106                 bnx2x_phy_def_cfg(params, phy, phy_index);
12107                 params->num_phys++;
12108         }
12109
12110         DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
12111         return 0;
12112 }
12113
12114 void bnx2x_init_bmac_loopback(struct link_params *params,
12115                               struct link_vars *vars)
12116 {
12117         struct bnx2x *bp = params->bp;
12118                 vars->link_up = 1;
12119                 vars->line_speed = SPEED_10000;
12120                 vars->duplex = DUPLEX_FULL;
12121                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12122                 vars->mac_type = MAC_TYPE_BMAC;
12123
12124                 vars->phy_flags = PHY_XGXS_FLAG;
12125
12126                 bnx2x_xgxs_deassert(params);
12127
12128                 /* set bmac loopback */
12129                 bnx2x_bmac_enable(params, vars, 1);
12130
12131                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12132 }
12133
12134 void bnx2x_init_emac_loopback(struct link_params *params,
12135                               struct link_vars *vars)
12136 {
12137         struct bnx2x *bp = params->bp;
12138                 vars->link_up = 1;
12139                 vars->line_speed = SPEED_1000;
12140                 vars->duplex = DUPLEX_FULL;
12141                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12142                 vars->mac_type = MAC_TYPE_EMAC;
12143
12144                 vars->phy_flags = PHY_XGXS_FLAG;
12145
12146                 bnx2x_xgxs_deassert(params);
12147                 /* set bmac loopback */
12148                 bnx2x_emac_enable(params, vars, 1);
12149                 bnx2x_emac_program(params, vars);
12150                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12151 }
12152
12153 void bnx2x_init_xmac_loopback(struct link_params *params,
12154                               struct link_vars *vars)
12155 {
12156         struct bnx2x *bp = params->bp;
12157         vars->link_up = 1;
12158         if (!params->req_line_speed[0])
12159                 vars->line_speed = SPEED_10000;
12160         else
12161                 vars->line_speed = params->req_line_speed[0];
12162         vars->duplex = DUPLEX_FULL;
12163         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12164         vars->mac_type = MAC_TYPE_XMAC;
12165         vars->phy_flags = PHY_XGXS_FLAG;
12166         /* Set WC to loopback mode since link is required to provide clock
12167          * to the XMAC in 20G mode
12168          */
12169         bnx2x_set_aer_mmd(params, &params->phy[0]);
12170         bnx2x_warpcore_reset_lane(bp, &params->phy[0], 0);
12171         params->phy[INT_PHY].config_loopback(
12172                         &params->phy[INT_PHY],
12173                         params);
12174
12175         bnx2x_xmac_enable(params, vars, 1);
12176         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12177 }
12178
12179 void bnx2x_init_umac_loopback(struct link_params *params,
12180                               struct link_vars *vars)
12181 {
12182         struct bnx2x *bp = params->bp;
12183         vars->link_up = 1;
12184         vars->line_speed = SPEED_1000;
12185         vars->duplex = DUPLEX_FULL;
12186         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12187         vars->mac_type = MAC_TYPE_UMAC;
12188         vars->phy_flags = PHY_XGXS_FLAG;
12189         bnx2x_umac_enable(params, vars, 1);
12190
12191         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12192 }
12193
12194 void bnx2x_init_xgxs_loopback(struct link_params *params,
12195                               struct link_vars *vars)
12196 {
12197         struct bnx2x *bp = params->bp;
12198                 vars->link_up = 1;
12199                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12200                 vars->duplex = DUPLEX_FULL;
12201         if (params->req_line_speed[0] == SPEED_1000)
12202                         vars->line_speed = SPEED_1000;
12203         else
12204                         vars->line_speed = SPEED_10000;
12205
12206         if (!USES_WARPCORE(bp))
12207                 bnx2x_xgxs_deassert(params);
12208         bnx2x_link_initialize(params, vars);
12209
12210         if (params->req_line_speed[0] == SPEED_1000) {
12211                 if (USES_WARPCORE(bp))
12212                         bnx2x_umac_enable(params, vars, 0);
12213                 else {
12214                         bnx2x_emac_program(params, vars);
12215                         bnx2x_emac_enable(params, vars, 0);
12216                 }
12217         } else {
12218                 if (USES_WARPCORE(bp))
12219                         bnx2x_xmac_enable(params, vars, 0);
12220                 else
12221                         bnx2x_bmac_enable(params, vars, 0);
12222         }
12223
12224                 if (params->loopback_mode == LOOPBACK_XGXS) {
12225                         /* set 10G XGXS loopback */
12226                         params->phy[INT_PHY].config_loopback(
12227                                 &params->phy[INT_PHY],
12228                                 params);
12229
12230                 } else {
12231                         /* set external phy loopback */
12232                         u8 phy_index;
12233                         for (phy_index = EXT_PHY1;
12234                               phy_index < params->num_phys; phy_index++) {
12235                                 if (params->phy[phy_index].config_loopback)
12236                                         params->phy[phy_index].config_loopback(
12237                                                 &params->phy[phy_index],
12238                                                 params);
12239                         }
12240                 }
12241                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12242
12243         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
12244 }
12245
12246 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
12247 {
12248         struct bnx2x *bp = params->bp;
12249         DP(NETIF_MSG_LINK, "Phy Initialization started\n");
12250         DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
12251                    params->req_line_speed[0], params->req_flow_ctrl[0]);
12252         DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
12253                    params->req_line_speed[1], params->req_flow_ctrl[1]);
12254         vars->link_status = 0;
12255         vars->phy_link_up = 0;
12256         vars->link_up = 0;
12257         vars->line_speed = 0;
12258         vars->duplex = DUPLEX_FULL;
12259         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12260         vars->mac_type = MAC_TYPE_NONE;
12261         vars->phy_flags = 0;
12262
12263         /* disable attentions */
12264         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12265                        (NIG_MASK_XGXS0_LINK_STATUS |
12266                         NIG_MASK_XGXS0_LINK10G |
12267                         NIG_MASK_SERDES0_LINK_STATUS |
12268                         NIG_MASK_MI_INT));
12269
12270         bnx2x_emac_init(params, vars);
12271
12272         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
12273                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
12274
12275         if (params->num_phys == 0) {
12276                 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
12277                 return -EINVAL;
12278         }
12279         set_phy_vars(params, vars);
12280
12281         DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
12282         switch (params->loopback_mode) {
12283         case LOOPBACK_BMAC:
12284                 bnx2x_init_bmac_loopback(params, vars);
12285                 break;
12286         case LOOPBACK_EMAC:
12287                 bnx2x_init_emac_loopback(params, vars);
12288                 break;
12289         case LOOPBACK_XMAC:
12290                 bnx2x_init_xmac_loopback(params, vars);
12291                 break;
12292         case LOOPBACK_UMAC:
12293                 bnx2x_init_umac_loopback(params, vars);
12294                 break;
12295         case LOOPBACK_XGXS:
12296         case LOOPBACK_EXT_PHY:
12297                 bnx2x_init_xgxs_loopback(params, vars);
12298                 break;
12299         default:
12300                 if (!CHIP_IS_E3(bp)) {
12301                         if (params->switch_cfg == SWITCH_CFG_10G)
12302                                 bnx2x_xgxs_deassert(params);
12303                         else
12304                                 bnx2x_serdes_deassert(bp, params->port);
12305                 }
12306                 bnx2x_link_initialize(params, vars);
12307                 msleep(30);
12308                 bnx2x_link_int_enable(params);
12309                 break;
12310         }
12311         bnx2x_update_mng(params, vars->link_status);
12312
12313         bnx2x_update_mng_eee(params, vars->eee_status);
12314         return 0;
12315 }
12316
12317 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
12318                      u8 reset_ext_phy)
12319 {
12320         struct bnx2x *bp = params->bp;
12321         u8 phy_index, port = params->port, clear_latch_ind = 0;
12322         DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
12323         /* disable attentions */
12324         vars->link_status = 0;
12325         bnx2x_update_mng(params, vars->link_status);
12326         vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
12327                               SHMEM_EEE_ACTIVE_BIT);
12328         bnx2x_update_mng_eee(params, vars->eee_status);
12329         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
12330                        (NIG_MASK_XGXS0_LINK_STATUS |
12331                         NIG_MASK_XGXS0_LINK10G |
12332                         NIG_MASK_SERDES0_LINK_STATUS |
12333                         NIG_MASK_MI_INT));
12334
12335         /* activate nig drain */
12336         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
12337
12338         /* disable nig egress interface */
12339         if (!CHIP_IS_E3(bp)) {
12340                 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
12341                 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
12342         }
12343
12344         /* Stop BigMac rx */
12345         if (!CHIP_IS_E3(bp))
12346                 bnx2x_bmac_rx_disable(bp, port);
12347         else {
12348                 bnx2x_xmac_disable(params);
12349                 bnx2x_umac_disable(params);
12350         }
12351         /* disable emac */
12352         if (!CHIP_IS_E3(bp))
12353                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
12354
12355         msleep(10);
12356         /* The PHY reset is controlled by GPIO 1
12357          * Hold it as vars low
12358          */
12359          /* clear link led */
12360         bnx2x_set_mdio_clk(bp, params->chip_id, port);
12361         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
12362
12363         if (reset_ext_phy) {
12364                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
12365                       phy_index++) {
12366                         if (params->phy[phy_index].link_reset) {
12367                                 bnx2x_set_aer_mmd(params,
12368                                                   &params->phy[phy_index]);
12369                                 params->phy[phy_index].link_reset(
12370                                         &params->phy[phy_index],
12371                                         params);
12372                         }
12373                         if (params->phy[phy_index].flags &
12374                             FLAGS_REARM_LATCH_SIGNAL)
12375                                 clear_latch_ind = 1;
12376                 }
12377         }
12378
12379         if (clear_latch_ind) {
12380                 /* Clear latching indication */
12381                 bnx2x_rearm_latch_signal(bp, port, 0);
12382                 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
12383                                1 << NIG_LATCH_BC_ENABLE_MI_INT);
12384         }
12385         if (params->phy[INT_PHY].link_reset)
12386                 params->phy[INT_PHY].link_reset(
12387                         &params->phy[INT_PHY], params);
12388
12389         /* disable nig ingress interface */
12390         if (!CHIP_IS_E3(bp)) {
12391                 /* reset BigMac */
12392                 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
12393                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
12394                 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
12395                 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
12396         } else {
12397                 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12398                 bnx2x_set_xumac_nig(params, 0, 0);
12399                 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12400                     MISC_REGISTERS_RESET_REG_2_XMAC)
12401                         REG_WR(bp, xmac_base + XMAC_REG_CTRL,
12402                                XMAC_CTRL_REG_SOFT_RESET);
12403         }
12404         vars->link_up = 0;
12405         vars->phy_flags = 0;
12406         return 0;
12407 }
12408
12409 /****************************************************************************/
12410 /*                              Common function                             */
12411 /****************************************************************************/
12412 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
12413                                       u32 shmem_base_path[],
12414                                       u32 shmem2_base_path[], u8 phy_index,
12415                                       u32 chip_id)
12416 {
12417         struct bnx2x_phy phy[PORT_MAX];
12418         struct bnx2x_phy *phy_blk[PORT_MAX];
12419         u16 val;
12420         s8 port = 0;
12421         s8 port_of_path = 0;
12422         u32 swap_val, swap_override;
12423         swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);
12424         swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);
12425         port ^= (swap_val && swap_override);
12426         bnx2x_ext_phy_hw_reset(bp, port);
12427         /* PART1 - Reset both phys */
12428         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12429                 u32 shmem_base, shmem2_base;
12430                 /* In E2, same phy is using for port0 of the two paths */
12431                 if (CHIP_IS_E1x(bp)) {
12432                         shmem_base = shmem_base_path[0];
12433                         shmem2_base = shmem2_base_path[0];
12434                         port_of_path = port;
12435                 } else {
12436                         shmem_base = shmem_base_path[port];
12437                         shmem2_base = shmem2_base_path[port];
12438                         port_of_path = 0;
12439                 }
12440
12441                 /* Extract the ext phy address for the port */
12442                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12443                                        port_of_path, &phy[port]) !=
12444                     0) {
12445                         DP(NETIF_MSG_LINK, "populate_phy failed\n");
12446                         return -EINVAL;
12447                 }
12448                 /* disable attentions */
12449                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12450                                port_of_path*4,
12451                                (NIG_MASK_XGXS0_LINK_STATUS |
12452                                 NIG_MASK_XGXS0_LINK10G |
12453                                 NIG_MASK_SERDES0_LINK_STATUS |
12454                                 NIG_MASK_MI_INT));
12455
12456                 /* Need to take the phy out of low power mode in order
12457                  * to write to access its registers
12458                  */
12459                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12460                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12461                                port);
12462
12463                 /* Reset the phy */
12464                 bnx2x_cl45_write(bp, &phy[port],
12465                                  MDIO_PMA_DEVAD,
12466                                  MDIO_PMA_REG_CTRL,
12467                                  1<<15);
12468         }
12469
12470         /* Add delay of 150ms after reset */
12471         msleep(150);
12472
12473         if (phy[PORT_0].addr & 0x1) {
12474                 phy_blk[PORT_0] = &(phy[PORT_1]);
12475                 phy_blk[PORT_1] = &(phy[PORT_0]);
12476         } else {
12477                 phy_blk[PORT_0] = &(phy[PORT_0]);
12478                 phy_blk[PORT_1] = &(phy[PORT_1]);
12479         }
12480
12481         /* PART2 - Download firmware to both phys */
12482         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12483                 if (CHIP_IS_E1x(bp))
12484                         port_of_path = port;
12485                 else
12486                         port_of_path = 0;
12487
12488                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12489                            phy_blk[port]->addr);
12490                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12491                                                       port_of_path))
12492                         return -EINVAL;
12493
12494                 /* Only set bit 10 = 1 (Tx power down) */
12495                 bnx2x_cl45_read(bp, phy_blk[port],
12496                                 MDIO_PMA_DEVAD,
12497                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12498
12499                 /* Phase1 of TX_POWER_DOWN reset */
12500                 bnx2x_cl45_write(bp, phy_blk[port],
12501                                  MDIO_PMA_DEVAD,
12502                                  MDIO_PMA_REG_TX_POWER_DOWN,
12503                                  (val | 1<<10));
12504         }
12505
12506         /* Toggle Transmitter: Power down and then up with 600ms delay
12507          * between
12508          */
12509         msleep(600);
12510
12511         /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12512         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12513                 /* Phase2 of POWER_DOWN_RESET */
12514                 /* Release bit 10 (Release Tx power down) */
12515                 bnx2x_cl45_read(bp, phy_blk[port],
12516                                 MDIO_PMA_DEVAD,
12517                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12518
12519                 bnx2x_cl45_write(bp, phy_blk[port],
12520                                 MDIO_PMA_DEVAD,
12521                                 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
12522                 msleep(15);
12523
12524                 /* Read modify write the SPI-ROM version select register */
12525                 bnx2x_cl45_read(bp, phy_blk[port],
12526                                 MDIO_PMA_DEVAD,
12527                                 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
12528                 bnx2x_cl45_write(bp, phy_blk[port],
12529                                  MDIO_PMA_DEVAD,
12530                                  MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
12531
12532                 /* set GPIO2 back to LOW */
12533                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12534                                MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
12535         }
12536         return 0;
12537 }
12538 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
12539                                       u32 shmem_base_path[],
12540                                       u32 shmem2_base_path[], u8 phy_index,
12541                                       u32 chip_id)
12542 {
12543         u32 val;
12544         s8 port;
12545         struct bnx2x_phy phy;
12546         /* Use port1 because of the static port-swap */
12547         /* Enable the module detection interrupt */
12548         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12549         val |= ((1<<MISC_REGISTERS_GPIO_3)|
12550                 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
12551         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12552
12553         bnx2x_ext_phy_hw_reset(bp, 0);
12554         msleep(5);
12555         for (port = 0; port < PORT_MAX; port++) {
12556                 u32 shmem_base, shmem2_base;
12557
12558                 /* In E2, same phy is using for port0 of the two paths */
12559                 if (CHIP_IS_E1x(bp)) {
12560                         shmem_base = shmem_base_path[0];
12561                         shmem2_base = shmem2_base_path[0];
12562                 } else {
12563                         shmem_base = shmem_base_path[port];
12564                         shmem2_base = shmem2_base_path[port];
12565                 }
12566                 /* Extract the ext phy address for the port */
12567                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12568                                        port, &phy) !=
12569                     0) {
12570                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12571                         return -EINVAL;
12572                 }
12573
12574                 /* Reset phy*/
12575                 bnx2x_cl45_write(bp, &phy,
12576                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
12577
12578
12579                 /* Set fault module detected LED on */
12580                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
12581                                MISC_REGISTERS_GPIO_HIGH,
12582                                port);
12583         }
12584
12585         return 0;
12586 }
12587 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
12588                                          u8 *io_gpio, u8 *io_port)
12589 {
12590
12591         u32 phy_gpio_reset = REG_RD(bp, shmem_base +
12592                                           offsetof(struct shmem_region,
12593                                 dev_info.port_hw_config[PORT_0].default_cfg));
12594         switch (phy_gpio_reset) {
12595         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
12596                 *io_gpio = 0;
12597                 *io_port = 0;
12598                 break;
12599         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
12600                 *io_gpio = 1;
12601                 *io_port = 0;
12602                 break;
12603         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
12604                 *io_gpio = 2;
12605                 *io_port = 0;
12606                 break;
12607         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
12608                 *io_gpio = 3;
12609                 *io_port = 0;
12610                 break;
12611         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
12612                 *io_gpio = 0;
12613                 *io_port = 1;
12614                 break;
12615         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
12616                 *io_gpio = 1;
12617                 *io_port = 1;
12618                 break;
12619         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
12620                 *io_gpio = 2;
12621                 *io_port = 1;
12622                 break;
12623         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
12624                 *io_gpio = 3;
12625                 *io_port = 1;
12626                 break;
12627         default:
12628                 /* Don't override the io_gpio and io_port */
12629                 break;
12630         }
12631 }
12632
12633 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
12634                                       u32 shmem_base_path[],
12635                                       u32 shmem2_base_path[], u8 phy_index,
12636                                       u32 chip_id)
12637 {
12638         s8 port, reset_gpio;
12639         u32 swap_val, swap_override;
12640         struct bnx2x_phy phy[PORT_MAX];
12641         struct bnx2x_phy *phy_blk[PORT_MAX];
12642         s8 port_of_path;
12643         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12644         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12645
12646         reset_gpio = MISC_REGISTERS_GPIO_1;
12647         port = 1;
12648
12649         /* Retrieve the reset gpio/port which control the reset.
12650          * Default is GPIO1, PORT1
12651          */
12652         bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
12653                                      (u8 *)&reset_gpio, (u8 *)&port);
12654
12655         /* Calculate the port based on port swap */
12656         port ^= (swap_val && swap_override);
12657
12658         /* Initiate PHY reset*/
12659         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
12660                        port);
12661         msleep(1);
12662         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12663                        port);
12664
12665         msleep(5);
12666
12667         /* PART1 - Reset both phys */
12668         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12669                 u32 shmem_base, shmem2_base;
12670
12671                 /* In E2, same phy is using for port0 of the two paths */
12672                 if (CHIP_IS_E1x(bp)) {
12673                         shmem_base = shmem_base_path[0];
12674                         shmem2_base = shmem2_base_path[0];
12675                         port_of_path = port;
12676                 } else {
12677                         shmem_base = shmem_base_path[port];
12678                         shmem2_base = shmem2_base_path[port];
12679                         port_of_path = 0;
12680                 }
12681
12682                 /* Extract the ext phy address for the port */
12683                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12684                                        port_of_path, &phy[port]) !=
12685                                        0) {
12686                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12687                         return -EINVAL;
12688                 }
12689                 /* disable attentions */
12690                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12691                                port_of_path*4,
12692                                (NIG_MASK_XGXS0_LINK_STATUS |
12693                                 NIG_MASK_XGXS0_LINK10G |
12694                                 NIG_MASK_SERDES0_LINK_STATUS |
12695                                 NIG_MASK_MI_INT));
12696
12697
12698                 /* Reset the phy */
12699                 bnx2x_cl45_write(bp, &phy[port],
12700                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
12701         }
12702
12703         /* Add delay of 150ms after reset */
12704         msleep(150);
12705         if (phy[PORT_0].addr & 0x1) {
12706                 phy_blk[PORT_0] = &(phy[PORT_1]);
12707                 phy_blk[PORT_1] = &(phy[PORT_0]);
12708         } else {
12709                 phy_blk[PORT_0] = &(phy[PORT_0]);
12710                 phy_blk[PORT_1] = &(phy[PORT_1]);
12711         }
12712         /* PART2 - Download firmware to both phys */
12713         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12714                 if (CHIP_IS_E1x(bp))
12715                         port_of_path = port;
12716                 else
12717                         port_of_path = 0;
12718                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12719                            phy_blk[port]->addr);
12720                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12721                                                       port_of_path))
12722                         return -EINVAL;
12723                 /* Disable PHY transmitter output */
12724                 bnx2x_cl45_write(bp, phy_blk[port],
12725                                  MDIO_PMA_DEVAD,
12726                                  MDIO_PMA_REG_TX_DISABLE, 1);
12727
12728         }
12729         return 0;
12730 }
12731
12732 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
12733                                                 u32 shmem_base_path[],
12734                                                 u32 shmem2_base_path[],
12735                                                 u8 phy_index,
12736                                                 u32 chip_id)
12737 {
12738         u8 reset_gpios;
12739         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
12740         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
12741         udelay(10);
12742         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
12743         DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
12744                 reset_gpios);
12745         return 0;
12746 }
12747
12748 static int bnx2x_84833_pre_init_phy(struct bnx2x *bp,
12749                                                struct bnx2x_phy *phy)
12750 {
12751         u16 val, cnt;
12752         /* Wait for FW completing its initialization. */
12753         for (cnt = 0; cnt < 1500; cnt++) {
12754                 bnx2x_cl45_read(bp, phy,
12755                                 MDIO_PMA_DEVAD,
12756                                 MDIO_PMA_REG_CTRL, &val);
12757                 if (!(val & (1<<15)))
12758                         break;
12759                 msleep(1);
12760         }
12761         if (cnt >= 1500) {
12762                 DP(NETIF_MSG_LINK, "84833 reset timeout\n");
12763                 return -EINVAL;
12764         }
12765
12766         /* Put the port in super isolate mode. */
12767         bnx2x_cl45_read(bp, phy,
12768                         MDIO_CTL_DEVAD,
12769                         MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
12770         val |= MDIO_84833_SUPER_ISOLATE;
12771         bnx2x_cl45_write(bp, phy,
12772                          MDIO_CTL_DEVAD,
12773                          MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
12774
12775         /* Save spirom version */
12776         bnx2x_save_848xx_spirom_version(phy, bp, PORT_0);
12777         return 0;
12778 }
12779
12780 int bnx2x_pre_init_phy(struct bnx2x *bp,
12781                                   u32 shmem_base,
12782                                   u32 shmem2_base,
12783                                   u32 chip_id)
12784 {
12785         int rc = 0;
12786         struct bnx2x_phy phy;
12787         bnx2x_set_mdio_clk(bp, chip_id, PORT_0);
12788         if (bnx2x_populate_phy(bp, EXT_PHY1, shmem_base, shmem2_base,
12789                                PORT_0, &phy)) {
12790                 DP(NETIF_MSG_LINK, "populate_phy failed\n");
12791                 return -EINVAL;
12792         }
12793         switch (phy.type) {
12794         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12795                 rc = bnx2x_84833_pre_init_phy(bp, &phy);
12796                 break;
12797         default:
12798                 break;
12799         }
12800         return rc;
12801 }
12802
12803 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
12804                                      u32 shmem2_base_path[], u8 phy_index,
12805                                      u32 ext_phy_type, u32 chip_id)
12806 {
12807         int rc = 0;
12808
12809         switch (ext_phy_type) {
12810         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12811                 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
12812                                                 shmem2_base_path,
12813                                                 phy_index, chip_id);
12814                 break;
12815         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12816         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12817         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12818                 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
12819                                                 shmem2_base_path,
12820                                                 phy_index, chip_id);
12821                 break;
12822
12823         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12824                 /* GPIO1 affects both ports, so there's need to pull
12825                  * it for single port alone
12826                  */
12827                 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
12828                                                 shmem2_base_path,
12829                                                 phy_index, chip_id);
12830                 break;
12831         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12832                 /* GPIO3's are linked, and so both need to be toggled
12833                  * to obtain required 2us pulse.
12834                  */
12835                 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path,
12836                                                 shmem2_base_path,
12837                                                 phy_index, chip_id);
12838                 break;
12839         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12840                 rc = -EINVAL;
12841                 break;
12842         default:
12843                 DP(NETIF_MSG_LINK,
12844                            "ext_phy 0x%x common init not required\n",
12845                            ext_phy_type);
12846                 break;
12847         }
12848
12849         if (rc != 0)
12850                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
12851                                       " Port %d\n",
12852                          0);
12853         return rc;
12854 }
12855
12856 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
12857                           u32 shmem2_base_path[], u32 chip_id)
12858 {
12859         int rc = 0;
12860         u32 phy_ver, val;
12861         u8 phy_index = 0;
12862         u32 ext_phy_type, ext_phy_config;
12863         bnx2x_set_mdio_clk(bp, chip_id, PORT_0);
12864         bnx2x_set_mdio_clk(bp, chip_id, PORT_1);
12865         DP(NETIF_MSG_LINK, "Begin common phy init\n");
12866         if (CHIP_IS_E3(bp)) {
12867                 /* Enable EPIO */
12868                 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
12869                 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
12870         }
12871         /* Check if common init was already done */
12872         phy_ver = REG_RD(bp, shmem_base_path[0] +
12873                          offsetof(struct shmem_region,
12874                                   port_mb[PORT_0].ext_phy_fw_version));
12875         if (phy_ver) {
12876                 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
12877                                phy_ver);
12878                 return 0;
12879         }
12880
12881         /* Read the ext_phy_type for arbitrary port(0) */
12882         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12883               phy_index++) {
12884                 ext_phy_config = bnx2x_get_ext_phy_config(bp,
12885                                                           shmem_base_path[0],
12886                                                           phy_index, 0);
12887                 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
12888                 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
12889                                                 shmem2_base_path,
12890                                                 phy_index, ext_phy_type,
12891                                                 chip_id);
12892         }
12893         return rc;
12894 }
12895
12896 static void bnx2x_check_over_curr(struct link_params *params,
12897                                   struct link_vars *vars)
12898 {
12899         struct bnx2x *bp = params->bp;
12900         u32 cfg_pin;
12901         u8 port = params->port;
12902         u32 pin_val;
12903
12904         cfg_pin = (REG_RD(bp, params->shmem_base +
12905                           offsetof(struct shmem_region,
12906                                dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
12907                    PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
12908                 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
12909
12910         /* Ignore check if no external input PIN available */
12911         if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
12912                 return;
12913
12914         if (!pin_val) {
12915                 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
12916                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
12917                                             " been detected and the power to "
12918                                             "that SFP+ module has been removed"
12919                                             " to prevent failure of the card."
12920                                             " Please remove the SFP+ module and"
12921                                             " restart the system to clear this"
12922                                             " error.\n",
12923                          params->port);
12924                         vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
12925                 }
12926         } else
12927                 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
12928 }
12929
12930 /* Returns 0 if no change occured since last check; 1 otherwise. */
12931 static u8 bnx2x_analyze_link_error(struct link_params *params,
12932                                     struct link_vars *vars, u32 status,
12933                                     u32 phy_flag, u32 link_flag, u8 notify)
12934 {
12935         struct bnx2x *bp = params->bp;
12936         /* Compare new value with previous value */
12937         u8 led_mode;
12938         u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
12939
12940         if ((status ^ old_status) == 0)
12941                 return 0;
12942
12943         /* If values differ */
12944         switch (phy_flag) {
12945         case PHY_HALF_OPEN_CONN_FLAG:
12946                 DP(NETIF_MSG_LINK, "Analyze Remote Fault\n");
12947                 break;
12948         case PHY_SFP_TX_FAULT_FLAG:
12949                 DP(NETIF_MSG_LINK, "Analyze TX Fault\n");
12950                 break;
12951         default:
12952                 DP(NETIF_MSG_LINK, "Analyze UNKOWN\n");
12953         }
12954         DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up,
12955            old_status, status);
12956
12957         /* a. Update shmem->link_status accordingly
12958          * b. Update link_vars->link_up
12959          */
12960         if (status) {
12961                 vars->link_status &= ~LINK_STATUS_LINK_UP;
12962                 vars->link_status |= link_flag;
12963                 vars->link_up = 0;
12964                 vars->phy_flags |= phy_flag;
12965
12966                 /* activate nig drain */
12967                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
12968                 /* Set LED mode to off since the PHY doesn't know about these
12969                  * errors
12970                  */
12971                 led_mode = LED_MODE_OFF;
12972         } else {
12973                 vars->link_status |= LINK_STATUS_LINK_UP;
12974                 vars->link_status &= ~link_flag;
12975                 vars->link_up = 1;
12976                 vars->phy_flags &= ~phy_flag;
12977                 led_mode = LED_MODE_OPER;
12978
12979                 /* Clear nig drain */
12980                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12981         }
12982         bnx2x_sync_link(params, vars);
12983         /* Update the LED according to the link state */
12984         bnx2x_set_led(params, vars, led_mode, SPEED_10000);
12985
12986         /* Update link status in the shared memory */
12987         bnx2x_update_mng(params, vars->link_status);
12988
12989         /* C. Trigger General Attention */
12990         vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
12991         if (notify)
12992                 bnx2x_notify_link_changed(bp);
12993
12994         return 1;
12995 }
12996
12997 /******************************************************************************
12998 * Description:
12999 *       This function checks for half opened connection change indication.
13000 *       When such change occurs, it calls the bnx2x_analyze_link_error
13001 *       to check if Remote Fault is set or cleared. Reception of remote fault
13002 *       status message in the MAC indicates that the peer's MAC has detected
13003 *       a fault, for example, due to break in the TX side of fiber.
13004 *
13005 ******************************************************************************/
13006 int bnx2x_check_half_open_conn(struct link_params *params,
13007                                 struct link_vars *vars,
13008                                 u8 notify)
13009 {
13010         struct bnx2x *bp = params->bp;
13011         u32 lss_status = 0;
13012         u32 mac_base;
13013         /* In case link status is physically up @ 10G do */
13014         if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
13015             (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
13016                 return 0;
13017
13018         if (CHIP_IS_E3(bp) &&
13019             (REG_RD(bp, MISC_REG_RESET_REG_2) &
13020               (MISC_REGISTERS_RESET_REG_2_XMAC))) {
13021                 /* Check E3 XMAC */
13022                 /* Note that link speed cannot be queried here, since it may be
13023                  * zero while link is down. In case UMAC is active, LSS will
13024                  * simply not be set
13025                  */
13026                 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13027
13028                 /* Clear stick bits (Requires rising edge) */
13029                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
13030                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
13031                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
13032                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
13033                 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
13034                         lss_status = 1;
13035
13036                 bnx2x_analyze_link_error(params, vars, lss_status,
13037                                          PHY_HALF_OPEN_CONN_FLAG,
13038                                          LINK_STATUS_NONE, notify);
13039         } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
13040                    (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
13041                 /* Check E1X / E2 BMAC */
13042                 u32 lss_status_reg;
13043                 u32 wb_data[2];
13044                 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
13045                         NIG_REG_INGRESS_BMAC0_MEM;
13046                 /*  Read BIGMAC_REGISTER_RX_LSS_STATUS */
13047                 if (CHIP_IS_E2(bp))
13048                         lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
13049                 else
13050                         lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
13051
13052                 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
13053                 lss_status = (wb_data[0] > 0);
13054
13055                 bnx2x_analyze_link_error(params, vars, lss_status,
13056                                          PHY_HALF_OPEN_CONN_FLAG,
13057                                          LINK_STATUS_NONE, notify);
13058         }
13059         return 0;
13060 }
13061 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy,
13062                                          struct link_params *params,
13063                                          struct link_vars *vars)
13064 {
13065         struct bnx2x *bp = params->bp;
13066         u32 cfg_pin, value = 0;
13067         u8 led_change, port = params->port;
13068
13069         /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
13070         cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region,
13071                           dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
13072                    PORT_HW_CFG_E3_TX_FAULT_MASK) >>
13073                   PORT_HW_CFG_E3_TX_FAULT_SHIFT;
13074
13075         if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) {
13076                 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin);
13077                 return;
13078         }
13079
13080         led_change = bnx2x_analyze_link_error(params, vars, value,
13081                                               PHY_SFP_TX_FAULT_FLAG,
13082                                               LINK_STATUS_SFP_TX_FAULT, 1);
13083
13084         if (led_change) {
13085                 /* Change TX_Fault led, set link status for further syncs */
13086                 u8 led_mode;
13087
13088                 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
13089                         led_mode = MISC_REGISTERS_GPIO_HIGH;
13090                         vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
13091                 } else {
13092                         led_mode = MISC_REGISTERS_GPIO_LOW;
13093                         vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13094                 }
13095
13096                 /* If module is unapproved, led should be on regardless */
13097                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
13098                         DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n",
13099                            led_mode);
13100                         bnx2x_set_e3_module_fault_led(params, led_mode);
13101                 }
13102         }
13103 }
13104 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
13105 {
13106         u16 phy_idx;
13107         struct bnx2x *bp = params->bp;
13108         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
13109                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
13110                         bnx2x_set_aer_mmd(params, &params->phy[phy_idx]);
13111                         if (bnx2x_check_half_open_conn(params, vars, 1) !=
13112                             0)
13113                                 DP(NETIF_MSG_LINK, "Fault detection failed\n");
13114                         break;
13115                 }
13116         }
13117
13118         if (CHIP_IS_E3(bp)) {
13119                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
13120                 bnx2x_set_aer_mmd(params, phy);
13121                 bnx2x_check_over_curr(params, vars);
13122                 if (vars->rx_tx_asic_rst)
13123                         bnx2x_warpcore_config_runtime(phy, params, vars);
13124
13125                 if ((REG_RD(bp, params->shmem_base +
13126                             offsetof(struct shmem_region, dev_info.
13127                                 port_hw_config[params->port].default_cfg))
13128                     & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
13129                     PORT_HW_CFG_NET_SERDES_IF_SFI) {
13130                         if (bnx2x_is_sfp_module_plugged(phy, params)) {
13131                                 bnx2x_sfp_tx_fault_detection(phy, params, vars);
13132                         } else if (vars->link_status &
13133                                 LINK_STATUS_SFP_TX_FAULT) {
13134                                 /* Clean trail, interrupt corrects the leds */
13135                                 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13136                                 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
13137                                 /* Update link status in the shared memory */
13138                                 bnx2x_update_mng(params, vars->link_status);
13139                         }
13140                 }
13141
13142         }
13143
13144 }
13145
13146 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
13147 {
13148         u8 phy_index;
13149         struct bnx2x_phy phy;
13150         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
13151               phy_index++) {
13152                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13153                                        0, &phy) != 0) {
13154                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13155                         return 0;
13156                 }
13157
13158                 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
13159                         return 1;
13160         }
13161         return 0;
13162 }
13163
13164 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
13165                              u32 shmem_base,
13166                              u32 shmem2_base,
13167                              u8 port)
13168 {
13169         u8 phy_index, fan_failure_det_req = 0;
13170         struct bnx2x_phy phy;
13171         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13172               phy_index++) {
13173                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13174                                        port, &phy)
13175                     != 0) {
13176                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13177                         return 0;
13178                 }
13179                 fan_failure_det_req |= (phy.flags &
13180                                         FLAGS_FAN_FAILURE_DET_REQ);
13181         }
13182         return fan_failure_det_req;
13183 }
13184
13185 void bnx2x_hw_reset_phy(struct link_params *params)
13186 {
13187         u8 phy_index;
13188         struct bnx2x *bp = params->bp;
13189         bnx2x_update_mng(params, 0);
13190         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
13191                        (NIG_MASK_XGXS0_LINK_STATUS |
13192                         NIG_MASK_XGXS0_LINK10G |
13193                         NIG_MASK_SERDES0_LINK_STATUS |
13194                         NIG_MASK_MI_INT));
13195
13196         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
13197               phy_index++) {
13198                 if (params->phy[phy_index].hw_reset) {
13199                         params->phy[phy_index].hw_reset(
13200                                 &params->phy[phy_index],
13201                                 params);
13202                         params->phy[phy_index] = phy_null;
13203                 }
13204         }
13205 }
13206
13207 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
13208                             u32 chip_id, u32 shmem_base, u32 shmem2_base,
13209                             u8 port)
13210 {
13211         u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
13212         u32 val;
13213         u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
13214         if (CHIP_IS_E3(bp)) {
13215                 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
13216                                               shmem_base,
13217                                               port,
13218                                               &gpio_num,
13219                                               &gpio_port) != 0)
13220                         return;
13221         } else {
13222                 struct bnx2x_phy phy;
13223                 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13224                       phy_index++) {
13225                         if (bnx2x_populate_phy(bp, phy_index, shmem_base,
13226                                                shmem2_base, port, &phy)
13227                             != 0) {
13228                                 DP(NETIF_MSG_LINK, "populate phy failed\n");
13229                                 return;
13230                         }
13231                         if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
13232                                 gpio_num = MISC_REGISTERS_GPIO_3;
13233                                 gpio_port = port;
13234                                 break;
13235                         }
13236                 }
13237         }
13238
13239         if (gpio_num == 0xff)
13240                 return;
13241
13242         /* Set GPIO3 to trigger SFP+ module insertion/removal */
13243         bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
13244
13245         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13246         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13247         gpio_port ^= (swap_val && swap_override);
13248
13249         vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
13250                 (gpio_num + (gpio_port << 2));
13251
13252         sync_offset = shmem_base +
13253                 offsetof(struct shmem_region,
13254                          dev_info.port_hw_config[port].aeu_int_mask);
13255         REG_WR(bp, sync_offset, vars->aeu_int_mask);
13256
13257         DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
13258                        gpio_num, gpio_port, vars->aeu_int_mask);
13259
13260         if (port == 0)
13261                 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
13262         else
13263                 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
13264
13265         /* Open appropriate AEU for interrupts */
13266         aeu_mask = REG_RD(bp, offset);
13267         aeu_mask |= vars->aeu_int_mask;
13268         REG_WR(bp, offset, aeu_mask);
13269
13270         /* Enable the GPIO to trigger interrupt */
13271         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
13272         val |= 1 << (gpio_num + (gpio_port << 2));
13273         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
13274 }