drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

   1 /* Copyright 2008-2012 Broadcom Corporation
   2  *
   3  * Unless you and Broadcom execute a separate written software license
   4  * agreement governing use of this software, this software is licensed to you
   5  * under the terms of the GNU General Public License version 2, available
   6  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
   7  *
   8  * Notwithstanding the above, under no circumstances may you combine this
   9  * software in any way with any other Broadcom software provided under a
  10  * license other than the GPL, without Broadcom's express prior written
  11  * consent.
  12  *
  13  * Written by Yaniv Rosner
  14  *
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/delay.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/mutex.h>
  26
  27 #include "bnx2x.h"
  28 #include "bnx2x_cmn.h"
  29
  30 /********************************************************/
  31 #define ETH_HLEN                        14
  32 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
  33 #define ETH_OVREHEAD                    (ETH_HLEN + 8 + 8)
  34 #define ETH_MIN_PACKET_SIZE             60
  35 #define ETH_MAX_PACKET_SIZE             1500
  36 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
  37 #define MDIO_ACCESS_TIMEOUT             1000
  38 #define WC_LANE_MAX                     4
  39 #define I2C_SWITCH_WIDTH                2
  40 #define I2C_BSC0                        0
  41 #define I2C_BSC1                        1
  42 #define I2C_WA_RETRY_CNT                3
  43 #define MCPR_IMC_COMMAND_READ_OP        1
  44 #define MCPR_IMC_COMMAND_WRITE_OP       2
  45
  46 /* LED Blink rate that will achieve ~15.9Hz */
  47 #define LED_BLINK_RATE_VAL_E3           354
  48 #define LED_BLINK_RATE_VAL_E1X_E2       480
  49 /***********************************************************/
  50 /*                      Shortcut definitions               */
  51 /***********************************************************/
  52
  53 #define NIG_LATCH_BC_ENABLE_MI_INT 0
  54
  55 #define NIG_STATUS_EMAC0_MI_INT \
  56                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
  57 #define NIG_STATUS_XGXS0_LINK10G \
  58                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
  59 #define NIG_STATUS_XGXS0_LINK_STATUS \
  60                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
  61 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
  62                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
  63 #define NIG_STATUS_SERDES0_LINK_STATUS \
  64                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
  65 #define NIG_MASK_MI_INT \
  66                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
  67 #define NIG_MASK_XGXS0_LINK10G \
  68                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
  69 #define NIG_MASK_XGXS0_LINK_STATUS \
  70                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
  71 #define NIG_MASK_SERDES0_LINK_STATUS \
  72                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
  73
  74 #define MDIO_AN_CL73_OR_37_COMPLETE \
  75                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
  76                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
  77
  78 #define XGXS_RESET_BITS \
  79         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
  80          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
  81          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
  82          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
  83          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
  84
  85 #define SERDES_RESET_BITS \
  86         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
  87          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
  88          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
  89          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
  90
  91 #define AUTONEG_CL37            SHARED_HW_CFG_AN_ENABLE_CL37
  92 #define AUTONEG_CL73            SHARED_HW_CFG_AN_ENABLE_CL73
  93 #define AUTONEG_BAM             SHARED_HW_CFG_AN_ENABLE_BAM
  94 #define AUTONEG_PARALLEL \
  95                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
  96 #define AUTONEG_SGMII_FIBER_AUTODET \
  97                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
  98 #define AUTONEG_REMOTE_PHY      SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
  99
 100 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
 101                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
 102 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
 103                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
 104 #define GP_STATUS_SPEED_MASK \
 105                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
 106 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
 107 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
 108 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
 109 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
 110 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
 111 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
 112 #define GP_STATUS_10G_HIG \
 113                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
 114 #define GP_STATUS_10G_CX4 \
 115                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
 116 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
 117 #define GP_STATUS_10G_KX4 \
 118                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
 119 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
 120 #define GP_STATUS_10G_XFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
 121 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
 122 #define GP_STATUS_10G_SFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
 123 #define LINK_10THD              LINK_STATUS_SPEED_AND_DUPLEX_10THD
 124 #define LINK_10TFD              LINK_STATUS_SPEED_AND_DUPLEX_10TFD
 125 #define LINK_100TXHD            LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
 126 #define LINK_100T4              LINK_STATUS_SPEED_AND_DUPLEX_100T4
 127 #define LINK_100TXFD            LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
 128 #define LINK_1000THD            LINK_STATUS_SPEED_AND_DUPLEX_1000THD
 129 #define LINK_1000TFD            LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
 130 #define LINK_1000XFD            LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
 131 #define LINK_2500THD            LINK_STATUS_SPEED_AND_DUPLEX_2500THD
 132 #define LINK_2500TFD            LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
 133 #define LINK_2500XFD            LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
 134 #define LINK_10GTFD             LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
 135 #define LINK_10GXFD             LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
 136 #define LINK_20GTFD             LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
 137 #define LINK_20GXFD             LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
 138
 139
 140
 141 #define SFP_EEPROM_CON_TYPE_ADDR                0x2
 142         #define SFP_EEPROM_CON_TYPE_VAL_LC      0x7
 143         #define SFP_EEPROM_CON_TYPE_VAL_COPPER  0x21
 144
 145
 146 #define SFP_EEPROM_COMP_CODE_ADDR               0x3
 147         #define SFP_EEPROM_COMP_CODE_SR_MASK    (1<<4)
 148         #define SFP_EEPROM_COMP_CODE_LR_MASK    (1<<5)
 149         #define SFP_EEPROM_COMP_CODE_LRM_MASK   (1<<6)
 150
 151 #define SFP_EEPROM_FC_TX_TECH_ADDR              0x8
 152         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
 153         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE  0x8
 154
 155 #define SFP_EEPROM_OPTIONS_ADDR                 0x40
 156         #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
 157 #define SFP_EEPROM_OPTIONS_SIZE                 2
 158
 159 #define EDC_MODE_LINEAR                         0x0022
 160 #define EDC_MODE_LIMITING                               0x0044
 161 #define EDC_MODE_PASSIVE_DAC                    0x0055
 162
 163 /* BRB default for class 0 E2 */
 164 #define DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR      170
 165 #define DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR               250
 166 #define DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR               10
 167 #define DEFAULT0_E2_BRB_MAC_FULL_XON_THR                50
 168
 169 /* BRB thresholds for E2*/
 170 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE             170
 171 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE         0
 172
 173 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE              250
 174 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE          0
 175
 176 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE              10
 177 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE          90
 178
 179 #define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE                       50
 180 #define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE           250
 181
 182 /* BRB default for class 0 E3A0 */
 183 #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR    290
 184 #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR     410
 185 #define DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR     10
 186 #define DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR      50
 187
 188 /* BRB thresholds for E3A0 */
 189 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE           290
 190 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE               0
 191
 192 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE            410
 193 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE                0
 194
 195 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE            10
 196 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE                170
 197
 198 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE             50
 199 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE         410
 200
 201 /* BRB default for E3B0 */
 202 #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR    330
 203 #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR     490
 204 #define DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR     15
 205 #define DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR      55
 206
 207 /* BRB thresholds for E3B0 2 port mode*/
 208 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE                1025
 209 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE    0
 210
 211 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE         1025
 212 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE     0
 213
 214 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE         10
 215 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE     1025
 216
 217 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE          50
 218 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE      1025
 219
 220 /* only for E3B0*/
 221 #define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR                        1025
 222 #define PFC_E3B0_2P_BRB_FULL_LB_XON_THR                 1025
 223
 224 /* Lossy +Lossless GUARANTIED == GUART */
 225 #define PFC_E3B0_2P_MIX_PAUSE_LB_GUART                  284
 226 /* Lossless +Lossless*/
 227 #define PFC_E3B0_2P_PAUSE_LB_GUART                      236
 228 /* Lossy +Lossy*/
 229 #define PFC_E3B0_2P_NON_PAUSE_LB_GUART                  342
 230
 231 /* Lossy +Lossless*/
 232 #define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART               284
 233 /* Lossless +Lossless*/
 234 #define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART           236
 235 /* Lossy +Lossy*/
 236 #define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART               336
 237 #define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST                80
 238
 239 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART             0
 240 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST                0
 241
 242 /* BRB thresholds for E3B0 4 port mode */
 243 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE                304
 244 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE    0
 245
 246 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE         384
 247 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE     0
 248
 249 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE         10
 250 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE     304
 251
 252 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE          50
 253 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE      384
 254
 255 /* only for E3B0*/
 256 #define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR                        304
 257 #define PFC_E3B0_4P_BRB_FULL_LB_XON_THR                 384
 258 #define PFC_E3B0_4P_LB_GUART            120
 259
 260 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART             120
 261 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST        80
 262
 263 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART             80
 264 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST        120
 265
 266 /* Pause defines*/
 267 #define DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR                       330
 268 #define DEFAULT_E3B0_BRB_FULL_LB_XON_THR                        490
 269 #define DEFAULT_E3B0_LB_GUART           40
 270
 271 #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART            40
 272 #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST       0
 273
 274 #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART            40
 275 #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST       0
 276
 277 /* ETS defines*/
 278 #define DCBX_INVALID_COS                                        (0xFF)
 279
 280 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND         (0x5000)
 281 #define ETS_BW_LIMIT_CREDIT_WEIGHT              (0x5000)
 282 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS             (1360)
 283 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS                   (2720)
 284 #define ETS_E3B0_PBF_MIN_W_VAL                          (10000)
 285
 286 #define MAX_PACKET_SIZE                                 (9700)
 287 #define WC_UC_TIMEOUT                                   100
 288 #define MAX_KR_LINK_RETRY                               4
 289
 290 /**********************************************************/
 291 /*                     INTERFACE                          */
 292 /**********************************************************/
 293
 294 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 295         bnx2x_cl45_write(_bp, _phy, \
 296                 (_phy)->def_md_devad, \
 297                 (_bank + (_addr & 0xf)), \
 298                 _val)
 299
 300 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 301         bnx2x_cl45_read(_bp, _phy, \
 302                 (_phy)->def_md_devad, \
 303                 (_bank + (_addr & 0xf)), \
 304                 _val)
 305
 306 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
 307 {
 308         u32 val = REG_RD(bp, reg);
 309
 310         val |= bits;
 311         REG_WR(bp, reg, val);
 312         return val;
 313 }
 314
 315 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
 316 {
 317         u32 val = REG_RD(bp, reg);
 318
 319         val &= ~bits;
 320         REG_WR(bp, reg, val);
 321         return val;
 322 }
 323
 324 /******************************************************************/
 325 /*                      EPIO/GPIO section                         */
 326 /******************************************************************/
 327 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
 328 {
 329         u32 epio_mask, gp_oenable;
 330         *en = 0;
 331         /* Sanity check */
 332         if (epio_pin > 31) {
 333                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
 334                 return;
 335         }
 336
 337         epio_mask = 1 << epio_pin;
 338         /* Set this EPIO to output */
 339         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 340         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
 341
 342         *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
 343 }
 344 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
 345 {
 346         u32 epio_mask, gp_output, gp_oenable;
 347
 348         /* Sanity check */
 349         if (epio_pin > 31) {
 350                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
 351                 return;
 352         }
 353         DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
 354         epio_mask = 1 << epio_pin;
 355         /* Set this EPIO to output */
 356         gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
 357         if (en)
 358                 gp_output |= epio_mask;
 359         else
 360                 gp_output &= ~epio_mask;
 361
 362         REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
 363
 364         /* Set the value for this EPIO */
 365         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 366         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
 367 }
 368
 369 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
 370 {
 371         if (pin_cfg == PIN_CFG_NA)
 372                 return;
 373         if (pin_cfg >= PIN_CFG_EPIO0) {
 374                 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 375         } else {
 376                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 377                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 378                 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
 379         }
 380 }
 381
 382 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
 383 {
 384         if (pin_cfg == PIN_CFG_NA)
 385                 return -EINVAL;
 386         if (pin_cfg >= PIN_CFG_EPIO0) {
 387                 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 388         } else {
 389                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 390                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 391                 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
 392         }
 393         return 0;
 394
 395 }
 396 /******************************************************************/
 397 /*                              ETS section                       */
 398 /******************************************************************/
 399 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
 400 {
 401         /* ETS disabled configuration*/
 402         struct bnx2x *bp = params->bp;
 403
 404         DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
 405
 406         /* mapping between entry  priority to client number (0,1,2 -debug and
 407          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 408          * 3bits client num.
 409          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 410          * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
 411          */
 412
 413         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
 414         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
 415          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 416          * COS0 entry, 4 - COS1 entry.
 417          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 418          * bit4   bit3    bit2   bit1     bit0
 419          * MCP and debug are strict
 420          */
 421
 422         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 423         /* defines which entries (clients) are subjected to WFQ arbitration */
 424         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 425         /* For strict priority entries defines the number of consecutive
 426          * slots for the highest priority.
 427          */
 428         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 429         /* mapping between the CREDIT_WEIGHT registers and actual client
 430          * numbers
 431          */
 432         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
 433         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
 434         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
 435
 436         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
 437         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
 438         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
 439         /* ETS mode disable */
 440         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 441         /* If ETS mode is enabled (there is no strict priority) defines a WFQ
 442          * weight for COS0/COS1.
 443          */
 444         REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
 445         REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
 446         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
 447         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
 448         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
 449         /* Defines the number of consecutive slots for the strict priority */
 450         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 451 }
 452 /******************************************************************************
 453 * Description:
 454 *       Getting min_w_val will be set according to line speed .
 455 *.
 456 ******************************************************************************/
 457 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
 458 {
 459         u32 min_w_val = 0;
 460         /* Calculate min_w_val.*/
 461         if (vars->link_up) {
 462                 if (vars->line_speed == SPEED_20000)
 463                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 464                 else
 465                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
 466         } else
 467                 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 468         /* If the link isn't up (static configuration for example ) The
 469          * link will be according to 20GBPS.
 470          */
 471         return min_w_val;
 472 }
 473 /******************************************************************************
 474 * Description:
 475 *       Getting credit upper bound form min_w_val.
 476 *.
 477 ******************************************************************************/
 478 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
 479 {
 480         const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
 481                                                 MAX_PACKET_SIZE);
 482         return credit_upper_bound;
 483 }
 484 /******************************************************************************
 485 * Description:
 486 *       Set credit upper bound for NIG.
 487 *.
 488 ******************************************************************************/
 489 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
 490         const struct link_params *params,
 491         const u32 min_w_val)
 492 {
 493         struct bnx2x *bp = params->bp;
 494         const u8 port = params->port;
 495         const u32 credit_upper_bound =
 496             bnx2x_ets_get_credit_upper_bound(min_w_val);
 497
 498         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
 499                 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
 500         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
 501                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
 502         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
 503                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
 504         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
 505                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
 506         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
 507                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
 508         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
 509                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
 510
 511         if (!port) {
 512                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
 513                         credit_upper_bound);
 514                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
 515                         credit_upper_bound);
 516                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
 517                         credit_upper_bound);
 518         }
 519 }
 520 /******************************************************************************
 521 * Description:
 522 *       Will return the NIG ETS registers to init values.Except
 523 *       credit_upper_bound.
 524 *       That isn't used in this configuration (No WFQ is enabled) and will be
 525 *       configured acording to spec
 526 *.
 527 ******************************************************************************/
 528 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
 529                                         const struct link_vars *vars)
 530 {
 531         struct bnx2x *bp = params->bp;
 532         const u8 port = params->port;
 533         const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
 534         /* Mapping between entry  priority to client number (0,1,2 -debug and
 535          * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
 536          * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
 537          * reset value or init tool
 538          */
 539         if (port) {
 540                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
 541                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
 542         } else {
 543                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
 544                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
 545         }
 546         /* For strict priority entries defines the number of consecutive
 547          * slots for the highest priority.
 548          */
 549         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
 550                    NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 551         /* Mapping between the CREDIT_WEIGHT registers and actual client
 552          * numbers
 553          */
 554         if (port) {
 555                 /*Port 1 has 6 COS*/
 556                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
 557                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
 558         } else {
 559                 /*Port 0 has 9 COS*/
 560                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
 561                        0x43210876);
 562                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
 563         }
 564
 565         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
 566          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 567          * COS0 entry, 4 - COS1 entry.
 568          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 569          * bit4   bit3    bit2   bit1     bit0
 570          * MCP and debug are strict
 571          */
 572         if (port)
 573                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
 574         else
 575                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
 576         /* defines which entries (clients) are subjected to WFQ arbitration */
 577         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 578                    NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 579
 580         /* Please notice the register address are note continuous and a
 581          * for here is note appropriate.In 2 port mode port0 only COS0-5
 582          * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
 583          * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
 584          * are never used for WFQ
 585          */
 586         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 587                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
 588         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 589                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
 590         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 591                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
 592         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
 593                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
 594         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
 595                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
 596         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
 597                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
 598         if (!port) {
 599                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
 600                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
 601                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
 602         }
 603
 604         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
 605 }
 606 /******************************************************************************
 607 * Description:
 608 *       Set credit upper bound for PBF.
 609 *.
 610 ******************************************************************************/
 611 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
 612         const struct link_params *params,
 613         const u32 min_w_val)
 614 {
 615         struct bnx2x *bp = params->bp;
 616         const u32 credit_upper_bound =
 617             bnx2x_ets_get_credit_upper_bound(min_w_val);
 618         const u8 port = params->port;
 619         u32 base_upper_bound = 0;
 620         u8 max_cos = 0;
 621         u8 i = 0;
 622         /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
 623          * port mode port1 has COS0-2 that can be used for WFQ.
 624          */
 625         if (!port) {
 626                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
 627                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 628         } else {
 629                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
 630                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 631         }
 632
 633         for (i = 0; i < max_cos; i++)
 634                 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
 635 }
 636
 637 /******************************************************************************
 638 * Description:
 639 *       Will return the PBF ETS registers to init values.Except
 640 *       credit_upper_bound.
 641 *       That isn't used in this configuration (No WFQ is enabled) and will be
 642 *       configured acording to spec
 643 *.
 644 ******************************************************************************/
 645 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
 646 {
 647         struct bnx2x *bp = params->bp;
 648         const u8 port = params->port;
 649         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
 650         u8 i = 0;
 651         u32 base_weight = 0;
 652         u8 max_cos = 0;
 653
 654         /* Mapping between entry  priority to client number 0 - COS0
 655          * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
 656          * TODO_ETS - Should be done by reset value or init tool
 657          */
 658         if (port)
 659                 /*  0x688 (|011|0 10|00 1|000) */
 660                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
 661         else
 662                 /*  (10 1|100 |011|0 10|00 1|000) */
 663                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
 664
 665         /* TODO_ETS - Should be done by reset value or init tool */
 666         if (port)
 667                 /* 0x688 (|011|0 10|00 1|000)*/
 668                 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
 669         else
 670         /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
 671         REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
 672
 673         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
 674                    PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
 675
 676
 677         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 678                    PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
 679
 680         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 681                    PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
 682         /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
 683          * In 4 port mode port1 has COS0-2 that can be used for WFQ.
 684          */
 685         if (!port) {
 686                 base_weight = PBF_REG_COS0_WEIGHT_P0;
 687                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 688         } else {
 689                 base_weight = PBF_REG_COS0_WEIGHT_P1;
 690                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 691         }
 692
 693         for (i = 0; i < max_cos; i++)
 694                 REG_WR(bp, base_weight + (0x4 * i), 0);
 695
 696         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
 697 }
 698 /******************************************************************************
 699 * Description:
 700 *       E3B0 disable will return basicly the values to init values.
 701 *.
 702 ******************************************************************************/
 703 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
 704                                    const struct link_vars *vars)
 705 {
 706         struct bnx2x *bp = params->bp;
 707
 708         if (!CHIP_IS_E3B0(bp)) {
 709                 DP(NETIF_MSG_LINK,
 710                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
 711                 return -EINVAL;
 712         }
 713
 714         bnx2x_ets_e3b0_nig_disabled(params, vars);
 715
 716         bnx2x_ets_e3b0_pbf_disabled(params);
 717
 718         return 0;
 719 }
 720
 721 /******************************************************************************
 722 * Description:
 723 *       Disable will return basicly the values to init values.
 724 *
 725 ******************************************************************************/
 726 int bnx2x_ets_disabled(struct link_params *params,
 727                       struct link_vars *vars)
 728 {
 729         struct bnx2x *bp = params->bp;
 730         int bnx2x_status = 0;
 731
 732         if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
 733                 bnx2x_ets_e2e3a0_disabled(params);
 734         else if (CHIP_IS_E3B0(bp))
 735                 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
 736         else {
 737                 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
 738                 return -EINVAL;
 739         }
 740
 741         return bnx2x_status;
 742 }
 743
 744 /******************************************************************************
 745 * Description
 746 *       Set the COS mappimg to SP and BW until this point all the COS are not
 747 *       set as SP or BW.
 748 ******************************************************************************/
 749 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
 750                                   const struct bnx2x_ets_params *ets_params,
 751                                   const u8 cos_sp_bitmap,
 752                                   const u8 cos_bw_bitmap)
 753 {
 754         struct bnx2x *bp = params->bp;
 755         const u8 port = params->port;
 756         const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
 757         const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
 758         const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
 759         const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
 760
 761         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
 762                NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
 763
 764         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 765                PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
 766
 767         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 768                NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
 769                nig_cli_subject2wfq_bitmap);
 770
 771         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 772                PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
 773                pbf_cli_subject2wfq_bitmap);
 774
 775         return 0;
 776 }
 777
 778 /******************************************************************************
 779 * Description:
 780 *       This function is needed because NIG ARB_CREDIT_WEIGHT_X are
 781 *       not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
 782 ******************************************************************************/
 783 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
 784                                      const u8 cos_entry,
 785                                      const u32 min_w_val_nig,
 786                                      const u32 min_w_val_pbf,
 787                                      const u16 total_bw,
 788                                      const u8 bw,
 789                                      const u8 port)
 790 {
 791         u32 nig_reg_adress_crd_weight = 0;
 792         u32 pbf_reg_adress_crd_weight = 0;
 793         /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
 794         const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
 795         const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
 796
 797         switch (cos_entry) {
 798         case 0:
 799             nig_reg_adress_crd_weight =
 800                  (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 801                      NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
 802              pbf_reg_adress_crd_weight = (port) ?
 803                  PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
 804              break;
 805         case 1:
 806              nig_reg_adress_crd_weight = (port) ?
 807                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 808                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
 809              pbf_reg_adress_crd_weight = (port) ?
 810                  PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
 811              break;
 812         case 2:
 813              nig_reg_adress_crd_weight = (port) ?
 814                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 815                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
 816
 817                  pbf_reg_adress_crd_weight = (port) ?
 818                      PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
 819              break;
 820         case 3:
 821             if (port)
 822                         return -EINVAL;
 823              nig_reg_adress_crd_weight =
 824                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
 825              pbf_reg_adress_crd_weight =
 826                  PBF_REG_COS3_WEIGHT_P0;
 827              break;
 828         case 4:
 829             if (port)
 830                 return -EINVAL;
 831              nig_reg_adress_crd_weight =
 832                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
 833              pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
 834              break;
 835         case 5:
 836             if (port)
 837                 return -EINVAL;
 838              nig_reg_adress_crd_weight =
 839                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
 840              pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
 841              break;
 842         }
 843
 844         REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
 845
 846         REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
 847
 848         return 0;
 849 }
 850 /******************************************************************************
 851 * Description:
 852 *       Calculate the total BW.A value of 0 isn't legal.
 853 *
 854 ******************************************************************************/
 855 static int bnx2x_ets_e3b0_get_total_bw(
 856         const struct link_params *params,
 857         struct bnx2x_ets_params *ets_params,
 858         u16 *total_bw)
 859 {
 860         struct bnx2x *bp = params->bp;
 861         u8 cos_idx = 0;
 862         u8 is_bw_cos_exist = 0;
 863
 864         *total_bw = 0 ;
 865         /* Calculate total BW requested */
 866         for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
 867                 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) {
 868                         is_bw_cos_exist = 1;
 869                         if (!ets_params->cos[cos_idx].params.bw_params.bw) {
 870                                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
 871                                                    "was set to 0\n");
 872                                 /* This is to prevent a state when ramrods
 873                                  * can't be sent
 874                                  */
 875                                 ets_params->cos[cos_idx].params.bw_params.bw
 876                                          = 1;
 877                         }
 878                         *total_bw +=
 879                                 ets_params->cos[cos_idx].params.bw_params.bw;
 880                 }
 881         }
 882
 883         /* Check total BW is valid */
 884         if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
 885                 if (*total_bw == 0) {
 886                         DP(NETIF_MSG_LINK,
 887                            "bnx2x_ets_E3B0_config total BW shouldn't be 0\n");
 888                         return -EINVAL;
 889                 }
 890                 DP(NETIF_MSG_LINK,
 891                    "bnx2x_ets_E3B0_config total BW should be 100\n");
 892                 /* We can handle a case whre the BW isn't 100 this can happen
 893                  * if the TC are joined.
 894                  */
 895         }
 896         return 0;
 897 }
 898
 899 /******************************************************************************
 900 * Description:
 901 *       Invalidate all the sp_pri_to_cos.
 902 *
 903 ******************************************************************************/
 904 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
 905 {
 906         u8 pri = 0;
 907         for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
 908                 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
 909 }
 910 /******************************************************************************
 911 * Description:
 912 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 913 *       according to sp_pri_to_cos.
 914 *
 915 ******************************************************************************/
 916 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
 917                                             u8 *sp_pri_to_cos, const u8 pri,
 918                                             const u8 cos_entry)
 919 {
 920         struct bnx2x *bp = params->bp;
 921         const u8 port = params->port;
 922         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
 923                 DCBX_E3B0_MAX_NUM_COS_PORT0;
 924
 925         if (pri >= max_num_of_cos) {
 926                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 927                    "parameter Illegal strict priority\n");
 928             return -EINVAL;
 929         }
 930
 931         if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
 932                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 933                                    "parameter There can't be two COS's with "
 934                                    "the same strict pri\n");
 935                 return -EINVAL;
 936         }
 937
 938         sp_pri_to_cos[pri] = cos_entry;
 939         return 0;
 940
 941 }
 942
 943 /******************************************************************************
 944 * Description:
 945 *       Returns the correct value according to COS and priority in
 946 *       the sp_pri_cli register.
 947 *
 948 ******************************************************************************/
 949 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
 950                                          const u8 pri_set,
 951                                          const u8 pri_offset,
 952                                          const u8 entry_size)
 953 {
 954         u64 pri_cli_nig = 0;
 955         pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
 956                                                     (pri_set + pri_offset));
 957
 958         return pri_cli_nig;
 959 }
 960 /******************************************************************************
 961 * Description:
 962 *       Returns the correct value according to COS and priority in the
 963 *       sp_pri_cli register for NIG.
 964 *
 965 ******************************************************************************/
 966 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
 967 {
 968         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
 969         const u8 nig_cos_offset = 3;
 970         const u8 nig_pri_offset = 3;
 971
 972         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
 973                 nig_pri_offset, 4);
 974
 975 }
 976 /******************************************************************************
 977 * Description:
 978 *       Returns the correct value according to COS and priority in the
 979 *       sp_pri_cli register for PBF.
 980 *
 981 ******************************************************************************/
 982 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
 983 {
 984         const u8 pbf_cos_offset = 0;
 985         const u8 pbf_pri_offset = 0;
 986
 987         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
 988                 pbf_pri_offset, 3);
 989
 990 }
 991
 992 /******************************************************************************
 993 * Description:
 994 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 995 *       according to sp_pri_to_cos.(which COS has higher priority)
 996 *
 997 ******************************************************************************/
 998 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
 999                                              u8 *sp_pri_to_cos)
1000 {
1001         struct bnx2x *bp = params->bp;
1002         u8 i = 0;
1003         const u8 port = params->port;
1004         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1005         u64 pri_cli_nig = 0x210;
1006         u32 pri_cli_pbf = 0x0;
1007         u8 pri_set = 0;
1008         u8 pri_bitmask = 0;
1009         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1010                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1011
1012         u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
1013
1014         /* Set all the strict priority first */
1015         for (i = 0; i < max_num_of_cos; i++) {
1016                 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1017                         if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) {
1018                                 DP(NETIF_MSG_LINK,
1019                                            "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1020                                            "invalid cos entry\n");
1021                                 return -EINVAL;
1022                         }
1023
1024                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1025                             sp_pri_to_cos[i], pri_set);
1026
1027                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1028                             sp_pri_to_cos[i], pri_set);
1029                         pri_bitmask = 1 << sp_pri_to_cos[i];
1030                         /* COS is used remove it from bitmap.*/
1031                         if (!(pri_bitmask & cos_bit_to_set)) {
1032                                 DP(NETIF_MSG_LINK,
1033                                         "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1034                                         "invalid There can't be two COS's with"
1035                                         " the same strict pri\n");
1036                                 return -EINVAL;
1037                         }
1038                         cos_bit_to_set &= ~pri_bitmask;
1039                         pri_set++;
1040                 }
1041         }
1042
1043         /* Set all the Non strict priority i= COS*/
1044         for (i = 0; i < max_num_of_cos; i++) {
1045                 pri_bitmask = 1 << i;
1046                 /* Check if COS was already used for SP */
1047                 if (pri_bitmask & cos_bit_to_set) {
1048                         /* COS wasn't used for SP */
1049                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1050                             i, pri_set);
1051
1052                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1053                             i, pri_set);
1054                         /* COS is used remove it from bitmap.*/
1055                         cos_bit_to_set &= ~pri_bitmask;
1056                         pri_set++;
1057                 }
1058         }
1059
1060         if (pri_set != max_num_of_cos) {
1061                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1062                                    "entries were set\n");
1063                 return -EINVAL;
1064         }
1065
1066         if (port) {
1067                 /* Only 6 usable clients*/
1068                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1069                        (u32)pri_cli_nig);
1070
1071                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1072         } else {
1073                 /* Only 9 usable clients*/
1074                 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1075                 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1076
1077                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1078                        pri_cli_nig_lsb);
1079                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1080                        pri_cli_nig_msb);
1081
1082                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1083         }
1084         return 0;
1085 }
1086
1087 /******************************************************************************
1088 * Description:
1089 *       Configure the COS to ETS according to BW and SP settings.
1090 ******************************************************************************/
1091 int bnx2x_ets_e3b0_config(const struct link_params *params,
1092                          const struct link_vars *vars,
1093                          struct bnx2x_ets_params *ets_params)
1094 {
1095         struct bnx2x *bp = params->bp;
1096         int bnx2x_status = 0;
1097         const u8 port = params->port;
1098         u16 total_bw = 0;
1099         const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1100         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1101         u8 cos_bw_bitmap = 0;
1102         u8 cos_sp_bitmap = 0;
1103         u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1104         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1105                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1106         u8 cos_entry = 0;
1107
1108         if (!CHIP_IS_E3B0(bp)) {
1109                 DP(NETIF_MSG_LINK,
1110                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
1111                 return -EINVAL;
1112         }
1113
1114         if ((ets_params->num_of_cos > max_num_of_cos)) {
1115                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1116                                    "isn't supported\n");
1117                 return -EINVAL;
1118         }
1119
1120         /* Prepare sp strict priority parameters*/
1121         bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1122
1123         /* Prepare BW parameters*/
1124         bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1125                                                    &total_bw);
1126         if (bnx2x_status) {
1127                 DP(NETIF_MSG_LINK,
1128                    "bnx2x_ets_E3B0_config get_total_bw failed\n");
1129                 return -EINVAL;
1130         }
1131
1132         /* Upper bound is set according to current link speed (min_w_val
1133          * should be the same for upper bound and COS credit val).
1134          */
1135         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1136         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1137
1138
1139         for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1140                 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1141                         cos_bw_bitmap |= (1 << cos_entry);
1142                         /* The function also sets the BW in HW(not the mappin
1143                          * yet)
1144                          */
1145                         bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1146                                 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1147                                 total_bw,
1148                                 ets_params->cos[cos_entry].params.bw_params.bw,
1149                                  port);
1150                 } else if (bnx2x_cos_state_strict ==
1151                         ets_params->cos[cos_entry].state){
1152                         cos_sp_bitmap |= (1 << cos_entry);
1153
1154                         bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1155                                 params,
1156                                 sp_pri_to_cos,
1157                                 ets_params->cos[cos_entry].params.sp_params.pri,
1158                                 cos_entry);
1159
1160                 } else {
1161                         DP(NETIF_MSG_LINK,
1162                            "bnx2x_ets_e3b0_config cos state not valid\n");
1163                         return -EINVAL;
1164                 }
1165                 if (bnx2x_status) {
1166                         DP(NETIF_MSG_LINK,
1167                            "bnx2x_ets_e3b0_config set cos bw failed\n");
1168                         return bnx2x_status;
1169                 }
1170         }
1171
1172         /* Set SP register (which COS has higher priority) */
1173         bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1174                                                          sp_pri_to_cos);
1175
1176         if (bnx2x_status) {
1177                 DP(NETIF_MSG_LINK,
1178                    "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
1179                 return bnx2x_status;
1180         }
1181
1182         /* Set client mapping of BW and strict */
1183         bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1184                                               cos_sp_bitmap,
1185                                               cos_bw_bitmap);
1186
1187         if (bnx2x_status) {
1188                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1189                 return bnx2x_status;
1190         }
1191         return 0;
1192 }
1193 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1194 {
1195         /* ETS disabled configuration */
1196         struct bnx2x *bp = params->bp;
1197         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1198         /* Defines which entries (clients) are subjected to WFQ arbitration
1199          * COS0 0x8
1200          * COS1 0x10
1201          */
1202         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1203         /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
1204          * client numbers (WEIGHT_0 does not actually have to represent
1205          * client 0)
1206          *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1207          *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
1208          */
1209         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1210
1211         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1212                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1213         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1214                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1215
1216         /* ETS mode enabled*/
1217         REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1218
1219         /* Defines the number of consecutive slots for the strict priority */
1220         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1221         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1222          * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
1223          * entry, 4 - COS1 entry.
1224          * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1225          * bit4   bit3    bit2     bit1    bit0
1226          * MCP and debug are strict
1227          */
1228         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1229
1230         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1231         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1232                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1233         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1234                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1235 }
1236
1237 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1238                         const u32 cos1_bw)
1239 {
1240         /* ETS disabled configuration*/
1241         struct bnx2x *bp = params->bp;
1242         const u32 total_bw = cos0_bw + cos1_bw;
1243         u32 cos0_credit_weight = 0;
1244         u32 cos1_credit_weight = 0;
1245
1246         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1247
1248         if ((!total_bw) ||
1249             (!cos0_bw) ||
1250             (!cos1_bw)) {
1251                 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1252                 return;
1253         }
1254
1255         cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1256                 total_bw;
1257         cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1258                 total_bw;
1259
1260         bnx2x_ets_bw_limit_common(params);
1261
1262         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1263         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1264
1265         REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1266         REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1267 }
1268
1269 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1270 {
1271         /* ETS disabled configuration*/
1272         struct bnx2x *bp = params->bp;
1273         u32 val = 0;
1274
1275         DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1276         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1277          * as strict.  Bits 0,1,2 - debug and management entries,
1278          * 3 - COS0 entry, 4 - COS1 entry.
1279          *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1280          *  bit4   bit3   bit2      bit1     bit0
1281          * MCP and debug are strict
1282          */
1283         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1284         /* For strict priority entries defines the number of consecutive slots
1285          * for the highest priority.
1286          */
1287         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1288         /* ETS mode disable */
1289         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1290         /* Defines the number of consecutive slots for the strict priority */
1291         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1292
1293         /* Defines the number of consecutive slots for the strict priority */
1294         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1295
1296         /* Mapping between entry  priority to client number (0,1,2 -debug and
1297          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1298          * 3bits client num.
1299          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1300          * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
1301          * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
1302          */
1303         val = (!strict_cos) ? 0x2318 : 0x22E0;
1304         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1305
1306         return 0;
1307 }
1308
1309 /******************************************************************/
1310 /*                      EEE section                                */
1311 /******************************************************************/
1312 static u8 bnx2x_eee_has_cap(struct link_params *params)
1313 {
1314         struct bnx2x *bp = params->bp;
1315
1316         if (REG_RD(bp, params->shmem2_base) <=
1317                    offsetof(struct shmem2_region, eee_status[params->port]))
1318                 return 0;
1319
1320         return 1;
1321 }
1322
1323 static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer)
1324 {
1325         switch (nvram_mode) {
1326         case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
1327                 *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME;
1328                 break;
1329         case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
1330                 *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME;
1331                 break;
1332         case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
1333                 *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME;
1334                 break;
1335         default:
1336                 *idle_timer = 0;
1337                 break;
1338         }
1339
1340         return 0;
1341 }
1342
1343 static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode)
1344 {
1345         switch (idle_timer) {
1346         case EEE_MODE_NVRAM_BALANCED_TIME:
1347                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
1348                 break;
1349         case EEE_MODE_NVRAM_AGGRESSIVE_TIME:
1350                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
1351                 break;
1352         case EEE_MODE_NVRAM_LATENCY_TIME:
1353                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
1354                 break;
1355         default:
1356                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
1357                 break;
1358         }
1359
1360         return 0;
1361 }
1362
1363 static u32 bnx2x_eee_calc_timer(struct link_params *params)
1364 {
1365         u32 eee_mode, eee_idle;
1366         struct bnx2x *bp = params->bp;
1367
1368         if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) {
1369                 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
1370                         /* time value in eee_mode --> used directly*/
1371                         eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK;
1372                 } else {
1373                         /* hsi value in eee_mode --> time */
1374                         if (bnx2x_eee_nvram_to_time(params->eee_mode &
1375                                                     EEE_MODE_NVRAM_MASK,
1376                                                     &eee_idle))
1377                                 return 0;
1378                 }
1379         } else {
1380                 /* hsi values in nvram --> time*/
1381                 eee_mode = ((REG_RD(bp, params->shmem_base +
1382                                     offsetof(struct shmem_region, dev_info.
1383                                     port_feature_config[params->port].
1384                                     eee_power_mode)) &
1385                              PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
1386                             PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
1387
1388                 if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle))
1389                         return 0;
1390         }
1391
1392         return eee_idle;
1393 }
1394
1395
1396 /******************************************************************/
1397 /*                      PFC section                               */
1398 /******************************************************************/
1399 static void bnx2x_update_pfc_xmac(struct link_params *params,
1400                                   struct link_vars *vars,
1401                                   u8 is_lb)
1402 {
1403         struct bnx2x *bp = params->bp;
1404         u32 xmac_base;
1405         u32 pause_val, pfc0_val, pfc1_val;
1406
1407         /* XMAC base adrr */
1408         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1409
1410         /* Initialize pause and pfc registers */
1411         pause_val = 0x18000;
1412         pfc0_val = 0xFFFF8000;
1413         pfc1_val = 0x2;
1414
1415         /* No PFC support */
1416         if (!(params->feature_config_flags &
1417               FEATURE_CONFIG_PFC_ENABLED)) {
1418
1419                 /* RX flow control - Process pause frame in receive direction
1420                  */
1421                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1422                         pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1423
1424                 /* TX flow control - Send pause packet when buffer is full */
1425                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1426                         pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1427         } else {/* PFC support */
1428                 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1429                         XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1430                         XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1431                         XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1432                         XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1433                 /* Write pause and PFC registers */
1434                 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1435                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1436                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1437                 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1438
1439         }
1440
1441         /* Write pause and PFC registers */
1442         REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1443         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1444         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1445
1446
1447         /* Set MAC address for source TX Pause/PFC frames */
1448         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1449                ((params->mac_addr[2] << 24) |
1450                 (params->mac_addr[3] << 16) |
1451                 (params->mac_addr[4] << 8) |
1452                 (params->mac_addr[5])));
1453         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1454                ((params->mac_addr[0] << 8) |
1455                 (params->mac_addr[1])));
1456
1457         udelay(30);
1458 }
1459
1460
1461 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
1462                                     u32 pfc_frames_sent[2],
1463                                     u32 pfc_frames_received[2])
1464 {
1465         /* Read pfc statistic */
1466         struct bnx2x *bp = params->bp;
1467         u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1468         u32 val_xon = 0;
1469         u32 val_xoff = 0;
1470
1471         DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
1472
1473         /* PFC received frames */
1474         val_xoff = REG_RD(bp, emac_base +
1475                                 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1476         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
1477         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1478         val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
1479
1480         pfc_frames_received[0] = val_xon + val_xoff;
1481
1482         /* PFC received sent */
1483         val_xoff = REG_RD(bp, emac_base +
1484                                 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1485         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
1486         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1487         val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
1488
1489         pfc_frames_sent[0] = val_xon + val_xoff;
1490 }
1491
1492 /* Read pfc statistic*/
1493 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1494                          u32 pfc_frames_sent[2],
1495                          u32 pfc_frames_received[2])
1496 {
1497         /* Read pfc statistic */
1498         struct bnx2x *bp = params->bp;
1499
1500         DP(NETIF_MSG_LINK, "pfc statistic\n");
1501
1502         if (!vars->link_up)
1503                 return;
1504
1505         if (vars->mac_type == MAC_TYPE_EMAC) {
1506                 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n");
1507                 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
1508                                         pfc_frames_received);
1509         }
1510 }
1511 /******************************************************************/
1512 /*                      MAC/PBF section                           */
1513 /******************************************************************/
1514 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port)
1515 {
1516         u32 mode, emac_base;
1517         /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1518          * (a value of 49==0x31) and make sure that the AUTO poll is off
1519          */
1520
1521         if (CHIP_IS_E2(bp))
1522                 emac_base = GRCBASE_EMAC0;
1523         else
1524                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1525         mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1526         mode &= ~(EMAC_MDIO_MODE_AUTO_POLL |
1527                   EMAC_MDIO_MODE_CLOCK_CNT);
1528         if (USES_WARPCORE(bp))
1529                 mode |= (74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1530         else
1531                 mode |= (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1532
1533         mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1534         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, mode);
1535
1536         udelay(40);
1537 }
1538 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1539 {
1540         u32 port4mode_ovwr_val;
1541         /* Check 4-port override enabled */
1542         port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1543         if (port4mode_ovwr_val & (1<<0)) {
1544                 /* Return 4-port mode override value */
1545                 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1546         }
1547         /* Return 4-port mode from input pin */
1548         return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1549 }
1550
1551 static void bnx2x_emac_init(struct link_params *params,
1552                             struct link_vars *vars)
1553 {
1554         /* reset and unreset the emac core */
1555         struct bnx2x *bp = params->bp;
1556         u8 port = params->port;
1557         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1558         u32 val;
1559         u16 timeout;
1560
1561         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1562                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1563         udelay(5);
1564         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1565                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1566
1567         /* init emac - use read-modify-write */
1568         /* self clear reset */
1569         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1570         EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1571
1572         timeout = 200;
1573         do {
1574                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1575                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1576                 if (!timeout) {
1577                         DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1578                         return;
1579                 }
1580                 timeout--;
1581         } while (val & EMAC_MODE_RESET);
1582         bnx2x_set_mdio_clk(bp, params->chip_id, port);
1583         /* Set mac address */
1584         val = ((params->mac_addr[0] << 8) |
1585                 params->mac_addr[1]);
1586         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1587
1588         val = ((params->mac_addr[2] << 24) |
1589                (params->mac_addr[3] << 16) |
1590                (params->mac_addr[4] << 8) |
1591                 params->mac_addr[5]);
1592         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1593 }
1594
1595 static void bnx2x_set_xumac_nig(struct link_params *params,
1596                                 u16 tx_pause_en,
1597                                 u8 enable)
1598 {
1599         struct bnx2x *bp = params->bp;
1600
1601         REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1602                enable);
1603         REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1604                enable);
1605         REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1606                NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1607 }
1608
1609 static void bnx2x_umac_disable(struct link_params *params)
1610 {
1611         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1612         struct bnx2x *bp = params->bp;
1613         if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &
1614                    (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1615                 return;
1616
1617         /* Disable RX and TX */
1618         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, 0);
1619 }
1620
1621 static void bnx2x_umac_enable(struct link_params *params,
1622                             struct link_vars *vars, u8 lb)
1623 {
1624         u32 val;
1625         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1626         struct bnx2x *bp = params->bp;
1627         /* Reset UMAC */
1628         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1629                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1630         usleep_range(1000, 1000);
1631
1632         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1633                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1634
1635         DP(NETIF_MSG_LINK, "enabling UMAC\n");
1636
1637         /* This register opens the gate for the UMAC despite its name */
1638         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1639
1640         val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1641                 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1642                 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1643                 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1644         switch (vars->line_speed) {
1645         case SPEED_10:
1646                 val |= (0<<2);
1647                 break;
1648         case SPEED_100:
1649                 val |= (1<<2);
1650                 break;
1651         case SPEED_1000:
1652                 val |= (2<<2);
1653                 break;
1654         case SPEED_2500:
1655                 val |= (3<<2);
1656                 break;
1657         default:
1658                 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1659                                vars->line_speed);
1660                 break;
1661         }
1662         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1663                 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1664
1665         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1666                 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1667
1668         if (vars->duplex == DUPLEX_HALF)
1669                 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
1670
1671         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1672         udelay(50);
1673
1674         /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1675         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1676                ((params->mac_addr[2] << 24) |
1677                 (params->mac_addr[3] << 16) |
1678                 (params->mac_addr[4] << 8) |
1679                 (params->mac_addr[5])));
1680         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1681                ((params->mac_addr[0] << 8) |
1682                 (params->mac_addr[1])));
1683
1684         /* Enable RX and TX */
1685         val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1686         val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1687                 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1688         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1689         udelay(50);
1690
1691         /* Remove SW Reset */
1692         val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1693
1694         /* Check loopback mode */
1695         if (lb)
1696                 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1697         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1698
1699         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1700          * length used by the MAC receive logic to check frames.
1701          */
1702         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1703         bnx2x_set_xumac_nig(params,
1704                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1705         vars->mac_type = MAC_TYPE_UMAC;
1706
1707 }
1708
1709 /* Define the XMAC mode */
1710 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1711 {
1712         struct bnx2x *bp = params->bp;
1713         u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1714
1715         /* In 4-port mode, need to set the mode only once, so if XMAC is
1716          * already out of reset, it means the mode has already been set,
1717          * and it must not* reset the XMAC again, since it controls both
1718          * ports of the path
1719          */
1720
1721         if ((CHIP_NUM(bp) == CHIP_NUM_57840) &&
1722             (REG_RD(bp, MISC_REG_RESET_REG_2) &
1723              MISC_REGISTERS_RESET_REG_2_XMAC)) {
1724                 DP(NETIF_MSG_LINK,
1725                    "XMAC already out of reset in 4-port mode\n");
1726                 return;
1727         }
1728
1729         /* Hard reset */
1730         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1731                MISC_REGISTERS_RESET_REG_2_XMAC);
1732         usleep_range(1000, 1000);
1733
1734         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1735                MISC_REGISTERS_RESET_REG_2_XMAC);
1736         if (is_port4mode) {
1737                 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1738
1739                 /* Set the number of ports on the system side to up to 2 */
1740                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1741
1742                 /* Set the number of ports on the Warp Core to 10G */
1743                 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1744         } else {
1745                 /* Set the number of ports on the system side to 1 */
1746                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1747                 if (max_speed == SPEED_10000) {
1748                         DP(NETIF_MSG_LINK,
1749                            "Init XMAC to 10G x 1 port per path\n");
1750                         /* Set the number of ports on the Warp Core to 10G */
1751                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1752                 } else {
1753                         DP(NETIF_MSG_LINK,
1754                            "Init XMAC to 20G x 2 ports per path\n");
1755                         /* Set the number of ports on the Warp Core to 20G */
1756                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1757                 }
1758         }
1759         /* Soft reset */
1760         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1761                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1762         usleep_range(1000, 1000);
1763
1764         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1765                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1766
1767 }
1768
1769 static void bnx2x_xmac_disable(struct link_params *params)
1770 {
1771         u8 port = params->port;
1772         struct bnx2x *bp = params->bp;
1773         u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1774
1775         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1776             MISC_REGISTERS_RESET_REG_2_XMAC) {
1777                 /* Send an indication to change the state in the NIG back to XON
1778                  * Clearing this bit enables the next set of this bit to get
1779                  * rising edge
1780                  */
1781                 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1782                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1783                        (pfc_ctrl & ~(1<<1)));
1784                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1785                        (pfc_ctrl | (1<<1)));
1786                 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1787                 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 0);
1788         }
1789 }
1790
1791 static int bnx2x_xmac_enable(struct link_params *params,
1792                              struct link_vars *vars, u8 lb)
1793 {
1794         u32 val, xmac_base;
1795         struct bnx2x *bp = params->bp;
1796         DP(NETIF_MSG_LINK, "enabling XMAC\n");
1797
1798         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1799
1800         bnx2x_xmac_init(params, vars->line_speed);
1801
1802         /* This register determines on which events the MAC will assert
1803          * error on the i/f to the NIG along w/ EOP.
1804          */
1805
1806         /* This register tells the NIG whether to send traffic to UMAC
1807          * or XMAC
1808          */
1809         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1810
1811         /* Set Max packet size */
1812         REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1813
1814         /* CRC append for Tx packets */
1815         REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1816
1817         /* update PFC */
1818         bnx2x_update_pfc_xmac(params, vars, 0);
1819
1820         if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1821                 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n");
1822                 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
1823                 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
1824         } else {
1825                 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
1826         }
1827
1828         /* Enable TX and RX */
1829         val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1830
1831         /* Check loopback mode */
1832         if (lb)
1833                 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1834         REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1835         bnx2x_set_xumac_nig(params,
1836                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1837
1838         vars->mac_type = MAC_TYPE_XMAC;
1839
1840         return 0;
1841 }
1842
1843 static int bnx2x_emac_enable(struct link_params *params,
1844                              struct link_vars *vars, u8 lb)
1845 {
1846         struct bnx2x *bp = params->bp;
1847         u8 port = params->port;
1848         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1849         u32 val;
1850
1851         DP(NETIF_MSG_LINK, "enabling EMAC\n");
1852
1853         /* Disable BMAC */
1854         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1855                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1856
1857         /* enable emac and not bmac */
1858         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1859
1860         /* ASIC */
1861         if (vars->phy_flags & PHY_XGXS_FLAG) {
1862                 u32 ser_lane = ((params->lane_config &
1863                                  PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1864                                 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1865
1866                 DP(NETIF_MSG_LINK, "XGXS\n");
1867                 /* select the master lanes (out of 0-3) */
1868                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1869                 /* select XGXS */
1870                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1871
1872         } else { /* SerDes */
1873                 DP(NETIF_MSG_LINK, "SerDes\n");
1874                 /* select SerDes */
1875                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1876         }
1877
1878         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1879                       EMAC_RX_MODE_RESET);
1880         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1881                       EMAC_TX_MODE_RESET);
1882
1883         if (CHIP_REV_IS_SLOW(bp)) {
1884                 /* config GMII mode */
1885                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1886                 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
1887         } else { /* ASIC */
1888                 /* pause enable/disable */
1889                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1890                                EMAC_RX_MODE_FLOW_EN);
1891
1892                 bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
1893                                (EMAC_TX_MODE_EXT_PAUSE_EN |
1894                                 EMAC_TX_MODE_FLOW_EN));
1895                 if (!(params->feature_config_flags &
1896                       FEATURE_CONFIG_PFC_ENABLED)) {
1897                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1898                                 bnx2x_bits_en(bp, emac_base +
1899                                               EMAC_REG_EMAC_RX_MODE,
1900                                               EMAC_RX_MODE_FLOW_EN);
1901
1902                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1903                                 bnx2x_bits_en(bp, emac_base +
1904                                               EMAC_REG_EMAC_TX_MODE,
1905                                               (EMAC_TX_MODE_EXT_PAUSE_EN |
1906                                                EMAC_TX_MODE_FLOW_EN));
1907                 } else
1908                         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1909                                       EMAC_TX_MODE_FLOW_EN);
1910         }
1911
1912         /* KEEP_VLAN_TAG, promiscuous */
1913         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1914         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1915
1916         /* Setting this bit causes MAC control frames (except for pause
1917          * frames) to be passed on for processing. This setting has no
1918          * affect on the operation of the pause frames. This bit effects
1919          * all packets regardless of RX Parser packet sorting logic.
1920          * Turn the PFC off to make sure we are in Xon state before
1921          * enabling it.
1922          */
1923         EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1924         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1925                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1926                 /* Enable PFC again */
1927                 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1928                         EMAC_REG_RX_PFC_MODE_RX_EN |
1929                         EMAC_REG_RX_PFC_MODE_TX_EN |
1930                         EMAC_REG_RX_PFC_MODE_PRIORITIES);
1931
1932                 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1933                         ((0x0101 <<
1934                           EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1935                          (0x00ff <<
1936                           EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1937                 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1938         }
1939         EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1940
1941         /* Set Loopback */
1942         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1943         if (lb)
1944                 val |= 0x810;
1945         else
1946                 val &= ~0x810;
1947         EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1948
1949         /* enable emac */
1950         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1951
1952         /* enable emac for jumbo packets */
1953         EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1954                 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1955                  (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1956
1957         /* strip CRC */
1958         REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1959
1960         /* disable the NIG in/out to the bmac */
1961         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1962         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1963         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1964
1965         /* enable the NIG in/out to the emac */
1966         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1967         val = 0;
1968         if ((params->feature_config_flags &
1969               FEATURE_CONFIG_PFC_ENABLED) ||
1970             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1971                 val = 1;
1972
1973         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1974         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1975
1976         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1977
1978         vars->mac_type = MAC_TYPE_EMAC;
1979         return 0;
1980 }
1981
1982 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1983                                    struct link_vars *vars)
1984 {
1985         u32 wb_data[2];
1986         struct bnx2x *bp = params->bp;
1987         u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1988                 NIG_REG_INGRESS_BMAC0_MEM;
1989
1990         u32 val = 0x14;
1991         if ((!(params->feature_config_flags &
1992               FEATURE_CONFIG_PFC_ENABLED)) &&
1993                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1994                 /* Enable BigMAC to react on received Pause packets */
1995                 val |= (1<<5);
1996         wb_data[0] = val;
1997         wb_data[1] = 0;
1998         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1999
2000         /* tx control */
2001         val = 0xc0;
2002         if (!(params->feature_config_flags &
2003               FEATURE_CONFIG_PFC_ENABLED) &&
2004                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2005                 val |= 0x800000;
2006         wb_data[0] = val;
2007         wb_data[1] = 0;
2008         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
2009 }
2010
2011 static void bnx2x_update_pfc_bmac2(struct link_params *params,
2012                                    struct link_vars *vars,
2013                                    u8 is_lb)
2014 {
2015         /* Set rx control: Strip CRC and enable BigMAC to relay
2016          * control packets to the system as well
2017          */
2018         u32 wb_data[2];
2019         struct bnx2x *bp = params->bp;
2020         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
2021                 NIG_REG_INGRESS_BMAC0_MEM;
2022         u32 val = 0x14;
2023
2024         if ((!(params->feature_config_flags &
2025               FEATURE_CONFIG_PFC_ENABLED)) &&
2026                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
2027                 /* Enable BigMAC to react on received Pause packets */
2028                 val |= (1<<5);
2029         wb_data[0] = val;
2030         wb_data[1] = 0;
2031         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
2032         udelay(30);
2033
2034         /* Tx control */
2035         val = 0xc0;
2036         if (!(params->feature_config_flags &
2037                                 FEATURE_CONFIG_PFC_ENABLED) &&
2038             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2039                 val |= 0x800000;
2040         wb_data[0] = val;
2041         wb_data[1] = 0;
2042         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
2043
2044         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
2045                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
2046                 /* Enable PFC RX & TX & STATS and set 8 COS  */
2047                 wb_data[0] = 0x0;
2048                 wb_data[0] |= (1<<0);  /* RX */
2049                 wb_data[0] |= (1<<1);  /* TX */
2050                 wb_data[0] |= (1<<2);  /* Force initial Xon */
2051                 wb_data[0] |= (1<<3);  /* 8 cos */
2052                 wb_data[0] |= (1<<5);  /* STATS */
2053                 wb_data[1] = 0;
2054                 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
2055                             wb_data, 2);
2056                 /* Clear the force Xon */
2057                 wb_data[0] &= ~(1<<2);
2058         } else {
2059                 DP(NETIF_MSG_LINK, "PFC is disabled\n");
2060                 /* disable PFC RX & TX & STATS and set 8 COS */
2061                 wb_data[0] = 0x8;
2062                 wb_data[1] = 0;
2063         }
2064
2065         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2066
2067         /* Set Time (based unit is 512 bit time) between automatic
2068          * re-sending of PP packets amd enable automatic re-send of
2069          * Per-Priroity Packet as long as pp_gen is asserted and
2070          * pp_disable is low.
2071          */
2072         val = 0x8000;
2073         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2074                 val |= (1<<16); /* enable automatic re-send */
2075
2076         wb_data[0] = val;
2077         wb_data[1] = 0;
2078         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
2079                     wb_data, 2);
2080
2081         /* mac control */
2082         val = 0x3; /* Enable RX and TX */
2083         if (is_lb) {
2084                 val |= 0x4; /* Local loopback */
2085                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2086         }
2087         /* When PFC enabled, Pass pause frames towards the NIG. */
2088         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2089                 val |= ((1<<6)|(1<<5));
2090
2091         wb_data[0] = val;
2092         wb_data[1] = 0;
2093         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2094 }
2095
2096 /* PFC BRB internal port configuration params */
2097 struct bnx2x_pfc_brb_threshold_val {
2098         u32 pause_xoff;
2099         u32 pause_xon;
2100         u32 full_xoff;
2101         u32 full_xon;
2102 };
2103
2104 struct bnx2x_pfc_brb_e3b0_val {
2105         u32 per_class_guaranty_mode;
2106         u32 lb_guarantied_hyst;
2107         u32 full_lb_xoff_th;
2108         u32 full_lb_xon_threshold;
2109         u32 lb_guarantied;
2110         u32 mac_0_class_t_guarantied;
2111         u32 mac_0_class_t_guarantied_hyst;
2112         u32 mac_1_class_t_guarantied;
2113         u32 mac_1_class_t_guarantied_hyst;
2114 };
2115
2116 struct bnx2x_pfc_brb_th_val {
2117         struct bnx2x_pfc_brb_threshold_val pauseable_th;
2118         struct bnx2x_pfc_brb_threshold_val non_pauseable_th;
2119         struct bnx2x_pfc_brb_threshold_val default_class0;
2120         struct bnx2x_pfc_brb_threshold_val default_class1;
2121
2122 };
2123 static int bnx2x_pfc_brb_get_config_params(
2124                                 struct link_params *params,
2125                                 struct bnx2x_pfc_brb_th_val *config_val)
2126 {
2127         struct bnx2x *bp = params->bp;
2128         DP(NETIF_MSG_LINK, "Setting PFC BRB configuration\n");
2129
2130         config_val->default_class1.pause_xoff = 0;
2131         config_val->default_class1.pause_xon = 0;
2132         config_val->default_class1.full_xoff = 0;
2133         config_val->default_class1.full_xon = 0;
2134
2135         if (CHIP_IS_E2(bp)) {
2136                 /* Class0 defaults */
2137                 config_val->default_class0.pause_xoff =
2138                         DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR;
2139                 config_val->default_class0.pause_xon =
2140                         DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR;
2141                 config_val->default_class0.full_xoff =
2142                         DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR;
2143                 config_val->default_class0.full_xon =
2144                         DEFAULT0_E2_BRB_MAC_FULL_XON_THR;
2145                 /* Pause able*/
2146                 config_val->pauseable_th.pause_xoff =
2147                         PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2148                 config_val->pauseable_th.pause_xon =
2149                         PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE;
2150                 config_val->pauseable_th.full_xoff =
2151                         PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
2152                 config_val->pauseable_th.full_xon =
2153                         PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
2154                 /* non pause able*/
2155                 config_val->non_pauseable_th.pause_xoff =
2156                         PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2157                 config_val->non_pauseable_th.pause_xon =
2158                         PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2159                 config_val->non_pauseable_th.full_xoff =
2160                         PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2161                 config_val->non_pauseable_th.full_xon =
2162                         PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2163         } else if (CHIP_IS_E3A0(bp)) {
2164                 /* Class0 defaults */
2165                 config_val->default_class0.pause_xoff =
2166                         DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR;
2167                 config_val->default_class0.pause_xon =
2168                         DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR;
2169                 config_val->default_class0.full_xoff =
2170                         DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR;
2171                 config_val->default_class0.full_xon =
2172                         DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR;
2173                 /* Pause able */
2174                 config_val->pauseable_th.pause_xoff =
2175                         PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2176                 config_val->pauseable_th.pause_xon =
2177                         PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE;
2178                 config_val->pauseable_th.full_xoff =
2179                         PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
2180                 config_val->pauseable_th.full_xon =
2181                         PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
2182                 /* non pause able*/
2183                 config_val->non_pauseable_th.pause_xoff =
2184                         PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2185                 config_val->non_pauseable_th.pause_xon =
2186                         PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2187                 config_val->non_pauseable_th.full_xoff =
2188                         PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2189                 config_val->non_pauseable_th.full_xon =
2190                         PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2191         } else if (CHIP_IS_E3B0(bp)) {
2192                 /* Class0 defaults */
2193                 config_val->default_class0.pause_xoff =
2194                         DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR;
2195                 config_val->default_class0.pause_xon =
2196                     DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR;
2197                 config_val->default_class0.full_xoff =
2198                     DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR;
2199                 config_val->default_class0.full_xon =
2200                     DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR;
2201
2202                 if (params->phy[INT_PHY].flags &
2203                     FLAGS_4_PORT_MODE) {
2204                         config_val->pauseable_th.pause_xoff =
2205                                 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2206                         config_val->pauseable_th.pause_xon =
2207                                 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2208                         config_val->pauseable_th.full_xoff =
2209                                 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2210                         config_val->pauseable_th.full_xon =
2211                                 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
2212                         /* non pause able*/
2213                         config_val->non_pauseable_th.pause_xoff =
2214                         PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2215                         config_val->non_pauseable_th.pause_xon =
2216                         PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2217                         config_val->non_pauseable_th.full_xoff =
2218                         PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2219                         config_val->non_pauseable_th.full_xon =
2220                         PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2221                 } else {
2222                         config_val->pauseable_th.pause_xoff =
2223                                 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2224                         config_val->pauseable_th.pause_xon =
2225                                 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2226                         config_val->pauseable_th.full_xoff =
2227                                 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2228                         config_val->pauseable_th.full_xon =
2229                                 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
2230                         /* non pause able*/
2231                         config_val->non_pauseable_th.pause_xoff =
2232                                 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2233                         config_val->non_pauseable_th.pause_xon =
2234                                 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2235                         config_val->non_pauseable_th.full_xoff =
2236                                 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2237                         config_val->non_pauseable_th.full_xon =
2238                                 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2239                 }
2240         } else
2241             return -EINVAL;
2242
2243         return 0;
2244 }
2245
2246 static void bnx2x_pfc_brb_get_e3b0_config_params(
2247                 struct link_params *params,
2248                 struct bnx2x_pfc_brb_e3b0_val
2249                 *e3b0_val,
2250                 struct bnx2x_nig_brb_pfc_port_params *pfc_params,
2251                 const u8 pfc_enabled)
2252 {
2253         if (pfc_enabled && pfc_params) {
2254                 e3b0_val->per_class_guaranty_mode = 1;
2255                 e3b0_val->lb_guarantied_hyst = 80;
2256
2257                 if (params->phy[INT_PHY].flags &
2258                     FLAGS_4_PORT_MODE) {
2259                         e3b0_val->full_lb_xoff_th =
2260                                 PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR;
2261                         e3b0_val->full_lb_xon_threshold =
2262                                 PFC_E3B0_4P_BRB_FULL_LB_XON_THR;
2263                         e3b0_val->lb_guarantied =
2264                                 PFC_E3B0_4P_LB_GUART;
2265                         e3b0_val->mac_0_class_t_guarantied =
2266                                 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART;
2267                         e3b0_val->mac_0_class_t_guarantied_hyst =
2268                                 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST;
2269                         e3b0_val->mac_1_class_t_guarantied =
2270                                 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART;
2271                         e3b0_val->mac_1_class_t_guarantied_hyst =
2272                                 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST;
2273                 } else {
2274                         e3b0_val->full_lb_xoff_th =
2275                                 PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR;
2276                         e3b0_val->full_lb_xon_threshold =
2277                                 PFC_E3B0_2P_BRB_FULL_LB_XON_THR;
2278                         e3b0_val->mac_0_class_t_guarantied_hyst =
2279                                 PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST;
2280                         e3b0_val->mac_1_class_t_guarantied =
2281                                 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART;
2282                         e3b0_val->mac_1_class_t_guarantied_hyst =
2283                                 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST;
2284
2285                         if (pfc_params->cos0_pauseable !=
2286                                 pfc_params->cos1_pauseable) {
2287                                 /* nonpauseable= Lossy + pauseable = Lossless*/
2288                                 e3b0_val->lb_guarantied =
2289                                         PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
2290                                 e3b0_val->mac_0_class_t_guarantied =
2291                                PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART;
2292                         } else if (pfc_params->cos0_pauseable) {
2293                                 /* Lossless +Lossless*/
2294                                 e3b0_val->lb_guarantied =
2295                                         PFC_E3B0_2P_PAUSE_LB_GUART;
2296                                 e3b0_val->mac_0_class_t_guarantied =
2297                                    PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART;
2298                         } else {
2299                                 /* Lossy +Lossy*/
2300                                 e3b0_val->lb_guarantied =
2301                                         PFC_E3B0_2P_NON_PAUSE_LB_GUART;
2302                                 e3b0_val->mac_0_class_t_guarantied =
2303                                PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART;
2304                         }
2305                 }
2306         } else {
2307                 e3b0_val->per_class_guaranty_mode = 0;
2308                 e3b0_val->lb_guarantied_hyst = 0;
2309                 e3b0_val->full_lb_xoff_th =
2310                         DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR;
2311                 e3b0_val->full_lb_xon_threshold =
2312                         DEFAULT_E3B0_BRB_FULL_LB_XON_THR;
2313                 e3b0_val->lb_guarantied =
2314                         DEFAULT_E3B0_LB_GUART;
2315                 e3b0_val->mac_0_class_t_guarantied =
2316                         DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART;
2317                 e3b0_val->mac_0_class_t_guarantied_hyst =
2318                         DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST;
2319                 e3b0_val->mac_1_class_t_guarantied =
2320                         DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART;
2321                 e3b0_val->mac_1_class_t_guarantied_hyst =
2322                         DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST;
2323         }
2324 }
2325 static int bnx2x_update_pfc_brb(struct link_params *params,
2326                                 struct link_vars *vars,
2327                                 struct bnx2x_nig_brb_pfc_port_params
2328                                 *pfc_params)
2329 {
2330         struct bnx2x *bp = params->bp;
2331         struct bnx2x_pfc_brb_th_val config_val = { {0} };
2332         struct bnx2x_pfc_brb_threshold_val *reg_th_config =
2333                 &config_val.pauseable_th;
2334         struct bnx2x_pfc_brb_e3b0_val e3b0_val = {0};
2335         const int set_pfc = params->feature_config_flags &
2336                 FEATURE_CONFIG_PFC_ENABLED;
2337         const u8 pfc_enabled = (set_pfc && pfc_params);
2338         int bnx2x_status = 0;
2339         u8 port = params->port;
2340
2341         /* default - pause configuration */
2342         reg_th_config = &config_val.pauseable_th;
2343         bnx2x_status = bnx2x_pfc_brb_get_config_params(params, &config_val);
2344         if (bnx2x_status)
2345                 return bnx2x_status;
2346
2347         if (pfc_enabled) {
2348                 /* First COS */
2349                 if (pfc_params->cos0_pauseable)
2350                         reg_th_config = &config_val.pauseable_th;
2351                 else
2352                         reg_th_config = &config_val.non_pauseable_th;
2353         } else
2354                 reg_th_config = &config_val.default_class0;
2355         /* The number of free blocks below which the pause signal to class 0
2356          * of MAC #n is asserted. n=0,1
2357          */
2358         REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 :
2359                BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
2360                reg_th_config->pause_xoff);
2361         /* The number of free blocks above which the pause signal to class 0
2362          * of MAC #n is de-asserted. n=0,1
2363          */
2364         REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 :
2365                BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon);
2366         /* The number of free blocks below which the full signal to class 0
2367          * of MAC #n is asserted. n=0,1
2368          */
2369         REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 :
2370                BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff);
2371         /* The number of free blocks above which the full signal to class 0
2372          * of MAC #n is de-asserted. n=0,1
2373          */
2374         REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 :
2375                BRB1_REG_FULL_0_XON_THRESHOLD_0 , reg_th_config->full_xon);
2376
2377         if (pfc_enabled) {
2378                 /* Second COS */
2379                 if (pfc_params->cos1_pauseable)
2380                         reg_th_config = &config_val.pauseable_th;
2381                 else
2382                         reg_th_config = &config_val.non_pauseable_th;
2383         } else
2384                 reg_th_config = &config_val.default_class1;
2385         /* The number of free blocks below which the pause signal to
2386          * class 1 of MAC #n is asserted. n=0,1
2387          */
2388         REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 :
2389                BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
2390                reg_th_config->pause_xoff);
2391
2392         /* The number of free blocks above which the pause signal to
2393          * class 1 of MAC #n is de-asserted. n=0,1
2394          */
2395         REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 :
2396                BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
2397                reg_th_config->pause_xon);
2398         /* The number of free blocks below which the full signal to
2399          * class 1 of MAC #n is asserted. n=0,1
2400          */
2401         REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 :
2402                BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
2403                reg_th_config->full_xoff);
2404         /* The number of free blocks above which the full signal to
2405          * class 1 of MAC #n is de-asserted. n=0,1
2406          */
2407         REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 :
2408                BRB1_REG_FULL_1_XON_THRESHOLD_0,
2409                reg_th_config->full_xon);
2410
2411         if (CHIP_IS_E3B0(bp)) {
2412                 bnx2x_pfc_brb_get_e3b0_config_params(
2413                         params,
2414                         &e3b0_val,
2415                         pfc_params,
2416                         pfc_enabled);
2417
2418                 REG_WR(bp, BRB1_REG_PER_CLASS_GUARANTY_MODE,
2419                            e3b0_val.per_class_guaranty_mode);
2420
2421                 /* The hysteresis on the guarantied buffer space for the Lb
2422                  * port before signaling XON.
2423                  */
2424                 REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST,
2425                            e3b0_val.lb_guarantied_hyst);
2426
2427                 /* The number of free blocks below which the full signal to the
2428                  * LB port is asserted.
2429                  */
2430                 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD,
2431                        e3b0_val.full_lb_xoff_th);
2432                 /* The number of free blocks above which the full signal to the
2433                  * LB port is de-asserted.
2434                  */
2435                 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD,
2436                        e3b0_val.full_lb_xon_threshold);
2437                 /* The number of blocks guarantied for the MAC #n port. n=0,1
2438                  */
2439
2440                 /* The number of blocks guarantied for the LB port. */
2441                 REG_WR(bp, BRB1_REG_LB_GUARANTIED,
2442                        e3b0_val.lb_guarantied);
2443
2444                 /* The number of blocks guarantied for the MAC #n port. */
2445                 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0,
2446                        2 * e3b0_val.mac_0_class_t_guarantied);
2447                 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1,
2448                        2 * e3b0_val.mac_1_class_t_guarantied);
2449                 /* The number of blocks guarantied for class #t in MAC0. t=0,1
2450                  */
2451                 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED,
2452                        e3b0_val.mac_0_class_t_guarantied);
2453                 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED,
2454                        e3b0_val.mac_0_class_t_guarantied);
2455                 /* The hysteresis on the guarantied buffer space for class in
2456                  * MAC0.  t=0,1
2457                  */
2458                 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST,
2459                        e3b0_val.mac_0_class_t_guarantied_hyst);
2460                 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST,
2461                        e3b0_val.mac_0_class_t_guarantied_hyst);
2462
2463                 /* The number of blocks guarantied for class #t in MAC1.t=0,1
2464                  */
2465                 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED,
2466                        e3b0_val.mac_1_class_t_guarantied);
2467                 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED,
2468                        e3b0_val.mac_1_class_t_guarantied);
2469                 /* The hysteresis on the guarantied buffer space for class #t
2470                  * in MAC1.  t=0,1
2471                  */
2472                 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST,
2473                        e3b0_val.mac_1_class_t_guarantied_hyst);
2474                 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST,
2475                        e3b0_val.mac_1_class_t_guarantied_hyst);
2476         }
2477
2478         return bnx2x_status;
2479 }
2480
2481 /******************************************************************************
2482 * Description:
2483 *  This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2484 *  not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2485 ******************************************************************************/
2486 int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2487                                               u8 cos_entry,
2488                                               u32 priority_mask, u8 port)
2489 {
2490         u32 nig_reg_rx_priority_mask_add = 0;
2491
2492         switch (cos_entry) {
2493         case 0:
2494              nig_reg_rx_priority_mask_add = (port) ?
2495                  NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2496                  NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2497              break;
2498         case 1:
2499             nig_reg_rx_priority_mask_add = (port) ?
2500                 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2501                 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2502             break;
2503         case 2:
2504             nig_reg_rx_priority_mask_add = (port) ?
2505                 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2506                 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2507             break;
2508         case 3:
2509             if (port)
2510                 return -EINVAL;
2511             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2512             break;
2513         case 4:
2514             if (port)
2515                 return -EINVAL;
2516             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2517             break;
2518         case 5:
2519             if (port)
2520                 return -EINVAL;
2521             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2522             break;
2523         }
2524
2525         REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2526
2527         return 0;
2528 }
2529 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2530 {
2531         struct bnx2x *bp = params->bp;
2532
2533         REG_WR(bp, params->shmem_base +
2534                offsetof(struct shmem_region,
2535                         port_mb[params->port].link_status), link_status);
2536 }
2537
2538 static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status)
2539 {
2540         struct bnx2x *bp = params->bp;
2541
2542         if (bnx2x_eee_has_cap(params))
2543                 REG_WR(bp, params->shmem2_base +
2544                        offsetof(struct shmem2_region,
2545                                 eee_status[params->port]), eee_status);
2546 }
2547
2548 static void bnx2x_update_pfc_nig(struct link_params *params,
2549                 struct link_vars *vars,
2550                 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2551 {
2552         u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2553         u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
2554         u32 pkt_priority_to_cos = 0;
2555         struct bnx2x *bp = params->bp;
2556         u8 port = params->port;
2557
2558         int set_pfc = params->feature_config_flags &
2559                 FEATURE_CONFIG_PFC_ENABLED;
2560         DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2561
2562         /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2563          * MAC control frames (that are not pause packets)
2564          * will be forwarded to the XCM.
2565          */
2566         xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :
2567                           NIG_REG_LLH0_XCM_MASK);
2568         /* NIG params will override non PFC params, since it's possible to
2569          * do transition from PFC to SAFC
2570          */
2571         if (set_pfc) {
2572                 pause_enable = 0;
2573                 llfc_out_en = 0;
2574                 llfc_enable = 0;
2575                 if (CHIP_IS_E3(bp))
2576                         ppp_enable = 0;
2577                 else
2578                 ppp_enable = 1;
2579                 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2580                                      NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2581                 xcm_out_en = 0;
2582                 hwpfc_enable = 1;
2583         } else  {
2584                 if (nig_params) {
2585                         llfc_out_en = nig_params->llfc_out_en;
2586                         llfc_enable = nig_params->llfc_enable;
2587                         pause_enable = nig_params->pause_enable;
2588                 } else  /* Default non PFC mode - PAUSE */
2589                         pause_enable = 1;
2590
2591                 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2592                         NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2593                 xcm_out_en = 1;
2594         }
2595
2596         if (CHIP_IS_E3(bp))
2597                 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2598                        NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2599         REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2600                NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2601         REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2602                NIG_REG_LLFC_ENABLE_0, llfc_enable);
2603         REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2604                NIG_REG_PAUSE_ENABLE_0, pause_enable);
2605
2606         REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2607                NIG_REG_PPP_ENABLE_0, ppp_enable);
2608
2609         REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2610                NIG_REG_LLH0_XCM_MASK, xcm_mask);
2611
2612         REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2613                NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2614
2615         /* output enable for RX_XCM # IF */
2616         REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN :
2617                NIG_REG_XCM0_OUT_EN, xcm_out_en);
2618
2619         /* HW PFC TX enable */
2620         REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE :
2621                NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
2622
2623         if (nig_params) {
2624                 u8 i = 0;
2625                 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2626
2627                 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2628                         bnx2x_pfc_nig_rx_priority_mask(bp, i,
2629                 nig_params->rx_cos_priority_mask[i], port);
2630
2631                 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2632                        NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2633                        nig_params->llfc_high_priority_classes);
2634
2635                 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2636                        NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2637                        nig_params->llfc_low_priority_classes);
2638         }
2639         REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2640                NIG_REG_P0_PKT_PRIORITY_TO_COS,
2641                pkt_priority_to_cos);
2642 }
2643
2644 int bnx2x_update_pfc(struct link_params *params,
2645                       struct link_vars *vars,
2646                       struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2647 {
2648         /* The PFC and pause are orthogonal to one another, meaning when
2649          * PFC is enabled, the pause are disabled, and when PFC is
2650          * disabled, pause are set according to the pause result.
2651          */
2652         u32 val;
2653         struct bnx2x *bp = params->bp;
2654         int bnx2x_status = 0;
2655         u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2656
2657         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2658                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2659         else
2660                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2661
2662         bnx2x_update_mng(params, vars->link_status);
2663
2664         /* update NIG params */
2665         bnx2x_update_pfc_nig(params, vars, pfc_params);
2666
2667         /* update BRB params */
2668         bnx2x_status = bnx2x_update_pfc_brb(params, vars, pfc_params);
2669         if (bnx2x_status)
2670                 return bnx2x_status;
2671
2672         if (!vars->link_up)
2673                 return bnx2x_status;
2674
2675         DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2676         if (CHIP_IS_E3(bp))
2677                 bnx2x_update_pfc_xmac(params, vars, 0);
2678         else {
2679                 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2680                 if ((val &
2681                      (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2682                     == 0) {
2683                         DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2684                         bnx2x_emac_enable(params, vars, 0);
2685                         return bnx2x_status;
2686                 }
2687                 if (CHIP_IS_E2(bp))
2688                         bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2689                 else
2690                         bnx2x_update_pfc_bmac1(params, vars);
2691
2692                 val = 0;
2693                 if ((params->feature_config_flags &
2694                      FEATURE_CONFIG_PFC_ENABLED) ||
2695                     (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2696                         val = 1;
2697                 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2698         }
2699         return bnx2x_status;
2700 }
2701
2702
2703 static int bnx2x_bmac1_enable(struct link_params *params,
2704                               struct link_vars *vars,
2705                               u8 is_lb)
2706 {
2707         struct bnx2x *bp = params->bp;
2708         u8 port = params->port;
2709         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2710                                NIG_REG_INGRESS_BMAC0_MEM;
2711         u32 wb_data[2];
2712         u32 val;
2713
2714         DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2715
2716         /* XGXS control */
2717         wb_data[0] = 0x3c;
2718         wb_data[1] = 0;
2719         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2720                     wb_data, 2);
2721
2722         /* tx MAC SA */
2723         wb_data[0] = ((params->mac_addr[2] << 24) |
2724                        (params->mac_addr[3] << 16) |
2725                        (params->mac_addr[4] << 8) |
2726                         params->mac_addr[5]);
2727         wb_data[1] = ((params->mac_addr[0] << 8) |
2728                         params->mac_addr[1]);
2729         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2730
2731         /* mac control */
2732         val = 0x3;
2733         if (is_lb) {
2734                 val |= 0x4;
2735                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2736         }
2737         wb_data[0] = val;
2738         wb_data[1] = 0;
2739         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2740
2741         /* set rx mtu */
2742         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2743         wb_data[1] = 0;
2744         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2745
2746         bnx2x_update_pfc_bmac1(params, vars);
2747
2748         /* set tx mtu */
2749         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2750         wb_data[1] = 0;
2751         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2752
2753         /* set cnt max size */
2754         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2755         wb_data[1] = 0;
2756         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2757
2758         /* configure safc */
2759         wb_data[0] = 0x1000200;
2760         wb_data[1] = 0;
2761         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2762                     wb_data, 2);
2763
2764         return 0;
2765 }
2766
2767 static int bnx2x_bmac2_enable(struct link_params *params,
2768                               struct link_vars *vars,
2769                               u8 is_lb)
2770 {
2771         struct bnx2x *bp = params->bp;
2772         u8 port = params->port;
2773         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2774                                NIG_REG_INGRESS_BMAC0_MEM;
2775         u32 wb_data[2];
2776
2777         DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2778
2779         wb_data[0] = 0;
2780         wb_data[1] = 0;
2781         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2782         udelay(30);
2783
2784         /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2785         wb_data[0] = 0x3c;
2786         wb_data[1] = 0;
2787         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2788                     wb_data, 2);
2789
2790         udelay(30);
2791
2792         /* tx MAC SA */
2793         wb_data[0] = ((params->mac_addr[2] << 24) |
2794                        (params->mac_addr[3] << 16) |
2795                        (params->mac_addr[4] << 8) |
2796                         params->mac_addr[5]);
2797         wb_data[1] = ((params->mac_addr[0] << 8) |
2798                         params->mac_addr[1]);
2799         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2800                     wb_data, 2);
2801
2802         udelay(30);
2803
2804         /* Configure SAFC */
2805         wb_data[0] = 0x1000200;
2806         wb_data[1] = 0;
2807         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2808                     wb_data, 2);
2809         udelay(30);
2810
2811         /* set rx mtu */
2812         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2813         wb_data[1] = 0;
2814         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2815         udelay(30);
2816
2817         /* set tx mtu */
2818         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2819         wb_data[1] = 0;
2820         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2821         udelay(30);
2822         /* set cnt max size */
2823         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2824         wb_data[1] = 0;
2825         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2826         udelay(30);
2827         bnx2x_update_pfc_bmac2(params, vars, is_lb);
2828
2829         return 0;
2830 }
2831
2832 static int bnx2x_bmac_enable(struct link_params *params,
2833                              struct link_vars *vars,
2834                              u8 is_lb)
2835 {
2836         int rc = 0;
2837         u8 port = params->port;
2838         struct bnx2x *bp = params->bp;
2839         u32 val;
2840         /* reset and unreset the BigMac */
2841         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2842                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2843         msleep(1);
2844
2845         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2846                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2847
2848         /* enable access for bmac registers */
2849         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2850
2851         /* Enable BMAC according to BMAC type*/
2852         if (CHIP_IS_E2(bp))
2853                 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2854         else
2855                 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2856         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2857         REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2858         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2859         val = 0;
2860         if ((params->feature_config_flags &
2861               FEATURE_CONFIG_PFC_ENABLED) ||
2862             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2863                 val = 1;
2864         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2865         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2866         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2867         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2868         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2869         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2870
2871         vars->mac_type = MAC_TYPE_BMAC;
2872         return rc;
2873 }
2874
2875 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
2876 {
2877         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2878                         NIG_REG_INGRESS_BMAC0_MEM;
2879         u32 wb_data[2];
2880         u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2881
2882         /* Only if the bmac is out of reset */
2883         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2884                         (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2885             nig_bmac_enable) {
2886
2887                 if (CHIP_IS_E2(bp)) {
2888                         /* Clear Rx Enable bit in BMAC_CONTROL register */
2889                         REG_RD_DMAE(bp, bmac_addr +
2890                                     BIGMAC2_REGISTER_BMAC_CONTROL,
2891                                     wb_data, 2);
2892                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2893                         REG_WR_DMAE(bp, bmac_addr +
2894                                     BIGMAC2_REGISTER_BMAC_CONTROL,
2895                                     wb_data, 2);
2896                 } else {
2897                         /* Clear Rx Enable bit in BMAC_CONTROL register */
2898                         REG_RD_DMAE(bp, bmac_addr +
2899                                         BIGMAC_REGISTER_BMAC_CONTROL,
2900                                         wb_data, 2);
2901                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2902                         REG_WR_DMAE(bp, bmac_addr +
2903                                         BIGMAC_REGISTER_BMAC_CONTROL,
2904                                         wb_data, 2);
2905                 }
2906                 msleep(1);
2907         }
2908 }
2909
2910 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2911                             u32 line_speed)
2912 {
2913         struct bnx2x *bp = params->bp;
2914         u8 port = params->port;
2915         u32 init_crd, crd;
2916         u32 count = 1000;
2917
2918         /* disable port */
2919         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2920
2921         /* wait for init credit */
2922         init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2923         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2924         DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
2925
2926         while ((init_crd != crd) && count) {
2927                 msleep(5);
2928
2929                 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2930                 count--;
2931         }
2932         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2933         if (init_crd != crd) {
2934                 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2935                           init_crd, crd);
2936                 return -EINVAL;
2937         }
2938
2939         if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2940             line_speed == SPEED_10 ||
2941             line_speed == SPEED_100 ||
2942             line_speed == SPEED_1000 ||
2943             line_speed == SPEED_2500) {
2944                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2945                 /* update threshold */
2946                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2947                 /* update init credit */
2948                 init_crd = 778;         /* (800-18-4) */
2949
2950         } else {
2951                 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2952                               ETH_OVREHEAD)/16;
2953                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2954                 /* update threshold */
2955                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2956                 /* update init credit */
2957                 switch (line_speed) {
2958                 case SPEED_10000:
2959                         init_crd = thresh + 553 - 22;
2960                         break;
2961                 default:
2962                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2963                                   line_speed);
2964                         return -EINVAL;
2965                 }
2966         }
2967         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2968         DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2969                  line_speed, init_crd);
2970
2971         /* probe the credit changes */
2972         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2973         msleep(5);
2974         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2975
2976         /* enable port */
2977         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2978         return 0;
2979 }
2980
2981 /**
2982  * bnx2x_get_emac_base - retrive emac base address
2983  *
2984  * @bp:                 driver handle
2985  * @mdc_mdio_access:    access type
2986  * @port:               port id
2987  *
2988  * This function selects the MDC/MDIO access (through emac0 or
2989  * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2990  * phy has a default access mode, which could also be overridden
2991  * by nvram configuration. This parameter, whether this is the
2992  * default phy configuration, or the nvram overrun
2993  * configuration, is passed here as mdc_mdio_access and selects
2994  * the emac_base for the CL45 read/writes operations
2995  */
2996 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2997                                u32 mdc_mdio_access, u8 port)
2998 {
2999         u32 emac_base = 0;
3000         switch (mdc_mdio_access) {
3001         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
3002                 break;
3003         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
3004                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
3005                         emac_base = GRCBASE_EMAC1;
3006                 else
3007                         emac_base = GRCBASE_EMAC0;
3008                 break;
3009         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
3010                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
3011                         emac_base = GRCBASE_EMAC0;
3012                 else
3013                         emac_base = GRCBASE_EMAC1;
3014                 break;
3015         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
3016                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3017                 break;
3018         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
3019                 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
3020                 break;
3021         default:
3022                 break;
3023         }
3024         return emac_base;
3025
3026 }
3027
3028 /******************************************************************/
3029 /*                      CL22 access functions                     */
3030 /******************************************************************/
3031 static int bnx2x_cl22_write(struct bnx2x *bp,
3032                                        struct bnx2x_phy *phy,
3033                                        u16 reg, u16 val)
3034 {
3035         u32 tmp, mode;
3036         u8 i;
3037         int rc = 0;
3038         /* Switch to CL22 */
3039         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
3040         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
3041                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
3042
3043         /* address */
3044         tmp = ((phy->addr << 21) | (reg << 16) | val |
3045                EMAC_MDIO_COMM_COMMAND_WRITE_22 |
3046                EMAC_MDIO_COMM_START_BUSY);
3047         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3048
3049         for (i = 0; i < 50; i++) {
3050                 udelay(10);
3051
3052                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3053                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3054                         udelay(5);
3055                         break;
3056                 }
3057         }
3058         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3059                 DP(NETIF_MSG_LINK, "write phy register failed\n");
3060                 rc = -EFAULT;
3061         }
3062         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
3063         return rc;
3064 }
3065
3066 static int bnx2x_cl22_read(struct bnx2x *bp,
3067                                       struct bnx2x_phy *phy,
3068                                       u16 reg, u16 *ret_val)
3069 {
3070         u32 val, mode;
3071         u16 i;
3072         int rc = 0;
3073
3074         /* Switch to CL22 */
3075         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
3076         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
3077                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
3078
3079         /* address */
3080         val = ((phy->addr << 21) | (reg << 16) |
3081                EMAC_MDIO_COMM_COMMAND_READ_22 |
3082                EMAC_MDIO_COMM_START_BUSY);
3083         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3084
3085         for (i = 0; i < 50; i++) {
3086                 udelay(10);
3087
3088                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3089                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3090                         *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
3091                         udelay(5);
3092                         break;
3093                 }
3094         }
3095         if (val & EMAC_MDIO_COMM_START_BUSY) {
3096                 DP(NETIF_MSG_LINK, "read phy register failed\n");
3097
3098                 *ret_val = 0;
3099                 rc = -EFAULT;
3100         }
3101         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
3102         return rc;
3103 }
3104
3105 /******************************************************************/
3106 /*                      CL45 access functions                     */
3107 /******************************************************************/
3108 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
3109                            u8 devad, u16 reg, u16 *ret_val)
3110 {
3111         u32 val;
3112         u16 i;
3113         int rc = 0;
3114         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3115                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3116                               EMAC_MDIO_STATUS_10MB);
3117         /* address */
3118         val = ((phy->addr << 21) | (devad << 16) | reg |
3119                EMAC_MDIO_COMM_COMMAND_ADDRESS |
3120                EMAC_MDIO_COMM_START_BUSY);
3121         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3122
3123         for (i = 0; i < 50; i++) {
3124                 udelay(10);
3125
3126                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3127                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3128                         udelay(5);
3129                         break;
3130                 }
3131         }
3132         if (val & EMAC_MDIO_COMM_START_BUSY) {
3133                 DP(NETIF_MSG_LINK, "read phy register failed\n");
3134                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
3135                 *ret_val = 0;
3136                 rc = -EFAULT;
3137         } else {
3138                 /* data */
3139                 val = ((phy->addr << 21) | (devad << 16) |
3140                        EMAC_MDIO_COMM_COMMAND_READ_45 |
3141                        EMAC_MDIO_COMM_START_BUSY);
3142                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3143
3144                 for (i = 0; i < 50; i++) {
3145                         udelay(10);
3146
3147                         val = REG_RD(bp, phy->mdio_ctrl +
3148                                      EMAC_REG_EMAC_MDIO_COMM);
3149                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3150                                 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
3151                                 break;
3152                         }
3153                 }
3154                 if (val & EMAC_MDIO_COMM_START_BUSY) {
3155                         DP(NETIF_MSG_LINK, "read phy register failed\n");
3156                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
3157                         *ret_val = 0;
3158                         rc = -EFAULT;
3159                 }
3160         }
3161         /* Work around for E3 A0 */
3162         if (phy->flags & FLAGS_MDC_MDIO_WA) {
3163                 phy->flags ^= FLAGS_DUMMY_READ;
3164                 if (phy->flags & FLAGS_DUMMY_READ) {
3165                         u16 temp_val;
3166                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3167                 }
3168         }
3169
3170         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3171                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3172                                EMAC_MDIO_STATUS_10MB);
3173         return rc;
3174 }
3175
3176 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3177                             u8 devad, u16 reg, u16 val)
3178 {
3179         u32 tmp;
3180         u8 i;
3181         int rc = 0;
3182         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3183                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3184                               EMAC_MDIO_STATUS_10MB);
3185
3186         /* address */
3187         tmp = ((phy->addr << 21) | (devad << 16) | reg |
3188                EMAC_MDIO_COMM_COMMAND_ADDRESS |
3189                EMAC_MDIO_COMM_START_BUSY);
3190         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3191
3192         for (i = 0; i < 50; i++) {
3193                 udelay(10);
3194
3195                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3196                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3197                         udelay(5);
3198                         break;
3199                 }
3200         }
3201         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3202                 DP(NETIF_MSG_LINK, "write phy register failed\n");
3203                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
3204                 rc = -EFAULT;
3205         } else {
3206                 /* data */
3207                 tmp = ((phy->addr << 21) | (devad << 16) | val |
3208                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
3209                        EMAC_MDIO_COMM_START_BUSY);
3210                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3211
3212                 for (i = 0; i < 50; i++) {
3213                         udelay(10);
3214
3215                         tmp = REG_RD(bp, phy->mdio_ctrl +
3216                                      EMAC_REG_EMAC_MDIO_COMM);
3217                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3218                                 udelay(5);
3219                                 break;
3220                         }
3221                 }
3222                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3223                         DP(NETIF_MSG_LINK, "write phy register failed\n");
3224                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
3225                         rc = -EFAULT;
3226                 }
3227         }
3228         /* Work around for E3 A0 */
3229         if (phy->flags & FLAGS_MDC_MDIO_WA) {
3230                 phy->flags ^= FLAGS_DUMMY_READ;
3231                 if (phy->flags & FLAGS_DUMMY_READ) {
3232                         u16 temp_val;
3233                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3234                 }
3235         }
3236         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3237                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3238                                EMAC_MDIO_STATUS_10MB);
3239         return rc;
3240 }
3241 /******************************************************************/
3242 /*                      BSC access functions from E3              */
3243 /******************************************************************/
3244 static void bnx2x_bsc_module_sel(struct link_params *params)
3245 {
3246         int idx;
3247         u32 board_cfg, sfp_ctrl;
3248         u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3249         struct bnx2x *bp = params->bp;
3250         u8 port = params->port;
3251         /* Read I2C output PINs */
3252         board_cfg = REG_RD(bp, params->shmem_base +
3253                            offsetof(struct shmem_region,
3254                                     dev_info.shared_hw_config.board));
3255         i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3256         i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3257                         SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3258
3259         /* Read I2C output value */
3260         sfp_ctrl = REG_RD(bp, params->shmem_base +
3261                           offsetof(struct shmem_region,
3262                                  dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3263         i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3264         i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3265         DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3266         for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3267                 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3268 }
3269
3270 static int bnx2x_bsc_read(struct link_params *params,
3271                           struct bnx2x_phy *phy,
3272                           u8 sl_devid,
3273                           u16 sl_addr,
3274                           u8 lc_addr,
3275                           u8 xfer_cnt,
3276                           u32 *data_array)
3277 {
3278         u32 val, i;
3279         int rc = 0;
3280         struct bnx2x *bp = params->bp;
3281
3282         if ((sl_devid != 0xa0) && (sl_devid != 0xa2)) {
3283                 DP(NETIF_MSG_LINK, "invalid sl_devid 0x%x\n", sl_devid);
3284                 return -EINVAL;
3285         }
3286
3287         if (xfer_cnt > 16) {
3288                 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3289                                         xfer_cnt);
3290                 return -EINVAL;
3291         }
3292         bnx2x_bsc_module_sel(params);
3293
3294         xfer_cnt = 16 - lc_addr;
3295
3296         /* enable the engine */
3297         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3298         val |= MCPR_IMC_COMMAND_ENABLE;
3299         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3300
3301         /* program slave device ID */
3302         val = (sl_devid << 16) | sl_addr;
3303         REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3304
3305         /* start xfer with 0 byte to update the address pointer ???*/
3306         val = (MCPR_IMC_COMMAND_ENABLE) |
3307               (MCPR_IMC_COMMAND_WRITE_OP <<
3308                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3309                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3310         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3311
3312         /* poll for completion */
3313         i = 0;
3314         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3315         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3316                 udelay(10);
3317                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3318                 if (i++ > 1000) {
3319                         DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3320                                                                 i);
3321                         rc = -EFAULT;
3322                         break;
3323                 }
3324         }
3325         if (rc == -EFAULT)
3326                 return rc;
3327
3328         /* start xfer with read op */
3329         val = (MCPR_IMC_COMMAND_ENABLE) |
3330                 (MCPR_IMC_COMMAND_READ_OP <<
3331                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3332                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3333                   (xfer_cnt);
3334         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3335
3336         /* poll for completion */
3337         i = 0;
3338         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3339         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3340                 udelay(10);
3341                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3342                 if (i++ > 1000) {
3343                         DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3344                         rc = -EFAULT;
3345                         break;
3346                 }
3347         }
3348         if (rc == -EFAULT)
3349                 return rc;
3350
3351         for (i = (lc_addr >> 2); i < 4; i++) {
3352                 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3353 #ifdef __BIG_ENDIAN
3354                 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3355                                 ((data_array[i] & 0x0000ff00) << 8) |
3356                                 ((data_array[i] & 0x00ff0000) >> 8) |
3357                                 ((data_array[i] & 0xff000000) >> 24);
3358 #endif
3359         }
3360         return rc;
3361 }
3362
3363 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3364                                      u8 devad, u16 reg, u16 or_val)
3365 {
3366         u16 val;
3367         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3368         bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3369 }
3370
3371 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3372                    u8 devad, u16 reg, u16 *ret_val)
3373 {
3374         u8 phy_index;
3375         /* Probe for the phy according to the given phy_addr, and execute
3376          * the read request on it
3377          */
3378         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3379                 if (params->phy[phy_index].addr == phy_addr) {
3380                         return bnx2x_cl45_read(params->bp,
3381                                                &params->phy[phy_index], devad,
3382                                                reg, ret_val);
3383                 }
3384         }
3385         return -EINVAL;
3386 }
3387
3388 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3389                     u8 devad, u16 reg, u16 val)
3390 {
3391         u8 phy_index;
3392         /* Probe for the phy according to the given phy_addr, and execute
3393          * the write request on it
3394          */
3395         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3396                 if (params->phy[phy_index].addr == phy_addr) {
3397                         return bnx2x_cl45_write(params->bp,
3398                                                 &params->phy[phy_index], devad,
3399                                                 reg, val);
3400                 }
3401         }
3402         return -EINVAL;
3403 }
3404 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3405                                   struct link_params *params)
3406 {
3407         u8 lane = 0;
3408         struct bnx2x *bp = params->bp;
3409         u32 path_swap, path_swap_ovr;
3410         u8 path, port;
3411
3412         path = BP_PATH(bp);
3413         port = params->port;
3414
3415         if (bnx2x_is_4_port_mode(bp)) {
3416                 u32 port_swap, port_swap_ovr;
3417
3418                 /* Figure out path swap value */
3419                 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3420                 if (path_swap_ovr & 0x1)
3421                         path_swap = (path_swap_ovr & 0x2);
3422                 else
3423                         path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3424
3425                 if (path_swap)
3426                         path = path ^ 1;
3427
3428                 /* Figure out port swap value */
3429                 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3430                 if (port_swap_ovr & 0x1)
3431                         port_swap = (port_swap_ovr & 0x2);
3432                 else
3433                         port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3434
3435                 if (port_swap)
3436                         port = port ^ 1;
3437
3438                 lane = (port<<1) + path;
3439         } else { /* two port mode - no port swap */
3440
3441                 /* Figure out path swap value */
3442                 path_swap_ovr =
3443                         REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3444                 if (path_swap_ovr & 0x1) {
3445                         path_swap = (path_swap_ovr & 0x2);
3446                 } else {
3447                         path_swap =
3448                                 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3449                 }
3450                 if (path_swap)
3451                         path = path ^ 1;
3452
3453                 lane = path << 1 ;
3454         }
3455         return lane;
3456 }
3457
3458 static void bnx2x_set_aer_mmd(struct link_params *params,
3459                               struct bnx2x_phy *phy)
3460 {
3461         u32 ser_lane;
3462         u16 offset, aer_val;
3463         struct bnx2x *bp = params->bp;
3464         ser_lane = ((params->lane_config &
3465                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3466                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3467
3468         offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3469                 (phy->addr + ser_lane) : 0;
3470
3471         if (USES_WARPCORE(bp)) {
3472                 aer_val = bnx2x_get_warpcore_lane(phy, params);
3473                 /* In Dual-lane mode, two lanes are joined together,
3474                  * so in order to configure them, the AER broadcast method is
3475                  * used here.
3476                  * 0x200 is the broadcast address for lanes 0,1
3477                  * 0x201 is the broadcast address for lanes 2,3
3478                  */
3479                 if (phy->flags & FLAGS_WC_DUAL_MODE)
3480                         aer_val = (aer_val >> 1) | 0x200;
3481         } else if (CHIP_IS_E2(bp))
3482                 aer_val = 0x3800 + offset - 1;
3483         else
3484                 aer_val = 0x3800 + offset;
3485
3486         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3487                           MDIO_AER_BLOCK_AER_REG, aer_val);
3488
3489 }
3490
3491 /******************************************************************/
3492 /*                      Internal phy section                      */
3493 /******************************************************************/
3494
3495 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3496 {
3497         u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3498
3499         /* Set Clause 22 */
3500         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3501         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3502         udelay(500);
3503         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3504         udelay(500);
3505          /* Set Clause 45 */
3506         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3507 }
3508
3509 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3510 {
3511         u32 val;
3512
3513         DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3514
3515         val = SERDES_RESET_BITS << (port*16);
3516
3517         /* reset and unreset the SerDes/XGXS */
3518         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3519         udelay(500);
3520         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3521
3522         bnx2x_set_serdes_access(bp, port);
3523
3524         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3525                DEFAULT_PHY_DEV_ADDR);
3526 }
3527
3528 static void bnx2x_xgxs_deassert(struct link_params *params)
3529 {
3530         struct bnx2x *bp = params->bp;
3531         u8 port;
3532         u32 val;
3533         DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3534         port = params->port;
3535
3536         val = XGXS_RESET_BITS << (port*16);
3537
3538         /* reset and unreset the SerDes/XGXS */
3539         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3540         udelay(500);
3541         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3542
3543         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
3544         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
3545                params->phy[INT_PHY].def_md_devad);
3546 }
3547
3548 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3549                                      struct link_params *params, u16 *ieee_fc)
3550 {
3551         struct bnx2x *bp = params->bp;
3552         *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3553         /* Resolve pause mode and advertisement Please refer to Table
3554          * 28B-3 of the 802.3ab-1999 spec
3555          */
3556
3557         switch (phy->req_flow_ctrl) {
3558         case BNX2X_FLOW_CTRL_AUTO:
3559                 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
3560                         *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3561                 else
3562                         *ieee_fc |=
3563                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3564                 break;
3565
3566         case BNX2X_FLOW_CTRL_TX:
3567                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3568                 break;
3569
3570         case BNX2X_FLOW_CTRL_RX:
3571         case BNX2X_FLOW_CTRL_BOTH:
3572                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3573                 break;
3574
3575         case BNX2X_FLOW_CTRL_NONE:
3576         default:
3577                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3578                 break;
3579         }
3580         DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3581 }
3582
3583 static void set_phy_vars(struct link_params *params,
3584                          struct link_vars *vars)
3585 {
3586         struct bnx2x *bp = params->bp;
3587         u8 actual_phy_idx, phy_index, link_cfg_idx;
3588         u8 phy_config_swapped = params->multi_phy_config &
3589                         PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3590         for (phy_index = INT_PHY; phy_index < params->num_phys;
3591               phy_index++) {
3592                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3593                 actual_phy_idx = phy_index;
3594                 if (phy_config_swapped) {
3595                         if (phy_index == EXT_PHY1)
3596                                 actual_phy_idx = EXT_PHY2;
3597                         else if (phy_index == EXT_PHY2)
3598                                 actual_phy_idx = EXT_PHY1;
3599                 }
3600                 params->phy[actual_phy_idx].req_flow_ctrl =
3601                         params->req_flow_ctrl[link_cfg_idx];
3602
3603                 params->phy[actual_phy_idx].req_line_speed =
3604                         params->req_line_speed[link_cfg_idx];
3605
3606                 params->phy[actual_phy_idx].speed_cap_mask =
3607                         params->speed_cap_mask[link_cfg_idx];
3608
3609                 params->phy[actual_phy_idx].req_duplex =
3610                         params->req_duplex[link_cfg_idx];
3611
3612                 if (params->req_line_speed[link_cfg_idx] ==
3613                     SPEED_AUTO_NEG)
3614                         vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3615
3616                 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3617                            " speed_cap_mask %x\n",
3618                            params->phy[actual_phy_idx].req_flow_ctrl,
3619                            params->phy[actual_phy_idx].req_line_speed,
3620                            params->phy[actual_phy_idx].speed_cap_mask);
3621         }
3622 }
3623
3624 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3625                                     struct bnx2x_phy *phy,
3626                                     struct link_vars *vars)
3627 {
3628         u16 val;
3629         struct bnx2x *bp = params->bp;
3630         /* read modify write pause advertizing */
3631         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3632
3633         val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3634
3635         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3636         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3637         if ((vars->ieee_fc &
3638             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3639             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3640                 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3641         }
3642         if ((vars->ieee_fc &
3643             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3644             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3645                 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3646         }
3647         DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3648         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3649 }
3650
3651 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3652 {                                               /*  LD      LP   */
3653         switch (pause_result) {                 /* ASYM P ASYM P */
3654         case 0xb:                               /*   1  0   1  1 */
3655                 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3656                 break;
3657
3658         case 0xe:                               /*   1  1   1  0 */
3659                 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3660                 break;
3661
3662         case 0x5:                               /*   0  1   0  1 */
3663         case 0x7:                               /*   0  1   1  1 */
3664         case 0xd:                               /*   1  1   0  1 */
3665         case 0xf:                               /*   1  1   1  1 */
3666                 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3667                 break;
3668
3669         default:
3670                 break;
3671         }
3672         if (pause_result & (1<<0))
3673                 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3674         if (pause_result & (1<<1))
3675                 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3676
3677 }
3678
3679 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
3680                                         struct link_params *params,
3681                                         struct link_vars *vars)
3682 {
3683         u16 ld_pause;           /* local */
3684         u16 lp_pause;           /* link partner */
3685         u16 pause_result;
3686         struct bnx2x *bp = params->bp;
3687         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3688                 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause);
3689                 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause);
3690         } else if (CHIP_IS_E3(bp) &&
3691                 SINGLE_MEDIA_DIRECT(params)) {
3692                 u8 lane = bnx2x_get_warpcore_lane(phy, params);
3693                 u16 gp_status, gp_mask;
3694                 bnx2x_cl45_read(bp, phy,
3695                                 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
3696                                 &gp_status);
3697                 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
3698                            MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3699                         lane;
3700                 if ((gp_status & gp_mask) == gp_mask) {
3701                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3702                                         MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3703                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3704                                         MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3705                 } else {
3706                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3707                                         MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3708                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3709                                         MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3710                         ld_pause = ((ld_pause &
3711                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3712                                     << 3);
3713                         lp_pause = ((lp_pause &
3714                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3715                                     << 3);
3716                 }
3717         } else {
3718                 bnx2x_cl45_read(bp, phy,
3719                                 MDIO_AN_DEVAD,
3720                                 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3721                 bnx2x_cl45_read(bp, phy,
3722                                 MDIO_AN_DEVAD,
3723                                 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3724         }
3725         pause_result = (ld_pause &
3726                         MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3727         pause_result |= (lp_pause &
3728                          MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3729         DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result);
3730         bnx2x_pause_resolve(vars, pause_result);
3731
3732 }
3733
3734 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3735                                    struct link_params *params,
3736                                    struct link_vars *vars)
3737 {
3738         u8 ret = 0;
3739         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3740         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
3741                 /* Update the advertised flow-controled of LD/LP in AN */
3742                 if (phy->req_line_speed == SPEED_AUTO_NEG)
3743                         bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3744                 /* But set the flow-control result as the requested one */
3745                 vars->flow_ctrl = phy->req_flow_ctrl;
3746         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
3747                 vars->flow_ctrl = params->req_fc_auto_adv;
3748         else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3749                 ret = 1;
3750                 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3751         }
3752         return ret;
3753 }
3754 /******************************************************************/
3755 /*                      Warpcore section                          */
3756 /******************************************************************/
3757 /* The init_internal_warpcore should mirror the xgxs,
3758  * i.e. reset the lane (if needed), set aer for the
3759  * init configuration, and set/clear SGMII flag. Internal
3760  * phy init is done purely in phy_init stage.
3761  */
3762 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3763                                         struct link_params *params,
3764                                         struct link_vars *vars) {
3765         u16 val16 = 0, lane, bam37 = 0;
3766         struct bnx2x *bp = params->bp;
3767         DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3768         /* Set to default registers that may be overriden by 10G force */
3769         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3770                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7);
3771         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3772                          MDIO_WC_REG_PAR_DET_10G_CTRL, 0);
3773         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3774                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0);
3775         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3776                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0xff);
3777         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3778                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0x5555);
3779         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3780                          MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0);
3781         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3782                          MDIO_WC_REG_RX66_CONTROL, 0x7415);
3783         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3784                          MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190);
3785         /* Disable Autoneg: re-enable it after adv is done. */
3786         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3787                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0);
3788
3789         /* Check adding advertisement for 1G KX */
3790         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3791              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3792             (vars->line_speed == SPEED_1000)) {
3793                 u16 sd_digital;
3794                 val16 |= (1<<5);
3795
3796                 /* Enable CL37 1G Parallel Detect */
3797                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3798                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &sd_digital);
3799                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3800                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3801                                  (sd_digital | 0x1));
3802
3803                 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3804         }
3805         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3806              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3807             (vars->line_speed ==  SPEED_10000)) {
3808                 /* Check adding advertisement for 10G KR */
3809                 val16 |= (1<<7);
3810                 /* Enable 10G Parallel Detect */
3811                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3812                                 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3813
3814                 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3815         }
3816
3817         /* Set Transmit PMD settings */
3818         lane = bnx2x_get_warpcore_lane(phy, params);
3819         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3820                       MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3821                      ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3822                       (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3823                       (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3824         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3825                          MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3826                          0x03f0);
3827         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3828                          MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3829                          0x03f0);
3830
3831         /* Advertised speeds */
3832         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3833                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, val16);
3834
3835         /* Advertised and set FEC (Forward Error Correction) */
3836         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3837                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3838                          (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3839                           MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3840
3841         /* Enable CL37 BAM */
3842         if (REG_RD(bp, params->shmem_base +
3843                    offsetof(struct shmem_region, dev_info.
3844                             port_hw_config[params->port].default_cfg)) &
3845             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3846                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3847                                 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, &bam37);
3848                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3849                         MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, bam37 | 1);
3850                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3851         }
3852
3853         /* Advertise pause */
3854         bnx2x_ext_phy_set_pause(params, phy, vars);
3855         /* Set KR Autoneg Work-Around flag for Warpcore version older than D108
3856          */
3857         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3858                         MDIO_WC_REG_UC_INFO_B1_VERSION, &val16);
3859         if (val16 < 0xd108) {
3860                 DP(NETIF_MSG_LINK, "Enable AN KR work-around\n");
3861                 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3862         }
3863         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3864                         MDIO_WC_REG_DIGITAL5_MISC7, &val16);
3865
3866         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3867                          MDIO_WC_REG_DIGITAL5_MISC7, val16 | 0x100);
3868
3869         /* Over 1G - AN local device user page 1 */
3870         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3871                         MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3872
3873         /* Enable Autoneg */
3874         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3875                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
3876
3877 }
3878
3879 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3880                                       struct link_params *params,
3881                                       struct link_vars *vars)
3882 {
3883         struct bnx2x *bp = params->bp;
3884         u16 val;
3885
3886         /* Disable Autoneg */
3887         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3888                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7);
3889
3890         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3891                          MDIO_WC_REG_PAR_DET_10G_CTRL, 0);
3892
3893         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3894                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0x3f00);
3895
3896         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3897                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0);
3898
3899         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3900                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3901
3902         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3903                         MDIO_WC_REG_DIGITAL3_UP1, 0x1);
3904
3905         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3906                          MDIO_WC_REG_DIGITAL5_MISC7, 0xa);
3907
3908         /* Disable CL36 PCS Tx */
3909         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3910                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0x0);
3911
3912         /* Double Wide Single Data Rate @ pll rate */
3913         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3914                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0xFFFF);
3915
3916         /* Leave cl72 training enable, needed for KR */
3917         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3918                 MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150,
3919                 0x2);
3920
3921         /* Leave CL72 enabled */
3922         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3923                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3924                          &val);
3925         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3926                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3927                          val | 0x3800);
3928
3929         /* Set speed via PMA/PMD register */
3930         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3931                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3932
3933         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3934                          MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3935
3936         /* Enable encoded forced speed */
3937         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3938                          MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3939
3940         /* Turn TX scramble payload only the 64/66 scrambler */
3941         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3942                          MDIO_WC_REG_TX66_CONTROL, 0x9);
3943
3944         /* Turn RX scramble payload only the 64/66 scrambler */
3945         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3946                                  MDIO_WC_REG_RX66_CONTROL, 0xF9);
3947
3948         /* set and clear loopback to cause a reset to 64/66 decoder */
3949         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3950                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3951         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3952                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3953
3954 }
3955
3956 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3957                                        struct link_params *params,
3958                                        u8 is_xfi)
3959 {
3960         struct bnx2x *bp = params->bp;
3961         u16 misc1_val, tap_val, tx_driver_val, lane, val;
3962         /* Hold rxSeqStart */
3963         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3964                         MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3965         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3966                          MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val | 0x8000));
3967
3968         /* Hold tx_fifo_reset */
3969         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3970                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3971         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3972                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, (val | 0x1));
3973
3974         /* Disable CL73 AN */
3975         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3976
3977         /* Disable 100FX Enable and Auto-Detect */
3978         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3979                         MDIO_WC_REG_FX100_CTRL1, &val);
3980         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3981                          MDIO_WC_REG_FX100_CTRL1, (val & 0xFFFA));
3982
3983         /* Disable 100FX Idle detect */
3984         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3985                         MDIO_WC_REG_FX100_CTRL3, &val);
3986         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3987                          MDIO_WC_REG_FX100_CTRL3, (val | 0x0080));
3988
3989         /* Set Block address to Remote PHY & Clear forced_speed[5] */
3990         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3991                         MDIO_WC_REG_DIGITAL4_MISC3, &val);
3992         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3993                          MDIO_WC_REG_DIGITAL4_MISC3, (val & 0xFF7F));
3994
3995         /* Turn off auto-detect & fiber mode */
3996         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3997                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3998         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3999                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4000                          (val & 0xFFEE));
4001
4002         /* Set filter_force_link, disable_false_link and parallel_detect */
4003         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4004                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
4005         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4006                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4007                          ((val | 0x0006) & 0xFFFE));
4008
4009         /* Set XFI / SFI */
4010         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4011                         MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
4012
4013         misc1_val &= ~(0x1f);
4014
4015         if (is_xfi) {
4016                 misc1_val |= 0x5;
4017                 tap_val = ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
4018                            (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
4019                            (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
4020                 tx_driver_val =
4021                       ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
4022                        (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
4023                        (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
4024
4025         } else {
4026                 misc1_val |= 0x9;
4027                 tap_val = ((0x0f << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
4028                            (0x2b << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
4029                            (0x02 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
4030                 tx_driver_val =
4031                       ((0x03 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
4032                        (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
4033                        (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
4034         }
4035         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4036                          MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
4037
4038         /* Set Transmit PMD settings */
4039         lane = bnx2x_get_warpcore_lane(phy, params);
4040         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4041                          MDIO_WC_REG_TX_FIR_TAP,
4042                          tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
4043         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4044                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4045                          tx_driver_val);
4046
4047         /* Enable fiber mode, enable and invert sig_det */
4048         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4049                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
4050         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4051                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, val | 0xd);
4052
4053         /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
4054         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4055                         MDIO_WC_REG_DIGITAL4_MISC3, &val);
4056         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4057                          MDIO_WC_REG_DIGITAL4_MISC3, val | 0x8080);
4058
4059         /* Enable LPI pass through */
4060         if ((params->eee_mode & EEE_MODE_ADV_LPI) &&
4061             (phy->flags & FLAGS_EEE_10GBT) &&
4062             (!(params->eee_mode & EEE_MODE_ENABLE_LPI) ||
4063               bnx2x_eee_calc_timer(params)) &&
4064             (params->req_duplex[bnx2x_phy_selection(params)] == DUPLEX_FULL)) {
4065                 DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n");
4066                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4067                                  MDIO_WC_REG_EEE_COMBO_CONTROL0,
4068                                  0x7c);
4069                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4070                                          MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
4071         }
4072
4073         /* 10G XFI Full Duplex */
4074         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4075                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
4076
4077         /* Release tx_fifo_reset */
4078         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4079                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
4080         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4081                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, val & 0xFFFE);
4082
4083         /* Release rxSeqStart */
4084         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4085                         MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
4086         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4087                          MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val & 0x7FFF));
4088 }
4089
4090 static void bnx2x_warpcore_set_20G_KR2(struct bnx2x *bp,
4091                                        struct bnx2x_phy *phy)
4092 {
4093         DP(NETIF_MSG_LINK, "KR2 still not supported !!!\n");
4094 }
4095
4096 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
4097                                          struct bnx2x_phy *phy,
4098                                          u16 lane)
4099 {
4100         /* Rx0 anaRxControl1G */
4101         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4102                          MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4103
4104         /* Rx2 anaRxControl1G */
4105         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4106                          MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4107
4108         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4109                          MDIO_WC_REG_RX66_SCW0, 0xE070);
4110
4111         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4112                          MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4113
4114         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4115                          MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4116
4117         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4118                          MDIO_WC_REG_RX66_SCW3, 0x8090);
4119
4120         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4121                          MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4122
4123         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4124                          MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4125
4126         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4127                          MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
4128
4129         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4130                          MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
4131
4132         /* Serdes Digital Misc1 */
4133         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4134                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
4135
4136         /* Serdes Digital4 Misc3 */
4137         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4138                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
4139
4140         /* Set Transmit PMD settings */
4141         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4142                          MDIO_WC_REG_TX_FIR_TAP,
4143                         ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
4144                          (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
4145                          (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET) |
4146                          MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4147         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4148                       MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4149                      ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
4150                       (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
4151                       (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
4152 }
4153
4154 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
4155                                            struct link_params *params,
4156                                            u8 fiber_mode,
4157                                            u8 always_autoneg)
4158 {
4159         struct bnx2x *bp = params->bp;
4160         u16 val16, digctrl_kx1, digctrl_kx2;
4161
4162         /* Clear XFI clock comp in non-10G single lane mode. */
4163         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4164                         MDIO_WC_REG_RX66_CONTROL, &val16);
4165         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4166                          MDIO_WC_REG_RX66_CONTROL, val16 & ~(3<<13));
4167
4168         if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) {
4169                 /* SGMII Autoneg */
4170                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4171                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4172                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4173                                  MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4174                                  val16 | 0x1000);
4175                 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
4176         } else {
4177                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4178                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4179                 val16 &= 0xcebf;
4180                 switch (phy->req_line_speed) {
4181                 case SPEED_10:
4182                         break;
4183                 case SPEED_100:
4184                         val16 |= 0x2000;
4185                         break;
4186                 case SPEED_1000:
4187                         val16 |= 0x0040;
4188                         break;
4189                 default:
4190                         DP(NETIF_MSG_LINK,
4191                            "Speed not supported: 0x%x\n", phy->req_line_speed);
4192                         return;
4193                 }
4194
4195                 if (phy->req_duplex == DUPLEX_FULL)
4196                         val16 |= 0x0100;
4197
4198                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4199                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
4200
4201                 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
4202                                phy->req_line_speed);
4203                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4204                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4205                 DP(NETIF_MSG_LINK, "  (readback) %x\n", val16);
4206         }
4207
4208         /* SGMII Slave mode and disable signal detect */
4209         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4210                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
4211         if (fiber_mode)
4212                 digctrl_kx1 = 1;
4213         else
4214                 digctrl_kx1 &= 0xff4a;
4215
4216         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4217                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4218                         digctrl_kx1);
4219
4220         /* Turn off parallel detect */
4221         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4222                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
4223         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4224                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4225                         (digctrl_kx2 & ~(1<<2)));
4226
4227         /* Re-enable parallel detect */
4228         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4229                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4230                         (digctrl_kx2 | (1<<2)));
4231
4232         /* Enable autodet */
4233         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4234                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4235                         (digctrl_kx1 | 0x10));
4236 }
4237
4238 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4239                                       struct bnx2x_phy *phy,
4240                                       u8 reset)
4241 {
4242         u16 val;
4243         /* Take lane out of reset after configuration is finished */
4244         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4245                         MDIO_WC_REG_DIGITAL5_MISC6, &val);
4246         if (reset)
4247                 val |= 0xC000;
4248         else
4249                 val &= 0x3FFF;
4250         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4251                          MDIO_WC_REG_DIGITAL5_MISC6, val);
4252         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4253                          MDIO_WC_REG_DIGITAL5_MISC6, &val);
4254 }
4255 /* Clear SFI/XFI link settings registers */
4256 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4257                                       struct link_params *params,
4258                                       u16 lane)
4259 {
4260         struct bnx2x *bp = params->bp;
4261         u16 val16;
4262
4263         /* Set XFI clock comp as default. */
4264         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4265                         MDIO_WC_REG_RX66_CONTROL, &val16);
4266         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4267                          MDIO_WC_REG_RX66_CONTROL, val16 | (3<<13));
4268
4269         bnx2x_warpcore_reset_lane(bp, phy, 1);
4270         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
4271         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4272                          MDIO_WC_REG_FX100_CTRL1, 0x014a);
4273         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4274                          MDIO_WC_REG_FX100_CTRL3, 0x0800);
4275         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4276                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8008);
4277         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4278                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x0195);
4279         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4280                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x0007);
4281         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4282                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x0002);
4283         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4284                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000);
4285         lane = bnx2x_get_warpcore_lane(phy, params);
4286         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4287                          MDIO_WC_REG_TX_FIR_TAP, 0x0000);
4288         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4289                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4290         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4291                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
4292         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4293                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140);
4294         bnx2x_warpcore_reset_lane(bp, phy, 0);
4295 }
4296
4297 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4298                                                 u32 chip_id,
4299                                                 u32 shmem_base, u8 port,
4300                                                 u8 *gpio_num, u8 *gpio_port)
4301 {
4302         u32 cfg_pin;
4303         *gpio_num = 0;
4304         *gpio_port = 0;
4305         if (CHIP_IS_E3(bp)) {
4306                 cfg_pin = (REG_RD(bp, shmem_base +
4307                                 offsetof(struct shmem_region,
4308                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4309                                 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4310                                 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4311
4312                 /* Should not happen. This function called upon interrupt
4313                  * triggered by GPIO ( since EPIO can only generate interrupts
4314                  * to MCP).
4315                  * So if this function was called and none of the GPIOs was set,
4316                  * it means the shit hit the fan.
4317                  */
4318                 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4319                     (cfg_pin > PIN_CFG_GPIO3_P1)) {
4320                         DP(NETIF_MSG_LINK,
4321                            "ERROR: Invalid cfg pin %x for module detect indication\n",
4322                            cfg_pin);
4323                         return -EINVAL;
4324                 }
4325
4326                 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4327                 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4328         } else {
4329                 *gpio_num = MISC_REGISTERS_GPIO_3;
4330                 *gpio_port = port;
4331         }
4332         DP(NETIF_MSG_LINK, "MOD_ABS int GPIO%d_P%d\n", *gpio_num, *gpio_port);
4333         return 0;
4334 }
4335
4336 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4337                                        struct link_params *params)
4338 {
4339         struct bnx2x *bp = params->bp;
4340         u8 gpio_num, gpio_port;
4341         u32 gpio_val;
4342         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4343                                       params->shmem_base, params->port,
4344                                       &gpio_num, &gpio_port) != 0)
4345                 return 0;
4346         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4347
4348         /* Call the handling function in case module is detected */
4349         if (gpio_val == 0)
4350                 return 1;
4351         else
4352                 return 0;
4353 }
4354 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy,
4355                                         struct link_params *params)
4356 {
4357         u16 gp2_status_reg0, lane;
4358         struct bnx2x *bp = params->bp;
4359
4360         lane = bnx2x_get_warpcore_lane(phy, params);
4361
4362         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4363                                  &gp2_status_reg0);
4364
4365         return (gp2_status_reg0 >> (8+lane)) & 0x1;
4366 }
4367
4368 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4369                                        struct link_params *params,
4370                                        struct link_vars *vars)
4371 {
4372         struct bnx2x *bp = params->bp;
4373         u32 serdes_net_if;
4374         u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4375         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4376
4377         vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4378
4379         if (!vars->turn_to_run_wc_rt)
4380                 return;
4381
4382         /* return if there is no link partner */
4383         if (!(bnx2x_warpcore_get_sigdet(phy, params))) {
4384                 DP(NETIF_MSG_LINK, "bnx2x_warpcore_get_sigdet false\n");
4385                 return;
4386         }
4387
4388         if (vars->rx_tx_asic_rst) {
4389                 serdes_net_if = (REG_RD(bp, params->shmem_base +
4390                                 offsetof(struct shmem_region, dev_info.
4391                                 port_hw_config[params->port].default_cfg)) &
4392                                 PORT_HW_CFG_NET_SERDES_IF_MASK);
4393
4394                 switch (serdes_net_if) {
4395                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4396                         /* Do we get link yet? */
4397                         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1,
4398                                                                 &gp_status1);
4399                         lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
4400                                 /*10G KR*/
4401                         lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
4402
4403                         DP(NETIF_MSG_LINK,
4404                                 "gp_status1 0x%x\n", gp_status1);
4405
4406                         if (lnkup_kr || lnkup) {
4407                                         vars->rx_tx_asic_rst = 0;
4408                                         DP(NETIF_MSG_LINK,
4409                                         "link up, rx_tx_asic_rst 0x%x\n",
4410                                         vars->rx_tx_asic_rst);
4411                         } else {
4412                                 /* Reset the lane to see if link comes up.*/
4413                                 bnx2x_warpcore_reset_lane(bp, phy, 1);
4414                                 bnx2x_warpcore_reset_lane(bp, phy, 0);
4415
4416                                 /* restart Autoneg */
4417                                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4418                                         MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4419
4420                                 vars->rx_tx_asic_rst--;
4421                                 DP(NETIF_MSG_LINK, "0x%x retry left\n",
4422                                 vars->rx_tx_asic_rst);
4423                         }
4424                         break;
4425
4426                 default:
4427                         break;
4428                 }
4429
4430         } /*params->rx_tx_asic_rst*/
4431
4432 }
4433 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4434                                        struct link_params *params,
4435                                        struct link_vars *vars)
4436 {
4437         struct bnx2x *bp = params->bp;
4438         u32 serdes_net_if;
4439         u8 fiber_mode;
4440         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4441         serdes_net_if = (REG_RD(bp, params->shmem_base +
4442                          offsetof(struct shmem_region, dev_info.
4443                                   port_hw_config[params->port].default_cfg)) &
4444                          PORT_HW_CFG_NET_SERDES_IF_MASK);
4445         DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4446                            "serdes_net_if = 0x%x\n",
4447                        vars->line_speed, serdes_net_if);
4448         bnx2x_set_aer_mmd(params, phy);
4449
4450         vars->phy_flags |= PHY_XGXS_FLAG;
4451         if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4452             (phy->req_line_speed &&
4453              ((phy->req_line_speed == SPEED_100) ||
4454               (phy->req_line_speed == SPEED_10)))) {
4455                 vars->phy_flags |= PHY_SGMII_FLAG;
4456                 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4457                 bnx2x_warpcore_clear_regs(phy, params, lane);
4458                 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1);
4459         } else {
4460                 switch (serdes_net_if) {
4461                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4462                         /* Enable KR Auto Neg */
4463                         if (params->loopback_mode != LOOPBACK_EXT)
4464                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4465                         else {
4466                                 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4467                                 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4468                         }
4469                         break;
4470
4471                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4472                         bnx2x_warpcore_clear_regs(phy, params, lane);
4473                         if (vars->line_speed == SPEED_10000) {
4474                                 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4475                                 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4476                         } else {
4477                                 if (SINGLE_MEDIA_DIRECT(params)) {
4478                                         DP(NETIF_MSG_LINK, "1G Fiber\n");
4479                                         fiber_mode = 1;
4480                                 } else {
4481                                         DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4482                                         fiber_mode = 0;
4483                                 }
4484                                 bnx2x_warpcore_set_sgmii_speed(phy,
4485                                                                 params,
4486                                                                 fiber_mode,
4487                                                                 0);
4488                         }
4489
4490                         break;
4491
4492                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4493
4494                         bnx2x_warpcore_clear_regs(phy, params, lane);
4495                         if (vars->line_speed == SPEED_10000) {
4496                                 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4497                                 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4498                         } else if (vars->line_speed == SPEED_1000) {
4499                                 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4500                                 bnx2x_warpcore_set_sgmii_speed(
4501                                                 phy, params, 1, 0);
4502                         }
4503                         /* Issue Module detection */
4504                         if (bnx2x_is_sfp_module_plugged(phy, params))
4505                                 bnx2x_sfp_module_detection(phy, params);
4506                         break;
4507
4508                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4509                         if (vars->line_speed != SPEED_20000) {
4510                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4511                                 return;
4512                         }
4513                         DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4514                         bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4515                         /* Issue Module detection */
4516
4517                         bnx2x_sfp_module_detection(phy, params);
4518                         break;
4519
4520                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4521                         if (vars->line_speed != SPEED_20000) {
4522                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4523                                 return;
4524                         }
4525                         DP(NETIF_MSG_LINK, "Setting 20G KR2\n");
4526                         bnx2x_warpcore_set_20G_KR2(bp, phy);
4527                         break;
4528
4529                 default:
4530                         DP(NETIF_MSG_LINK,
4531                            "Unsupported Serdes Net Interface 0x%x\n",
4532                            serdes_net_if);
4533                         return;
4534                 }
4535         }
4536
4537         /* Take lane out of reset after configuration is finished */
4538         bnx2x_warpcore_reset_lane(bp, phy, 0);
4539         DP(NETIF_MSG_LINK, "Exit config init\n");
4540 }
4541
4542 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4543                                          struct bnx2x_phy *phy,
4544                                          u8 tx_en)
4545 {
4546         struct bnx2x *bp = params->bp;
4547         u32 cfg_pin;
4548         u8 port = params->port;
4549
4550         cfg_pin = REG_RD(bp, params->shmem_base +
4551                                 offsetof(struct shmem_region,
4552                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4553                                 PORT_HW_CFG_TX_LASER_MASK;
4554         /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4555         DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4556         /* For 20G, the expected pin to be used is 3 pins after the current */
4557
4558         bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4559         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4560                 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4561 }
4562
4563 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4564                                       struct link_params *params)
4565 {
4566         struct bnx2x *bp = params->bp;
4567         u16 val16;
4568         bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4569         bnx2x_set_mdio_clk(bp, params->chip_id, params->port);
4570         bnx2x_set_aer_mmd(params, phy);
4571         /* Global register */
4572         bnx2x_warpcore_reset_lane(bp, phy, 1);
4573
4574         /* Clear loopback settings (if any) */
4575         /* 10G & 20G */
4576         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4577                         MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4578         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4579                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 &
4580                          0xBFFF);
4581
4582         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4583                         MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4584         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4585                         MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 & 0xfffe);
4586
4587         /* Update those 1-copy registers */
4588         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4589                           MDIO_AER_BLOCK_AER_REG, 0);
4590         /* Enable 1G MDIO (1-copy) */
4591         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4592                         MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4593                         &val16);
4594         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4595                          MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4596                          val16 & ~0x10);
4597
4598         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4599                         MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4600         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4601                          MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4602                          val16 & 0xff00);
4603
4604 }
4605
4606 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4607                                         struct link_params *params)
4608 {
4609         struct bnx2x *bp = params->bp;
4610         u16 val16;
4611         u32 lane;
4612         DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4613                        params->loopback_mode, phy->req_line_speed);
4614
4615         if (phy->req_line_speed < SPEED_10000) {
4616                 /* 10/100/1000 */
4617
4618                 /* Update those 1-copy registers */
4619                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4620                                   MDIO_AER_BLOCK_AER_REG, 0);
4621                 /* Enable 1G MDIO (1-copy) */
4622                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4623                                 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4624                                 &val16);
4625                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4626                                 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4627                                 val16 | 0x10);
4628                 /* Set 1G loopback based on lane (1-copy) */
4629                 lane = bnx2x_get_warpcore_lane(phy, params);
4630                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4631                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4632                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4633                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4634                                 val16 | (1<<lane));
4635
4636                 /* Switch back to 4-copy registers */
4637                 bnx2x_set_aer_mmd(params, phy);
4638         } else {
4639                 /* 10G & 20G */
4640                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4641                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4642                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4643                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
4644                                  0x4000);
4645
4646                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4647                                 MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4648                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4649                                 MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 | 0x1);
4650         }
4651 }
4652
4653
4654 void bnx2x_sync_link(struct link_params *params,
4655                            struct link_vars *vars)
4656 {
4657         struct bnx2x *bp = params->bp;
4658         u8 link_10g_plus;
4659         if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4660                 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4661         vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4662         if (vars->link_up) {
4663                 DP(NETIF_MSG_LINK, "phy link up\n");
4664
4665                 vars->phy_link_up = 1;
4666                 vars->duplex = DUPLEX_FULL;
4667                 switch (vars->link_status &
4668                         LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4669                 case LINK_10THD:
4670                         vars->duplex = DUPLEX_HALF;
4671                         /* Fall thru */
4672                 case LINK_10TFD:
4673                         vars->line_speed = SPEED_10;
4674                         break;
4675
4676                 case LINK_100TXHD:
4677                         vars->duplex = DUPLEX_HALF;
4678                         /* Fall thru */
4679                 case LINK_100T4:
4680                 case LINK_100TXFD:
4681                         vars->line_speed = SPEED_100;
4682                         break;
4683
4684                 case LINK_1000THD:
4685                         vars->duplex = DUPLEX_HALF;
4686                         /* Fall thru */
4687                 case LINK_1000TFD:
4688                         vars->line_speed = SPEED_1000;
4689                         break;
4690
4691                 case LINK_2500THD:
4692                         vars->duplex = DUPLEX_HALF;
4693                         /* Fall thru */
4694                 case LINK_2500TFD:
4695                         vars->line_speed = SPEED_2500;
4696                         break;
4697
4698                 case LINK_10GTFD:
4699                         vars->line_speed = SPEED_10000;
4700                         break;
4701                 case LINK_20GTFD:
4702                         vars->line_speed = SPEED_20000;
4703                         break;
4704                 default:
4705                         break;
4706                 }
4707                 vars->flow_ctrl = 0;
4708                 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4709                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4710
4711                 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4712                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4713
4714                 if (!vars->flow_ctrl)
4715                         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4716
4717                 if (vars->line_speed &&
4718                     ((vars->line_speed == SPEED_10) ||
4719                      (vars->line_speed == SPEED_100))) {
4720                         vars->phy_flags |= PHY_SGMII_FLAG;
4721                 } else {
4722                         vars->phy_flags &= ~PHY_SGMII_FLAG;
4723                 }
4724                 if (vars->line_speed &&
4725                     USES_WARPCORE(bp) &&
4726                     (vars->line_speed == SPEED_1000))
4727                         vars->phy_flags |= PHY_SGMII_FLAG;
4728                 /* anything 10 and over uses the bmac */
4729                 link_10g_plus = (vars->line_speed >= SPEED_10000);
4730
4731                 if (link_10g_plus) {
4732                         if (USES_WARPCORE(bp))
4733                                 vars->mac_type = MAC_TYPE_XMAC;
4734                         else
4735                                 vars->mac_type = MAC_TYPE_BMAC;
4736                 } else {
4737                         if (USES_WARPCORE(bp))
4738                                 vars->mac_type = MAC_TYPE_UMAC;
4739                         else
4740                                 vars->mac_type = MAC_TYPE_EMAC;
4741                 }
4742         } else { /* link down */
4743                 DP(NETIF_MSG_LINK, "phy link down\n");
4744
4745                 vars->phy_link_up = 0;
4746
4747                 vars->line_speed = 0;
4748                 vars->duplex = DUPLEX_FULL;
4749                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4750
4751                 /* indicate no mac active */
4752                 vars->mac_type = MAC_TYPE_NONE;
4753                 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4754                         vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4755         }
4756 }
4757
4758 void bnx2x_link_status_update(struct link_params *params,
4759                               struct link_vars *vars)
4760 {
4761         struct bnx2x *bp = params->bp;
4762         u8 port = params->port;
4763         u32 sync_offset, media_types;
4764         /* Update PHY configuration */
4765         set_phy_vars(params, vars);
4766
4767         vars->link_status = REG_RD(bp, params->shmem_base +
4768                                    offsetof(struct shmem_region,
4769                                             port_mb[port].link_status));
4770
4771         vars->phy_flags = PHY_XGXS_FLAG;
4772         bnx2x_sync_link(params, vars);
4773         /* Sync media type */
4774         sync_offset = params->shmem_base +
4775                         offsetof(struct shmem_region,
4776                                  dev_info.port_hw_config[port].media_type);
4777         media_types = REG_RD(bp, sync_offset);
4778
4779         params->phy[INT_PHY].media_type =
4780                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4781                 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4782         params->phy[EXT_PHY1].media_type =
4783                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4784                 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4785         params->phy[EXT_PHY2].media_type =
4786                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4787                 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4788         DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4789
4790         /* Sync AEU offset */
4791         sync_offset = params->shmem_base +
4792                         offsetof(struct shmem_region,
4793                                  dev_info.port_hw_config[port].aeu_int_mask);
4794
4795         vars->aeu_int_mask = REG_RD(bp, sync_offset);
4796
4797         /* Sync PFC status */
4798         if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4799                 params->feature_config_flags |=
4800                                         FEATURE_CONFIG_PFC_ENABLED;
4801         else
4802                 params->feature_config_flags &=
4803                                         ~FEATURE_CONFIG_PFC_ENABLED;
4804
4805         DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x int_mask 0x%x\n",
4806                  vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4807         DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
4808                  vars->line_speed, vars->duplex, vars->flow_ctrl);
4809 }
4810
4811 static void bnx2x_set_master_ln(struct link_params *params,
4812                                 struct bnx2x_phy *phy)
4813 {
4814         struct bnx2x *bp = params->bp;
4815         u16 new_master_ln, ser_lane;
4816         ser_lane = ((params->lane_config &
4817                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4818                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4819
4820         /* set the master_ln for AN */
4821         CL22_RD_OVER_CL45(bp, phy,
4822                           MDIO_REG_BANK_XGXS_BLOCK2,
4823                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4824                           &new_master_ln);
4825
4826         CL22_WR_OVER_CL45(bp, phy,
4827                           MDIO_REG_BANK_XGXS_BLOCK2 ,
4828                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4829                           (new_master_ln | ser_lane));
4830 }
4831
4832 static int bnx2x_reset_unicore(struct link_params *params,
4833                                struct bnx2x_phy *phy,
4834                                u8 set_serdes)
4835 {
4836         struct bnx2x *bp = params->bp;
4837         u16 mii_control;
4838         u16 i;
4839         CL22_RD_OVER_CL45(bp, phy,
4840                           MDIO_REG_BANK_COMBO_IEEE0,
4841                           MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4842
4843         /* reset the unicore */
4844         CL22_WR_OVER_CL45(bp, phy,
4845                           MDIO_REG_BANK_COMBO_IEEE0,
4846                           MDIO_COMBO_IEEE0_MII_CONTROL,
4847                           (mii_control |
4848                            MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4849         if (set_serdes)
4850                 bnx2x_set_serdes_access(bp, params->port);
4851
4852         /* wait for the reset to self clear */
4853         for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4854                 udelay(5);
4855
4856                 /* the reset erased the previous bank value */
4857                 CL22_RD_OVER_CL45(bp, phy,
4858                                   MDIO_REG_BANK_COMBO_IEEE0,
4859                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4860                                   &mii_control);
4861
4862                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4863                         udelay(5);
4864                         return 0;
4865                 }
4866         }
4867
4868         netdev_err(bp->dev,  "Warning: PHY was not initialized,"
4869                               " Port %d\n",
4870                          params->port);
4871         DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4872         return -EINVAL;
4873
4874 }
4875
4876 static void bnx2x_set_swap_lanes(struct link_params *params,
4877                                  struct bnx2x_phy *phy)
4878 {
4879         struct bnx2x *bp = params->bp;
4880         /* Each two bits represents a lane number:
4881          * No swap is 0123 => 0x1b no need to enable the swap
4882          */
4883         u16 rx_lane_swap, tx_lane_swap;
4884
4885         rx_lane_swap = ((params->lane_config &
4886                          PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4887                         PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4888         tx_lane_swap = ((params->lane_config &
4889                          PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4890                         PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4891
4892         if (rx_lane_swap != 0x1b) {
4893                 CL22_WR_OVER_CL45(bp, phy,
4894                                   MDIO_REG_BANK_XGXS_BLOCK2,
4895                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4896                                   (rx_lane_swap |
4897                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4898                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4899         } else {
4900                 CL22_WR_OVER_CL45(bp, phy,
4901                                   MDIO_REG_BANK_XGXS_BLOCK2,
4902                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4903         }
4904
4905         if (tx_lane_swap != 0x1b) {
4906                 CL22_WR_OVER_CL45(bp, phy,
4907                                   MDIO_REG_BANK_XGXS_BLOCK2,
4908                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4909                                   (tx_lane_swap |
4910                                    MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4911         } else {
4912                 CL22_WR_OVER_CL45(bp, phy,
4913                                   MDIO_REG_BANK_XGXS_BLOCK2,
4914                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4915         }
4916 }
4917
4918 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4919                                          struct link_params *params)
4920 {
4921         struct bnx2x *bp = params->bp;
4922         u16 control2;
4923         CL22_RD_OVER_CL45(bp, phy,
4924                           MDIO_REG_BANK_SERDES_DIGITAL,
4925                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4926                           &control2);
4927         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4928                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4929         else
4930                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4931         DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4932                 phy->speed_cap_mask, control2);
4933         CL22_WR_OVER_CL45(bp, phy,
4934                           MDIO_REG_BANK_SERDES_DIGITAL,
4935                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4936                           control2);
4937
4938         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4939              (phy->speed_cap_mask &
4940                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4941                 DP(NETIF_MSG_LINK, "XGXS\n");
4942
4943                 CL22_WR_OVER_CL45(bp, phy,
4944                                  MDIO_REG_BANK_10G_PARALLEL_DETECT,
4945                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4946                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4947
4948                 CL22_RD_OVER_CL45(bp, phy,
4949                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4950                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4951                                   &control2);
4952
4953
4954                 control2 |=
4955                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4956
4957                 CL22_WR_OVER_CL45(bp, phy,
4958                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4959                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4960                                   control2);
4961
4962                 /* Disable parallel detection of HiG */
4963                 CL22_WR_OVER_CL45(bp, phy,
4964                                   MDIO_REG_BANK_XGXS_BLOCK2,
4965                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4966                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4967                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4968         }
4969 }
4970
4971 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
4972                               struct link_params *params,
4973                               struct link_vars *vars,
4974                               u8 enable_cl73)
4975 {
4976         struct bnx2x *bp = params->bp;
4977         u16 reg_val;
4978
4979         /* CL37 Autoneg */
4980         CL22_RD_OVER_CL45(bp, phy,
4981                           MDIO_REG_BANK_COMBO_IEEE0,
4982                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4983
4984         /* CL37 Autoneg Enabled */
4985         if (vars->line_speed == SPEED_AUTO_NEG)
4986                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4987         else /* CL37 Autoneg Disabled */
4988                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4989                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4990
4991         CL22_WR_OVER_CL45(bp, phy,
4992                           MDIO_REG_BANK_COMBO_IEEE0,
4993                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4994
4995         /* Enable/Disable Autodetection */
4996
4997         CL22_RD_OVER_CL45(bp, phy,
4998                           MDIO_REG_BANK_SERDES_DIGITAL,
4999                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
5000         reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
5001                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
5002         reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
5003         if (vars->line_speed == SPEED_AUTO_NEG)
5004                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5005         else
5006                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5007
5008         CL22_WR_OVER_CL45(bp, phy,
5009                           MDIO_REG_BANK_SERDES_DIGITAL,
5010                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
5011
5012         /* Enable TetonII and BAM autoneg */
5013         CL22_RD_OVER_CL45(bp, phy,
5014                           MDIO_REG_BANK_BAM_NEXT_PAGE,
5015                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5016                           &reg_val);
5017         if (vars->line_speed == SPEED_AUTO_NEG) {
5018                 /* Enable BAM aneg Mode and TetonII aneg Mode */
5019                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5020                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5021         } else {
5022                 /* TetonII and BAM Autoneg Disabled */
5023                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5024                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5025         }
5026         CL22_WR_OVER_CL45(bp, phy,
5027                           MDIO_REG_BANK_BAM_NEXT_PAGE,
5028                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5029                           reg_val);
5030
5031         if (enable_cl73) {
5032                 /* Enable Cl73 FSM status bits */
5033                 CL22_WR_OVER_CL45(bp, phy,
5034                                   MDIO_REG_BANK_CL73_USERB0,
5035                                   MDIO_CL73_USERB0_CL73_UCTRL,
5036                                   0xe);
5037
5038                 /* Enable BAM Station Manager*/
5039                 CL22_WR_OVER_CL45(bp, phy,
5040                         MDIO_REG_BANK_CL73_USERB0,
5041                         MDIO_CL73_USERB0_CL73_BAM_CTRL1,
5042                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
5043                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
5044                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
5045
5046                 /* Advertise CL73 link speeds */
5047                 CL22_RD_OVER_CL45(bp, phy,
5048                                   MDIO_REG_BANK_CL73_IEEEB1,
5049                                   MDIO_CL73_IEEEB1_AN_ADV2,
5050                                   &reg_val);
5051                 if (phy->speed_cap_mask &
5052                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5053                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
5054                 if (phy->speed_cap_mask &
5055                     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5056                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
5057
5058                 CL22_WR_OVER_CL45(bp, phy,
5059                                   MDIO_REG_BANK_CL73_IEEEB1,
5060                                   MDIO_CL73_IEEEB1_AN_ADV2,
5061                                   reg_val);
5062
5063                 /* CL73 Autoneg Enabled */
5064                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
5065
5066         } else /* CL73 Autoneg Disabled */
5067                 reg_val = 0;
5068
5069         CL22_WR_OVER_CL45(bp, phy,
5070                           MDIO_REG_BANK_CL73_IEEEB0,
5071                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
5072 }
5073
5074 /* program SerDes, forced speed */
5075 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
5076                                  struct link_params *params,
5077                                  struct link_vars *vars)
5078 {
5079         struct bnx2x *bp = params->bp;
5080         u16 reg_val;
5081
5082         /* program duplex, disable autoneg and sgmii*/
5083         CL22_RD_OVER_CL45(bp, phy,
5084                           MDIO_REG_BANK_COMBO_IEEE0,
5085                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
5086         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
5087                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5088                      MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
5089         if (phy->req_duplex == DUPLEX_FULL)
5090                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5091         CL22_WR_OVER_CL45(bp, phy,
5092                           MDIO_REG_BANK_COMBO_IEEE0,
5093                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5094
5095         /* Program speed
5096          *  - needed only if the speed is greater than 1G (2.5G or 10G)
5097          */
5098         CL22_RD_OVER_CL45(bp, phy,
5099                           MDIO_REG_BANK_SERDES_DIGITAL,
5100                           MDIO_SERDES_DIGITAL_MISC1, &reg_val);
5101         /* clearing the speed value before setting the right speed */
5102         DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5103
5104         reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
5105                      MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5106
5107         if (!((vars->line_speed == SPEED_1000) ||
5108               (vars->line_speed == SPEED_100) ||
5109               (vars->line_speed == SPEED_10))) {
5110
5111                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
5112                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5113                 if (vars->line_speed == SPEED_10000)
5114                         reg_val |=
5115                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5116         }
5117
5118         CL22_WR_OVER_CL45(bp, phy,
5119                           MDIO_REG_BANK_SERDES_DIGITAL,
5120                           MDIO_SERDES_DIGITAL_MISC1, reg_val);
5121
5122 }
5123
5124 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
5125                                               struct link_params *params)
5126 {
5127         struct bnx2x *bp = params->bp;
5128         u16 val = 0;
5129
5130         /* set extended capabilities */
5131         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
5132                 val |= MDIO_OVER_1G_UP1_2_5G;
5133         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5134                 val |= MDIO_OVER_1G_UP1_10G;
5135         CL22_WR_OVER_CL45(bp, phy,
5136                           MDIO_REG_BANK_OVER_1G,
5137                           MDIO_OVER_1G_UP1, val);
5138
5139         CL22_WR_OVER_CL45(bp, phy,
5140                           MDIO_REG_BANK_OVER_1G,
5141                           MDIO_OVER_1G_UP3, 0x400);
5142 }
5143
5144 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
5145                                               struct link_params *params,
5146                                               u16 ieee_fc)
5147 {
5148         struct bnx2x *bp = params->bp;
5149         u16 val;
5150         /* for AN, we are always publishing full duplex */
5151
5152         CL22_WR_OVER_CL45(bp, phy,
5153                           MDIO_REG_BANK_COMBO_IEEE0,
5154                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
5155         CL22_RD_OVER_CL45(bp, phy,
5156                           MDIO_REG_BANK_CL73_IEEEB1,
5157                           MDIO_CL73_IEEEB1_AN_ADV1, &val);
5158         val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
5159         val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
5160         CL22_WR_OVER_CL45(bp, phy,
5161                           MDIO_REG_BANK_CL73_IEEEB1,
5162                           MDIO_CL73_IEEEB1_AN_ADV1, val);
5163 }
5164
5165 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
5166                                   struct link_params *params,
5167                                   u8 enable_cl73)
5168 {
5169         struct bnx2x *bp = params->bp;
5170         u16 mii_control;
5171
5172         DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
5173         /* Enable and restart BAM/CL37 aneg */
5174
5175         if (enable_cl73) {
5176                 CL22_RD_OVER_CL45(bp, phy,
5177                                   MDIO_REG_BANK_CL73_IEEEB0,
5178                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5179                                   &mii_control);
5180
5181                 CL22_WR_OVER_CL45(bp, phy,
5182                                   MDIO_REG_BANK_CL73_IEEEB0,
5183                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5184                                   (mii_control |
5185                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5186                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5187         } else {
5188
5189                 CL22_RD_OVER_CL45(bp, phy,
5190                                   MDIO_REG_BANK_COMBO_IEEE0,
5191                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5192                                   &mii_control);
5193                 DP(NETIF_MSG_LINK,
5194                          "bnx2x_restart_autoneg mii_control before = 0x%x\n",
5195                          mii_control);
5196                 CL22_WR_OVER_CL45(bp, phy,
5197                                   MDIO_REG_BANK_COMBO_IEEE0,
5198                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5199                                   (mii_control |
5200                                    MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5201                                    MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
5202         }
5203 }
5204
5205 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5206                                            struct link_params *params,
5207                                            struct link_vars *vars)
5208 {
5209         struct bnx2x *bp = params->bp;
5210         u16 control1;
5211
5212         /* in SGMII mode, the unicore is always slave */
5213
5214         CL22_RD_OVER_CL45(bp, phy,
5215                           MDIO_REG_BANK_SERDES_DIGITAL,
5216                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5217                           &control1);
5218         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
5219         /* set sgmii mode (and not fiber) */
5220         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
5221                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5222                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
5223         CL22_WR_OVER_CL45(bp, phy,
5224                           MDIO_REG_BANK_SERDES_DIGITAL,
5225                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5226                           control1);
5227
5228         /* if forced speed */
5229         if (!(vars->line_speed == SPEED_AUTO_NEG)) {
5230                 /* set speed, disable autoneg */
5231                 u16 mii_control;
5232
5233                 CL22_RD_OVER_CL45(bp, phy,
5234                                   MDIO_REG_BANK_COMBO_IEEE0,
5235                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5236                                   &mii_control);
5237                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5238                                  MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5239                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5240
5241                 switch (vars->line_speed) {
5242                 case SPEED_100:
5243                         mii_control |=
5244                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5245                         break;
5246                 case SPEED_1000:
5247                         mii_control |=
5248                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5249                         break;
5250                 case SPEED_10:
5251                         /* there is nothing to set for 10M */
5252                         break;
5253                 default:
5254                         /* invalid speed for SGMII */
5255                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5256                                   vars->line_speed);
5257                         break;
5258                 }
5259
5260                 /* setting the full duplex */
5261                 if (phy->req_duplex == DUPLEX_FULL)
5262                         mii_control |=
5263                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5264                 CL22_WR_OVER_CL45(bp, phy,
5265                                   MDIO_REG_BANK_COMBO_IEEE0,
5266                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5267                                   mii_control);
5268
5269         } else { /* AN mode */
5270                 /* enable and restart AN */
5271                 bnx2x_restart_autoneg(phy, params, 0);
5272         }
5273 }
5274
5275 /* Link management
5276  */
5277 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
5278                                              struct link_params *params)
5279 {
5280         struct bnx2x *bp = params->bp;
5281         u16 pd_10g, status2_1000x;
5282         if (phy->req_line_speed != SPEED_AUTO_NEG)
5283                 return 0;
5284         CL22_RD_OVER_CL45(bp, phy,
5285                           MDIO_REG_BANK_SERDES_DIGITAL,
5286                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5287                           &status2_1000x);
5288         CL22_RD_OVER_CL45(bp, phy,
5289                           MDIO_REG_BANK_SERDES_DIGITAL,
5290                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5291                           &status2_1000x);
5292         if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5293                 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5294                          params->port);
5295                 return 1;
5296         }
5297
5298         CL22_RD_OVER_CL45(bp, phy,
5299                           MDIO_REG_BANK_10G_PARALLEL_DETECT,
5300                           MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5301                           &pd_10g);
5302
5303         if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5304                 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5305                          params->port);
5306                 return 1;
5307         }
5308         return 0;
5309 }
5310
5311 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy,
5312                                 struct link_params *params,
5313                                 struct link_vars *vars,
5314                                 u32 gp_status)
5315 {
5316         u16 ld_pause;   /* local driver */
5317         u16 lp_pause;   /* link partner */
5318         u16 pause_result;
5319         struct bnx2x *bp = params->bp;
5320         if ((gp_status &
5321              (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5322               MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5323             (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5324              MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5325
5326                 CL22_RD_OVER_CL45(bp, phy,
5327                                   MDIO_REG_BANK_CL73_IEEEB1,
5328                                   MDIO_CL73_IEEEB1_AN_ADV1,
5329                                   &ld_pause);
5330                 CL22_RD_OVER_CL45(bp, phy,
5331                                   MDIO_REG_BANK_CL73_IEEEB1,
5332                                   MDIO_CL73_IEEEB1_AN_LP_ADV1,
5333                                   &lp_pause);
5334                 pause_result = (ld_pause &
5335                                 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
5336                 pause_result |= (lp_pause &
5337                                  MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
5338                 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result);
5339         } else {
5340                 CL22_RD_OVER_CL45(bp, phy,
5341                                   MDIO_REG_BANK_COMBO_IEEE0,
5342                                   MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5343                                   &ld_pause);
5344                 CL22_RD_OVER_CL45(bp, phy,
5345                         MDIO_REG_BANK_COMBO_IEEE0,
5346                         MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5347                         &lp_pause);
5348                 pause_result = (ld_pause &
5349                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5350                 pause_result |= (lp_pause &
5351                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5352                 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result);
5353         }
5354         bnx2x_pause_resolve(vars, pause_result);
5355
5356 }
5357
5358 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5359                                     struct link_params *params,
5360                                     struct link_vars *vars,
5361                                     u32 gp_status)
5362 {
5363         struct bnx2x *bp = params->bp;
5364         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5365
5366         /* resolve from gp_status in case of AN complete and not sgmii */
5367         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
5368                 /* Update the advertised flow-controled of LD/LP in AN */
5369                 if (phy->req_line_speed == SPEED_AUTO_NEG)
5370                         bnx2x_update_adv_fc(phy, params, vars, gp_status);
5371                 /* But set the flow-control result as the requested one */
5372                 vars->flow_ctrl = phy->req_flow_ctrl;
5373         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
5374                 vars->flow_ctrl = params->req_fc_auto_adv;
5375         else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5376                  (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5377                 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5378                         vars->flow_ctrl = params->req_fc_auto_adv;
5379                         return;
5380                 }
5381                 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5382         }
5383         DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5384 }
5385
5386 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5387                                          struct link_params *params)
5388 {
5389         struct bnx2x *bp = params->bp;
5390         u16 rx_status, ustat_val, cl37_fsm_received;
5391         DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5392         /* Step 1: Make sure signal is detected */
5393         CL22_RD_OVER_CL45(bp, phy,
5394                           MDIO_REG_BANK_RX0,
5395                           MDIO_RX0_RX_STATUS,
5396                           &rx_status);
5397         if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5398             (MDIO_RX0_RX_STATUS_SIGDET)) {
5399                 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5400                              "rx_status(0x80b0) = 0x%x\n", rx_status);
5401                 CL22_WR_OVER_CL45(bp, phy,
5402                                   MDIO_REG_BANK_CL73_IEEEB0,
5403                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5404                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5405                 return;
5406         }
5407         /* Step 2: Check CL73 state machine */
5408         CL22_RD_OVER_CL45(bp, phy,
5409                           MDIO_REG_BANK_CL73_USERB0,
5410                           MDIO_CL73_USERB0_CL73_USTAT1,
5411                           &ustat_val);
5412         if ((ustat_val &
5413              (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5414               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5415             (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5416               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5417                 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5418                              "ustat_val(0x8371) = 0x%x\n", ustat_val);
5419                 return;
5420         }
5421         /* Step 3: Check CL37 Message Pages received to indicate LP
5422          * supports only CL37
5423          */
5424         CL22_RD_OVER_CL45(bp, phy,
5425                           MDIO_REG_BANK_REMOTE_PHY,
5426                           MDIO_REMOTE_PHY_MISC_RX_STATUS,
5427                           &cl37_fsm_received);
5428         if ((cl37_fsm_received &
5429              (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5430              MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5431             (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5432               MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5433                 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5434                              "misc_rx_status(0x8330) = 0x%x\n",
5435                          cl37_fsm_received);
5436                 return;
5437         }
5438         /* The combined cl37/cl73 fsm state information indicating that
5439          * we are connected to a device which does not support cl73, but
5440          * does support cl37 BAM. In this case we disable cl73 and
5441          * restart cl37 auto-neg
5442          */
5443
5444         /* Disable CL73 */
5445         CL22_WR_OVER_CL45(bp, phy,
5446                           MDIO_REG_BANK_CL73_IEEEB0,
5447                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5448                           0);
5449         /* Restart CL37 autoneg */
5450         bnx2x_restart_autoneg(phy, params, 0);
5451         DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5452 }
5453
5454 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5455                                   struct link_params *params,
5456                                   struct link_vars *vars,
5457                                   u32 gp_status)
5458 {
5459         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5460                 vars->link_status |=
5461                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5462
5463         if (bnx2x_direct_parallel_detect_used(phy, params))
5464                 vars->link_status |=
5465                         LINK_STATUS_PARALLEL_DETECTION_USED;
5466 }
5467 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5468                                      struct link_params *params,
5469                                       struct link_vars *vars,
5470                                       u16 is_link_up,
5471                                       u16 speed_mask,
5472                                       u16 is_duplex)
5473 {
5474         struct bnx2x *bp = params->bp;
5475         if (phy->req_line_speed == SPEED_AUTO_NEG)
5476                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5477         if (is_link_up) {
5478                 DP(NETIF_MSG_LINK, "phy link up\n");
5479
5480                 vars->phy_link_up = 1;
5481                 vars->link_status |= LINK_STATUS_LINK_UP;
5482
5483                 switch (speed_mask) {
5484                 case GP_STATUS_10M:
5485                         vars->line_speed = SPEED_10;
5486                         if (vars->duplex == DUPLEX_FULL)
5487                                 vars->link_status |= LINK_10TFD;
5488                         else
5489                                 vars->link_status |= LINK_10THD;
5490                         break;
5491
5492                 case GP_STATUS_100M:
5493                         vars->line_speed = SPEED_100;
5494                         if (vars->duplex == DUPLEX_FULL)
5495                                 vars->link_status |= LINK_100TXFD;
5496                         else
5497                                 vars->link_status |= LINK_100TXHD;
5498                         break;
5499
5500                 case GP_STATUS_1G:
5501                 case GP_STATUS_1G_KX:
5502                         vars->line_speed = SPEED_1000;
5503                         if (vars->duplex == DUPLEX_FULL)
5504                                 vars->link_status |= LINK_1000TFD;
5505                         else
5506                                 vars->link_status |= LINK_1000THD;
5507                         break;
5508
5509                 case GP_STATUS_2_5G:
5510                         vars->line_speed = SPEED_2500;
5511                         if (vars->duplex == DUPLEX_FULL)
5512                                 vars->link_status |= LINK_2500TFD;
5513                         else
5514                                 vars->link_status |= LINK_2500THD;
5515                         break;
5516
5517                 case GP_STATUS_5G:
5518                 case GP_STATUS_6G:
5519                         DP(NETIF_MSG_LINK,
5520                                  "link speed unsupported  gp_status 0x%x\n",
5521                                   speed_mask);
5522                         return -EINVAL;
5523
5524                 case GP_STATUS_10G_KX4:
5525                 case GP_STATUS_10G_HIG:
5526                 case GP_STATUS_10G_CX4:
5527                 case GP_STATUS_10G_KR:
5528                 case GP_STATUS_10G_SFI:
5529                 case GP_STATUS_10G_XFI:
5530                         vars->line_speed = SPEED_10000;
5531                         vars->link_status |= LINK_10GTFD;
5532                         break;
5533                 case GP_STATUS_20G_DXGXS:
5534                         vars->line_speed = SPEED_20000;
5535                         vars->link_status |= LINK_20GTFD;
5536                         break;
5537                 default:
5538                         DP(NETIF_MSG_LINK,
5539                                   "link speed unsupported gp_status 0x%x\n",
5540                                   speed_mask);
5541                         return -EINVAL;
5542                 }
5543         } else { /* link_down */
5544                 DP(NETIF_MSG_LINK, "phy link down\n");
5545
5546                 vars->phy_link_up = 0;
5547
5548                 vars->duplex = DUPLEX_FULL;
5549                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5550                 vars->mac_type = MAC_TYPE_NONE;
5551         }
5552         DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5553                     vars->phy_link_up, vars->line_speed);
5554         return 0;
5555 }
5556
5557 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5558                                       struct link_params *params,
5559                                       struct link_vars *vars)
5560 {
5561         struct bnx2x *bp = params->bp;
5562
5563         u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5564         int rc = 0;
5565
5566         /* Read gp_status */
5567         CL22_RD_OVER_CL45(bp, phy,
5568                           MDIO_REG_BANK_GP_STATUS,
5569                           MDIO_GP_STATUS_TOP_AN_STATUS1,
5570                           &gp_status);
5571         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5572                 duplex = DUPLEX_FULL;
5573         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5574                 link_up = 1;
5575         speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5576         DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5577                        gp_status, link_up, speed_mask);
5578         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5579                                          duplex);
5580         if (rc == -EINVAL)
5581                 return rc;
5582
5583         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5584                 if (SINGLE_MEDIA_DIRECT(params)) {
5585                         bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5586                         if (phy->req_line_speed == SPEED_AUTO_NEG)
5587                                 bnx2x_xgxs_an_resolve(phy, params, vars,
5588                                                       gp_status);
5589                 }
5590         } else { /* link_down */
5591                 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5592                     SINGLE_MEDIA_DIRECT(params)) {
5593                         /* Check signal is detected */
5594                         bnx2x_check_fallback_to_cl37(phy, params);
5595                 }
5596         }
5597
5598         /* Read LP advertised speeds*/
5599         if (SINGLE_MEDIA_DIRECT(params) &&
5600             (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
5601                 u16 val;
5602
5603                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1,
5604                                   MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
5605
5606                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5607                         vars->link_status |=
5608                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5609                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5610                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5611                         vars->link_status |=
5612                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5613
5614                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G,
5615                                   MDIO_OVER_1G_LP_UP1, &val);
5616
5617                 if (val & MDIO_OVER_1G_UP1_2_5G)
5618                         vars->link_status |=
5619                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5620                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5621                         vars->link_status |=
5622                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5623         }
5624
5625         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5626                    vars->duplex, vars->flow_ctrl, vars->link_status);
5627         return rc;
5628 }
5629
5630 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5631                                      struct link_params *params,
5632                                      struct link_vars *vars)
5633 {
5634         struct bnx2x *bp = params->bp;
5635         u8 lane;
5636         u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5637         int rc = 0;
5638         lane = bnx2x_get_warpcore_lane(phy, params);
5639         /* Read gp_status */
5640         if (phy->req_line_speed > SPEED_10000) {
5641                 u16 temp_link_up;
5642                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5643                                 1, &temp_link_up);
5644                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5645                                 1, &link_up);
5646                 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5647                                temp_link_up, link_up);
5648                 link_up &= (1<<2);
5649                 if (link_up)
5650                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5651         } else {
5652                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5653                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);
5654                 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5655                 /* Check for either KR or generic link up. */
5656                 gp_status1 = ((gp_status1 >> 8) & 0xf) |
5657                         ((gp_status1 >> 12) & 0xf);
5658                 link_up = gp_status1 & (1 << lane);
5659                 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5660                         u16 pd, gp_status4;
5661                         if (phy->req_line_speed == SPEED_AUTO_NEG) {
5662                                 /* Check Autoneg complete */
5663                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5664                                                 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5665                                                 &gp_status4);
5666                                 if (gp_status4 & ((1<<12)<<lane))
5667                                         vars->link_status |=
5668                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5669
5670                                 /* Check parallel detect used */
5671                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5672                                                 MDIO_WC_REG_PAR_DET_10G_STATUS,
5673                                                 &pd);
5674                                 if (pd & (1<<15))
5675                                         vars->link_status |=
5676                                         LINK_STATUS_PARALLEL_DETECTION_USED;
5677                         }
5678                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5679                 }
5680         }
5681
5682         if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
5683             SINGLE_MEDIA_DIRECT(params)) {
5684                 u16 val;
5685
5686                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5687                                 MDIO_AN_REG_LP_AUTO_NEG2, &val);
5688
5689                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5690                         vars->link_status |=
5691                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5692                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5693                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5694                         vars->link_status |=
5695                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5696
5697                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5698                                 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
5699
5700                 if (val & MDIO_OVER_1G_UP1_2_5G)
5701                         vars->link_status |=
5702                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5703                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5704                         vars->link_status |=
5705                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5706
5707         }
5708
5709
5710         if (lane < 2) {
5711                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5712                                 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5713         } else {
5714                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5715                                 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5716         }
5717         DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5718
5719         if ((lane & 1) == 0)
5720                 gp_speed <<= 8;
5721         gp_speed &= 0x3f00;
5722
5723
5724         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5725                                          duplex);
5726
5727         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5728                    vars->duplex, vars->flow_ctrl, vars->link_status);
5729         return rc;
5730 }
5731 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5732 {
5733         struct bnx2x *bp = params->bp;
5734         struct bnx2x_phy *phy = &params->phy[INT_PHY];
5735         u16 lp_up2;
5736         u16 tx_driver;
5737         u16 bank;
5738
5739         /* read precomp */
5740         CL22_RD_OVER_CL45(bp, phy,
5741                           MDIO_REG_BANK_OVER_1G,
5742                           MDIO_OVER_1G_LP_UP2, &lp_up2);
5743
5744         /* bits [10:7] at lp_up2, positioned at [15:12] */
5745         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5746                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5747                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5748
5749         if (lp_up2 == 0)
5750                 return;
5751
5752         for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5753               bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5754                 CL22_RD_OVER_CL45(bp, phy,
5755                                   bank,
5756                                   MDIO_TX0_TX_DRIVER, &tx_driver);
5757
5758                 /* replace tx_driver bits [15:12] */
5759                 if (lp_up2 !=
5760                     (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5761                         tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5762                         tx_driver |= lp_up2;
5763                         CL22_WR_OVER_CL45(bp, phy,
5764                                           bank,
5765                                           MDIO_TX0_TX_DRIVER, tx_driver);
5766                 }
5767         }
5768 }
5769
5770 static int bnx2x_emac_program(struct link_params *params,
5771                               struct link_vars *vars)
5772 {
5773         struct bnx2x *bp = params->bp;
5774         u8 port = params->port;
5775         u16 mode = 0;
5776
5777         DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5778         bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5779                        EMAC_REG_EMAC_MODE,
5780                        (EMAC_MODE_25G_MODE |
5781                         EMAC_MODE_PORT_MII_10M |
5782                         EMAC_MODE_HALF_DUPLEX));
5783         switch (vars->line_speed) {
5784         case SPEED_10:
5785                 mode |= EMAC_MODE_PORT_MII_10M;
5786                 break;
5787
5788         case SPEED_100:
5789                 mode |= EMAC_MODE_PORT_MII;
5790                 break;
5791
5792         case SPEED_1000:
5793                 mode |= EMAC_MODE_PORT_GMII;
5794                 break;
5795
5796         case SPEED_2500:
5797                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5798                 break;
5799
5800         default:
5801                 /* 10G not valid for EMAC */
5802                 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5803                            vars->line_speed);
5804                 return -EINVAL;
5805         }
5806
5807         if (vars->duplex == DUPLEX_HALF)
5808                 mode |= EMAC_MODE_HALF_DUPLEX;
5809         bnx2x_bits_en(bp,
5810                       GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5811                       mode);
5812
5813         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5814         return 0;
5815 }
5816
5817 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5818                                   struct link_params *params)
5819 {
5820
5821         u16 bank, i = 0;
5822         struct bnx2x *bp = params->bp;
5823
5824         for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5825               bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5826                         CL22_WR_OVER_CL45(bp, phy,
5827                                           bank,
5828                                           MDIO_RX0_RX_EQ_BOOST,
5829                                           phy->rx_preemphasis[i]);
5830         }
5831
5832         for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5833                       bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5834                         CL22_WR_OVER_CL45(bp, phy,
5835                                           bank,
5836                                           MDIO_TX0_TX_DRIVER,
5837                                           phy->tx_preemphasis[i]);
5838         }
5839 }
5840
5841 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5842                                    struct link_params *params,
5843                                    struct link_vars *vars)
5844 {
5845         struct bnx2x *bp = params->bp;
5846         u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5847                           (params->loopback_mode == LOOPBACK_XGXS));
5848         if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5849                 if (SINGLE_MEDIA_DIRECT(params) &&
5850                     (params->feature_config_flags &
5851                      FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5852                         bnx2x_set_preemphasis(phy, params);
5853
5854                 /* forced speed requested? */
5855                 if (vars->line_speed != SPEED_AUTO_NEG ||
5856                     (SINGLE_MEDIA_DIRECT(params) &&
5857                      params->loopback_mode == LOOPBACK_EXT)) {
5858                         DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5859
5860                         /* disable autoneg */
5861                         bnx2x_set_autoneg(phy, params, vars, 0);
5862
5863                         /* program speed and duplex */
5864                         bnx2x_program_serdes(phy, params, vars);
5865
5866                 } else { /* AN_mode */
5867                         DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5868
5869                         /* AN enabled */
5870                         bnx2x_set_brcm_cl37_advertisement(phy, params);
5871
5872                         /* program duplex & pause advertisement (for aneg) */
5873                         bnx2x_set_ieee_aneg_advertisement(phy, params,
5874                                                           vars->ieee_fc);
5875
5876                         /* enable autoneg */
5877                         bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5878
5879                         /* enable and restart AN */
5880                         bnx2x_restart_autoneg(phy, params, enable_cl73);
5881                 }
5882
5883         } else { /* SGMII mode */
5884                 DP(NETIF_MSG_LINK, "SGMII\n");
5885
5886                 bnx2x_initialize_sgmii_process(phy, params, vars);
5887         }
5888 }
5889
5890 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5891                           struct link_params *params,
5892                           struct link_vars *vars)
5893 {
5894         int rc;
5895         vars->phy_flags |= PHY_XGXS_FLAG;
5896         if ((phy->req_line_speed &&
5897              ((phy->req_line_speed == SPEED_100) ||
5898               (phy->req_line_speed == SPEED_10))) ||
5899             (!phy->req_line_speed &&
5900              (phy->speed_cap_mask >=
5901               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5902              (phy->speed_cap_mask <
5903               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5904             (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5905                 vars->phy_flags |= PHY_SGMII_FLAG;
5906         else
5907                 vars->phy_flags &= ~PHY_SGMII_FLAG;
5908
5909         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5910         bnx2x_set_aer_mmd(params, phy);
5911         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5912                 bnx2x_set_master_ln(params, phy);
5913
5914         rc = bnx2x_reset_unicore(params, phy, 0);
5915         /* reset the SerDes and wait for reset bit return low */
5916         if (rc != 0)
5917                 return rc;
5918
5919         bnx2x_set_aer_mmd(params, phy);
5920         /* setting the masterLn_def again after the reset */
5921         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5922                 bnx2x_set_master_ln(params, phy);
5923                 bnx2x_set_swap_lanes(params, phy);
5924         }
5925
5926         return rc;
5927 }
5928
5929 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
5930                                      struct bnx2x_phy *phy,
5931                                      struct link_params *params)
5932 {
5933         u16 cnt, ctrl;
5934         /* Wait for soft reset to get cleared up to 1 sec */
5935         for (cnt = 0; cnt < 1000; cnt++) {
5936                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
5937                         bnx2x_cl22_read(bp, phy,
5938                                 MDIO_PMA_REG_CTRL, &ctrl);
5939                 else
5940                         bnx2x_cl45_read(bp, phy,
5941                                 MDIO_PMA_DEVAD,
5942                                 MDIO_PMA_REG_CTRL, &ctrl);
5943                 if (!(ctrl & (1<<15)))
5944                         break;
5945                 msleep(1);
5946         }
5947
5948         if (cnt == 1000)
5949                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
5950                                       " Port %d\n",
5951                          params->port);
5952         DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
5953         return cnt;
5954 }
5955
5956 static void bnx2x_link_int_enable(struct link_params *params)
5957 {
5958         u8 port = params->port;
5959         u32 mask;
5960         struct bnx2x *bp = params->bp;
5961
5962         /* Setting the status to report on link up for either XGXS or SerDes */
5963         if (CHIP_IS_E3(bp)) {
5964                 mask = NIG_MASK_XGXS0_LINK_STATUS;
5965                 if (!(SINGLE_MEDIA_DIRECT(params)))
5966                         mask |= NIG_MASK_MI_INT;
5967         } else if (params->switch_cfg == SWITCH_CFG_10G) {
5968                 mask = (NIG_MASK_XGXS0_LINK10G |
5969                         NIG_MASK_XGXS0_LINK_STATUS);
5970                 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5971                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5972                         params->phy[INT_PHY].type !=
5973                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5974                         mask |= NIG_MASK_MI_INT;
5975                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
5976                 }
5977
5978         } else { /* SerDes */
5979                 mask = NIG_MASK_SERDES0_LINK_STATUS;
5980                 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
5981                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5982                         params->phy[INT_PHY].type !=
5983                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
5984                         mask |= NIG_MASK_MI_INT;
5985                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
5986                 }
5987         }
5988         bnx2x_bits_en(bp,
5989                       NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
5990                       mask);
5991
5992         DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
5993                  (params->switch_cfg == SWITCH_CFG_10G),
5994                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
5995         DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
5996                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
5997                  REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
5998                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
5999         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6000            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6001            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6002 }
6003
6004 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
6005                                      u8 exp_mi_int)
6006 {
6007         u32 latch_status = 0;
6008
6009         /* Disable the MI INT ( external phy int ) by writing 1 to the
6010          * status register. Link down indication is high-active-signal,
6011          * so in this case we need to write the status to clear the XOR
6012          */
6013         /* Read Latched signals */
6014         latch_status = REG_RD(bp,
6015                                     NIG_REG_LATCH_STATUS_0 + port*8);
6016         DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
6017         /* Handle only those with latched-signal=up.*/
6018         if (exp_mi_int)
6019                 bnx2x_bits_en(bp,
6020                               NIG_REG_STATUS_INTERRUPT_PORT0
6021                               + port*4,
6022                               NIG_STATUS_EMAC0_MI_INT);
6023         else
6024                 bnx2x_bits_dis(bp,
6025                                NIG_REG_STATUS_INTERRUPT_PORT0
6026                                + port*4,
6027                                NIG_STATUS_EMAC0_MI_INT);
6028
6029         if (latch_status & 1) {
6030
6031                 /* For all latched-signal=up : Re-Arm Latch signals */
6032                 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
6033                        (latch_status & 0xfffe) | (latch_status & 1));
6034         }
6035         /* For all latched-signal=up,Write original_signal to status */
6036 }
6037
6038 static void bnx2x_link_int_ack(struct link_params *params,
6039                                struct link_vars *vars, u8 is_10g_plus)
6040 {
6041         struct bnx2x *bp = params->bp;
6042         u8 port = params->port;
6043         u32 mask;
6044         /* First reset all status we assume only one line will be
6045          * change at a time
6046          */
6047         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6048                        (NIG_STATUS_XGXS0_LINK10G |
6049                         NIG_STATUS_XGXS0_LINK_STATUS |
6050                         NIG_STATUS_SERDES0_LINK_STATUS));
6051         if (vars->phy_link_up) {
6052                 if (USES_WARPCORE(bp))
6053                         mask = NIG_STATUS_XGXS0_LINK_STATUS;
6054                 else {
6055                         if (is_10g_plus)
6056                                 mask = NIG_STATUS_XGXS0_LINK10G;
6057                         else if (params->switch_cfg == SWITCH_CFG_10G) {
6058                                 /* Disable the link interrupt by writing 1 to
6059                                  * the relevant lane in the status register
6060                                  */
6061                                 u32 ser_lane =
6062                                         ((params->lane_config &
6063                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6064                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
6065                                 mask = ((1 << ser_lane) <<
6066                                        NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
6067                         } else
6068                                 mask = NIG_STATUS_SERDES0_LINK_STATUS;
6069                 }
6070                 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
6071                                mask);
6072                 bnx2x_bits_en(bp,
6073                               NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6074                               mask);
6075         }
6076 }
6077
6078 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
6079 {
6080         u8 *str_ptr = str;
6081         u32 mask = 0xf0000000;
6082         u8 shift = 8*4;
6083         u8 digit;
6084         u8 remove_leading_zeros = 1;
6085         if (*len < 10) {
6086                 /* Need more than 10chars for this format */
6087                 *str_ptr = '\0';
6088                 (*len)--;
6089                 return -EINVAL;
6090         }
6091         while (shift > 0) {
6092
6093                 shift -= 4;
6094                 digit = ((num & mask) >> shift);
6095                 if (digit == 0 && remove_leading_zeros) {
6096                         mask = mask >> 4;
6097                         continue;
6098                 } else if (digit < 0xa)
6099                         *str_ptr = digit + '0';
6100                 else
6101                         *str_ptr = digit - 0xa + 'a';
6102                 remove_leading_zeros = 0;
6103                 str_ptr++;
6104                 (*len)--;
6105                 mask = mask >> 4;
6106                 if (shift == 4*4) {
6107                         *str_ptr = '.';
6108                         str_ptr++;
6109                         (*len)--;
6110                         remove_leading_zeros = 1;
6111                 }
6112         }
6113         return 0;
6114 }
6115
6116
6117 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6118 {
6119         str[0] = '\0';
6120         (*len)--;
6121         return 0;
6122 }
6123
6124 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
6125                                  u16 len)
6126 {
6127         struct bnx2x *bp;
6128         u32 spirom_ver = 0;
6129         int status = 0;
6130         u8 *ver_p = version;
6131         u16 remain_len = len;
6132         if (version == NULL || params == NULL)
6133                 return -EINVAL;
6134         bp = params->bp;
6135
6136         /* Extract first external phy*/
6137         version[0] = '\0';
6138         spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
6139
6140         if (params->phy[EXT_PHY1].format_fw_ver) {
6141                 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
6142                                                               ver_p,
6143                                                               &remain_len);
6144                 ver_p += (len - remain_len);
6145         }
6146         if ((params->num_phys == MAX_PHYS) &&
6147             (params->phy[EXT_PHY2].ver_addr != 0)) {
6148                 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
6149                 if (params->phy[EXT_PHY2].format_fw_ver) {
6150                         *ver_p = '/';
6151                         ver_p++;
6152                         remain_len--;
6153                         status |= params->phy[EXT_PHY2].format_fw_ver(
6154                                 spirom_ver,
6155                                 ver_p,
6156                                 &remain_len);
6157                         ver_p = version + (len - remain_len);
6158                 }
6159         }
6160         *ver_p = '\0';
6161         return status;
6162 }
6163
6164 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
6165                                     struct link_params *params)
6166 {
6167         u8 port = params->port;
6168         struct bnx2x *bp = params->bp;
6169
6170         if (phy->req_line_speed != SPEED_1000) {
6171                 u32 md_devad = 0;
6172
6173                 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
6174
6175                 if (!CHIP_IS_E3(bp)) {
6176                         /* change the uni_phy_addr in the nig */
6177                         md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
6178                                                port*0x18));
6179
6180                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6181                                0x5);
6182                 }
6183
6184                 bnx2x_cl45_write(bp, phy,
6185                                  5,
6186                                  (MDIO_REG_BANK_AER_BLOCK +
6187                                   (MDIO_AER_BLOCK_AER_REG & 0xf)),
6188                                  0x2800);
6189
6190                 bnx2x_cl45_write(bp, phy,
6191                                  5,
6192                                  (MDIO_REG_BANK_CL73_IEEEB0 +
6193                                   (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
6194                                  0x6041);
6195                 msleep(200);
6196                 /* set aer mmd back */
6197                 bnx2x_set_aer_mmd(params, phy);
6198
6199                 if (!CHIP_IS_E3(bp)) {
6200                         /* and md_devad */
6201                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6202                                md_devad);
6203                 }
6204         } else {
6205                 u16 mii_ctrl;
6206                 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
6207                 bnx2x_cl45_read(bp, phy, 5,
6208                                 (MDIO_REG_BANK_COMBO_IEEE0 +
6209                                 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6210                                 &mii_ctrl);
6211                 bnx2x_cl45_write(bp, phy, 5,
6212                                  (MDIO_REG_BANK_COMBO_IEEE0 +
6213                                  (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6214                                  mii_ctrl |
6215                                  MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6216         }
6217 }
6218
6219 int bnx2x_set_led(struct link_params *params,
6220                   struct link_vars *vars, u8 mode, u32 speed)
6221 {
6222         u8 port = params->port;
6223         u16 hw_led_mode = params->hw_led_mode;
6224         int rc = 0;
6225         u8 phy_idx;
6226         u32 tmp;
6227         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6228         struct bnx2x *bp = params->bp;
6229         DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
6230         DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
6231                  speed, hw_led_mode);
6232         /* In case */
6233         for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
6234                 if (params->phy[phy_idx].set_link_led) {
6235                         params->phy[phy_idx].set_link_led(
6236                                 &params->phy[phy_idx], params, mode);
6237                 }
6238         }
6239
6240         switch (mode) {
6241         case LED_MODE_FRONT_PANEL_OFF:
6242         case LED_MODE_OFF:
6243                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
6244                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6245                        SHARED_HW_CFG_LED_MAC1);
6246
6247                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6248                 if (params->phy[EXT_PHY1].type ==
6249                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6250                         tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
6251                                 EMAC_LED_100MB_OVERRIDE |
6252                                 EMAC_LED_10MB_OVERRIDE);
6253                 else
6254                         tmp |= EMAC_LED_OVERRIDE;
6255
6256                 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp);
6257                 break;
6258
6259         case LED_MODE_OPER:
6260                 /* For all other phys, OPER mode is same as ON, so in case
6261                  * link is down, do nothing
6262                  */
6263                 if (!vars->link_up)
6264                         break;
6265         case LED_MODE_ON:
6266                 if (((params->phy[EXT_PHY1].type ==
6267                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6268                          (params->phy[EXT_PHY1].type ==
6269                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6270                     CHIP_IS_E2(bp) && params->num_phys == 2) {
6271                         /* This is a work-around for E2+8727 Configurations */
6272                         if (mode == LED_MODE_ON ||
6273                                 speed == SPEED_10000){
6274                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6275                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6276
6277                                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6278                                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6279                                         (tmp | EMAC_LED_OVERRIDE));
6280                                 /* Return here without enabling traffic
6281                                  * LED blink and setting rate in ON mode.
6282                                  * In oper mode, enabling LED blink
6283                                  * and setting rate is needed.
6284                                  */
6285                                 if (mode == LED_MODE_ON)
6286                                         return rc;
6287                         }
6288                 } else if (SINGLE_MEDIA_DIRECT(params)) {
6289                         /* This is a work-around for HW issue found when link
6290                          * is up in CL73
6291                          */
6292                         if ((!CHIP_IS_E3(bp)) ||
6293                             (CHIP_IS_E3(bp) &&
6294                              mode == LED_MODE_ON))
6295                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6296
6297                         if (CHIP_IS_E1x(bp) ||
6298                             CHIP_IS_E2(bp) ||
6299                             (mode == LED_MODE_ON))
6300                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6301                         else
6302                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6303                                        hw_led_mode);
6304                 } else if ((params->phy[EXT_PHY1].type ==
6305                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6306                            (mode == LED_MODE_ON)) {
6307                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6308                         tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6309                         EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp |
6310                                 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE);
6311                         /* Break here; otherwise, it'll disable the
6312                          * intended override.
6313                          */
6314                         break;
6315                 } else
6316                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6317                                hw_led_mode);
6318
6319                 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
6320                 /* Set blinking rate to ~15.9Hz */
6321                 if (CHIP_IS_E3(bp))
6322                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6323                                LED_BLINK_RATE_VAL_E3);
6324                 else
6325                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6326                                LED_BLINK_RATE_VAL_E1X_E2);
6327                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
6328                        port*4, 1);
6329                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6330                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6331                         (tmp & (~EMAC_LED_OVERRIDE)));
6332
6333                 if (CHIP_IS_E1(bp) &&
6334                     ((speed == SPEED_2500) ||
6335                      (speed == SPEED_1000) ||
6336                      (speed == SPEED_100) ||
6337                      (speed == SPEED_10))) {
6338                         /* For speeds less than 10G LED scheme is different */
6339                         REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
6340                                + port*4, 1);
6341                         REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
6342                                port*4, 0);
6343                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
6344                                port*4, 1);
6345                 }
6346                 break;
6347
6348         default:
6349                 rc = -EINVAL;
6350                 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
6351                          mode);
6352                 break;
6353         }
6354         return rc;
6355
6356 }
6357
6358 /* This function comes to reflect the actual link state read DIRECTLY from the
6359  * HW
6360  */
6361 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
6362                     u8 is_serdes)
6363 {
6364         struct bnx2x *bp = params->bp;
6365         u16 gp_status = 0, phy_index = 0;
6366         u8 ext_phy_link_up = 0, serdes_phy_type;
6367         struct link_vars temp_vars;
6368         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
6369
6370         if (CHIP_IS_E3(bp)) {
6371                 u16 link_up;
6372                 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6373                     > SPEED_10000) {
6374                         /* Check 20G link */
6375                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6376                                         1, &link_up);
6377                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6378                                         1, &link_up);
6379                         link_up &= (1<<2);
6380                 } else {
6381                         /* Check 10G link and below*/
6382                         u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6383                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6384                                         MDIO_WC_REG_GP2_STATUS_GP_2_1,
6385                                         &gp_status);
6386                         gp_status = ((gp_status >> 8) & 0xf) |
6387                                 ((gp_status >> 12) & 0xf);
6388                         link_up = gp_status & (1 << lane);
6389                 }
6390                 if (!link_up)
6391                         return -ESRCH;
6392         } else {
6393                 CL22_RD_OVER_CL45(bp, int_phy,
6394                           MDIO_REG_BANK_GP_STATUS,
6395                           MDIO_GP_STATUS_TOP_AN_STATUS1,
6396                           &gp_status);
6397         /* link is up only if both local phy and external phy are up */
6398         if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6399                 return -ESRCH;
6400         }
6401         /* In XGXS loopback mode, do not check external PHY */
6402         if (params->loopback_mode == LOOPBACK_XGXS)
6403                 return 0;
6404
6405         switch (params->num_phys) {
6406         case 1:
6407                 /* No external PHY */
6408                 return 0;
6409         case 2:
6410                 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6411                         &params->phy[EXT_PHY1],
6412                         params, &temp_vars);
6413                 break;
6414         case 3: /* Dual Media */
6415                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6416                       phy_index++) {
6417                         serdes_phy_type = ((params->phy[phy_index].media_type ==
6418                                             ETH_PHY_SFP_FIBER) ||
6419                                            (params->phy[phy_index].media_type ==
6420                                             ETH_PHY_XFP_FIBER) ||
6421                                            (params->phy[phy_index].media_type ==
6422                                             ETH_PHY_DA_TWINAX));
6423
6424                         if (is_serdes != serdes_phy_type)
6425                                 continue;
6426                         if (params->phy[phy_index].read_status) {
6427                                 ext_phy_link_up |=
6428                                         params->phy[phy_index].read_status(
6429                                                 &params->phy[phy_index],
6430                                                 params, &temp_vars);
6431                         }
6432                 }
6433                 break;
6434         }
6435         if (ext_phy_link_up)
6436                 return 0;
6437         return -ESRCH;
6438 }
6439
6440 static int bnx2x_link_initialize(struct link_params *params,
6441                                  struct link_vars *vars)
6442 {
6443         int rc = 0;
6444         u8 phy_index, non_ext_phy;
6445         struct bnx2x *bp = params->bp;
6446         /* In case of external phy existence, the line speed would be the
6447          * line speed linked up by the external phy. In case it is direct
6448          * only, then the line_speed during initialization will be
6449          * equal to the req_line_speed
6450          */
6451         vars->line_speed = params->phy[INT_PHY].req_line_speed;
6452
6453         /* Initialize the internal phy in case this is a direct board
6454          * (no external phys), or this board has external phy which requires
6455          * to first.
6456          */
6457         if (!USES_WARPCORE(bp))
6458                 bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
6459         /* init ext phy and enable link state int */
6460         non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6461                        (params->loopback_mode == LOOPBACK_XGXS));
6462
6463         if (non_ext_phy ||
6464             (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6465             (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6466                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
6467                 if (vars->line_speed == SPEED_AUTO_NEG &&
6468                     (CHIP_IS_E1x(bp) ||
6469                      CHIP_IS_E2(bp)))
6470                         bnx2x_set_parallel_detection(phy, params);
6471                         if (params->phy[INT_PHY].config_init)
6472                                 params->phy[INT_PHY].config_init(phy,
6473                                                                  params,
6474                                                                  vars);
6475         }
6476
6477         /* Init external phy*/
6478         if (non_ext_phy) {
6479                 if (params->phy[INT_PHY].supported &
6480                     SUPPORTED_FIBRE)
6481                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6482         } else {
6483                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6484                       phy_index++) {
6485                         /* No need to initialize second phy in case of first
6486                          * phy only selection. In case of second phy, we do
6487                          * need to initialize the first phy, since they are
6488                          * connected.
6489                          */
6490                         if (params->phy[phy_index].supported &
6491                             SUPPORTED_FIBRE)
6492                                 vars->link_status |= LINK_STATUS_SERDES_LINK;
6493
6494                         if (phy_index == EXT_PHY2 &&
6495                             (bnx2x_phy_selection(params) ==
6496                              PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6497                                 DP(NETIF_MSG_LINK,
6498                                    "Not initializing second phy\n");
6499                                 continue;
6500                         }
6501                         params->phy[phy_index].config_init(
6502                                 &params->phy[phy_index],
6503                                 params, vars);
6504                 }
6505         }
6506         /* Reset the interrupt indication after phy was initialized */
6507         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6508                        params->port*4,
6509                        (NIG_STATUS_XGXS0_LINK10G |
6510                         NIG_STATUS_XGXS0_LINK_STATUS |
6511                         NIG_STATUS_SERDES0_LINK_STATUS |
6512                         NIG_MASK_MI_INT));
6513         return rc;
6514 }
6515
6516 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6517                                  struct link_params *params)
6518 {
6519         /* reset the SerDes/XGXS */
6520         REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6521                (0x1ff << (params->port*16)));
6522 }
6523
6524 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6525                                         struct link_params *params)
6526 {
6527         struct bnx2x *bp = params->bp;
6528         u8 gpio_port;
6529         /* HW reset */
6530         if (CHIP_IS_E2(bp))
6531                 gpio_port = BP_PATH(bp);
6532         else
6533                 gpio_port = params->port;
6534         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6535                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6536                        gpio_port);
6537         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6538                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6539                        gpio_port);
6540         DP(NETIF_MSG_LINK, "reset external PHY\n");
6541 }
6542
6543 static int bnx2x_update_link_down(struct link_params *params,
6544                                   struct link_vars *vars)
6545 {
6546         struct bnx2x *bp = params->bp;
6547         u8 port = params->port;
6548
6549         DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6550         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6551         vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6552         /* indicate no mac active */
6553         vars->mac_type = MAC_TYPE_NONE;
6554
6555         /* update shared memory */
6556         vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK |
6557                                LINK_STATUS_LINK_UP |
6558                                LINK_STATUS_PHYSICAL_LINK_FLAG |
6559                                LINK_STATUS_AUTO_NEGOTIATE_COMPLETE |
6560                                LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK |
6561                                LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK |
6562                                LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK |
6563                                LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE |
6564                                LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE);
6565         vars->line_speed = 0;
6566         bnx2x_update_mng(params, vars->link_status);
6567
6568         /* activate nig drain */
6569         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6570
6571         /* disable emac */
6572         if (!CHIP_IS_E3(bp))
6573                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6574
6575         msleep(10);
6576         /* reset BigMac/Xmac */
6577         if (CHIP_IS_E1x(bp) ||
6578             CHIP_IS_E2(bp)) {
6579                 bnx2x_bmac_rx_disable(bp, params->port);
6580                 REG_WR(bp, GRCBASE_MISC +
6581                        MISC_REGISTERS_RESET_REG_2_CLEAR,
6582                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6583         }
6584         if (CHIP_IS_E3(bp)) {
6585                 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
6586                        0);
6587                 REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 0);
6588                 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
6589                        0);
6590                 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
6591                                       SHMEM_EEE_ACTIVE_BIT);
6592
6593                 bnx2x_update_mng_eee(params, vars->eee_status);
6594                 bnx2x_xmac_disable(params);
6595                 bnx2x_umac_disable(params);
6596         }
6597
6598         return 0;
6599 }
6600
6601 static int bnx2x_update_link_up(struct link_params *params,
6602                                 struct link_vars *vars,
6603                                 u8 link_10g)
6604 {
6605         struct bnx2x *bp = params->bp;
6606         u8 phy_idx, port = params->port;
6607         int rc = 0;
6608
6609         vars->link_status |= (LINK_STATUS_LINK_UP |
6610                               LINK_STATUS_PHYSICAL_LINK_FLAG);
6611         vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6612
6613         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6614                 vars->link_status |=
6615                         LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6616
6617         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6618                 vars->link_status |=
6619                         LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6620         if (USES_WARPCORE(bp)) {
6621                 if (link_10g) {
6622                         if (bnx2x_xmac_enable(params, vars, 0) ==
6623                             -ESRCH) {
6624                                 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6625                                 vars->link_up = 0;
6626                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6627                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6628                         }
6629                 } else
6630                         bnx2x_umac_enable(params, vars, 0);
6631                 bnx2x_set_led(params, vars,
6632                               LED_MODE_OPER, vars->line_speed);
6633
6634                 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
6635                     (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
6636                         DP(NETIF_MSG_LINK, "Enabling LPI assertion\n");
6637                         REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
6638                                (params->port << 2), 1);
6639                         REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1);
6640                         REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 +
6641                                (params->port << 2), 0xfc20);
6642                 }
6643         }
6644         if ((CHIP_IS_E1x(bp) ||
6645              CHIP_IS_E2(bp))) {
6646                 if (link_10g) {
6647                         if (bnx2x_bmac_enable(params, vars, 0) ==
6648                             -ESRCH) {
6649                                 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6650                                 vars->link_up = 0;
6651                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6652                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6653                         }
6654
6655                         bnx2x_set_led(params, vars,
6656                                       LED_MODE_OPER, SPEED_10000);
6657                 } else {
6658                         rc = bnx2x_emac_program(params, vars);
6659                         bnx2x_emac_enable(params, vars, 0);
6660
6661                         /* AN complete? */
6662                         if ((vars->link_status &
6663                              LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6664                             && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6665                             SINGLE_MEDIA_DIRECT(params))
6666                                 bnx2x_set_gmii_tx_driver(params);
6667                 }
6668         }
6669
6670         /* PBF - link up */
6671         if (CHIP_IS_E1x(bp))
6672                 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6673                                        vars->line_speed);
6674
6675         /* disable drain */
6676         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6677
6678         /* update shared memory */
6679         bnx2x_update_mng(params, vars->link_status);
6680         bnx2x_update_mng_eee(params, vars->eee_status);
6681         /* Check remote fault */
6682         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
6683                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
6684                         bnx2x_check_half_open_conn(params, vars, 0);
6685                         break;
6686                 }
6687         }
6688         msleep(20);
6689         return rc;
6690 }
6691 /* The bnx2x_link_update function should be called upon link
6692  * interrupt.
6693  * Link is considered up as follows:
6694  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6695  *   to be up
6696  * - SINGLE_MEDIA - The link between the 577xx and the external
6697  *   phy (XGXS) need to up as well as the external link of the
6698  *   phy (PHY_EXT1)
6699  * - DUAL_MEDIA - The link between the 577xx and the first
6700  *   external phy needs to be up, and at least one of the 2
6701  *   external phy link must be up.
6702  */
6703 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6704 {
6705         struct bnx2x *bp = params->bp;
6706         struct link_vars phy_vars[MAX_PHYS];
6707         u8 port = params->port;
6708         u8 link_10g_plus, phy_index;
6709         u8 ext_phy_link_up = 0, cur_link_up;
6710         int rc = 0;
6711         u8 is_mi_int = 0;
6712         u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6713         u8 active_external_phy = INT_PHY;
6714         vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6715         for (phy_index = INT_PHY; phy_index < params->num_phys;
6716               phy_index++) {
6717                 phy_vars[phy_index].flow_ctrl = 0;
6718                 phy_vars[phy_index].link_status = 0;
6719                 phy_vars[phy_index].line_speed = 0;
6720                 phy_vars[phy_index].duplex = DUPLEX_FULL;
6721                 phy_vars[phy_index].phy_link_up = 0;
6722                 phy_vars[phy_index].link_up = 0;
6723                 phy_vars[phy_index].fault_detected = 0;
6724                 /* different consideration, since vars holds inner state */
6725                 phy_vars[phy_index].eee_status = vars->eee_status;
6726         }
6727
6728         if (USES_WARPCORE(bp))
6729                 bnx2x_set_aer_mmd(params, &params->phy[INT_PHY]);
6730
6731         DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6732                  port, (vars->phy_flags & PHY_XGXS_FLAG),
6733                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6734
6735         is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6736                                 port*0x18) > 0);
6737         DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6738                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6739                  is_mi_int,
6740                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6741
6742         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6743           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6744           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6745
6746         /* disable emac */
6747         if (!CHIP_IS_E3(bp))
6748                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6749
6750         /* Step 1:
6751          * Check external link change only for external phys, and apply
6752          * priority selection between them in case the link on both phys
6753          * is up. Note that instead of the common vars, a temporary
6754          * vars argument is used since each phy may have different link/
6755          * speed/duplex result
6756          */
6757         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6758               phy_index++) {
6759                 struct bnx2x_phy *phy = &params->phy[phy_index];
6760                 if (!phy->read_status)
6761                         continue;
6762                 /* Read link status and params of this ext phy */
6763                 cur_link_up = phy->read_status(phy, params,
6764                                                &phy_vars[phy_index]);
6765                 if (cur_link_up) {
6766                         DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6767                                    phy_index);
6768                 } else {
6769                         DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6770                                    phy_index);
6771                         continue;
6772                 }
6773
6774                 if (!ext_phy_link_up) {
6775                         ext_phy_link_up = 1;
6776                         active_external_phy = phy_index;
6777                 } else {
6778                         switch (bnx2x_phy_selection(params)) {
6779                         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6780                         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6781                         /* In this option, the first PHY makes sure to pass the
6782                          * traffic through itself only.
6783                          * Its not clear how to reset the link on the second phy
6784                          */
6785                                 active_external_phy = EXT_PHY1;
6786                                 break;
6787                         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6788                         /* In this option, the first PHY makes sure to pass the
6789                          * traffic through the second PHY.
6790                          */
6791                                 active_external_phy = EXT_PHY2;
6792                                 break;
6793                         default:
6794                         /* Link indication on both PHYs with the following cases
6795                          * is invalid:
6796                          * - FIRST_PHY means that second phy wasn't initialized,
6797                          * hence its link is expected to be down
6798                          * - SECOND_PHY means that first phy should not be able
6799                          * to link up by itself (using configuration)
6800                          * - DEFAULT should be overriden during initialiazation
6801                          */
6802                                 DP(NETIF_MSG_LINK, "Invalid link indication"
6803                                            "mpc=0x%x. DISABLING LINK !!!\n",
6804                                            params->multi_phy_config);
6805                                 ext_phy_link_up = 0;
6806                                 break;
6807                         }
6808                 }
6809         }
6810         prev_line_speed = vars->line_speed;
6811         /* Step 2:
6812          * Read the status of the internal phy. In case of
6813          * DIRECT_SINGLE_MEDIA board, this link is the external link,
6814          * otherwise this is the link between the 577xx and the first
6815          * external phy
6816          */
6817         if (params->phy[INT_PHY].read_status)
6818                 params->phy[INT_PHY].read_status(
6819                         &params->phy[INT_PHY],
6820                         params, vars);
6821         /* The INT_PHY flow control reside in the vars. This include the
6822          * case where the speed or flow control are not set to AUTO.
6823          * Otherwise, the active external phy flow control result is set
6824          * to the vars. The ext_phy_line_speed is needed to check if the
6825          * speed is different between the internal phy and external phy.
6826          * This case may be result of intermediate link speed change.
6827          */
6828         if (active_external_phy > INT_PHY) {
6829                 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6830                 /* Link speed is taken from the XGXS. AN and FC result from
6831                  * the external phy.
6832                  */
6833                 vars->link_status |= phy_vars[active_external_phy].link_status;
6834
6835                 /* if active_external_phy is first PHY and link is up - disable
6836                  * disable TX on second external PHY
6837                  */
6838                 if (active_external_phy == EXT_PHY1) {
6839                         if (params->phy[EXT_PHY2].phy_specific_func) {
6840                                 DP(NETIF_MSG_LINK,
6841                                    "Disabling TX on EXT_PHY2\n");
6842                                 params->phy[EXT_PHY2].phy_specific_func(
6843                                         &params->phy[EXT_PHY2],
6844                                         params, DISABLE_TX);
6845                         }
6846                 }
6847
6848                 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6849                 vars->duplex = phy_vars[active_external_phy].duplex;
6850                 if (params->phy[active_external_phy].supported &
6851                     SUPPORTED_FIBRE)
6852                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6853                 else
6854                         vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6855
6856                 vars->eee_status = phy_vars[active_external_phy].eee_status;
6857
6858                 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6859                            active_external_phy);
6860         }
6861
6862         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6863               phy_index++) {
6864                 if (params->phy[phy_index].flags &
6865                     FLAGS_REARM_LATCH_SIGNAL) {
6866                         bnx2x_rearm_latch_signal(bp, port,
6867                                                  phy_index ==
6868                                                  active_external_phy);
6869                         break;
6870                 }
6871         }
6872         DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6873                    " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6874                    vars->link_status, ext_phy_line_speed);
6875         /* Upon link speed change set the NIG into drain mode. Comes to
6876          * deals with possible FIFO glitch due to clk change when speed
6877          * is decreased without link down indicator
6878          */
6879
6880         if (vars->phy_link_up) {
6881                 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6882                     (ext_phy_line_speed != vars->line_speed)) {
6883                         DP(NETIF_MSG_LINK, "Internal link speed %d is"
6884                                    " different than the external"
6885                                    " link speed %d\n", vars->line_speed,
6886                                    ext_phy_line_speed);
6887                         vars->phy_link_up = 0;
6888                 } else if (prev_line_speed != vars->line_speed) {
6889                         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6890                                0);
6891                         msleep(1);
6892                 }
6893         }
6894
6895         /* anything 10 and over uses the bmac */
6896         link_10g_plus = (vars->line_speed >= SPEED_10000);
6897
6898         bnx2x_link_int_ack(params, vars, link_10g_plus);
6899
6900         /* In case external phy link is up, and internal link is down
6901          * (not initialized yet probably after link initialization, it
6902          * needs to be initialized.
6903          * Note that after link down-up as result of cable plug, the xgxs
6904          * link would probably become up again without the need
6905          * initialize it
6906          */
6907         if (!(SINGLE_MEDIA_DIRECT(params))) {
6908                 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6909                            " init_preceding = %d\n", ext_phy_link_up,
6910                            vars->phy_link_up,
6911                            params->phy[EXT_PHY1].flags &
6912                            FLAGS_INIT_XGXS_FIRST);
6913                 if (!(params->phy[EXT_PHY1].flags &
6914                       FLAGS_INIT_XGXS_FIRST)
6915                     && ext_phy_link_up && !vars->phy_link_up) {
6916                         vars->line_speed = ext_phy_line_speed;
6917                         if (vars->line_speed < SPEED_1000)
6918                                 vars->phy_flags |= PHY_SGMII_FLAG;
6919                         else
6920                                 vars->phy_flags &= ~PHY_SGMII_FLAG;
6921
6922                         if (params->phy[INT_PHY].config_init)
6923                                 params->phy[INT_PHY].config_init(
6924                                         &params->phy[INT_PHY], params,
6925                                                 vars);
6926                 }
6927         }
6928         /* Link is up only if both local phy and external phy (in case of
6929          * non-direct board) are up and no fault detected on active PHY.
6930          */
6931         vars->link_up = (vars->phy_link_up &&
6932                          (ext_phy_link_up ||
6933                           SINGLE_MEDIA_DIRECT(params)) &&
6934                          (phy_vars[active_external_phy].fault_detected == 0));
6935
6936         /* Update the PFC configuration in case it was changed */
6937         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
6938                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
6939         else
6940                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
6941
6942         if (vars->link_up)
6943                 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
6944         else
6945                 rc = bnx2x_update_link_down(params, vars);
6946
6947         /* Update MCP link status was changed */
6948         if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX)
6949                 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
6950
6951         return rc;
6952 }
6953
6954 /*****************************************************************************/
6955 /*                          External Phy section                             */
6956 /*****************************************************************************/
6957 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
6958 {
6959         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6960                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6961         msleep(1);
6962         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6963                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6964 }
6965
6966 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
6967                                       u32 spirom_ver, u32 ver_addr)
6968 {
6969         DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
6970                  (u16)(spirom_ver>>16), (u16)spirom_ver, port);
6971
6972         if (ver_addr)
6973                 REG_WR(bp, ver_addr, spirom_ver);
6974 }
6975
6976 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
6977                                       struct bnx2x_phy *phy,
6978                                       u8 port)
6979 {
6980         u16 fw_ver1, fw_ver2;
6981
6982         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6983                         MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6984         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6985                         MDIO_PMA_REG_ROM_VER2, &fw_ver2);
6986         bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
6987                                   phy->ver_addr);
6988 }
6989
6990 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
6991                                        struct bnx2x_phy *phy,
6992                                        struct link_vars *vars)
6993 {
6994         u16 val;
6995         bnx2x_cl45_read(bp, phy,
6996                         MDIO_AN_DEVAD,
6997                         MDIO_AN_REG_STATUS, &val);
6998         bnx2x_cl45_read(bp, phy,
6999                         MDIO_AN_DEVAD,
7000                         MDIO_AN_REG_STATUS, &val);
7001         if (val & (1<<5))
7002                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
7003         if ((val & (1<<0)) == 0)
7004                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
7005 }
7006
7007 /******************************************************************/
7008 /*              common BCM8073/BCM8727 PHY SECTION                */
7009 /******************************************************************/
7010 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
7011                                   struct link_params *params,
7012                                   struct link_vars *vars)
7013 {
7014         struct bnx2x *bp = params->bp;
7015         if (phy->req_line_speed == SPEED_10 ||
7016             phy->req_line_speed == SPEED_100) {
7017                 vars->flow_ctrl = phy->req_flow_ctrl;
7018                 return;
7019         }
7020
7021         if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
7022             (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
7023                 u16 pause_result;
7024                 u16 ld_pause;           /* local */
7025                 u16 lp_pause;           /* link partner */
7026                 bnx2x_cl45_read(bp, phy,
7027                                 MDIO_AN_DEVAD,
7028                                 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
7029
7030                 bnx2x_cl45_read(bp, phy,
7031                                 MDIO_AN_DEVAD,
7032                                 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
7033                 pause_result = (ld_pause &
7034                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
7035                 pause_result |= (lp_pause &
7036                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
7037
7038                 bnx2x_pause_resolve(vars, pause_result);
7039                 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
7040                            pause_result);
7041         }
7042 }
7043 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
7044                                              struct bnx2x_phy *phy,
7045                                              u8 port)
7046 {
7047         u32 count = 0;
7048         u16 fw_ver1, fw_msgout;
7049         int rc = 0;
7050
7051         /* Boot port from external ROM  */
7052         /* EDC grst */
7053         bnx2x_cl45_write(bp, phy,
7054                          MDIO_PMA_DEVAD,
7055                          MDIO_PMA_REG_GEN_CTRL,
7056                          0x0001);
7057
7058         /* ucode reboot and rst */
7059         bnx2x_cl45_write(bp, phy,
7060                          MDIO_PMA_DEVAD,
7061                          MDIO_PMA_REG_GEN_CTRL,
7062                          0x008c);
7063
7064         bnx2x_cl45_write(bp, phy,
7065                          MDIO_PMA_DEVAD,
7066                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
7067
7068         /* Reset internal microprocessor */
7069         bnx2x_cl45_write(bp, phy,
7070                          MDIO_PMA_DEVAD,
7071                          MDIO_PMA_REG_GEN_CTRL,
7072                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
7073
7074         /* Release srst bit */
7075         bnx2x_cl45_write(bp, phy,
7076                          MDIO_PMA_DEVAD,
7077                          MDIO_PMA_REG_GEN_CTRL,
7078                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
7079
7080         /* Delay 100ms per the PHY specifications */
7081         msleep(100);
7082
7083         /* 8073 sometimes taking longer to download */
7084         do {
7085                 count++;
7086                 if (count > 300) {
7087                         DP(NETIF_MSG_LINK,
7088                                  "bnx2x_8073_8727_external_rom_boot port %x:"
7089                                  "Download failed. fw version = 0x%x\n",
7090                                  port, fw_ver1);
7091                         rc = -EINVAL;
7092                         break;
7093                 }
7094
7095                 bnx2x_cl45_read(bp, phy,
7096                                 MDIO_PMA_DEVAD,
7097                                 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7098                 bnx2x_cl45_read(bp, phy,
7099                                 MDIO_PMA_DEVAD,
7100                                 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
7101
7102                 msleep(1);
7103         } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
7104                         ((fw_msgout & 0xff) != 0x03 && (phy->type ==
7105                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
7106
7107         /* Clear ser_boot_ctl bit */
7108         bnx2x_cl45_write(bp, phy,
7109                          MDIO_PMA_DEVAD,
7110                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
7111         bnx2x_save_bcm_spirom_ver(bp, phy, port);
7112
7113         DP(NETIF_MSG_LINK,
7114                  "bnx2x_8073_8727_external_rom_boot port %x:"
7115                  "Download complete. fw version = 0x%x\n",
7116                  port, fw_ver1);
7117
7118         return rc;
7119 }
7120
7121 /******************************************************************/
7122 /*                      BCM8073 PHY SECTION                       */
7123 /******************************************************************/
7124 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
7125 {
7126         /* This is only required for 8073A1, version 102 only */
7127         u16 val;
7128
7129         /* Read 8073 HW revision*/
7130         bnx2x_cl45_read(bp, phy,
7131                         MDIO_PMA_DEVAD,
7132                         MDIO_PMA_REG_8073_CHIP_REV, &val);
7133
7134         if (val != 1) {
7135                 /* No need to workaround in 8073 A1 */
7136                 return 0;
7137         }
7138
7139         bnx2x_cl45_read(bp, phy,
7140                         MDIO_PMA_DEVAD,
7141                         MDIO_PMA_REG_ROM_VER2, &val);
7142
7143         /* SNR should be applied only for version 0x102 */
7144         if (val != 0x102)
7145                 return 0;
7146
7147         return 1;
7148 }
7149
7150 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
7151 {
7152         u16 val, cnt, cnt1 ;
7153
7154         bnx2x_cl45_read(bp, phy,
7155                         MDIO_PMA_DEVAD,
7156                         MDIO_PMA_REG_8073_CHIP_REV, &val);
7157
7158         if (val > 0) {
7159                 /* No need to workaround in 8073 A1 */
7160                 return 0;
7161         }
7162         /* XAUI workaround in 8073 A0: */
7163
7164         /* After loading the boot ROM and restarting Autoneg, poll
7165          * Dev1, Reg $C820:
7166          */
7167
7168         for (cnt = 0; cnt < 1000; cnt++) {
7169                 bnx2x_cl45_read(bp, phy,
7170                                 MDIO_PMA_DEVAD,
7171                                 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7172                                 &val);
7173                   /* If bit [14] = 0 or bit [13] = 0, continue on with
7174                    * system initialization (XAUI work-around not required, as
7175                    * these bits indicate 2.5G or 1G link up).
7176                    */
7177                 if (!(val & (1<<14)) || !(val & (1<<13))) {
7178                         DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
7179                         return 0;
7180                 } else if (!(val & (1<<15))) {
7181                         DP(NETIF_MSG_LINK, "bit 15 went off\n");
7182                         /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7183                          * MSB (bit15) goes to 1 (indicating that the XAUI
7184                          * workaround has completed), then continue on with
7185                          * system initialization.
7186                          */
7187                         for (cnt1 = 0; cnt1 < 1000; cnt1++) {
7188                                 bnx2x_cl45_read(bp, phy,
7189                                         MDIO_PMA_DEVAD,
7190                                         MDIO_PMA_REG_8073_XAUI_WA, &val);
7191                                 if (val & (1<<15)) {
7192                                         DP(NETIF_MSG_LINK,
7193                                           "XAUI workaround has completed\n");
7194                                         return 0;
7195                                  }
7196                                  msleep(3);
7197                         }
7198                         break;
7199                 }
7200                 msleep(3);
7201         }
7202         DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
7203         return -EINVAL;
7204 }
7205
7206 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
7207 {
7208         /* Force KR or KX */
7209         bnx2x_cl45_write(bp, phy,
7210                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
7211         bnx2x_cl45_write(bp, phy,
7212                          MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
7213         bnx2x_cl45_write(bp, phy,
7214                          MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
7215         bnx2x_cl45_write(bp, phy,
7216                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
7217 }
7218
7219 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
7220                                       struct bnx2x_phy *phy,
7221                                       struct link_vars *vars)
7222 {
7223         u16 cl37_val;
7224         struct bnx2x *bp = params->bp;
7225         bnx2x_cl45_read(bp, phy,
7226                         MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
7227
7228         cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7229         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
7230         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
7231         if ((vars->ieee_fc &
7232             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7233             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7234                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
7235         }
7236         if ((vars->ieee_fc &
7237             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7238             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7239                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
7240         }
7241         if ((vars->ieee_fc &
7242             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7243             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7244                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7245         }
7246         DP(NETIF_MSG_LINK,
7247                  "Ext phy AN advertize cl37 0x%x\n", cl37_val);
7248
7249         bnx2x_cl45_write(bp, phy,
7250                          MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
7251         msleep(500);
7252 }
7253
7254 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
7255                                   struct link_params *params,
7256                                   struct link_vars *vars)
7257 {
7258         struct bnx2x *bp = params->bp;
7259         u16 val = 0, tmp1;
7260         u8 gpio_port;
7261         DP(NETIF_MSG_LINK, "Init 8073\n");
7262
7263         if (CHIP_IS_E2(bp))
7264                 gpio_port = BP_PATH(bp);
7265         else
7266                 gpio_port = params->port;
7267         /* Restore normal power mode*/
7268         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7269                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7270
7271         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7272                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7273
7274         /* enable LASI */
7275         bnx2x_cl45_write(bp, phy,
7276                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
7277         bnx2x_cl45_write(bp, phy,
7278                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,  0x0004);
7279
7280         bnx2x_8073_set_pause_cl37(params, phy, vars);
7281
7282         bnx2x_cl45_read(bp, phy,
7283                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
7284
7285         bnx2x_cl45_read(bp, phy,
7286                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
7287
7288         DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
7289
7290         /* Swap polarity if required - Must be done only in non-1G mode */
7291         if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7292                 /* Configure the 8073 to swap _P and _N of the KR lines */
7293                 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
7294                 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7295                 bnx2x_cl45_read(bp, phy,
7296                                 MDIO_PMA_DEVAD,
7297                                 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
7298                 bnx2x_cl45_write(bp, phy,
7299                                  MDIO_PMA_DEVAD,
7300                                  MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7301                                  (val | (3<<9)));
7302         }
7303
7304
7305         /* Enable CL37 BAM */
7306         if (REG_RD(bp, params->shmem_base +
7307                          offsetof(struct shmem_region, dev_info.
7308                                   port_hw_config[params->port].default_cfg)) &
7309             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
7310
7311                 bnx2x_cl45_read(bp, phy,
7312                                 MDIO_AN_DEVAD,
7313                                 MDIO_AN_REG_8073_BAM, &val);
7314                 bnx2x_cl45_write(bp, phy,
7315                                  MDIO_AN_DEVAD,
7316                                  MDIO_AN_REG_8073_BAM, val | 1);
7317                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
7318         }
7319         if (params->loopback_mode == LOOPBACK_EXT) {
7320                 bnx2x_807x_force_10G(bp, phy);
7321                 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
7322                 return 0;
7323         } else {
7324                 bnx2x_cl45_write(bp, phy,
7325                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
7326         }
7327         if (phy->req_line_speed != SPEED_AUTO_NEG) {
7328                 if (phy->req_line_speed == SPEED_10000) {
7329                         val = (1<<7);
7330                 } else if (phy->req_line_speed ==  SPEED_2500) {
7331                         val = (1<<5);
7332                         /* Note that 2.5G works only when used with 1G
7333                          * advertisement
7334                          */
7335                 } else
7336                         val = (1<<5);
7337         } else {
7338                 val = 0;
7339                 if (phy->speed_cap_mask &
7340                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7341                         val |= (1<<7);
7342
7343                 /* Note that 2.5G works only when used with 1G advertisement */
7344                 if (phy->speed_cap_mask &
7345                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
7346                          PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7347                         val |= (1<<5);
7348                 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
7349         }
7350
7351         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
7352         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
7353
7354         if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
7355              (phy->req_line_speed == SPEED_AUTO_NEG)) ||
7356             (phy->req_line_speed == SPEED_2500)) {
7357                 u16 phy_ver;
7358                 /* Allow 2.5G for A1 and above */
7359                 bnx2x_cl45_read(bp, phy,
7360                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
7361                                 &phy_ver);
7362                 DP(NETIF_MSG_LINK, "Add 2.5G\n");
7363                 if (phy_ver > 0)
7364                         tmp1 |= 1;
7365                 else
7366                         tmp1 &= 0xfffe;
7367         } else {
7368                 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
7369                 tmp1 &= 0xfffe;
7370         }
7371
7372         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
7373         /* Add support for CL37 (passive mode) II */
7374
7375         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
7376         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
7377                          (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
7378                                   0x20 : 0x40)));
7379
7380         /* Add support for CL37 (passive mode) III */
7381         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
7382
7383         /* The SNR will improve about 2db by changing BW and FEE main
7384          * tap. Rest commands are executed after link is up
7385          * Change FFE main cursor to 5 in EDC register
7386          */
7387         if (bnx2x_8073_is_snr_needed(bp, phy))
7388                 bnx2x_cl45_write(bp, phy,
7389                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7390                                  0xFB0C);
7391
7392         /* Enable FEC (Forware Error Correction) Request in the AN */
7393         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7394         tmp1 |= (1<<15);
7395         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7396
7397         bnx2x_ext_phy_set_pause(params, phy, vars);
7398
7399         /* Restart autoneg */
7400         msleep(500);
7401         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7402         DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7403                    ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7404         return 0;
7405 }
7406
7407 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7408                                  struct link_params *params,
7409                                  struct link_vars *vars)
7410 {
7411         struct bnx2x *bp = params->bp;
7412         u8 link_up = 0;
7413         u16 val1, val2;
7414         u16 link_status = 0;
7415         u16 an1000_status = 0;
7416
7417         bnx2x_cl45_read(bp, phy,
7418                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7419
7420         DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7421
7422         /* clear the interrupt LASI status register */
7423         bnx2x_cl45_read(bp, phy,
7424                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7425         bnx2x_cl45_read(bp, phy,
7426                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7427         DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7428         /* Clear MSG-OUT */
7429         bnx2x_cl45_read(bp, phy,
7430                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7431
7432         /* Check the LASI */
7433         bnx2x_cl45_read(bp, phy,
7434                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7435
7436         DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7437
7438         /* Check the link status */
7439         bnx2x_cl45_read(bp, phy,
7440                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7441         DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7442
7443         bnx2x_cl45_read(bp, phy,
7444                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7445         bnx2x_cl45_read(bp, phy,
7446                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7447         link_up = ((val1 & 4) == 4);
7448         DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7449
7450         if (link_up &&
7451              ((phy->req_line_speed != SPEED_10000))) {
7452                 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7453                         return 0;
7454         }
7455         bnx2x_cl45_read(bp, phy,
7456                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7457         bnx2x_cl45_read(bp, phy,
7458                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7459
7460         /* Check the link status on 1.1.2 */
7461         bnx2x_cl45_read(bp, phy,
7462                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7463         bnx2x_cl45_read(bp, phy,
7464                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7465         DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7466                    "an_link_status=0x%x\n", val2, val1, an1000_status);
7467
7468         link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7469         if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7470                 /* The SNR will improve about 2dbby changing the BW and FEE main
7471                  * tap. The 1st write to change FFE main tap is set before
7472                  * restart AN. Change PLL Bandwidth in EDC register
7473                  */
7474                 bnx2x_cl45_write(bp, phy,
7475                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7476                                  0x26BC);
7477
7478                 /* Change CDR Bandwidth in EDC register */
7479                 bnx2x_cl45_write(bp, phy,
7480                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7481                                  0x0333);
7482         }
7483         bnx2x_cl45_read(bp, phy,
7484                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7485                         &link_status);
7486
7487         /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7488         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7489                 link_up = 1;
7490                 vars->line_speed = SPEED_10000;
7491                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7492                            params->port);
7493         } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7494                 link_up = 1;
7495                 vars->line_speed = SPEED_2500;
7496                 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7497                            params->port);
7498         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7499                 link_up = 1;
7500                 vars->line_speed = SPEED_1000;
7501                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7502                            params->port);
7503         } else {
7504                 link_up = 0;
7505                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7506                            params->port);
7507         }
7508
7509         if (link_up) {
7510                 /* Swap polarity if required */
7511                 if (params->lane_config &
7512                     PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7513                         /* Configure the 8073 to swap P and N of the KR lines */
7514                         bnx2x_cl45_read(bp, phy,
7515                                         MDIO_XS_DEVAD,
7516                                         MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7517                         /* Set bit 3 to invert Rx in 1G mode and clear this bit
7518                          * when it`s in 10G mode.
7519                          */
7520                         if (vars->line_speed == SPEED_1000) {
7521                                 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7522                                               "the 8073\n");
7523                                 val1 |= (1<<3);
7524                         } else
7525                                 val1 &= ~(1<<3);
7526
7527                         bnx2x_cl45_write(bp, phy,
7528                                          MDIO_XS_DEVAD,
7529                                          MDIO_XS_REG_8073_RX_CTRL_PCIE,
7530                                          val1);
7531                 }
7532                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7533                 bnx2x_8073_resolve_fc(phy, params, vars);
7534                 vars->duplex = DUPLEX_FULL;
7535         }
7536
7537         if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
7538                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
7539                                 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
7540
7541                 if (val1 & (1<<5))
7542                         vars->link_status |=
7543                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7544                 if (val1 & (1<<7))
7545                         vars->link_status |=
7546                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7547         }
7548
7549         return link_up;
7550 }
7551
7552 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7553                                   struct link_params *params)
7554 {
7555         struct bnx2x *bp = params->bp;
7556         u8 gpio_port;
7557         if (CHIP_IS_E2(bp))
7558                 gpio_port = BP_PATH(bp);
7559         else
7560                 gpio_port = params->port;
7561         DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7562            gpio_port);
7563         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7564                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
7565                        gpio_port);
7566 }
7567
7568 /******************************************************************/
7569 /*                      BCM8705 PHY SECTION                       */
7570 /******************************************************************/
7571 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7572                                   struct link_params *params,
7573                                   struct link_vars *vars)
7574 {
7575         struct bnx2x *bp = params->bp;
7576         DP(NETIF_MSG_LINK, "init 8705\n");
7577         /* Restore normal power mode*/
7578         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7579                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7580         /* HW reset */
7581         bnx2x_ext_phy_hw_reset(bp, params->port);
7582         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7583         bnx2x_wait_reset_complete(bp, phy, params);
7584
7585         bnx2x_cl45_write(bp, phy,
7586                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7587         bnx2x_cl45_write(bp, phy,
7588                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7589         bnx2x_cl45_write(bp, phy,
7590                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7591         bnx2x_cl45_write(bp, phy,
7592                          MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7593         /* BCM8705 doesn't have microcode, hence the 0 */
7594         bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7595         return 0;
7596 }
7597
7598 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7599                                  struct link_params *params,
7600                                  struct link_vars *vars)
7601 {
7602         u8 link_up = 0;
7603         u16 val1, rx_sd;
7604         struct bnx2x *bp = params->bp;
7605         DP(NETIF_MSG_LINK, "read status 8705\n");
7606         bnx2x_cl45_read(bp, phy,
7607                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7608         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7609
7610         bnx2x_cl45_read(bp, phy,
7611                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7612         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7613
7614         bnx2x_cl45_read(bp, phy,
7615                       MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7616
7617         bnx2x_cl45_read(bp, phy,
7618                       MDIO_PMA_DEVAD, 0xc809, &val1);
7619         bnx2x_cl45_read(bp, phy,
7620                       MDIO_PMA_DEVAD, 0xc809, &val1);
7621
7622         DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7623         link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7624         if (link_up) {
7625                 vars->line_speed = SPEED_10000;
7626                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7627         }
7628         return link_up;
7629 }
7630
7631 /******************************************************************/
7632 /*                      SFP+ module Section                       */
7633 /******************************************************************/
7634 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7635                                            struct bnx2x_phy *phy,
7636                                            u8 pmd_dis)
7637 {
7638         struct bnx2x *bp = params->bp;
7639         /* Disable transmitter only for bootcodes which can enable it afterwards
7640          * (for D3 link)
7641          */
7642         if (pmd_dis) {
7643                 if (params->feature_config_flags &
7644                      FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7645                         DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7646                 else {
7647                         DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7648                         return;
7649                 }
7650         } else
7651                 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7652         bnx2x_cl45_write(bp, phy,
7653                          MDIO_PMA_DEVAD,
7654                          MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7655 }
7656
7657 static u8 bnx2x_get_gpio_port(struct link_params *params)
7658 {
7659         u8 gpio_port;
7660         u32 swap_val, swap_override;
7661         struct bnx2x *bp = params->bp;
7662         if (CHIP_IS_E2(bp))
7663                 gpio_port = BP_PATH(bp);
7664         else
7665                 gpio_port = params->port;
7666         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7667         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7668         return gpio_port ^ (swap_val && swap_override);
7669 }
7670
7671 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7672                                            struct bnx2x_phy *phy,
7673                                            u8 tx_en)
7674 {
7675         u16 val;
7676         u8 port = params->port;
7677         struct bnx2x *bp = params->bp;
7678         u32 tx_en_mode;
7679
7680         /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7681         tx_en_mode = REG_RD(bp, params->shmem_base +
7682                             offsetof(struct shmem_region,
7683                                      dev_info.port_hw_config[port].sfp_ctrl)) &
7684                 PORT_HW_CFG_TX_LASER_MASK;
7685         DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7686                            "mode = %x\n", tx_en, port, tx_en_mode);
7687         switch (tx_en_mode) {
7688         case PORT_HW_CFG_TX_LASER_MDIO:
7689
7690                 bnx2x_cl45_read(bp, phy,
7691                                 MDIO_PMA_DEVAD,
7692                                 MDIO_PMA_REG_PHY_IDENTIFIER,
7693                                 &val);
7694
7695                 if (tx_en)
7696                         val &= ~(1<<15);
7697                 else
7698                         val |= (1<<15);
7699
7700                 bnx2x_cl45_write(bp, phy,
7701                                  MDIO_PMA_DEVAD,
7702                                  MDIO_PMA_REG_PHY_IDENTIFIER,
7703                                  val);
7704         break;
7705         case PORT_HW_CFG_TX_LASER_GPIO0:
7706         case PORT_HW_CFG_TX_LASER_GPIO1:
7707         case PORT_HW_CFG_TX_LASER_GPIO2:
7708         case PORT_HW_CFG_TX_LASER_GPIO3:
7709         {
7710                 u16 gpio_pin;
7711                 u8 gpio_port, gpio_mode;
7712                 if (tx_en)
7713                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7714                 else
7715                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7716
7717                 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7718                 gpio_port = bnx2x_get_gpio_port(params);
7719                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7720                 break;
7721         }
7722         default:
7723                 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7724                 break;
7725         }
7726 }
7727
7728 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7729                                       struct bnx2x_phy *phy,
7730                                       u8 tx_en)
7731 {
7732         struct bnx2x *bp = params->bp;
7733         DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7734         if (CHIP_IS_E3(bp))
7735                 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7736         else
7737                 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7738 }
7739
7740 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7741                                              struct link_params *params,
7742                                              u16 addr, u8 byte_cnt, u8 *o_buf)
7743 {
7744         struct bnx2x *bp = params->bp;
7745         u16 val = 0;
7746         u16 i;
7747         if (byte_cnt > 16) {
7748                 DP(NETIF_MSG_LINK,
7749                    "Reading from eeprom is limited to 0xf\n");
7750                 return -EINVAL;
7751         }
7752         /* Set the read command byte count */
7753         bnx2x_cl45_write(bp, phy,
7754                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7755                          (byte_cnt | 0xa000));
7756
7757         /* Set the read command address */
7758         bnx2x_cl45_write(bp, phy,
7759                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7760                          addr);
7761
7762         /* Activate read command */
7763         bnx2x_cl45_write(bp, phy,
7764                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7765                          0x2c0f);
7766
7767         /* Wait up to 500us for command complete status */
7768         for (i = 0; i < 100; i++) {
7769                 bnx2x_cl45_read(bp, phy,
7770                                 MDIO_PMA_DEVAD,
7771                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7772                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7773                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7774                         break;
7775                 udelay(5);
7776         }
7777
7778         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7779                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7780                 DP(NETIF_MSG_LINK,
7781                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7782                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7783                 return -EINVAL;
7784         }
7785
7786         /* Read the buffer */
7787         for (i = 0; i < byte_cnt; i++) {
7788                 bnx2x_cl45_read(bp, phy,
7789                                 MDIO_PMA_DEVAD,
7790                                 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7791                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7792         }
7793
7794         for (i = 0; i < 100; i++) {
7795                 bnx2x_cl45_read(bp, phy,
7796                                 MDIO_PMA_DEVAD,
7797                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7798                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7799                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7800                         return 0;
7801                 msleep(1);
7802         }
7803         return -EINVAL;
7804 }
7805
7806 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7807                                                  struct link_params *params,
7808                                                  u16 addr, u8 byte_cnt,
7809                                                  u8 *o_buf)
7810 {
7811         int rc = 0;
7812         u8 i, j = 0, cnt = 0;
7813         u32 data_array[4];
7814         u16 addr32;
7815         struct bnx2x *bp = params->bp;
7816         if (byte_cnt > 16) {
7817                 DP(NETIF_MSG_LINK,
7818                    "Reading from eeprom is limited to 16 bytes\n");
7819                 return -EINVAL;
7820         }
7821
7822         /* 4 byte aligned address */
7823         addr32 = addr & (~0x3);
7824         do {
7825                 rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt,
7826                                     data_array);
7827         } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7828
7829         if (rc == 0) {
7830                 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7831                         o_buf[j] = *((u8 *)data_array + i);
7832                         j++;
7833                 }
7834         }
7835
7836         return rc;
7837 }
7838
7839 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7840                                              struct link_params *params,
7841                                              u16 addr, u8 byte_cnt, u8 *o_buf)
7842 {
7843         struct bnx2x *bp = params->bp;
7844         u16 val, i;
7845
7846         if (byte_cnt > 16) {
7847                 DP(NETIF_MSG_LINK,
7848                    "Reading from eeprom is limited to 0xf\n");
7849                 return -EINVAL;
7850         }
7851
7852         /* Need to read from 1.8000 to clear it */
7853         bnx2x_cl45_read(bp, phy,
7854                         MDIO_PMA_DEVAD,
7855                         MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7856                         &val);
7857
7858         /* Set the read command byte count */
7859         bnx2x_cl45_write(bp, phy,
7860                          MDIO_PMA_DEVAD,
7861                          MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7862                          ((byte_cnt < 2) ? 2 : byte_cnt));
7863
7864         /* Set the read command address */
7865         bnx2x_cl45_write(bp, phy,
7866                          MDIO_PMA_DEVAD,
7867                          MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7868                          addr);
7869         /* Set the destination address */
7870         bnx2x_cl45_write(bp, phy,
7871                          MDIO_PMA_DEVAD,
7872                          0x8004,
7873                          MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7874
7875         /* Activate read command */
7876         bnx2x_cl45_write(bp, phy,
7877                          MDIO_PMA_DEVAD,
7878                          MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7879                          0x8002);
7880         /* Wait appropriate time for two-wire command to finish before
7881          * polling the status register
7882          */
7883         msleep(1);
7884
7885         /* Wait up to 500us for command complete status */
7886         for (i = 0; i < 100; i++) {
7887                 bnx2x_cl45_read(bp, phy,
7888                                 MDIO_PMA_DEVAD,
7889                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7890                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7891                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7892                         break;
7893                 udelay(5);
7894         }
7895
7896         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7897                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7898                 DP(NETIF_MSG_LINK,
7899                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7900                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7901                 return -EFAULT;
7902         }
7903
7904         /* Read the buffer */
7905         for (i = 0; i < byte_cnt; i++) {
7906                 bnx2x_cl45_read(bp, phy,
7907                                 MDIO_PMA_DEVAD,
7908                                 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
7909                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7910         }
7911
7912         for (i = 0; i < 100; i++) {
7913                 bnx2x_cl45_read(bp, phy,
7914                                 MDIO_PMA_DEVAD,
7915                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7916                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7917                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7918                         return 0;
7919                 msleep(1);
7920         }
7921
7922         return -EINVAL;
7923 }
7924
7925 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7926                                  struct link_params *params, u16 addr,
7927                                  u8 byte_cnt, u8 *o_buf)
7928 {
7929         int rc = -EINVAL;
7930         switch (phy->type) {
7931         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7932                 rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
7933                                                        byte_cnt, o_buf);
7934         break;
7935         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7936         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7937                 rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
7938                                                        byte_cnt, o_buf);
7939         break;
7940         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7941                 rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr,
7942                                                            byte_cnt, o_buf);
7943         break;
7944         }
7945         return rc;
7946 }
7947
7948 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
7949                               struct link_params *params,
7950                               u16 *edc_mode)
7951 {
7952         struct bnx2x *bp = params->bp;
7953         u32 sync_offset = 0, phy_idx, media_types;
7954         u8 val, check_limiting_mode = 0;
7955         *edc_mode = EDC_MODE_LIMITING;
7956
7957         phy->media_type = ETH_PHY_UNSPECIFIED;
7958         /* First check for copper cable */
7959         if (bnx2x_read_sfp_module_eeprom(phy,
7960                                          params,
7961                                          SFP_EEPROM_CON_TYPE_ADDR,
7962                                          1,
7963                                          &val) != 0) {
7964                 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
7965                 return -EINVAL;
7966         }
7967
7968         switch (val) {
7969         case SFP_EEPROM_CON_TYPE_VAL_COPPER:
7970         {
7971                 u8 copper_module_type;
7972                 phy->media_type = ETH_PHY_DA_TWINAX;
7973                 /* Check if its active cable (includes SFP+ module)
7974                  * of passive cable
7975                  */
7976                 if (bnx2x_read_sfp_module_eeprom(phy,
7977                                                params,
7978                                                SFP_EEPROM_FC_TX_TECH_ADDR,
7979                                                1,
7980                                                &copper_module_type) != 0) {
7981                         DP(NETIF_MSG_LINK,
7982                                 "Failed to read copper-cable-type"
7983                                 " from SFP+ EEPROM\n");
7984                         return -EINVAL;
7985                 }
7986
7987                 if (copper_module_type &
7988                     SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
7989                         DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
7990                         check_limiting_mode = 1;
7991                 } else if (copper_module_type &
7992                         SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
7993                                 DP(NETIF_MSG_LINK,
7994                                    "Passive Copper cable detected\n");
7995                                 *edc_mode =
7996                                       EDC_MODE_PASSIVE_DAC;
7997                 } else {
7998                         DP(NETIF_MSG_LINK,
7999                            "Unknown copper-cable-type 0x%x !!!\n",
8000                            copper_module_type);
8001                         return -EINVAL;
8002                 }
8003                 break;
8004         }
8005         case SFP_EEPROM_CON_TYPE_VAL_LC:
8006                 phy->media_type = ETH_PHY_SFP_FIBER;
8007                 DP(NETIF_MSG_LINK, "Optic module detected\n");
8008                 check_limiting_mode = 1;
8009                 break;
8010         default:
8011                 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
8012                          val);
8013                 return -EINVAL;
8014         }
8015         sync_offset = params->shmem_base +
8016                 offsetof(struct shmem_region,
8017                          dev_info.port_hw_config[params->port].media_type);
8018         media_types = REG_RD(bp, sync_offset);
8019         /* Update media type for non-PMF sync */
8020         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
8021                 if (&(params->phy[phy_idx]) == phy) {
8022                         media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
8023                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8024                         media_types |= ((phy->media_type &
8025                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
8026                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8027                         break;
8028                 }
8029         }
8030         REG_WR(bp, sync_offset, media_types);
8031         if (check_limiting_mode) {
8032                 u8 options[SFP_EEPROM_OPTIONS_SIZE];
8033                 if (bnx2x_read_sfp_module_eeprom(phy,
8034                                                  params,
8035                                                  SFP_EEPROM_OPTIONS_ADDR,
8036                                                  SFP_EEPROM_OPTIONS_SIZE,
8037                                                  options) != 0) {
8038                         DP(NETIF_MSG_LINK,
8039                            "Failed to read Option field from module EEPROM\n");
8040                         return -EINVAL;
8041                 }
8042                 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
8043                         *edc_mode = EDC_MODE_LINEAR;
8044                 else
8045                         *edc_mode = EDC_MODE_LIMITING;
8046         }
8047         DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
8048         return 0;
8049 }
8050 /* This function read the relevant field from the module (SFP+), and verify it
8051  * is compliant with this board
8052  */
8053 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
8054                                    struct link_params *params)
8055 {
8056         struct bnx2x *bp = params->bp;
8057         u32 val, cmd;
8058         u32 fw_resp, fw_cmd_param;
8059         char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
8060         char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
8061         phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
8062         val = REG_RD(bp, params->shmem_base +
8063                          offsetof(struct shmem_region, dev_info.
8064                                   port_feature_config[params->port].config));
8065         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8066             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
8067                 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
8068                 return 0;
8069         }
8070
8071         if (params->feature_config_flags &
8072             FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
8073                 /* Use specific phy request */
8074                 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
8075         } else if (params->feature_config_flags &
8076                    FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
8077                 /* Use first phy request only in case of non-dual media*/
8078                 if (DUAL_MEDIA(params)) {
8079                         DP(NETIF_MSG_LINK,
8080                            "FW does not support OPT MDL verification\n");
8081                         return -EINVAL;
8082                 }
8083                 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
8084         } else {
8085                 /* No support in OPT MDL detection */
8086                 DP(NETIF_MSG_LINK,
8087                    "FW does not support OPT MDL verification\n");
8088                 return -EINVAL;
8089         }
8090
8091         fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
8092         fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
8093         if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
8094                 DP(NETIF_MSG_LINK, "Approved module\n");
8095                 return 0;
8096         }
8097
8098         /* format the warning message */
8099         if (bnx2x_read_sfp_module_eeprom(phy,
8100                                          params,
8101                                          SFP_EEPROM_VENDOR_NAME_ADDR,
8102                                          SFP_EEPROM_VENDOR_NAME_SIZE,
8103                                          (u8 *)vendor_name))
8104                 vendor_name[0] = '\0';
8105         else
8106                 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
8107         if (bnx2x_read_sfp_module_eeprom(phy,
8108                                          params,
8109                                          SFP_EEPROM_PART_NO_ADDR,
8110                                          SFP_EEPROM_PART_NO_SIZE,
8111                                          (u8 *)vendor_pn))
8112                 vendor_pn[0] = '\0';
8113         else
8114                 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
8115
8116         netdev_err(bp->dev,  "Warning: Unqualified SFP+ module detected,"
8117                               " Port %d from %s part number %s\n",
8118                          params->port, vendor_name, vendor_pn);
8119         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8120             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
8121                 phy->flags |= FLAGS_SFP_NOT_APPROVED;
8122         return -EINVAL;
8123 }
8124
8125 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
8126                                                  struct link_params *params)
8127
8128 {
8129         u8 val;
8130         struct bnx2x *bp = params->bp;
8131         u16 timeout;
8132         /* Initialization time after hot-plug may take up to 300ms for
8133          * some phys type ( e.g. JDSU )
8134          */
8135
8136         for (timeout = 0; timeout < 60; timeout++) {
8137                 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
8138                     == 0) {
8139                         DP(NETIF_MSG_LINK,
8140                            "SFP+ module initialization took %d ms\n",
8141                            timeout * 5);
8142                         return 0;
8143                 }
8144                 msleep(5);
8145         }
8146         return -EINVAL;
8147 }
8148
8149 static void bnx2x_8727_power_module(struct bnx2x *bp,
8150                                     struct bnx2x_phy *phy,
8151                                     u8 is_power_up) {
8152         /* Make sure GPIOs are not using for LED mode */
8153         u16 val;
8154         /* In the GPIO register, bit 4 is use to determine if the GPIOs are
8155          * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
8156          * output
8157          * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
8158          * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
8159          * where the 1st bit is the over-current(only input), and 2nd bit is
8160          * for power( only output )
8161          *
8162          * In case of NOC feature is disabled and power is up, set GPIO control
8163          *  as input to enable listening of over-current indication
8164          */
8165         if (phy->flags & FLAGS_NOC)
8166                 return;
8167         if (is_power_up)
8168                 val = (1<<4);
8169         else
8170                 /* Set GPIO control to OUTPUT, and set the power bit
8171                  * to according to the is_power_up
8172                  */
8173                 val = (1<<1);
8174
8175         bnx2x_cl45_write(bp, phy,
8176                          MDIO_PMA_DEVAD,
8177                          MDIO_PMA_REG_8727_GPIO_CTRL,
8178                          val);
8179 }
8180
8181 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
8182                                         struct bnx2x_phy *phy,
8183                                         u16 edc_mode)
8184 {
8185         u16 cur_limiting_mode;
8186
8187         bnx2x_cl45_read(bp, phy,
8188                         MDIO_PMA_DEVAD,
8189                         MDIO_PMA_REG_ROM_VER2,
8190                         &cur_limiting_mode);
8191         DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
8192                  cur_limiting_mode);
8193
8194         if (edc_mode == EDC_MODE_LIMITING) {
8195                 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
8196                 bnx2x_cl45_write(bp, phy,
8197                                  MDIO_PMA_DEVAD,
8198                                  MDIO_PMA_REG_ROM_VER2,
8199                                  EDC_MODE_LIMITING);
8200         } else { /* LRM mode ( default )*/
8201
8202                 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
8203
8204                 /* Changing to LRM mode takes quite few seconds. So do it only
8205                  * if current mode is limiting (default is LRM)
8206                  */
8207                 if (cur_limiting_mode != EDC_MODE_LIMITING)
8208                         return 0;
8209
8210                 bnx2x_cl45_write(bp, phy,
8211                                  MDIO_PMA_DEVAD,
8212                                  MDIO_PMA_REG_LRM_MODE,
8213                                  0);
8214                 bnx2x_cl45_write(bp, phy,
8215                                  MDIO_PMA_DEVAD,
8216                                  MDIO_PMA_REG_ROM_VER2,
8217                                  0x128);
8218                 bnx2x_cl45_write(bp, phy,
8219                                  MDIO_PMA_DEVAD,
8220                                  MDIO_PMA_REG_MISC_CTRL0,
8221                                  0x4008);
8222                 bnx2x_cl45_write(bp, phy,
8223                                  MDIO_PMA_DEVAD,
8224                                  MDIO_PMA_REG_LRM_MODE,
8225                                  0xaaaa);
8226         }
8227         return 0;
8228 }
8229
8230 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
8231                                         struct bnx2x_phy *phy,
8232                                         u16 edc_mode)
8233 {
8234         u16 phy_identifier;
8235         u16 rom_ver2_val;
8236         bnx2x_cl45_read(bp, phy,
8237                         MDIO_PMA_DEVAD,
8238                         MDIO_PMA_REG_PHY_IDENTIFIER,
8239                         &phy_identifier);
8240
8241         bnx2x_cl45_write(bp, phy,
8242                          MDIO_PMA_DEVAD,
8243                          MDIO_PMA_REG_PHY_IDENTIFIER,
8244                          (phy_identifier & ~(1<<9)));
8245
8246         bnx2x_cl45_read(bp, phy,
8247                         MDIO_PMA_DEVAD,
8248                         MDIO_PMA_REG_ROM_VER2,
8249                         &rom_ver2_val);
8250         /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8251         bnx2x_cl45_write(bp, phy,
8252                          MDIO_PMA_DEVAD,
8253                          MDIO_PMA_REG_ROM_VER2,
8254                          (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
8255
8256         bnx2x_cl45_write(bp, phy,
8257                          MDIO_PMA_DEVAD,
8258                          MDIO_PMA_REG_PHY_IDENTIFIER,
8259                          (phy_identifier | (1<<9)));
8260
8261         return 0;
8262 }
8263
8264 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
8265                                      struct link_params *params,
8266                                      u32 action)
8267 {
8268         struct bnx2x *bp = params->bp;
8269
8270         switch (action) {
8271         case DISABLE_TX:
8272                 bnx2x_sfp_set_transmitter(params, phy, 0);
8273                 break;
8274         case ENABLE_TX:
8275                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
8276                         bnx2x_sfp_set_transmitter(params, phy, 1);
8277                 break;
8278         default:
8279                 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
8280                    action);
8281                 return;
8282         }
8283 }
8284
8285 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
8286                                            u8 gpio_mode)
8287 {
8288         struct bnx2x *bp = params->bp;
8289
8290         u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
8291                             offsetof(struct shmem_region,
8292                         dev_info.port_hw_config[params->port].sfp_ctrl)) &
8293                 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8294         switch (fault_led_gpio) {
8295         case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
8296                 return;
8297         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
8298         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
8299         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
8300         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
8301         {
8302                 u8 gpio_port = bnx2x_get_gpio_port(params);
8303                 u16 gpio_pin = fault_led_gpio -
8304                         PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8305                 DP(NETIF_MSG_LINK, "Set fault module-detected led "
8306                                    "pin %x port %x mode %x\n",
8307                                gpio_pin, gpio_port, gpio_mode);
8308                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
8309         }
8310         break;
8311         default:
8312                 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
8313                                fault_led_gpio);
8314         }
8315 }
8316
8317 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
8318                                           u8 gpio_mode)
8319 {
8320         u32 pin_cfg;
8321         u8 port = params->port;
8322         struct bnx2x *bp = params->bp;
8323         pin_cfg = (REG_RD(bp, params->shmem_base +
8324                          offsetof(struct shmem_region,
8325                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
8326                 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8327                 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8328         DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
8329                        gpio_mode, pin_cfg);
8330         bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
8331 }
8332
8333 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
8334                                            u8 gpio_mode)
8335 {
8336         struct bnx2x *bp = params->bp;
8337         DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
8338         if (CHIP_IS_E3(bp)) {
8339                 /* Low ==> if SFP+ module is supported otherwise
8340                  * High ==> if SFP+ module is not on the approved vendor list
8341                  */
8342                 bnx2x_set_e3_module_fault_led(params, gpio_mode);
8343         } else
8344                 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
8345 }
8346
8347 static void bnx2x_warpcore_power_module(struct link_params *params,
8348                                         struct bnx2x_phy *phy,
8349                                         u8 power)
8350 {
8351         u32 pin_cfg;
8352         struct bnx2x *bp = params->bp;
8353
8354         pin_cfg = (REG_RD(bp, params->shmem_base +
8355                           offsetof(struct shmem_region,
8356                         dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
8357                         PORT_HW_CFG_E3_PWR_DIS_MASK) >>
8358                         PORT_HW_CFG_E3_PWR_DIS_SHIFT;
8359
8360         if (pin_cfg == PIN_CFG_NA)
8361                 return;
8362         DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
8363                        power, pin_cfg);
8364         /* Low ==> corresponding SFP+ module is powered
8365          * high ==> the SFP+ module is powered down
8366          */
8367         bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
8368 }
8369
8370 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
8371                                     struct link_params *params)
8372 {
8373         struct bnx2x *bp = params->bp;
8374         bnx2x_warpcore_power_module(params, phy, 0);
8375         /* Put Warpcore in low power mode */
8376         REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e);
8377
8378         /* Put LCPLL in low power mode */
8379         REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1);
8380         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8381         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
8382 }
8383
8384 static void bnx2x_power_sfp_module(struct link_params *params,
8385                                    struct bnx2x_phy *phy,
8386                                    u8 power)
8387 {
8388         struct bnx2x *bp = params->bp;
8389         DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
8390
8391         switch (phy->type) {
8392         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8393         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8394                 bnx2x_8727_power_module(params->bp, phy, power);
8395                 break;
8396         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8397                 bnx2x_warpcore_power_module(params, phy, power);
8398                 break;
8399         default:
8400                 break;
8401         }
8402 }
8403 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8404                                              struct bnx2x_phy *phy,
8405                                              u16 edc_mode)
8406 {
8407         u16 val = 0;
8408         u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8409         struct bnx2x *bp = params->bp;
8410
8411         u8 lane = bnx2x_get_warpcore_lane(phy, params);
8412         /* This is a global register which controls all lanes */
8413         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8414                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8415         val &= ~(0xf << (lane << 2));
8416
8417         switch (edc_mode) {
8418         case EDC_MODE_LINEAR:
8419         case EDC_MODE_LIMITING:
8420                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8421                 break;
8422         case EDC_MODE_PASSIVE_DAC:
8423                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8424                 break;
8425         default:
8426                 break;
8427         }
8428
8429         val |= (mode << (lane << 2));
8430         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8431                          MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8432         /* A must read */
8433         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8434                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8435
8436         /* Restart microcode to re-read the new mode */
8437         bnx2x_warpcore_reset_lane(bp, phy, 1);
8438         bnx2x_warpcore_reset_lane(bp, phy, 0);
8439
8440 }
8441
8442 static void bnx2x_set_limiting_mode(struct link_params *params,
8443                                     struct bnx2x_phy *phy,
8444                                     u16 edc_mode)
8445 {
8446         switch (phy->type) {
8447         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8448                 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8449                 break;
8450         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8451         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8452                 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8453                 break;
8454         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8455                 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8456                 break;
8457         }
8458 }
8459
8460 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8461                                struct link_params *params)
8462 {
8463         struct bnx2x *bp = params->bp;
8464         u16 edc_mode;
8465         int rc = 0;
8466
8467         u32 val = REG_RD(bp, params->shmem_base +
8468                              offsetof(struct shmem_region, dev_info.
8469                                      port_feature_config[params->port].config));
8470
8471         DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8472                  params->port);
8473         /* Power up module */
8474         bnx2x_power_sfp_module(params, phy, 1);
8475         if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8476                 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8477                 return -EINVAL;
8478         } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8479                 /* check SFP+ module compatibility */
8480                 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8481                 rc = -EINVAL;
8482                 /* Turn on fault module-detected led */
8483                 bnx2x_set_sfp_module_fault_led(params,
8484                                                MISC_REGISTERS_GPIO_HIGH);
8485
8486                 /* Check if need to power down the SFP+ module */
8487                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8488                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8489                         DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8490                         bnx2x_power_sfp_module(params, phy, 0);
8491                         return rc;
8492                 }
8493         } else {
8494                 /* Turn off fault module-detected led */
8495                 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8496         }
8497
8498         /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8499          * is done automatically
8500          */
8501         bnx2x_set_limiting_mode(params, phy, edc_mode);
8502
8503         /* Enable transmit for this module if the module is approved, or
8504          * if unapproved modules should also enable the Tx laser
8505          */
8506         if (rc == 0 ||
8507             (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8508             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8509                 bnx2x_sfp_set_transmitter(params, phy, 1);
8510         else
8511                 bnx2x_sfp_set_transmitter(params, phy, 0);
8512
8513         return rc;
8514 }
8515
8516 void bnx2x_handle_module_detect_int(struct link_params *params)
8517 {
8518         struct bnx2x *bp = params->bp;
8519         struct bnx2x_phy *phy;
8520         u32 gpio_val;
8521         u8 gpio_num, gpio_port;
8522         if (CHIP_IS_E3(bp))
8523                 phy = &params->phy[INT_PHY];
8524         else
8525                 phy = &params->phy[EXT_PHY1];
8526
8527         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8528                                       params->port, &gpio_num, &gpio_port) ==
8529             -EINVAL) {
8530                 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8531                 return;
8532         }
8533
8534         /* Set valid module led off */
8535         bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8536
8537         /* Get current gpio val reflecting module plugged in / out*/
8538         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8539
8540         /* Call the handling function in case module is detected */
8541         if (gpio_val == 0) {
8542                 bnx2x_power_sfp_module(params, phy, 1);
8543                 bnx2x_set_gpio_int(bp, gpio_num,
8544                                    MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8545                                    gpio_port);
8546                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
8547                         bnx2x_sfp_module_detection(phy, params);
8548                 else
8549                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8550         } else {
8551                 u32 val = REG_RD(bp, params->shmem_base +
8552                                  offsetof(struct shmem_region, dev_info.
8553                                           port_feature_config[params->port].
8554                                           config));
8555                 bnx2x_set_gpio_int(bp, gpio_num,
8556                                    MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8557                                    gpio_port);
8558                 /* Module was plugged out.
8559                  * Disable transmit for this module
8560                  */
8561                 phy->media_type = ETH_PHY_NOT_PRESENT;
8562                 if (((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8563                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) ||
8564                     CHIP_IS_E3(bp))
8565                         bnx2x_sfp_set_transmitter(params, phy, 0);
8566         }
8567 }
8568
8569 /******************************************************************/
8570 /*              Used by 8706 and 8727                             */
8571 /******************************************************************/
8572 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8573                                  struct bnx2x_phy *phy,
8574                                  u16 alarm_status_offset,
8575                                  u16 alarm_ctrl_offset)
8576 {
8577         u16 alarm_status, val;
8578         bnx2x_cl45_read(bp, phy,
8579                         MDIO_PMA_DEVAD, alarm_status_offset,
8580                         &alarm_status);
8581         bnx2x_cl45_read(bp, phy,
8582                         MDIO_PMA_DEVAD, alarm_status_offset,
8583                         &alarm_status);
8584         /* Mask or enable the fault event. */
8585         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8586         if (alarm_status & (1<<0))
8587                 val &= ~(1<<0);
8588         else
8589                 val |= (1<<0);
8590         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8591 }
8592 /******************************************************************/
8593 /*              common BCM8706/BCM8726 PHY SECTION                */
8594 /******************************************************************/
8595 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8596                                       struct link_params *params,
8597                                       struct link_vars *vars)
8598 {
8599         u8 link_up = 0;
8600         u16 val1, val2, rx_sd, pcs_status;
8601         struct bnx2x *bp = params->bp;
8602         DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8603         /* Clear RX Alarm*/
8604         bnx2x_cl45_read(bp, phy,
8605                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8606
8607         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8608                              MDIO_PMA_LASI_TXCTRL);
8609
8610         /* clear LASI indication*/
8611         bnx2x_cl45_read(bp, phy,
8612                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8613         bnx2x_cl45_read(bp, phy,
8614                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8615         DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8616
8617         bnx2x_cl45_read(bp, phy,
8618                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8619         bnx2x_cl45_read(bp, phy,
8620                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8621         bnx2x_cl45_read(bp, phy,
8622                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8623         bnx2x_cl45_read(bp, phy,
8624                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8625
8626         DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8627                         " link_status 0x%x\n", rx_sd, pcs_status, val2);
8628         /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8629          * are set, or if the autoneg bit 1 is set
8630          */
8631         link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8632         if (link_up) {
8633                 if (val2 & (1<<1))
8634                         vars->line_speed = SPEED_1000;
8635                 else
8636                         vars->line_speed = SPEED_10000;
8637                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8638                 vars->duplex = DUPLEX_FULL;
8639         }
8640
8641         /* Capture 10G link fault. Read twice to clear stale value. */
8642         if (vars->line_speed == SPEED_10000) {
8643                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8644                             MDIO_PMA_LASI_TXSTAT, &val1);
8645                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8646                             MDIO_PMA_LASI_TXSTAT, &val1);
8647                 if (val1 & (1<<0))
8648                         vars->fault_detected = 1;
8649         }
8650
8651         return link_up;
8652 }
8653
8654 /******************************************************************/
8655 /*                      BCM8706 PHY SECTION                       */
8656 /******************************************************************/
8657 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8658                                  struct link_params *params,
8659                                  struct link_vars *vars)
8660 {
8661         u32 tx_en_mode;
8662         u16 cnt, val, tmp1;
8663         struct bnx2x *bp = params->bp;
8664
8665         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8666                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8667         /* HW reset */
8668         bnx2x_ext_phy_hw_reset(bp, params->port);
8669         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8670         bnx2x_wait_reset_complete(bp, phy, params);
8671
8672         /* Wait until fw is loaded */
8673         for (cnt = 0; cnt < 100; cnt++) {
8674                 bnx2x_cl45_read(bp, phy,
8675                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8676                 if (val)
8677                         break;
8678                 msleep(10);
8679         }
8680         DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8681         if ((params->feature_config_flags &
8682              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8683                 u8 i;
8684                 u16 reg;
8685                 for (i = 0; i < 4; i++) {
8686                         reg = MDIO_XS_8706_REG_BANK_RX0 +
8687                                 i*(MDIO_XS_8706_REG_BANK_RX1 -
8688                                    MDIO_XS_8706_REG_BANK_RX0);
8689                         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8690                         /* Clear first 3 bits of the control */
8691                         val &= ~0x7;
8692                         /* Set control bits according to configuration */
8693                         val |= (phy->rx_preemphasis[i] & 0x7);
8694                         DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8695                                    " reg 0x%x <-- val 0x%x\n", reg, val);
8696                         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8697                 }
8698         }
8699         /* Force speed */
8700         if (phy->req_line_speed == SPEED_10000) {
8701                 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8702
8703                 bnx2x_cl45_write(bp, phy,
8704                                  MDIO_PMA_DEVAD,
8705                                  MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8706                 bnx2x_cl45_write(bp, phy,
8707                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8708                                  0);
8709                 /* Arm LASI for link and Tx fault. */
8710                 bnx2x_cl45_write(bp, phy,
8711                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8712         } else {
8713                 /* Force 1Gbps using autoneg with 1G advertisement */
8714
8715                 /* Allow CL37 through CL73 */
8716                 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8717                 bnx2x_cl45_write(bp, phy,
8718                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8719
8720                 /* Enable Full-Duplex advertisement on CL37 */
8721                 bnx2x_cl45_write(bp, phy,
8722                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8723                 /* Enable CL37 AN */
8724                 bnx2x_cl45_write(bp, phy,
8725                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8726                 /* 1G support */
8727                 bnx2x_cl45_write(bp, phy,
8728                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8729
8730                 /* Enable clause 73 AN */
8731                 bnx2x_cl45_write(bp, phy,
8732                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8733                 bnx2x_cl45_write(bp, phy,
8734                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8735                                  0x0400);
8736                 bnx2x_cl45_write(bp, phy,
8737                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8738                                  0x0004);
8739         }
8740         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8741
8742         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8743          * power mode, if TX Laser is disabled
8744          */
8745
8746         tx_en_mode = REG_RD(bp, params->shmem_base +
8747                             offsetof(struct shmem_region,
8748                                 dev_info.port_hw_config[params->port].sfp_ctrl))
8749                         & PORT_HW_CFG_TX_LASER_MASK;
8750
8751         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8752                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8753                 bnx2x_cl45_read(bp, phy,
8754                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8755                 tmp1 |= 0x1;
8756                 bnx2x_cl45_write(bp, phy,
8757                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8758         }
8759
8760         return 0;
8761 }
8762
8763 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8764                                   struct link_params *params,
8765                                   struct link_vars *vars)
8766 {
8767         return bnx2x_8706_8726_read_status(phy, params, vars);
8768 }
8769
8770 /******************************************************************/
8771 /*                      BCM8726 PHY SECTION                       */
8772 /******************************************************************/
8773 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8774                                        struct link_params *params)
8775 {
8776         struct bnx2x *bp = params->bp;
8777         DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8778         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8779 }
8780
8781 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8782                                          struct link_params *params)
8783 {
8784         struct bnx2x *bp = params->bp;
8785         /* Need to wait 100ms after reset */
8786         msleep(100);
8787
8788         /* Micro controller re-boot */
8789         bnx2x_cl45_write(bp, phy,
8790                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8791
8792         /* Set soft reset */
8793         bnx2x_cl45_write(bp, phy,
8794                          MDIO_PMA_DEVAD,
8795                          MDIO_PMA_REG_GEN_CTRL,
8796                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8797
8798         bnx2x_cl45_write(bp, phy,
8799                          MDIO_PMA_DEVAD,
8800                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8801
8802         bnx2x_cl45_write(bp, phy,
8803                          MDIO_PMA_DEVAD,
8804                          MDIO_PMA_REG_GEN_CTRL,
8805                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8806
8807         /* wait for 150ms for microcode load */
8808         msleep(150);
8809
8810         /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8811         bnx2x_cl45_write(bp, phy,
8812                          MDIO_PMA_DEVAD,
8813                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8814
8815         msleep(200);
8816         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8817 }
8818
8819 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
8820                                  struct link_params *params,
8821                                  struct link_vars *vars)
8822 {
8823         struct bnx2x *bp = params->bp;
8824         u16 val1;
8825         u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
8826         if (link_up) {
8827                 bnx2x_cl45_read(bp, phy,
8828                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8829                                 &val1);
8830                 if (val1 & (1<<15)) {
8831                         DP(NETIF_MSG_LINK, "Tx is disabled\n");
8832                         link_up = 0;
8833                         vars->line_speed = 0;
8834                 }
8835         }
8836         return link_up;
8837 }
8838
8839
8840 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
8841                                   struct link_params *params,
8842                                   struct link_vars *vars)
8843 {
8844         struct bnx2x *bp = params->bp;
8845         DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
8846
8847         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
8848         bnx2x_wait_reset_complete(bp, phy, params);
8849
8850         bnx2x_8726_external_rom_boot(phy, params);
8851
8852         /* Need to call module detected on initialization since the module
8853          * detection triggered by actual module insertion might occur before
8854          * driver is loaded, and when driver is loaded, it reset all
8855          * registers, including the transmitter
8856          */
8857         bnx2x_sfp_module_detection(phy, params);
8858
8859         if (phy->req_line_speed == SPEED_1000) {
8860                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8861                 bnx2x_cl45_write(bp, phy,
8862                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8863                 bnx2x_cl45_write(bp, phy,
8864                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8865                 bnx2x_cl45_write(bp, phy,
8866                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
8867                 bnx2x_cl45_write(bp, phy,
8868                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8869                                  0x400);
8870         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8871                    (phy->speed_cap_mask &
8872                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
8873                    ((phy->speed_cap_mask &
8874                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8875                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8876                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8877                 /* Set Flow control */
8878                 bnx2x_ext_phy_set_pause(params, phy, vars);
8879                 bnx2x_cl45_write(bp, phy,
8880                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
8881                 bnx2x_cl45_write(bp, phy,
8882                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8883                 bnx2x_cl45_write(bp, phy,
8884                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
8885                 bnx2x_cl45_write(bp, phy,
8886                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8887                 bnx2x_cl45_write(bp, phy,
8888                                 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8889                 /* Enable RX-ALARM control to receive interrupt for 1G speed
8890                  * change
8891                  */
8892                 bnx2x_cl45_write(bp, phy,
8893                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
8894                 bnx2x_cl45_write(bp, phy,
8895                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8896                                  0x400);
8897
8898         } else { /* Default 10G. Set only LASI control */
8899                 bnx2x_cl45_write(bp, phy,
8900                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
8901         }
8902
8903         /* Set TX PreEmphasis if needed */
8904         if ((params->feature_config_flags &
8905              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8906                 DP(NETIF_MSG_LINK,
8907                    "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
8908                          phy->tx_preemphasis[0],
8909                          phy->tx_preemphasis[1]);
8910                 bnx2x_cl45_write(bp, phy,
8911                                  MDIO_PMA_DEVAD,
8912                                  MDIO_PMA_REG_8726_TX_CTRL1,
8913                                  phy->tx_preemphasis[0]);
8914
8915                 bnx2x_cl45_write(bp, phy,
8916                                  MDIO_PMA_DEVAD,
8917                                  MDIO_PMA_REG_8726_TX_CTRL2,
8918                                  phy->tx_preemphasis[1]);
8919         }
8920
8921         return 0;
8922
8923 }
8924
8925 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
8926                                   struct link_params *params)
8927 {
8928         struct bnx2x *bp = params->bp;
8929         DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
8930         /* Set serial boot control for external load */
8931         bnx2x_cl45_write(bp, phy,
8932                          MDIO_PMA_DEVAD,
8933                          MDIO_PMA_REG_GEN_CTRL, 0x0001);
8934 }
8935
8936 /******************************************************************/
8937 /*                      BCM8727 PHY SECTION                       */
8938 /******************************************************************/
8939
8940 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
8941                                     struct link_params *params, u8 mode)
8942 {
8943         struct bnx2x *bp = params->bp;
8944         u16 led_mode_bitmask = 0;
8945         u16 gpio_pins_bitmask = 0;
8946         u16 val;
8947         /* Only NOC flavor requires to set the LED specifically */
8948         if (!(phy->flags & FLAGS_NOC))
8949                 return;
8950         switch (mode) {
8951         case LED_MODE_FRONT_PANEL_OFF:
8952         case LED_MODE_OFF:
8953                 led_mode_bitmask = 0;
8954                 gpio_pins_bitmask = 0x03;
8955                 break;
8956         case LED_MODE_ON:
8957                 led_mode_bitmask = 0;
8958                 gpio_pins_bitmask = 0x02;
8959                 break;
8960         case LED_MODE_OPER:
8961                 led_mode_bitmask = 0x60;
8962                 gpio_pins_bitmask = 0x11;
8963                 break;
8964         }
8965         bnx2x_cl45_read(bp, phy,
8966                         MDIO_PMA_DEVAD,
8967                         MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8968                         &val);
8969         val &= 0xff8f;
8970         val |= led_mode_bitmask;
8971         bnx2x_cl45_write(bp, phy,
8972                          MDIO_PMA_DEVAD,
8973                          MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8974                          val);
8975         bnx2x_cl45_read(bp, phy,
8976                         MDIO_PMA_DEVAD,
8977                         MDIO_PMA_REG_8727_GPIO_CTRL,
8978                         &val);
8979         val &= 0xffe0;
8980         val |= gpio_pins_bitmask;
8981         bnx2x_cl45_write(bp, phy,
8982                          MDIO_PMA_DEVAD,
8983                          MDIO_PMA_REG_8727_GPIO_CTRL,
8984                          val);
8985 }
8986 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
8987                                 struct link_params *params) {
8988         u32 swap_val, swap_override;
8989         u8 port;
8990         /* The PHY reset is controlled by GPIO 1. Fake the port number
8991          * to cancel the swap done in set_gpio()
8992          */
8993         struct bnx2x *bp = params->bp;
8994         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8995         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8996         port = (swap_val && swap_override) ^ 1;
8997         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
8998                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
8999 }
9000
9001 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
9002                                   struct link_params *params,
9003                                   struct link_vars *vars)
9004 {
9005         u32 tx_en_mode;
9006         u16 tmp1, val, mod_abs, tmp2;
9007         u16 rx_alarm_ctrl_val;
9008         u16 lasi_ctrl_val;
9009         struct bnx2x *bp = params->bp;
9010         /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
9011
9012         bnx2x_wait_reset_complete(bp, phy, params);
9013         rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
9014         /* Should be 0x6 to enable XS on Tx side. */
9015         lasi_ctrl_val = 0x0006;
9016
9017         DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
9018         /* enable LASI */
9019         bnx2x_cl45_write(bp, phy,
9020                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9021                          rx_alarm_ctrl_val);
9022         bnx2x_cl45_write(bp, phy,
9023                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
9024                          0);
9025         bnx2x_cl45_write(bp, phy,
9026                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, lasi_ctrl_val);
9027
9028         /* Initially configure MOD_ABS to interrupt when module is
9029          * presence( bit 8)
9030          */
9031         bnx2x_cl45_read(bp, phy,
9032                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9033         /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
9034          * When the EDC is off it locks onto a reference clock and avoids
9035          * becoming 'lost'
9036          */
9037         mod_abs &= ~(1<<8);
9038         if (!(phy->flags & FLAGS_NOC))
9039                 mod_abs &= ~(1<<9);
9040         bnx2x_cl45_write(bp, phy,
9041                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9042
9043
9044         /* Enable/Disable PHY transmitter output */
9045         bnx2x_set_disable_pmd_transmit(params, phy, 0);
9046
9047         /* Make MOD_ABS give interrupt on change */
9048         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9049                         &val);
9050         val |= (1<<12);
9051         if (phy->flags & FLAGS_NOC)
9052                 val |= (3<<5);
9053
9054         /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
9055          * status which reflect SFP+ module over-current
9056          */
9057         if (!(phy->flags & FLAGS_NOC))
9058                 val &= 0xff8f; /* Reset bits 4-6 */
9059         bnx2x_cl45_write(bp, phy,
9060                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
9061
9062         bnx2x_8727_power_module(bp, phy, 1);
9063
9064         bnx2x_cl45_read(bp, phy,
9065                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
9066
9067         bnx2x_cl45_read(bp, phy,
9068                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
9069
9070         /* Set option 1G speed */
9071         if (phy->req_line_speed == SPEED_1000) {
9072                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9073                 bnx2x_cl45_write(bp, phy,
9074                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9075                 bnx2x_cl45_write(bp, phy,
9076                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9077                 bnx2x_cl45_read(bp, phy,
9078                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
9079                 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
9080                 /* Power down the XAUI until link is up in case of dual-media
9081                  * and 1G
9082                  */
9083                 if (DUAL_MEDIA(params)) {
9084                         bnx2x_cl45_read(bp, phy,
9085                                         MDIO_PMA_DEVAD,
9086                                         MDIO_PMA_REG_8727_PCS_GP, &val);
9087                         val |= (3<<10);
9088                         bnx2x_cl45_write(bp, phy,
9089                                          MDIO_PMA_DEVAD,
9090                                          MDIO_PMA_REG_8727_PCS_GP, val);
9091                 }
9092         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9093                    ((phy->speed_cap_mask &
9094                      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
9095                    ((phy->speed_cap_mask &
9096                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9097                    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9098
9099                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9100                 bnx2x_cl45_write(bp, phy,
9101                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
9102                 bnx2x_cl45_write(bp, phy,
9103                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
9104         } else {
9105                 /* Since the 8727 has only single reset pin, need to set the 10G
9106                  * registers although it is default
9107                  */
9108                 bnx2x_cl45_write(bp, phy,
9109                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
9110                                  0x0020);
9111                 bnx2x_cl45_write(bp, phy,
9112                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
9113                 bnx2x_cl45_write(bp, phy,
9114                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
9115                 bnx2x_cl45_write(bp, phy,
9116                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
9117                                  0x0008);
9118         }
9119
9120         /* Set 2-wire transfer rate of SFP+ module EEPROM
9121          * to 100Khz since some DACs(direct attached cables) do
9122          * not work at 400Khz.
9123          */
9124         bnx2x_cl45_write(bp, phy,
9125                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
9126                          0xa001);
9127
9128         /* Set TX PreEmphasis if needed */
9129         if ((params->feature_config_flags &
9130              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9131                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9132                            phy->tx_preemphasis[0],
9133                            phy->tx_preemphasis[1]);
9134                 bnx2x_cl45_write(bp, phy,
9135                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
9136                                  phy->tx_preemphasis[0]);
9137
9138                 bnx2x_cl45_write(bp, phy,
9139                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
9140                                  phy->tx_preemphasis[1]);
9141         }
9142
9143         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
9144          * power mode, if TX Laser is disabled
9145          */
9146         tx_en_mode = REG_RD(bp, params->shmem_base +
9147                             offsetof(struct shmem_region,
9148                                 dev_info.port_hw_config[params->port].sfp_ctrl))
9149                         & PORT_HW_CFG_TX_LASER_MASK;
9150
9151         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9152
9153                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
9154                 bnx2x_cl45_read(bp, phy,
9155                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
9156                 tmp2 |= 0x1000;
9157                 tmp2 &= 0xFFEF;
9158                 bnx2x_cl45_write(bp, phy,
9159                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
9160                 bnx2x_cl45_read(bp, phy,
9161                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9162                                 &tmp2);
9163                 bnx2x_cl45_write(bp, phy,
9164                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9165                                  (tmp2 & 0x7fff));
9166         }
9167
9168         return 0;
9169 }
9170
9171 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9172                                       struct link_params *params)
9173 {
9174         struct bnx2x *bp = params->bp;
9175         u16 mod_abs, rx_alarm_status;
9176         u32 val = REG_RD(bp, params->shmem_base +
9177                              offsetof(struct shmem_region, dev_info.
9178                                       port_feature_config[params->port].
9179                                       config));
9180         bnx2x_cl45_read(bp, phy,
9181                         MDIO_PMA_DEVAD,
9182                         MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9183         if (mod_abs & (1<<8)) {
9184
9185                 /* Module is absent */
9186                 DP(NETIF_MSG_LINK,
9187                    "MOD_ABS indication show module is absent\n");
9188                 phy->media_type = ETH_PHY_NOT_PRESENT;
9189                 /* 1. Set mod_abs to detect next module
9190                  *    presence event
9191                  * 2. Set EDC off by setting OPTXLOS signal input to low
9192                  *    (bit 9).
9193                  *    When the EDC is off it locks onto a reference clock and
9194                  *    avoids becoming 'lost'.
9195                  */
9196                 mod_abs &= ~(1<<8);
9197                 if (!(phy->flags & FLAGS_NOC))
9198                         mod_abs &= ~(1<<9);
9199                 bnx2x_cl45_write(bp, phy,
9200                                  MDIO_PMA_DEVAD,
9201                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9202
9203                 /* Clear RX alarm since it stays up as long as
9204                  * the mod_abs wasn't changed
9205                  */
9206                 bnx2x_cl45_read(bp, phy,
9207                                 MDIO_PMA_DEVAD,
9208                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9209
9210         } else {
9211                 /* Module is present */
9212                 DP(NETIF_MSG_LINK,
9213                    "MOD_ABS indication show module is present\n");
9214                 /* First disable transmitter, and if the module is ok, the
9215                  * module_detection will enable it
9216                  * 1. Set mod_abs to detect next module absent event ( bit 8)
9217                  * 2. Restore the default polarity of the OPRXLOS signal and
9218                  * this signal will then correctly indicate the presence or
9219                  * absence of the Rx signal. (bit 9)
9220                  */
9221                 mod_abs |= (1<<8);
9222                 if (!(phy->flags & FLAGS_NOC))
9223                         mod_abs |= (1<<9);
9224                 bnx2x_cl45_write(bp, phy,
9225                                  MDIO_PMA_DEVAD,
9226                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9227
9228                 /* Clear RX alarm since it stays up as long as the mod_abs
9229                  * wasn't changed. This is need to be done before calling the
9230                  * module detection, otherwise it will clear* the link update
9231                  * alarm
9232                  */
9233                 bnx2x_cl45_read(bp, phy,
9234                                 MDIO_PMA_DEVAD,
9235                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9236
9237
9238                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9239                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
9240                         bnx2x_sfp_set_transmitter(params, phy, 0);
9241
9242                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
9243                         bnx2x_sfp_module_detection(phy, params);
9244                 else
9245                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
9246         }
9247
9248         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
9249                    rx_alarm_status);
9250         /* No need to check link status in case of module plugged in/out */
9251 }
9252
9253 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9254                                  struct link_params *params,
9255                                  struct link_vars *vars)
9256
9257 {
9258         struct bnx2x *bp = params->bp;
9259         u8 link_up = 0, oc_port = params->port;
9260         u16 link_status = 0;
9261         u16 rx_alarm_status, lasi_ctrl, val1;
9262
9263         /* If PHY is not initialized, do not check link status */
9264         bnx2x_cl45_read(bp, phy,
9265                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9266                         &lasi_ctrl);
9267         if (!lasi_ctrl)
9268                 return 0;
9269
9270         /* Check the LASI on Rx */
9271         bnx2x_cl45_read(bp, phy,
9272                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
9273                         &rx_alarm_status);
9274         vars->line_speed = 0;
9275         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);
9276
9277         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
9278                              MDIO_PMA_LASI_TXCTRL);
9279
9280         bnx2x_cl45_read(bp, phy,
9281                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9282
9283         DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
9284
9285         /* Clear MSG-OUT */
9286         bnx2x_cl45_read(bp, phy,
9287                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
9288
9289         /* If a module is present and there is need to check
9290          * for over current
9291          */
9292         if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
9293                 /* Check over-current using 8727 GPIO0 input*/
9294                 bnx2x_cl45_read(bp, phy,
9295                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
9296                                 &val1);
9297
9298                 if ((val1 & (1<<8)) == 0) {
9299                         if (!CHIP_IS_E1x(bp))
9300                                 oc_port = BP_PATH(bp) + (params->port << 1);
9301                         DP(NETIF_MSG_LINK,
9302                            "8727 Power fault has been detected on port %d\n",
9303                            oc_port);
9304                         netdev_err(bp->dev, "Error: Power fault on Port %d has "
9305                                             "been detected and the power to "
9306                                             "that SFP+ module has been removed "
9307                                             "to prevent failure of the card. "
9308                                             "Please remove the SFP+ module and "
9309                                             "restart the system to clear this "
9310                                             "error.\n",
9311                          oc_port);
9312                         /* Disable all RX_ALARMs except for mod_abs */
9313                         bnx2x_cl45_write(bp, phy,
9314                                          MDIO_PMA_DEVAD,
9315                                          MDIO_PMA_LASI_RXCTRL, (1<<5));
9316
9317                         bnx2x_cl45_read(bp, phy,
9318                                         MDIO_PMA_DEVAD,
9319                                         MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9320                         /* Wait for module_absent_event */
9321                         val1 |= (1<<8);
9322                         bnx2x_cl45_write(bp, phy,
9323                                          MDIO_PMA_DEVAD,
9324                                          MDIO_PMA_REG_PHY_IDENTIFIER, val1);
9325                         /* Clear RX alarm */
9326                         bnx2x_cl45_read(bp, phy,
9327                                 MDIO_PMA_DEVAD,
9328                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9329                         return 0;
9330                 }
9331         } /* Over current check */
9332
9333         /* When module absent bit is set, check module */
9334         if (rx_alarm_status & (1<<5)) {
9335                 bnx2x_8727_handle_mod_abs(phy, params);
9336                 /* Enable all mod_abs and link detection bits */
9337                 bnx2x_cl45_write(bp, phy,
9338                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9339                                  ((1<<5) | (1<<2)));
9340         }
9341
9342         if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
9343                 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n");
9344                 bnx2x_sfp_set_transmitter(params, phy, 1);
9345         } else {
9346                 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9347                 return 0;
9348         }
9349
9350         bnx2x_cl45_read(bp, phy,
9351                         MDIO_PMA_DEVAD,
9352                         MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
9353
9354         /* Bits 0..2 --> speed detected,
9355          * Bits 13..15--> link is down
9356          */
9357         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
9358                 link_up = 1;
9359                 vars->line_speed = SPEED_10000;
9360                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
9361                            params->port);
9362         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
9363                 link_up = 1;
9364                 vars->line_speed = SPEED_1000;
9365                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
9366                            params->port);
9367         } else {
9368                 link_up = 0;
9369                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
9370                            params->port);
9371         }
9372
9373         /* Capture 10G link fault. */
9374         if (vars->line_speed == SPEED_10000) {
9375                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9376                             MDIO_PMA_LASI_TXSTAT, &val1);
9377
9378                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9379                             MDIO_PMA_LASI_TXSTAT, &val1);
9380
9381                 if (val1 & (1<<0)) {
9382                         vars->fault_detected = 1;
9383                 }
9384         }
9385
9386         if (link_up) {
9387                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9388                 vars->duplex = DUPLEX_FULL;
9389                 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9390         }
9391
9392         if ((DUAL_MEDIA(params)) &&
9393             (phy->req_line_speed == SPEED_1000)) {
9394                 bnx2x_cl45_read(bp, phy,
9395                                 MDIO_PMA_DEVAD,
9396                                 MDIO_PMA_REG_8727_PCS_GP, &val1);
9397                 /* In case of dual-media board and 1G, power up the XAUI side,
9398                  * otherwise power it down. For 10G it is done automatically
9399                  */
9400                 if (link_up)
9401                         val1 &= ~(3<<10);
9402                 else
9403                         val1 |= (3<<10);
9404                 bnx2x_cl45_write(bp, phy,
9405                                  MDIO_PMA_DEVAD,
9406                                  MDIO_PMA_REG_8727_PCS_GP, val1);
9407         }
9408         return link_up;
9409 }
9410
9411 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9412                                   struct link_params *params)
9413 {
9414         struct bnx2x *bp = params->bp;
9415
9416         /* Enable/Disable PHY transmitter output */
9417         bnx2x_set_disable_pmd_transmit(params, phy, 1);
9418
9419         /* Disable Transmitter */
9420         bnx2x_sfp_set_transmitter(params, phy, 0);
9421         /* Clear LASI */
9422         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9423
9424 }
9425
9426 /******************************************************************/
9427 /*              BCM8481/BCM84823/BCM84833 PHY SECTION             */
9428 /******************************************************************/
9429 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9430                                             struct bnx2x *bp,
9431                                             u8 port)
9432 {
9433         u16 val, fw_ver1, fw_ver2, cnt;
9434
9435         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9436                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
9437                 bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff,
9438                                 phy->ver_addr);
9439         } else {
9440                 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9441                 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9442                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
9443                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9444                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
9445                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
9446                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
9447
9448                 for (cnt = 0; cnt < 100; cnt++) {
9449                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9450                         if (val & 1)
9451                                 break;
9452                         udelay(5);
9453                 }
9454                 if (cnt == 100) {
9455                         DP(NETIF_MSG_LINK, "Unable to read 848xx "
9456                                         "phy fw version(1)\n");
9457                         bnx2x_save_spirom_version(bp, port, 0,
9458                                                   phy->ver_addr);
9459                         return;
9460                 }
9461
9462
9463                 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9464                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9465                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9466                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9467                 for (cnt = 0; cnt < 100; cnt++) {
9468                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9469                         if (val & 1)
9470                                 break;
9471                         udelay(5);
9472                 }
9473                 if (cnt == 100) {
9474                         DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw "
9475                                         "version(2)\n");
9476                         bnx2x_save_spirom_version(bp, port, 0,
9477                                                   phy->ver_addr);
9478                         return;
9479                 }
9480
9481                 /* lower 16 bits of the register SPI_FW_STATUS */
9482                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9483                 /* upper 16 bits of register SPI_FW_STATUS */
9484                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9485
9486                 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9487                                           phy->ver_addr);
9488         }
9489
9490 }
9491 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9492                                 struct bnx2x_phy *phy)
9493 {
9494         u16 val, offset;
9495
9496         /* PHYC_CTL_LED_CTL */
9497         bnx2x_cl45_read(bp, phy,
9498                         MDIO_PMA_DEVAD,
9499                         MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9500         val &= 0xFE00;
9501         val |= 0x0092;
9502
9503         bnx2x_cl45_write(bp, phy,
9504                          MDIO_PMA_DEVAD,
9505                          MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9506
9507         bnx2x_cl45_write(bp, phy,
9508                          MDIO_PMA_DEVAD,
9509                          MDIO_PMA_REG_8481_LED1_MASK,
9510                          0x80);
9511
9512         bnx2x_cl45_write(bp, phy,
9513                          MDIO_PMA_DEVAD,
9514                          MDIO_PMA_REG_8481_LED2_MASK,
9515                          0x18);
9516
9517         /* Select activity source by Tx and Rx, as suggested by PHY AE */
9518         bnx2x_cl45_write(bp, phy,
9519                          MDIO_PMA_DEVAD,
9520                          MDIO_PMA_REG_8481_LED3_MASK,
9521                          0x0006);
9522
9523         /* Select the closest activity blink rate to that in 10/100/1000 */
9524         bnx2x_cl45_write(bp, phy,
9525                         MDIO_PMA_DEVAD,
9526                         MDIO_PMA_REG_8481_LED3_BLINK,
9527                         0);
9528
9529         /* Configure the blink rate to ~15.9 Hz */
9530         bnx2x_cl45_write(bp, phy,
9531                         MDIO_PMA_DEVAD,
9532                         MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9533                         MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ);
9534
9535         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9536                 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9537         else
9538                 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9539
9540         bnx2x_cl45_read(bp, phy,
9541                         MDIO_PMA_DEVAD, offset, &val);
9542         val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/
9543         bnx2x_cl45_write(bp, phy,
9544                          MDIO_PMA_DEVAD, offset, val);
9545
9546         /* 'Interrupt Mask' */
9547         bnx2x_cl45_write(bp, phy,
9548                          MDIO_AN_DEVAD,
9549                          0xFFFB, 0xFFFD);
9550 }
9551
9552 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9553                                        struct link_params *params,
9554                                        struct link_vars *vars)
9555 {
9556         struct bnx2x *bp = params->bp;
9557         u16 autoneg_val, an_1000_val, an_10_100_val, an_10g_val;
9558
9559         if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9560                 /* Save spirom version */
9561                 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9562         }
9563         /* This phy uses the NIG latch mechanism since link indication
9564          * arrives through its LED4 and not via its LASI signal, so we
9565          * get steady signal instead of clear on read
9566          */
9567         bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9568                       1 << NIG_LATCH_BC_ENABLE_MI_INT);
9569
9570         bnx2x_cl45_write(bp, phy,
9571                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9572
9573         bnx2x_848xx_set_led(bp, phy);
9574
9575         /* set 1000 speed advertisement */
9576         bnx2x_cl45_read(bp, phy,
9577                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9578                         &an_1000_val);
9579
9580         bnx2x_ext_phy_set_pause(params, phy, vars);
9581         bnx2x_cl45_read(bp, phy,
9582                         MDIO_AN_DEVAD,
9583                         MDIO_AN_REG_8481_LEGACY_AN_ADV,
9584                         &an_10_100_val);
9585         bnx2x_cl45_read(bp, phy,
9586                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9587                         &autoneg_val);
9588         /* Disable forced speed */
9589         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9590         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9591
9592         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9593              (phy->speed_cap_mask &
9594              PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9595             (phy->req_line_speed == SPEED_1000)) {
9596                 an_1000_val |= (1<<8);
9597                 autoneg_val |= (1<<9 | 1<<12);
9598                 if (phy->req_duplex == DUPLEX_FULL)
9599                         an_1000_val |= (1<<9);
9600                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9601         } else
9602                 an_1000_val &= ~((1<<8) | (1<<9));
9603
9604         bnx2x_cl45_write(bp, phy,
9605                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9606                          an_1000_val);
9607
9608         /* set 100 speed advertisement */
9609         if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9610              (phy->speed_cap_mask &
9611               (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
9612                PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))) {
9613                 an_10_100_val |= (1<<7);
9614                 /* Enable autoneg and restart autoneg for legacy speeds */
9615                 autoneg_val |= (1<<9 | 1<<12);
9616
9617                 if (phy->req_duplex == DUPLEX_FULL)
9618                         an_10_100_val |= (1<<8);
9619                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
9620         }
9621         /* set 10 speed advertisement */
9622         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9623              (phy->speed_cap_mask &
9624               (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
9625                PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
9626              (phy->supported &
9627               (SUPPORTED_10baseT_Half |
9628                SUPPORTED_10baseT_Full)))) {
9629                 an_10_100_val |= (1<<5);
9630                 autoneg_val |= (1<<9 | 1<<12);
9631                 if (phy->req_duplex == DUPLEX_FULL)
9632                         an_10_100_val |= (1<<6);
9633                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
9634         }
9635
9636         /* Only 10/100 are allowed to work in FORCE mode */
9637         if ((phy->req_line_speed == SPEED_100) &&
9638             (phy->supported &
9639              (SUPPORTED_100baseT_Half |
9640               SUPPORTED_100baseT_Full))) {
9641                 autoneg_val |= (1<<13);
9642                 /* Enabled AUTO-MDIX when autoneg is disabled */
9643                 bnx2x_cl45_write(bp, phy,
9644                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9645                                  (1<<15 | 1<<9 | 7<<0));
9646                 /* The PHY needs this set even for forced link. */
9647                 an_10_100_val |= (1<<8) | (1<<7);
9648                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9649         }
9650         if ((phy->req_line_speed == SPEED_10) &&
9651             (phy->supported &
9652              (SUPPORTED_10baseT_Half |
9653               SUPPORTED_10baseT_Full))) {
9654                 /* Enabled AUTO-MDIX when autoneg is disabled */
9655                 bnx2x_cl45_write(bp, phy,
9656                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9657                                  (1<<15 | 1<<9 | 7<<0));
9658                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9659         }
9660
9661         bnx2x_cl45_write(bp, phy,
9662                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9663                          an_10_100_val);
9664
9665         if (phy->req_duplex == DUPLEX_FULL)
9666                 autoneg_val |= (1<<8);
9667
9668         /* Always write this if this is not 84833.
9669          * For 84833, write it only when it's a forced speed.
9670          */
9671         if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9672                 ((autoneg_val & (1<<12)) == 0))
9673                 bnx2x_cl45_write(bp, phy,
9674                          MDIO_AN_DEVAD,
9675                          MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9676
9677         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9678             (phy->speed_cap_mask &
9679              PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9680                 (phy->req_line_speed == SPEED_10000)) {
9681                         DP(NETIF_MSG_LINK, "Advertising 10G\n");
9682                         /* Restart autoneg for 10G*/
9683
9684                         bnx2x_cl45_read(bp, phy,
9685                                         MDIO_AN_DEVAD,
9686                                         MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9687                                         &an_10g_val);
9688                         bnx2x_cl45_write(bp, phy,
9689                                          MDIO_AN_DEVAD,
9690                                          MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9691                                          an_10g_val | 0x1000);
9692                         bnx2x_cl45_write(bp, phy,
9693                                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9694                                          0x3200);
9695         } else
9696                 bnx2x_cl45_write(bp, phy,
9697                                  MDIO_AN_DEVAD,
9698                                  MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9699                                  1);
9700
9701         return 0;
9702 }
9703
9704 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9705                                   struct link_params *params,
9706                                   struct link_vars *vars)
9707 {
9708         struct bnx2x *bp = params->bp;
9709         /* Restore normal power mode*/
9710         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9711                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9712
9713         /* HW reset */
9714         bnx2x_ext_phy_hw_reset(bp, params->port);
9715         bnx2x_wait_reset_complete(bp, phy, params);
9716
9717         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9718         return bnx2x_848xx_cmn_config_init(phy, params, vars);
9719 }
9720
9721 #define PHY84833_CMDHDLR_WAIT 300
9722 #define PHY84833_CMDHDLR_MAX_ARGS 5
9723 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
9724                                    struct link_params *params,
9725                    u16 fw_cmd,
9726                    u16 cmd_args[], int argc)
9727 {
9728         int idx;
9729         u16 val;
9730         struct bnx2x *bp = params->bp;
9731         /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9732         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9733                         MDIO_84833_CMD_HDLR_STATUS,
9734                         PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9735         for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9736                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9737                                 MDIO_84833_CMD_HDLR_STATUS, &val);
9738                 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
9739                         break;
9740                 msleep(1);
9741         }
9742         if (idx >= PHY84833_CMDHDLR_WAIT) {
9743                 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
9744                 return -EINVAL;
9745         }
9746
9747         /* Prepare argument(s) and issue command */
9748         for (idx = 0; idx < argc; idx++) {
9749                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9750                                 MDIO_84833_CMD_HDLR_DATA1 + idx,
9751                                 cmd_args[idx]);
9752         }
9753         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9754                         MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
9755         for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9756                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9757                                 MDIO_84833_CMD_HDLR_STATUS, &val);
9758                 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
9759                         (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
9760                         break;
9761                 msleep(1);
9762         }
9763         if ((idx >= PHY84833_CMDHDLR_WAIT) ||
9764                 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
9765                 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
9766                 return -EINVAL;
9767         }
9768         /* Gather returning data */
9769         for (idx = 0; idx < argc; idx++) {
9770                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9771                                 MDIO_84833_CMD_HDLR_DATA1 + idx,
9772                                 &cmd_args[idx]);
9773         }
9774         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9775                         MDIO_84833_CMD_HDLR_STATUS,
9776                         PHY84833_STATUS_CMD_CLEAR_COMPLETE);
9777         return 0;
9778 }
9779
9780
9781 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9782                                    struct link_params *params,
9783                                    struct link_vars *vars)
9784 {
9785         u32 pair_swap;
9786         u16 data[PHY84833_CMDHDLR_MAX_ARGS];
9787         int status;
9788         struct bnx2x *bp = params->bp;
9789
9790         /* Check for configuration. */
9791         pair_swap = REG_RD(bp, params->shmem_base +
9792                            offsetof(struct shmem_region,
9793                         dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9794                 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9795
9796         if (pair_swap == 0)
9797                 return 0;
9798
9799         /* Only the second argument is used for this command */
9800         data[1] = (u16)pair_swap;
9801
9802         status = bnx2x_84833_cmd_hdlr(phy, params,
9803                 PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS);
9804         if (status == 0)
9805                 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]);
9806
9807         return status;
9808 }
9809
9810 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
9811                                       u32 shmem_base_path[],
9812                                       u32 chip_id)
9813 {
9814         u32 reset_pin[2];
9815         u32 idx;
9816         u8 reset_gpios;
9817         if (CHIP_IS_E3(bp)) {
9818                 /* Assume that these will be GPIOs, not EPIOs. */
9819                 for (idx = 0; idx < 2; idx++) {
9820                         /* Map config param to register bit. */
9821                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9822                                 offsetof(struct shmem_region,
9823                                 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9824                         reset_pin[idx] = (reset_pin[idx] &
9825                                 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9826                                 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9827                         reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9828                         reset_pin[idx] = (1 << reset_pin[idx]);
9829                 }
9830                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9831         } else {
9832                 /* E2, look from diff place of shmem. */
9833                 for (idx = 0; idx < 2; idx++) {
9834                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9835                                 offsetof(struct shmem_region,
9836                                 dev_info.port_hw_config[0].default_cfg));
9837                         reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9838                         reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9839                         reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9840                         reset_pin[idx] = (1 << reset_pin[idx]);
9841                 }
9842                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9843         }
9844
9845         return reset_gpios;
9846 }
9847
9848 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
9849                                 struct link_params *params)
9850 {
9851         struct bnx2x *bp = params->bp;
9852         u8 reset_gpios;
9853         u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
9854                                 offsetof(struct shmem2_region,
9855                                 other_shmem_base_addr));
9856
9857         u32 shmem_base_path[2];
9858
9859         /* Work around for 84833 LED failure inside RESET status */
9860         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
9861                 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9862                 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
9863         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
9864                 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
9865                 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
9866
9867         shmem_base_path[0] = params->shmem_base;
9868         shmem_base_path[1] = other_shmem_base_addr;
9869
9870         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
9871                                                   params->chip_id);
9872
9873         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9874         udelay(10);
9875         DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
9876                 reset_gpios);
9877
9878         return 0;
9879 }
9880
9881 static int bnx2x_8483x_eee_timers(struct link_params *params,
9882                                    struct link_vars *vars)
9883 {
9884         u32 eee_idle = 0, eee_mode;
9885         struct bnx2x *bp = params->bp;
9886
9887         eee_idle = bnx2x_eee_calc_timer(params);
9888
9889         if (eee_idle) {
9890                 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
9891                        eee_idle);
9892         } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) &&
9893                    (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) &&
9894                    (params->eee_mode & EEE_MODE_OUTPUT_TIME)) {
9895                 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n");
9896                 return -EINVAL;
9897         }
9898
9899         vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
9900         if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
9901                 /* eee_idle in 1u --> eee_status in 16u */
9902                 eee_idle >>= 4;
9903                 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
9904                                     SHMEM_EEE_TIME_OUTPUT_BIT;
9905         } else {
9906                 if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode))
9907                         return -EINVAL;
9908                 vars->eee_status |= eee_mode;
9909         }
9910
9911         return 0;
9912 }
9913
9914 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy,
9915                                    struct link_params *params,
9916                                    struct link_vars *vars)
9917 {
9918         int rc;
9919         struct bnx2x *bp = params->bp;
9920         u16 cmd_args = 0;
9921
9922         DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n");
9923
9924         /* Make Certain LPI is disabled */
9925         REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
9926         REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 0);
9927
9928         /* Prevent Phy from working in EEE and advertising it */
9929         rc = bnx2x_84833_cmd_hdlr(phy, params,
9930                 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
9931         if (rc != 0) {
9932                 DP(NETIF_MSG_LINK, "EEE disable failed.\n");
9933                 return rc;
9934         }
9935
9936         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0);
9937         vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
9938
9939         return 0;
9940 }
9941
9942 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy,
9943                                    struct link_params *params,
9944                                    struct link_vars *vars)
9945 {
9946         int rc;
9947         struct bnx2x *bp = params->bp;
9948         u16 cmd_args = 1;
9949
9950         DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n");
9951
9952         rc = bnx2x_84833_cmd_hdlr(phy, params,
9953                 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
9954         if (rc != 0) {
9955                 DP(NETIF_MSG_LINK, "EEE enable failed.\n");
9956                 return rc;
9957         }
9958
9959         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x8);
9960
9961         /* Mask events preventing LPI generation */
9962         REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
9963
9964         vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
9965         vars->eee_status |= (SHMEM_EEE_10G_ADV << SHMEM_EEE_ADV_STATUS_SHIFT);
9966
9967         return 0;
9968 }
9969
9970 #define PHY84833_CONSTANT_LATENCY 1193
9971 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
9972                                    struct link_params *params,
9973                                    struct link_vars *vars)
9974 {
9975         struct bnx2x *bp = params->bp;
9976         u8 port, initialize = 1;
9977         u16 val;
9978         u32 actual_phy_selection, cms_enable;
9979         u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
9980         int rc = 0;
9981
9982         msleep(1);
9983
9984         if (!(CHIP_IS_E1(bp)))
9985                 port = BP_PATH(bp);
9986         else
9987                 port = params->port;
9988
9989         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9990                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9991                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
9992                                port);
9993         } else {
9994                 /* MDIO reset */
9995                 bnx2x_cl45_write(bp, phy,
9996                                 MDIO_PMA_DEVAD,
9997                                 MDIO_PMA_REG_CTRL, 0x8000);
9998         }
9999
10000         bnx2x_wait_reset_complete(bp, phy, params);
10001
10002         /* Wait for GPHY to come out of reset */
10003         msleep(50);
10004         if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
10005                 /* BCM84823 requires that XGXS links up first @ 10G for normal
10006                  * behavior.
10007                  */
10008                 u16 temp;
10009                 temp = vars->line_speed;
10010                 vars->line_speed = SPEED_10000;
10011                 bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
10012                 bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
10013                 vars->line_speed = temp;
10014         }
10015
10016         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10017                         MDIO_CTL_REG_84823_MEDIA, &val);
10018         val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10019                  MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
10020                  MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
10021                  MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
10022                  MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
10023
10024         if (CHIP_IS_E3(bp)) {
10025                 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10026                          MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
10027         } else {
10028                 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
10029                         MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
10030         }
10031
10032         actual_phy_selection = bnx2x_phy_selection(params);
10033
10034         switch (actual_phy_selection) {
10035         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
10036                 /* Do nothing. Essentially this is like the priority copper */
10037                 break;
10038         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
10039                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
10040                 break;
10041         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
10042                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
10043                 break;
10044         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
10045                 /* Do nothing here. The first PHY won't be initialized at all */
10046                 break;
10047         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
10048                 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
10049                 initialize = 0;
10050                 break;
10051         }
10052         if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
10053                 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
10054
10055         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10056                          MDIO_CTL_REG_84823_MEDIA, val);
10057         DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
10058                    params->multi_phy_config, val);
10059
10060         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
10061                 bnx2x_84833_pair_swap_cfg(phy, params, vars);
10062
10063                 /* Keep AutogrEEEn disabled. */
10064                 cmd_args[0] = 0x0;
10065                 cmd_args[1] = 0x0;
10066                 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
10067                 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
10068                 rc = bnx2x_84833_cmd_hdlr(phy, params,
10069                         PHY84833_CMD_SET_EEE_MODE, cmd_args,
10070                         PHY84833_CMDHDLR_MAX_ARGS);
10071                 if (rc != 0)
10072                         DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
10073         }
10074         if (initialize)
10075                 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
10076         else
10077                 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
10078         /* 84833 PHY has a better feature and doesn't need to support this. */
10079         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10080                 cms_enable = REG_RD(bp, params->shmem_base +
10081                         offsetof(struct shmem_region,
10082                         dev_info.port_hw_config[params->port].default_cfg)) &
10083                         PORT_HW_CFG_ENABLE_CMS_MASK;
10084
10085                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10086                                 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
10087                 if (cms_enable)
10088                         val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
10089                 else
10090                         val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
10091                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10092                                  MDIO_CTL_REG_84823_USER_CTRL_REG, val);
10093         }
10094
10095         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10096                         MDIO_84833_TOP_CFG_FW_REV, &val);
10097
10098         /* Configure EEE support */
10099         if ((val >= MDIO_84833_TOP_CFG_FW_EEE) && bnx2x_eee_has_cap(params)) {
10100                 phy->flags |= FLAGS_EEE_10GBT;
10101                 vars->eee_status |= SHMEM_EEE_10G_ADV <<
10102                                     SHMEM_EEE_SUPPORTED_SHIFT;
10103                 /* Propogate params' bits --> vars (for migration exposure) */
10104                 if (params->eee_mode & EEE_MODE_ENABLE_LPI)
10105                         vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
10106                 else
10107                         vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
10108
10109                 if (params->eee_mode & EEE_MODE_ADV_LPI)
10110                         vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
10111                 else
10112                         vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
10113
10114                 rc = bnx2x_8483x_eee_timers(params, vars);
10115                 if (rc != 0) {
10116                         DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10117                         bnx2x_8483x_disable_eee(phy, params, vars);
10118                         return rc;
10119                 }
10120
10121                 if ((params->req_duplex[actual_phy_selection] == DUPLEX_FULL) &&
10122                     (params->eee_mode & EEE_MODE_ADV_LPI) &&
10123                     (bnx2x_eee_calc_timer(params) ||
10124                      !(params->eee_mode & EEE_MODE_ENABLE_LPI)))
10125                         rc = bnx2x_8483x_enable_eee(phy, params, vars);
10126                 else
10127                         rc = bnx2x_8483x_disable_eee(phy, params, vars);
10128                 if (rc != 0) {
10129                         DP(NETIF_MSG_LINK, "Failed to set EEE advertisment\n");
10130                         return rc;
10131                 }
10132         } else {
10133                 phy->flags &= ~FLAGS_EEE_10GBT;
10134                 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
10135         }
10136
10137         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
10138                 /* Bring PHY out of super isolate mode as the final step. */
10139                 bnx2x_cl45_read(bp, phy,
10140                                 MDIO_CTL_DEVAD,
10141                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
10142                 val &= ~MDIO_84833_SUPER_ISOLATE;
10143                 bnx2x_cl45_write(bp, phy,
10144                                 MDIO_CTL_DEVAD,
10145                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
10146         }
10147         return rc;
10148 }
10149
10150 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
10151                                   struct link_params *params,
10152                                   struct link_vars *vars)
10153 {
10154         struct bnx2x *bp = params->bp;
10155         u16 val, val1, val2;
10156         u8 link_up = 0;
10157
10158
10159         /* Check 10G-BaseT link status */
10160         /* Check PMD signal ok */
10161         bnx2x_cl45_read(bp, phy,
10162                         MDIO_AN_DEVAD, 0xFFFA, &val1);
10163         bnx2x_cl45_read(bp, phy,
10164                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
10165                         &val2);
10166         DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
10167
10168         /* Check link 10G */
10169         if (val2 & (1<<11)) {
10170                 vars->line_speed = SPEED_10000;
10171                 vars->duplex = DUPLEX_FULL;
10172                 link_up = 1;
10173                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10174         } else { /* Check Legacy speed link */
10175                 u16 legacy_status, legacy_speed;
10176
10177                 /* Enable expansion register 0x42 (Operation mode status) */
10178                 bnx2x_cl45_write(bp, phy,
10179                                  MDIO_AN_DEVAD,
10180                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
10181
10182                 /* Get legacy speed operation status */
10183                 bnx2x_cl45_read(bp, phy,
10184                                 MDIO_AN_DEVAD,
10185                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
10186                                 &legacy_status);
10187
10188                 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
10189                    legacy_status);
10190                 link_up = ((legacy_status & (1<<11)) == (1<<11));
10191                 if (link_up) {
10192                         legacy_speed = (legacy_status & (3<<9));
10193                         if (legacy_speed == (0<<9))
10194                                 vars->line_speed = SPEED_10;
10195                         else if (legacy_speed == (1<<9))
10196                                 vars->line_speed = SPEED_100;
10197                         else if (legacy_speed == (2<<9))
10198                                 vars->line_speed = SPEED_1000;
10199                         else /* Should not happen */
10200                                 vars->line_speed = 0;
10201
10202                         if (legacy_status & (1<<8))
10203                                 vars->duplex = DUPLEX_FULL;
10204                         else
10205                                 vars->duplex = DUPLEX_HALF;
10206
10207                         DP(NETIF_MSG_LINK,
10208                            "Link is up in %dMbps, is_duplex_full= %d\n",
10209                            vars->line_speed,
10210                            (vars->duplex == DUPLEX_FULL));
10211                         /* Check legacy speed AN resolution */
10212                         bnx2x_cl45_read(bp, phy,
10213                                         MDIO_AN_DEVAD,
10214                                         MDIO_AN_REG_8481_LEGACY_MII_STATUS,
10215                                         &val);
10216                         if (val & (1<<5))
10217                                 vars->link_status |=
10218                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10219                         bnx2x_cl45_read(bp, phy,
10220                                         MDIO_AN_DEVAD,
10221                                         MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
10222                                         &val);
10223                         if ((val & (1<<0)) == 0)
10224                                 vars->link_status |=
10225                                         LINK_STATUS_PARALLEL_DETECTION_USED;
10226                 }
10227         }
10228         if (link_up) {
10229                 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
10230                            vars->line_speed);
10231                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10232
10233                 /* Read LP advertised speeds */
10234                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10235                                 MDIO_AN_REG_CL37_FC_LP, &val);
10236                 if (val & (1<<5))
10237                         vars->link_status |=
10238                                 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10239                 if (val & (1<<6))
10240                         vars->link_status |=
10241                                 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10242                 if (val & (1<<7))
10243                         vars->link_status |=
10244                                 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10245                 if (val & (1<<8))
10246                         vars->link_status |=
10247                                 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10248                 if (val & (1<<9))
10249                         vars->link_status |=
10250                                 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10251
10252                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10253                                 MDIO_AN_REG_1000T_STATUS, &val);
10254
10255                 if (val & (1<<10))
10256                         vars->link_status |=
10257                                 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10258                 if (val & (1<<11))
10259                         vars->link_status |=
10260                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10261
10262                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10263                                 MDIO_AN_REG_MASTER_STATUS, &val);
10264
10265                 if (val & (1<<11))
10266                         vars->link_status |=
10267                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10268
10269                 /* Determine if EEE was negotiated */
10270                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
10271                         u32 eee_shmem = 0;
10272
10273                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10274                                         MDIO_AN_REG_EEE_ADV, &val1);
10275                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10276                                         MDIO_AN_REG_LP_EEE_ADV, &val2);
10277                         if ((val1 & val2) & 0x8) {
10278                                 DP(NETIF_MSG_LINK, "EEE negotiated\n");
10279                                 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
10280                         }
10281
10282                         if (val2 & 0x12)
10283                                 eee_shmem |= SHMEM_EEE_100M_ADV;
10284                         if (val2 & 0x4)
10285                                 eee_shmem |= SHMEM_EEE_1G_ADV;
10286                         if (val2 & 0x68)
10287                                 eee_shmem |= SHMEM_EEE_10G_ADV;
10288
10289                         vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
10290                         vars->eee_status |= (eee_shmem <<
10291                                              SHMEM_EEE_LP_ADV_STATUS_SHIFT);
10292                 }
10293         }
10294
10295         return link_up;
10296 }
10297
10298
10299 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
10300 {
10301         int status = 0;
10302         u32 spirom_ver;
10303         spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
10304         status = bnx2x_format_ver(spirom_ver, str, len);
10305         return status;
10306 }
10307
10308 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
10309                                 struct link_params *params)
10310 {
10311         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10312                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
10313         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10314                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
10315 }
10316
10317 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
10318                                         struct link_params *params)
10319 {
10320         bnx2x_cl45_write(params->bp, phy,
10321                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
10322         bnx2x_cl45_write(params->bp, phy,
10323                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
10324 }
10325
10326 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
10327                                    struct link_params *params)
10328 {
10329         struct bnx2x *bp = params->bp;
10330         u8 port;
10331         u16 val16;
10332
10333         if (!(CHIP_IS_E1x(bp)))
10334                 port = BP_PATH(bp);
10335         else
10336                 port = params->port;
10337
10338         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10339                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10340                                MISC_REGISTERS_GPIO_OUTPUT_LOW,
10341                                port);
10342         } else {
10343                 bnx2x_cl45_read(bp, phy,
10344                                 MDIO_CTL_DEVAD,
10345                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
10346                 val16 |= MDIO_84833_SUPER_ISOLATE;
10347                 bnx2x_cl45_write(bp, phy,
10348                                  MDIO_CTL_DEVAD,
10349                                  MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
10350         }
10351 }
10352
10353 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
10354                                      struct link_params *params, u8 mode)
10355 {
10356         struct bnx2x *bp = params->bp;
10357         u16 val;
10358         u8 port;
10359
10360         if (!(CHIP_IS_E1x(bp)))
10361                 port = BP_PATH(bp);
10362         else
10363                 port = params->port;
10364
10365         switch (mode) {
10366         case LED_MODE_OFF:
10367
10368                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
10369
10370                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10371                     SHARED_HW_CFG_LED_EXTPHY1) {
10372
10373                         /* Set LED masks */
10374                         bnx2x_cl45_write(bp, phy,
10375                                         MDIO_PMA_DEVAD,
10376                                         MDIO_PMA_REG_8481_LED1_MASK,
10377                                         0x0);
10378
10379                         bnx2x_cl45_write(bp, phy,
10380                                         MDIO_PMA_DEVAD,
10381                                         MDIO_PMA_REG_8481_LED2_MASK,
10382                                         0x0);
10383
10384                         bnx2x_cl45_write(bp, phy,
10385                                         MDIO_PMA_DEVAD,
10386                                         MDIO_PMA_REG_8481_LED3_MASK,
10387                                         0x0);
10388
10389                         bnx2x_cl45_write(bp, phy,
10390                                         MDIO_PMA_DEVAD,
10391                                         MDIO_PMA_REG_8481_LED5_MASK,
10392                                         0x0);
10393
10394                 } else {
10395                         bnx2x_cl45_write(bp, phy,
10396                                          MDIO_PMA_DEVAD,
10397                                          MDIO_PMA_REG_8481_LED1_MASK,
10398                                          0x0);
10399                 }
10400                 break;
10401         case LED_MODE_FRONT_PANEL_OFF:
10402
10403                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
10404                    port);
10405
10406                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10407                     SHARED_HW_CFG_LED_EXTPHY1) {
10408
10409                         /* Set LED masks */
10410                         bnx2x_cl45_write(bp, phy,
10411                                          MDIO_PMA_DEVAD,
10412                                          MDIO_PMA_REG_8481_LED1_MASK,
10413                                          0x0);
10414
10415                         bnx2x_cl45_write(bp, phy,
10416                                          MDIO_PMA_DEVAD,
10417                                          MDIO_PMA_REG_8481_LED2_MASK,
10418                                          0x0);
10419
10420                         bnx2x_cl45_write(bp, phy,
10421                                          MDIO_PMA_DEVAD,
10422                                          MDIO_PMA_REG_8481_LED3_MASK,
10423                                          0x0);
10424
10425                         bnx2x_cl45_write(bp, phy,
10426                                          MDIO_PMA_DEVAD,
10427                                          MDIO_PMA_REG_8481_LED5_MASK,
10428                                          0x20);
10429
10430                 } else {
10431                         bnx2x_cl45_write(bp, phy,
10432                                          MDIO_PMA_DEVAD,
10433                                          MDIO_PMA_REG_8481_LED1_MASK,
10434                                          0x0);
10435                 }
10436                 break;
10437         case LED_MODE_ON:
10438
10439                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
10440
10441                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10442                     SHARED_HW_CFG_LED_EXTPHY1) {
10443                         /* Set control reg */
10444                         bnx2x_cl45_read(bp, phy,
10445                                         MDIO_PMA_DEVAD,
10446                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10447                                         &val);
10448                         val &= 0x8000;
10449                         val |= 0x2492;
10450
10451                         bnx2x_cl45_write(bp, phy,
10452                                          MDIO_PMA_DEVAD,
10453                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10454                                          val);
10455
10456                         /* Set LED masks */
10457                         bnx2x_cl45_write(bp, phy,
10458                                          MDIO_PMA_DEVAD,
10459                                          MDIO_PMA_REG_8481_LED1_MASK,
10460                                          0x0);
10461
10462                         bnx2x_cl45_write(bp, phy,
10463                                          MDIO_PMA_DEVAD,
10464                                          MDIO_PMA_REG_8481_LED2_MASK,
10465                                          0x20);
10466
10467                         bnx2x_cl45_write(bp, phy,
10468                                          MDIO_PMA_DEVAD,
10469                                          MDIO_PMA_REG_8481_LED3_MASK,
10470                                          0x20);
10471
10472                         bnx2x_cl45_write(bp, phy,
10473                                          MDIO_PMA_DEVAD,
10474                                          MDIO_PMA_REG_8481_LED5_MASK,
10475                                          0x0);
10476                 } else {
10477                         bnx2x_cl45_write(bp, phy,
10478                                          MDIO_PMA_DEVAD,
10479                                          MDIO_PMA_REG_8481_LED1_MASK,
10480                                          0x20);
10481                 }
10482                 break;
10483
10484         case LED_MODE_OPER:
10485
10486                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
10487
10488                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10489                     SHARED_HW_CFG_LED_EXTPHY1) {
10490
10491                         /* Set control reg */
10492                         bnx2x_cl45_read(bp, phy,
10493                                         MDIO_PMA_DEVAD,
10494                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10495                                         &val);
10496
10497                         if (!((val &
10498                                MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10499                           >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
10500                                 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
10501                                 bnx2x_cl45_write(bp, phy,
10502                                                  MDIO_PMA_DEVAD,
10503                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
10504                                                  0xa492);
10505                         }
10506
10507                         /* Set LED masks */
10508                         bnx2x_cl45_write(bp, phy,
10509                                          MDIO_PMA_DEVAD,
10510                                          MDIO_PMA_REG_8481_LED1_MASK,
10511                                          0x10);
10512
10513                         bnx2x_cl45_write(bp, phy,
10514                                          MDIO_PMA_DEVAD,
10515                                          MDIO_PMA_REG_8481_LED2_MASK,
10516                                          0x80);
10517
10518                         bnx2x_cl45_write(bp, phy,
10519                                          MDIO_PMA_DEVAD,
10520                                          MDIO_PMA_REG_8481_LED3_MASK,
10521                                          0x98);
10522
10523                         bnx2x_cl45_write(bp, phy,
10524                                          MDIO_PMA_DEVAD,
10525                                          MDIO_PMA_REG_8481_LED5_MASK,
10526                                          0x40);
10527
10528                 } else {
10529                         bnx2x_cl45_write(bp, phy,
10530                                          MDIO_PMA_DEVAD,
10531                                          MDIO_PMA_REG_8481_LED1_MASK,
10532                                          0x80);
10533
10534                         /* Tell LED3 to blink on source */
10535                         bnx2x_cl45_read(bp, phy,
10536                                         MDIO_PMA_DEVAD,
10537                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10538                                         &val);
10539                         val &= ~(7<<6);
10540                         val |= (1<<6); /* A83B[8:6]= 1 */
10541                         bnx2x_cl45_write(bp, phy,
10542                                          MDIO_PMA_DEVAD,
10543                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10544                                          val);
10545                 }
10546                 break;
10547         }
10548
10549         /* This is a workaround for E3+84833 until autoneg
10550          * restart is fixed in f/w
10551          */
10552         if (CHIP_IS_E3(bp)) {
10553                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
10554                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10555         }
10556 }
10557
10558 /******************************************************************/
10559 /*                      54618SE PHY SECTION                       */
10560 /******************************************************************/
10561 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10562                                                struct link_params *params,
10563                                                struct link_vars *vars)
10564 {
10565         struct bnx2x *bp = params->bp;
10566         u8 port;
10567         u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10568         u32 cfg_pin;
10569
10570         DP(NETIF_MSG_LINK, "54618SE cfg init\n");
10571         usleep_range(1000, 1000);
10572
10573         /* This works with E3 only, no need to check the chip
10574          * before determining the port.
10575          */
10576         port = params->port;
10577
10578         cfg_pin = (REG_RD(bp, params->shmem_base +
10579                         offsetof(struct shmem_region,
10580                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10581                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10582                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10583
10584         /* Drive pin high to bring the GPHY out of reset. */
10585         bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10586
10587         /* wait for GPHY to reset */
10588         msleep(50);
10589
10590         /* reset phy */
10591         bnx2x_cl22_write(bp, phy,
10592                          MDIO_PMA_REG_CTRL, 0x8000);
10593         bnx2x_wait_reset_complete(bp, phy, params);
10594
10595         /* Wait for GPHY to reset */
10596         msleep(50);
10597
10598         /* Configure LED4: set to INTR (0x6). */
10599         /* Accessing shadow register 0xe. */
10600         bnx2x_cl22_write(bp, phy,
10601                         MDIO_REG_GPHY_SHADOW,
10602                         MDIO_REG_GPHY_SHADOW_LED_SEL2);
10603         bnx2x_cl22_read(bp, phy,
10604                         MDIO_REG_GPHY_SHADOW,
10605                         &temp);
10606         temp &= ~(0xf << 4);
10607         temp |= (0x6 << 4);
10608         bnx2x_cl22_write(bp, phy,
10609                         MDIO_REG_GPHY_SHADOW,
10610                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10611         /* Configure INTR based on link status change. */
10612         bnx2x_cl22_write(bp, phy,
10613                         MDIO_REG_INTR_MASK,
10614                         ~MDIO_REG_INTR_MASK_LINK_STATUS);
10615
10616         /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10617         bnx2x_cl22_write(bp, phy,
10618                         MDIO_REG_GPHY_SHADOW,
10619                         MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10620         bnx2x_cl22_read(bp, phy,
10621                         MDIO_REG_GPHY_SHADOW,
10622                         &temp);
10623         temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10624         bnx2x_cl22_write(bp, phy,
10625                         MDIO_REG_GPHY_SHADOW,
10626                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10627
10628         /* Set up fc */
10629         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10630         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10631         fc_val = 0;
10632         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10633                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10634                 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10635
10636         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10637                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10638                 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10639
10640         /* read all advertisement */
10641         bnx2x_cl22_read(bp, phy,
10642                         0x09,
10643                         &an_1000_val);
10644
10645         bnx2x_cl22_read(bp, phy,
10646                         0x04,
10647                         &an_10_100_val);
10648
10649         bnx2x_cl22_read(bp, phy,
10650                         MDIO_PMA_REG_CTRL,
10651                         &autoneg_val);
10652
10653         /* Disable forced speed */
10654         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10655         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10656                            (1<<11));
10657
10658         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10659                         (phy->speed_cap_mask &
10660                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10661                         (phy->req_line_speed == SPEED_1000)) {
10662                 an_1000_val |= (1<<8);
10663                 autoneg_val |= (1<<9 | 1<<12);
10664                 if (phy->req_duplex == DUPLEX_FULL)
10665                         an_1000_val |= (1<<9);
10666                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10667         } else
10668                 an_1000_val &= ~((1<<8) | (1<<9));
10669
10670         bnx2x_cl22_write(bp, phy,
10671                         0x09,
10672                         an_1000_val);
10673         bnx2x_cl22_read(bp, phy,
10674                         0x09,
10675                         &an_1000_val);
10676
10677         /* set 100 speed advertisement */
10678         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10679                         (phy->speed_cap_mask &
10680                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
10681                         PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10682                 an_10_100_val |= (1<<7);
10683                 /* Enable autoneg and restart autoneg for legacy speeds */
10684                 autoneg_val |= (1<<9 | 1<<12);
10685
10686                 if (phy->req_duplex == DUPLEX_FULL)
10687                         an_10_100_val |= (1<<8);
10688                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
10689         }
10690
10691         /* set 10 speed advertisement */
10692         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10693                         (phy->speed_cap_mask &
10694                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
10695                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10696                 an_10_100_val |= (1<<5);
10697                 autoneg_val |= (1<<9 | 1<<12);
10698                 if (phy->req_duplex == DUPLEX_FULL)
10699                         an_10_100_val |= (1<<6);
10700                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
10701         }
10702
10703         /* Only 10/100 are allowed to work in FORCE mode */
10704         if (phy->req_line_speed == SPEED_100) {
10705                 autoneg_val |= (1<<13);
10706                 /* Enabled AUTO-MDIX when autoneg is disabled */
10707                 bnx2x_cl22_write(bp, phy,
10708                                 0x18,
10709                                 (1<<15 | 1<<9 | 7<<0));
10710                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10711         }
10712         if (phy->req_line_speed == SPEED_10) {
10713                 /* Enabled AUTO-MDIX when autoneg is disabled */
10714                 bnx2x_cl22_write(bp, phy,
10715                                 0x18,
10716                                 (1<<15 | 1<<9 | 7<<0));
10717                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10718         }
10719
10720         /* Check if we should turn on Auto-GrEEEn */
10721         bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &temp);
10722         if (temp == MDIO_REG_GPHY_ID_54618SE) {
10723                 if (params->feature_config_flags &
10724                     FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10725                         temp = 6;
10726                         DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10727                 } else {
10728                         temp = 0;
10729                         DP(NETIF_MSG_LINK, "Disabling Auto-GrEEEn\n");
10730                 }
10731                 bnx2x_cl22_write(bp, phy,
10732                                  MDIO_REG_GPHY_CL45_ADDR_REG, MDIO_AN_DEVAD);
10733                 bnx2x_cl22_write(bp, phy,
10734                                  MDIO_REG_GPHY_CL45_DATA_REG,
10735                                  MDIO_REG_GPHY_EEE_ADV);
10736                 bnx2x_cl22_write(bp, phy,
10737                                  MDIO_REG_GPHY_CL45_ADDR_REG,
10738                                  (0x1 << 14) | MDIO_AN_DEVAD);
10739                 bnx2x_cl22_write(bp, phy,
10740                                  MDIO_REG_GPHY_CL45_DATA_REG,
10741                                  temp);
10742         }
10743
10744         bnx2x_cl22_write(bp, phy,
10745                         0x04,
10746                         an_10_100_val | fc_val);
10747
10748         if (phy->req_duplex == DUPLEX_FULL)
10749                 autoneg_val |= (1<<8);
10750
10751         bnx2x_cl22_write(bp, phy,
10752                         MDIO_PMA_REG_CTRL, autoneg_val);
10753
10754         return 0;
10755 }
10756
10757
10758 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy,
10759                                        struct link_params *params, u8 mode)
10760 {
10761         struct bnx2x *bp = params->bp;
10762         u16 temp;
10763
10764         bnx2x_cl22_write(bp, phy,
10765                 MDIO_REG_GPHY_SHADOW,
10766                 MDIO_REG_GPHY_SHADOW_LED_SEL1);
10767         bnx2x_cl22_read(bp, phy,
10768                 MDIO_REG_GPHY_SHADOW,
10769                 &temp);
10770         temp &= 0xff00;
10771
10772         DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode);
10773         switch (mode) {
10774         case LED_MODE_FRONT_PANEL_OFF:
10775         case LED_MODE_OFF:
10776                 temp |= 0x00ee;
10777                 break;
10778         case LED_MODE_OPER:
10779                 temp |= 0x0001;
10780                 break;
10781         case LED_MODE_ON:
10782                 temp |= 0x00ff;
10783                 break;
10784         default:
10785                 break;
10786         }
10787         bnx2x_cl22_write(bp, phy,
10788                 MDIO_REG_GPHY_SHADOW,
10789                 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10790         return;
10791 }
10792
10793
10794 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10795                                      struct link_params *params)
10796 {
10797         struct bnx2x *bp = params->bp;
10798         u32 cfg_pin;
10799         u8 port;
10800
10801         /* In case of no EPIO routed to reset the GPHY, put it
10802          * in low power mode.
10803          */
10804         bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
10805         /* This works with E3 only, no need to check the chip
10806          * before determining the port.
10807          */
10808         port = params->port;
10809         cfg_pin = (REG_RD(bp, params->shmem_base +
10810                         offsetof(struct shmem_region,
10811                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10812                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10813                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10814
10815         /* Drive pin low to put GPHY in reset. */
10816         bnx2x_set_cfg_pin(bp, cfg_pin, 0);
10817 }
10818
10819 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
10820                                     struct link_params *params,
10821                                     struct link_vars *vars)
10822 {
10823         struct bnx2x *bp = params->bp;
10824         u16 val;
10825         u8 link_up = 0;
10826         u16 legacy_status, legacy_speed;
10827
10828         /* Get speed operation status */
10829         bnx2x_cl22_read(bp, phy,
10830                         0x19,
10831                         &legacy_status);
10832         DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
10833
10834         /* Read status to clear the PHY interrupt. */
10835         bnx2x_cl22_read(bp, phy,
10836                         MDIO_REG_INTR_STATUS,
10837                         &val);
10838
10839         link_up = ((legacy_status & (1<<2)) == (1<<2));
10840
10841         if (link_up) {
10842                 legacy_speed = (legacy_status & (7<<8));
10843                 if (legacy_speed == (7<<8)) {
10844                         vars->line_speed = SPEED_1000;
10845                         vars->duplex = DUPLEX_FULL;
10846                 } else if (legacy_speed == (6<<8)) {
10847                         vars->line_speed = SPEED_1000;
10848                         vars->duplex = DUPLEX_HALF;
10849                 } else if (legacy_speed == (5<<8)) {
10850                         vars->line_speed = SPEED_100;
10851                         vars->duplex = DUPLEX_FULL;
10852                 }
10853                 /* Omitting 100Base-T4 for now */
10854                 else if (legacy_speed == (3<<8)) {
10855                         vars->line_speed = SPEED_100;
10856                         vars->duplex = DUPLEX_HALF;
10857                 } else if (legacy_speed == (2<<8)) {
10858                         vars->line_speed = SPEED_10;
10859                         vars->duplex = DUPLEX_FULL;
10860                 } else if (legacy_speed == (1<<8)) {
10861                         vars->line_speed = SPEED_10;
10862                         vars->duplex = DUPLEX_HALF;
10863                 } else /* Should not happen */
10864                         vars->line_speed = 0;
10865
10866                 DP(NETIF_MSG_LINK,
10867                    "Link is up in %dMbps, is_duplex_full= %d\n",
10868                    vars->line_speed,
10869                    (vars->duplex == DUPLEX_FULL));
10870
10871                 /* Check legacy speed AN resolution */
10872                 bnx2x_cl22_read(bp, phy,
10873                                 0x01,
10874                                 &val);
10875                 if (val & (1<<5))
10876                         vars->link_status |=
10877                                 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10878                 bnx2x_cl22_read(bp, phy,
10879                                 0x06,
10880                                 &val);
10881                 if ((val & (1<<0)) == 0)
10882                         vars->link_status |=
10883                                 LINK_STATUS_PARALLEL_DETECTION_USED;
10884
10885                 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
10886                            vars->line_speed);
10887
10888                 /* Report whether EEE is resolved. */
10889                 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &val);
10890                 if (val == MDIO_REG_GPHY_ID_54618SE) {
10891                         if (vars->link_status &
10892                             LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
10893                                 val = 0;
10894                         else {
10895                                 bnx2x_cl22_write(bp, phy,
10896                                         MDIO_REG_GPHY_CL45_ADDR_REG,
10897                                         MDIO_AN_DEVAD);
10898                                 bnx2x_cl22_write(bp, phy,
10899                                         MDIO_REG_GPHY_CL45_DATA_REG,
10900                                         MDIO_REG_GPHY_EEE_RESOLVED);
10901                                 bnx2x_cl22_write(bp, phy,
10902                                         MDIO_REG_GPHY_CL45_ADDR_REG,
10903                                         (0x1 << 14) | MDIO_AN_DEVAD);
10904                                 bnx2x_cl22_read(bp, phy,
10905                                         MDIO_REG_GPHY_CL45_DATA_REG,
10906                                         &val);
10907                         }
10908                         DP(NETIF_MSG_LINK, "EEE resolution: 0x%x\n", val);
10909                 }
10910
10911                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10912
10913                 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
10914                         /* Report LP advertised speeds */
10915                         bnx2x_cl22_read(bp, phy, 0x5, &val);
10916
10917                         if (val & (1<<5))
10918                                 vars->link_status |=
10919                                   LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10920                         if (val & (1<<6))
10921                                 vars->link_status |=
10922                                   LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10923                         if (val & (1<<7))
10924                                 vars->link_status |=
10925                                   LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10926                         if (val & (1<<8))
10927                                 vars->link_status |=
10928                                   LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10929                         if (val & (1<<9))
10930                                 vars->link_status |=
10931                                   LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10932
10933                         bnx2x_cl22_read(bp, phy, 0xa, &val);
10934                         if (val & (1<<10))
10935                                 vars->link_status |=
10936                                   LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10937                         if (val & (1<<11))
10938                                 vars->link_status |=
10939                                   LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10940                 }
10941         }
10942         return link_up;
10943 }
10944
10945 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
10946                                           struct link_params *params)
10947 {
10948         struct bnx2x *bp = params->bp;
10949         u16 val;
10950         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10951
10952         DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
10953
10954         /* Enable master/slave manual mmode and set to master */
10955         /* mii write 9 [bits set 11 12] */
10956         bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
10957
10958         /* forced 1G and disable autoneg */
10959         /* set val [mii read 0] */
10960         /* set val [expr $val & [bits clear 6 12 13]] */
10961         /* set val [expr $val | [bits set 6 8]] */
10962         /* mii write 0 $val */
10963         bnx2x_cl22_read(bp, phy, 0x00, &val);
10964         val &= ~((1<<6) | (1<<12) | (1<<13));
10965         val |= (1<<6) | (1<<8);
10966         bnx2x_cl22_write(bp, phy, 0x00, val);
10967
10968         /* Set external loopback and Tx using 6dB coding */
10969         /* mii write 0x18 7 */
10970         /* set val [mii read 0x18] */
10971         /* mii write 0x18 [expr $val | [bits set 10 15]] */
10972         bnx2x_cl22_write(bp, phy, 0x18, 7);
10973         bnx2x_cl22_read(bp, phy, 0x18, &val);
10974         bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
10975
10976         /* This register opens the gate for the UMAC despite its name */
10977         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
10978
10979         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10980          * length used by the MAC receive logic to check frames.
10981          */
10982         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
10983 }
10984
10985 /******************************************************************/
10986 /*                      SFX7101 PHY SECTION                       */
10987 /******************************************************************/
10988 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
10989                                        struct link_params *params)
10990 {
10991         struct bnx2x *bp = params->bp;
10992         /* SFX7101_XGXS_TEST1 */
10993         bnx2x_cl45_write(bp, phy,
10994                          MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
10995 }
10996
10997 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
10998                                   struct link_params *params,
10999                                   struct link_vars *vars)
11000 {
11001         u16 fw_ver1, fw_ver2, val;
11002         struct bnx2x *bp = params->bp;
11003         DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
11004
11005         /* Restore normal power mode*/
11006         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11007                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
11008         /* HW reset */
11009         bnx2x_ext_phy_hw_reset(bp, params->port);
11010         bnx2x_wait_reset_complete(bp, phy, params);
11011
11012         bnx2x_cl45_write(bp, phy,
11013                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
11014         DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
11015         bnx2x_cl45_write(bp, phy,
11016                          MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
11017
11018         bnx2x_ext_phy_set_pause(params, phy, vars);
11019         /* Restart autoneg */
11020         bnx2x_cl45_read(bp, phy,
11021                         MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
11022         val |= 0x200;
11023         bnx2x_cl45_write(bp, phy,
11024                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
11025
11026         /* Save spirom version */
11027         bnx2x_cl45_read(bp, phy,
11028                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
11029
11030         bnx2x_cl45_read(bp, phy,
11031                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
11032         bnx2x_save_spirom_version(bp, params->port,
11033                                   (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
11034         return 0;
11035 }
11036
11037 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
11038                                  struct link_params *params,
11039                                  struct link_vars *vars)
11040 {
11041         struct bnx2x *bp = params->bp;
11042         u8 link_up;
11043         u16 val1, val2;
11044         bnx2x_cl45_read(bp, phy,
11045                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
11046         bnx2x_cl45_read(bp, phy,
11047                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
11048         DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
11049                    val2, val1);
11050         bnx2x_cl45_read(bp, phy,
11051                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
11052         bnx2x_cl45_read(bp, phy,
11053                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
11054         DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
11055                    val2, val1);
11056         link_up = ((val1 & 4) == 4);
11057         /* if link is up print the AN outcome of the SFX7101 PHY */
11058         if (link_up) {
11059                 bnx2x_cl45_read(bp, phy,
11060                                 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
11061                                 &val2);
11062                 vars->line_speed = SPEED_10000;
11063                 vars->duplex = DUPLEX_FULL;
11064                 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
11065                            val2, (val2 & (1<<14)));
11066                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
11067                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11068
11069                 /* read LP advertised speeds */
11070                 if (val2 & (1<<11))
11071                         vars->link_status |=
11072                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
11073         }
11074         return link_up;
11075 }
11076
11077 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
11078 {
11079         if (*len < 5)
11080                 return -EINVAL;
11081         str[0] = (spirom_ver & 0xFF);
11082         str[1] = (spirom_ver & 0xFF00) >> 8;
11083         str[2] = (spirom_ver & 0xFF0000) >> 16;
11084         str[3] = (spirom_ver & 0xFF000000) >> 24;
11085         str[4] = '\0';
11086         *len -= 5;
11087         return 0;
11088 }
11089
11090 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
11091 {
11092         u16 val, cnt;
11093
11094         bnx2x_cl45_read(bp, phy,
11095                         MDIO_PMA_DEVAD,
11096                         MDIO_PMA_REG_7101_RESET, &val);
11097
11098         for (cnt = 0; cnt < 10; cnt++) {
11099                 msleep(50);
11100                 /* Writes a self-clearing reset */
11101                 bnx2x_cl45_write(bp, phy,
11102                                  MDIO_PMA_DEVAD,
11103                                  MDIO_PMA_REG_7101_RESET,
11104                                  (val | (1<<15)));
11105                 /* Wait for clear */
11106                 bnx2x_cl45_read(bp, phy,
11107                                 MDIO_PMA_DEVAD,
11108                                 MDIO_PMA_REG_7101_RESET, &val);
11109
11110                 if ((val & (1<<15)) == 0)
11111                         break;
11112         }
11113 }
11114
11115 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
11116                                 struct link_params *params) {
11117         /* Low power mode is controlled by GPIO 2 */
11118         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
11119                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11120         /* The PHY reset is controlled by GPIO 1 */
11121         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
11122                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11123 }
11124
11125 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
11126                                     struct link_params *params, u8 mode)
11127 {
11128         u16 val = 0;
11129         struct bnx2x *bp = params->bp;
11130         switch (mode) {
11131         case LED_MODE_FRONT_PANEL_OFF:
11132         case LED_MODE_OFF:
11133                 val = 2;
11134                 break;
11135         case LED_MODE_ON:
11136                 val = 1;
11137                 break;
11138         case LED_MODE_OPER:
11139                 val = 0;
11140                 break;
11141         }
11142         bnx2x_cl45_write(bp, phy,
11143                          MDIO_PMA_DEVAD,
11144                          MDIO_PMA_REG_7107_LINK_LED_CNTL,
11145                          val);
11146 }
11147
11148 /******************************************************************/
11149 /*                      STATIC PHY DECLARATION                    */
11150 /******************************************************************/
11151
11152 static struct bnx2x_phy phy_null = {
11153         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
11154         .addr           = 0,
11155         .def_md_devad   = 0,
11156         .flags          = FLAGS_INIT_XGXS_FIRST,
11157         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11158         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11159         .mdio_ctrl      = 0,
11160         .supported      = 0,
11161         .media_type     = ETH_PHY_NOT_PRESENT,
11162         .ver_addr       = 0,
11163         .req_flow_ctrl  = 0,
11164         .req_line_speed = 0,
11165         .speed_cap_mask = 0,
11166         .req_duplex     = 0,
11167         .rsrv           = 0,
11168         .config_init    = (config_init_t)NULL,
11169         .read_status    = (read_status_t)NULL,
11170         .link_reset     = (link_reset_t)NULL,
11171         .config_loopback = (config_loopback_t)NULL,
11172         .format_fw_ver  = (format_fw_ver_t)NULL,
11173         .hw_reset       = (hw_reset_t)NULL,
11174         .set_link_led   = (set_link_led_t)NULL,
11175         .phy_specific_func = (phy_specific_func_t)NULL
11176 };
11177
11178 static struct bnx2x_phy phy_serdes = {
11179         .type           = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
11180         .addr           = 0xff,
11181         .def_md_devad   = 0,
11182         .flags          = 0,
11183         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11184         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11185         .mdio_ctrl      = 0,
11186         .supported      = (SUPPORTED_10baseT_Half |
11187                            SUPPORTED_10baseT_Full |
11188                            SUPPORTED_100baseT_Half |
11189                            SUPPORTED_100baseT_Full |
11190                            SUPPORTED_1000baseT_Full |
11191                            SUPPORTED_2500baseX_Full |
11192                            SUPPORTED_TP |
11193                            SUPPORTED_Autoneg |
11194                            SUPPORTED_Pause |
11195                            SUPPORTED_Asym_Pause),
11196         .media_type     = ETH_PHY_BASE_T,
11197         .ver_addr       = 0,
11198         .req_flow_ctrl  = 0,
11199         .req_line_speed = 0,
11200         .speed_cap_mask = 0,
11201         .req_duplex     = 0,
11202         .rsrv           = 0,
11203         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
11204         .read_status    = (read_status_t)bnx2x_link_settings_status,
11205         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
11206         .config_loopback = (config_loopback_t)NULL,
11207         .format_fw_ver  = (format_fw_ver_t)NULL,
11208         .hw_reset       = (hw_reset_t)NULL,
11209         .set_link_led   = (set_link_led_t)NULL,
11210         .phy_specific_func = (phy_specific_func_t)NULL
11211 };
11212
11213 static struct bnx2x_phy phy_xgxs = {
11214         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11215         .addr           = 0xff,
11216         .def_md_devad   = 0,
11217         .flags          = 0,
11218         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11219         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11220         .mdio_ctrl      = 0,
11221         .supported      = (SUPPORTED_10baseT_Half |
11222                            SUPPORTED_10baseT_Full |
11223                            SUPPORTED_100baseT_Half |
11224                            SUPPORTED_100baseT_Full |
11225                            SUPPORTED_1000baseT_Full |
11226                            SUPPORTED_2500baseX_Full |
11227                            SUPPORTED_10000baseT_Full |
11228                            SUPPORTED_FIBRE |
11229                            SUPPORTED_Autoneg |
11230                            SUPPORTED_Pause |
11231                            SUPPORTED_Asym_Pause),
11232         .media_type     = ETH_PHY_CX4,
11233         .ver_addr       = 0,
11234         .req_flow_ctrl  = 0,
11235         .req_line_speed = 0,
11236         .speed_cap_mask = 0,
11237         .req_duplex     = 0,
11238         .rsrv           = 0,
11239         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
11240         .read_status    = (read_status_t)bnx2x_link_settings_status,
11241         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
11242         .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
11243         .format_fw_ver  = (format_fw_ver_t)NULL,
11244         .hw_reset       = (hw_reset_t)NULL,
11245         .set_link_led   = (set_link_led_t)NULL,
11246         .phy_specific_func = (phy_specific_func_t)NULL
11247 };
11248 static struct bnx2x_phy phy_warpcore = {
11249         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11250         .addr           = 0xff,
11251         .def_md_devad   = 0,
11252         .flags          = (FLAGS_HW_LOCK_REQUIRED |
11253                            FLAGS_TX_ERROR_CHECK),
11254         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11255         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11256         .mdio_ctrl      = 0,
11257         .supported      = (SUPPORTED_10baseT_Half |
11258                            SUPPORTED_10baseT_Full |
11259                            SUPPORTED_100baseT_Half |
11260                            SUPPORTED_100baseT_Full |
11261                            SUPPORTED_1000baseT_Full |
11262                            SUPPORTED_10000baseT_Full |
11263                            SUPPORTED_20000baseKR2_Full |
11264                            SUPPORTED_20000baseMLD2_Full |
11265                            SUPPORTED_FIBRE |
11266                            SUPPORTED_Autoneg |
11267                            SUPPORTED_Pause |
11268                            SUPPORTED_Asym_Pause),
11269         .media_type     = ETH_PHY_UNSPECIFIED,
11270         .ver_addr       = 0,
11271         .req_flow_ctrl  = 0,
11272         .req_line_speed = 0,
11273         .speed_cap_mask = 0,
11274         /* req_duplex = */0,
11275         /* rsrv = */0,
11276         .config_init    = (config_init_t)bnx2x_warpcore_config_init,
11277         .read_status    = (read_status_t)bnx2x_warpcore_read_status,
11278         .link_reset     = (link_reset_t)bnx2x_warpcore_link_reset,
11279         .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
11280         .format_fw_ver  = (format_fw_ver_t)NULL,
11281         .hw_reset       = (hw_reset_t)bnx2x_warpcore_hw_reset,
11282         .set_link_led   = (set_link_led_t)NULL,
11283         .phy_specific_func = (phy_specific_func_t)NULL
11284 };
11285
11286
11287 static struct bnx2x_phy phy_7101 = {
11288         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
11289         .addr           = 0xff,
11290         .def_md_devad   = 0,
11291         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
11292         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11293         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11294         .mdio_ctrl      = 0,
11295         .supported      = (SUPPORTED_10000baseT_Full |
11296                            SUPPORTED_TP |
11297                            SUPPORTED_Autoneg |
11298                            SUPPORTED_Pause |
11299                            SUPPORTED_Asym_Pause),
11300         .media_type     = ETH_PHY_BASE_T,
11301         .ver_addr       = 0,
11302         .req_flow_ctrl  = 0,
11303         .req_line_speed = 0,
11304         .speed_cap_mask = 0,
11305         .req_duplex     = 0,
11306         .rsrv           = 0,
11307         .config_init    = (config_init_t)bnx2x_7101_config_init,
11308         .read_status    = (read_status_t)bnx2x_7101_read_status,
11309         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11310         .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
11311         .format_fw_ver  = (format_fw_ver_t)bnx2x_7101_format_ver,
11312         .hw_reset       = (hw_reset_t)bnx2x_7101_hw_reset,
11313         .set_link_led   = (set_link_led_t)bnx2x_7101_set_link_led,
11314         .phy_specific_func = (phy_specific_func_t)NULL
11315 };
11316 static struct bnx2x_phy phy_8073 = {
11317         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
11318         .addr           = 0xff,
11319         .def_md_devad   = 0,
11320         .flags          = FLAGS_HW_LOCK_REQUIRED,
11321         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11322         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11323         .mdio_ctrl      = 0,
11324         .supported      = (SUPPORTED_10000baseT_Full |
11325                            SUPPORTED_2500baseX_Full |
11326                            SUPPORTED_1000baseT_Full |
11327                            SUPPORTED_FIBRE |
11328                            SUPPORTED_Autoneg |
11329                            SUPPORTED_Pause |
11330                            SUPPORTED_Asym_Pause),
11331         .media_type     = ETH_PHY_KR,
11332         .ver_addr       = 0,
11333         .req_flow_ctrl  = 0,
11334         .req_line_speed = 0,
11335         .speed_cap_mask = 0,
11336         .req_duplex     = 0,
11337         .rsrv           = 0,
11338         .config_init    = (config_init_t)bnx2x_8073_config_init,
11339         .read_status    = (read_status_t)bnx2x_8073_read_status,
11340         .link_reset     = (link_reset_t)bnx2x_8073_link_reset,
11341         .config_loopback = (config_loopback_t)NULL,
11342         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11343         .hw_reset       = (hw_reset_t)NULL,
11344         .set_link_led   = (set_link_led_t)NULL,
11345         .phy_specific_func = (phy_specific_func_t)NULL
11346 };
11347 static struct bnx2x_phy phy_8705 = {
11348         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
11349         .addr           = 0xff,
11350         .def_md_devad   = 0,
11351         .flags          = FLAGS_INIT_XGXS_FIRST,
11352         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11353         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11354         .mdio_ctrl      = 0,
11355         .supported      = (SUPPORTED_10000baseT_Full |
11356                            SUPPORTED_FIBRE |
11357                            SUPPORTED_Pause |
11358                            SUPPORTED_Asym_Pause),
11359         .media_type     = ETH_PHY_XFP_FIBER,
11360         .ver_addr       = 0,
11361         .req_flow_ctrl  = 0,
11362         .req_line_speed = 0,
11363         .speed_cap_mask = 0,
11364         .req_duplex     = 0,
11365         .rsrv           = 0,
11366         .config_init    = (config_init_t)bnx2x_8705_config_init,
11367         .read_status    = (read_status_t)bnx2x_8705_read_status,
11368         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11369         .config_loopback = (config_loopback_t)NULL,
11370         .format_fw_ver  = (format_fw_ver_t)bnx2x_null_format_ver,
11371         .hw_reset       = (hw_reset_t)NULL,
11372         .set_link_led   = (set_link_led_t)NULL,
11373         .phy_specific_func = (phy_specific_func_t)NULL
11374 };
11375 static struct bnx2x_phy phy_8706 = {
11376         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
11377         .addr           = 0xff,
11378         .def_md_devad   = 0,
11379         .flags          = FLAGS_INIT_XGXS_FIRST,
11380         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11381         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11382         .mdio_ctrl      = 0,
11383         .supported      = (SUPPORTED_10000baseT_Full |
11384                            SUPPORTED_1000baseT_Full |
11385                            SUPPORTED_FIBRE |
11386                            SUPPORTED_Pause |
11387                            SUPPORTED_Asym_Pause),
11388         .media_type     = ETH_PHY_SFP_FIBER,
11389         .ver_addr       = 0,
11390         .req_flow_ctrl  = 0,
11391         .req_line_speed = 0,
11392         .speed_cap_mask = 0,
11393         .req_duplex     = 0,
11394         .rsrv           = 0,
11395         .config_init    = (config_init_t)bnx2x_8706_config_init,
11396         .read_status    = (read_status_t)bnx2x_8706_read_status,
11397         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11398         .config_loopback = (config_loopback_t)NULL,
11399         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11400         .hw_reset       = (hw_reset_t)NULL,
11401         .set_link_led   = (set_link_led_t)NULL,
11402         .phy_specific_func = (phy_specific_func_t)NULL
11403 };
11404
11405 static struct bnx2x_phy phy_8726 = {
11406         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
11407         .addr           = 0xff,
11408         .def_md_devad   = 0,
11409         .flags          = (FLAGS_HW_LOCK_REQUIRED |
11410                            FLAGS_INIT_XGXS_FIRST |
11411                            FLAGS_TX_ERROR_CHECK),
11412         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11413         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11414         .mdio_ctrl      = 0,
11415         .supported      = (SUPPORTED_10000baseT_Full |
11416                            SUPPORTED_1000baseT_Full |
11417                            SUPPORTED_Autoneg |
11418                            SUPPORTED_FIBRE |
11419                            SUPPORTED_Pause |
11420                            SUPPORTED_Asym_Pause),
11421         .media_type     = ETH_PHY_NOT_PRESENT,
11422         .ver_addr       = 0,
11423         .req_flow_ctrl  = 0,
11424         .req_line_speed = 0,
11425         .speed_cap_mask = 0,
11426         .req_duplex     = 0,
11427         .rsrv           = 0,
11428         .config_init    = (config_init_t)bnx2x_8726_config_init,
11429         .read_status    = (read_status_t)bnx2x_8726_read_status,
11430         .link_reset     = (link_reset_t)bnx2x_8726_link_reset,
11431         .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
11432         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11433         .hw_reset       = (hw_reset_t)NULL,
11434         .set_link_led   = (set_link_led_t)NULL,
11435         .phy_specific_func = (phy_specific_func_t)NULL
11436 };
11437
11438 static struct bnx2x_phy phy_8727 = {
11439         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
11440         .addr           = 0xff,
11441         .def_md_devad   = 0,
11442         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11443                            FLAGS_TX_ERROR_CHECK),
11444         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11445         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11446         .mdio_ctrl      = 0,
11447         .supported      = (SUPPORTED_10000baseT_Full |
11448                            SUPPORTED_1000baseT_Full |
11449                            SUPPORTED_FIBRE |
11450                            SUPPORTED_Pause |
11451                            SUPPORTED_Asym_Pause),
11452         .media_type     = ETH_PHY_NOT_PRESENT,
11453         .ver_addr       = 0,
11454         .req_flow_ctrl  = 0,
11455         .req_line_speed = 0,
11456         .speed_cap_mask = 0,
11457         .req_duplex     = 0,
11458         .rsrv           = 0,
11459         .config_init    = (config_init_t)bnx2x_8727_config_init,
11460         .read_status    = (read_status_t)bnx2x_8727_read_status,
11461         .link_reset     = (link_reset_t)bnx2x_8727_link_reset,
11462         .config_loopback = (config_loopback_t)NULL,
11463         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11464         .hw_reset       = (hw_reset_t)bnx2x_8727_hw_reset,
11465         .set_link_led   = (set_link_led_t)bnx2x_8727_set_link_led,
11466         .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
11467 };
11468 static struct bnx2x_phy phy_8481 = {
11469         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
11470         .addr           = 0xff,
11471         .def_md_devad   = 0,
11472         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
11473                           FLAGS_REARM_LATCH_SIGNAL,
11474         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11475         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11476         .mdio_ctrl      = 0,
11477         .supported      = (SUPPORTED_10baseT_Half |
11478                            SUPPORTED_10baseT_Full |
11479                            SUPPORTED_100baseT_Half |
11480                            SUPPORTED_100baseT_Full |
11481                            SUPPORTED_1000baseT_Full |
11482                            SUPPORTED_10000baseT_Full |
11483                            SUPPORTED_TP |
11484                            SUPPORTED_Autoneg |
11485                            SUPPORTED_Pause |
11486                            SUPPORTED_Asym_Pause),
11487         .media_type     = ETH_PHY_BASE_T,
11488         .ver_addr       = 0,
11489         .req_flow_ctrl  = 0,
11490         .req_line_speed = 0,
11491         .speed_cap_mask = 0,
11492         .req_duplex     = 0,
11493         .rsrv           = 0,
11494         .config_init    = (config_init_t)bnx2x_8481_config_init,
11495         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11496         .link_reset     = (link_reset_t)bnx2x_8481_link_reset,
11497         .config_loopback = (config_loopback_t)NULL,
11498         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11499         .hw_reset       = (hw_reset_t)bnx2x_8481_hw_reset,
11500         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11501         .phy_specific_func = (phy_specific_func_t)NULL
11502 };
11503
11504 static struct bnx2x_phy phy_84823 = {
11505         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
11506         .addr           = 0xff,
11507         .def_md_devad   = 0,
11508         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11509                            FLAGS_REARM_LATCH_SIGNAL |
11510                            FLAGS_TX_ERROR_CHECK),
11511         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11512         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11513         .mdio_ctrl      = 0,
11514         .supported      = (SUPPORTED_10baseT_Half |
11515                            SUPPORTED_10baseT_Full |
11516                            SUPPORTED_100baseT_Half |
11517                            SUPPORTED_100baseT_Full |
11518                            SUPPORTED_1000baseT_Full |
11519                            SUPPORTED_10000baseT_Full |
11520                            SUPPORTED_TP |
11521                            SUPPORTED_Autoneg |
11522                            SUPPORTED_Pause |
11523                            SUPPORTED_Asym_Pause),
11524         .media_type     = ETH_PHY_BASE_T,
11525         .ver_addr       = 0,
11526         .req_flow_ctrl  = 0,
11527         .req_line_speed = 0,
11528         .speed_cap_mask = 0,
11529         .req_duplex     = 0,
11530         .rsrv           = 0,
11531         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11532         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11533         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11534         .config_loopback = (config_loopback_t)NULL,
11535         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11536         .hw_reset       = (hw_reset_t)NULL,
11537         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11538         .phy_specific_func = (phy_specific_func_t)NULL
11539 };
11540
11541 static struct bnx2x_phy phy_84833 = {
11542         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
11543         .addr           = 0xff,
11544         .def_md_devad   = 0,
11545         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11546                            FLAGS_REARM_LATCH_SIGNAL |
11547                            FLAGS_TX_ERROR_CHECK |
11548                            FLAGS_EEE_10GBT),
11549         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11550         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11551         .mdio_ctrl      = 0,
11552         .supported      = (SUPPORTED_100baseT_Half |
11553                            SUPPORTED_100baseT_Full |
11554                            SUPPORTED_1000baseT_Full |
11555                            SUPPORTED_10000baseT_Full |
11556                            SUPPORTED_TP |
11557                            SUPPORTED_Autoneg |
11558                            SUPPORTED_Pause |
11559                            SUPPORTED_Asym_Pause),
11560         .media_type     = ETH_PHY_BASE_T,
11561         .ver_addr       = 0,
11562         .req_flow_ctrl  = 0,
11563         .req_line_speed = 0,
11564         .speed_cap_mask = 0,
11565         .req_duplex     = 0,
11566         .rsrv           = 0,
11567         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11568         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11569         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11570         .config_loopback = (config_loopback_t)NULL,
11571         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11572         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11573         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11574         .phy_specific_func = (phy_specific_func_t)NULL
11575 };
11576
11577 static struct bnx2x_phy phy_54618se = {
11578         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
11579         .addr           = 0xff,
11580         .def_md_devad   = 0,
11581         .flags          = FLAGS_INIT_XGXS_FIRST,
11582         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11583         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11584         .mdio_ctrl      = 0,
11585         .supported      = (SUPPORTED_10baseT_Half |
11586                            SUPPORTED_10baseT_Full |
11587                            SUPPORTED_100baseT_Half |
11588                            SUPPORTED_100baseT_Full |
11589                            SUPPORTED_1000baseT_Full |
11590                            SUPPORTED_TP |
11591                            SUPPORTED_Autoneg |
11592                            SUPPORTED_Pause |
11593                            SUPPORTED_Asym_Pause),
11594         .media_type     = ETH_PHY_BASE_T,
11595         .ver_addr       = 0,
11596         .req_flow_ctrl  = 0,
11597         .req_line_speed = 0,
11598         .speed_cap_mask = 0,
11599         /* req_duplex = */0,
11600         /* rsrv = */0,
11601         .config_init    = (config_init_t)bnx2x_54618se_config_init,
11602         .read_status    = (read_status_t)bnx2x_54618se_read_status,
11603         .link_reset     = (link_reset_t)bnx2x_54618se_link_reset,
11604         .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
11605         .format_fw_ver  = (format_fw_ver_t)NULL,
11606         .hw_reset       = (hw_reset_t)NULL,
11607         .set_link_led   = (set_link_led_t)bnx2x_5461x_set_link_led,
11608         .phy_specific_func = (phy_specific_func_t)NULL
11609 };
11610 /*****************************************************************/
11611 /*                                                               */
11612 /* Populate the phy according. Main function: bnx2x_populate_phy   */
11613 /*                                                               */
11614 /*****************************************************************/
11615
11616 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
11617                                      struct bnx2x_phy *phy, u8 port,
11618                                      u8 phy_index)
11619 {
11620         /* Get the 4 lanes xgxs config rx and tx */
11621         u32 rx = 0, tx = 0, i;
11622         for (i = 0; i < 2; i++) {
11623                 /* INT_PHY and EXT_PHY1 share the same value location in
11624                  * the shmem. When num_phys is greater than 1, than this value
11625                  * applies only to EXT_PHY1
11626                  */
11627                 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
11628                         rx = REG_RD(bp, shmem_base +
11629                                     offsetof(struct shmem_region,
11630                           dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
11631
11632                         tx = REG_RD(bp, shmem_base +
11633                                     offsetof(struct shmem_region,
11634                           dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
11635                 } else {
11636                         rx = REG_RD(bp, shmem_base +
11637                                     offsetof(struct shmem_region,
11638                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11639
11640                         tx = REG_RD(bp, shmem_base +
11641                                     offsetof(struct shmem_region,
11642                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11643                 }
11644
11645                 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
11646                 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11647
11648                 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
11649                 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11650         }
11651 }
11652
11653 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11654                                     u8 phy_index, u8 port)
11655 {
11656         u32 ext_phy_config = 0;
11657         switch (phy_index) {
11658         case EXT_PHY1:
11659                 ext_phy_config = REG_RD(bp, shmem_base +
11660                                               offsetof(struct shmem_region,
11661                         dev_info.port_hw_config[port].external_phy_config));
11662                 break;
11663         case EXT_PHY2:
11664                 ext_phy_config = REG_RD(bp, shmem_base +
11665                                               offsetof(struct shmem_region,
11666                         dev_info.port_hw_config[port].external_phy_config2));
11667                 break;
11668         default:
11669                 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11670                 return -EINVAL;
11671         }
11672
11673         return ext_phy_config;
11674 }
11675 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11676                                   struct bnx2x_phy *phy)
11677 {
11678         u32 phy_addr;
11679         u32 chip_id;
11680         u32 switch_cfg = (REG_RD(bp, shmem_base +
11681                                        offsetof(struct shmem_region,
11682                         dev_info.port_feature_config[port].link_config)) &
11683                           PORT_FEATURE_CONNECTED_SWITCH_MASK);
11684         chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
11685                 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
11686
11687         DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11688         if (USES_WARPCORE(bp)) {
11689                 u32 serdes_net_if;
11690                 phy_addr = REG_RD(bp,
11691                                   MISC_REG_WC0_CTRL_PHY_ADDR);
11692                 *phy = phy_warpcore;
11693                 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11694                         phy->flags |= FLAGS_4_PORT_MODE;
11695                 else
11696                         phy->flags &= ~FLAGS_4_PORT_MODE;
11697                         /* Check Dual mode */
11698                 serdes_net_if = (REG_RD(bp, shmem_base +
11699                                         offsetof(struct shmem_region, dev_info.
11700                                         port_hw_config[port].default_cfg)) &
11701                                  PORT_HW_CFG_NET_SERDES_IF_MASK);
11702                 /* Set the appropriate supported and flags indications per
11703                  * interface type of the chip
11704                  */
11705                 switch (serdes_net_if) {
11706                 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11707                         phy->supported &= (SUPPORTED_10baseT_Half |
11708                                            SUPPORTED_10baseT_Full |
11709                                            SUPPORTED_100baseT_Half |
11710                                            SUPPORTED_100baseT_Full |
11711                                            SUPPORTED_1000baseT_Full |
11712                                            SUPPORTED_FIBRE |
11713                                            SUPPORTED_Autoneg |
11714                                            SUPPORTED_Pause |
11715                                            SUPPORTED_Asym_Pause);
11716                         phy->media_type = ETH_PHY_BASE_T;
11717                         break;
11718                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11719                         phy->media_type = ETH_PHY_XFP_FIBER;
11720                         break;
11721                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11722                         phy->supported &= (SUPPORTED_1000baseT_Full |
11723                                            SUPPORTED_10000baseT_Full |
11724                                            SUPPORTED_FIBRE |
11725                                            SUPPORTED_Pause |
11726                                            SUPPORTED_Asym_Pause);
11727                         phy->media_type = ETH_PHY_SFP_FIBER;
11728                         break;
11729                 case PORT_HW_CFG_NET_SERDES_IF_KR:
11730                         phy->media_type = ETH_PHY_KR;
11731                         phy->supported &= (SUPPORTED_1000baseT_Full |
11732                                            SUPPORTED_10000baseT_Full |
11733                                            SUPPORTED_FIBRE |
11734                                            SUPPORTED_Autoneg |
11735                                            SUPPORTED_Pause |
11736                                            SUPPORTED_Asym_Pause);
11737                         break;
11738                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11739                         phy->media_type = ETH_PHY_KR;
11740                         phy->flags |= FLAGS_WC_DUAL_MODE;
11741                         phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11742                                            SUPPORTED_FIBRE |
11743                                            SUPPORTED_Pause |
11744                                            SUPPORTED_Asym_Pause);
11745                         break;
11746                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11747                         phy->media_type = ETH_PHY_KR;
11748                         phy->flags |= FLAGS_WC_DUAL_MODE;
11749                         phy->supported &= (SUPPORTED_20000baseKR2_Full |
11750                                            SUPPORTED_FIBRE |
11751                                            SUPPORTED_Pause |
11752                                            SUPPORTED_Asym_Pause);
11753                         break;
11754                 default:
11755                         DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
11756                                        serdes_net_if);
11757                         break;
11758                 }
11759
11760                 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
11761                  * was not set as expected. For B0, ECO will be enabled so there
11762                  * won't be an issue there
11763                  */
11764                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11765                         phy->flags |= FLAGS_MDC_MDIO_WA;
11766                 else
11767                         phy->flags |= FLAGS_MDC_MDIO_WA_B0;
11768         } else {
11769                 switch (switch_cfg) {
11770                 case SWITCH_CFG_1G:
11771                         phy_addr = REG_RD(bp,
11772                                           NIG_REG_SERDES0_CTRL_PHY_ADDR +
11773                                           port * 0x10);
11774                         *phy = phy_serdes;
11775                         break;
11776                 case SWITCH_CFG_10G:
11777                         phy_addr = REG_RD(bp,
11778                                           NIG_REG_XGXS0_CTRL_PHY_ADDR +
11779                                           port * 0x18);
11780                         *phy = phy_xgxs;
11781                         break;
11782                 default:
11783                         DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
11784                         return -EINVAL;
11785                 }
11786         }
11787         phy->addr = (u8)phy_addr;
11788         phy->mdio_ctrl = bnx2x_get_emac_base(bp,
11789                                             SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11790                                             port);
11791         if (CHIP_IS_E2(bp))
11792                 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
11793         else
11794                 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
11795
11796         DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
11797                    port, phy->addr, phy->mdio_ctrl);
11798
11799         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
11800         return 0;
11801 }
11802
11803 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
11804                                   u8 phy_index,
11805                                   u32 shmem_base,
11806                                   u32 shmem2_base,
11807                                   u8 port,
11808                                   struct bnx2x_phy *phy)
11809 {
11810         u32 ext_phy_config, phy_type, config2;
11811         u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11812         ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
11813                                                   phy_index, port);
11814         phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11815         /* Select the phy type */
11816         switch (phy_type) {
11817         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
11818                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
11819                 *phy = phy_8073;
11820                 break;
11821         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
11822                 *phy = phy_8705;
11823                 break;
11824         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
11825                 *phy = phy_8706;
11826                 break;
11827         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
11828                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11829                 *phy = phy_8726;
11830                 break;
11831         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
11832                 /* BCM8727_NOC => BCM8727 no over current */
11833                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11834                 *phy = phy_8727;
11835                 phy->flags |= FLAGS_NOC;
11836                 break;
11837         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
11838         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
11839                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11840                 *phy = phy_8727;
11841                 break;
11842         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
11843                 *phy = phy_8481;
11844                 break;
11845         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
11846                 *phy = phy_84823;
11847                 break;
11848         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
11849                 *phy = phy_84833;
11850                 break;
11851         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
11852         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
11853                 *phy = phy_54618se;
11854                 break;
11855         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
11856                 *phy = phy_7101;
11857                 break;
11858         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
11859                 *phy = phy_null;
11860                 return -EINVAL;
11861         default:
11862                 *phy = phy_null;
11863                 /* In case external PHY wasn't found */
11864                 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
11865                     (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11866                         return -EINVAL;
11867                 return 0;
11868         }
11869
11870         phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
11871         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
11872
11873         /* The shmem address of the phy version is located on different
11874          * structures. In case this structure is too old, do not set
11875          * the address
11876          */
11877         config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
11878                                         dev_info.shared_hw_config.config2));
11879         if (phy_index == EXT_PHY1) {
11880                 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
11881                                 port_mb[port].ext_phy_fw_version);
11882
11883                 /* Check specific mdc mdio settings */
11884                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
11885                         mdc_mdio_access = config2 &
11886                         SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
11887         } else {
11888                 u32 size = REG_RD(bp, shmem2_base);
11889
11890                 if (size >
11891                     offsetof(struct shmem2_region, ext_phy_fw_version2)) {
11892                         phy->ver_addr = shmem2_base +
11893                             offsetof(struct shmem2_region,
11894                                      ext_phy_fw_version2[port]);
11895                 }
11896                 /* Check specific mdc mdio settings */
11897                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
11898                         mdc_mdio_access = (config2 &
11899                         SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
11900                         (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
11901                          SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
11902         }
11903         phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
11904
11905         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
11906             (phy->ver_addr)) {
11907                 /* Remove 100Mb link supported for BCM84833 when phy fw
11908                  * version lower than or equal to 1.39
11909                  */
11910                 u32 raw_ver = REG_RD(bp, phy->ver_addr);
11911                 if (((raw_ver & 0x7F) <= 39) &&
11912                     (((raw_ver & 0xF80) >> 7) <= 1))
11913                         phy->supported &= ~(SUPPORTED_100baseT_Half |
11914                                             SUPPORTED_100baseT_Full);
11915         }
11916
11917         /* In case mdc/mdio_access of the external phy is different than the
11918          * mdc/mdio access of the XGXS, a HW lock must be taken in each access
11919          * to prevent one port interfere with another port's CL45 operations.
11920          */
11921         if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
11922                 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
11923         DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
11924                    phy_type, port, phy_index);
11925         DP(NETIF_MSG_LINK, "             addr=0x%x, mdio_ctl=0x%x\n",
11926                    phy->addr, phy->mdio_ctrl);
11927         return 0;
11928 }
11929
11930 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
11931                               u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
11932 {
11933         int status = 0;
11934         phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
11935         if (phy_index == INT_PHY)
11936                 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
11937         status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
11938                                         port, phy);
11939         return status;
11940 }
11941
11942 static void bnx2x_phy_def_cfg(struct link_params *params,
11943                               struct bnx2x_phy *phy,
11944                               u8 phy_index)
11945 {
11946         struct bnx2x *bp = params->bp;
11947         u32 link_config;
11948         /* Populate the default phy configuration for MF mode */
11949         if (phy_index == EXT_PHY2) {
11950                 link_config = REG_RD(bp, params->shmem_base +
11951                                      offsetof(struct shmem_region, dev_info.
11952                         port_feature_config[params->port].link_config2));
11953                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11954                                              offsetof(struct shmem_region,
11955                                                       dev_info.
11956                         port_hw_config[params->port].speed_capability_mask2));
11957         } else {
11958                 link_config = REG_RD(bp, params->shmem_base +
11959                                      offsetof(struct shmem_region, dev_info.
11960                                 port_feature_config[params->port].link_config));
11961                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11962                                              offsetof(struct shmem_region,
11963                                                       dev_info.
11964                         port_hw_config[params->port].speed_capability_mask));
11965         }
11966         DP(NETIF_MSG_LINK,
11967            "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
11968            phy_index, link_config, phy->speed_cap_mask);
11969
11970         phy->req_duplex = DUPLEX_FULL;
11971         switch (link_config  & PORT_FEATURE_LINK_SPEED_MASK) {
11972         case PORT_FEATURE_LINK_SPEED_10M_HALF:
11973                 phy->req_duplex = DUPLEX_HALF;
11974         case PORT_FEATURE_LINK_SPEED_10M_FULL:
11975                 phy->req_line_speed = SPEED_10;
11976                 break;
11977         case PORT_FEATURE_LINK_SPEED_100M_HALF:
11978                 phy->req_duplex = DUPLEX_HALF;
11979         case PORT_FEATURE_LINK_SPEED_100M_FULL:
11980                 phy->req_line_speed = SPEED_100;
11981                 break;
11982         case PORT_FEATURE_LINK_SPEED_1G:
11983                 phy->req_line_speed = SPEED_1000;
11984                 break;
11985         case PORT_FEATURE_LINK_SPEED_2_5G:
11986                 phy->req_line_speed = SPEED_2500;
11987                 break;
11988         case PORT_FEATURE_LINK_SPEED_10G_CX4:
11989                 phy->req_line_speed = SPEED_10000;
11990                 break;
11991         default:
11992                 phy->req_line_speed = SPEED_AUTO_NEG;
11993                 break;
11994         }
11995
11996         switch (link_config  & PORT_FEATURE_FLOW_CONTROL_MASK) {
11997         case PORT_FEATURE_FLOW_CONTROL_AUTO:
11998                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
11999                 break;
12000         case PORT_FEATURE_FLOW_CONTROL_TX:
12001                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
12002                 break;
12003         case PORT_FEATURE_FLOW_CONTROL_RX:
12004                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
12005                 break;
12006         case PORT_FEATURE_FLOW_CONTROL_BOTH:
12007                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
12008                 break;
12009         default:
12010                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12011                 break;
12012         }
12013 }
12014
12015 u32 bnx2x_phy_selection(struct link_params *params)
12016 {
12017         u32 phy_config_swapped, prio_cfg;
12018         u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
12019
12020         phy_config_swapped = params->multi_phy_config &
12021                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12022
12023         prio_cfg = params->multi_phy_config &
12024                         PORT_HW_CFG_PHY_SELECTION_MASK;
12025
12026         if (phy_config_swapped) {
12027                 switch (prio_cfg) {
12028                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
12029                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
12030                      break;
12031                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
12032                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
12033                      break;
12034                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
12035                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
12036                      break;
12037                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
12038                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
12039                      break;
12040                 }
12041         } else
12042                 return_cfg = prio_cfg;
12043
12044         return return_cfg;
12045 }
12046
12047
12048 int bnx2x_phy_probe(struct link_params *params)
12049 {
12050         u8 phy_index, actual_phy_idx;
12051         u32 phy_config_swapped, sync_offset, media_types;
12052         struct bnx2x *bp = params->bp;
12053         struct bnx2x_phy *phy;
12054         params->num_phys = 0;
12055         DP(NETIF_MSG_LINK, "Begin phy probe\n");
12056         phy_config_swapped = params->multi_phy_config &
12057                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12058
12059         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12060               phy_index++) {
12061                 actual_phy_idx = phy_index;
12062                 if (phy_config_swapped) {
12063                         if (phy_index == EXT_PHY1)
12064                                 actual_phy_idx = EXT_PHY2;
12065                         else if (phy_index == EXT_PHY2)
12066                                 actual_phy_idx = EXT_PHY1;
12067                 }
12068                 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
12069                                " actual_phy_idx %x\n", phy_config_swapped,
12070                            phy_index, actual_phy_idx);
12071                 phy = &params->phy[actual_phy_idx];
12072                 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
12073                                        params->shmem2_base, params->port,
12074                                        phy) != 0) {
12075                         params->num_phys = 0;
12076                         DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
12077                                    phy_index);
12078                         for (phy_index = INT_PHY;
12079                               phy_index < MAX_PHYS;
12080                               phy_index++)
12081                                 *phy = phy_null;
12082                         return -EINVAL;
12083                 }
12084                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
12085                         break;
12086
12087                 if (params->feature_config_flags &
12088                     FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
12089                         phy->flags &= ~FLAGS_TX_ERROR_CHECK;
12090
12091                 sync_offset = params->shmem_base +
12092                         offsetof(struct shmem_region,
12093                         dev_info.port_hw_config[params->port].media_type);
12094                 media_types = REG_RD(bp, sync_offset);
12095
12096                 /* Update media type for non-PMF sync only for the first time
12097                  * In case the media type changes afterwards, it will be updated
12098                  * using the update_status function
12099                  */
12100                 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
12101                                     (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12102                                      actual_phy_idx))) == 0) {
12103                         media_types |= ((phy->media_type &
12104                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
12105                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12106                                  actual_phy_idx));
12107                 }
12108                 REG_WR(bp, sync_offset, media_types);
12109
12110                 bnx2x_phy_def_cfg(params, phy, phy_index);
12111                 params->num_phys++;
12112         }
12113
12114         DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
12115         return 0;
12116 }
12117
12118 void bnx2x_init_bmac_loopback(struct link_params *params,
12119                               struct link_vars *vars)
12120 {
12121         struct bnx2x *bp = params->bp;
12122                 vars->link_up = 1;
12123                 vars->line_speed = SPEED_10000;
12124                 vars->duplex = DUPLEX_FULL;
12125                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12126                 vars->mac_type = MAC_TYPE_BMAC;
12127
12128                 vars->phy_flags = PHY_XGXS_FLAG;
12129
12130                 bnx2x_xgxs_deassert(params);
12131
12132                 /* set bmac loopback */
12133                 bnx2x_bmac_enable(params, vars, 1);
12134
12135                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12136 }
12137
12138 void bnx2x_init_emac_loopback(struct link_params *params,
12139                               struct link_vars *vars)
12140 {
12141         struct bnx2x *bp = params->bp;
12142                 vars->link_up = 1;
12143                 vars->line_speed = SPEED_1000;
12144                 vars->duplex = DUPLEX_FULL;
12145                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12146                 vars->mac_type = MAC_TYPE_EMAC;
12147
12148                 vars->phy_flags = PHY_XGXS_FLAG;
12149
12150                 bnx2x_xgxs_deassert(params);
12151                 /* set bmac loopback */
12152                 bnx2x_emac_enable(params, vars, 1);
12153                 bnx2x_emac_program(params, vars);
12154                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12155 }
12156
12157 void bnx2x_init_xmac_loopback(struct link_params *params,
12158                               struct link_vars *vars)
12159 {
12160         struct bnx2x *bp = params->bp;
12161         vars->link_up = 1;
12162         if (!params->req_line_speed[0])
12163                 vars->line_speed = SPEED_10000;
12164         else
12165                 vars->line_speed = params->req_line_speed[0];
12166         vars->duplex = DUPLEX_FULL;
12167         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12168         vars->mac_type = MAC_TYPE_XMAC;
12169         vars->phy_flags = PHY_XGXS_FLAG;
12170         /* Set WC to loopback mode since link is required to provide clock
12171          * to the XMAC in 20G mode
12172          */
12173         bnx2x_set_aer_mmd(params, &params->phy[0]);
12174         bnx2x_warpcore_reset_lane(bp, &params->phy[0], 0);
12175         params->phy[INT_PHY].config_loopback(
12176                         &params->phy[INT_PHY],
12177                         params);
12178
12179         bnx2x_xmac_enable(params, vars, 1);
12180         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12181 }
12182
12183 void bnx2x_init_umac_loopback(struct link_params *params,
12184                               struct link_vars *vars)
12185 {
12186         struct bnx2x *bp = params->bp;
12187         vars->link_up = 1;
12188         vars->line_speed = SPEED_1000;
12189         vars->duplex = DUPLEX_FULL;
12190         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12191         vars->mac_type = MAC_TYPE_UMAC;
12192         vars->phy_flags = PHY_XGXS_FLAG;
12193         bnx2x_umac_enable(params, vars, 1);
12194
12195         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12196 }
12197
12198 void bnx2x_init_xgxs_loopback(struct link_params *params,
12199                               struct link_vars *vars)
12200 {
12201         struct bnx2x *bp = params->bp;
12202                 vars->link_up = 1;
12203                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12204                 vars->duplex = DUPLEX_FULL;
12205         if (params->req_line_speed[0] == SPEED_1000)
12206                         vars->line_speed = SPEED_1000;
12207         else
12208                         vars->line_speed = SPEED_10000;
12209
12210         if (!USES_WARPCORE(bp))
12211                 bnx2x_xgxs_deassert(params);
12212         bnx2x_link_initialize(params, vars);
12213
12214         if (params->req_line_speed[0] == SPEED_1000) {
12215                 if (USES_WARPCORE(bp))
12216                         bnx2x_umac_enable(params, vars, 0);
12217                 else {
12218                         bnx2x_emac_program(params, vars);
12219                         bnx2x_emac_enable(params, vars, 0);
12220                 }
12221         } else {
12222                 if (USES_WARPCORE(bp))
12223                         bnx2x_xmac_enable(params, vars, 0);
12224                 else
12225                         bnx2x_bmac_enable(params, vars, 0);
12226         }
12227
12228                 if (params->loopback_mode == LOOPBACK_XGXS) {
12229                         /* set 10G XGXS loopback */
12230                         params->phy[INT_PHY].config_loopback(
12231                                 &params->phy[INT_PHY],
12232                                 params);
12233
12234                 } else {
12235                         /* set external phy loopback */
12236                         u8 phy_index;
12237                         for (phy_index = EXT_PHY1;
12238                               phy_index < params->num_phys; phy_index++) {
12239                                 if (params->phy[phy_index].config_loopback)
12240                                         params->phy[phy_index].config_loopback(
12241                                                 &params->phy[phy_index],
12242                                                 params);
12243                         }
12244                 }
12245                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12246
12247         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
12248 }
12249
12250 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
12251 {
12252         struct bnx2x *bp = params->bp;
12253         DP(NETIF_MSG_LINK, "Phy Initialization started\n");
12254         DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
12255                    params->req_line_speed[0], params->req_flow_ctrl[0]);
12256         DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
12257                    params->req_line_speed[1], params->req_flow_ctrl[1]);
12258         vars->link_status = 0;
12259         vars->phy_link_up = 0;
12260         vars->link_up = 0;
12261         vars->line_speed = 0;
12262         vars->duplex = DUPLEX_FULL;
12263         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12264         vars->mac_type = MAC_TYPE_NONE;
12265         vars->phy_flags = 0;
12266
12267         /* disable attentions */
12268         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12269                        (NIG_MASK_XGXS0_LINK_STATUS |
12270                         NIG_MASK_XGXS0_LINK10G |
12271                         NIG_MASK_SERDES0_LINK_STATUS |
12272                         NIG_MASK_MI_INT));
12273
12274         bnx2x_emac_init(params, vars);
12275
12276         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
12277                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
12278
12279         if (params->num_phys == 0) {
12280                 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
12281                 return -EINVAL;
12282         }
12283         set_phy_vars(params, vars);
12284
12285         DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
12286         switch (params->loopback_mode) {
12287         case LOOPBACK_BMAC:
12288                 bnx2x_init_bmac_loopback(params, vars);
12289                 break;
12290         case LOOPBACK_EMAC:
12291                 bnx2x_init_emac_loopback(params, vars);
12292                 break;
12293         case LOOPBACK_XMAC:
12294                 bnx2x_init_xmac_loopback(params, vars);
12295                 break;
12296         case LOOPBACK_UMAC:
12297                 bnx2x_init_umac_loopback(params, vars);
12298                 break;
12299         case LOOPBACK_XGXS:
12300         case LOOPBACK_EXT_PHY:
12301                 bnx2x_init_xgxs_loopback(params, vars);
12302                 break;
12303         default:
12304                 if (!CHIP_IS_E3(bp)) {
12305                         if (params->switch_cfg == SWITCH_CFG_10G)
12306                                 bnx2x_xgxs_deassert(params);
12307                         else
12308                                 bnx2x_serdes_deassert(bp, params->port);
12309                 }
12310                 bnx2x_link_initialize(params, vars);
12311                 msleep(30);
12312                 bnx2x_link_int_enable(params);
12313                 break;
12314         }
12315         bnx2x_update_mng(params, vars->link_status);
12316
12317         bnx2x_update_mng_eee(params, vars->eee_status);
12318         return 0;
12319 }
12320
12321 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
12322                      u8 reset_ext_phy)
12323 {
12324         struct bnx2x *bp = params->bp;
12325         u8 phy_index, port = params->port, clear_latch_ind = 0;
12326         DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
12327         /* disable attentions */
12328         vars->link_status = 0;
12329         bnx2x_update_mng(params, vars->link_status);
12330         vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
12331                               SHMEM_EEE_ACTIVE_BIT);
12332         bnx2x_update_mng_eee(params, vars->eee_status);
12333         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
12334                        (NIG_MASK_XGXS0_LINK_STATUS |
12335                         NIG_MASK_XGXS0_LINK10G |
12336                         NIG_MASK_SERDES0_LINK_STATUS |
12337                         NIG_MASK_MI_INT));
12338
12339         /* activate nig drain */
12340         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
12341
12342         /* disable nig egress interface */
12343         if (!CHIP_IS_E3(bp)) {
12344                 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
12345                 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
12346         }
12347
12348         /* Stop BigMac rx */
12349         if (!CHIP_IS_E3(bp))
12350                 bnx2x_bmac_rx_disable(bp, port);
12351         else {
12352                 bnx2x_xmac_disable(params);
12353                 bnx2x_umac_disable(params);
12354         }
12355         /* disable emac */
12356         if (!CHIP_IS_E3(bp))
12357                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
12358
12359         msleep(10);
12360         /* The PHY reset is controlled by GPIO 1
12361          * Hold it as vars low
12362          */
12363          /* clear link led */
12364         bnx2x_set_mdio_clk(bp, params->chip_id, port);
12365         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
12366
12367         if (reset_ext_phy) {
12368                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
12369                       phy_index++) {
12370                         if (params->phy[phy_index].link_reset) {
12371                                 bnx2x_set_aer_mmd(params,
12372                                                   &params->phy[phy_index]);
12373                                 params->phy[phy_index].link_reset(
12374                                         &params->phy[phy_index],
12375                                         params);
12376                         }
12377                         if (params->phy[phy_index].flags &
12378                             FLAGS_REARM_LATCH_SIGNAL)
12379                                 clear_latch_ind = 1;
12380                 }
12381         }
12382
12383         if (clear_latch_ind) {
12384                 /* Clear latching indication */
12385                 bnx2x_rearm_latch_signal(bp, port, 0);
12386                 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
12387                                1 << NIG_LATCH_BC_ENABLE_MI_INT);
12388         }
12389         if (params->phy[INT_PHY].link_reset)
12390                 params->phy[INT_PHY].link_reset(
12391                         &params->phy[INT_PHY], params);
12392
12393         /* disable nig ingress interface */
12394         if (!CHIP_IS_E3(bp)) {
12395                 /* reset BigMac */
12396                 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
12397                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
12398                 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
12399                 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
12400         } else {
12401                 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12402                 bnx2x_set_xumac_nig(params, 0, 0);
12403                 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12404                     MISC_REGISTERS_RESET_REG_2_XMAC)
12405                         REG_WR(bp, xmac_base + XMAC_REG_CTRL,
12406                                XMAC_CTRL_REG_SOFT_RESET);
12407         }
12408         vars->link_up = 0;
12409         vars->phy_flags = 0;
12410         return 0;
12411 }
12412
12413 /****************************************************************************/
12414 /*                              Common function                             */
12415 /****************************************************************************/
12416 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
12417                                       u32 shmem_base_path[],
12418                                       u32 shmem2_base_path[], u8 phy_index,
12419                                       u32 chip_id)
12420 {
12421         struct bnx2x_phy phy[PORT_MAX];
12422         struct bnx2x_phy *phy_blk[PORT_MAX];
12423         u16 val;
12424         s8 port = 0;
12425         s8 port_of_path = 0;
12426         u32 swap_val, swap_override;
12427         swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);
12428         swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);
12429         port ^= (swap_val && swap_override);
12430         bnx2x_ext_phy_hw_reset(bp, port);
12431         /* PART1 - Reset both phys */
12432         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12433                 u32 shmem_base, shmem2_base;
12434                 /* In E2, same phy is using for port0 of the two paths */
12435                 if (CHIP_IS_E1x(bp)) {
12436                         shmem_base = shmem_base_path[0];
12437                         shmem2_base = shmem2_base_path[0];
12438                         port_of_path = port;
12439                 } else {
12440                         shmem_base = shmem_base_path[port];
12441                         shmem2_base = shmem2_base_path[port];
12442                         port_of_path = 0;
12443                 }
12444
12445                 /* Extract the ext phy address for the port */
12446                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12447                                        port_of_path, &phy[port]) !=
12448                     0) {
12449                         DP(NETIF_MSG_LINK, "populate_phy failed\n");
12450                         return -EINVAL;
12451                 }
12452                 /* disable attentions */
12453                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12454                                port_of_path*4,
12455                                (NIG_MASK_XGXS0_LINK_STATUS |
12456                                 NIG_MASK_XGXS0_LINK10G |
12457                                 NIG_MASK_SERDES0_LINK_STATUS |
12458                                 NIG_MASK_MI_INT));
12459
12460                 /* Need to take the phy out of low power mode in order
12461                  * to write to access its registers
12462                  */
12463                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12464                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12465                                port);
12466
12467                 /* Reset the phy */
12468                 bnx2x_cl45_write(bp, &phy[port],
12469                                  MDIO_PMA_DEVAD,
12470                                  MDIO_PMA_REG_CTRL,
12471                                  1<<15);
12472         }
12473
12474         /* Add delay of 150ms after reset */
12475         msleep(150);
12476
12477         if (phy[PORT_0].addr & 0x1) {
12478                 phy_blk[PORT_0] = &(phy[PORT_1]);
12479                 phy_blk[PORT_1] = &(phy[PORT_0]);
12480         } else {
12481                 phy_blk[PORT_0] = &(phy[PORT_0]);
12482                 phy_blk[PORT_1] = &(phy[PORT_1]);
12483         }
12484
12485         /* PART2 - Download firmware to both phys */
12486         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12487                 if (CHIP_IS_E1x(bp))
12488                         port_of_path = port;
12489                 else
12490                         port_of_path = 0;
12491
12492                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12493                            phy_blk[port]->addr);
12494                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12495                                                       port_of_path))
12496                         return -EINVAL;
12497
12498                 /* Only set bit 10 = 1 (Tx power down) */
12499                 bnx2x_cl45_read(bp, phy_blk[port],
12500                                 MDIO_PMA_DEVAD,
12501                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12502
12503                 /* Phase1 of TX_POWER_DOWN reset */
12504                 bnx2x_cl45_write(bp, phy_blk[port],
12505                                  MDIO_PMA_DEVAD,
12506                                  MDIO_PMA_REG_TX_POWER_DOWN,
12507                                  (val | 1<<10));
12508         }
12509
12510         /* Toggle Transmitter: Power down and then up with 600ms delay
12511          * between
12512          */
12513         msleep(600);
12514
12515         /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12516         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12517                 /* Phase2 of POWER_DOWN_RESET */
12518                 /* Release bit 10 (Release Tx power down) */
12519                 bnx2x_cl45_read(bp, phy_blk[port],
12520                                 MDIO_PMA_DEVAD,
12521                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12522
12523                 bnx2x_cl45_write(bp, phy_blk[port],
12524                                 MDIO_PMA_DEVAD,
12525                                 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
12526                 msleep(15);
12527
12528                 /* Read modify write the SPI-ROM version select register */
12529                 bnx2x_cl45_read(bp, phy_blk[port],
12530                                 MDIO_PMA_DEVAD,
12531                                 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
12532                 bnx2x_cl45_write(bp, phy_blk[port],
12533                                  MDIO_PMA_DEVAD,
12534                                  MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
12535
12536                 /* set GPIO2 back to LOW */
12537                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12538                                MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
12539         }
12540         return 0;
12541 }
12542 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
12543                                       u32 shmem_base_path[],
12544                                       u32 shmem2_base_path[], u8 phy_index,
12545                                       u32 chip_id)
12546 {
12547         u32 val;
12548         s8 port;
12549         struct bnx2x_phy phy;
12550         /* Use port1 because of the static port-swap */
12551         /* Enable the module detection interrupt */
12552         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12553         val |= ((1<<MISC_REGISTERS_GPIO_3)|
12554                 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
12555         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12556
12557         bnx2x_ext_phy_hw_reset(bp, 0);
12558         msleep(5);
12559         for (port = 0; port < PORT_MAX; port++) {
12560                 u32 shmem_base, shmem2_base;
12561
12562                 /* In E2, same phy is using for port0 of the two paths */
12563                 if (CHIP_IS_E1x(bp)) {
12564                         shmem_base = shmem_base_path[0];
12565                         shmem2_base = shmem2_base_path[0];
12566                 } else {
12567                         shmem_base = shmem_base_path[port];
12568                         shmem2_base = shmem2_base_path[port];
12569                 }
12570                 /* Extract the ext phy address for the port */
12571                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12572                                        port, &phy) !=
12573                     0) {
12574                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12575                         return -EINVAL;
12576                 }
12577
12578                 /* Reset phy*/
12579                 bnx2x_cl45_write(bp, &phy,
12580                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
12581
12582
12583                 /* Set fault module detected LED on */
12584                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
12585                                MISC_REGISTERS_GPIO_HIGH,
12586                                port);
12587         }
12588
12589         return 0;
12590 }
12591 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
12592                                          u8 *io_gpio, u8 *io_port)
12593 {
12594
12595         u32 phy_gpio_reset = REG_RD(bp, shmem_base +
12596                                           offsetof(struct shmem_region,
12597                                 dev_info.port_hw_config[PORT_0].default_cfg));
12598         switch (phy_gpio_reset) {
12599         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
12600                 *io_gpio = 0;
12601                 *io_port = 0;
12602                 break;
12603         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
12604                 *io_gpio = 1;
12605                 *io_port = 0;
12606                 break;
12607         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
12608                 *io_gpio = 2;
12609                 *io_port = 0;
12610                 break;
12611         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
12612                 *io_gpio = 3;
12613                 *io_port = 0;
12614                 break;
12615         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
12616                 *io_gpio = 0;
12617                 *io_port = 1;
12618                 break;
12619         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
12620                 *io_gpio = 1;
12621                 *io_port = 1;
12622                 break;
12623         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
12624                 *io_gpio = 2;
12625                 *io_port = 1;
12626                 break;
12627         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
12628                 *io_gpio = 3;
12629                 *io_port = 1;
12630                 break;
12631         default:
12632                 /* Don't override the io_gpio and io_port */
12633                 break;
12634         }
12635 }
12636
12637 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
12638                                       u32 shmem_base_path[],
12639                                       u32 shmem2_base_path[], u8 phy_index,
12640                                       u32 chip_id)
12641 {
12642         s8 port, reset_gpio;
12643         u32 swap_val, swap_override;
12644         struct bnx2x_phy phy[PORT_MAX];
12645         struct bnx2x_phy *phy_blk[PORT_MAX];
12646         s8 port_of_path;
12647         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12648         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12649
12650         reset_gpio = MISC_REGISTERS_GPIO_1;
12651         port = 1;
12652
12653         /* Retrieve the reset gpio/port which control the reset.
12654          * Default is GPIO1, PORT1
12655          */
12656         bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
12657                                      (u8 *)&reset_gpio, (u8 *)&port);
12658
12659         /* Calculate the port based on port swap */
12660         port ^= (swap_val && swap_override);
12661
12662         /* Initiate PHY reset*/
12663         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
12664                        port);
12665         msleep(1);
12666         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12667                        port);
12668
12669         msleep(5);
12670
12671         /* PART1 - Reset both phys */
12672         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12673                 u32 shmem_base, shmem2_base;
12674
12675                 /* In E2, same phy is using for port0 of the two paths */
12676                 if (CHIP_IS_E1x(bp)) {
12677                         shmem_base = shmem_base_path[0];
12678                         shmem2_base = shmem2_base_path[0];
12679                         port_of_path = port;
12680                 } else {
12681                         shmem_base = shmem_base_path[port];
12682                         shmem2_base = shmem2_base_path[port];
12683                         port_of_path = 0;
12684                 }
12685
12686                 /* Extract the ext phy address for the port */
12687                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12688                                        port_of_path, &phy[port]) !=
12689                                        0) {
12690                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12691                         return -EINVAL;
12692                 }
12693                 /* disable attentions */
12694                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12695                                port_of_path*4,
12696                                (NIG_MASK_XGXS0_LINK_STATUS |
12697                                 NIG_MASK_XGXS0_LINK10G |
12698                                 NIG_MASK_SERDES0_LINK_STATUS |
12699                                 NIG_MASK_MI_INT));
12700
12701
12702                 /* Reset the phy */
12703                 bnx2x_cl45_write(bp, &phy[port],
12704                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
12705         }
12706
12707         /* Add delay of 150ms after reset */
12708         msleep(150);
12709         if (phy[PORT_0].addr & 0x1) {
12710                 phy_blk[PORT_0] = &(phy[PORT_1]);
12711                 phy_blk[PORT_1] = &(phy[PORT_0]);
12712         } else {
12713                 phy_blk[PORT_0] = &(phy[PORT_0]);
12714                 phy_blk[PORT_1] = &(phy[PORT_1]);
12715         }
12716         /* PART2 - Download firmware to both phys */
12717         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12718                 if (CHIP_IS_E1x(bp))
12719                         port_of_path = port;
12720                 else
12721                         port_of_path = 0;
12722                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12723                            phy_blk[port]->addr);
12724                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12725                                                       port_of_path))
12726                         return -EINVAL;
12727                 /* Disable PHY transmitter output */
12728                 bnx2x_cl45_write(bp, phy_blk[port],
12729                                  MDIO_PMA_DEVAD,
12730                                  MDIO_PMA_REG_TX_DISABLE, 1);
12731
12732         }
12733         return 0;
12734 }
12735
12736 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
12737                                                 u32 shmem_base_path[],
12738                                                 u32 shmem2_base_path[],
12739                                                 u8 phy_index,
12740                                                 u32 chip_id)
12741 {
12742         u8 reset_gpios;
12743         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
12744         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
12745         udelay(10);
12746         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
12747         DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
12748                 reset_gpios);
12749         return 0;
12750 }
12751
12752 static int bnx2x_84833_pre_init_phy(struct bnx2x *bp,
12753                                                struct bnx2x_phy *phy)
12754 {
12755         u16 val, cnt;
12756         /* Wait for FW completing its initialization. */
12757         for (cnt = 0; cnt < 1500; cnt++) {
12758                 bnx2x_cl45_read(bp, phy,
12759                                 MDIO_PMA_DEVAD,
12760                                 MDIO_PMA_REG_CTRL, &val);
12761                 if (!(val & (1<<15)))
12762                         break;
12763                 msleep(1);
12764         }
12765         if (cnt >= 1500) {
12766                 DP(NETIF_MSG_LINK, "84833 reset timeout\n");
12767                 return -EINVAL;
12768         }
12769
12770         /* Put the port in super isolate mode. */
12771         bnx2x_cl45_read(bp, phy,
12772                         MDIO_CTL_DEVAD,
12773                         MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
12774         val |= MDIO_84833_SUPER_ISOLATE;
12775         bnx2x_cl45_write(bp, phy,
12776                          MDIO_CTL_DEVAD,
12777                          MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
12778
12779         /* Save spirom version */
12780         bnx2x_save_848xx_spirom_version(phy, bp, PORT_0);
12781         return 0;
12782 }
12783
12784 int bnx2x_pre_init_phy(struct bnx2x *bp,
12785                                   u32 shmem_base,
12786                                   u32 shmem2_base,
12787                                   u32 chip_id)
12788 {
12789         int rc = 0;
12790         struct bnx2x_phy phy;
12791         bnx2x_set_mdio_clk(bp, chip_id, PORT_0);
12792         if (bnx2x_populate_phy(bp, EXT_PHY1, shmem_base, shmem2_base,
12793                                PORT_0, &phy)) {
12794                 DP(NETIF_MSG_LINK, "populate_phy failed\n");
12795                 return -EINVAL;
12796         }
12797         switch (phy.type) {
12798         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12799                 rc = bnx2x_84833_pre_init_phy(bp, &phy);
12800                 break;
12801         default:
12802                 break;
12803         }
12804         return rc;
12805 }
12806
12807 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
12808                                      u32 shmem2_base_path[], u8 phy_index,
12809                                      u32 ext_phy_type, u32 chip_id)
12810 {
12811         int rc = 0;
12812
12813         switch (ext_phy_type) {
12814         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12815                 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
12816                                                 shmem2_base_path,
12817                                                 phy_index, chip_id);
12818                 break;
12819         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12820         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12821         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12822                 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
12823                                                 shmem2_base_path,
12824                                                 phy_index, chip_id);
12825                 break;
12826
12827         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12828                 /* GPIO1 affects both ports, so there's need to pull
12829                  * it for single port alone
12830                  */
12831                 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
12832                                                 shmem2_base_path,
12833                                                 phy_index, chip_id);
12834                 break;
12835         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12836                 /* GPIO3's are linked, and so both need to be toggled
12837                  * to obtain required 2us pulse.
12838                  */
12839                 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path,
12840                                                 shmem2_base_path,
12841                                                 phy_index, chip_id);
12842                 break;
12843         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12844                 rc = -EINVAL;
12845                 break;
12846         default:
12847                 DP(NETIF_MSG_LINK,
12848                            "ext_phy 0x%x common init not required\n",
12849                            ext_phy_type);
12850                 break;
12851         }
12852
12853         if (rc != 0)
12854                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
12855                                       " Port %d\n",
12856                          0);
12857         return rc;
12858 }
12859
12860 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
12861                           u32 shmem2_base_path[], u32 chip_id)
12862 {
12863         int rc = 0;
12864         u32 phy_ver, val;
12865         u8 phy_index = 0;
12866         u32 ext_phy_type, ext_phy_config;
12867         bnx2x_set_mdio_clk(bp, chip_id, PORT_0);
12868         bnx2x_set_mdio_clk(bp, chip_id, PORT_1);
12869         DP(NETIF_MSG_LINK, "Begin common phy init\n");
12870         if (CHIP_IS_E3(bp)) {
12871                 /* Enable EPIO */
12872                 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
12873                 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
12874         }
12875         /* Check if common init was already done */
12876         phy_ver = REG_RD(bp, shmem_base_path[0] +
12877                          offsetof(struct shmem_region,
12878                                   port_mb[PORT_0].ext_phy_fw_version));
12879         if (phy_ver) {
12880                 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
12881                                phy_ver);
12882                 return 0;
12883         }
12884
12885         /* Read the ext_phy_type for arbitrary port(0) */
12886         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12887               phy_index++) {
12888                 ext_phy_config = bnx2x_get_ext_phy_config(bp,
12889                                                           shmem_base_path[0],
12890                                                           phy_index, 0);
12891                 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
12892                 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
12893                                                 shmem2_base_path,
12894                                                 phy_index, ext_phy_type,
12895                                                 chip_id);
12896         }
12897         return rc;
12898 }
12899
12900 static void bnx2x_check_over_curr(struct link_params *params,
12901                                   struct link_vars *vars)
12902 {
12903         struct bnx2x *bp = params->bp;
12904         u32 cfg_pin;
12905         u8 port = params->port;
12906         u32 pin_val;
12907
12908         cfg_pin = (REG_RD(bp, params->shmem_base +
12909                           offsetof(struct shmem_region,
12910                                dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
12911                    PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
12912                 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
12913
12914         /* Ignore check if no external input PIN available */
12915         if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
12916                 return;
12917
12918         if (!pin_val) {
12919                 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
12920                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
12921                                             " been detected and the power to "
12922                                             "that SFP+ module has been removed"
12923                                             " to prevent failure of the card."
12924                                             " Please remove the SFP+ module and"
12925                                             " restart the system to clear this"
12926                                             " error.\n",
12927                          params->port);
12928                         vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
12929                 }
12930         } else
12931                 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
12932 }
12933
12934 static void bnx2x_analyze_link_error(struct link_params *params,
12935                                      struct link_vars *vars, u32 lss_status,
12936                                      u8 notify)
12937 {
12938         struct bnx2x *bp = params->bp;
12939         /* Compare new value with previous value */
12940         u8 led_mode;
12941         u32 half_open_conn = (vars->phy_flags & PHY_HALF_OPEN_CONN_FLAG) > 0;
12942
12943         if ((lss_status ^ half_open_conn) == 0)
12944                 return;
12945
12946         /* If values differ */
12947         DP(NETIF_MSG_LINK, "Link changed:%x %x->%x\n", vars->link_up,
12948                        half_open_conn, lss_status);
12949
12950         /* a. Update shmem->link_status accordingly
12951          * b. Update link_vars->link_up
12952          */
12953         if (lss_status) {
12954                 DP(NETIF_MSG_LINK, "Remote Fault detected !!!\n");
12955                 vars->link_status &= ~LINK_STATUS_LINK_UP;
12956                 vars->link_up = 0;
12957                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
12958
12959                 /* activate nig drain */
12960                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
12961                 /* Set LED mode to off since the PHY doesn't know about these
12962                  * errors
12963                  */
12964                 led_mode = LED_MODE_OFF;
12965         } else {
12966                 DP(NETIF_MSG_LINK, "Remote Fault cleared\n");
12967                 vars->link_status |= LINK_STATUS_LINK_UP;
12968                 vars->link_up = 1;
12969                 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
12970                 led_mode = LED_MODE_OPER;
12971
12972                 /* Clear nig drain */
12973                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12974         }
12975         bnx2x_sync_link(params, vars);
12976         /* Update the LED according to the link state */
12977         bnx2x_set_led(params, vars, led_mode, SPEED_10000);
12978
12979         /* Update link status in the shared memory */
12980         bnx2x_update_mng(params, vars->link_status);
12981
12982         /* C. Trigger General Attention */
12983         vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
12984         if (notify)
12985                 bnx2x_notify_link_changed(bp);
12986 }
12987
12988 /******************************************************************************
12989 * Description:
12990 *       This function checks for half opened connection change indication.
12991 *       When such change occurs, it calls the bnx2x_analyze_link_error
12992 *       to check if Remote Fault is set or cleared. Reception of remote fault
12993 *       status message in the MAC indicates that the peer's MAC has detected
12994 *       a fault, for example, due to break in the TX side of fiber.
12995 *
12996 ******************************************************************************/
12997 int bnx2x_check_half_open_conn(struct link_params *params,
12998                                 struct link_vars *vars,
12999                                 u8 notify)
13000 {
13001         struct bnx2x *bp = params->bp;
13002         u32 lss_status = 0;
13003         u32 mac_base;
13004         /* In case link status is physically up @ 10G do */
13005         if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
13006             (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
13007                 return 0;
13008
13009         if (CHIP_IS_E3(bp) &&
13010             (REG_RD(bp, MISC_REG_RESET_REG_2) &
13011               (MISC_REGISTERS_RESET_REG_2_XMAC))) {
13012                 /* Check E3 XMAC */
13013                 /* Note that link speed cannot be queried here, since it may be
13014                  * zero while link is down. In case UMAC is active, LSS will
13015                  * simply not be set
13016                  */
13017                 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13018
13019                 /* Clear stick bits (Requires rising edge) */
13020                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
13021                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
13022                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
13023                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
13024                 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
13025                         lss_status = 1;
13026
13027                 bnx2x_analyze_link_error(params, vars, lss_status, notify);
13028         } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
13029                    (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
13030                 /* Check E1X / E2 BMAC */
13031                 u32 lss_status_reg;
13032                 u32 wb_data[2];
13033                 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
13034                         NIG_REG_INGRESS_BMAC0_MEM;
13035                 /*  Read BIGMAC_REGISTER_RX_LSS_STATUS */
13036                 if (CHIP_IS_E2(bp))
13037                         lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
13038                 else
13039                         lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
13040
13041                 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
13042                 lss_status = (wb_data[0] > 0);
13043
13044                 bnx2x_analyze_link_error(params, vars, lss_status, notify);
13045         }
13046         return 0;
13047 }
13048
13049 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
13050 {
13051         u16 phy_idx;
13052         struct bnx2x *bp = params->bp;
13053         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
13054                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
13055                         bnx2x_set_aer_mmd(params, &params->phy[phy_idx]);
13056                         if (bnx2x_check_half_open_conn(params, vars, 1) !=
13057                             0)
13058                                 DP(NETIF_MSG_LINK, "Fault detection failed\n");
13059                         break;
13060                 }
13061         }
13062
13063         if (CHIP_IS_E3(bp)) {
13064                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
13065                 bnx2x_set_aer_mmd(params, phy);
13066                 bnx2x_check_over_curr(params, vars);
13067                 bnx2x_warpcore_config_runtime(phy, params, vars);
13068         }
13069
13070 }
13071
13072 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
13073 {
13074         u8 phy_index;
13075         struct bnx2x_phy phy;
13076         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
13077               phy_index++) {
13078                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13079                                        0, &phy) != 0) {
13080                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13081                         return 0;
13082                 }
13083
13084                 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
13085                         return 1;
13086         }
13087         return 0;
13088 }
13089
13090 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
13091                              u32 shmem_base,
13092                              u32 shmem2_base,
13093                              u8 port)
13094 {
13095         u8 phy_index, fan_failure_det_req = 0;
13096         struct bnx2x_phy phy;
13097         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13098               phy_index++) {
13099                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13100                                        port, &phy)
13101                     != 0) {
13102                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13103                         return 0;
13104                 }
13105                 fan_failure_det_req |= (phy.flags &
13106                                         FLAGS_FAN_FAILURE_DET_REQ);
13107         }
13108         return fan_failure_det_req;
13109 }
13110
13111 void bnx2x_hw_reset_phy(struct link_params *params)
13112 {
13113         u8 phy_index;
13114         struct bnx2x *bp = params->bp;
13115         bnx2x_update_mng(params, 0);
13116         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
13117                        (NIG_MASK_XGXS0_LINK_STATUS |
13118                         NIG_MASK_XGXS0_LINK10G |
13119                         NIG_MASK_SERDES0_LINK_STATUS |
13120                         NIG_MASK_MI_INT));
13121
13122         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
13123               phy_index++) {
13124                 if (params->phy[phy_index].hw_reset) {
13125                         params->phy[phy_index].hw_reset(
13126                                 &params->phy[phy_index],
13127                                 params);
13128                         params->phy[phy_index] = phy_null;
13129                 }
13130         }
13131 }
13132
13133 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
13134                             u32 chip_id, u32 shmem_base, u32 shmem2_base,
13135                             u8 port)
13136 {
13137         u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
13138         u32 val;
13139         u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
13140         if (CHIP_IS_E3(bp)) {
13141                 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
13142                                               shmem_base,
13143                                               port,
13144                                               &gpio_num,
13145                                               &gpio_port) != 0)
13146                         return;
13147         } else {
13148                 struct bnx2x_phy phy;
13149                 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13150                       phy_index++) {
13151                         if (bnx2x_populate_phy(bp, phy_index, shmem_base,
13152                                                shmem2_base, port, &phy)
13153                             != 0) {
13154                                 DP(NETIF_MSG_LINK, "populate phy failed\n");
13155                                 return;
13156                         }
13157                         if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
13158                                 gpio_num = MISC_REGISTERS_GPIO_3;
13159                                 gpio_port = port;
13160                                 break;
13161                         }
13162                 }
13163         }
13164
13165         if (gpio_num == 0xff)
13166                 return;
13167
13168         /* Set GPIO3 to trigger SFP+ module insertion/removal */
13169         bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
13170
13171         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13172         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13173         gpio_port ^= (swap_val && swap_override);
13174
13175         vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
13176                 (gpio_num + (gpio_port << 2));
13177
13178         sync_offset = shmem_base +
13179                 offsetof(struct shmem_region,
13180                          dev_info.port_hw_config[port].aeu_int_mask);
13181         REG_WR(bp, sync_offset, vars->aeu_int_mask);
13182
13183         DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
13184                        gpio_num, gpio_port, vars->aeu_int_mask);
13185
13186         if (port == 0)
13187                 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
13188         else
13189                 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
13190
13191         /* Open appropriate AEU for interrupts */
13192         aeu_mask = REG_RD(bp, offset);
13193         aeu_mask |= vars->aeu_int_mask;
13194         REG_WR(bp, offset, aeu_mask);
13195
13196         /* Enable the GPIO to trigger interrupt */
13197         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
13198         val |= 1 << (gpio_num + (gpio_port << 2));
13199         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
13200 }