1 /* Copyright 2008-2012 Broadcom Corporation
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
13 * Written by Yaniv Rosner
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/delay.h>
24 #include <linux/ethtool.h>
25 #include <linux/mutex.h>
28 #include "bnx2x_cmn.h"
30 /********************************************************/
32 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
33 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
34 #define ETH_MIN_PACKET_SIZE 60
35 #define ETH_MAX_PACKET_SIZE 1500
36 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
37 #define MDIO_ACCESS_TIMEOUT 1000
39 #define I2C_SWITCH_WIDTH 2
42 #define I2C_WA_RETRY_CNT 3
43 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
44 #define MCPR_IMC_COMMAND_READ_OP 1
45 #define MCPR_IMC_COMMAND_WRITE_OP 2
47 /* LED Blink rate that will achieve ~15.9Hz */
48 #define LED_BLINK_RATE_VAL_E3 354
49 #define LED_BLINK_RATE_VAL_E1X_E2 480
50 /***********************************************************/
51 /* Shortcut definitions */
52 /***********************************************************/
54 #define NIG_LATCH_BC_ENABLE_MI_INT 0
56 #define NIG_STATUS_EMAC0_MI_INT \
57 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
58 #define NIG_STATUS_XGXS0_LINK10G \
59 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
60 #define NIG_STATUS_XGXS0_LINK_STATUS \
61 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
62 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
63 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
64 #define NIG_STATUS_SERDES0_LINK_STATUS \
65 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
66 #define NIG_MASK_MI_INT \
67 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
68 #define NIG_MASK_XGXS0_LINK10G \
69 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
70 #define NIG_MASK_XGXS0_LINK_STATUS \
71 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
72 #define NIG_MASK_SERDES0_LINK_STATUS \
73 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
75 #define MDIO_AN_CL73_OR_37_COMPLETE \
76 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
77 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
79 #define XGXS_RESET_BITS \
80 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
81 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
82 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
83 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
84 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
86 #define SERDES_RESET_BITS \
87 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
88 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
89 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
90 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
92 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
93 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
94 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
95 #define AUTONEG_PARALLEL \
96 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
97 #define AUTONEG_SGMII_FIBER_AUTODET \
98 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
99 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
101 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
102 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
103 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
104 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
105 #define GP_STATUS_SPEED_MASK \
106 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
107 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
108 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
109 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
110 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
111 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
112 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
113 #define GP_STATUS_10G_HIG \
114 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
115 #define GP_STATUS_10G_CX4 \
116 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
117 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
118 #define GP_STATUS_10G_KX4 \
119 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
120 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
121 #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
122 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
123 #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
124 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
125 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
126 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
127 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
128 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
129 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
130 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
131 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
132 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
133 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
134 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
135 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
136 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
137 #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
138 #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
142 #define SFP_EEPROM_CON_TYPE_ADDR 0x2
143 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
144 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
147 #define SFP_EEPROM_COMP_CODE_ADDR 0x3
148 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
149 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
150 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
152 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
153 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
154 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
156 #define SFP_EEPROM_OPTIONS_ADDR 0x40
157 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
158 #define SFP_EEPROM_OPTIONS_SIZE 2
160 #define EDC_MODE_LINEAR 0x0022
161 #define EDC_MODE_LIMITING 0x0044
162 #define EDC_MODE_PASSIVE_DAC 0x0055
164 /* BRB default for class 0 E2 */
165 #define DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR 170
166 #define DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR 250
167 #define DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR 10
168 #define DEFAULT0_E2_BRB_MAC_FULL_XON_THR 50
170 /* BRB thresholds for E2*/
171 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE 170
172 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
174 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE 250
175 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
177 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE 10
178 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 90
180 #define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE 50
181 #define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE 250
183 /* BRB default for class 0 E3A0 */
184 #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR 290
185 #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR 410
186 #define DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR 10
187 #define DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR 50
189 /* BRB thresholds for E3A0 */
190 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE 290
191 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
193 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE 410
194 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
196 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE 10
197 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 170
199 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE 50
200 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE 410
202 /* BRB default for E3B0 */
203 #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR 330
204 #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR 490
205 #define DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR 15
206 #define DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR 55
208 /* BRB thresholds for E3B0 2 port mode*/
209 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 1025
210 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
212 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE 1025
213 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
215 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
216 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 1025
218 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE 50
219 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE 1025
222 #define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR 1025
223 #define PFC_E3B0_2P_BRB_FULL_LB_XON_THR 1025
225 /* Lossy +Lossless GUARANTIED == GUART */
226 #define PFC_E3B0_2P_MIX_PAUSE_LB_GUART 284
227 /* Lossless +Lossless*/
228 #define PFC_E3B0_2P_PAUSE_LB_GUART 236
230 #define PFC_E3B0_2P_NON_PAUSE_LB_GUART 342
233 #define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART 284
234 /* Lossless +Lossless*/
235 #define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART 236
237 #define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART 336
238 #define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST 80
240 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART 0
241 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST 0
243 /* BRB thresholds for E3B0 4 port mode */
244 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 304
245 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
247 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE 384
248 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
250 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
251 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 304
253 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE 50
254 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE 384
257 #define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR 304
258 #define PFC_E3B0_4P_BRB_FULL_LB_XON_THR 384
259 #define PFC_E3B0_4P_LB_GUART 120
261 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART 120
262 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST 80
264 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART 80
265 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST 120
268 #define DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR 330
269 #define DEFAULT_E3B0_BRB_FULL_LB_XON_THR 490
270 #define DEFAULT_E3B0_LB_GUART 40
272 #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART 40
273 #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST 0
275 #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART 40
276 #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST 0
279 #define DCBX_INVALID_COS (0xFF)
281 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
282 #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
283 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
284 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
285 #define ETS_E3B0_PBF_MIN_W_VAL (10000)
287 #define MAX_PACKET_SIZE (9700)
288 #define MAX_KR_LINK_RETRY 4
290 /**********************************************************/
292 /**********************************************************/
294 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
295 bnx2x_cl45_write(_bp, _phy, \
296 (_phy)->def_md_devad, \
297 (_bank + (_addr & 0xf)), \
300 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
301 bnx2x_cl45_read(_bp, _phy, \
302 (_phy)->def_md_devad, \
303 (_bank + (_addr & 0xf)), \
306 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
308 u32 val = REG_RD(bp, reg);
311 REG_WR(bp, reg, val);
315 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
317 u32 val = REG_RD(bp, reg);
320 REG_WR(bp, reg, val);
324 /******************************************************************/
325 /* EPIO/GPIO section */
326 /******************************************************************/
327 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
329 u32 epio_mask, gp_oenable;
333 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
337 epio_mask = 1 << epio_pin;
338 /* Set this EPIO to output */
339 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
340 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
342 *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
344 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
346 u32 epio_mask, gp_output, gp_oenable;
350 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
353 DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
354 epio_mask = 1 << epio_pin;
355 /* Set this EPIO to output */
356 gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
358 gp_output |= epio_mask;
360 gp_output &= ~epio_mask;
362 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
364 /* Set the value for this EPIO */
365 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
366 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
369 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
371 if (pin_cfg == PIN_CFG_NA)
373 if (pin_cfg >= PIN_CFG_EPIO0) {
374 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
376 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
377 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
378 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
382 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
384 if (pin_cfg == PIN_CFG_NA)
386 if (pin_cfg >= PIN_CFG_EPIO0) {
387 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
389 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
390 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
391 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
396 /******************************************************************/
398 /******************************************************************/
399 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
401 /* ETS disabled configuration*/
402 struct bnx2x *bp = params->bp;
404 DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
406 /* mapping between entry priority to client number (0,1,2 -debug and
407 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
409 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
410 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
413 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
414 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
415 * as strict. Bits 0,1,2 - debug and management entries, 3 -
416 * COS0 entry, 4 - COS1 entry.
417 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
418 * bit4 bit3 bit2 bit1 bit0
419 * MCP and debug are strict
422 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
423 /* defines which entries (clients) are subjected to WFQ arbitration */
424 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
425 /* For strict priority entries defines the number of consecutive
426 * slots for the highest priority.
428 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
429 /* mapping between the CREDIT_WEIGHT registers and actual client
432 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
433 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
434 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
436 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
437 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
438 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
439 /* ETS mode disable */
440 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
441 /* If ETS mode is enabled (there is no strict priority) defines a WFQ
442 * weight for COS0/COS1.
444 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
445 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
446 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
447 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
448 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
449 /* Defines the number of consecutive slots for the strict priority */
450 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
452 /******************************************************************************
454 * Getting min_w_val will be set according to line speed .
456 ******************************************************************************/
457 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
460 /* Calculate min_w_val.*/
462 if (vars->line_speed == SPEED_20000)
463 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
465 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
467 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
468 /* If the link isn't up (static configuration for example ) The
469 * link will be according to 20GBPS.
473 /******************************************************************************
475 * Getting credit upper bound form min_w_val.
477 ******************************************************************************/
478 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
480 const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
482 return credit_upper_bound;
484 /******************************************************************************
486 * Set credit upper bound for NIG.
488 ******************************************************************************/
489 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
490 const struct link_params *params,
493 struct bnx2x *bp = params->bp;
494 const u8 port = params->port;
495 const u32 credit_upper_bound =
496 bnx2x_ets_get_credit_upper_bound(min_w_val);
498 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
499 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
500 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
501 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
502 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
503 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
504 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
505 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
506 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
507 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
508 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
509 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
512 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
514 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
516 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
520 /******************************************************************************
522 * Will return the NIG ETS registers to init values.Except
523 * credit_upper_bound.
524 * That isn't used in this configuration (No WFQ is enabled) and will be
525 * configured acording to spec
527 ******************************************************************************/
528 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
529 const struct link_vars *vars)
531 struct bnx2x *bp = params->bp;
532 const u8 port = params->port;
533 const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
534 /* Mapping between entry priority to client number (0,1,2 -debug and
535 * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
536 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
537 * reset value or init tool
540 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
541 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
543 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
544 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
546 /* For strict priority entries defines the number of consecutive
547 * slots for the highest priority.
549 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
550 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
551 /* Mapping between the CREDIT_WEIGHT registers and actual client
556 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
557 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
560 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
562 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
565 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
566 * as strict. Bits 0,1,2 - debug and management entries, 3 -
567 * COS0 entry, 4 - COS1 entry.
568 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
569 * bit4 bit3 bit2 bit1 bit0
570 * MCP and debug are strict
573 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
575 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
576 /* defines which entries (clients) are subjected to WFQ arbitration */
577 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
578 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
580 /* Please notice the register address are note continuous and a
581 * for here is note appropriate.In 2 port mode port0 only COS0-5
582 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
583 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
584 * are never used for WFQ
586 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
587 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
588 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
589 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
590 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
591 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
592 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
593 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
594 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
595 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
596 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
597 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
599 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
600 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
601 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
604 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
606 /******************************************************************************
608 * Set credit upper bound for PBF.
610 ******************************************************************************/
611 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
612 const struct link_params *params,
615 struct bnx2x *bp = params->bp;
616 const u32 credit_upper_bound =
617 bnx2x_ets_get_credit_upper_bound(min_w_val);
618 const u8 port = params->port;
619 u32 base_upper_bound = 0;
622 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
623 * port mode port1 has COS0-2 that can be used for WFQ.
626 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
627 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
629 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
630 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
633 for (i = 0; i < max_cos; i++)
634 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
637 /******************************************************************************
639 * Will return the PBF ETS registers to init values.Except
640 * credit_upper_bound.
641 * That isn't used in this configuration (No WFQ is enabled) and will be
642 * configured acording to spec
644 ******************************************************************************/
645 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
647 struct bnx2x *bp = params->bp;
648 const u8 port = params->port;
649 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
654 /* Mapping between entry priority to client number 0 - COS0
655 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
656 * TODO_ETS - Should be done by reset value or init tool
659 /* 0x688 (|011|0 10|00 1|000) */
660 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
662 /* (10 1|100 |011|0 10|00 1|000) */
663 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
665 /* TODO_ETS - Should be done by reset value or init tool */
667 /* 0x688 (|011|0 10|00 1|000)*/
668 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
670 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
671 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
673 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
674 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
677 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
678 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
680 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
681 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
682 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
683 * In 4 port mode port1 has COS0-2 that can be used for WFQ.
686 base_weight = PBF_REG_COS0_WEIGHT_P0;
687 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
689 base_weight = PBF_REG_COS0_WEIGHT_P1;
690 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
693 for (i = 0; i < max_cos; i++)
694 REG_WR(bp, base_weight + (0x4 * i), 0);
696 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
698 /******************************************************************************
700 * E3B0 disable will return basicly the values to init values.
702 ******************************************************************************/
703 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
704 const struct link_vars *vars)
706 struct bnx2x *bp = params->bp;
708 if (!CHIP_IS_E3B0(bp)) {
710 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
714 bnx2x_ets_e3b0_nig_disabled(params, vars);
716 bnx2x_ets_e3b0_pbf_disabled(params);
721 /******************************************************************************
723 * Disable will return basicly the values to init values.
725 ******************************************************************************/
726 int bnx2x_ets_disabled(struct link_params *params,
727 struct link_vars *vars)
729 struct bnx2x *bp = params->bp;
730 int bnx2x_status = 0;
732 if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
733 bnx2x_ets_e2e3a0_disabled(params);
734 else if (CHIP_IS_E3B0(bp))
735 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
737 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
744 /******************************************************************************
746 * Set the COS mappimg to SP and BW until this point all the COS are not
748 ******************************************************************************/
749 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
750 const struct bnx2x_ets_params *ets_params,
751 const u8 cos_sp_bitmap,
752 const u8 cos_bw_bitmap)
754 struct bnx2x *bp = params->bp;
755 const u8 port = params->port;
756 const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
757 const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
758 const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
759 const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
761 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
762 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
764 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
765 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
767 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
768 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
769 nig_cli_subject2wfq_bitmap);
771 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
772 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
773 pbf_cli_subject2wfq_bitmap);
778 /******************************************************************************
780 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
781 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
782 ******************************************************************************/
783 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
785 const u32 min_w_val_nig,
786 const u32 min_w_val_pbf,
791 u32 nig_reg_adress_crd_weight = 0;
792 u32 pbf_reg_adress_crd_weight = 0;
793 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
794 const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
795 const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
799 nig_reg_adress_crd_weight =
800 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
801 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
802 pbf_reg_adress_crd_weight = (port) ?
803 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
806 nig_reg_adress_crd_weight = (port) ?
807 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
808 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
809 pbf_reg_adress_crd_weight = (port) ?
810 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
813 nig_reg_adress_crd_weight = (port) ?
814 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
815 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
817 pbf_reg_adress_crd_weight = (port) ?
818 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
823 nig_reg_adress_crd_weight =
824 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
825 pbf_reg_adress_crd_weight =
826 PBF_REG_COS3_WEIGHT_P0;
831 nig_reg_adress_crd_weight =
832 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
833 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
838 nig_reg_adress_crd_weight =
839 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
840 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
844 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
846 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
850 /******************************************************************************
852 * Calculate the total BW.A value of 0 isn't legal.
854 ******************************************************************************/
855 static int bnx2x_ets_e3b0_get_total_bw(
856 const struct link_params *params,
857 struct bnx2x_ets_params *ets_params,
860 struct bnx2x *bp = params->bp;
862 u8 is_bw_cos_exist = 0;
865 /* Calculate total BW requested */
866 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
867 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) {
869 if (!ets_params->cos[cos_idx].params.bw_params.bw) {
870 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
872 /* This is to prevent a state when ramrods
875 ets_params->cos[cos_idx].params.bw_params.bw
879 ets_params->cos[cos_idx].params.bw_params.bw;
883 /* Check total BW is valid */
884 if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
885 if (*total_bw == 0) {
887 "bnx2x_ets_E3B0_config total BW shouldn't be 0\n");
891 "bnx2x_ets_E3B0_config total BW should be 100\n");
892 /* We can handle a case whre the BW isn't 100 this can happen
893 * if the TC are joined.
899 /******************************************************************************
901 * Invalidate all the sp_pri_to_cos.
903 ******************************************************************************/
904 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
907 for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
908 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
910 /******************************************************************************
912 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
913 * according to sp_pri_to_cos.
915 ******************************************************************************/
916 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
917 u8 *sp_pri_to_cos, const u8 pri,
920 struct bnx2x *bp = params->bp;
921 const u8 port = params->port;
922 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
923 DCBX_E3B0_MAX_NUM_COS_PORT0;
925 if (pri >= max_num_of_cos) {
926 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
927 "parameter Illegal strict priority\n");
931 if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
932 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
933 "parameter There can't be two COS's with "
934 "the same strict pri\n");
938 sp_pri_to_cos[pri] = cos_entry;
943 /******************************************************************************
945 * Returns the correct value according to COS and priority in
946 * the sp_pri_cli register.
948 ******************************************************************************/
949 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
955 pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
956 (pri_set + pri_offset));
960 /******************************************************************************
962 * Returns the correct value according to COS and priority in the
963 * sp_pri_cli register for NIG.
965 ******************************************************************************/
966 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
968 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
969 const u8 nig_cos_offset = 3;
970 const u8 nig_pri_offset = 3;
972 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
976 /******************************************************************************
978 * Returns the correct value according to COS and priority in the
979 * sp_pri_cli register for PBF.
981 ******************************************************************************/
982 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
984 const u8 pbf_cos_offset = 0;
985 const u8 pbf_pri_offset = 0;
987 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
992 /******************************************************************************
994 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
995 * according to sp_pri_to_cos.(which COS has higher priority)
997 ******************************************************************************/
998 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
1001 struct bnx2x *bp = params->bp;
1003 const u8 port = params->port;
1004 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1005 u64 pri_cli_nig = 0x210;
1006 u32 pri_cli_pbf = 0x0;
1009 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1010 DCBX_E3B0_MAX_NUM_COS_PORT0;
1012 u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
1014 /* Set all the strict priority first */
1015 for (i = 0; i < max_num_of_cos; i++) {
1016 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1017 if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) {
1019 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1020 "invalid cos entry\n");
1024 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1025 sp_pri_to_cos[i], pri_set);
1027 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1028 sp_pri_to_cos[i], pri_set);
1029 pri_bitmask = 1 << sp_pri_to_cos[i];
1030 /* COS is used remove it from bitmap.*/
1031 if (!(pri_bitmask & cos_bit_to_set)) {
1033 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1034 "invalid There can't be two COS's with"
1035 " the same strict pri\n");
1038 cos_bit_to_set &= ~pri_bitmask;
1043 /* Set all the Non strict priority i= COS*/
1044 for (i = 0; i < max_num_of_cos; i++) {
1045 pri_bitmask = 1 << i;
1046 /* Check if COS was already used for SP */
1047 if (pri_bitmask & cos_bit_to_set) {
1048 /* COS wasn't used for SP */
1049 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1052 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1054 /* COS is used remove it from bitmap.*/
1055 cos_bit_to_set &= ~pri_bitmask;
1060 if (pri_set != max_num_of_cos) {
1061 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1062 "entries were set\n");
1067 /* Only 6 usable clients*/
1068 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1071 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1073 /* Only 9 usable clients*/
1074 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1075 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1077 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1079 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1082 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1087 /******************************************************************************
1089 * Configure the COS to ETS according to BW and SP settings.
1090 ******************************************************************************/
1091 int bnx2x_ets_e3b0_config(const struct link_params *params,
1092 const struct link_vars *vars,
1093 struct bnx2x_ets_params *ets_params)
1095 struct bnx2x *bp = params->bp;
1096 int bnx2x_status = 0;
1097 const u8 port = params->port;
1099 const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1100 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1101 u8 cos_bw_bitmap = 0;
1102 u8 cos_sp_bitmap = 0;
1103 u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1104 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1105 DCBX_E3B0_MAX_NUM_COS_PORT0;
1108 if (!CHIP_IS_E3B0(bp)) {
1110 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
1114 if ((ets_params->num_of_cos > max_num_of_cos)) {
1115 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1116 "isn't supported\n");
1120 /* Prepare sp strict priority parameters*/
1121 bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1123 /* Prepare BW parameters*/
1124 bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1128 "bnx2x_ets_E3B0_config get_total_bw failed\n");
1132 /* Upper bound is set according to current link speed (min_w_val
1133 * should be the same for upper bound and COS credit val).
1135 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1136 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1139 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1140 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1141 cos_bw_bitmap |= (1 << cos_entry);
1142 /* The function also sets the BW in HW(not the mappin
1145 bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1146 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1148 ets_params->cos[cos_entry].params.bw_params.bw,
1150 } else if (bnx2x_cos_state_strict ==
1151 ets_params->cos[cos_entry].state){
1152 cos_sp_bitmap |= (1 << cos_entry);
1154 bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1157 ets_params->cos[cos_entry].params.sp_params.pri,
1162 "bnx2x_ets_e3b0_config cos state not valid\n");
1167 "bnx2x_ets_e3b0_config set cos bw failed\n");
1168 return bnx2x_status;
1172 /* Set SP register (which COS has higher priority) */
1173 bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1178 "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
1179 return bnx2x_status;
1182 /* Set client mapping of BW and strict */
1183 bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1188 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1189 return bnx2x_status;
1193 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1195 /* ETS disabled configuration */
1196 struct bnx2x *bp = params->bp;
1197 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1198 /* Defines which entries (clients) are subjected to WFQ arbitration
1202 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1203 /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
1204 * client numbers (WEIGHT_0 does not actually have to represent
1206 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1207 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
1209 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1211 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1212 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1213 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1214 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1216 /* ETS mode enabled*/
1217 REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1219 /* Defines the number of consecutive slots for the strict priority */
1220 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1221 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1222 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
1223 * entry, 4 - COS1 entry.
1224 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1225 * bit4 bit3 bit2 bit1 bit0
1226 * MCP and debug are strict
1228 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1230 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1231 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1232 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1233 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1234 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1237 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1240 /* ETS disabled configuration*/
1241 struct bnx2x *bp = params->bp;
1242 const u32 total_bw = cos0_bw + cos1_bw;
1243 u32 cos0_credit_weight = 0;
1244 u32 cos1_credit_weight = 0;
1246 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1251 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1255 cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1257 cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1260 bnx2x_ets_bw_limit_common(params);
1262 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1263 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1265 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1266 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1269 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1271 /* ETS disabled configuration*/
1272 struct bnx2x *bp = params->bp;
1275 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1276 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1277 * as strict. Bits 0,1,2 - debug and management entries,
1278 * 3 - COS0 entry, 4 - COS1 entry.
1279 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1280 * bit4 bit3 bit2 bit1 bit0
1281 * MCP and debug are strict
1283 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1284 /* For strict priority entries defines the number of consecutive slots
1285 * for the highest priority.
1287 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1288 /* ETS mode disable */
1289 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1290 /* Defines the number of consecutive slots for the strict priority */
1291 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1293 /* Defines the number of consecutive slots for the strict priority */
1294 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1296 /* Mapping between entry priority to client number (0,1,2 -debug and
1297 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1299 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1300 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
1301 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
1303 val = (!strict_cos) ? 0x2318 : 0x22E0;
1304 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1309 /******************************************************************/
1311 /******************************************************************/
1312 static void bnx2x_update_pfc_xmac(struct link_params *params,
1313 struct link_vars *vars,
1316 struct bnx2x *bp = params->bp;
1318 u32 pause_val, pfc0_val, pfc1_val;
1320 /* XMAC base adrr */
1321 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1323 /* Initialize pause and pfc registers */
1324 pause_val = 0x18000;
1325 pfc0_val = 0xFFFF8000;
1328 /* No PFC support */
1329 if (!(params->feature_config_flags &
1330 FEATURE_CONFIG_PFC_ENABLED)) {
1332 /* RX flow control - Process pause frame in receive direction
1334 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1335 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1337 /* TX flow control - Send pause packet when buffer is full */
1338 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1339 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1340 } else {/* PFC support */
1341 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1342 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1343 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1344 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1345 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1346 /* Write pause and PFC registers */
1347 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1348 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1349 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1350 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1354 /* Write pause and PFC registers */
1355 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1356 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1357 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1360 /* Set MAC address for source TX Pause/PFC frames */
1361 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1362 ((params->mac_addr[2] << 24) |
1363 (params->mac_addr[3] << 16) |
1364 (params->mac_addr[4] << 8) |
1365 (params->mac_addr[5])));
1366 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1367 ((params->mac_addr[0] << 8) |
1368 (params->mac_addr[1])));
1374 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
1375 u32 pfc_frames_sent[2],
1376 u32 pfc_frames_received[2])
1378 /* Read pfc statistic */
1379 struct bnx2x *bp = params->bp;
1380 u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1384 DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
1386 /* PFC received frames */
1387 val_xoff = REG_RD(bp, emac_base +
1388 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1389 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
1390 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1391 val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
1393 pfc_frames_received[0] = val_xon + val_xoff;
1395 /* PFC received sent */
1396 val_xoff = REG_RD(bp, emac_base +
1397 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1398 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
1399 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1400 val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
1402 pfc_frames_sent[0] = val_xon + val_xoff;
1405 /* Read pfc statistic*/
1406 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1407 u32 pfc_frames_sent[2],
1408 u32 pfc_frames_received[2])
1410 /* Read pfc statistic */
1411 struct bnx2x *bp = params->bp;
1413 DP(NETIF_MSG_LINK, "pfc statistic\n");
1418 if (vars->mac_type == MAC_TYPE_EMAC) {
1419 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n");
1420 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
1421 pfc_frames_received);
1424 /******************************************************************/
1425 /* MAC/PBF section */
1426 /******************************************************************/
1427 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port)
1429 u32 mode, emac_base;
1430 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1431 * (a value of 49==0x31) and make sure that the AUTO poll is off
1435 emac_base = GRCBASE_EMAC0;
1437 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1438 mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1439 mode &= ~(EMAC_MDIO_MODE_AUTO_POLL |
1440 EMAC_MDIO_MODE_CLOCK_CNT);
1441 if (USES_WARPCORE(bp))
1442 mode |= (74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1444 mode |= (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1446 mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1447 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, mode);
1451 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1453 u32 port4mode_ovwr_val;
1454 /* Check 4-port override enabled */
1455 port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1456 if (port4mode_ovwr_val & (1<<0)) {
1457 /* Return 4-port mode override value */
1458 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1460 /* Return 4-port mode from input pin */
1461 return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1464 static void bnx2x_emac_init(struct link_params *params,
1465 struct link_vars *vars)
1467 /* reset and unreset the emac core */
1468 struct bnx2x *bp = params->bp;
1469 u8 port = params->port;
1470 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1474 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1475 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1477 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1478 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1480 /* init emac - use read-modify-write */
1481 /* self clear reset */
1482 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1483 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1487 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1488 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1490 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1494 } while (val & EMAC_MODE_RESET);
1495 bnx2x_set_mdio_clk(bp, params->chip_id, port);
1496 /* Set mac address */
1497 val = ((params->mac_addr[0] << 8) |
1498 params->mac_addr[1]);
1499 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1501 val = ((params->mac_addr[2] << 24) |
1502 (params->mac_addr[3] << 16) |
1503 (params->mac_addr[4] << 8) |
1504 params->mac_addr[5]);
1505 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1508 static void bnx2x_set_xumac_nig(struct link_params *params,
1512 struct bnx2x *bp = params->bp;
1514 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1516 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1518 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1519 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1522 static void bnx2x_umac_disable(struct link_params *params)
1524 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1525 struct bnx2x *bp = params->bp;
1526 if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &
1527 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1530 /* Disable RX and TX */
1531 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, 0);
1534 static void bnx2x_umac_enable(struct link_params *params,
1535 struct link_vars *vars, u8 lb)
1538 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1539 struct bnx2x *bp = params->bp;
1541 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1542 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1543 usleep_range(1000, 2000);
1545 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1546 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1548 DP(NETIF_MSG_LINK, "enabling UMAC\n");
1550 /* This register opens the gate for the UMAC despite its name */
1551 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1553 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1554 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1555 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1556 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1557 switch (vars->line_speed) {
1571 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1575 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1576 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1578 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1579 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1581 if (vars->duplex == DUPLEX_HALF)
1582 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
1584 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1587 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1588 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1589 ((params->mac_addr[2] << 24) |
1590 (params->mac_addr[3] << 16) |
1591 (params->mac_addr[4] << 8) |
1592 (params->mac_addr[5])));
1593 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1594 ((params->mac_addr[0] << 8) |
1595 (params->mac_addr[1])));
1597 /* Enable RX and TX */
1598 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1599 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1600 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1601 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1604 /* Remove SW Reset */
1605 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1607 /* Check loopback mode */
1609 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1610 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1612 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1613 * length used by the MAC receive logic to check frames.
1615 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1616 bnx2x_set_xumac_nig(params,
1617 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1618 vars->mac_type = MAC_TYPE_UMAC;
1622 /* Define the XMAC mode */
1623 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1625 struct bnx2x *bp = params->bp;
1626 u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1628 /* In 4-port mode, need to set the mode only once, so if XMAC is
1629 * already out of reset, it means the mode has already been set,
1630 * and it must not* reset the XMAC again, since it controls both
1634 if ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) &&
1635 (REG_RD(bp, MISC_REG_RESET_REG_2) &
1636 MISC_REGISTERS_RESET_REG_2_XMAC)) {
1638 "XMAC already out of reset in 4-port mode\n");
1643 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1644 MISC_REGISTERS_RESET_REG_2_XMAC);
1645 usleep_range(1000, 2000);
1647 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1648 MISC_REGISTERS_RESET_REG_2_XMAC);
1650 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1652 /* Set the number of ports on the system side to up to 2 */
1653 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1655 /* Set the number of ports on the Warp Core to 10G */
1656 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1658 /* Set the number of ports on the system side to 1 */
1659 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1660 if (max_speed == SPEED_10000) {
1662 "Init XMAC to 10G x 1 port per path\n");
1663 /* Set the number of ports on the Warp Core to 10G */
1664 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1667 "Init XMAC to 20G x 2 ports per path\n");
1668 /* Set the number of ports on the Warp Core to 20G */
1669 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1673 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1674 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1675 usleep_range(1000, 2000);
1677 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1678 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1682 static void bnx2x_xmac_disable(struct link_params *params)
1684 u8 port = params->port;
1685 struct bnx2x *bp = params->bp;
1686 u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1688 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1689 MISC_REGISTERS_RESET_REG_2_XMAC) {
1690 /* Send an indication to change the state in the NIG back to XON
1691 * Clearing this bit enables the next set of this bit to get
1694 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1695 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1696 (pfc_ctrl & ~(1<<1)));
1697 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1698 (pfc_ctrl | (1<<1)));
1699 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1700 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 0);
1704 static int bnx2x_xmac_enable(struct link_params *params,
1705 struct link_vars *vars, u8 lb)
1708 struct bnx2x *bp = params->bp;
1709 DP(NETIF_MSG_LINK, "enabling XMAC\n");
1711 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1713 bnx2x_xmac_init(params, vars->line_speed);
1715 /* This register determines on which events the MAC will assert
1716 * error on the i/f to the NIG along w/ EOP.
1719 /* This register tells the NIG whether to send traffic to UMAC
1722 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1724 /* Set Max packet size */
1725 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1727 /* CRC append for Tx packets */
1728 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1731 bnx2x_update_pfc_xmac(params, vars, 0);
1733 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1734 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n");
1735 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
1736 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
1738 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
1741 /* Enable TX and RX */
1742 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1744 /* Check loopback mode */
1746 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1747 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1748 bnx2x_set_xumac_nig(params,
1749 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1751 vars->mac_type = MAC_TYPE_XMAC;
1756 static int bnx2x_emac_enable(struct link_params *params,
1757 struct link_vars *vars, u8 lb)
1759 struct bnx2x *bp = params->bp;
1760 u8 port = params->port;
1761 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1764 DP(NETIF_MSG_LINK, "enabling EMAC\n");
1767 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1768 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1770 /* enable emac and not bmac */
1771 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1774 if (vars->phy_flags & PHY_XGXS_FLAG) {
1775 u32 ser_lane = ((params->lane_config &
1776 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1777 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1779 DP(NETIF_MSG_LINK, "XGXS\n");
1780 /* select the master lanes (out of 0-3) */
1781 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1783 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1785 } else { /* SerDes */
1786 DP(NETIF_MSG_LINK, "SerDes\n");
1788 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1791 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1792 EMAC_RX_MODE_RESET);
1793 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1794 EMAC_TX_MODE_RESET);
1796 /* pause enable/disable */
1797 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1798 EMAC_RX_MODE_FLOW_EN);
1800 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1801 (EMAC_TX_MODE_EXT_PAUSE_EN |
1802 EMAC_TX_MODE_FLOW_EN));
1803 if (!(params->feature_config_flags &
1804 FEATURE_CONFIG_PFC_ENABLED)) {
1805 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1806 bnx2x_bits_en(bp, emac_base +
1807 EMAC_REG_EMAC_RX_MODE,
1808 EMAC_RX_MODE_FLOW_EN);
1810 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1811 bnx2x_bits_en(bp, emac_base +
1812 EMAC_REG_EMAC_TX_MODE,
1813 (EMAC_TX_MODE_EXT_PAUSE_EN |
1814 EMAC_TX_MODE_FLOW_EN));
1816 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1817 EMAC_TX_MODE_FLOW_EN);
1819 /* KEEP_VLAN_TAG, promiscuous */
1820 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1821 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1823 /* Setting this bit causes MAC control frames (except for pause
1824 * frames) to be passed on for processing. This setting has no
1825 * affect on the operation of the pause frames. This bit effects
1826 * all packets regardless of RX Parser packet sorting logic.
1827 * Turn the PFC off to make sure we are in Xon state before
1830 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1831 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1832 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1833 /* Enable PFC again */
1834 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1835 EMAC_REG_RX_PFC_MODE_RX_EN |
1836 EMAC_REG_RX_PFC_MODE_TX_EN |
1837 EMAC_REG_RX_PFC_MODE_PRIORITIES);
1839 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1841 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1843 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1844 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1846 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1849 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1854 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1857 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1859 /* Enable emac for jumbo packets */
1860 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1861 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1862 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1865 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1867 /* Disable the NIG in/out to the bmac */
1868 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1869 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1870 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1872 /* Enable the NIG in/out to the emac */
1873 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1875 if ((params->feature_config_flags &
1876 FEATURE_CONFIG_PFC_ENABLED) ||
1877 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1880 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1881 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1883 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1885 vars->mac_type = MAC_TYPE_EMAC;
1889 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1890 struct link_vars *vars)
1893 struct bnx2x *bp = params->bp;
1894 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1895 NIG_REG_INGRESS_BMAC0_MEM;
1898 if ((!(params->feature_config_flags &
1899 FEATURE_CONFIG_PFC_ENABLED)) &&
1900 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1901 /* Enable BigMAC to react on received Pause packets */
1905 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1909 if (!(params->feature_config_flags &
1910 FEATURE_CONFIG_PFC_ENABLED) &&
1911 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1915 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1918 static void bnx2x_update_pfc_bmac2(struct link_params *params,
1919 struct link_vars *vars,
1922 /* Set rx control: Strip CRC and enable BigMAC to relay
1923 * control packets to the system as well
1926 struct bnx2x *bp = params->bp;
1927 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1928 NIG_REG_INGRESS_BMAC0_MEM;
1931 if ((!(params->feature_config_flags &
1932 FEATURE_CONFIG_PFC_ENABLED)) &&
1933 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1934 /* Enable BigMAC to react on received Pause packets */
1938 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1943 if (!(params->feature_config_flags &
1944 FEATURE_CONFIG_PFC_ENABLED) &&
1945 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1949 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
1951 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1952 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1953 /* Enable PFC RX & TX & STATS and set 8 COS */
1955 wb_data[0] |= (1<<0); /* RX */
1956 wb_data[0] |= (1<<1); /* TX */
1957 wb_data[0] |= (1<<2); /* Force initial Xon */
1958 wb_data[0] |= (1<<3); /* 8 cos */
1959 wb_data[0] |= (1<<5); /* STATS */
1961 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
1963 /* Clear the force Xon */
1964 wb_data[0] &= ~(1<<2);
1966 DP(NETIF_MSG_LINK, "PFC is disabled\n");
1967 /* Disable PFC RX & TX & STATS and set 8 COS */
1972 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
1974 /* Set Time (based unit is 512 bit time) between automatic
1975 * re-sending of PP packets amd enable automatic re-send of
1976 * Per-Priroity Packet as long as pp_gen is asserted and
1977 * pp_disable is low.
1980 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
1981 val |= (1<<16); /* enable automatic re-send */
1985 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
1989 val = 0x3; /* Enable RX and TX */
1991 val |= 0x4; /* Local loopback */
1992 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
1994 /* When PFC enabled, Pass pause frames towards the NIG. */
1995 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
1996 val |= ((1<<6)|(1<<5));
2000 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2003 /* PFC BRB internal port configuration params */
2004 struct bnx2x_pfc_brb_threshold_val {
2011 struct bnx2x_pfc_brb_e3b0_val {
2012 u32 per_class_guaranty_mode;
2013 u32 lb_guarantied_hyst;
2014 u32 full_lb_xoff_th;
2015 u32 full_lb_xon_threshold;
2017 u32 mac_0_class_t_guarantied;
2018 u32 mac_0_class_t_guarantied_hyst;
2019 u32 mac_1_class_t_guarantied;
2020 u32 mac_1_class_t_guarantied_hyst;
2023 struct bnx2x_pfc_brb_th_val {
2024 struct bnx2x_pfc_brb_threshold_val pauseable_th;
2025 struct bnx2x_pfc_brb_threshold_val non_pauseable_th;
2026 struct bnx2x_pfc_brb_threshold_val default_class0;
2027 struct bnx2x_pfc_brb_threshold_val default_class1;
2030 static int bnx2x_pfc_brb_get_config_params(
2031 struct link_params *params,
2032 struct bnx2x_pfc_brb_th_val *config_val)
2034 struct bnx2x *bp = params->bp;
2035 DP(NETIF_MSG_LINK, "Setting PFC BRB configuration\n");
2037 config_val->default_class1.pause_xoff = 0;
2038 config_val->default_class1.pause_xon = 0;
2039 config_val->default_class1.full_xoff = 0;
2040 config_val->default_class1.full_xon = 0;
2042 if (CHIP_IS_E2(bp)) {
2043 /* Class0 defaults */
2044 config_val->default_class0.pause_xoff =
2045 DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR;
2046 config_val->default_class0.pause_xon =
2047 DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR;
2048 config_val->default_class0.full_xoff =
2049 DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR;
2050 config_val->default_class0.full_xon =
2051 DEFAULT0_E2_BRB_MAC_FULL_XON_THR;
2053 config_val->pauseable_th.pause_xoff =
2054 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2055 config_val->pauseable_th.pause_xon =
2056 PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE;
2057 config_val->pauseable_th.full_xoff =
2058 PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
2059 config_val->pauseable_th.full_xon =
2060 PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
2062 config_val->non_pauseable_th.pause_xoff =
2063 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2064 config_val->non_pauseable_th.pause_xon =
2065 PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2066 config_val->non_pauseable_th.full_xoff =
2067 PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2068 config_val->non_pauseable_th.full_xon =
2069 PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2070 } else if (CHIP_IS_E3A0(bp)) {
2071 /* Class0 defaults */
2072 config_val->default_class0.pause_xoff =
2073 DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR;
2074 config_val->default_class0.pause_xon =
2075 DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR;
2076 config_val->default_class0.full_xoff =
2077 DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR;
2078 config_val->default_class0.full_xon =
2079 DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR;
2081 config_val->pauseable_th.pause_xoff =
2082 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2083 config_val->pauseable_th.pause_xon =
2084 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE;
2085 config_val->pauseable_th.full_xoff =
2086 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
2087 config_val->pauseable_th.full_xon =
2088 PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
2090 config_val->non_pauseable_th.pause_xoff =
2091 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2092 config_val->non_pauseable_th.pause_xon =
2093 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2094 config_val->non_pauseable_th.full_xoff =
2095 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2096 config_val->non_pauseable_th.full_xon =
2097 PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2098 } else if (CHIP_IS_E3B0(bp)) {
2099 /* Class0 defaults */
2100 config_val->default_class0.pause_xoff =
2101 DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR;
2102 config_val->default_class0.pause_xon =
2103 DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR;
2104 config_val->default_class0.full_xoff =
2105 DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR;
2106 config_val->default_class0.full_xon =
2107 DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR;
2109 if (params->phy[INT_PHY].flags &
2110 FLAGS_4_PORT_MODE) {
2111 config_val->pauseable_th.pause_xoff =
2112 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2113 config_val->pauseable_th.pause_xon =
2114 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2115 config_val->pauseable_th.full_xoff =
2116 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2117 config_val->pauseable_th.full_xon =
2118 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
2120 config_val->non_pauseable_th.pause_xoff =
2121 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2122 config_val->non_pauseable_th.pause_xon =
2123 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2124 config_val->non_pauseable_th.full_xoff =
2125 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2126 config_val->non_pauseable_th.full_xon =
2127 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2129 config_val->pauseable_th.pause_xoff =
2130 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2131 config_val->pauseable_th.pause_xon =
2132 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2133 config_val->pauseable_th.full_xoff =
2134 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2135 config_val->pauseable_th.full_xon =
2136 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
2138 config_val->non_pauseable_th.pause_xoff =
2139 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2140 config_val->non_pauseable_th.pause_xon =
2141 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2142 config_val->non_pauseable_th.full_xoff =
2143 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2144 config_val->non_pauseable_th.full_xon =
2145 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2153 static void bnx2x_pfc_brb_get_e3b0_config_params(
2154 struct link_params *params,
2155 struct bnx2x_pfc_brb_e3b0_val
2157 struct bnx2x_nig_brb_pfc_port_params *pfc_params,
2158 const u8 pfc_enabled)
2160 if (pfc_enabled && pfc_params) {
2161 e3b0_val->per_class_guaranty_mode = 1;
2162 e3b0_val->lb_guarantied_hyst = 80;
2164 if (params->phy[INT_PHY].flags &
2165 FLAGS_4_PORT_MODE) {
2166 e3b0_val->full_lb_xoff_th =
2167 PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR;
2168 e3b0_val->full_lb_xon_threshold =
2169 PFC_E3B0_4P_BRB_FULL_LB_XON_THR;
2170 e3b0_val->lb_guarantied =
2171 PFC_E3B0_4P_LB_GUART;
2172 e3b0_val->mac_0_class_t_guarantied =
2173 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART;
2174 e3b0_val->mac_0_class_t_guarantied_hyst =
2175 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST;
2176 e3b0_val->mac_1_class_t_guarantied =
2177 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART;
2178 e3b0_val->mac_1_class_t_guarantied_hyst =
2179 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST;
2181 e3b0_val->full_lb_xoff_th =
2182 PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR;
2183 e3b0_val->full_lb_xon_threshold =
2184 PFC_E3B0_2P_BRB_FULL_LB_XON_THR;
2185 e3b0_val->mac_0_class_t_guarantied_hyst =
2186 PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST;
2187 e3b0_val->mac_1_class_t_guarantied =
2188 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART;
2189 e3b0_val->mac_1_class_t_guarantied_hyst =
2190 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST;
2192 if (pfc_params->cos0_pauseable !=
2193 pfc_params->cos1_pauseable) {
2194 /* Nonpauseable= Lossy + pauseable = Lossless*/
2195 e3b0_val->lb_guarantied =
2196 PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
2197 e3b0_val->mac_0_class_t_guarantied =
2198 PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART;
2199 } else if (pfc_params->cos0_pauseable) {
2200 /* Lossless +Lossless*/
2201 e3b0_val->lb_guarantied =
2202 PFC_E3B0_2P_PAUSE_LB_GUART;
2203 e3b0_val->mac_0_class_t_guarantied =
2204 PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART;
2207 e3b0_val->lb_guarantied =
2208 PFC_E3B0_2P_NON_PAUSE_LB_GUART;
2209 e3b0_val->mac_0_class_t_guarantied =
2210 PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART;
2214 e3b0_val->per_class_guaranty_mode = 0;
2215 e3b0_val->lb_guarantied_hyst = 0;
2216 e3b0_val->full_lb_xoff_th =
2217 DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR;
2218 e3b0_val->full_lb_xon_threshold =
2219 DEFAULT_E3B0_BRB_FULL_LB_XON_THR;
2220 e3b0_val->lb_guarantied =
2221 DEFAULT_E3B0_LB_GUART;
2222 e3b0_val->mac_0_class_t_guarantied =
2223 DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART;
2224 e3b0_val->mac_0_class_t_guarantied_hyst =
2225 DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST;
2226 e3b0_val->mac_1_class_t_guarantied =
2227 DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART;
2228 e3b0_val->mac_1_class_t_guarantied_hyst =
2229 DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST;
2232 static int bnx2x_update_pfc_brb(struct link_params *params,
2233 struct link_vars *vars,
2234 struct bnx2x_nig_brb_pfc_port_params
2237 struct bnx2x *bp = params->bp;
2238 struct bnx2x_pfc_brb_th_val config_val = { {0} };
2239 struct bnx2x_pfc_brb_threshold_val *reg_th_config =
2240 &config_val.pauseable_th;
2241 struct bnx2x_pfc_brb_e3b0_val e3b0_val = {0};
2242 const int set_pfc = params->feature_config_flags &
2243 FEATURE_CONFIG_PFC_ENABLED;
2244 const u8 pfc_enabled = (set_pfc && pfc_params);
2245 int bnx2x_status = 0;
2246 u8 port = params->port;
2248 /* default - pause configuration */
2249 reg_th_config = &config_val.pauseable_th;
2250 bnx2x_status = bnx2x_pfc_brb_get_config_params(params, &config_val);
2252 return bnx2x_status;
2256 if (pfc_params->cos0_pauseable)
2257 reg_th_config = &config_val.pauseable_th;
2259 reg_th_config = &config_val.non_pauseable_th;
2261 reg_th_config = &config_val.default_class0;
2262 /* The number of free blocks below which the pause signal to class 0
2263 * of MAC #n is asserted. n=0,1
2265 REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 :
2266 BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
2267 reg_th_config->pause_xoff);
2268 /* The number of free blocks above which the pause signal to class 0
2269 * of MAC #n is de-asserted. n=0,1
2271 REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 :
2272 BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon);
2273 /* The number of free blocks below which the full signal to class 0
2274 * of MAC #n is asserted. n=0,1
2276 REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 :
2277 BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff);
2278 /* The number of free blocks above which the full signal to class 0
2279 * of MAC #n is de-asserted. n=0,1
2281 REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 :
2282 BRB1_REG_FULL_0_XON_THRESHOLD_0 , reg_th_config->full_xon);
2286 if (pfc_params->cos1_pauseable)
2287 reg_th_config = &config_val.pauseable_th;
2289 reg_th_config = &config_val.non_pauseable_th;
2291 reg_th_config = &config_val.default_class1;
2292 /* The number of free blocks below which the pause signal to
2293 * class 1 of MAC #n is asserted. n=0,1
2295 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 :
2296 BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
2297 reg_th_config->pause_xoff);
2299 /* The number of free blocks above which the pause signal to
2300 * class 1 of MAC #n is de-asserted. n=0,1
2302 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 :
2303 BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
2304 reg_th_config->pause_xon);
2305 /* The number of free blocks below which the full signal to
2306 * class 1 of MAC #n is asserted. n=0,1
2308 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 :
2309 BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
2310 reg_th_config->full_xoff);
2311 /* The number of free blocks above which the full signal to
2312 * class 1 of MAC #n is de-asserted. n=0,1
2314 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 :
2315 BRB1_REG_FULL_1_XON_THRESHOLD_0,
2316 reg_th_config->full_xon);
2318 if (CHIP_IS_E3B0(bp)) {
2319 bnx2x_pfc_brb_get_e3b0_config_params(
2325 REG_WR(bp, BRB1_REG_PER_CLASS_GUARANTY_MODE,
2326 e3b0_val.per_class_guaranty_mode);
2328 /* The hysteresis on the guarantied buffer space for the Lb
2329 * port before signaling XON.
2331 REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST,
2332 e3b0_val.lb_guarantied_hyst);
2334 /* The number of free blocks below which the full signal to the
2335 * LB port is asserted.
2337 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD,
2338 e3b0_val.full_lb_xoff_th);
2339 /* The number of free blocks above which the full signal to the
2340 * LB port is de-asserted.
2342 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD,
2343 e3b0_val.full_lb_xon_threshold);
2344 /* The number of blocks guarantied for the MAC #n port. n=0,1
2347 /* The number of blocks guarantied for the LB port. */
2348 REG_WR(bp, BRB1_REG_LB_GUARANTIED,
2349 e3b0_val.lb_guarantied);
2351 /* The number of blocks guarantied for the MAC #n port. */
2352 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0,
2353 2 * e3b0_val.mac_0_class_t_guarantied);
2354 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1,
2355 2 * e3b0_val.mac_1_class_t_guarantied);
2356 /* The number of blocks guarantied for class #t in MAC0. t=0,1
2358 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED,
2359 e3b0_val.mac_0_class_t_guarantied);
2360 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED,
2361 e3b0_val.mac_0_class_t_guarantied);
2362 /* The hysteresis on the guarantied buffer space for class in
2365 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST,
2366 e3b0_val.mac_0_class_t_guarantied_hyst);
2367 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST,
2368 e3b0_val.mac_0_class_t_guarantied_hyst);
2370 /* The number of blocks guarantied for class #t in MAC1.t=0,1
2372 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED,
2373 e3b0_val.mac_1_class_t_guarantied);
2374 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED,
2375 e3b0_val.mac_1_class_t_guarantied);
2376 /* The hysteresis on the guarantied buffer space for class #t
2379 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST,
2380 e3b0_val.mac_1_class_t_guarantied_hyst);
2381 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST,
2382 e3b0_val.mac_1_class_t_guarantied_hyst);
2385 return bnx2x_status;
2388 /******************************************************************************
2390 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2391 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2392 ******************************************************************************/
2393 static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2395 u32 priority_mask, u8 port)
2397 u32 nig_reg_rx_priority_mask_add = 0;
2399 switch (cos_entry) {
2401 nig_reg_rx_priority_mask_add = (port) ?
2402 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2403 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2406 nig_reg_rx_priority_mask_add = (port) ?
2407 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2408 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2411 nig_reg_rx_priority_mask_add = (port) ?
2412 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2413 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2418 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2423 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2428 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2432 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2436 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2438 struct bnx2x *bp = params->bp;
2440 REG_WR(bp, params->shmem_base +
2441 offsetof(struct shmem_region,
2442 port_mb[params->port].link_status), link_status);
2445 static void bnx2x_update_pfc_nig(struct link_params *params,
2446 struct link_vars *vars,
2447 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2449 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2450 u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
2451 u32 pkt_priority_to_cos = 0;
2452 struct bnx2x *bp = params->bp;
2453 u8 port = params->port;
2455 int set_pfc = params->feature_config_flags &
2456 FEATURE_CONFIG_PFC_ENABLED;
2457 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2459 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2460 * MAC control frames (that are not pause packets)
2461 * will be forwarded to the XCM.
2463 xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :
2464 NIG_REG_LLH0_XCM_MASK);
2465 /* NIG params will override non PFC params, since it's possible to
2466 * do transition from PFC to SAFC
2476 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2477 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2482 llfc_out_en = nig_params->llfc_out_en;
2483 llfc_enable = nig_params->llfc_enable;
2484 pause_enable = nig_params->pause_enable;
2485 } else /* Default non PFC mode - PAUSE */
2488 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2489 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2494 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2495 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2496 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2497 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2498 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2499 NIG_REG_LLFC_ENABLE_0, llfc_enable);
2500 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2501 NIG_REG_PAUSE_ENABLE_0, pause_enable);
2503 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2504 NIG_REG_PPP_ENABLE_0, ppp_enable);
2506 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2507 NIG_REG_LLH0_XCM_MASK, xcm_mask);
2509 REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2510 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2512 /* Output enable for RX_XCM # IF */
2513 REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN :
2514 NIG_REG_XCM0_OUT_EN, xcm_out_en);
2516 /* HW PFC TX enable */
2517 REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE :
2518 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
2522 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2524 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2525 bnx2x_pfc_nig_rx_priority_mask(bp, i,
2526 nig_params->rx_cos_priority_mask[i], port);
2528 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2529 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2530 nig_params->llfc_high_priority_classes);
2532 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2533 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2534 nig_params->llfc_low_priority_classes);
2536 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2537 NIG_REG_P0_PKT_PRIORITY_TO_COS,
2538 pkt_priority_to_cos);
2541 int bnx2x_update_pfc(struct link_params *params,
2542 struct link_vars *vars,
2543 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2545 /* The PFC and pause are orthogonal to one another, meaning when
2546 * PFC is enabled, the pause are disabled, and when PFC is
2547 * disabled, pause are set according to the pause result.
2550 struct bnx2x *bp = params->bp;
2551 int bnx2x_status = 0;
2552 u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2554 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2555 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2557 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2559 bnx2x_update_mng(params, vars->link_status);
2561 /* Update NIG params */
2562 bnx2x_update_pfc_nig(params, vars, pfc_params);
2564 /* Update BRB params */
2565 bnx2x_status = bnx2x_update_pfc_brb(params, vars, pfc_params);
2567 return bnx2x_status;
2570 return bnx2x_status;
2572 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2574 bnx2x_update_pfc_xmac(params, vars, 0);
2576 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2578 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2580 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2581 bnx2x_emac_enable(params, vars, 0);
2582 return bnx2x_status;
2585 bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2587 bnx2x_update_pfc_bmac1(params, vars);
2590 if ((params->feature_config_flags &
2591 FEATURE_CONFIG_PFC_ENABLED) ||
2592 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2594 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2596 return bnx2x_status;
2600 static int bnx2x_bmac1_enable(struct link_params *params,
2601 struct link_vars *vars,
2604 struct bnx2x *bp = params->bp;
2605 u8 port = params->port;
2606 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2607 NIG_REG_INGRESS_BMAC0_MEM;
2611 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2616 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2620 wb_data[0] = ((params->mac_addr[2] << 24) |
2621 (params->mac_addr[3] << 16) |
2622 (params->mac_addr[4] << 8) |
2623 params->mac_addr[5]);
2624 wb_data[1] = ((params->mac_addr[0] << 8) |
2625 params->mac_addr[1]);
2626 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2632 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2636 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2639 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2641 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2643 bnx2x_update_pfc_bmac1(params, vars);
2646 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2648 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2650 /* Set cnt max size */
2651 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2653 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2655 /* Configure SAFC */
2656 wb_data[0] = 0x1000200;
2658 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2664 static int bnx2x_bmac2_enable(struct link_params *params,
2665 struct link_vars *vars,
2668 struct bnx2x *bp = params->bp;
2669 u8 port = params->port;
2670 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2671 NIG_REG_INGRESS_BMAC0_MEM;
2674 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2678 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2681 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2684 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2690 wb_data[0] = ((params->mac_addr[2] << 24) |
2691 (params->mac_addr[3] << 16) |
2692 (params->mac_addr[4] << 8) |
2693 params->mac_addr[5]);
2694 wb_data[1] = ((params->mac_addr[0] << 8) |
2695 params->mac_addr[1]);
2696 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2701 /* Configure SAFC */
2702 wb_data[0] = 0x1000200;
2704 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2709 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2711 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2715 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2717 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2719 /* Set cnt max size */
2720 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2722 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2724 bnx2x_update_pfc_bmac2(params, vars, is_lb);
2729 static int bnx2x_bmac_enable(struct link_params *params,
2730 struct link_vars *vars,
2734 u8 port = params->port;
2735 struct bnx2x *bp = params->bp;
2737 /* Reset and unreset the BigMac */
2738 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2739 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2740 usleep_range(1000, 2000);
2742 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2743 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2745 /* Enable access for bmac registers */
2746 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2748 /* Enable BMAC according to BMAC type*/
2750 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2752 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2753 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2754 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2755 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2757 if ((params->feature_config_flags &
2758 FEATURE_CONFIG_PFC_ENABLED) ||
2759 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2761 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2762 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2763 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2764 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2765 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2766 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2768 vars->mac_type = MAC_TYPE_BMAC;
2772 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
2774 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2775 NIG_REG_INGRESS_BMAC0_MEM;
2777 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2779 /* Only if the bmac is out of reset */
2780 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2781 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2784 if (CHIP_IS_E2(bp)) {
2785 /* Clear Rx Enable bit in BMAC_CONTROL register */
2786 REG_RD_DMAE(bp, bmac_addr +
2787 BIGMAC2_REGISTER_BMAC_CONTROL,
2789 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2790 REG_WR_DMAE(bp, bmac_addr +
2791 BIGMAC2_REGISTER_BMAC_CONTROL,
2794 /* Clear Rx Enable bit in BMAC_CONTROL register */
2795 REG_RD_DMAE(bp, bmac_addr +
2796 BIGMAC_REGISTER_BMAC_CONTROL,
2798 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2799 REG_WR_DMAE(bp, bmac_addr +
2800 BIGMAC_REGISTER_BMAC_CONTROL,
2803 usleep_range(1000, 2000);
2807 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2810 struct bnx2x *bp = params->bp;
2811 u8 port = params->port;
2816 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2818 /* Wait for init credit */
2819 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2820 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2821 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
2823 while ((init_crd != crd) && count) {
2824 usleep_range(5000, 10000);
2825 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2828 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2829 if (init_crd != crd) {
2830 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2835 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2836 line_speed == SPEED_10 ||
2837 line_speed == SPEED_100 ||
2838 line_speed == SPEED_1000 ||
2839 line_speed == SPEED_2500) {
2840 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2841 /* Update threshold */
2842 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2843 /* Update init credit */
2844 init_crd = 778; /* (800-18-4) */
2847 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2849 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2850 /* Update threshold */
2851 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2852 /* Update init credit */
2853 switch (line_speed) {
2855 init_crd = thresh + 553 - 22;
2858 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2863 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2864 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2865 line_speed, init_crd);
2867 /* Probe the credit changes */
2868 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2869 usleep_range(5000, 10000);
2870 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2873 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2878 * bnx2x_get_emac_base - retrive emac base address
2880 * @bp: driver handle
2881 * @mdc_mdio_access: access type
2884 * This function selects the MDC/MDIO access (through emac0 or
2885 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2886 * phy has a default access mode, which could also be overridden
2887 * by nvram configuration. This parameter, whether this is the
2888 * default phy configuration, or the nvram overrun
2889 * configuration, is passed here as mdc_mdio_access and selects
2890 * the emac_base for the CL45 read/writes operations
2892 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2893 u32 mdc_mdio_access, u8 port)
2896 switch (mdc_mdio_access) {
2897 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2899 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2900 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2901 emac_base = GRCBASE_EMAC1;
2903 emac_base = GRCBASE_EMAC0;
2905 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2906 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2907 emac_base = GRCBASE_EMAC0;
2909 emac_base = GRCBASE_EMAC1;
2911 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2912 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2914 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2915 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2924 /******************************************************************/
2925 /* CL22 access functions */
2926 /******************************************************************/
2927 static int bnx2x_cl22_write(struct bnx2x *bp,
2928 struct bnx2x_phy *phy,
2934 /* Switch to CL22 */
2935 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2936 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2937 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2940 tmp = ((phy->addr << 21) | (reg << 16) | val |
2941 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2942 EMAC_MDIO_COMM_START_BUSY);
2943 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2945 for (i = 0; i < 50; i++) {
2948 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2949 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2954 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2955 DP(NETIF_MSG_LINK, "write phy register failed\n");
2958 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2962 static int bnx2x_cl22_read(struct bnx2x *bp,
2963 struct bnx2x_phy *phy,
2964 u16 reg, u16 *ret_val)
2970 /* Switch to CL22 */
2971 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2972 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2973 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2976 val = ((phy->addr << 21) | (reg << 16) |
2977 EMAC_MDIO_COMM_COMMAND_READ_22 |
2978 EMAC_MDIO_COMM_START_BUSY);
2979 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2981 for (i = 0; i < 50; i++) {
2984 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2985 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2986 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2991 if (val & EMAC_MDIO_COMM_START_BUSY) {
2992 DP(NETIF_MSG_LINK, "read phy register failed\n");
2997 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
3001 /******************************************************************/
3002 /* CL45 access functions */
3003 /******************************************************************/
3004 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
3005 u8 devad, u16 reg, u16 *ret_val)
3010 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3011 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3012 EMAC_MDIO_STATUS_10MB);
3014 val = ((phy->addr << 21) | (devad << 16) | reg |
3015 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3016 EMAC_MDIO_COMM_START_BUSY);
3017 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3019 for (i = 0; i < 50; i++) {
3022 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3023 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3028 if (val & EMAC_MDIO_COMM_START_BUSY) {
3029 DP(NETIF_MSG_LINK, "read phy register failed\n");
3030 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
3035 val = ((phy->addr << 21) | (devad << 16) |
3036 EMAC_MDIO_COMM_COMMAND_READ_45 |
3037 EMAC_MDIO_COMM_START_BUSY);
3038 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3040 for (i = 0; i < 50; i++) {
3043 val = REG_RD(bp, phy->mdio_ctrl +
3044 EMAC_REG_EMAC_MDIO_COMM);
3045 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3046 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
3050 if (val & EMAC_MDIO_COMM_START_BUSY) {
3051 DP(NETIF_MSG_LINK, "read phy register failed\n");
3052 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
3057 /* Work around for E3 A0 */
3058 if (phy->flags & FLAGS_MDC_MDIO_WA) {
3059 phy->flags ^= FLAGS_DUMMY_READ;
3060 if (phy->flags & FLAGS_DUMMY_READ) {
3062 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3066 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3067 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3068 EMAC_MDIO_STATUS_10MB);
3072 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3073 u8 devad, u16 reg, u16 val)
3078 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3079 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3080 EMAC_MDIO_STATUS_10MB);
3083 tmp = ((phy->addr << 21) | (devad << 16) | reg |
3084 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3085 EMAC_MDIO_COMM_START_BUSY);
3086 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3088 for (i = 0; i < 50; i++) {
3091 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3092 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3097 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3098 DP(NETIF_MSG_LINK, "write phy register failed\n");
3099 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
3103 tmp = ((phy->addr << 21) | (devad << 16) | val |
3104 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
3105 EMAC_MDIO_COMM_START_BUSY);
3106 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3108 for (i = 0; i < 50; i++) {
3111 tmp = REG_RD(bp, phy->mdio_ctrl +
3112 EMAC_REG_EMAC_MDIO_COMM);
3113 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3118 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3119 DP(NETIF_MSG_LINK, "write phy register failed\n");
3120 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
3124 /* Work around for E3 A0 */
3125 if (phy->flags & FLAGS_MDC_MDIO_WA) {
3126 phy->flags ^= FLAGS_DUMMY_READ;
3127 if (phy->flags & FLAGS_DUMMY_READ) {
3129 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3132 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3133 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3134 EMAC_MDIO_STATUS_10MB);
3138 /******************************************************************/
3140 /******************************************************************/
3141 static u8 bnx2x_eee_has_cap(struct link_params *params)
3143 struct bnx2x *bp = params->bp;
3145 if (REG_RD(bp, params->shmem2_base) <=
3146 offsetof(struct shmem2_region, eee_status[params->port]))
3152 static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer)
3154 switch (nvram_mode) {
3155 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
3156 *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME;
3158 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
3159 *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME;
3161 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
3162 *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME;
3172 static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode)
3174 switch (idle_timer) {
3175 case EEE_MODE_NVRAM_BALANCED_TIME:
3176 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
3178 case EEE_MODE_NVRAM_AGGRESSIVE_TIME:
3179 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
3181 case EEE_MODE_NVRAM_LATENCY_TIME:
3182 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
3185 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
3192 static u32 bnx2x_eee_calc_timer(struct link_params *params)
3194 u32 eee_mode, eee_idle;
3195 struct bnx2x *bp = params->bp;
3197 if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) {
3198 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
3199 /* time value in eee_mode --> used directly*/
3200 eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK;
3202 /* hsi value in eee_mode --> time */
3203 if (bnx2x_eee_nvram_to_time(params->eee_mode &
3204 EEE_MODE_NVRAM_MASK,
3209 /* hsi values in nvram --> time*/
3210 eee_mode = ((REG_RD(bp, params->shmem_base +
3211 offsetof(struct shmem_region, dev_info.
3212 port_feature_config[params->port].
3214 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
3215 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
3217 if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle))
3224 static int bnx2x_eee_set_timers(struct link_params *params,
3225 struct link_vars *vars)
3227 u32 eee_idle = 0, eee_mode;
3228 struct bnx2x *bp = params->bp;
3230 eee_idle = bnx2x_eee_calc_timer(params);
3233 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
3235 } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) &&
3236 (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) &&
3237 (params->eee_mode & EEE_MODE_OUTPUT_TIME)) {
3238 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n");
3242 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
3243 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
3244 /* eee_idle in 1u --> eee_status in 16u */
3246 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
3247 SHMEM_EEE_TIME_OUTPUT_BIT;
3249 if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode))
3251 vars->eee_status |= eee_mode;
3257 static int bnx2x_eee_initial_config(struct link_params *params,
3258 struct link_vars *vars, u8 mode)
3260 vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
3262 /* Propogate params' bits --> vars (for migration exposure) */
3263 if (params->eee_mode & EEE_MODE_ENABLE_LPI)
3264 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
3266 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
3268 if (params->eee_mode & EEE_MODE_ADV_LPI)
3269 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
3271 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
3273 return bnx2x_eee_set_timers(params, vars);
3276 static int bnx2x_eee_disable(struct bnx2x_phy *phy,
3277 struct link_params *params,
3278 struct link_vars *vars)
3280 struct bnx2x *bp = params->bp;
3282 /* Make Certain LPI is disabled */
3283 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
3285 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
3287 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3292 static int bnx2x_eee_advertise(struct bnx2x_phy *phy,
3293 struct link_params *params,
3294 struct link_vars *vars, u8 modes)
3296 struct bnx2x *bp = params->bp;
3299 /* Mask events preventing LPI generation */
3300 REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
3302 if (modes & SHMEM_EEE_10G_ADV) {
3303 DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n");
3306 if (modes & SHMEM_EEE_1G_ADV) {
3307 DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n");
3311 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
3313 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3314 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
3319 static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status)
3321 struct bnx2x *bp = params->bp;
3323 if (bnx2x_eee_has_cap(params))
3324 REG_WR(bp, params->shmem2_base +
3325 offsetof(struct shmem2_region,
3326 eee_status[params->port]), eee_status);
3329 static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy,
3330 struct link_params *params,
3331 struct link_vars *vars)
3333 struct bnx2x *bp = params->bp;
3334 u16 adv = 0, lp = 0;
3338 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
3339 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
3342 lp_adv |= SHMEM_EEE_100M_ADV;
3344 if (vars->line_speed == SPEED_100)
3346 DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n");
3350 lp_adv |= SHMEM_EEE_1G_ADV;
3352 if (vars->line_speed == SPEED_1000)
3354 DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n");
3358 lp_adv |= SHMEM_EEE_10G_ADV;
3360 if (vars->line_speed == SPEED_10000)
3362 DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n");
3366 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
3367 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
3370 DP(NETIF_MSG_LINK, "EEE is active\n");
3371 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
3376 /******************************************************************/
3377 /* BSC access functions from E3 */
3378 /******************************************************************/
3379 static void bnx2x_bsc_module_sel(struct link_params *params)
3382 u32 board_cfg, sfp_ctrl;
3383 u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3384 struct bnx2x *bp = params->bp;
3385 u8 port = params->port;
3386 /* Read I2C output PINs */
3387 board_cfg = REG_RD(bp, params->shmem_base +
3388 offsetof(struct shmem_region,
3389 dev_info.shared_hw_config.board));
3390 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3391 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3392 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3394 /* Read I2C output value */
3395 sfp_ctrl = REG_RD(bp, params->shmem_base +
3396 offsetof(struct shmem_region,
3397 dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3398 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3399 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3400 DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3401 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3402 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3405 static int bnx2x_bsc_read(struct link_params *params,
3406 struct bnx2x_phy *phy,
3415 struct bnx2x *bp = params->bp;
3417 if ((sl_devid != 0xa0) && (sl_devid != 0xa2)) {
3418 DP(NETIF_MSG_LINK, "invalid sl_devid 0x%x\n", sl_devid);
3422 if (xfer_cnt > 16) {
3423 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3427 bnx2x_bsc_module_sel(params);
3429 xfer_cnt = 16 - lc_addr;
3431 /* Enable the engine */
3432 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3433 val |= MCPR_IMC_COMMAND_ENABLE;
3434 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3436 /* Program slave device ID */
3437 val = (sl_devid << 16) | sl_addr;
3438 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3440 /* Start xfer with 0 byte to update the address pointer ???*/
3441 val = (MCPR_IMC_COMMAND_ENABLE) |
3442 (MCPR_IMC_COMMAND_WRITE_OP <<
3443 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3444 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3445 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3447 /* Poll for completion */
3449 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3450 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3452 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3454 DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3463 /* Start xfer with read op */
3464 val = (MCPR_IMC_COMMAND_ENABLE) |
3465 (MCPR_IMC_COMMAND_READ_OP <<
3466 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3467 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3469 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3471 /* Poll for completion */
3473 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3474 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3476 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3478 DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3486 for (i = (lc_addr >> 2); i < 4; i++) {
3487 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3489 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3490 ((data_array[i] & 0x0000ff00) << 8) |
3491 ((data_array[i] & 0x00ff0000) >> 8) |
3492 ((data_array[i] & 0xff000000) >> 24);
3498 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3499 u8 devad, u16 reg, u16 or_val)
3502 bnx2x_cl45_read(bp, phy, devad, reg, &val);
3503 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3506 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3507 u8 devad, u16 reg, u16 *ret_val)
3510 /* Probe for the phy according to the given phy_addr, and execute
3511 * the read request on it
3513 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3514 if (params->phy[phy_index].addr == phy_addr) {
3515 return bnx2x_cl45_read(params->bp,
3516 ¶ms->phy[phy_index], devad,
3523 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3524 u8 devad, u16 reg, u16 val)
3527 /* Probe for the phy according to the given phy_addr, and execute
3528 * the write request on it
3530 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3531 if (params->phy[phy_index].addr == phy_addr) {
3532 return bnx2x_cl45_write(params->bp,
3533 ¶ms->phy[phy_index], devad,
3539 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3540 struct link_params *params)
3543 struct bnx2x *bp = params->bp;
3544 u32 path_swap, path_swap_ovr;
3548 port = params->port;
3550 if (bnx2x_is_4_port_mode(bp)) {
3551 u32 port_swap, port_swap_ovr;
3553 /* Figure out path swap value */
3554 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3555 if (path_swap_ovr & 0x1)
3556 path_swap = (path_swap_ovr & 0x2);
3558 path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3563 /* Figure out port swap value */
3564 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3565 if (port_swap_ovr & 0x1)
3566 port_swap = (port_swap_ovr & 0x2);
3568 port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3573 lane = (port<<1) + path;
3574 } else { /* Two port mode - no port swap */
3576 /* Figure out path swap value */
3578 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3579 if (path_swap_ovr & 0x1) {
3580 path_swap = (path_swap_ovr & 0x2);
3583 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3593 static void bnx2x_set_aer_mmd(struct link_params *params,
3594 struct bnx2x_phy *phy)
3597 u16 offset, aer_val;
3598 struct bnx2x *bp = params->bp;
3599 ser_lane = ((params->lane_config &
3600 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3601 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3603 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3604 (phy->addr + ser_lane) : 0;
3606 if (USES_WARPCORE(bp)) {
3607 aer_val = bnx2x_get_warpcore_lane(phy, params);
3608 /* In Dual-lane mode, two lanes are joined together,
3609 * so in order to configure them, the AER broadcast method is
3611 * 0x200 is the broadcast address for lanes 0,1
3612 * 0x201 is the broadcast address for lanes 2,3
3614 if (phy->flags & FLAGS_WC_DUAL_MODE)
3615 aer_val = (aer_val >> 1) | 0x200;
3616 } else if (CHIP_IS_E2(bp))
3617 aer_val = 0x3800 + offset - 1;
3619 aer_val = 0x3800 + offset;
3621 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3622 MDIO_AER_BLOCK_AER_REG, aer_val);
3626 /******************************************************************/
3627 /* Internal phy section */
3628 /******************************************************************/
3630 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3632 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3635 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3636 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3638 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3641 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3644 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3648 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3650 val = SERDES_RESET_BITS << (port*16);
3652 /* Reset and unreset the SerDes/XGXS */
3653 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3655 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3657 bnx2x_set_serdes_access(bp, port);
3659 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3660 DEFAULT_PHY_DEV_ADDR);
3663 static void bnx2x_xgxs_deassert(struct link_params *params)
3665 struct bnx2x *bp = params->bp;
3668 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3669 port = params->port;
3671 val = XGXS_RESET_BITS << (port*16);
3673 /* Reset and unreset the SerDes/XGXS */
3674 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3676 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3678 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
3679 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
3680 params->phy[INT_PHY].def_md_devad);
3683 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3684 struct link_params *params, u16 *ieee_fc)
3686 struct bnx2x *bp = params->bp;
3687 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3688 /* Resolve pause mode and advertisement Please refer to Table
3689 * 28B-3 of the 802.3ab-1999 spec
3692 switch (phy->req_flow_ctrl) {
3693 case BNX2X_FLOW_CTRL_AUTO:
3694 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
3695 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3698 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3701 case BNX2X_FLOW_CTRL_TX:
3702 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3705 case BNX2X_FLOW_CTRL_RX:
3706 case BNX2X_FLOW_CTRL_BOTH:
3707 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3710 case BNX2X_FLOW_CTRL_NONE:
3712 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3715 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3718 static void set_phy_vars(struct link_params *params,
3719 struct link_vars *vars)
3721 struct bnx2x *bp = params->bp;
3722 u8 actual_phy_idx, phy_index, link_cfg_idx;
3723 u8 phy_config_swapped = params->multi_phy_config &
3724 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3725 for (phy_index = INT_PHY; phy_index < params->num_phys;
3727 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3728 actual_phy_idx = phy_index;
3729 if (phy_config_swapped) {
3730 if (phy_index == EXT_PHY1)
3731 actual_phy_idx = EXT_PHY2;
3732 else if (phy_index == EXT_PHY2)
3733 actual_phy_idx = EXT_PHY1;
3735 params->phy[actual_phy_idx].req_flow_ctrl =
3736 params->req_flow_ctrl[link_cfg_idx];
3738 params->phy[actual_phy_idx].req_line_speed =
3739 params->req_line_speed[link_cfg_idx];
3741 params->phy[actual_phy_idx].speed_cap_mask =
3742 params->speed_cap_mask[link_cfg_idx];
3744 params->phy[actual_phy_idx].req_duplex =
3745 params->req_duplex[link_cfg_idx];
3747 if (params->req_line_speed[link_cfg_idx] ==
3749 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3751 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3752 " speed_cap_mask %x\n",
3753 params->phy[actual_phy_idx].req_flow_ctrl,
3754 params->phy[actual_phy_idx].req_line_speed,
3755 params->phy[actual_phy_idx].speed_cap_mask);
3759 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3760 struct bnx2x_phy *phy,
3761 struct link_vars *vars)
3764 struct bnx2x *bp = params->bp;
3765 /* Read modify write pause advertizing */
3766 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3768 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3770 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3771 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3772 if ((vars->ieee_fc &
3773 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3774 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3775 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3777 if ((vars->ieee_fc &
3778 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3779 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3780 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3782 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3783 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3786 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3788 switch (pause_result) { /* ASYM P ASYM P */
3789 case 0xb: /* 1 0 1 1 */
3790 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3793 case 0xe: /* 1 1 1 0 */
3794 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3797 case 0x5: /* 0 1 0 1 */
3798 case 0x7: /* 0 1 1 1 */
3799 case 0xd: /* 1 1 0 1 */
3800 case 0xf: /* 1 1 1 1 */
3801 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3807 if (pause_result & (1<<0))
3808 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3809 if (pause_result & (1<<1))
3810 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3814 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
3815 struct link_params *params,
3816 struct link_vars *vars)
3818 u16 ld_pause; /* local */
3819 u16 lp_pause; /* link partner */
3821 struct bnx2x *bp = params->bp;
3822 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3823 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause);
3824 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause);
3825 } else if (CHIP_IS_E3(bp) &&
3826 SINGLE_MEDIA_DIRECT(params)) {
3827 u8 lane = bnx2x_get_warpcore_lane(phy, params);
3828 u16 gp_status, gp_mask;
3829 bnx2x_cl45_read(bp, phy,
3830 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
3832 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
3833 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3835 if ((gp_status & gp_mask) == gp_mask) {
3836 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3837 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3838 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3839 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3841 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3842 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3843 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3844 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3845 ld_pause = ((ld_pause &
3846 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3848 lp_pause = ((lp_pause &
3849 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3853 bnx2x_cl45_read(bp, phy,
3855 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3856 bnx2x_cl45_read(bp, phy,
3858 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3860 pause_result = (ld_pause &
3861 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3862 pause_result |= (lp_pause &
3863 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3864 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result);
3865 bnx2x_pause_resolve(vars, pause_result);
3869 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3870 struct link_params *params,
3871 struct link_vars *vars)
3874 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3875 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
3876 /* Update the advertised flow-controled of LD/LP in AN */
3877 if (phy->req_line_speed == SPEED_AUTO_NEG)
3878 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3879 /* But set the flow-control result as the requested one */
3880 vars->flow_ctrl = phy->req_flow_ctrl;
3881 } else if (phy->req_line_speed != SPEED_AUTO_NEG)
3882 vars->flow_ctrl = params->req_fc_auto_adv;
3883 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3885 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3889 /******************************************************************/
3890 /* Warpcore section */
3891 /******************************************************************/
3892 /* The init_internal_warpcore should mirror the xgxs,
3893 * i.e. reset the lane (if needed), set aer for the
3894 * init configuration, and set/clear SGMII flag. Internal
3895 * phy init is done purely in phy_init stage.
3898 static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy,
3899 struct link_params *params)
3901 struct bnx2x *bp = params->bp;
3903 DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n");
3904 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3905 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
3906 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3907 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
3910 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3911 struct link_params *params,
3912 struct link_vars *vars) {
3913 u16 val16 = 0, lane, i;
3914 struct bnx2x *bp = params->bp;
3915 static struct bnx2x_reg_set reg_set[] = {
3916 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3917 {MDIO_AN_DEVAD, MDIO_WC_REG_PAR_DET_10G_CTRL, 0},
3918 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0},
3919 {MDIO_WC_DEVAD, MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0xff},
3920 {MDIO_WC_DEVAD, MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0x5555},
3921 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
3922 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
3923 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
3924 /* Disable Autoneg: re-enable it after adv is done. */
3925 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0}
3927 DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3928 /* Set to default registers that may be overriden by 10G force */
3929 for (i = 0; i < sizeof(reg_set)/sizeof(struct bnx2x_reg_set); i++)
3930 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3933 /* Check adding advertisement for 1G KX */
3934 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3935 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3936 (vars->line_speed == SPEED_1000)) {
3937 u32 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
3940 /* Enable CL37 1G Parallel Detect */
3941 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1);
3942 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3944 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3945 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3946 (vars->line_speed == SPEED_10000)) {
3947 /* Check adding advertisement for 10G KR */
3949 /* Enable 10G Parallel Detect */
3950 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3951 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3953 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3956 /* Set Transmit PMD settings */
3957 lane = bnx2x_get_warpcore_lane(phy, params);
3958 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3959 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3960 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3961 (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3962 (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3963 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3964 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3966 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3967 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3970 /* Advertised speeds */
3971 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3972 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, val16);
3974 /* Advertised and set FEC (Forward Error Correction) */
3975 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3976 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3977 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3978 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3980 /* Enable CL37 BAM */
3981 if (REG_RD(bp, params->shmem_base +
3982 offsetof(struct shmem_region, dev_info.
3983 port_hw_config[params->port].default_cfg)) &
3984 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3985 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3986 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
3988 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3991 /* Advertise pause */
3992 bnx2x_ext_phy_set_pause(params, phy, vars);
3993 /* Set KR Autoneg Work-Around flag for Warpcore version older than D108
3995 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3996 MDIO_WC_REG_UC_INFO_B1_VERSION, &val16);
3997 if (val16 < 0xd108) {
3998 DP(NETIF_MSG_LINK, "Enable AN KR work-around\n");
3999 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
4001 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4002 MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
4004 /* Over 1G - AN local device user page 1 */
4005 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4006 MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
4008 /* Enable Autoneg */
4009 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4010 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4014 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
4015 struct link_params *params,
4016 struct link_vars *vars)
4018 struct bnx2x *bp = params->bp;
4020 static struct bnx2x_reg_set reg_set[] = {
4021 /* Disable Autoneg */
4022 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
4023 {MDIO_AN_DEVAD, MDIO_WC_REG_PAR_DET_10G_CTRL, 0},
4024 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
4026 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
4027 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
4028 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
4029 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
4030 /* Disable CL36 PCS Tx */
4031 {MDIO_WC_DEVAD, MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0x0},
4032 /* Double Wide Single Data Rate @ pll rate */
4033 {MDIO_WC_DEVAD, MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0xFFFF},
4034 /* Leave cl72 training enable, needed for KR */
4036 MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150,
4040 for (i = 0; i < sizeof(reg_set)/sizeof(struct bnx2x_reg_set); i++)
4041 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
4044 /* Leave CL72 enabled */
4045 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4046 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
4049 /* Set speed via PMA/PMD register */
4050 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
4051 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
4053 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
4054 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
4056 /* Enable encoded forced speed */
4057 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4058 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
4060 /* Turn TX scramble payload only the 64/66 scrambler */
4061 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4062 MDIO_WC_REG_TX66_CONTROL, 0x9);
4064 /* Turn RX scramble payload only the 64/66 scrambler */
4065 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4066 MDIO_WC_REG_RX66_CONTROL, 0xF9);
4068 /* Set and clear loopback to cause a reset to 64/66 decoder */
4069 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4070 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
4071 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4072 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
4076 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
4077 struct link_params *params,
4080 struct bnx2x *bp = params->bp;
4081 u16 misc1_val, tap_val, tx_driver_val, lane, val;
4082 /* Hold rxSeqStart */
4083 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4084 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
4086 /* Hold tx_fifo_reset */
4087 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4088 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
4090 /* Disable CL73 AN */
4091 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
4093 /* Disable 100FX Enable and Auto-Detect */
4094 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4095 MDIO_WC_REG_FX100_CTRL1, &val);
4096 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4097 MDIO_WC_REG_FX100_CTRL1, (val & 0xFFFA));
4099 /* Disable 100FX Idle detect */
4100 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4101 MDIO_WC_REG_FX100_CTRL3, 0x0080);
4103 /* Set Block address to Remote PHY & Clear forced_speed[5] */
4104 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4105 MDIO_WC_REG_DIGITAL4_MISC3, &val);
4106 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4107 MDIO_WC_REG_DIGITAL4_MISC3, (val & 0xFF7F));
4109 /* Turn off auto-detect & fiber mode */
4110 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4111 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
4112 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4113 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4116 /* Set filter_force_link, disable_false_link and parallel_detect */
4117 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4118 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
4119 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4120 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4121 ((val | 0x0006) & 0xFFFE));
4124 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4125 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
4127 misc1_val &= ~(0x1f);
4131 tap_val = ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
4132 (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
4133 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
4135 ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
4136 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
4137 (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
4141 tap_val = ((0x0f << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
4142 (0x2b << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
4143 (0x02 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
4145 ((0x03 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
4146 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
4147 (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
4149 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4150 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
4152 /* Set Transmit PMD settings */
4153 lane = bnx2x_get_warpcore_lane(phy, params);
4154 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4155 MDIO_WC_REG_TX_FIR_TAP,
4156 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
4157 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4158 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4161 /* Enable fiber mode, enable and invert sig_det */
4162 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4163 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
4165 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
4166 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4167 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
4169 bnx2x_warpcore_set_lpi_passthrough(phy, params);
4171 /* 10G XFI Full Duplex */
4172 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4173 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
4175 /* Release tx_fifo_reset */
4176 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4177 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
4178 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4179 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, val & 0xFFFE);
4181 /* Release rxSeqStart */
4182 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4183 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
4184 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4185 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val & 0x7FFF));
4188 static void bnx2x_warpcore_set_20G_KR2(struct bnx2x *bp,
4189 struct bnx2x_phy *phy)
4191 DP(NETIF_MSG_LINK, "KR2 still not supported !!!\n");
4194 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
4195 struct bnx2x_phy *phy,
4198 /* Rx0 anaRxControl1G */
4199 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4200 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4202 /* Rx2 anaRxControl1G */
4203 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4204 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4206 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4207 MDIO_WC_REG_RX66_SCW0, 0xE070);
4209 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4210 MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4212 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4213 MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4215 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4216 MDIO_WC_REG_RX66_SCW3, 0x8090);
4218 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4219 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4221 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4222 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4224 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4225 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
4227 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4228 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
4230 /* Serdes Digital Misc1 */
4231 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4232 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
4234 /* Serdes Digital4 Misc3 */
4235 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4236 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
4238 /* Set Transmit PMD settings */
4239 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4240 MDIO_WC_REG_TX_FIR_TAP,
4241 ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
4242 (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
4243 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET) |
4244 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4245 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4246 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4247 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
4248 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
4249 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
4252 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
4253 struct link_params *params,
4257 struct bnx2x *bp = params->bp;
4258 u16 val16, digctrl_kx1, digctrl_kx2;
4260 /* Clear XFI clock comp in non-10G single lane mode. */
4261 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4262 MDIO_WC_REG_RX66_CONTROL, &val16);
4263 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4264 MDIO_WC_REG_RX66_CONTROL, val16 & ~(3<<13));
4266 if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) {
4268 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4269 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4270 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4271 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4273 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
4275 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4276 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4278 switch (phy->req_line_speed) {
4289 "Speed not supported: 0x%x\n", phy->req_line_speed);
4293 if (phy->req_duplex == DUPLEX_FULL)
4296 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4297 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
4299 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
4300 phy->req_line_speed);
4301 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4302 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4303 DP(NETIF_MSG_LINK, " (readback) %x\n", val16);
4306 /* SGMII Slave mode and disable signal detect */
4307 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4308 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
4312 digctrl_kx1 &= 0xff4a;
4314 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4315 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4318 /* Turn off parallel detect */
4319 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4320 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
4321 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4322 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4323 (digctrl_kx2 & ~(1<<2)));
4325 /* Re-enable parallel detect */
4326 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4327 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4328 (digctrl_kx2 | (1<<2)));
4330 /* Enable autodet */
4331 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4332 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4333 (digctrl_kx1 | 0x10));
4336 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4337 struct bnx2x_phy *phy,
4341 /* Take lane out of reset after configuration is finished */
4342 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4343 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4348 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4349 MDIO_WC_REG_DIGITAL5_MISC6, val);
4350 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4351 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4353 /* Clear SFI/XFI link settings registers */
4354 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4355 struct link_params *params,
4358 struct bnx2x *bp = params->bp;
4360 static struct bnx2x_reg_set wc_regs[] = {
4361 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
4362 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
4363 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
4364 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
4365 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4367 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4369 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4371 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
4372 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
4373 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
4374 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
4376 /* Set XFI clock comp as default. */
4377 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4378 MDIO_WC_REG_RX66_CONTROL, (3<<13));
4380 for (i = 0; i < sizeof(wc_regs)/sizeof(struct bnx2x_reg_set); i++)
4381 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg,
4384 lane = bnx2x_get_warpcore_lane(phy, params);
4385 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4386 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4390 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4392 u32 shmem_base, u8 port,
4393 u8 *gpio_num, u8 *gpio_port)
4398 if (CHIP_IS_E3(bp)) {
4399 cfg_pin = (REG_RD(bp, shmem_base +
4400 offsetof(struct shmem_region,
4401 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4402 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4403 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4405 /* Should not happen. This function called upon interrupt
4406 * triggered by GPIO ( since EPIO can only generate interrupts
4408 * So if this function was called and none of the GPIOs was set,
4409 * it means the shit hit the fan.
4411 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4412 (cfg_pin > PIN_CFG_GPIO3_P1)) {
4414 "ERROR: Invalid cfg pin %x for module detect indication\n",
4419 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4420 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4422 *gpio_num = MISC_REGISTERS_GPIO_3;
4425 DP(NETIF_MSG_LINK, "MOD_ABS int GPIO%d_P%d\n", *gpio_num, *gpio_port);
4429 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4430 struct link_params *params)
4432 struct bnx2x *bp = params->bp;
4433 u8 gpio_num, gpio_port;
4435 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4436 params->shmem_base, params->port,
4437 &gpio_num, &gpio_port) != 0)
4439 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4441 /* Call the handling function in case module is detected */
4447 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy,
4448 struct link_params *params)
4450 u16 gp2_status_reg0, lane;
4451 struct bnx2x *bp = params->bp;
4453 lane = bnx2x_get_warpcore_lane(phy, params);
4455 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4458 return (gp2_status_reg0 >> (8+lane)) & 0x1;
4461 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4462 struct link_params *params,
4463 struct link_vars *vars)
4465 struct bnx2x *bp = params->bp;
4467 u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4468 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4470 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4472 if (!vars->turn_to_run_wc_rt)
4475 /* Return if there is no link partner */
4476 if (!(bnx2x_warpcore_get_sigdet(phy, params))) {
4477 DP(NETIF_MSG_LINK, "bnx2x_warpcore_get_sigdet false\n");
4481 if (vars->rx_tx_asic_rst) {
4482 serdes_net_if = (REG_RD(bp, params->shmem_base +
4483 offsetof(struct shmem_region, dev_info.
4484 port_hw_config[params->port].default_cfg)) &
4485 PORT_HW_CFG_NET_SERDES_IF_MASK);
4487 switch (serdes_net_if) {
4488 case PORT_HW_CFG_NET_SERDES_IF_KR:
4489 /* Do we get link yet? */
4490 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1,
4492 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
4494 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
4497 "gp_status1 0x%x\n", gp_status1);
4499 if (lnkup_kr || lnkup) {
4500 vars->rx_tx_asic_rst = 0;
4502 "link up, rx_tx_asic_rst 0x%x\n",
4503 vars->rx_tx_asic_rst);
4505 /* Reset the lane to see if link comes up.*/
4506 bnx2x_warpcore_reset_lane(bp, phy, 1);
4507 bnx2x_warpcore_reset_lane(bp, phy, 0);
4509 /* Restart Autoneg */
4510 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4511 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4513 vars->rx_tx_asic_rst--;
4514 DP(NETIF_MSG_LINK, "0x%x retry left\n",
4515 vars->rx_tx_asic_rst);
4523 } /*params->rx_tx_asic_rst*/
4526 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy,
4527 struct link_params *params)
4529 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4530 struct bnx2x *bp = params->bp;
4531 bnx2x_warpcore_clear_regs(phy, params, lane);
4532 if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] ==
4534 (phy->media_type != ETH_PHY_SFP_1G_FIBER)) {
4535 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4536 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4538 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4539 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0);
4543 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4544 struct link_params *params,
4545 struct link_vars *vars)
4547 struct bnx2x *bp = params->bp;
4550 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4551 serdes_net_if = (REG_RD(bp, params->shmem_base +
4552 offsetof(struct shmem_region, dev_info.
4553 port_hw_config[params->port].default_cfg)) &
4554 PORT_HW_CFG_NET_SERDES_IF_MASK);
4555 DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4556 "serdes_net_if = 0x%x\n",
4557 vars->line_speed, serdes_net_if);
4558 bnx2x_set_aer_mmd(params, phy);
4560 vars->phy_flags |= PHY_XGXS_FLAG;
4561 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4562 (phy->req_line_speed &&
4563 ((phy->req_line_speed == SPEED_100) ||
4564 (phy->req_line_speed == SPEED_10)))) {
4565 vars->phy_flags |= PHY_SGMII_FLAG;
4566 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4567 bnx2x_warpcore_clear_regs(phy, params, lane);
4568 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1);
4570 switch (serdes_net_if) {
4571 case PORT_HW_CFG_NET_SERDES_IF_KR:
4572 /* Enable KR Auto Neg */
4573 if (params->loopback_mode != LOOPBACK_EXT)
4574 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4576 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4577 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4581 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4582 bnx2x_warpcore_clear_regs(phy, params, lane);
4583 if (vars->line_speed == SPEED_10000) {
4584 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4585 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4587 if (SINGLE_MEDIA_DIRECT(params)) {
4588 DP(NETIF_MSG_LINK, "1G Fiber\n");
4591 DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4594 bnx2x_warpcore_set_sgmii_speed(phy,
4602 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4603 /* Issue Module detection */
4604 if (bnx2x_is_sfp_module_plugged(phy, params))
4605 bnx2x_sfp_module_detection(phy, params);
4607 bnx2x_warpcore_config_sfi(phy, params);
4610 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4611 if (vars->line_speed != SPEED_20000) {
4612 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4615 DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4616 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4617 /* Issue Module detection */
4619 bnx2x_sfp_module_detection(phy, params);
4622 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4623 if (vars->line_speed != SPEED_20000) {
4624 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4627 DP(NETIF_MSG_LINK, "Setting 20G KR2\n");
4628 bnx2x_warpcore_set_20G_KR2(bp, phy);
4633 "Unsupported Serdes Net Interface 0x%x\n",
4639 /* Take lane out of reset after configuration is finished */
4640 bnx2x_warpcore_reset_lane(bp, phy, 0);
4641 DP(NETIF_MSG_LINK, "Exit config init\n");
4644 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4645 struct bnx2x_phy *phy,
4648 struct bnx2x *bp = params->bp;
4650 u8 port = params->port;
4652 cfg_pin = REG_RD(bp, params->shmem_base +
4653 offsetof(struct shmem_region,
4654 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4655 PORT_HW_CFG_TX_LASER_MASK;
4656 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4657 DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4658 /* For 20G, the expected pin to be used is 3 pins after the current */
4660 bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4661 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4662 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4665 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4666 struct link_params *params)
4668 struct bnx2x *bp = params->bp;
4670 bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4671 bnx2x_set_mdio_clk(bp, params->chip_id, params->port);
4672 bnx2x_set_aer_mmd(params, phy);
4673 /* Global register */
4674 bnx2x_warpcore_reset_lane(bp, phy, 1);
4676 /* Clear loopback settings (if any) */
4678 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4679 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4680 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4681 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 &
4684 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4685 MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4686 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4687 MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 & 0xfffe);
4689 /* Update those 1-copy registers */
4690 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4691 MDIO_AER_BLOCK_AER_REG, 0);
4692 /* Enable 1G MDIO (1-copy) */
4693 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4694 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4696 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4697 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4700 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4701 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4702 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4703 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4708 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4709 struct link_params *params)
4711 struct bnx2x *bp = params->bp;
4714 DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4715 params->loopback_mode, phy->req_line_speed);
4717 if (phy->req_line_speed < SPEED_10000) {
4720 /* Update those 1-copy registers */
4721 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4722 MDIO_AER_BLOCK_AER_REG, 0);
4723 /* Enable 1G MDIO (1-copy) */
4724 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4725 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4727 /* Set 1G loopback based on lane (1-copy) */
4728 lane = bnx2x_get_warpcore_lane(phy, params);
4729 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4730 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4731 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4732 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4735 /* Switch back to 4-copy registers */
4736 bnx2x_set_aer_mmd(params, phy);
4739 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4740 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4743 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4744 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
4750 static void bnx2x_sync_link(struct link_params *params,
4751 struct link_vars *vars)
4753 struct bnx2x *bp = params->bp;
4755 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4756 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4757 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4758 if (vars->link_up) {
4759 DP(NETIF_MSG_LINK, "phy link up\n");
4761 vars->phy_link_up = 1;
4762 vars->duplex = DUPLEX_FULL;
4763 switch (vars->link_status &
4764 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4766 vars->duplex = DUPLEX_HALF;
4769 vars->line_speed = SPEED_10;
4773 vars->duplex = DUPLEX_HALF;
4777 vars->line_speed = SPEED_100;
4781 vars->duplex = DUPLEX_HALF;
4784 vars->line_speed = SPEED_1000;
4788 vars->duplex = DUPLEX_HALF;
4791 vars->line_speed = SPEED_2500;
4795 vars->line_speed = SPEED_10000;
4798 vars->line_speed = SPEED_20000;
4803 vars->flow_ctrl = 0;
4804 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4805 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4807 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4808 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4810 if (!vars->flow_ctrl)
4811 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4813 if (vars->line_speed &&
4814 ((vars->line_speed == SPEED_10) ||
4815 (vars->line_speed == SPEED_100))) {
4816 vars->phy_flags |= PHY_SGMII_FLAG;
4818 vars->phy_flags &= ~PHY_SGMII_FLAG;
4820 if (vars->line_speed &&
4821 USES_WARPCORE(bp) &&
4822 (vars->line_speed == SPEED_1000))
4823 vars->phy_flags |= PHY_SGMII_FLAG;
4824 /* Anything 10 and over uses the bmac */
4825 link_10g_plus = (vars->line_speed >= SPEED_10000);
4827 if (link_10g_plus) {
4828 if (USES_WARPCORE(bp))
4829 vars->mac_type = MAC_TYPE_XMAC;
4831 vars->mac_type = MAC_TYPE_BMAC;
4833 if (USES_WARPCORE(bp))
4834 vars->mac_type = MAC_TYPE_UMAC;
4836 vars->mac_type = MAC_TYPE_EMAC;
4838 } else { /* Link down */
4839 DP(NETIF_MSG_LINK, "phy link down\n");
4841 vars->phy_link_up = 0;
4843 vars->line_speed = 0;
4844 vars->duplex = DUPLEX_FULL;
4845 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4847 /* Indicate no mac active */
4848 vars->mac_type = MAC_TYPE_NONE;
4849 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4850 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4851 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
4852 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
4856 void bnx2x_link_status_update(struct link_params *params,
4857 struct link_vars *vars)
4859 struct bnx2x *bp = params->bp;
4860 u8 port = params->port;
4861 u32 sync_offset, media_types;
4862 /* Update PHY configuration */
4863 set_phy_vars(params, vars);
4865 vars->link_status = REG_RD(bp, params->shmem_base +
4866 offsetof(struct shmem_region,
4867 port_mb[port].link_status));
4868 if (bnx2x_eee_has_cap(params))
4869 vars->eee_status = REG_RD(bp, params->shmem2_base +
4870 offsetof(struct shmem2_region,
4871 eee_status[params->port]));
4873 vars->phy_flags = PHY_XGXS_FLAG;
4874 bnx2x_sync_link(params, vars);
4875 /* Sync media type */
4876 sync_offset = params->shmem_base +
4877 offsetof(struct shmem_region,
4878 dev_info.port_hw_config[port].media_type);
4879 media_types = REG_RD(bp, sync_offset);
4881 params->phy[INT_PHY].media_type =
4882 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4883 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4884 params->phy[EXT_PHY1].media_type =
4885 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4886 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4887 params->phy[EXT_PHY2].media_type =
4888 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4889 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4890 DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4892 /* Sync AEU offset */
4893 sync_offset = params->shmem_base +
4894 offsetof(struct shmem_region,
4895 dev_info.port_hw_config[port].aeu_int_mask);
4897 vars->aeu_int_mask = REG_RD(bp, sync_offset);
4899 /* Sync PFC status */
4900 if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4901 params->feature_config_flags |=
4902 FEATURE_CONFIG_PFC_ENABLED;
4904 params->feature_config_flags &=
4905 ~FEATURE_CONFIG_PFC_ENABLED;
4907 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n",
4908 vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4909 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
4910 vars->line_speed, vars->duplex, vars->flow_ctrl);
4913 static void bnx2x_set_master_ln(struct link_params *params,
4914 struct bnx2x_phy *phy)
4916 struct bnx2x *bp = params->bp;
4917 u16 new_master_ln, ser_lane;
4918 ser_lane = ((params->lane_config &
4919 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4920 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4922 /* Set the master_ln for AN */
4923 CL22_RD_OVER_CL45(bp, phy,
4924 MDIO_REG_BANK_XGXS_BLOCK2,
4925 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4928 CL22_WR_OVER_CL45(bp, phy,
4929 MDIO_REG_BANK_XGXS_BLOCK2 ,
4930 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4931 (new_master_ln | ser_lane));
4934 static int bnx2x_reset_unicore(struct link_params *params,
4935 struct bnx2x_phy *phy,
4938 struct bnx2x *bp = params->bp;
4941 CL22_RD_OVER_CL45(bp, phy,
4942 MDIO_REG_BANK_COMBO_IEEE0,
4943 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4945 /* Reset the unicore */
4946 CL22_WR_OVER_CL45(bp, phy,
4947 MDIO_REG_BANK_COMBO_IEEE0,
4948 MDIO_COMBO_IEEE0_MII_CONTROL,
4950 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4952 bnx2x_set_serdes_access(bp, params->port);
4954 /* Wait for the reset to self clear */
4955 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4958 /* The reset erased the previous bank value */
4959 CL22_RD_OVER_CL45(bp, phy,
4960 MDIO_REG_BANK_COMBO_IEEE0,
4961 MDIO_COMBO_IEEE0_MII_CONTROL,
4964 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4970 netdev_err(bp->dev, "Warning: PHY was not initialized,"
4973 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4978 static void bnx2x_set_swap_lanes(struct link_params *params,
4979 struct bnx2x_phy *phy)
4981 struct bnx2x *bp = params->bp;
4982 /* Each two bits represents a lane number:
4983 * No swap is 0123 => 0x1b no need to enable the swap
4985 u16 rx_lane_swap, tx_lane_swap;
4987 rx_lane_swap = ((params->lane_config &
4988 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4989 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4990 tx_lane_swap = ((params->lane_config &
4991 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4992 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4994 if (rx_lane_swap != 0x1b) {
4995 CL22_WR_OVER_CL45(bp, phy,
4996 MDIO_REG_BANK_XGXS_BLOCK2,
4997 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4999 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
5000 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
5002 CL22_WR_OVER_CL45(bp, phy,
5003 MDIO_REG_BANK_XGXS_BLOCK2,
5004 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
5007 if (tx_lane_swap != 0x1b) {
5008 CL22_WR_OVER_CL45(bp, phy,
5009 MDIO_REG_BANK_XGXS_BLOCK2,
5010 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
5012 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
5014 CL22_WR_OVER_CL45(bp, phy,
5015 MDIO_REG_BANK_XGXS_BLOCK2,
5016 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
5020 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
5021 struct link_params *params)
5023 struct bnx2x *bp = params->bp;
5025 CL22_RD_OVER_CL45(bp, phy,
5026 MDIO_REG_BANK_SERDES_DIGITAL,
5027 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
5029 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5030 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
5032 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
5033 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
5034 phy->speed_cap_mask, control2);
5035 CL22_WR_OVER_CL45(bp, phy,
5036 MDIO_REG_BANK_SERDES_DIGITAL,
5037 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
5040 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
5041 (phy->speed_cap_mask &
5042 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5043 DP(NETIF_MSG_LINK, "XGXS\n");
5045 CL22_WR_OVER_CL45(bp, phy,
5046 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5047 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
5048 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
5050 CL22_RD_OVER_CL45(bp, phy,
5051 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5052 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
5057 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
5059 CL22_WR_OVER_CL45(bp, phy,
5060 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5061 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
5064 /* Disable parallel detection of HiG */
5065 CL22_WR_OVER_CL45(bp, phy,
5066 MDIO_REG_BANK_XGXS_BLOCK2,
5067 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
5068 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
5069 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
5073 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
5074 struct link_params *params,
5075 struct link_vars *vars,
5078 struct bnx2x *bp = params->bp;
5082 CL22_RD_OVER_CL45(bp, phy,
5083 MDIO_REG_BANK_COMBO_IEEE0,
5084 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
5086 /* CL37 Autoneg Enabled */
5087 if (vars->line_speed == SPEED_AUTO_NEG)
5088 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
5089 else /* CL37 Autoneg Disabled */
5090 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5091 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
5093 CL22_WR_OVER_CL45(bp, phy,
5094 MDIO_REG_BANK_COMBO_IEEE0,
5095 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5097 /* Enable/Disable Autodetection */
5099 CL22_RD_OVER_CL45(bp, phy,
5100 MDIO_REG_BANK_SERDES_DIGITAL,
5101 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);
5102 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
5103 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
5104 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
5105 if (vars->line_speed == SPEED_AUTO_NEG)
5106 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5108 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5110 CL22_WR_OVER_CL45(bp, phy,
5111 MDIO_REG_BANK_SERDES_DIGITAL,
5112 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
5114 /* Enable TetonII and BAM autoneg */
5115 CL22_RD_OVER_CL45(bp, phy,
5116 MDIO_REG_BANK_BAM_NEXT_PAGE,
5117 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5119 if (vars->line_speed == SPEED_AUTO_NEG) {
5120 /* Enable BAM aneg Mode and TetonII aneg Mode */
5121 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5122 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5124 /* TetonII and BAM Autoneg Disabled */
5125 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5126 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5128 CL22_WR_OVER_CL45(bp, phy,
5129 MDIO_REG_BANK_BAM_NEXT_PAGE,
5130 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5134 /* Enable Cl73 FSM status bits */
5135 CL22_WR_OVER_CL45(bp, phy,
5136 MDIO_REG_BANK_CL73_USERB0,
5137 MDIO_CL73_USERB0_CL73_UCTRL,
5140 /* Enable BAM Station Manager*/
5141 CL22_WR_OVER_CL45(bp, phy,
5142 MDIO_REG_BANK_CL73_USERB0,
5143 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
5144 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
5145 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
5146 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
5148 /* Advertise CL73 link speeds */
5149 CL22_RD_OVER_CL45(bp, phy,
5150 MDIO_REG_BANK_CL73_IEEEB1,
5151 MDIO_CL73_IEEEB1_AN_ADV2,
5153 if (phy->speed_cap_mask &
5154 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5155 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
5156 if (phy->speed_cap_mask &
5157 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5158 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
5160 CL22_WR_OVER_CL45(bp, phy,
5161 MDIO_REG_BANK_CL73_IEEEB1,
5162 MDIO_CL73_IEEEB1_AN_ADV2,
5165 /* CL73 Autoneg Enabled */
5166 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
5168 } else /* CL73 Autoneg Disabled */
5171 CL22_WR_OVER_CL45(bp, phy,
5172 MDIO_REG_BANK_CL73_IEEEB0,
5173 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
5176 /* Program SerDes, forced speed */
5177 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
5178 struct link_params *params,
5179 struct link_vars *vars)
5181 struct bnx2x *bp = params->bp;
5184 /* Program duplex, disable autoneg and sgmii*/
5185 CL22_RD_OVER_CL45(bp, phy,
5186 MDIO_REG_BANK_COMBO_IEEE0,
5187 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
5188 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
5189 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5190 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
5191 if (phy->req_duplex == DUPLEX_FULL)
5192 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5193 CL22_WR_OVER_CL45(bp, phy,
5194 MDIO_REG_BANK_COMBO_IEEE0,
5195 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5198 * - needed only if the speed is greater than 1G (2.5G or 10G)
5200 CL22_RD_OVER_CL45(bp, phy,
5201 MDIO_REG_BANK_SERDES_DIGITAL,
5202 MDIO_SERDES_DIGITAL_MISC1, ®_val);
5203 /* Clearing the speed value before setting the right speed */
5204 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5206 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
5207 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5209 if (!((vars->line_speed == SPEED_1000) ||
5210 (vars->line_speed == SPEED_100) ||
5211 (vars->line_speed == SPEED_10))) {
5213 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
5214 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5215 if (vars->line_speed == SPEED_10000)
5217 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5220 CL22_WR_OVER_CL45(bp, phy,
5221 MDIO_REG_BANK_SERDES_DIGITAL,
5222 MDIO_SERDES_DIGITAL_MISC1, reg_val);
5226 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
5227 struct link_params *params)
5229 struct bnx2x *bp = params->bp;
5232 /* Set extended capabilities */
5233 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
5234 val |= MDIO_OVER_1G_UP1_2_5G;
5235 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5236 val |= MDIO_OVER_1G_UP1_10G;
5237 CL22_WR_OVER_CL45(bp, phy,
5238 MDIO_REG_BANK_OVER_1G,
5239 MDIO_OVER_1G_UP1, val);
5241 CL22_WR_OVER_CL45(bp, phy,
5242 MDIO_REG_BANK_OVER_1G,
5243 MDIO_OVER_1G_UP3, 0x400);
5246 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
5247 struct link_params *params,
5250 struct bnx2x *bp = params->bp;
5252 /* For AN, we are always publishing full duplex */
5254 CL22_WR_OVER_CL45(bp, phy,
5255 MDIO_REG_BANK_COMBO_IEEE0,
5256 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
5257 CL22_RD_OVER_CL45(bp, phy,
5258 MDIO_REG_BANK_CL73_IEEEB1,
5259 MDIO_CL73_IEEEB1_AN_ADV1, &val);
5260 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
5261 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
5262 CL22_WR_OVER_CL45(bp, phy,
5263 MDIO_REG_BANK_CL73_IEEEB1,
5264 MDIO_CL73_IEEEB1_AN_ADV1, val);
5267 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
5268 struct link_params *params,
5271 struct bnx2x *bp = params->bp;
5274 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
5275 /* Enable and restart BAM/CL37 aneg */
5278 CL22_RD_OVER_CL45(bp, phy,
5279 MDIO_REG_BANK_CL73_IEEEB0,
5280 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5283 CL22_WR_OVER_CL45(bp, phy,
5284 MDIO_REG_BANK_CL73_IEEEB0,
5285 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5287 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5288 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5291 CL22_RD_OVER_CL45(bp, phy,
5292 MDIO_REG_BANK_COMBO_IEEE0,
5293 MDIO_COMBO_IEEE0_MII_CONTROL,
5296 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
5298 CL22_WR_OVER_CL45(bp, phy,
5299 MDIO_REG_BANK_COMBO_IEEE0,
5300 MDIO_COMBO_IEEE0_MII_CONTROL,
5302 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5303 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
5307 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5308 struct link_params *params,
5309 struct link_vars *vars)
5311 struct bnx2x *bp = params->bp;
5314 /* In SGMII mode, the unicore is always slave */
5316 CL22_RD_OVER_CL45(bp, phy,
5317 MDIO_REG_BANK_SERDES_DIGITAL,
5318 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5320 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
5321 /* Set sgmii mode (and not fiber) */
5322 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
5323 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5324 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
5325 CL22_WR_OVER_CL45(bp, phy,
5326 MDIO_REG_BANK_SERDES_DIGITAL,
5327 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5330 /* If forced speed */
5331 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
5332 /* Set speed, disable autoneg */
5335 CL22_RD_OVER_CL45(bp, phy,
5336 MDIO_REG_BANK_COMBO_IEEE0,
5337 MDIO_COMBO_IEEE0_MII_CONTROL,
5339 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5340 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5341 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5343 switch (vars->line_speed) {
5346 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5350 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5353 /* There is nothing to set for 10M */
5356 /* Invalid speed for SGMII */
5357 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5362 /* Setting the full duplex */
5363 if (phy->req_duplex == DUPLEX_FULL)
5365 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5366 CL22_WR_OVER_CL45(bp, phy,
5367 MDIO_REG_BANK_COMBO_IEEE0,
5368 MDIO_COMBO_IEEE0_MII_CONTROL,
5371 } else { /* AN mode */
5372 /* Enable and restart AN */
5373 bnx2x_restart_autoneg(phy, params, 0);
5379 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
5380 struct link_params *params)
5382 struct bnx2x *bp = params->bp;
5383 u16 pd_10g, status2_1000x;
5384 if (phy->req_line_speed != SPEED_AUTO_NEG)
5386 CL22_RD_OVER_CL45(bp, phy,
5387 MDIO_REG_BANK_SERDES_DIGITAL,
5388 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5390 CL22_RD_OVER_CL45(bp, phy,
5391 MDIO_REG_BANK_SERDES_DIGITAL,
5392 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5394 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5395 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5400 CL22_RD_OVER_CL45(bp, phy,
5401 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5402 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5405 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5406 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5413 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy,
5414 struct link_params *params,
5415 struct link_vars *vars,
5418 u16 ld_pause; /* local driver */
5419 u16 lp_pause; /* link partner */
5421 struct bnx2x *bp = params->bp;
5423 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5424 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5425 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5426 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5428 CL22_RD_OVER_CL45(bp, phy,
5429 MDIO_REG_BANK_CL73_IEEEB1,
5430 MDIO_CL73_IEEEB1_AN_ADV1,
5432 CL22_RD_OVER_CL45(bp, phy,
5433 MDIO_REG_BANK_CL73_IEEEB1,
5434 MDIO_CL73_IEEEB1_AN_LP_ADV1,
5436 pause_result = (ld_pause &
5437 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
5438 pause_result |= (lp_pause &
5439 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
5440 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result);
5442 CL22_RD_OVER_CL45(bp, phy,
5443 MDIO_REG_BANK_COMBO_IEEE0,
5444 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5446 CL22_RD_OVER_CL45(bp, phy,
5447 MDIO_REG_BANK_COMBO_IEEE0,
5448 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5450 pause_result = (ld_pause &
5451 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5452 pause_result |= (lp_pause &
5453 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5454 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result);
5456 bnx2x_pause_resolve(vars, pause_result);
5460 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5461 struct link_params *params,
5462 struct link_vars *vars,
5465 struct bnx2x *bp = params->bp;
5466 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5468 /* Resolve from gp_status in case of AN complete and not sgmii */
5469 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
5470 /* Update the advertised flow-controled of LD/LP in AN */
5471 if (phy->req_line_speed == SPEED_AUTO_NEG)
5472 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5473 /* But set the flow-control result as the requested one */
5474 vars->flow_ctrl = phy->req_flow_ctrl;
5475 } else if (phy->req_line_speed != SPEED_AUTO_NEG)
5476 vars->flow_ctrl = params->req_fc_auto_adv;
5477 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5478 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5479 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5480 vars->flow_ctrl = params->req_fc_auto_adv;
5483 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5485 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5488 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5489 struct link_params *params)
5491 struct bnx2x *bp = params->bp;
5492 u16 rx_status, ustat_val, cl37_fsm_received;
5493 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5494 /* Step 1: Make sure signal is detected */
5495 CL22_RD_OVER_CL45(bp, phy,
5499 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5500 (MDIO_RX0_RX_STATUS_SIGDET)) {
5501 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5502 "rx_status(0x80b0) = 0x%x\n", rx_status);
5503 CL22_WR_OVER_CL45(bp, phy,
5504 MDIO_REG_BANK_CL73_IEEEB0,
5505 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5506 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5509 /* Step 2: Check CL73 state machine */
5510 CL22_RD_OVER_CL45(bp, phy,
5511 MDIO_REG_BANK_CL73_USERB0,
5512 MDIO_CL73_USERB0_CL73_USTAT1,
5515 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5516 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5517 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5518 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5519 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5520 "ustat_val(0x8371) = 0x%x\n", ustat_val);
5523 /* Step 3: Check CL37 Message Pages received to indicate LP
5524 * supports only CL37
5526 CL22_RD_OVER_CL45(bp, phy,
5527 MDIO_REG_BANK_REMOTE_PHY,
5528 MDIO_REMOTE_PHY_MISC_RX_STATUS,
5529 &cl37_fsm_received);
5530 if ((cl37_fsm_received &
5531 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5532 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5533 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5534 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5535 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5536 "misc_rx_status(0x8330) = 0x%x\n",
5540 /* The combined cl37/cl73 fsm state information indicating that
5541 * we are connected to a device which does not support cl73, but
5542 * does support cl37 BAM. In this case we disable cl73 and
5543 * restart cl37 auto-neg
5547 CL22_WR_OVER_CL45(bp, phy,
5548 MDIO_REG_BANK_CL73_IEEEB0,
5549 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5551 /* Restart CL37 autoneg */
5552 bnx2x_restart_autoneg(phy, params, 0);
5553 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5556 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5557 struct link_params *params,
5558 struct link_vars *vars,
5561 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5562 vars->link_status |=
5563 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5565 if (bnx2x_direct_parallel_detect_used(phy, params))
5566 vars->link_status |=
5567 LINK_STATUS_PARALLEL_DETECTION_USED;
5569 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5570 struct link_params *params,
5571 struct link_vars *vars,
5576 struct bnx2x *bp = params->bp;
5577 if (phy->req_line_speed == SPEED_AUTO_NEG)
5578 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5580 DP(NETIF_MSG_LINK, "phy link up\n");
5582 vars->phy_link_up = 1;
5583 vars->link_status |= LINK_STATUS_LINK_UP;
5585 switch (speed_mask) {
5587 vars->line_speed = SPEED_10;
5588 if (vars->duplex == DUPLEX_FULL)
5589 vars->link_status |= LINK_10TFD;
5591 vars->link_status |= LINK_10THD;
5594 case GP_STATUS_100M:
5595 vars->line_speed = SPEED_100;
5596 if (vars->duplex == DUPLEX_FULL)
5597 vars->link_status |= LINK_100TXFD;
5599 vars->link_status |= LINK_100TXHD;
5603 case GP_STATUS_1G_KX:
5604 vars->line_speed = SPEED_1000;
5605 if (vars->duplex == DUPLEX_FULL)
5606 vars->link_status |= LINK_1000TFD;
5608 vars->link_status |= LINK_1000THD;
5611 case GP_STATUS_2_5G:
5612 vars->line_speed = SPEED_2500;
5613 if (vars->duplex == DUPLEX_FULL)
5614 vars->link_status |= LINK_2500TFD;
5616 vars->link_status |= LINK_2500THD;
5622 "link speed unsupported gp_status 0x%x\n",
5626 case GP_STATUS_10G_KX4:
5627 case GP_STATUS_10G_HIG:
5628 case GP_STATUS_10G_CX4:
5629 case GP_STATUS_10G_KR:
5630 case GP_STATUS_10G_SFI:
5631 case GP_STATUS_10G_XFI:
5632 vars->line_speed = SPEED_10000;
5633 vars->link_status |= LINK_10GTFD;
5635 case GP_STATUS_20G_DXGXS:
5636 vars->line_speed = SPEED_20000;
5637 vars->link_status |= LINK_20GTFD;
5641 "link speed unsupported gp_status 0x%x\n",
5645 } else { /* link_down */
5646 DP(NETIF_MSG_LINK, "phy link down\n");
5648 vars->phy_link_up = 0;
5650 vars->duplex = DUPLEX_FULL;
5651 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5652 vars->mac_type = MAC_TYPE_NONE;
5654 DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5655 vars->phy_link_up, vars->line_speed);
5659 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5660 struct link_params *params,
5661 struct link_vars *vars)
5663 struct bnx2x *bp = params->bp;
5665 u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5668 /* Read gp_status */
5669 CL22_RD_OVER_CL45(bp, phy,
5670 MDIO_REG_BANK_GP_STATUS,
5671 MDIO_GP_STATUS_TOP_AN_STATUS1,
5673 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5674 duplex = DUPLEX_FULL;
5675 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5677 speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5678 DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5679 gp_status, link_up, speed_mask);
5680 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5685 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5686 if (SINGLE_MEDIA_DIRECT(params)) {
5687 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5688 if (phy->req_line_speed == SPEED_AUTO_NEG)
5689 bnx2x_xgxs_an_resolve(phy, params, vars,
5692 } else { /* Link_down */
5693 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5694 SINGLE_MEDIA_DIRECT(params)) {
5695 /* Check signal is detected */
5696 bnx2x_check_fallback_to_cl37(phy, params);
5700 /* Read LP advertised speeds*/
5701 if (SINGLE_MEDIA_DIRECT(params) &&
5702 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
5705 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1,
5706 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
5708 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5709 vars->link_status |=
5710 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5711 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5712 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5713 vars->link_status |=
5714 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5716 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G,
5717 MDIO_OVER_1G_LP_UP1, &val);
5719 if (val & MDIO_OVER_1G_UP1_2_5G)
5720 vars->link_status |=
5721 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5722 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5723 vars->link_status |=
5724 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5727 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5728 vars->duplex, vars->flow_ctrl, vars->link_status);
5732 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5733 struct link_params *params,
5734 struct link_vars *vars)
5736 struct bnx2x *bp = params->bp;
5738 u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5740 lane = bnx2x_get_warpcore_lane(phy, params);
5741 /* Read gp_status */
5742 if (phy->req_line_speed > SPEED_10000) {
5744 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5746 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5748 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5749 temp_link_up, link_up);
5752 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5754 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5755 MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);
5756 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5757 /* Check for either KR or generic link up. */
5758 gp_status1 = ((gp_status1 >> 8) & 0xf) |
5759 ((gp_status1 >> 12) & 0xf);
5760 link_up = gp_status1 & (1 << lane);
5761 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5763 if (phy->req_line_speed == SPEED_AUTO_NEG) {
5764 /* Check Autoneg complete */
5765 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5766 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5768 if (gp_status4 & ((1<<12)<<lane))
5769 vars->link_status |=
5770 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5772 /* Check parallel detect used */
5773 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5774 MDIO_WC_REG_PAR_DET_10G_STATUS,
5777 vars->link_status |=
5778 LINK_STATUS_PARALLEL_DETECTION_USED;
5780 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5784 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
5785 SINGLE_MEDIA_DIRECT(params)) {
5788 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5789 MDIO_AN_REG_LP_AUTO_NEG2, &val);
5791 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5792 vars->link_status |=
5793 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5794 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5795 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5796 vars->link_status |=
5797 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5799 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5800 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
5802 if (val & MDIO_OVER_1G_UP1_2_5G)
5803 vars->link_status |=
5804 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5805 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5806 vars->link_status |=
5807 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5813 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5814 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5816 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5817 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5819 DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5821 if ((lane & 1) == 0)
5826 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5829 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5830 vars->duplex, vars->flow_ctrl, vars->link_status);
5833 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5835 struct bnx2x *bp = params->bp;
5836 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
5842 CL22_RD_OVER_CL45(bp, phy,
5843 MDIO_REG_BANK_OVER_1G,
5844 MDIO_OVER_1G_LP_UP2, &lp_up2);
5846 /* Bits [10:7] at lp_up2, positioned at [15:12] */
5847 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5848 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5849 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5854 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5855 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5856 CL22_RD_OVER_CL45(bp, phy,
5858 MDIO_TX0_TX_DRIVER, &tx_driver);
5860 /* Replace tx_driver bits [15:12] */
5862 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5863 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5864 tx_driver |= lp_up2;
5865 CL22_WR_OVER_CL45(bp, phy,
5867 MDIO_TX0_TX_DRIVER, tx_driver);
5872 static int bnx2x_emac_program(struct link_params *params,
5873 struct link_vars *vars)
5875 struct bnx2x *bp = params->bp;
5876 u8 port = params->port;
5879 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5880 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5882 (EMAC_MODE_25G_MODE |
5883 EMAC_MODE_PORT_MII_10M |
5884 EMAC_MODE_HALF_DUPLEX));
5885 switch (vars->line_speed) {
5887 mode |= EMAC_MODE_PORT_MII_10M;
5891 mode |= EMAC_MODE_PORT_MII;
5895 mode |= EMAC_MODE_PORT_GMII;
5899 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5903 /* 10G not valid for EMAC */
5904 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5909 if (vars->duplex == DUPLEX_HALF)
5910 mode |= EMAC_MODE_HALF_DUPLEX;
5912 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5915 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5919 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5920 struct link_params *params)
5924 struct bnx2x *bp = params->bp;
5926 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5927 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5928 CL22_WR_OVER_CL45(bp, phy,
5930 MDIO_RX0_RX_EQ_BOOST,
5931 phy->rx_preemphasis[i]);
5934 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5935 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5936 CL22_WR_OVER_CL45(bp, phy,
5939 phy->tx_preemphasis[i]);
5943 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5944 struct link_params *params,
5945 struct link_vars *vars)
5947 struct bnx2x *bp = params->bp;
5948 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5949 (params->loopback_mode == LOOPBACK_XGXS));
5950 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5951 if (SINGLE_MEDIA_DIRECT(params) &&
5952 (params->feature_config_flags &
5953 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5954 bnx2x_set_preemphasis(phy, params);
5956 /* Forced speed requested? */
5957 if (vars->line_speed != SPEED_AUTO_NEG ||
5958 (SINGLE_MEDIA_DIRECT(params) &&
5959 params->loopback_mode == LOOPBACK_EXT)) {
5960 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5962 /* Disable autoneg */
5963 bnx2x_set_autoneg(phy, params, vars, 0);
5965 /* Program speed and duplex */
5966 bnx2x_program_serdes(phy, params, vars);
5968 } else { /* AN_mode */
5969 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5972 bnx2x_set_brcm_cl37_advertisement(phy, params);
5974 /* Program duplex & pause advertisement (for aneg) */
5975 bnx2x_set_ieee_aneg_advertisement(phy, params,
5978 /* Enable autoneg */
5979 bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5981 /* Enable and restart AN */
5982 bnx2x_restart_autoneg(phy, params, enable_cl73);
5985 } else { /* SGMII mode */
5986 DP(NETIF_MSG_LINK, "SGMII\n");
5988 bnx2x_initialize_sgmii_process(phy, params, vars);
5992 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5993 struct link_params *params,
5994 struct link_vars *vars)
5997 vars->phy_flags |= PHY_XGXS_FLAG;
5998 if ((phy->req_line_speed &&
5999 ((phy->req_line_speed == SPEED_100) ||
6000 (phy->req_line_speed == SPEED_10))) ||
6001 (!phy->req_line_speed &&
6002 (phy->speed_cap_mask >=
6003 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
6004 (phy->speed_cap_mask <
6005 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
6006 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
6007 vars->phy_flags |= PHY_SGMII_FLAG;
6009 vars->phy_flags &= ~PHY_SGMII_FLAG;
6011 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6012 bnx2x_set_aer_mmd(params, phy);
6013 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
6014 bnx2x_set_master_ln(params, phy);
6016 rc = bnx2x_reset_unicore(params, phy, 0);
6017 /* Reset the SerDes and wait for reset bit return low */
6021 bnx2x_set_aer_mmd(params, phy);
6022 /* Setting the masterLn_def again after the reset */
6023 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
6024 bnx2x_set_master_ln(params, phy);
6025 bnx2x_set_swap_lanes(params, phy);
6031 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
6032 struct bnx2x_phy *phy,
6033 struct link_params *params)
6036 /* Wait for soft reset to get cleared up to 1 sec */
6037 for (cnt = 0; cnt < 1000; cnt++) {
6038 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6039 bnx2x_cl22_read(bp, phy,
6040 MDIO_PMA_REG_CTRL, &ctrl);
6042 bnx2x_cl45_read(bp, phy,
6044 MDIO_PMA_REG_CTRL, &ctrl);
6045 if (!(ctrl & (1<<15)))
6047 usleep_range(1000, 2000);
6051 netdev_err(bp->dev, "Warning: PHY was not initialized,"
6054 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
6058 static void bnx2x_link_int_enable(struct link_params *params)
6060 u8 port = params->port;
6062 struct bnx2x *bp = params->bp;
6064 /* Setting the status to report on link up for either XGXS or SerDes */
6065 if (CHIP_IS_E3(bp)) {
6066 mask = NIG_MASK_XGXS0_LINK_STATUS;
6067 if (!(SINGLE_MEDIA_DIRECT(params)))
6068 mask |= NIG_MASK_MI_INT;
6069 } else if (params->switch_cfg == SWITCH_CFG_10G) {
6070 mask = (NIG_MASK_XGXS0_LINK10G |
6071 NIG_MASK_XGXS0_LINK_STATUS);
6072 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
6073 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6074 params->phy[INT_PHY].type !=
6075 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
6076 mask |= NIG_MASK_MI_INT;
6077 DP(NETIF_MSG_LINK, "enabled external phy int\n");
6080 } else { /* SerDes */
6081 mask = NIG_MASK_SERDES0_LINK_STATUS;
6082 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
6083 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6084 params->phy[INT_PHY].type !=
6085 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
6086 mask |= NIG_MASK_MI_INT;
6087 DP(NETIF_MSG_LINK, "enabled external phy int\n");
6091 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6094 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
6095 (params->switch_cfg == SWITCH_CFG_10G),
6096 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6097 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
6098 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6099 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
6100 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
6101 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6102 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6103 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6106 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
6109 u32 latch_status = 0;
6111 /* Disable the MI INT ( external phy int ) by writing 1 to the
6112 * status register. Link down indication is high-active-signal,
6113 * so in this case we need to write the status to clear the XOR
6115 /* Read Latched signals */
6116 latch_status = REG_RD(bp,
6117 NIG_REG_LATCH_STATUS_0 + port*8);
6118 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
6119 /* Handle only those with latched-signal=up.*/
6122 NIG_REG_STATUS_INTERRUPT_PORT0
6124 NIG_STATUS_EMAC0_MI_INT);
6127 NIG_REG_STATUS_INTERRUPT_PORT0
6129 NIG_STATUS_EMAC0_MI_INT);
6131 if (latch_status & 1) {
6133 /* For all latched-signal=up : Re-Arm Latch signals */
6134 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
6135 (latch_status & 0xfffe) | (latch_status & 1));
6137 /* For all latched-signal=up,Write original_signal to status */
6140 static void bnx2x_link_int_ack(struct link_params *params,
6141 struct link_vars *vars, u8 is_10g_plus)
6143 struct bnx2x *bp = params->bp;
6144 u8 port = params->port;
6146 /* First reset all status we assume only one line will be
6149 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6150 (NIG_STATUS_XGXS0_LINK10G |
6151 NIG_STATUS_XGXS0_LINK_STATUS |
6152 NIG_STATUS_SERDES0_LINK_STATUS));
6153 if (vars->phy_link_up) {
6154 if (USES_WARPCORE(bp))
6155 mask = NIG_STATUS_XGXS0_LINK_STATUS;
6158 mask = NIG_STATUS_XGXS0_LINK10G;
6159 else if (params->switch_cfg == SWITCH_CFG_10G) {
6160 /* Disable the link interrupt by writing 1 to
6161 * the relevant lane in the status register
6164 ((params->lane_config &
6165 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6166 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
6167 mask = ((1 << ser_lane) <<
6168 NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
6170 mask = NIG_STATUS_SERDES0_LINK_STATUS;
6172 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
6175 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6180 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
6183 u32 mask = 0xf0000000;
6186 u8 remove_leading_zeros = 1;
6188 /* Need more than 10chars for this format */
6196 digit = ((num & mask) >> shift);
6197 if (digit == 0 && remove_leading_zeros) {
6200 } else if (digit < 0xa)
6201 *str_ptr = digit + '0';
6203 *str_ptr = digit - 0xa + 'a';
6204 remove_leading_zeros = 0;
6212 remove_leading_zeros = 1;
6219 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6226 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
6232 u8 *ver_p = version;
6233 u16 remain_len = len;
6234 if (version == NULL || params == NULL)
6238 /* Extract first external phy*/
6240 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
6242 if (params->phy[EXT_PHY1].format_fw_ver) {
6243 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
6246 ver_p += (len - remain_len);
6248 if ((params->num_phys == MAX_PHYS) &&
6249 (params->phy[EXT_PHY2].ver_addr != 0)) {
6250 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
6251 if (params->phy[EXT_PHY2].format_fw_ver) {
6255 status |= params->phy[EXT_PHY2].format_fw_ver(
6259 ver_p = version + (len - remain_len);
6266 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
6267 struct link_params *params)
6269 u8 port = params->port;
6270 struct bnx2x *bp = params->bp;
6272 if (phy->req_line_speed != SPEED_1000) {
6275 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
6277 if (!CHIP_IS_E3(bp)) {
6278 /* Change the uni_phy_addr in the nig */
6279 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
6282 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6286 bnx2x_cl45_write(bp, phy,
6288 (MDIO_REG_BANK_AER_BLOCK +
6289 (MDIO_AER_BLOCK_AER_REG & 0xf)),
6292 bnx2x_cl45_write(bp, phy,
6294 (MDIO_REG_BANK_CL73_IEEEB0 +
6295 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
6298 /* Set aer mmd back */
6299 bnx2x_set_aer_mmd(params, phy);
6301 if (!CHIP_IS_E3(bp)) {
6303 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6308 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
6309 bnx2x_cl45_read(bp, phy, 5,
6310 (MDIO_REG_BANK_COMBO_IEEE0 +
6311 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6313 bnx2x_cl45_write(bp, phy, 5,
6314 (MDIO_REG_BANK_COMBO_IEEE0 +
6315 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6317 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6321 int bnx2x_set_led(struct link_params *params,
6322 struct link_vars *vars, u8 mode, u32 speed)
6324 u8 port = params->port;
6325 u16 hw_led_mode = params->hw_led_mode;
6329 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6330 struct bnx2x *bp = params->bp;
6331 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
6332 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
6333 speed, hw_led_mode);
6335 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
6336 if (params->phy[phy_idx].set_link_led) {
6337 params->phy[phy_idx].set_link_led(
6338 ¶ms->phy[phy_idx], params, mode);
6343 case LED_MODE_FRONT_PANEL_OFF:
6345 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
6346 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6347 SHARED_HW_CFG_LED_MAC1);
6349 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6350 if (params->phy[EXT_PHY1].type ==
6351 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6352 tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
6353 EMAC_LED_100MB_OVERRIDE |
6354 EMAC_LED_10MB_OVERRIDE);
6356 tmp |= EMAC_LED_OVERRIDE;
6358 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp);
6362 /* For all other phys, OPER mode is same as ON, so in case
6363 * link is down, do nothing
6368 if (((params->phy[EXT_PHY1].type ==
6369 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6370 (params->phy[EXT_PHY1].type ==
6371 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6372 CHIP_IS_E2(bp) && params->num_phys == 2) {
6373 /* This is a work-around for E2+8727 Configurations */
6374 if (mode == LED_MODE_ON ||
6375 speed == SPEED_10000){
6376 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6377 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6379 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6380 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6381 (tmp | EMAC_LED_OVERRIDE));
6382 /* Return here without enabling traffic
6383 * LED blink and setting rate in ON mode.
6384 * In oper mode, enabling LED blink
6385 * and setting rate is needed.
6387 if (mode == LED_MODE_ON)
6390 } else if (SINGLE_MEDIA_DIRECT(params)) {
6391 /* This is a work-around for HW issue found when link
6394 if ((!CHIP_IS_E3(bp)) ||
6396 mode == LED_MODE_ON))
6397 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6399 if (CHIP_IS_E1x(bp) ||
6401 (mode == LED_MODE_ON))
6402 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6404 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6406 } else if ((params->phy[EXT_PHY1].type ==
6407 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6408 (mode == LED_MODE_ON)) {
6409 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6410 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6411 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp |
6412 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE);
6413 /* Break here; otherwise, it'll disable the
6414 * intended override.
6418 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6421 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
6422 /* Set blinking rate to ~15.9Hz */
6424 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6425 LED_BLINK_RATE_VAL_E3);
6427 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6428 LED_BLINK_RATE_VAL_E1X_E2);
6429 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
6431 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6432 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6433 (tmp & (~EMAC_LED_OVERRIDE)));
6435 if (CHIP_IS_E1(bp) &&
6436 ((speed == SPEED_2500) ||
6437 (speed == SPEED_1000) ||
6438 (speed == SPEED_100) ||
6439 (speed == SPEED_10))) {
6440 /* For speeds less than 10G LED scheme is different */
6441 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
6443 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
6445 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
6452 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
6460 /* This function comes to reflect the actual link state read DIRECTLY from the
6463 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
6466 struct bnx2x *bp = params->bp;
6467 u16 gp_status = 0, phy_index = 0;
6468 u8 ext_phy_link_up = 0, serdes_phy_type;
6469 struct link_vars temp_vars;
6470 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY];
6472 if (CHIP_IS_E3(bp)) {
6474 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6476 /* Check 20G link */
6477 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6479 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6483 /* Check 10G link and below*/
6484 u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6485 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6486 MDIO_WC_REG_GP2_STATUS_GP_2_1,
6488 gp_status = ((gp_status >> 8) & 0xf) |
6489 ((gp_status >> 12) & 0xf);
6490 link_up = gp_status & (1 << lane);
6495 CL22_RD_OVER_CL45(bp, int_phy,
6496 MDIO_REG_BANK_GP_STATUS,
6497 MDIO_GP_STATUS_TOP_AN_STATUS1,
6499 /* Link is up only if both local phy and external phy are up */
6500 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6503 /* In XGXS loopback mode, do not check external PHY */
6504 if (params->loopback_mode == LOOPBACK_XGXS)
6507 switch (params->num_phys) {
6509 /* No external PHY */
6512 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6513 ¶ms->phy[EXT_PHY1],
6514 params, &temp_vars);
6516 case 3: /* Dual Media */
6517 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6519 serdes_phy_type = ((params->phy[phy_index].media_type ==
6520 ETH_PHY_SFPP_10G_FIBER) ||
6521 (params->phy[phy_index].media_type ==
6522 ETH_PHY_SFP_1G_FIBER) ||
6523 (params->phy[phy_index].media_type ==
6524 ETH_PHY_XFP_FIBER) ||
6525 (params->phy[phy_index].media_type ==
6526 ETH_PHY_DA_TWINAX));
6528 if (is_serdes != serdes_phy_type)
6530 if (params->phy[phy_index].read_status) {
6532 params->phy[phy_index].read_status(
6533 ¶ms->phy[phy_index],
6534 params, &temp_vars);
6539 if (ext_phy_link_up)
6544 static int bnx2x_link_initialize(struct link_params *params,
6545 struct link_vars *vars)
6548 u8 phy_index, non_ext_phy;
6549 struct bnx2x *bp = params->bp;
6550 /* In case of external phy existence, the line speed would be the
6551 * line speed linked up by the external phy. In case it is direct
6552 * only, then the line_speed during initialization will be
6553 * equal to the req_line_speed
6555 vars->line_speed = params->phy[INT_PHY].req_line_speed;
6557 /* Initialize the internal phy in case this is a direct board
6558 * (no external phys), or this board has external phy which requires
6561 if (!USES_WARPCORE(bp))
6562 bnx2x_prepare_xgxs(¶ms->phy[INT_PHY], params, vars);
6563 /* init ext phy and enable link state int */
6564 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6565 (params->loopback_mode == LOOPBACK_XGXS));
6568 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6569 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6570 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
6571 if (vars->line_speed == SPEED_AUTO_NEG &&
6574 bnx2x_set_parallel_detection(phy, params);
6575 if (params->phy[INT_PHY].config_init)
6576 params->phy[INT_PHY].config_init(phy,
6581 /* Init external phy*/
6583 if (params->phy[INT_PHY].supported &
6585 vars->link_status |= LINK_STATUS_SERDES_LINK;
6587 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6589 /* No need to initialize second phy in case of first
6590 * phy only selection. In case of second phy, we do
6591 * need to initialize the first phy, since they are
6594 if (params->phy[phy_index].supported &
6596 vars->link_status |= LINK_STATUS_SERDES_LINK;
6598 if (phy_index == EXT_PHY2 &&
6599 (bnx2x_phy_selection(params) ==
6600 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6602 "Not initializing second phy\n");
6605 params->phy[phy_index].config_init(
6606 ¶ms->phy[phy_index],
6610 /* Reset the interrupt indication after phy was initialized */
6611 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6613 (NIG_STATUS_XGXS0_LINK10G |
6614 NIG_STATUS_XGXS0_LINK_STATUS |
6615 NIG_STATUS_SERDES0_LINK_STATUS |
6620 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6621 struct link_params *params)
6623 /* Reset the SerDes/XGXS */
6624 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6625 (0x1ff << (params->port*16)));
6628 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6629 struct link_params *params)
6631 struct bnx2x *bp = params->bp;
6635 gpio_port = BP_PATH(bp);
6637 gpio_port = params->port;
6638 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6639 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6641 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6642 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6644 DP(NETIF_MSG_LINK, "reset external PHY\n");
6647 static int bnx2x_update_link_down(struct link_params *params,
6648 struct link_vars *vars)
6650 struct bnx2x *bp = params->bp;
6651 u8 port = params->port;
6653 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6654 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6655 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6656 /* Indicate no mac active */
6657 vars->mac_type = MAC_TYPE_NONE;
6659 /* Update shared memory */
6660 vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK |
6661 LINK_STATUS_LINK_UP |
6662 LINK_STATUS_PHYSICAL_LINK_FLAG |
6663 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE |
6664 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK |
6665 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK |
6666 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK |
6667 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE |
6668 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE);
6669 vars->line_speed = 0;
6670 bnx2x_update_mng(params, vars->link_status);
6672 /* Activate nig drain */
6673 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6676 if (!CHIP_IS_E3(bp))
6677 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6679 usleep_range(10000, 20000);
6680 /* Reset BigMac/Xmac */
6681 if (CHIP_IS_E1x(bp) ||
6683 bnx2x_bmac_rx_disable(bp, params->port);
6684 REG_WR(bp, GRCBASE_MISC +
6685 MISC_REGISTERS_RESET_REG_2_CLEAR,
6686 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6688 if (CHIP_IS_E3(bp)) {
6689 /* Prevent LPI Generation by chip */
6690 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
6692 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
6694 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
6695 SHMEM_EEE_ACTIVE_BIT);
6697 bnx2x_update_mng_eee(params, vars->eee_status);
6698 bnx2x_xmac_disable(params);
6699 bnx2x_umac_disable(params);
6705 static int bnx2x_update_link_up(struct link_params *params,
6706 struct link_vars *vars,
6709 struct bnx2x *bp = params->bp;
6710 u8 phy_idx, port = params->port;
6713 vars->link_status |= (LINK_STATUS_LINK_UP |
6714 LINK_STATUS_PHYSICAL_LINK_FLAG);
6715 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6717 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6718 vars->link_status |=
6719 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6721 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6722 vars->link_status |=
6723 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6724 if (USES_WARPCORE(bp)) {
6726 if (bnx2x_xmac_enable(params, vars, 0) ==
6728 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6730 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6731 vars->link_status &= ~LINK_STATUS_LINK_UP;
6734 bnx2x_umac_enable(params, vars, 0);
6735 bnx2x_set_led(params, vars,
6736 LED_MODE_OPER, vars->line_speed);
6738 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
6739 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
6740 DP(NETIF_MSG_LINK, "Enabling LPI assertion\n");
6741 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
6742 (params->port << 2), 1);
6743 REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1);
6744 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 +
6745 (params->port << 2), 0xfc20);
6748 if ((CHIP_IS_E1x(bp) ||
6751 if (bnx2x_bmac_enable(params, vars, 0) ==
6753 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6755 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6756 vars->link_status &= ~LINK_STATUS_LINK_UP;
6759 bnx2x_set_led(params, vars,
6760 LED_MODE_OPER, SPEED_10000);
6762 rc = bnx2x_emac_program(params, vars);
6763 bnx2x_emac_enable(params, vars, 0);
6766 if ((vars->link_status &
6767 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6768 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6769 SINGLE_MEDIA_DIRECT(params))
6770 bnx2x_set_gmii_tx_driver(params);
6775 if (CHIP_IS_E1x(bp))
6776 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6780 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6782 /* Update shared memory */
6783 bnx2x_update_mng(params, vars->link_status);
6784 bnx2x_update_mng_eee(params, vars->eee_status);
6785 /* Check remote fault */
6786 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
6787 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
6788 bnx2x_check_half_open_conn(params, vars, 0);
6795 /* The bnx2x_link_update function should be called upon link
6797 * Link is considered up as follows:
6798 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6800 * - SINGLE_MEDIA - The link between the 577xx and the external
6801 * phy (XGXS) need to up as well as the external link of the
6803 * - DUAL_MEDIA - The link between the 577xx and the first
6804 * external phy needs to be up, and at least one of the 2
6805 * external phy link must be up.
6807 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6809 struct bnx2x *bp = params->bp;
6810 struct link_vars phy_vars[MAX_PHYS];
6811 u8 port = params->port;
6812 u8 link_10g_plus, phy_index;
6813 u8 ext_phy_link_up = 0, cur_link_up;
6816 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6817 u8 active_external_phy = INT_PHY;
6818 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6819 for (phy_index = INT_PHY; phy_index < params->num_phys;
6821 phy_vars[phy_index].flow_ctrl = 0;
6822 phy_vars[phy_index].link_status = 0;
6823 phy_vars[phy_index].line_speed = 0;
6824 phy_vars[phy_index].duplex = DUPLEX_FULL;
6825 phy_vars[phy_index].phy_link_up = 0;
6826 phy_vars[phy_index].link_up = 0;
6827 phy_vars[phy_index].fault_detected = 0;
6828 /* different consideration, since vars holds inner state */
6829 phy_vars[phy_index].eee_status = vars->eee_status;
6832 if (USES_WARPCORE(bp))
6833 bnx2x_set_aer_mmd(params, ¶ms->phy[INT_PHY]);
6835 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6836 port, (vars->phy_flags & PHY_XGXS_FLAG),
6837 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6839 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6841 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6842 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6844 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6846 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6847 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6848 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6851 if (!CHIP_IS_E3(bp))
6852 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6855 * Check external link change only for external phys, and apply
6856 * priority selection between them in case the link on both phys
6857 * is up. Note that instead of the common vars, a temporary
6858 * vars argument is used since each phy may have different link/
6859 * speed/duplex result
6861 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6863 struct bnx2x_phy *phy = ¶ms->phy[phy_index];
6864 if (!phy->read_status)
6866 /* Read link status and params of this ext phy */
6867 cur_link_up = phy->read_status(phy, params,
6868 &phy_vars[phy_index]);
6870 DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6873 DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6878 if (!ext_phy_link_up) {
6879 ext_phy_link_up = 1;
6880 active_external_phy = phy_index;
6882 switch (bnx2x_phy_selection(params)) {
6883 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6884 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6885 /* In this option, the first PHY makes sure to pass the
6886 * traffic through itself only.
6887 * Its not clear how to reset the link on the second phy
6889 active_external_phy = EXT_PHY1;
6891 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6892 /* In this option, the first PHY makes sure to pass the
6893 * traffic through the second PHY.
6895 active_external_phy = EXT_PHY2;
6898 /* Link indication on both PHYs with the following cases
6900 * - FIRST_PHY means that second phy wasn't initialized,
6901 * hence its link is expected to be down
6902 * - SECOND_PHY means that first phy should not be able
6903 * to link up by itself (using configuration)
6904 * - DEFAULT should be overriden during initialiazation
6906 DP(NETIF_MSG_LINK, "Invalid link indication"
6907 "mpc=0x%x. DISABLING LINK !!!\n",
6908 params->multi_phy_config);
6909 ext_phy_link_up = 0;
6914 prev_line_speed = vars->line_speed;
6916 * Read the status of the internal phy. In case of
6917 * DIRECT_SINGLE_MEDIA board, this link is the external link,
6918 * otherwise this is the link between the 577xx and the first
6921 if (params->phy[INT_PHY].read_status)
6922 params->phy[INT_PHY].read_status(
6923 ¶ms->phy[INT_PHY],
6925 /* The INT_PHY flow control reside in the vars. This include the
6926 * case where the speed or flow control are not set to AUTO.
6927 * Otherwise, the active external phy flow control result is set
6928 * to the vars. The ext_phy_line_speed is needed to check if the
6929 * speed is different between the internal phy and external phy.
6930 * This case may be result of intermediate link speed change.
6932 if (active_external_phy > INT_PHY) {
6933 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6934 /* Link speed is taken from the XGXS. AN and FC result from
6937 vars->link_status |= phy_vars[active_external_phy].link_status;
6939 /* if active_external_phy is first PHY and link is up - disable
6940 * disable TX on second external PHY
6942 if (active_external_phy == EXT_PHY1) {
6943 if (params->phy[EXT_PHY2].phy_specific_func) {
6945 "Disabling TX on EXT_PHY2\n");
6946 params->phy[EXT_PHY2].phy_specific_func(
6947 ¶ms->phy[EXT_PHY2],
6948 params, DISABLE_TX);
6952 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6953 vars->duplex = phy_vars[active_external_phy].duplex;
6954 if (params->phy[active_external_phy].supported &
6956 vars->link_status |= LINK_STATUS_SERDES_LINK;
6958 vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6960 vars->eee_status = phy_vars[active_external_phy].eee_status;
6962 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6963 active_external_phy);
6966 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6968 if (params->phy[phy_index].flags &
6969 FLAGS_REARM_LATCH_SIGNAL) {
6970 bnx2x_rearm_latch_signal(bp, port,
6972 active_external_phy);
6976 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6977 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6978 vars->link_status, ext_phy_line_speed);
6979 /* Upon link speed change set the NIG into drain mode. Comes to
6980 * deals with possible FIFO glitch due to clk change when speed
6981 * is decreased without link down indicator
6984 if (vars->phy_link_up) {
6985 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6986 (ext_phy_line_speed != vars->line_speed)) {
6987 DP(NETIF_MSG_LINK, "Internal link speed %d is"
6988 " different than the external"
6989 " link speed %d\n", vars->line_speed,
6990 ext_phy_line_speed);
6991 vars->phy_link_up = 0;
6992 } else if (prev_line_speed != vars->line_speed) {
6993 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6995 usleep_range(1000, 2000);
6999 /* Anything 10 and over uses the bmac */
7000 link_10g_plus = (vars->line_speed >= SPEED_10000);
7002 bnx2x_link_int_ack(params, vars, link_10g_plus);
7004 /* In case external phy link is up, and internal link is down
7005 * (not initialized yet probably after link initialization, it
7006 * needs to be initialized.
7007 * Note that after link down-up as result of cable plug, the xgxs
7008 * link would probably become up again without the need
7011 if (!(SINGLE_MEDIA_DIRECT(params))) {
7012 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
7013 " init_preceding = %d\n", ext_phy_link_up,
7015 params->phy[EXT_PHY1].flags &
7016 FLAGS_INIT_XGXS_FIRST);
7017 if (!(params->phy[EXT_PHY1].flags &
7018 FLAGS_INIT_XGXS_FIRST)
7019 && ext_phy_link_up && !vars->phy_link_up) {
7020 vars->line_speed = ext_phy_line_speed;
7021 if (vars->line_speed < SPEED_1000)
7022 vars->phy_flags |= PHY_SGMII_FLAG;
7024 vars->phy_flags &= ~PHY_SGMII_FLAG;
7026 if (params->phy[INT_PHY].config_init)
7027 params->phy[INT_PHY].config_init(
7028 ¶ms->phy[INT_PHY], params,
7032 /* Link is up only if both local phy and external phy (in case of
7033 * non-direct board) are up and no fault detected on active PHY.
7035 vars->link_up = (vars->phy_link_up &&
7037 SINGLE_MEDIA_DIRECT(params)) &&
7038 (phy_vars[active_external_phy].fault_detected == 0));
7040 /* Update the PFC configuration in case it was changed */
7041 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
7042 vars->link_status |= LINK_STATUS_PFC_ENABLED;
7044 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
7047 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
7049 rc = bnx2x_update_link_down(params, vars);
7051 /* Update MCP link status was changed */
7052 if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX)
7053 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
7058 /*****************************************************************************/
7059 /* External Phy section */
7060 /*****************************************************************************/
7061 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
7063 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7064 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
7065 usleep_range(1000, 2000);
7066 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7067 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
7070 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
7071 u32 spirom_ver, u32 ver_addr)
7073 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
7074 (u16)(spirom_ver>>16), (u16)spirom_ver, port);
7077 REG_WR(bp, ver_addr, spirom_ver);
7080 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
7081 struct bnx2x_phy *phy,
7084 u16 fw_ver1, fw_ver2;
7086 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7087 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7088 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7089 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
7090 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
7094 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
7095 struct bnx2x_phy *phy,
7096 struct link_vars *vars)
7099 bnx2x_cl45_read(bp, phy,
7101 MDIO_AN_REG_STATUS, &val);
7102 bnx2x_cl45_read(bp, phy,
7104 MDIO_AN_REG_STATUS, &val);
7106 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
7107 if ((val & (1<<0)) == 0)
7108 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
7111 /******************************************************************/
7112 /* common BCM8073/BCM8727 PHY SECTION */
7113 /******************************************************************/
7114 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
7115 struct link_params *params,
7116 struct link_vars *vars)
7118 struct bnx2x *bp = params->bp;
7119 if (phy->req_line_speed == SPEED_10 ||
7120 phy->req_line_speed == SPEED_100) {
7121 vars->flow_ctrl = phy->req_flow_ctrl;
7125 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
7126 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
7128 u16 ld_pause; /* local */
7129 u16 lp_pause; /* link partner */
7130 bnx2x_cl45_read(bp, phy,
7132 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
7134 bnx2x_cl45_read(bp, phy,
7136 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
7137 pause_result = (ld_pause &
7138 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
7139 pause_result |= (lp_pause &
7140 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
7142 bnx2x_pause_resolve(vars, pause_result);
7143 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
7147 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
7148 struct bnx2x_phy *phy,
7152 u16 fw_ver1, fw_msgout;
7155 /* Boot port from external ROM */
7157 bnx2x_cl45_write(bp, phy,
7159 MDIO_PMA_REG_GEN_CTRL,
7162 /* Ucode reboot and rst */
7163 bnx2x_cl45_write(bp, phy,
7165 MDIO_PMA_REG_GEN_CTRL,
7168 bnx2x_cl45_write(bp, phy,
7170 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
7172 /* Reset internal microprocessor */
7173 bnx2x_cl45_write(bp, phy,
7175 MDIO_PMA_REG_GEN_CTRL,
7176 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
7178 /* Release srst bit */
7179 bnx2x_cl45_write(bp, phy,
7181 MDIO_PMA_REG_GEN_CTRL,
7182 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
7184 /* Delay 100ms per the PHY specifications */
7187 /* 8073 sometimes taking longer to download */
7192 "bnx2x_8073_8727_external_rom_boot port %x:"
7193 "Download failed. fw version = 0x%x\n",
7199 bnx2x_cl45_read(bp, phy,
7201 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7202 bnx2x_cl45_read(bp, phy,
7204 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
7206 usleep_range(1000, 2000);
7207 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
7208 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
7209 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
7211 /* Clear ser_boot_ctl bit */
7212 bnx2x_cl45_write(bp, phy,
7214 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
7215 bnx2x_save_bcm_spirom_ver(bp, phy, port);
7218 "bnx2x_8073_8727_external_rom_boot port %x:"
7219 "Download complete. fw version = 0x%x\n",
7225 /******************************************************************/
7226 /* BCM8073 PHY SECTION */
7227 /******************************************************************/
7228 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
7230 /* This is only required for 8073A1, version 102 only */
7233 /* Read 8073 HW revision*/
7234 bnx2x_cl45_read(bp, phy,
7236 MDIO_PMA_REG_8073_CHIP_REV, &val);
7239 /* No need to workaround in 8073 A1 */
7243 bnx2x_cl45_read(bp, phy,
7245 MDIO_PMA_REG_ROM_VER2, &val);
7247 /* SNR should be applied only for version 0x102 */
7254 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
7256 u16 val, cnt, cnt1 ;
7258 bnx2x_cl45_read(bp, phy,
7260 MDIO_PMA_REG_8073_CHIP_REV, &val);
7263 /* No need to workaround in 8073 A1 */
7266 /* XAUI workaround in 8073 A0: */
7268 /* After loading the boot ROM and restarting Autoneg, poll
7272 for (cnt = 0; cnt < 1000; cnt++) {
7273 bnx2x_cl45_read(bp, phy,
7275 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7277 /* If bit [14] = 0 or bit [13] = 0, continue on with
7278 * system initialization (XAUI work-around not required, as
7279 * these bits indicate 2.5G or 1G link up).
7281 if (!(val & (1<<14)) || !(val & (1<<13))) {
7282 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
7284 } else if (!(val & (1<<15))) {
7285 DP(NETIF_MSG_LINK, "bit 15 went off\n");
7286 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7287 * MSB (bit15) goes to 1 (indicating that the XAUI
7288 * workaround has completed), then continue on with
7289 * system initialization.
7291 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
7292 bnx2x_cl45_read(bp, phy,
7294 MDIO_PMA_REG_8073_XAUI_WA, &val);
7295 if (val & (1<<15)) {
7297 "XAUI workaround has completed\n");
7300 usleep_range(3000, 6000);
7304 usleep_range(3000, 6000);
7306 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
7310 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
7312 /* Force KR or KX */
7313 bnx2x_cl45_write(bp, phy,
7314 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
7315 bnx2x_cl45_write(bp, phy,
7316 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
7317 bnx2x_cl45_write(bp, phy,
7318 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
7319 bnx2x_cl45_write(bp, phy,
7320 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
7323 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
7324 struct bnx2x_phy *phy,
7325 struct link_vars *vars)
7328 struct bnx2x *bp = params->bp;
7329 bnx2x_cl45_read(bp, phy,
7330 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
7332 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7333 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
7334 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
7335 if ((vars->ieee_fc &
7336 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7337 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7338 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
7340 if ((vars->ieee_fc &
7341 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7342 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7343 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
7345 if ((vars->ieee_fc &
7346 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7347 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7348 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7351 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
7353 bnx2x_cl45_write(bp, phy,
7354 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
7358 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
7359 struct link_params *params,
7360 struct link_vars *vars)
7362 struct bnx2x *bp = params->bp;
7365 DP(NETIF_MSG_LINK, "Init 8073\n");
7368 gpio_port = BP_PATH(bp);
7370 gpio_port = params->port;
7371 /* Restore normal power mode*/
7372 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7373 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7375 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7376 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7379 bnx2x_cl45_write(bp, phy,
7380 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
7381 bnx2x_cl45_write(bp, phy,
7382 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
7384 bnx2x_8073_set_pause_cl37(params, phy, vars);
7386 bnx2x_cl45_read(bp, phy,
7387 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
7389 bnx2x_cl45_read(bp, phy,
7390 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
7392 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
7394 /* Swap polarity if required - Must be done only in non-1G mode */
7395 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7396 /* Configure the 8073 to swap _P and _N of the KR lines */
7397 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
7398 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7399 bnx2x_cl45_read(bp, phy,
7401 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
7402 bnx2x_cl45_write(bp, phy,
7404 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7409 /* Enable CL37 BAM */
7410 if (REG_RD(bp, params->shmem_base +
7411 offsetof(struct shmem_region, dev_info.
7412 port_hw_config[params->port].default_cfg)) &
7413 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
7415 bnx2x_cl45_read(bp, phy,
7417 MDIO_AN_REG_8073_BAM, &val);
7418 bnx2x_cl45_write(bp, phy,
7420 MDIO_AN_REG_8073_BAM, val | 1);
7421 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
7423 if (params->loopback_mode == LOOPBACK_EXT) {
7424 bnx2x_807x_force_10G(bp, phy);
7425 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
7428 bnx2x_cl45_write(bp, phy,
7429 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
7431 if (phy->req_line_speed != SPEED_AUTO_NEG) {
7432 if (phy->req_line_speed == SPEED_10000) {
7434 } else if (phy->req_line_speed == SPEED_2500) {
7436 /* Note that 2.5G works only when used with 1G
7443 if (phy->speed_cap_mask &
7444 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7447 /* Note that 2.5G works only when used with 1G advertisement */
7448 if (phy->speed_cap_mask &
7449 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
7450 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7452 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
7455 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
7456 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
7458 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
7459 (phy->req_line_speed == SPEED_AUTO_NEG)) ||
7460 (phy->req_line_speed == SPEED_2500)) {
7462 /* Allow 2.5G for A1 and above */
7463 bnx2x_cl45_read(bp, phy,
7464 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
7466 DP(NETIF_MSG_LINK, "Add 2.5G\n");
7472 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
7476 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
7477 /* Add support for CL37 (passive mode) II */
7479 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
7480 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
7481 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
7484 /* Add support for CL37 (passive mode) III */
7485 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
7487 /* The SNR will improve about 2db by changing BW and FEE main
7488 * tap. Rest commands are executed after link is up
7489 * Change FFE main cursor to 5 in EDC register
7491 if (bnx2x_8073_is_snr_needed(bp, phy))
7492 bnx2x_cl45_write(bp, phy,
7493 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7496 /* Enable FEC (Forware Error Correction) Request in the AN */
7497 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7499 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7501 bnx2x_ext_phy_set_pause(params, phy, vars);
7503 /* Restart autoneg */
7505 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7506 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7507 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7511 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7512 struct link_params *params,
7513 struct link_vars *vars)
7515 struct bnx2x *bp = params->bp;
7518 u16 link_status = 0;
7519 u16 an1000_status = 0;
7521 bnx2x_cl45_read(bp, phy,
7522 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7524 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7526 /* Clear the interrupt LASI status register */
7527 bnx2x_cl45_read(bp, phy,
7528 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7529 bnx2x_cl45_read(bp, phy,
7530 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7531 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7533 bnx2x_cl45_read(bp, phy,
7534 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7536 /* Check the LASI */
7537 bnx2x_cl45_read(bp, phy,
7538 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7540 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7542 /* Check the link status */
7543 bnx2x_cl45_read(bp, phy,
7544 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7545 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7547 bnx2x_cl45_read(bp, phy,
7548 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7549 bnx2x_cl45_read(bp, phy,
7550 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7551 link_up = ((val1 & 4) == 4);
7552 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7555 ((phy->req_line_speed != SPEED_10000))) {
7556 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7559 bnx2x_cl45_read(bp, phy,
7560 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7561 bnx2x_cl45_read(bp, phy,
7562 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7564 /* Check the link status on 1.1.2 */
7565 bnx2x_cl45_read(bp, phy,
7566 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7567 bnx2x_cl45_read(bp, phy,
7568 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7569 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7570 "an_link_status=0x%x\n", val2, val1, an1000_status);
7572 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7573 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7574 /* The SNR will improve about 2dbby changing the BW and FEE main
7575 * tap. The 1st write to change FFE main tap is set before
7576 * restart AN. Change PLL Bandwidth in EDC register
7578 bnx2x_cl45_write(bp, phy,
7579 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7582 /* Change CDR Bandwidth in EDC register */
7583 bnx2x_cl45_write(bp, phy,
7584 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7587 bnx2x_cl45_read(bp, phy,
7588 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7591 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7592 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7594 vars->line_speed = SPEED_10000;
7595 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7597 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7599 vars->line_speed = SPEED_2500;
7600 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7602 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7604 vars->line_speed = SPEED_1000;
7605 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7609 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7614 /* Swap polarity if required */
7615 if (params->lane_config &
7616 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7617 /* Configure the 8073 to swap P and N of the KR lines */
7618 bnx2x_cl45_read(bp, phy,
7620 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7621 /* Set bit 3 to invert Rx in 1G mode and clear this bit
7622 * when it`s in 10G mode.
7624 if (vars->line_speed == SPEED_1000) {
7625 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7631 bnx2x_cl45_write(bp, phy,
7633 MDIO_XS_REG_8073_RX_CTRL_PCIE,
7636 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7637 bnx2x_8073_resolve_fc(phy, params, vars);
7638 vars->duplex = DUPLEX_FULL;
7641 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
7642 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
7643 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
7646 vars->link_status |=
7647 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7649 vars->link_status |=
7650 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7656 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7657 struct link_params *params)
7659 struct bnx2x *bp = params->bp;
7662 gpio_port = BP_PATH(bp);
7664 gpio_port = params->port;
7665 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7667 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7668 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7672 /******************************************************************/
7673 /* BCM8705 PHY SECTION */
7674 /******************************************************************/
7675 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7676 struct link_params *params,
7677 struct link_vars *vars)
7679 struct bnx2x *bp = params->bp;
7680 DP(NETIF_MSG_LINK, "init 8705\n");
7681 /* Restore normal power mode*/
7682 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7683 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7685 bnx2x_ext_phy_hw_reset(bp, params->port);
7686 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7687 bnx2x_wait_reset_complete(bp, phy, params);
7689 bnx2x_cl45_write(bp, phy,
7690 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7691 bnx2x_cl45_write(bp, phy,
7692 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7693 bnx2x_cl45_write(bp, phy,
7694 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7695 bnx2x_cl45_write(bp, phy,
7696 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7697 /* BCM8705 doesn't have microcode, hence the 0 */
7698 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7702 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7703 struct link_params *params,
7704 struct link_vars *vars)
7708 struct bnx2x *bp = params->bp;
7709 DP(NETIF_MSG_LINK, "read status 8705\n");
7710 bnx2x_cl45_read(bp, phy,
7711 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7712 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7714 bnx2x_cl45_read(bp, phy,
7715 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7716 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7718 bnx2x_cl45_read(bp, phy,
7719 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7721 bnx2x_cl45_read(bp, phy,
7722 MDIO_PMA_DEVAD, 0xc809, &val1);
7723 bnx2x_cl45_read(bp, phy,
7724 MDIO_PMA_DEVAD, 0xc809, &val1);
7726 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7727 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7729 vars->line_speed = SPEED_10000;
7730 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7735 /******************************************************************/
7736 /* SFP+ module Section */
7737 /******************************************************************/
7738 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7739 struct bnx2x_phy *phy,
7742 struct bnx2x *bp = params->bp;
7743 /* Disable transmitter only for bootcodes which can enable it afterwards
7747 if (params->feature_config_flags &
7748 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7749 DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7751 DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7755 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7756 bnx2x_cl45_write(bp, phy,
7758 MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7761 static u8 bnx2x_get_gpio_port(struct link_params *params)
7764 u32 swap_val, swap_override;
7765 struct bnx2x *bp = params->bp;
7767 gpio_port = BP_PATH(bp);
7769 gpio_port = params->port;
7770 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7771 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7772 return gpio_port ^ (swap_val && swap_override);
7775 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7776 struct bnx2x_phy *phy,
7780 u8 port = params->port;
7781 struct bnx2x *bp = params->bp;
7784 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7785 tx_en_mode = REG_RD(bp, params->shmem_base +
7786 offsetof(struct shmem_region,
7787 dev_info.port_hw_config[port].sfp_ctrl)) &
7788 PORT_HW_CFG_TX_LASER_MASK;
7789 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7790 "mode = %x\n", tx_en, port, tx_en_mode);
7791 switch (tx_en_mode) {
7792 case PORT_HW_CFG_TX_LASER_MDIO:
7794 bnx2x_cl45_read(bp, phy,
7796 MDIO_PMA_REG_PHY_IDENTIFIER,
7804 bnx2x_cl45_write(bp, phy,
7806 MDIO_PMA_REG_PHY_IDENTIFIER,
7809 case PORT_HW_CFG_TX_LASER_GPIO0:
7810 case PORT_HW_CFG_TX_LASER_GPIO1:
7811 case PORT_HW_CFG_TX_LASER_GPIO2:
7812 case PORT_HW_CFG_TX_LASER_GPIO3:
7815 u8 gpio_port, gpio_mode;
7817 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7819 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7821 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7822 gpio_port = bnx2x_get_gpio_port(params);
7823 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7827 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7832 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7833 struct bnx2x_phy *phy,
7836 struct bnx2x *bp = params->bp;
7837 DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7839 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7841 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7844 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7845 struct link_params *params,
7846 u16 addr, u8 byte_cnt, u8 *o_buf)
7848 struct bnx2x *bp = params->bp;
7851 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7853 "Reading from eeprom is limited to 0xf\n");
7856 /* Set the read command byte count */
7857 bnx2x_cl45_write(bp, phy,
7858 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7859 (byte_cnt | 0xa000));
7861 /* Set the read command address */
7862 bnx2x_cl45_write(bp, phy,
7863 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7866 /* Activate read command */
7867 bnx2x_cl45_write(bp, phy,
7868 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7871 /* Wait up to 500us for command complete status */
7872 for (i = 0; i < 100; i++) {
7873 bnx2x_cl45_read(bp, phy,
7875 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7876 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7877 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7882 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7883 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7885 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7886 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7890 /* Read the buffer */
7891 for (i = 0; i < byte_cnt; i++) {
7892 bnx2x_cl45_read(bp, phy,
7894 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7895 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7898 for (i = 0; i < 100; i++) {
7899 bnx2x_cl45_read(bp, phy,
7901 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7902 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7903 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7905 usleep_range(1000, 2000);
7910 static void bnx2x_warpcore_power_module(struct link_params *params,
7911 struct bnx2x_phy *phy,
7915 struct bnx2x *bp = params->bp;
7917 pin_cfg = (REG_RD(bp, params->shmem_base +
7918 offsetof(struct shmem_region,
7919 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7920 PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7921 PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7923 if (pin_cfg == PIN_CFG_NA)
7925 DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
7927 /* Low ==> corresponding SFP+ module is powered
7928 * high ==> the SFP+ module is powered down
7930 bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
7932 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7933 struct link_params *params,
7934 u16 addr, u8 byte_cnt,
7938 u8 i, j = 0, cnt = 0;
7941 struct bnx2x *bp = params->bp;
7943 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7945 "Reading from eeprom is limited to 16 bytes\n");
7949 /* 4 byte aligned address */
7950 addr32 = addr & (~0x3);
7952 if (cnt == I2C_WA_PWR_ITER) {
7953 bnx2x_warpcore_power_module(params, phy, 0);
7954 /* Note that 100us are not enough here */
7955 usleep_range(1000,1000);
7956 bnx2x_warpcore_power_module(params, phy, 1);
7958 rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt,
7960 } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7963 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7964 o_buf[j] = *((u8 *)data_array + i);
7972 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7973 struct link_params *params,
7974 u16 addr, u8 byte_cnt, u8 *o_buf)
7976 struct bnx2x *bp = params->bp;
7979 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7981 "Reading from eeprom is limited to 0xf\n");
7985 /* Need to read from 1.8000 to clear it */
7986 bnx2x_cl45_read(bp, phy,
7988 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7991 /* Set the read command byte count */
7992 bnx2x_cl45_write(bp, phy,
7994 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7995 ((byte_cnt < 2) ? 2 : byte_cnt));
7997 /* Set the read command address */
7998 bnx2x_cl45_write(bp, phy,
8000 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
8002 /* Set the destination address */
8003 bnx2x_cl45_write(bp, phy,
8006 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
8008 /* Activate read command */
8009 bnx2x_cl45_write(bp, phy,
8011 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
8013 /* Wait appropriate time for two-wire command to finish before
8014 * polling the status register
8016 usleep_range(1000, 2000);
8018 /* Wait up to 500us for command complete status */
8019 for (i = 0; i < 100; i++) {
8020 bnx2x_cl45_read(bp, phy,
8022 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8023 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8024 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
8029 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
8030 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
8032 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
8033 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
8037 /* Read the buffer */
8038 for (i = 0; i < byte_cnt; i++) {
8039 bnx2x_cl45_read(bp, phy,
8041 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
8042 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
8045 for (i = 0; i < 100; i++) {
8046 bnx2x_cl45_read(bp, phy,
8048 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8049 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8050 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
8052 usleep_range(1000, 2000);
8058 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
8059 struct link_params *params, u16 addr,
8060 u8 byte_cnt, u8 *o_buf)
8062 int rc = -EOPNOTSUPP;
8063 switch (phy->type) {
8064 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8065 rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
8068 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8069 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8070 rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
8073 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8074 rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr,
8081 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
8082 struct link_params *params,
8085 struct bnx2x *bp = params->bp;
8086 u32 sync_offset = 0, phy_idx, media_types;
8087 u8 val[2], check_limiting_mode = 0;
8088 *edc_mode = EDC_MODE_LIMITING;
8090 phy->media_type = ETH_PHY_UNSPECIFIED;
8091 /* First check for copper cable */
8092 if (bnx2x_read_sfp_module_eeprom(phy,
8094 SFP_EEPROM_CON_TYPE_ADDR,
8097 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
8102 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
8104 u8 copper_module_type;
8105 phy->media_type = ETH_PHY_DA_TWINAX;
8106 /* Check if its active cable (includes SFP+ module)
8109 if (bnx2x_read_sfp_module_eeprom(phy,
8111 SFP_EEPROM_FC_TX_TECH_ADDR,
8113 &copper_module_type) != 0) {
8115 "Failed to read copper-cable-type"
8116 " from SFP+ EEPROM\n");
8120 if (copper_module_type &
8121 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
8122 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
8123 check_limiting_mode = 1;
8124 } else if (copper_module_type &
8125 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
8127 "Passive Copper cable detected\n");
8129 EDC_MODE_PASSIVE_DAC;
8132 "Unknown copper-cable-type 0x%x !!!\n",
8133 copper_module_type);
8138 case SFP_EEPROM_CON_TYPE_VAL_LC:
8139 check_limiting_mode = 1;
8140 if ((val[1] & (SFP_EEPROM_COMP_CODE_SR_MASK |
8141 SFP_EEPROM_COMP_CODE_LR_MASK |
8142 SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) {
8143 DP(NETIF_MSG_LINK, "1G Optic module detected\n");
8144 phy->media_type = ETH_PHY_SFP_1G_FIBER;
8145 phy->req_line_speed = SPEED_1000;
8147 int idx, cfg_idx = 0;
8148 DP(NETIF_MSG_LINK, "10G Optic module detected\n");
8149 for (idx = INT_PHY; idx < MAX_PHYS; idx++) {
8150 if (params->phy[idx].type == phy->type) {
8151 cfg_idx = LINK_CONFIG_IDX(idx);
8155 phy->media_type = ETH_PHY_SFPP_10G_FIBER;
8156 phy->req_line_speed = params->req_line_speed[cfg_idx];
8160 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
8164 sync_offset = params->shmem_base +
8165 offsetof(struct shmem_region,
8166 dev_info.port_hw_config[params->port].media_type);
8167 media_types = REG_RD(bp, sync_offset);
8168 /* Update media type for non-PMF sync */
8169 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
8170 if (&(params->phy[phy_idx]) == phy) {
8171 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
8172 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8173 media_types |= ((phy->media_type &
8174 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
8175 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8179 REG_WR(bp, sync_offset, media_types);
8180 if (check_limiting_mode) {
8181 u8 options[SFP_EEPROM_OPTIONS_SIZE];
8182 if (bnx2x_read_sfp_module_eeprom(phy,
8184 SFP_EEPROM_OPTIONS_ADDR,
8185 SFP_EEPROM_OPTIONS_SIZE,
8188 "Failed to read Option field from module EEPROM\n");
8191 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
8192 *edc_mode = EDC_MODE_LINEAR;
8194 *edc_mode = EDC_MODE_LIMITING;
8196 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
8199 /* This function read the relevant field from the module (SFP+), and verify it
8200 * is compliant with this board
8202 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
8203 struct link_params *params)
8205 struct bnx2x *bp = params->bp;
8207 u32 fw_resp, fw_cmd_param;
8208 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
8209 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
8210 phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
8211 val = REG_RD(bp, params->shmem_base +
8212 offsetof(struct shmem_region, dev_info.
8213 port_feature_config[params->port].config));
8214 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8215 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
8216 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
8220 if (params->feature_config_flags &
8221 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
8222 /* Use specific phy request */
8223 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
8224 } else if (params->feature_config_flags &
8225 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
8226 /* Use first phy request only in case of non-dual media*/
8227 if (DUAL_MEDIA(params)) {
8229 "FW does not support OPT MDL verification\n");
8232 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
8234 /* No support in OPT MDL detection */
8236 "FW does not support OPT MDL verification\n");
8240 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
8241 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
8242 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
8243 DP(NETIF_MSG_LINK, "Approved module\n");
8247 /* Format the warning message */
8248 if (bnx2x_read_sfp_module_eeprom(phy,
8250 SFP_EEPROM_VENDOR_NAME_ADDR,
8251 SFP_EEPROM_VENDOR_NAME_SIZE,
8253 vendor_name[0] = '\0';
8255 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
8256 if (bnx2x_read_sfp_module_eeprom(phy,
8258 SFP_EEPROM_PART_NO_ADDR,
8259 SFP_EEPROM_PART_NO_SIZE,
8261 vendor_pn[0] = '\0';
8263 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
8265 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected,"
8266 " Port %d from %s part number %s\n",
8267 params->port, vendor_name, vendor_pn);
8268 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8269 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
8270 phy->flags |= FLAGS_SFP_NOT_APPROVED;
8274 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
8275 struct link_params *params)
8279 struct bnx2x *bp = params->bp;
8281 /* Initialization time after hot-plug may take up to 300ms for
8282 * some phys type ( e.g. JDSU )
8285 for (timeout = 0; timeout < 60; timeout++) {
8286 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
8289 "SFP+ module initialization took %d ms\n",
8293 usleep_range(5000, 10000);
8298 static void bnx2x_8727_power_module(struct bnx2x *bp,
8299 struct bnx2x_phy *phy,
8301 /* Make sure GPIOs are not using for LED mode */
8303 /* In the GPIO register, bit 4 is use to determine if the GPIOs are
8304 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
8306 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
8307 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
8308 * where the 1st bit is the over-current(only input), and 2nd bit is
8309 * for power( only output )
8311 * In case of NOC feature is disabled and power is up, set GPIO control
8312 * as input to enable listening of over-current indication
8314 if (phy->flags & FLAGS_NOC)
8319 /* Set GPIO control to OUTPUT, and set the power bit
8320 * to according to the is_power_up
8324 bnx2x_cl45_write(bp, phy,
8326 MDIO_PMA_REG_8727_GPIO_CTRL,
8330 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
8331 struct bnx2x_phy *phy,
8334 u16 cur_limiting_mode;
8336 bnx2x_cl45_read(bp, phy,
8338 MDIO_PMA_REG_ROM_VER2,
8339 &cur_limiting_mode);
8340 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
8343 if (edc_mode == EDC_MODE_LIMITING) {
8344 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
8345 bnx2x_cl45_write(bp, phy,
8347 MDIO_PMA_REG_ROM_VER2,
8349 } else { /* LRM mode ( default )*/
8351 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
8353 /* Changing to LRM mode takes quite few seconds. So do it only
8354 * if current mode is limiting (default is LRM)
8356 if (cur_limiting_mode != EDC_MODE_LIMITING)
8359 bnx2x_cl45_write(bp, phy,
8361 MDIO_PMA_REG_LRM_MODE,
8363 bnx2x_cl45_write(bp, phy,
8365 MDIO_PMA_REG_ROM_VER2,
8367 bnx2x_cl45_write(bp, phy,
8369 MDIO_PMA_REG_MISC_CTRL0,
8371 bnx2x_cl45_write(bp, phy,
8373 MDIO_PMA_REG_LRM_MODE,
8379 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
8380 struct bnx2x_phy *phy,
8385 bnx2x_cl45_read(bp, phy,
8387 MDIO_PMA_REG_PHY_IDENTIFIER,
8390 bnx2x_cl45_write(bp, phy,
8392 MDIO_PMA_REG_PHY_IDENTIFIER,
8393 (phy_identifier & ~(1<<9)));
8395 bnx2x_cl45_read(bp, phy,
8397 MDIO_PMA_REG_ROM_VER2,
8399 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8400 bnx2x_cl45_write(bp, phy,
8402 MDIO_PMA_REG_ROM_VER2,
8403 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
8405 bnx2x_cl45_write(bp, phy,
8407 MDIO_PMA_REG_PHY_IDENTIFIER,
8408 (phy_identifier | (1<<9)));
8413 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
8414 struct link_params *params,
8417 struct bnx2x *bp = params->bp;
8421 bnx2x_sfp_set_transmitter(params, phy, 0);
8424 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
8425 bnx2x_sfp_set_transmitter(params, phy, 1);
8428 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
8434 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
8437 struct bnx2x *bp = params->bp;
8439 u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
8440 offsetof(struct shmem_region,
8441 dev_info.port_hw_config[params->port].sfp_ctrl)) &
8442 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8443 switch (fault_led_gpio) {
8444 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
8446 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
8447 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
8448 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
8449 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
8451 u8 gpio_port = bnx2x_get_gpio_port(params);
8452 u16 gpio_pin = fault_led_gpio -
8453 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8454 DP(NETIF_MSG_LINK, "Set fault module-detected led "
8455 "pin %x port %x mode %x\n",
8456 gpio_pin, gpio_port, gpio_mode);
8457 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
8461 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
8466 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
8470 u8 port = params->port;
8471 struct bnx2x *bp = params->bp;
8472 pin_cfg = (REG_RD(bp, params->shmem_base +
8473 offsetof(struct shmem_region,
8474 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
8475 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8476 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8477 DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
8478 gpio_mode, pin_cfg);
8479 bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
8482 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
8485 struct bnx2x *bp = params->bp;
8486 DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
8487 if (CHIP_IS_E3(bp)) {
8488 /* Low ==> if SFP+ module is supported otherwise
8489 * High ==> if SFP+ module is not on the approved vendor list
8491 bnx2x_set_e3_module_fault_led(params, gpio_mode);
8493 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
8496 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
8497 struct link_params *params)
8499 struct bnx2x *bp = params->bp;
8500 bnx2x_warpcore_power_module(params, phy, 0);
8501 /* Put Warpcore in low power mode */
8502 REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e);
8504 /* Put LCPLL in low power mode */
8505 REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1);
8506 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8507 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
8510 static void bnx2x_power_sfp_module(struct link_params *params,
8511 struct bnx2x_phy *phy,
8514 struct bnx2x *bp = params->bp;
8515 DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
8517 switch (phy->type) {
8518 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8519 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8520 bnx2x_8727_power_module(params->bp, phy, power);
8522 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8523 bnx2x_warpcore_power_module(params, phy, power);
8529 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8530 struct bnx2x_phy *phy,
8534 u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8535 struct bnx2x *bp = params->bp;
8537 u8 lane = bnx2x_get_warpcore_lane(phy, params);
8538 /* This is a global register which controls all lanes */
8539 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8540 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8541 val &= ~(0xf << (lane << 2));
8544 case EDC_MODE_LINEAR:
8545 case EDC_MODE_LIMITING:
8546 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8548 case EDC_MODE_PASSIVE_DAC:
8549 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8555 val |= (mode << (lane << 2));
8556 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8557 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8559 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8560 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8562 /* Restart microcode to re-read the new mode */
8563 bnx2x_warpcore_reset_lane(bp, phy, 1);
8564 bnx2x_warpcore_reset_lane(bp, phy, 0);
8568 static void bnx2x_set_limiting_mode(struct link_params *params,
8569 struct bnx2x_phy *phy,
8572 switch (phy->type) {
8573 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8574 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8576 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8577 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8578 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8580 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8581 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8586 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8587 struct link_params *params)
8589 struct bnx2x *bp = params->bp;
8593 u32 val = REG_RD(bp, params->shmem_base +
8594 offsetof(struct shmem_region, dev_info.
8595 port_feature_config[params->port].config));
8597 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8599 /* Power up module */
8600 bnx2x_power_sfp_module(params, phy, 1);
8601 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8602 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8604 } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8605 /* Check SFP+ module compatibility */
8606 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8608 /* Turn on fault module-detected led */
8609 bnx2x_set_sfp_module_fault_led(params,
8610 MISC_REGISTERS_GPIO_HIGH);
8612 /* Check if need to power down the SFP+ module */
8613 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8614 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8615 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8616 bnx2x_power_sfp_module(params, phy, 0);
8620 /* Turn off fault module-detected led */
8621 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8624 /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8625 * is done automatically
8627 bnx2x_set_limiting_mode(params, phy, edc_mode);
8629 /* Enable transmit for this module if the module is approved, or
8630 * if unapproved modules should also enable the Tx laser
8633 (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8634 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8635 bnx2x_sfp_set_transmitter(params, phy, 1);
8637 bnx2x_sfp_set_transmitter(params, phy, 0);
8642 void bnx2x_handle_module_detect_int(struct link_params *params)
8644 struct bnx2x *bp = params->bp;
8645 struct bnx2x_phy *phy;
8647 u8 gpio_num, gpio_port;
8649 phy = ¶ms->phy[INT_PHY];
8651 phy = ¶ms->phy[EXT_PHY1];
8653 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8654 params->port, &gpio_num, &gpio_port) ==
8656 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8660 /* Set valid module led off */
8661 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8663 /* Get current gpio val reflecting module plugged in / out*/
8664 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8666 /* Call the handling function in case module is detected */
8667 if (gpio_val == 0) {
8668 bnx2x_set_mdio_clk(bp, params->chip_id, params->port);
8669 bnx2x_set_aer_mmd(params, phy);
8671 bnx2x_power_sfp_module(params, phy, 1);
8672 bnx2x_set_gpio_int(bp, gpio_num,
8673 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8675 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) {
8676 bnx2x_sfp_module_detection(phy, params);
8677 if (CHIP_IS_E3(bp)) {
8679 /* In case WC is out of reset, reconfigure the
8680 * link speed while taking into account 1G
8681 * module limitation.
8683 bnx2x_cl45_read(bp, phy,
8685 MDIO_WC_REG_DIGITAL5_MISC6,
8687 if (!rx_tx_in_reset) {
8688 bnx2x_warpcore_reset_lane(bp, phy, 1);
8689 bnx2x_warpcore_config_sfi(phy, params);
8690 bnx2x_warpcore_reset_lane(bp, phy, 0);
8694 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8697 u32 val = REG_RD(bp, params->shmem_base +
8698 offsetof(struct shmem_region, dev_info.
8699 port_feature_config[params->port].
8701 bnx2x_set_gpio_int(bp, gpio_num,
8702 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8704 /* Module was plugged out.
8705 * Disable transmit for this module
8707 phy->media_type = ETH_PHY_NOT_PRESENT;
8708 if (((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8709 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) ||
8711 bnx2x_sfp_set_transmitter(params, phy, 0);
8715 /******************************************************************/
8716 /* Used by 8706 and 8727 */
8717 /******************************************************************/
8718 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8719 struct bnx2x_phy *phy,
8720 u16 alarm_status_offset,
8721 u16 alarm_ctrl_offset)
8723 u16 alarm_status, val;
8724 bnx2x_cl45_read(bp, phy,
8725 MDIO_PMA_DEVAD, alarm_status_offset,
8727 bnx2x_cl45_read(bp, phy,
8728 MDIO_PMA_DEVAD, alarm_status_offset,
8730 /* Mask or enable the fault event. */
8731 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8732 if (alarm_status & (1<<0))
8736 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8738 /******************************************************************/
8739 /* common BCM8706/BCM8726 PHY SECTION */
8740 /******************************************************************/
8741 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8742 struct link_params *params,
8743 struct link_vars *vars)
8746 u16 val1, val2, rx_sd, pcs_status;
8747 struct bnx2x *bp = params->bp;
8748 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8750 bnx2x_cl45_read(bp, phy,
8751 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8753 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8754 MDIO_PMA_LASI_TXCTRL);
8756 /* Clear LASI indication*/
8757 bnx2x_cl45_read(bp, phy,
8758 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8759 bnx2x_cl45_read(bp, phy,
8760 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8761 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8763 bnx2x_cl45_read(bp, phy,
8764 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8765 bnx2x_cl45_read(bp, phy,
8766 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8767 bnx2x_cl45_read(bp, phy,
8768 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8769 bnx2x_cl45_read(bp, phy,
8770 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8772 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8773 " link_status 0x%x\n", rx_sd, pcs_status, val2);
8774 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8775 * are set, or if the autoneg bit 1 is set
8777 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8780 vars->line_speed = SPEED_1000;
8782 vars->line_speed = SPEED_10000;
8783 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8784 vars->duplex = DUPLEX_FULL;
8787 /* Capture 10G link fault. Read twice to clear stale value. */
8788 if (vars->line_speed == SPEED_10000) {
8789 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8790 MDIO_PMA_LASI_TXSTAT, &val1);
8791 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8792 MDIO_PMA_LASI_TXSTAT, &val1);
8794 vars->fault_detected = 1;
8800 /******************************************************************/
8801 /* BCM8706 PHY SECTION */
8802 /******************************************************************/
8803 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8804 struct link_params *params,
8805 struct link_vars *vars)
8809 struct bnx2x *bp = params->bp;
8811 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8812 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8814 bnx2x_ext_phy_hw_reset(bp, params->port);
8815 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8816 bnx2x_wait_reset_complete(bp, phy, params);
8818 /* Wait until fw is loaded */
8819 for (cnt = 0; cnt < 100; cnt++) {
8820 bnx2x_cl45_read(bp, phy,
8821 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8824 usleep_range(10000, 20000);
8826 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8827 if ((params->feature_config_flags &
8828 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8831 for (i = 0; i < 4; i++) {
8832 reg = MDIO_XS_8706_REG_BANK_RX0 +
8833 i*(MDIO_XS_8706_REG_BANK_RX1 -
8834 MDIO_XS_8706_REG_BANK_RX0);
8835 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8836 /* Clear first 3 bits of the control */
8838 /* Set control bits according to configuration */
8839 val |= (phy->rx_preemphasis[i] & 0x7);
8840 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8841 " reg 0x%x <-- val 0x%x\n", reg, val);
8842 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8846 if (phy->req_line_speed == SPEED_10000) {
8847 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8849 bnx2x_cl45_write(bp, phy,
8851 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8852 bnx2x_cl45_write(bp, phy,
8853 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8855 /* Arm LASI for link and Tx fault. */
8856 bnx2x_cl45_write(bp, phy,
8857 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8859 /* Force 1Gbps using autoneg with 1G advertisement */
8861 /* Allow CL37 through CL73 */
8862 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8863 bnx2x_cl45_write(bp, phy,
8864 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8866 /* Enable Full-Duplex advertisement on CL37 */
8867 bnx2x_cl45_write(bp, phy,
8868 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8869 /* Enable CL37 AN */
8870 bnx2x_cl45_write(bp, phy,
8871 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8873 bnx2x_cl45_write(bp, phy,
8874 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8876 /* Enable clause 73 AN */
8877 bnx2x_cl45_write(bp, phy,
8878 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8879 bnx2x_cl45_write(bp, phy,
8880 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8882 bnx2x_cl45_write(bp, phy,
8883 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8886 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8888 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8889 * power mode, if TX Laser is disabled
8892 tx_en_mode = REG_RD(bp, params->shmem_base +
8893 offsetof(struct shmem_region,
8894 dev_info.port_hw_config[params->port].sfp_ctrl))
8895 & PORT_HW_CFG_TX_LASER_MASK;
8897 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8898 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8899 bnx2x_cl45_read(bp, phy,
8900 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8902 bnx2x_cl45_write(bp, phy,
8903 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8909 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8910 struct link_params *params,
8911 struct link_vars *vars)
8913 return bnx2x_8706_8726_read_status(phy, params, vars);
8916 /******************************************************************/
8917 /* BCM8726 PHY SECTION */
8918 /******************************************************************/
8919 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8920 struct link_params *params)
8922 struct bnx2x *bp = params->bp;
8923 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8924 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8927 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8928 struct link_params *params)
8930 struct bnx2x *bp = params->bp;
8931 /* Need to wait 100ms after reset */
8934 /* Micro controller re-boot */
8935 bnx2x_cl45_write(bp, phy,
8936 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8938 /* Set soft reset */
8939 bnx2x_cl45_write(bp, phy,
8941 MDIO_PMA_REG_GEN_CTRL,
8942 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8944 bnx2x_cl45_write(bp, phy,
8946 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8948 bnx2x_cl45_write(bp, phy,
8950 MDIO_PMA_REG_GEN_CTRL,
8951 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8953 /* Wait for 150ms for microcode load */
8956 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8957 bnx2x_cl45_write(bp, phy,
8959 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8962 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8965 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
8966 struct link_params *params,
8967 struct link_vars *vars)
8969 struct bnx2x *bp = params->bp;
8971 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
8973 bnx2x_cl45_read(bp, phy,
8974 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8976 if (val1 & (1<<15)) {
8977 DP(NETIF_MSG_LINK, "Tx is disabled\n");
8979 vars->line_speed = 0;
8986 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
8987 struct link_params *params,
8988 struct link_vars *vars)
8990 struct bnx2x *bp = params->bp;
8991 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
8993 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
8994 bnx2x_wait_reset_complete(bp, phy, params);
8996 bnx2x_8726_external_rom_boot(phy, params);
8998 /* Need to call module detected on initialization since the module
8999 * detection triggered by actual module insertion might occur before
9000 * driver is loaded, and when driver is loaded, it reset all
9001 * registers, including the transmitter
9003 bnx2x_sfp_module_detection(phy, params);
9005 if (phy->req_line_speed == SPEED_1000) {
9006 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9007 bnx2x_cl45_write(bp, phy,
9008 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9009 bnx2x_cl45_write(bp, phy,
9010 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9011 bnx2x_cl45_write(bp, phy,
9012 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
9013 bnx2x_cl45_write(bp, phy,
9014 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9016 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9017 (phy->speed_cap_mask &
9018 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
9019 ((phy->speed_cap_mask &
9020 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9021 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9022 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9023 /* Set Flow control */
9024 bnx2x_ext_phy_set_pause(params, phy, vars);
9025 bnx2x_cl45_write(bp, phy,
9026 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
9027 bnx2x_cl45_write(bp, phy,
9028 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
9029 bnx2x_cl45_write(bp, phy,
9030 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
9031 bnx2x_cl45_write(bp, phy,
9032 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
9033 bnx2x_cl45_write(bp, phy,
9034 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
9035 /* Enable RX-ALARM control to receive interrupt for 1G speed
9038 bnx2x_cl45_write(bp, phy,
9039 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
9040 bnx2x_cl45_write(bp, phy,
9041 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9044 } else { /* Default 10G. Set only LASI control */
9045 bnx2x_cl45_write(bp, phy,
9046 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
9049 /* Set TX PreEmphasis if needed */
9050 if ((params->feature_config_flags &
9051 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9053 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9054 phy->tx_preemphasis[0],
9055 phy->tx_preemphasis[1]);
9056 bnx2x_cl45_write(bp, phy,
9058 MDIO_PMA_REG_8726_TX_CTRL1,
9059 phy->tx_preemphasis[0]);
9061 bnx2x_cl45_write(bp, phy,
9063 MDIO_PMA_REG_8726_TX_CTRL2,
9064 phy->tx_preemphasis[1]);
9071 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
9072 struct link_params *params)
9074 struct bnx2x *bp = params->bp;
9075 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
9076 /* Set serial boot control for external load */
9077 bnx2x_cl45_write(bp, phy,
9079 MDIO_PMA_REG_GEN_CTRL, 0x0001);
9082 /******************************************************************/
9083 /* BCM8727 PHY SECTION */
9084 /******************************************************************/
9086 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
9087 struct link_params *params, u8 mode)
9089 struct bnx2x *bp = params->bp;
9090 u16 led_mode_bitmask = 0;
9091 u16 gpio_pins_bitmask = 0;
9093 /* Only NOC flavor requires to set the LED specifically */
9094 if (!(phy->flags & FLAGS_NOC))
9097 case LED_MODE_FRONT_PANEL_OFF:
9099 led_mode_bitmask = 0;
9100 gpio_pins_bitmask = 0x03;
9103 led_mode_bitmask = 0;
9104 gpio_pins_bitmask = 0x02;
9107 led_mode_bitmask = 0x60;
9108 gpio_pins_bitmask = 0x11;
9111 bnx2x_cl45_read(bp, phy,
9113 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9116 val |= led_mode_bitmask;
9117 bnx2x_cl45_write(bp, phy,
9119 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9121 bnx2x_cl45_read(bp, phy,
9123 MDIO_PMA_REG_8727_GPIO_CTRL,
9126 val |= gpio_pins_bitmask;
9127 bnx2x_cl45_write(bp, phy,
9129 MDIO_PMA_REG_8727_GPIO_CTRL,
9132 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
9133 struct link_params *params) {
9134 u32 swap_val, swap_override;
9136 /* The PHY reset is controlled by GPIO 1. Fake the port number
9137 * to cancel the swap done in set_gpio()
9139 struct bnx2x *bp = params->bp;
9140 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
9141 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
9142 port = (swap_val && swap_override) ^ 1;
9143 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
9144 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
9147 static void bnx2x_8727_config_speed(struct bnx2x_phy *phy,
9148 struct link_params *params)
9150 struct bnx2x *bp = params->bp;
9152 /* Set option 1G speed */
9153 if ((phy->req_line_speed == SPEED_1000) ||
9154 (phy->media_type == ETH_PHY_SFP_1G_FIBER)) {
9155 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9156 bnx2x_cl45_write(bp, phy,
9157 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9158 bnx2x_cl45_write(bp, phy,
9159 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9160 bnx2x_cl45_read(bp, phy,
9161 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
9162 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
9163 /* Power down the XAUI until link is up in case of dual-media
9166 if (DUAL_MEDIA(params)) {
9167 bnx2x_cl45_read(bp, phy,
9169 MDIO_PMA_REG_8727_PCS_GP, &val);
9171 bnx2x_cl45_write(bp, phy,
9173 MDIO_PMA_REG_8727_PCS_GP, val);
9175 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9176 ((phy->speed_cap_mask &
9177 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
9178 ((phy->speed_cap_mask &
9179 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9180 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9182 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9183 bnx2x_cl45_write(bp, phy,
9184 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
9185 bnx2x_cl45_write(bp, phy,
9186 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
9188 /* Since the 8727 has only single reset pin, need to set the 10G
9189 * registers although it is default
9191 bnx2x_cl45_write(bp, phy,
9192 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
9194 bnx2x_cl45_write(bp, phy,
9195 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
9196 bnx2x_cl45_write(bp, phy,
9197 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
9198 bnx2x_cl45_write(bp, phy,
9199 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
9204 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
9205 struct link_params *params,
9206 struct link_vars *vars)
9209 u16 tmp1, val, mod_abs, tmp2;
9210 u16 rx_alarm_ctrl_val;
9212 struct bnx2x *bp = params->bp;
9213 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
9215 bnx2x_wait_reset_complete(bp, phy, params);
9216 rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
9217 /* Should be 0x6 to enable XS on Tx side. */
9218 lasi_ctrl_val = 0x0006;
9220 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
9222 bnx2x_cl45_write(bp, phy,
9223 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9225 bnx2x_cl45_write(bp, phy,
9226 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
9228 bnx2x_cl45_write(bp, phy,
9229 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, lasi_ctrl_val);
9231 /* Initially configure MOD_ABS to interrupt when module is
9234 bnx2x_cl45_read(bp, phy,
9235 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9236 /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
9237 * When the EDC is off it locks onto a reference clock and avoids
9241 if (!(phy->flags & FLAGS_NOC))
9243 bnx2x_cl45_write(bp, phy,
9244 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9247 /* Enable/Disable PHY transmitter output */
9248 bnx2x_set_disable_pmd_transmit(params, phy, 0);
9250 /* Make MOD_ABS give interrupt on change */
9251 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9254 if (phy->flags & FLAGS_NOC)
9257 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
9258 * status which reflect SFP+ module over-current
9260 if (!(phy->flags & FLAGS_NOC))
9261 val &= 0xff8f; /* Reset bits 4-6 */
9262 bnx2x_cl45_write(bp, phy,
9263 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
9265 bnx2x_8727_power_module(bp, phy, 1);
9267 bnx2x_cl45_read(bp, phy,
9268 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
9270 bnx2x_cl45_read(bp, phy,
9271 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
9273 bnx2x_8727_config_speed(phy, params);
9274 /* Set 2-wire transfer rate of SFP+ module EEPROM
9275 * to 100Khz since some DACs(direct attached cables) do
9276 * not work at 400Khz.
9278 bnx2x_cl45_write(bp, phy,
9279 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
9282 /* Set TX PreEmphasis if needed */
9283 if ((params->feature_config_flags &
9284 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9285 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9286 phy->tx_preemphasis[0],
9287 phy->tx_preemphasis[1]);
9288 bnx2x_cl45_write(bp, phy,
9289 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
9290 phy->tx_preemphasis[0]);
9292 bnx2x_cl45_write(bp, phy,
9293 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
9294 phy->tx_preemphasis[1]);
9297 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
9298 * power mode, if TX Laser is disabled
9300 tx_en_mode = REG_RD(bp, params->shmem_base +
9301 offsetof(struct shmem_region,
9302 dev_info.port_hw_config[params->port].sfp_ctrl))
9303 & PORT_HW_CFG_TX_LASER_MASK;
9305 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9307 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
9308 bnx2x_cl45_read(bp, phy,
9309 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
9312 bnx2x_cl45_write(bp, phy,
9313 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
9314 bnx2x_cl45_read(bp, phy,
9315 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9317 bnx2x_cl45_write(bp, phy,
9318 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9325 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9326 struct link_params *params)
9328 struct bnx2x *bp = params->bp;
9329 u16 mod_abs, rx_alarm_status;
9330 u32 val = REG_RD(bp, params->shmem_base +
9331 offsetof(struct shmem_region, dev_info.
9332 port_feature_config[params->port].
9334 bnx2x_cl45_read(bp, phy,
9336 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9337 if (mod_abs & (1<<8)) {
9339 /* Module is absent */
9341 "MOD_ABS indication show module is absent\n");
9342 phy->media_type = ETH_PHY_NOT_PRESENT;
9343 /* 1. Set mod_abs to detect next module
9345 * 2. Set EDC off by setting OPTXLOS signal input to low
9347 * When the EDC is off it locks onto a reference clock and
9348 * avoids becoming 'lost'.
9351 if (!(phy->flags & FLAGS_NOC))
9353 bnx2x_cl45_write(bp, phy,
9355 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9357 /* Clear RX alarm since it stays up as long as
9358 * the mod_abs wasn't changed
9360 bnx2x_cl45_read(bp, phy,
9362 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9365 /* Module is present */
9367 "MOD_ABS indication show module is present\n");
9368 /* First disable transmitter, and if the module is ok, the
9369 * module_detection will enable it
9370 * 1. Set mod_abs to detect next module absent event ( bit 8)
9371 * 2. Restore the default polarity of the OPRXLOS signal and
9372 * this signal will then correctly indicate the presence or
9373 * absence of the Rx signal. (bit 9)
9376 if (!(phy->flags & FLAGS_NOC))
9378 bnx2x_cl45_write(bp, phy,
9380 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9382 /* Clear RX alarm since it stays up as long as the mod_abs
9383 * wasn't changed. This is need to be done before calling the
9384 * module detection, otherwise it will clear* the link update
9387 bnx2x_cl45_read(bp, phy,
9389 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9392 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9393 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
9394 bnx2x_sfp_set_transmitter(params, phy, 0);
9396 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
9397 bnx2x_sfp_module_detection(phy, params);
9399 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
9401 /* Reconfigure link speed based on module type limitations */
9402 bnx2x_8727_config_speed(phy, params);
9405 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
9407 /* No need to check link status in case of module plugged in/out */
9410 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9411 struct link_params *params,
9412 struct link_vars *vars)
9415 struct bnx2x *bp = params->bp;
9416 u8 link_up = 0, oc_port = params->port;
9417 u16 link_status = 0;
9418 u16 rx_alarm_status, lasi_ctrl, val1;
9420 /* If PHY is not initialized, do not check link status */
9421 bnx2x_cl45_read(bp, phy,
9422 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9427 /* Check the LASI on Rx */
9428 bnx2x_cl45_read(bp, phy,
9429 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
9431 vars->line_speed = 0;
9432 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
9434 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
9435 MDIO_PMA_LASI_TXCTRL);
9437 bnx2x_cl45_read(bp, phy,
9438 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9440 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
9443 bnx2x_cl45_read(bp, phy,
9444 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
9446 /* If a module is present and there is need to check
9449 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
9450 /* Check over-current using 8727 GPIO0 input*/
9451 bnx2x_cl45_read(bp, phy,
9452 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
9455 if ((val1 & (1<<8)) == 0) {
9456 if (!CHIP_IS_E1x(bp))
9457 oc_port = BP_PATH(bp) + (params->port << 1);
9459 "8727 Power fault has been detected on port %d\n",
9461 netdev_err(bp->dev, "Error: Power fault on Port %d has "
9462 "been detected and the power to "
9463 "that SFP+ module has been removed "
9464 "to prevent failure of the card. "
9465 "Please remove the SFP+ module and "
9466 "restart the system to clear this "
9469 /* Disable all RX_ALARMs except for mod_abs */
9470 bnx2x_cl45_write(bp, phy,
9472 MDIO_PMA_LASI_RXCTRL, (1<<5));
9474 bnx2x_cl45_read(bp, phy,
9476 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9477 /* Wait for module_absent_event */
9479 bnx2x_cl45_write(bp, phy,
9481 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
9482 /* Clear RX alarm */
9483 bnx2x_cl45_read(bp, phy,
9485 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9488 } /* Over current check */
9490 /* When module absent bit is set, check module */
9491 if (rx_alarm_status & (1<<5)) {
9492 bnx2x_8727_handle_mod_abs(phy, params);
9493 /* Enable all mod_abs and link detection bits */
9494 bnx2x_cl45_write(bp, phy,
9495 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9499 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
9500 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n");
9501 bnx2x_sfp_set_transmitter(params, phy, 1);
9503 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9507 bnx2x_cl45_read(bp, phy,
9509 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
9511 /* Bits 0..2 --> speed detected,
9512 * Bits 13..15--> link is down
9514 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
9516 vars->line_speed = SPEED_10000;
9517 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
9519 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
9521 vars->line_speed = SPEED_1000;
9522 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
9526 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
9530 /* Capture 10G link fault. */
9531 if (vars->line_speed == SPEED_10000) {
9532 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9533 MDIO_PMA_LASI_TXSTAT, &val1);
9535 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9536 MDIO_PMA_LASI_TXSTAT, &val1);
9538 if (val1 & (1<<0)) {
9539 vars->fault_detected = 1;
9544 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9545 vars->duplex = DUPLEX_FULL;
9546 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9549 if ((DUAL_MEDIA(params)) &&
9550 (phy->req_line_speed == SPEED_1000)) {
9551 bnx2x_cl45_read(bp, phy,
9553 MDIO_PMA_REG_8727_PCS_GP, &val1);
9554 /* In case of dual-media board and 1G, power up the XAUI side,
9555 * otherwise power it down. For 10G it is done automatically
9561 bnx2x_cl45_write(bp, phy,
9563 MDIO_PMA_REG_8727_PCS_GP, val1);
9568 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9569 struct link_params *params)
9571 struct bnx2x *bp = params->bp;
9573 /* Enable/Disable PHY transmitter output */
9574 bnx2x_set_disable_pmd_transmit(params, phy, 1);
9576 /* Disable Transmitter */
9577 bnx2x_sfp_set_transmitter(params, phy, 0);
9579 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9583 /******************************************************************/
9584 /* BCM8481/BCM84823/BCM84833 PHY SECTION */
9585 /******************************************************************/
9586 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9590 u16 val, fw_ver1, fw_ver2, cnt;
9592 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9593 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
9594 bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff,
9597 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9598 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9599 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
9600 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9601 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
9602 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
9603 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
9605 for (cnt = 0; cnt < 100; cnt++) {
9606 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9612 DP(NETIF_MSG_LINK, "Unable to read 848xx "
9613 "phy fw version(1)\n");
9614 bnx2x_save_spirom_version(bp, port, 0,
9620 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9621 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9622 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9623 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9624 for (cnt = 0; cnt < 100; cnt++) {
9625 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9631 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw "
9633 bnx2x_save_spirom_version(bp, port, 0,
9638 /* lower 16 bits of the register SPI_FW_STATUS */
9639 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9640 /* upper 16 bits of register SPI_FW_STATUS */
9641 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9643 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9648 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9649 struct bnx2x_phy *phy)
9653 /* PHYC_CTL_LED_CTL */
9654 bnx2x_cl45_read(bp, phy,
9656 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9660 bnx2x_cl45_write(bp, phy,
9662 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9664 bnx2x_cl45_write(bp, phy,
9666 MDIO_PMA_REG_8481_LED1_MASK,
9669 bnx2x_cl45_write(bp, phy,
9671 MDIO_PMA_REG_8481_LED2_MASK,
9674 /* Select activity source by Tx and Rx, as suggested by PHY AE */
9675 bnx2x_cl45_write(bp, phy,
9677 MDIO_PMA_REG_8481_LED3_MASK,
9680 /* Select the closest activity blink rate to that in 10/100/1000 */
9681 bnx2x_cl45_write(bp, phy,
9683 MDIO_PMA_REG_8481_LED3_BLINK,
9686 /* Configure the blink rate to ~15.9 Hz */
9687 bnx2x_cl45_write(bp, phy,
9689 MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9690 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ);
9692 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9693 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9695 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9697 bnx2x_cl45_read(bp, phy,
9698 MDIO_PMA_DEVAD, offset, &val);
9699 val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/
9700 bnx2x_cl45_write(bp, phy,
9701 MDIO_PMA_DEVAD, offset, val);
9703 /* 'Interrupt Mask' */
9704 bnx2x_cl45_write(bp, phy,
9709 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9710 struct link_params *params,
9711 struct link_vars *vars)
9713 struct bnx2x *bp = params->bp;
9714 u16 autoneg_val, an_1000_val, an_10_100_val, an_10g_val;
9716 if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9717 /* Save spirom version */
9718 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9720 /* This phy uses the NIG latch mechanism since link indication
9721 * arrives through its LED4 and not via its LASI signal, so we
9722 * get steady signal instead of clear on read
9724 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9725 1 << NIG_LATCH_BC_ENABLE_MI_INT);
9727 bnx2x_cl45_write(bp, phy,
9728 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9730 bnx2x_848xx_set_led(bp, phy);
9732 /* set 1000 speed advertisement */
9733 bnx2x_cl45_read(bp, phy,
9734 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9737 bnx2x_ext_phy_set_pause(params, phy, vars);
9738 bnx2x_cl45_read(bp, phy,
9740 MDIO_AN_REG_8481_LEGACY_AN_ADV,
9742 bnx2x_cl45_read(bp, phy,
9743 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9745 /* Disable forced speed */
9746 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9747 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9749 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9750 (phy->speed_cap_mask &
9751 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9752 (phy->req_line_speed == SPEED_1000)) {
9753 an_1000_val |= (1<<8);
9754 autoneg_val |= (1<<9 | 1<<12);
9755 if (phy->req_duplex == DUPLEX_FULL)
9756 an_1000_val |= (1<<9);
9757 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9759 an_1000_val &= ~((1<<8) | (1<<9));
9761 bnx2x_cl45_write(bp, phy,
9762 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9765 /* set 100 speed advertisement */
9766 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9767 (phy->speed_cap_mask &
9768 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
9769 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))) {
9770 an_10_100_val |= (1<<7);
9771 /* Enable autoneg and restart autoneg for legacy speeds */
9772 autoneg_val |= (1<<9 | 1<<12);
9774 if (phy->req_duplex == DUPLEX_FULL)
9775 an_10_100_val |= (1<<8);
9776 DP(NETIF_MSG_LINK, "Advertising 100M\n");
9778 /* set 10 speed advertisement */
9779 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9780 (phy->speed_cap_mask &
9781 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
9782 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
9784 (SUPPORTED_10baseT_Half |
9785 SUPPORTED_10baseT_Full)))) {
9786 an_10_100_val |= (1<<5);
9787 autoneg_val |= (1<<9 | 1<<12);
9788 if (phy->req_duplex == DUPLEX_FULL)
9789 an_10_100_val |= (1<<6);
9790 DP(NETIF_MSG_LINK, "Advertising 10M\n");
9793 /* Only 10/100 are allowed to work in FORCE mode */
9794 if ((phy->req_line_speed == SPEED_100) &&
9796 (SUPPORTED_100baseT_Half |
9797 SUPPORTED_100baseT_Full))) {
9798 autoneg_val |= (1<<13);
9799 /* Enabled AUTO-MDIX when autoneg is disabled */
9800 bnx2x_cl45_write(bp, phy,
9801 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9802 (1<<15 | 1<<9 | 7<<0));
9803 /* The PHY needs this set even for forced link. */
9804 an_10_100_val |= (1<<8) | (1<<7);
9805 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9807 if ((phy->req_line_speed == SPEED_10) &&
9809 (SUPPORTED_10baseT_Half |
9810 SUPPORTED_10baseT_Full))) {
9811 /* Enabled AUTO-MDIX when autoneg is disabled */
9812 bnx2x_cl45_write(bp, phy,
9813 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9814 (1<<15 | 1<<9 | 7<<0));
9815 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9818 bnx2x_cl45_write(bp, phy,
9819 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9822 if (phy->req_duplex == DUPLEX_FULL)
9823 autoneg_val |= (1<<8);
9825 /* Always write this if this is not 84833.
9826 * For 84833, write it only when it's a forced speed.
9828 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9829 ((autoneg_val & (1<<12)) == 0))
9830 bnx2x_cl45_write(bp, phy,
9832 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9834 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9835 (phy->speed_cap_mask &
9836 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9837 (phy->req_line_speed == SPEED_10000)) {
9838 DP(NETIF_MSG_LINK, "Advertising 10G\n");
9839 /* Restart autoneg for 10G*/
9841 bnx2x_cl45_read(bp, phy,
9843 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9845 bnx2x_cl45_write(bp, phy,
9847 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9848 an_10g_val | 0x1000);
9849 bnx2x_cl45_write(bp, phy,
9850 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9853 bnx2x_cl45_write(bp, phy,
9855 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9861 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9862 struct link_params *params,
9863 struct link_vars *vars)
9865 struct bnx2x *bp = params->bp;
9866 /* Restore normal power mode*/
9867 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9868 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9871 bnx2x_ext_phy_hw_reset(bp, params->port);
9872 bnx2x_wait_reset_complete(bp, phy, params);
9874 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9875 return bnx2x_848xx_cmn_config_init(phy, params, vars);
9878 #define PHY84833_CMDHDLR_WAIT 300
9879 #define PHY84833_CMDHDLR_MAX_ARGS 5
9880 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
9881 struct link_params *params,
9883 u16 cmd_args[], int argc)
9887 struct bnx2x *bp = params->bp;
9888 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9889 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9890 MDIO_84833_CMD_HDLR_STATUS,
9891 PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9892 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9893 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9894 MDIO_84833_CMD_HDLR_STATUS, &val);
9895 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
9897 usleep_range(1000, 2000);
9899 if (idx >= PHY84833_CMDHDLR_WAIT) {
9900 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
9904 /* Prepare argument(s) and issue command */
9905 for (idx = 0; idx < argc; idx++) {
9906 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9907 MDIO_84833_CMD_HDLR_DATA1 + idx,
9910 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9911 MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
9912 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9913 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9914 MDIO_84833_CMD_HDLR_STATUS, &val);
9915 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
9916 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
9918 usleep_range(1000, 2000);
9920 if ((idx >= PHY84833_CMDHDLR_WAIT) ||
9921 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
9922 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
9925 /* Gather returning data */
9926 for (idx = 0; idx < argc; idx++) {
9927 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9928 MDIO_84833_CMD_HDLR_DATA1 + idx,
9931 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9932 MDIO_84833_CMD_HDLR_STATUS,
9933 PHY84833_STATUS_CMD_CLEAR_COMPLETE);
9938 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9939 struct link_params *params,
9940 struct link_vars *vars)
9943 u16 data[PHY84833_CMDHDLR_MAX_ARGS];
9945 struct bnx2x *bp = params->bp;
9947 /* Check for configuration. */
9948 pair_swap = REG_RD(bp, params->shmem_base +
9949 offsetof(struct shmem_region,
9950 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9951 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9956 /* Only the second argument is used for this command */
9957 data[1] = (u16)pair_swap;
9959 status = bnx2x_84833_cmd_hdlr(phy, params,
9960 PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS);
9962 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]);
9967 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
9968 u32 shmem_base_path[],
9974 if (CHIP_IS_E3(bp)) {
9975 /* Assume that these will be GPIOs, not EPIOs. */
9976 for (idx = 0; idx < 2; idx++) {
9977 /* Map config param to register bit. */
9978 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9979 offsetof(struct shmem_region,
9980 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9981 reset_pin[idx] = (reset_pin[idx] &
9982 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9983 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9984 reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9985 reset_pin[idx] = (1 << reset_pin[idx]);
9987 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9989 /* E2, look from diff place of shmem. */
9990 for (idx = 0; idx < 2; idx++) {
9991 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9992 offsetof(struct shmem_region,
9993 dev_info.port_hw_config[0].default_cfg));
9994 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9995 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9996 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9997 reset_pin[idx] = (1 << reset_pin[idx]);
9999 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
10002 return reset_gpios;
10005 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
10006 struct link_params *params)
10008 struct bnx2x *bp = params->bp;
10010 u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
10011 offsetof(struct shmem2_region,
10012 other_shmem_base_addr));
10014 u32 shmem_base_path[2];
10016 /* Work around for 84833 LED failure inside RESET status */
10017 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10018 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
10019 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
10020 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10021 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
10022 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
10024 shmem_base_path[0] = params->shmem_base;
10025 shmem_base_path[1] = other_shmem_base_addr;
10027 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
10030 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
10032 DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
10038 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy,
10039 struct link_params *params,
10040 struct link_vars *vars)
10043 struct bnx2x *bp = params->bp;
10046 DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n");
10048 /* Prevent Phy from working in EEE and advertising it */
10049 rc = bnx2x_84833_cmd_hdlr(phy, params,
10050 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
10052 DP(NETIF_MSG_LINK, "EEE disable failed.\n");
10056 return bnx2x_eee_disable(phy, params, vars);
10059 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy,
10060 struct link_params *params,
10061 struct link_vars *vars)
10064 struct bnx2x *bp = params->bp;
10067 rc = bnx2x_84833_cmd_hdlr(phy, params,
10068 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
10070 DP(NETIF_MSG_LINK, "EEE enable failed.\n");
10074 return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
10077 #define PHY84833_CONSTANT_LATENCY 1193
10078 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
10079 struct link_params *params,
10080 struct link_vars *vars)
10082 struct bnx2x *bp = params->bp;
10083 u8 port, initialize = 1;
10085 u32 actual_phy_selection, cms_enable;
10086 u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
10089 usleep_range(1000, 2000);
10091 if (!(CHIP_IS_E1x(bp)))
10092 port = BP_PATH(bp);
10094 port = params->port;
10096 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10097 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10098 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
10102 bnx2x_cl45_write(bp, phy,
10104 MDIO_PMA_REG_CTRL, 0x8000);
10107 bnx2x_wait_reset_complete(bp, phy, params);
10109 /* Wait for GPHY to come out of reset */
10111 if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
10112 /* BCM84823 requires that XGXS links up first @ 10G for normal
10116 temp = vars->line_speed;
10117 vars->line_speed = SPEED_10000;
10118 bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0);
10119 bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars);
10120 vars->line_speed = temp;
10123 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10124 MDIO_CTL_REG_84823_MEDIA, &val);
10125 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10126 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
10127 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
10128 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
10129 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
10131 if (CHIP_IS_E3(bp)) {
10132 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10133 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
10135 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
10136 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
10139 actual_phy_selection = bnx2x_phy_selection(params);
10141 switch (actual_phy_selection) {
10142 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
10143 /* Do nothing. Essentially this is like the priority copper */
10145 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
10146 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
10148 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
10149 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
10151 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
10152 /* Do nothing here. The first PHY won't be initialized at all */
10154 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
10155 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
10159 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
10160 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
10162 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10163 MDIO_CTL_REG_84823_MEDIA, val);
10164 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
10165 params->multi_phy_config, val);
10167 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
10168 bnx2x_84833_pair_swap_cfg(phy, params, vars);
10170 /* Keep AutogrEEEn disabled. */
10173 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
10174 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
10175 rc = bnx2x_84833_cmd_hdlr(phy, params,
10176 PHY84833_CMD_SET_EEE_MODE, cmd_args,
10177 PHY84833_CMDHDLR_MAX_ARGS);
10179 DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
10182 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
10184 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
10185 /* 84833 PHY has a better feature and doesn't need to support this. */
10186 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10187 cms_enable = REG_RD(bp, params->shmem_base +
10188 offsetof(struct shmem_region,
10189 dev_info.port_hw_config[params->port].default_cfg)) &
10190 PORT_HW_CFG_ENABLE_CMS_MASK;
10192 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10193 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
10195 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
10197 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
10198 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10199 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
10202 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10203 MDIO_84833_TOP_CFG_FW_REV, &val);
10205 /* Configure EEE support */
10206 if ((val >= MDIO_84833_TOP_CFG_FW_EEE) && bnx2x_eee_has_cap(params)) {
10207 phy->flags |= FLAGS_EEE_10GBT;
10208 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
10210 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10211 bnx2x_8483x_disable_eee(phy, params, vars);
10215 if ((params->req_duplex[actual_phy_selection] == DUPLEX_FULL) &&
10216 (params->eee_mode & EEE_MODE_ADV_LPI) &&
10217 (bnx2x_eee_calc_timer(params) ||
10218 !(params->eee_mode & EEE_MODE_ENABLE_LPI)))
10219 rc = bnx2x_8483x_enable_eee(phy, params, vars);
10221 rc = bnx2x_8483x_disable_eee(phy, params, vars);
10223 DP(NETIF_MSG_LINK, "Failed to set EEE advertisment\n");
10227 phy->flags &= ~FLAGS_EEE_10GBT;
10228 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
10231 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
10232 /* Bring PHY out of super isolate mode as the final step. */
10233 bnx2x_cl45_read(bp, phy,
10235 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
10236 val &= ~MDIO_84833_SUPER_ISOLATE;
10237 bnx2x_cl45_write(bp, phy,
10239 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
10244 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
10245 struct link_params *params,
10246 struct link_vars *vars)
10248 struct bnx2x *bp = params->bp;
10249 u16 val, val1, val2;
10253 /* Check 10G-BaseT link status */
10254 /* Check PMD signal ok */
10255 bnx2x_cl45_read(bp, phy,
10256 MDIO_AN_DEVAD, 0xFFFA, &val1);
10257 bnx2x_cl45_read(bp, phy,
10258 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
10260 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
10262 /* Check link 10G */
10263 if (val2 & (1<<11)) {
10264 vars->line_speed = SPEED_10000;
10265 vars->duplex = DUPLEX_FULL;
10267 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10268 } else { /* Check Legacy speed link */
10269 u16 legacy_status, legacy_speed;
10271 /* Enable expansion register 0x42 (Operation mode status) */
10272 bnx2x_cl45_write(bp, phy,
10274 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
10276 /* Get legacy speed operation status */
10277 bnx2x_cl45_read(bp, phy,
10279 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
10282 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
10284 link_up = ((legacy_status & (1<<11)) == (1<<11));
10285 legacy_speed = (legacy_status & (3<<9));
10286 if (legacy_speed == (0<<9))
10287 vars->line_speed = SPEED_10;
10288 else if (legacy_speed == (1<<9))
10289 vars->line_speed = SPEED_100;
10290 else if (legacy_speed == (2<<9))
10291 vars->line_speed = SPEED_1000;
10292 else { /* Should not happen: Treat as link down */
10293 vars->line_speed = 0;
10298 if (legacy_status & (1<<8))
10299 vars->duplex = DUPLEX_FULL;
10301 vars->duplex = DUPLEX_HALF;
10304 "Link is up in %dMbps, is_duplex_full= %d\n",
10306 (vars->duplex == DUPLEX_FULL));
10307 /* Check legacy speed AN resolution */
10308 bnx2x_cl45_read(bp, phy,
10310 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
10313 vars->link_status |=
10314 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10315 bnx2x_cl45_read(bp, phy,
10317 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
10319 if ((val & (1<<0)) == 0)
10320 vars->link_status |=
10321 LINK_STATUS_PARALLEL_DETECTION_USED;
10325 DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n",
10327 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10329 /* Read LP advertised speeds */
10330 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10331 MDIO_AN_REG_CL37_FC_LP, &val);
10333 vars->link_status |=
10334 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10336 vars->link_status |=
10337 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10339 vars->link_status |=
10340 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10342 vars->link_status |=
10343 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10345 vars->link_status |=
10346 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10348 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10349 MDIO_AN_REG_1000T_STATUS, &val);
10352 vars->link_status |=
10353 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10355 vars->link_status |=
10356 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10358 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10359 MDIO_AN_REG_MASTER_STATUS, &val);
10362 vars->link_status |=
10363 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10365 /* Determine if EEE was negotiated */
10366 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10367 bnx2x_eee_an_resolve(phy, params, vars);
10374 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
10378 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
10379 status = bnx2x_format_ver(spirom_ver, str, len);
10383 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
10384 struct link_params *params)
10386 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10387 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
10388 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10389 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
10392 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
10393 struct link_params *params)
10395 bnx2x_cl45_write(params->bp, phy,
10396 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
10397 bnx2x_cl45_write(params->bp, phy,
10398 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
10401 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
10402 struct link_params *params)
10404 struct bnx2x *bp = params->bp;
10408 if (!(CHIP_IS_E1x(bp)))
10409 port = BP_PATH(bp);
10411 port = params->port;
10413 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10414 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10415 MISC_REGISTERS_GPIO_OUTPUT_LOW,
10418 bnx2x_cl45_read(bp, phy,
10420 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
10421 val16 |= MDIO_84833_SUPER_ISOLATE;
10422 bnx2x_cl45_write(bp, phy,
10424 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
10428 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
10429 struct link_params *params, u8 mode)
10431 struct bnx2x *bp = params->bp;
10435 if (!(CHIP_IS_E1x(bp)))
10436 port = BP_PATH(bp);
10438 port = params->port;
10443 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
10445 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10446 SHARED_HW_CFG_LED_EXTPHY1) {
10448 /* Set LED masks */
10449 bnx2x_cl45_write(bp, phy,
10451 MDIO_PMA_REG_8481_LED1_MASK,
10454 bnx2x_cl45_write(bp, phy,
10456 MDIO_PMA_REG_8481_LED2_MASK,
10459 bnx2x_cl45_write(bp, phy,
10461 MDIO_PMA_REG_8481_LED3_MASK,
10464 bnx2x_cl45_write(bp, phy,
10466 MDIO_PMA_REG_8481_LED5_MASK,
10470 bnx2x_cl45_write(bp, phy,
10472 MDIO_PMA_REG_8481_LED1_MASK,
10476 case LED_MODE_FRONT_PANEL_OFF:
10478 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
10481 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10482 SHARED_HW_CFG_LED_EXTPHY1) {
10484 /* Set LED masks */
10485 bnx2x_cl45_write(bp, phy,
10487 MDIO_PMA_REG_8481_LED1_MASK,
10490 bnx2x_cl45_write(bp, phy,
10492 MDIO_PMA_REG_8481_LED2_MASK,
10495 bnx2x_cl45_write(bp, phy,
10497 MDIO_PMA_REG_8481_LED3_MASK,
10500 bnx2x_cl45_write(bp, phy,
10502 MDIO_PMA_REG_8481_LED5_MASK,
10506 bnx2x_cl45_write(bp, phy,
10508 MDIO_PMA_REG_8481_LED1_MASK,
10514 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
10516 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10517 SHARED_HW_CFG_LED_EXTPHY1) {
10518 /* Set control reg */
10519 bnx2x_cl45_read(bp, phy,
10521 MDIO_PMA_REG_8481_LINK_SIGNAL,
10526 bnx2x_cl45_write(bp, phy,
10528 MDIO_PMA_REG_8481_LINK_SIGNAL,
10531 /* Set LED masks */
10532 bnx2x_cl45_write(bp, phy,
10534 MDIO_PMA_REG_8481_LED1_MASK,
10537 bnx2x_cl45_write(bp, phy,
10539 MDIO_PMA_REG_8481_LED2_MASK,
10542 bnx2x_cl45_write(bp, phy,
10544 MDIO_PMA_REG_8481_LED3_MASK,
10547 bnx2x_cl45_write(bp, phy,
10549 MDIO_PMA_REG_8481_LED5_MASK,
10552 bnx2x_cl45_write(bp, phy,
10554 MDIO_PMA_REG_8481_LED1_MASK,
10559 case LED_MODE_OPER:
10561 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
10563 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10564 SHARED_HW_CFG_LED_EXTPHY1) {
10566 /* Set control reg */
10567 bnx2x_cl45_read(bp, phy,
10569 MDIO_PMA_REG_8481_LINK_SIGNAL,
10573 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10574 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
10575 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
10576 bnx2x_cl45_write(bp, phy,
10578 MDIO_PMA_REG_8481_LINK_SIGNAL,
10582 /* Set LED masks */
10583 bnx2x_cl45_write(bp, phy,
10585 MDIO_PMA_REG_8481_LED1_MASK,
10588 bnx2x_cl45_write(bp, phy,
10590 MDIO_PMA_REG_8481_LED2_MASK,
10593 bnx2x_cl45_write(bp, phy,
10595 MDIO_PMA_REG_8481_LED3_MASK,
10598 bnx2x_cl45_write(bp, phy,
10600 MDIO_PMA_REG_8481_LED5_MASK,
10604 bnx2x_cl45_write(bp, phy,
10606 MDIO_PMA_REG_8481_LED1_MASK,
10609 /* Tell LED3 to blink on source */
10610 bnx2x_cl45_read(bp, phy,
10612 MDIO_PMA_REG_8481_LINK_SIGNAL,
10615 val |= (1<<6); /* A83B[8:6]= 1 */
10616 bnx2x_cl45_write(bp, phy,
10618 MDIO_PMA_REG_8481_LINK_SIGNAL,
10624 /* This is a workaround for E3+84833 until autoneg
10625 * restart is fixed in f/w
10627 if (CHIP_IS_E3(bp)) {
10628 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
10629 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10633 /******************************************************************/
10634 /* 54618SE PHY SECTION */
10635 /******************************************************************/
10636 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10637 struct link_params *params,
10638 struct link_vars *vars)
10640 struct bnx2x *bp = params->bp;
10642 u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10645 DP(NETIF_MSG_LINK, "54618SE cfg init\n");
10646 usleep_range(1000, 2000);
10648 /* This works with E3 only, no need to check the chip
10649 * before determining the port.
10651 port = params->port;
10653 cfg_pin = (REG_RD(bp, params->shmem_base +
10654 offsetof(struct shmem_region,
10655 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10656 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10657 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10659 /* Drive pin high to bring the GPHY out of reset. */
10660 bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10662 /* wait for GPHY to reset */
10666 bnx2x_cl22_write(bp, phy,
10667 MDIO_PMA_REG_CTRL, 0x8000);
10668 bnx2x_wait_reset_complete(bp, phy, params);
10670 /* Wait for GPHY to reset */
10673 /* Configure LED4: set to INTR (0x6). */
10674 /* Accessing shadow register 0xe. */
10675 bnx2x_cl22_write(bp, phy,
10676 MDIO_REG_GPHY_SHADOW,
10677 MDIO_REG_GPHY_SHADOW_LED_SEL2);
10678 bnx2x_cl22_read(bp, phy,
10679 MDIO_REG_GPHY_SHADOW,
10681 temp &= ~(0xf << 4);
10682 temp |= (0x6 << 4);
10683 bnx2x_cl22_write(bp, phy,
10684 MDIO_REG_GPHY_SHADOW,
10685 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10686 /* Configure INTR based on link status change. */
10687 bnx2x_cl22_write(bp, phy,
10688 MDIO_REG_INTR_MASK,
10689 ~MDIO_REG_INTR_MASK_LINK_STATUS);
10691 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10692 bnx2x_cl22_write(bp, phy,
10693 MDIO_REG_GPHY_SHADOW,
10694 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10695 bnx2x_cl22_read(bp, phy,
10696 MDIO_REG_GPHY_SHADOW,
10698 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10699 bnx2x_cl22_write(bp, phy,
10700 MDIO_REG_GPHY_SHADOW,
10701 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10704 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10705 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10707 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10708 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10709 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10711 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10712 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10713 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10715 /* Read all advertisement */
10716 bnx2x_cl22_read(bp, phy,
10720 bnx2x_cl22_read(bp, phy,
10724 bnx2x_cl22_read(bp, phy,
10728 /* Disable forced speed */
10729 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10730 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10733 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10734 (phy->speed_cap_mask &
10735 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10736 (phy->req_line_speed == SPEED_1000)) {
10737 an_1000_val |= (1<<8);
10738 autoneg_val |= (1<<9 | 1<<12);
10739 if (phy->req_duplex == DUPLEX_FULL)
10740 an_1000_val |= (1<<9);
10741 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10743 an_1000_val &= ~((1<<8) | (1<<9));
10745 bnx2x_cl22_write(bp, phy,
10748 bnx2x_cl22_read(bp, phy,
10752 /* Set 100 speed advertisement */
10753 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10754 (phy->speed_cap_mask &
10755 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
10756 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10757 an_10_100_val |= (1<<7);
10758 /* Enable autoneg and restart autoneg for legacy speeds */
10759 autoneg_val |= (1<<9 | 1<<12);
10761 if (phy->req_duplex == DUPLEX_FULL)
10762 an_10_100_val |= (1<<8);
10763 DP(NETIF_MSG_LINK, "Advertising 100M\n");
10766 /* Set 10 speed advertisement */
10767 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10768 (phy->speed_cap_mask &
10769 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
10770 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10771 an_10_100_val |= (1<<5);
10772 autoneg_val |= (1<<9 | 1<<12);
10773 if (phy->req_duplex == DUPLEX_FULL)
10774 an_10_100_val |= (1<<6);
10775 DP(NETIF_MSG_LINK, "Advertising 10M\n");
10778 /* Only 10/100 are allowed to work in FORCE mode */
10779 if (phy->req_line_speed == SPEED_100) {
10780 autoneg_val |= (1<<13);
10781 /* Enabled AUTO-MDIX when autoneg is disabled */
10782 bnx2x_cl22_write(bp, phy,
10784 (1<<15 | 1<<9 | 7<<0));
10785 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10787 if (phy->req_line_speed == SPEED_10) {
10788 /* Enabled AUTO-MDIX when autoneg is disabled */
10789 bnx2x_cl22_write(bp, phy,
10791 (1<<15 | 1<<9 | 7<<0));
10792 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10795 /* Check if we should turn on Auto-GrEEEn */
10796 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &temp);
10797 if (temp == MDIO_REG_GPHY_ID_54618SE) {
10798 if (params->feature_config_flags &
10799 FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10801 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10804 DP(NETIF_MSG_LINK, "Disabling Auto-GrEEEn\n");
10806 bnx2x_cl22_write(bp, phy,
10807 MDIO_REG_GPHY_CL45_ADDR_REG, MDIO_AN_DEVAD);
10808 bnx2x_cl22_write(bp, phy,
10809 MDIO_REG_GPHY_CL45_DATA_REG,
10810 MDIO_REG_GPHY_EEE_ADV);
10811 bnx2x_cl22_write(bp, phy,
10812 MDIO_REG_GPHY_CL45_ADDR_REG,
10813 (0x1 << 14) | MDIO_AN_DEVAD);
10814 bnx2x_cl22_write(bp, phy,
10815 MDIO_REG_GPHY_CL45_DATA_REG,
10819 bnx2x_cl22_write(bp, phy,
10821 an_10_100_val | fc_val);
10823 if (phy->req_duplex == DUPLEX_FULL)
10824 autoneg_val |= (1<<8);
10826 bnx2x_cl22_write(bp, phy,
10827 MDIO_PMA_REG_CTRL, autoneg_val);
10833 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy,
10834 struct link_params *params, u8 mode)
10836 struct bnx2x *bp = params->bp;
10839 bnx2x_cl22_write(bp, phy,
10840 MDIO_REG_GPHY_SHADOW,
10841 MDIO_REG_GPHY_SHADOW_LED_SEL1);
10842 bnx2x_cl22_read(bp, phy,
10843 MDIO_REG_GPHY_SHADOW,
10847 DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode);
10849 case LED_MODE_FRONT_PANEL_OFF:
10853 case LED_MODE_OPER:
10862 bnx2x_cl22_write(bp, phy,
10863 MDIO_REG_GPHY_SHADOW,
10864 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10869 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10870 struct link_params *params)
10872 struct bnx2x *bp = params->bp;
10876 /* In case of no EPIO routed to reset the GPHY, put it
10877 * in low power mode.
10879 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
10880 /* This works with E3 only, no need to check the chip
10881 * before determining the port.
10883 port = params->port;
10884 cfg_pin = (REG_RD(bp, params->shmem_base +
10885 offsetof(struct shmem_region,
10886 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10887 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10888 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10890 /* Drive pin low to put GPHY in reset. */
10891 bnx2x_set_cfg_pin(bp, cfg_pin, 0);
10894 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
10895 struct link_params *params,
10896 struct link_vars *vars)
10898 struct bnx2x *bp = params->bp;
10901 u16 legacy_status, legacy_speed;
10903 /* Get speed operation status */
10904 bnx2x_cl22_read(bp, phy,
10905 MDIO_REG_GPHY_AUX_STATUS,
10907 DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
10909 /* Read status to clear the PHY interrupt. */
10910 bnx2x_cl22_read(bp, phy,
10911 MDIO_REG_INTR_STATUS,
10914 link_up = ((legacy_status & (1<<2)) == (1<<2));
10917 legacy_speed = (legacy_status & (7<<8));
10918 if (legacy_speed == (7<<8)) {
10919 vars->line_speed = SPEED_1000;
10920 vars->duplex = DUPLEX_FULL;
10921 } else if (legacy_speed == (6<<8)) {
10922 vars->line_speed = SPEED_1000;
10923 vars->duplex = DUPLEX_HALF;
10924 } else if (legacy_speed == (5<<8)) {
10925 vars->line_speed = SPEED_100;
10926 vars->duplex = DUPLEX_FULL;
10928 /* Omitting 100Base-T4 for now */
10929 else if (legacy_speed == (3<<8)) {
10930 vars->line_speed = SPEED_100;
10931 vars->duplex = DUPLEX_HALF;
10932 } else if (legacy_speed == (2<<8)) {
10933 vars->line_speed = SPEED_10;
10934 vars->duplex = DUPLEX_FULL;
10935 } else if (legacy_speed == (1<<8)) {
10936 vars->line_speed = SPEED_10;
10937 vars->duplex = DUPLEX_HALF;
10938 } else /* Should not happen */
10939 vars->line_speed = 0;
10942 "Link is up in %dMbps, is_duplex_full= %d\n",
10944 (vars->duplex == DUPLEX_FULL));
10946 /* Check legacy speed AN resolution */
10947 bnx2x_cl22_read(bp, phy,
10951 vars->link_status |=
10952 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10953 bnx2x_cl22_read(bp, phy,
10956 if ((val & (1<<0)) == 0)
10957 vars->link_status |=
10958 LINK_STATUS_PARALLEL_DETECTION_USED;
10960 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
10963 /* Report whether EEE is resolved. */
10964 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &val);
10965 if (val == MDIO_REG_GPHY_ID_54618SE) {
10966 if (vars->link_status &
10967 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
10970 bnx2x_cl22_write(bp, phy,
10971 MDIO_REG_GPHY_CL45_ADDR_REG,
10973 bnx2x_cl22_write(bp, phy,
10974 MDIO_REG_GPHY_CL45_DATA_REG,
10975 MDIO_REG_GPHY_EEE_RESOLVED);
10976 bnx2x_cl22_write(bp, phy,
10977 MDIO_REG_GPHY_CL45_ADDR_REG,
10978 (0x1 << 14) | MDIO_AN_DEVAD);
10979 bnx2x_cl22_read(bp, phy,
10980 MDIO_REG_GPHY_CL45_DATA_REG,
10983 DP(NETIF_MSG_LINK, "EEE resolution: 0x%x\n", val);
10986 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10988 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
10989 /* Report LP advertised speeds */
10990 bnx2x_cl22_read(bp, phy, 0x5, &val);
10993 vars->link_status |=
10994 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10996 vars->link_status |=
10997 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10999 vars->link_status |=
11000 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
11002 vars->link_status |=
11003 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
11005 vars->link_status |=
11006 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
11008 bnx2x_cl22_read(bp, phy, 0xa, &val);
11010 vars->link_status |=
11011 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
11013 vars->link_status |=
11014 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
11020 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
11021 struct link_params *params)
11023 struct bnx2x *bp = params->bp;
11025 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
11027 DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
11029 /* Enable master/slave manual mmode and set to master */
11030 /* mii write 9 [bits set 11 12] */
11031 bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
11033 /* forced 1G and disable autoneg */
11034 /* set val [mii read 0] */
11035 /* set val [expr $val & [bits clear 6 12 13]] */
11036 /* set val [expr $val | [bits set 6 8]] */
11037 /* mii write 0 $val */
11038 bnx2x_cl22_read(bp, phy, 0x00, &val);
11039 val &= ~((1<<6) | (1<<12) | (1<<13));
11040 val |= (1<<6) | (1<<8);
11041 bnx2x_cl22_write(bp, phy, 0x00, val);
11043 /* Set external loopback and Tx using 6dB coding */
11044 /* mii write 0x18 7 */
11045 /* set val [mii read 0x18] */
11046 /* mii write 0x18 [expr $val | [bits set 10 15]] */
11047 bnx2x_cl22_write(bp, phy, 0x18, 7);
11048 bnx2x_cl22_read(bp, phy, 0x18, &val);
11049 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
11051 /* This register opens the gate for the UMAC despite its name */
11052 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
11054 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
11055 * length used by the MAC receive logic to check frames.
11057 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
11060 /******************************************************************/
11061 /* SFX7101 PHY SECTION */
11062 /******************************************************************/
11063 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
11064 struct link_params *params)
11066 struct bnx2x *bp = params->bp;
11067 /* SFX7101_XGXS_TEST1 */
11068 bnx2x_cl45_write(bp, phy,
11069 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
11072 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
11073 struct link_params *params,
11074 struct link_vars *vars)
11076 u16 fw_ver1, fw_ver2, val;
11077 struct bnx2x *bp = params->bp;
11078 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
11080 /* Restore normal power mode*/
11081 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11082 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
11084 bnx2x_ext_phy_hw_reset(bp, params->port);
11085 bnx2x_wait_reset_complete(bp, phy, params);
11087 bnx2x_cl45_write(bp, phy,
11088 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
11089 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
11090 bnx2x_cl45_write(bp, phy,
11091 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
11093 bnx2x_ext_phy_set_pause(params, phy, vars);
11094 /* Restart autoneg */
11095 bnx2x_cl45_read(bp, phy,
11096 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
11098 bnx2x_cl45_write(bp, phy,
11099 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
11101 /* Save spirom version */
11102 bnx2x_cl45_read(bp, phy,
11103 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
11105 bnx2x_cl45_read(bp, phy,
11106 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
11107 bnx2x_save_spirom_version(bp, params->port,
11108 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
11112 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
11113 struct link_params *params,
11114 struct link_vars *vars)
11116 struct bnx2x *bp = params->bp;
11119 bnx2x_cl45_read(bp, phy,
11120 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
11121 bnx2x_cl45_read(bp, phy,
11122 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
11123 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
11125 bnx2x_cl45_read(bp, phy,
11126 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
11127 bnx2x_cl45_read(bp, phy,
11128 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
11129 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
11131 link_up = ((val1 & 4) == 4);
11132 /* If link is up print the AN outcome of the SFX7101 PHY */
11134 bnx2x_cl45_read(bp, phy,
11135 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
11137 vars->line_speed = SPEED_10000;
11138 vars->duplex = DUPLEX_FULL;
11139 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
11140 val2, (val2 & (1<<14)));
11141 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
11142 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11144 /* Read LP advertised speeds */
11145 if (val2 & (1<<11))
11146 vars->link_status |=
11147 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
11152 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
11156 str[0] = (spirom_ver & 0xFF);
11157 str[1] = (spirom_ver & 0xFF00) >> 8;
11158 str[2] = (spirom_ver & 0xFF0000) >> 16;
11159 str[3] = (spirom_ver & 0xFF000000) >> 24;
11165 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
11169 bnx2x_cl45_read(bp, phy,
11171 MDIO_PMA_REG_7101_RESET, &val);
11173 for (cnt = 0; cnt < 10; cnt++) {
11175 /* Writes a self-clearing reset */
11176 bnx2x_cl45_write(bp, phy,
11178 MDIO_PMA_REG_7101_RESET,
11180 /* Wait for clear */
11181 bnx2x_cl45_read(bp, phy,
11183 MDIO_PMA_REG_7101_RESET, &val);
11185 if ((val & (1<<15)) == 0)
11190 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
11191 struct link_params *params) {
11192 /* Low power mode is controlled by GPIO 2 */
11193 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
11194 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11195 /* The PHY reset is controlled by GPIO 1 */
11196 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
11197 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11200 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
11201 struct link_params *params, u8 mode)
11204 struct bnx2x *bp = params->bp;
11206 case LED_MODE_FRONT_PANEL_OFF:
11213 case LED_MODE_OPER:
11217 bnx2x_cl45_write(bp, phy,
11219 MDIO_PMA_REG_7107_LINK_LED_CNTL,
11223 /******************************************************************/
11224 /* STATIC PHY DECLARATION */
11225 /******************************************************************/
11227 static struct bnx2x_phy phy_null = {
11228 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
11231 .flags = FLAGS_INIT_XGXS_FIRST,
11232 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11233 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11236 .media_type = ETH_PHY_NOT_PRESENT,
11238 .req_flow_ctrl = 0,
11239 .req_line_speed = 0,
11240 .speed_cap_mask = 0,
11243 .config_init = (config_init_t)NULL,
11244 .read_status = (read_status_t)NULL,
11245 .link_reset = (link_reset_t)NULL,
11246 .config_loopback = (config_loopback_t)NULL,
11247 .format_fw_ver = (format_fw_ver_t)NULL,
11248 .hw_reset = (hw_reset_t)NULL,
11249 .set_link_led = (set_link_led_t)NULL,
11250 .phy_specific_func = (phy_specific_func_t)NULL
11253 static struct bnx2x_phy phy_serdes = {
11254 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
11258 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11259 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11261 .supported = (SUPPORTED_10baseT_Half |
11262 SUPPORTED_10baseT_Full |
11263 SUPPORTED_100baseT_Half |
11264 SUPPORTED_100baseT_Full |
11265 SUPPORTED_1000baseT_Full |
11266 SUPPORTED_2500baseX_Full |
11268 SUPPORTED_Autoneg |
11270 SUPPORTED_Asym_Pause),
11271 .media_type = ETH_PHY_BASE_T,
11273 .req_flow_ctrl = 0,
11274 .req_line_speed = 0,
11275 .speed_cap_mask = 0,
11278 .config_init = (config_init_t)bnx2x_xgxs_config_init,
11279 .read_status = (read_status_t)bnx2x_link_settings_status,
11280 .link_reset = (link_reset_t)bnx2x_int_link_reset,
11281 .config_loopback = (config_loopback_t)NULL,
11282 .format_fw_ver = (format_fw_ver_t)NULL,
11283 .hw_reset = (hw_reset_t)NULL,
11284 .set_link_led = (set_link_led_t)NULL,
11285 .phy_specific_func = (phy_specific_func_t)NULL
11288 static struct bnx2x_phy phy_xgxs = {
11289 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11293 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11294 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11296 .supported = (SUPPORTED_10baseT_Half |
11297 SUPPORTED_10baseT_Full |
11298 SUPPORTED_100baseT_Half |
11299 SUPPORTED_100baseT_Full |
11300 SUPPORTED_1000baseT_Full |
11301 SUPPORTED_2500baseX_Full |
11302 SUPPORTED_10000baseT_Full |
11304 SUPPORTED_Autoneg |
11306 SUPPORTED_Asym_Pause),
11307 .media_type = ETH_PHY_CX4,
11309 .req_flow_ctrl = 0,
11310 .req_line_speed = 0,
11311 .speed_cap_mask = 0,
11314 .config_init = (config_init_t)bnx2x_xgxs_config_init,
11315 .read_status = (read_status_t)bnx2x_link_settings_status,
11316 .link_reset = (link_reset_t)bnx2x_int_link_reset,
11317 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
11318 .format_fw_ver = (format_fw_ver_t)NULL,
11319 .hw_reset = (hw_reset_t)NULL,
11320 .set_link_led = (set_link_led_t)NULL,
11321 .phy_specific_func = (phy_specific_func_t)NULL
11323 static struct bnx2x_phy phy_warpcore = {
11324 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11327 .flags = (FLAGS_HW_LOCK_REQUIRED |
11328 FLAGS_TX_ERROR_CHECK),
11329 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11330 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11332 .supported = (SUPPORTED_10baseT_Half |
11333 SUPPORTED_10baseT_Full |
11334 SUPPORTED_100baseT_Half |
11335 SUPPORTED_100baseT_Full |
11336 SUPPORTED_1000baseT_Full |
11337 SUPPORTED_10000baseT_Full |
11338 SUPPORTED_20000baseKR2_Full |
11339 SUPPORTED_20000baseMLD2_Full |
11341 SUPPORTED_Autoneg |
11343 SUPPORTED_Asym_Pause),
11344 .media_type = ETH_PHY_UNSPECIFIED,
11346 .req_flow_ctrl = 0,
11347 .req_line_speed = 0,
11348 .speed_cap_mask = 0,
11349 /* req_duplex = */0,
11351 .config_init = (config_init_t)bnx2x_warpcore_config_init,
11352 .read_status = (read_status_t)bnx2x_warpcore_read_status,
11353 .link_reset = (link_reset_t)bnx2x_warpcore_link_reset,
11354 .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
11355 .format_fw_ver = (format_fw_ver_t)NULL,
11356 .hw_reset = (hw_reset_t)bnx2x_warpcore_hw_reset,
11357 .set_link_led = (set_link_led_t)NULL,
11358 .phy_specific_func = (phy_specific_func_t)NULL
11362 static struct bnx2x_phy phy_7101 = {
11363 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
11366 .flags = FLAGS_FAN_FAILURE_DET_REQ,
11367 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11368 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11370 .supported = (SUPPORTED_10000baseT_Full |
11372 SUPPORTED_Autoneg |
11374 SUPPORTED_Asym_Pause),
11375 .media_type = ETH_PHY_BASE_T,
11377 .req_flow_ctrl = 0,
11378 .req_line_speed = 0,
11379 .speed_cap_mask = 0,
11382 .config_init = (config_init_t)bnx2x_7101_config_init,
11383 .read_status = (read_status_t)bnx2x_7101_read_status,
11384 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11385 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
11386 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver,
11387 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset,
11388 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led,
11389 .phy_specific_func = (phy_specific_func_t)NULL
11391 static struct bnx2x_phy phy_8073 = {
11392 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
11395 .flags = FLAGS_HW_LOCK_REQUIRED,
11396 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11397 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11399 .supported = (SUPPORTED_10000baseT_Full |
11400 SUPPORTED_2500baseX_Full |
11401 SUPPORTED_1000baseT_Full |
11403 SUPPORTED_Autoneg |
11405 SUPPORTED_Asym_Pause),
11406 .media_type = ETH_PHY_KR,
11408 .req_flow_ctrl = 0,
11409 .req_line_speed = 0,
11410 .speed_cap_mask = 0,
11413 .config_init = (config_init_t)bnx2x_8073_config_init,
11414 .read_status = (read_status_t)bnx2x_8073_read_status,
11415 .link_reset = (link_reset_t)bnx2x_8073_link_reset,
11416 .config_loopback = (config_loopback_t)NULL,
11417 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11418 .hw_reset = (hw_reset_t)NULL,
11419 .set_link_led = (set_link_led_t)NULL,
11420 .phy_specific_func = (phy_specific_func_t)NULL
11422 static struct bnx2x_phy phy_8705 = {
11423 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
11426 .flags = FLAGS_INIT_XGXS_FIRST,
11427 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11428 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11430 .supported = (SUPPORTED_10000baseT_Full |
11433 SUPPORTED_Asym_Pause),
11434 .media_type = ETH_PHY_XFP_FIBER,
11436 .req_flow_ctrl = 0,
11437 .req_line_speed = 0,
11438 .speed_cap_mask = 0,
11441 .config_init = (config_init_t)bnx2x_8705_config_init,
11442 .read_status = (read_status_t)bnx2x_8705_read_status,
11443 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11444 .config_loopback = (config_loopback_t)NULL,
11445 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver,
11446 .hw_reset = (hw_reset_t)NULL,
11447 .set_link_led = (set_link_led_t)NULL,
11448 .phy_specific_func = (phy_specific_func_t)NULL
11450 static struct bnx2x_phy phy_8706 = {
11451 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
11454 .flags = FLAGS_INIT_XGXS_FIRST,
11455 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11456 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11458 .supported = (SUPPORTED_10000baseT_Full |
11459 SUPPORTED_1000baseT_Full |
11462 SUPPORTED_Asym_Pause),
11463 .media_type = ETH_PHY_SFPP_10G_FIBER,
11465 .req_flow_ctrl = 0,
11466 .req_line_speed = 0,
11467 .speed_cap_mask = 0,
11470 .config_init = (config_init_t)bnx2x_8706_config_init,
11471 .read_status = (read_status_t)bnx2x_8706_read_status,
11472 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11473 .config_loopback = (config_loopback_t)NULL,
11474 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11475 .hw_reset = (hw_reset_t)NULL,
11476 .set_link_led = (set_link_led_t)NULL,
11477 .phy_specific_func = (phy_specific_func_t)NULL
11480 static struct bnx2x_phy phy_8726 = {
11481 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
11484 .flags = (FLAGS_HW_LOCK_REQUIRED |
11485 FLAGS_INIT_XGXS_FIRST |
11486 FLAGS_TX_ERROR_CHECK),
11487 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11488 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11490 .supported = (SUPPORTED_10000baseT_Full |
11491 SUPPORTED_1000baseT_Full |
11492 SUPPORTED_Autoneg |
11495 SUPPORTED_Asym_Pause),
11496 .media_type = ETH_PHY_NOT_PRESENT,
11498 .req_flow_ctrl = 0,
11499 .req_line_speed = 0,
11500 .speed_cap_mask = 0,
11503 .config_init = (config_init_t)bnx2x_8726_config_init,
11504 .read_status = (read_status_t)bnx2x_8726_read_status,
11505 .link_reset = (link_reset_t)bnx2x_8726_link_reset,
11506 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
11507 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11508 .hw_reset = (hw_reset_t)NULL,
11509 .set_link_led = (set_link_led_t)NULL,
11510 .phy_specific_func = (phy_specific_func_t)NULL
11513 static struct bnx2x_phy phy_8727 = {
11514 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
11517 .flags = (FLAGS_FAN_FAILURE_DET_REQ |
11518 FLAGS_TX_ERROR_CHECK),
11519 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11520 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11522 .supported = (SUPPORTED_10000baseT_Full |
11523 SUPPORTED_1000baseT_Full |
11526 SUPPORTED_Asym_Pause),
11527 .media_type = ETH_PHY_NOT_PRESENT,
11529 .req_flow_ctrl = 0,
11530 .req_line_speed = 0,
11531 .speed_cap_mask = 0,
11534 .config_init = (config_init_t)bnx2x_8727_config_init,
11535 .read_status = (read_status_t)bnx2x_8727_read_status,
11536 .link_reset = (link_reset_t)bnx2x_8727_link_reset,
11537 .config_loopback = (config_loopback_t)NULL,
11538 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11539 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset,
11540 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led,
11541 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
11543 static struct bnx2x_phy phy_8481 = {
11544 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
11547 .flags = FLAGS_FAN_FAILURE_DET_REQ |
11548 FLAGS_REARM_LATCH_SIGNAL,
11549 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11550 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11552 .supported = (SUPPORTED_10baseT_Half |
11553 SUPPORTED_10baseT_Full |
11554 SUPPORTED_100baseT_Half |
11555 SUPPORTED_100baseT_Full |
11556 SUPPORTED_1000baseT_Full |
11557 SUPPORTED_10000baseT_Full |
11559 SUPPORTED_Autoneg |
11561 SUPPORTED_Asym_Pause),
11562 .media_type = ETH_PHY_BASE_T,
11564 .req_flow_ctrl = 0,
11565 .req_line_speed = 0,
11566 .speed_cap_mask = 0,
11569 .config_init = (config_init_t)bnx2x_8481_config_init,
11570 .read_status = (read_status_t)bnx2x_848xx_read_status,
11571 .link_reset = (link_reset_t)bnx2x_8481_link_reset,
11572 .config_loopback = (config_loopback_t)NULL,
11573 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11574 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset,
11575 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11576 .phy_specific_func = (phy_specific_func_t)NULL
11579 static struct bnx2x_phy phy_84823 = {
11580 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
11583 .flags = (FLAGS_FAN_FAILURE_DET_REQ |
11584 FLAGS_REARM_LATCH_SIGNAL |
11585 FLAGS_TX_ERROR_CHECK),
11586 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11587 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11589 .supported = (SUPPORTED_10baseT_Half |
11590 SUPPORTED_10baseT_Full |
11591 SUPPORTED_100baseT_Half |
11592 SUPPORTED_100baseT_Full |
11593 SUPPORTED_1000baseT_Full |
11594 SUPPORTED_10000baseT_Full |
11596 SUPPORTED_Autoneg |
11598 SUPPORTED_Asym_Pause),
11599 .media_type = ETH_PHY_BASE_T,
11601 .req_flow_ctrl = 0,
11602 .req_line_speed = 0,
11603 .speed_cap_mask = 0,
11606 .config_init = (config_init_t)bnx2x_848x3_config_init,
11607 .read_status = (read_status_t)bnx2x_848xx_read_status,
11608 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
11609 .config_loopback = (config_loopback_t)NULL,
11610 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11611 .hw_reset = (hw_reset_t)NULL,
11612 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11613 .phy_specific_func = (phy_specific_func_t)NULL
11616 static struct bnx2x_phy phy_84833 = {
11617 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
11620 .flags = (FLAGS_FAN_FAILURE_DET_REQ |
11621 FLAGS_REARM_LATCH_SIGNAL |
11622 FLAGS_TX_ERROR_CHECK |
11624 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11625 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11627 .supported = (SUPPORTED_100baseT_Half |
11628 SUPPORTED_100baseT_Full |
11629 SUPPORTED_1000baseT_Full |
11630 SUPPORTED_10000baseT_Full |
11632 SUPPORTED_Autoneg |
11634 SUPPORTED_Asym_Pause),
11635 .media_type = ETH_PHY_BASE_T,
11637 .req_flow_ctrl = 0,
11638 .req_line_speed = 0,
11639 .speed_cap_mask = 0,
11642 .config_init = (config_init_t)bnx2x_848x3_config_init,
11643 .read_status = (read_status_t)bnx2x_848xx_read_status,
11644 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
11645 .config_loopback = (config_loopback_t)NULL,
11646 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11647 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11648 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11649 .phy_specific_func = (phy_specific_func_t)NULL
11652 static struct bnx2x_phy phy_54618se = {
11653 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
11656 .flags = FLAGS_INIT_XGXS_FIRST,
11657 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11658 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11660 .supported = (SUPPORTED_10baseT_Half |
11661 SUPPORTED_10baseT_Full |
11662 SUPPORTED_100baseT_Half |
11663 SUPPORTED_100baseT_Full |
11664 SUPPORTED_1000baseT_Full |
11666 SUPPORTED_Autoneg |
11668 SUPPORTED_Asym_Pause),
11669 .media_type = ETH_PHY_BASE_T,
11671 .req_flow_ctrl = 0,
11672 .req_line_speed = 0,
11673 .speed_cap_mask = 0,
11674 /* req_duplex = */0,
11676 .config_init = (config_init_t)bnx2x_54618se_config_init,
11677 .read_status = (read_status_t)bnx2x_54618se_read_status,
11678 .link_reset = (link_reset_t)bnx2x_54618se_link_reset,
11679 .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
11680 .format_fw_ver = (format_fw_ver_t)NULL,
11681 .hw_reset = (hw_reset_t)NULL,
11682 .set_link_led = (set_link_led_t)bnx2x_5461x_set_link_led,
11683 .phy_specific_func = (phy_specific_func_t)NULL
11685 /*****************************************************************/
11687 /* Populate the phy according. Main function: bnx2x_populate_phy */
11689 /*****************************************************************/
11691 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
11692 struct bnx2x_phy *phy, u8 port,
11695 /* Get the 4 lanes xgxs config rx and tx */
11696 u32 rx = 0, tx = 0, i;
11697 for (i = 0; i < 2; i++) {
11698 /* INT_PHY and EXT_PHY1 share the same value location in
11699 * the shmem. When num_phys is greater than 1, than this value
11700 * applies only to EXT_PHY1
11702 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
11703 rx = REG_RD(bp, shmem_base +
11704 offsetof(struct shmem_region,
11705 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
11707 tx = REG_RD(bp, shmem_base +
11708 offsetof(struct shmem_region,
11709 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
11711 rx = REG_RD(bp, shmem_base +
11712 offsetof(struct shmem_region,
11713 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11715 tx = REG_RD(bp, shmem_base +
11716 offsetof(struct shmem_region,
11717 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11720 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
11721 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11723 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
11724 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11728 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11729 u8 phy_index, u8 port)
11731 u32 ext_phy_config = 0;
11732 switch (phy_index) {
11734 ext_phy_config = REG_RD(bp, shmem_base +
11735 offsetof(struct shmem_region,
11736 dev_info.port_hw_config[port].external_phy_config));
11739 ext_phy_config = REG_RD(bp, shmem_base +
11740 offsetof(struct shmem_region,
11741 dev_info.port_hw_config[port].external_phy_config2));
11744 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11748 return ext_phy_config;
11750 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11751 struct bnx2x_phy *phy)
11755 u32 switch_cfg = (REG_RD(bp, shmem_base +
11756 offsetof(struct shmem_region,
11757 dev_info.port_feature_config[port].link_config)) &
11758 PORT_FEATURE_CONNECTED_SWITCH_MASK);
11759 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
11760 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
11762 DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11763 if (USES_WARPCORE(bp)) {
11765 phy_addr = REG_RD(bp,
11766 MISC_REG_WC0_CTRL_PHY_ADDR);
11767 *phy = phy_warpcore;
11768 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11769 phy->flags |= FLAGS_4_PORT_MODE;
11771 phy->flags &= ~FLAGS_4_PORT_MODE;
11772 /* Check Dual mode */
11773 serdes_net_if = (REG_RD(bp, shmem_base +
11774 offsetof(struct shmem_region, dev_info.
11775 port_hw_config[port].default_cfg)) &
11776 PORT_HW_CFG_NET_SERDES_IF_MASK);
11777 /* Set the appropriate supported and flags indications per
11778 * interface type of the chip
11780 switch (serdes_net_if) {
11781 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11782 phy->supported &= (SUPPORTED_10baseT_Half |
11783 SUPPORTED_10baseT_Full |
11784 SUPPORTED_100baseT_Half |
11785 SUPPORTED_100baseT_Full |
11786 SUPPORTED_1000baseT_Full |
11788 SUPPORTED_Autoneg |
11790 SUPPORTED_Asym_Pause);
11791 phy->media_type = ETH_PHY_BASE_T;
11793 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11794 phy->media_type = ETH_PHY_XFP_FIBER;
11796 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11797 phy->supported &= (SUPPORTED_1000baseT_Full |
11798 SUPPORTED_10000baseT_Full |
11801 SUPPORTED_Asym_Pause);
11802 phy->media_type = ETH_PHY_SFPP_10G_FIBER;
11804 case PORT_HW_CFG_NET_SERDES_IF_KR:
11805 phy->media_type = ETH_PHY_KR;
11806 phy->supported &= (SUPPORTED_1000baseT_Full |
11807 SUPPORTED_10000baseT_Full |
11809 SUPPORTED_Autoneg |
11811 SUPPORTED_Asym_Pause);
11813 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11814 phy->media_type = ETH_PHY_KR;
11815 phy->flags |= FLAGS_WC_DUAL_MODE;
11816 phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11819 SUPPORTED_Asym_Pause);
11821 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11822 phy->media_type = ETH_PHY_KR;
11823 phy->flags |= FLAGS_WC_DUAL_MODE;
11824 phy->supported &= (SUPPORTED_20000baseKR2_Full |
11827 SUPPORTED_Asym_Pause);
11830 DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
11835 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
11836 * was not set as expected. For B0, ECO will be enabled so there
11837 * won't be an issue there
11839 if (CHIP_REV(bp) == CHIP_REV_Ax)
11840 phy->flags |= FLAGS_MDC_MDIO_WA;
11842 phy->flags |= FLAGS_MDC_MDIO_WA_B0;
11844 switch (switch_cfg) {
11845 case SWITCH_CFG_1G:
11846 phy_addr = REG_RD(bp,
11847 NIG_REG_SERDES0_CTRL_PHY_ADDR +
11851 case SWITCH_CFG_10G:
11852 phy_addr = REG_RD(bp,
11853 NIG_REG_XGXS0_CTRL_PHY_ADDR +
11858 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
11862 phy->addr = (u8)phy_addr;
11863 phy->mdio_ctrl = bnx2x_get_emac_base(bp,
11864 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11866 if (CHIP_IS_E2(bp))
11867 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
11869 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
11871 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
11872 port, phy->addr, phy->mdio_ctrl);
11874 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
11878 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
11883 struct bnx2x_phy *phy)
11885 u32 ext_phy_config, phy_type, config2;
11886 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11887 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
11889 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11890 /* Select the phy type */
11891 switch (phy_type) {
11892 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
11893 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
11896 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
11899 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
11902 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
11903 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11906 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
11907 /* BCM8727_NOC => BCM8727 no over current */
11908 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11910 phy->flags |= FLAGS_NOC;
11912 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
11913 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
11914 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11917 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
11920 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
11923 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
11926 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
11927 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
11928 *phy = phy_54618se;
11930 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
11933 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
11938 /* In case external PHY wasn't found */
11939 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
11940 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11945 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
11946 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
11948 /* The shmem address of the phy version is located on different
11949 * structures. In case this structure is too old, do not set
11952 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
11953 dev_info.shared_hw_config.config2));
11954 if (phy_index == EXT_PHY1) {
11955 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
11956 port_mb[port].ext_phy_fw_version);
11958 /* Check specific mdc mdio settings */
11959 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
11960 mdc_mdio_access = config2 &
11961 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
11963 u32 size = REG_RD(bp, shmem2_base);
11966 offsetof(struct shmem2_region, ext_phy_fw_version2)) {
11967 phy->ver_addr = shmem2_base +
11968 offsetof(struct shmem2_region,
11969 ext_phy_fw_version2[port]);
11971 /* Check specific mdc mdio settings */
11972 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
11973 mdc_mdio_access = (config2 &
11974 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
11975 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
11976 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
11978 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
11980 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
11982 /* Remove 100Mb link supported for BCM84833 when phy fw
11983 * version lower than or equal to 1.39
11985 u32 raw_ver = REG_RD(bp, phy->ver_addr);
11986 if (((raw_ver & 0x7F) <= 39) &&
11987 (((raw_ver & 0xF80) >> 7) <= 1))
11988 phy->supported &= ~(SUPPORTED_100baseT_Half |
11989 SUPPORTED_100baseT_Full);
11992 /* In case mdc/mdio_access of the external phy is different than the
11993 * mdc/mdio access of the XGXS, a HW lock must be taken in each access
11994 * to prevent one port interfere with another port's CL45 operations.
11996 if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
11997 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
11998 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
11999 phy_type, port, phy_index);
12000 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n",
12001 phy->addr, phy->mdio_ctrl);
12005 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
12006 u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
12009 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
12010 if (phy_index == INT_PHY)
12011 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
12012 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
12017 static void bnx2x_phy_def_cfg(struct link_params *params,
12018 struct bnx2x_phy *phy,
12021 struct bnx2x *bp = params->bp;
12023 /* Populate the default phy configuration for MF mode */
12024 if (phy_index == EXT_PHY2) {
12025 link_config = REG_RD(bp, params->shmem_base +
12026 offsetof(struct shmem_region, dev_info.
12027 port_feature_config[params->port].link_config2));
12028 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12029 offsetof(struct shmem_region,
12031 port_hw_config[params->port].speed_capability_mask2));
12033 link_config = REG_RD(bp, params->shmem_base +
12034 offsetof(struct shmem_region, dev_info.
12035 port_feature_config[params->port].link_config));
12036 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12037 offsetof(struct shmem_region,
12039 port_hw_config[params->port].speed_capability_mask));
12042 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
12043 phy_index, link_config, phy->speed_cap_mask);
12045 phy->req_duplex = DUPLEX_FULL;
12046 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
12047 case PORT_FEATURE_LINK_SPEED_10M_HALF:
12048 phy->req_duplex = DUPLEX_HALF;
12049 case PORT_FEATURE_LINK_SPEED_10M_FULL:
12050 phy->req_line_speed = SPEED_10;
12052 case PORT_FEATURE_LINK_SPEED_100M_HALF:
12053 phy->req_duplex = DUPLEX_HALF;
12054 case PORT_FEATURE_LINK_SPEED_100M_FULL:
12055 phy->req_line_speed = SPEED_100;
12057 case PORT_FEATURE_LINK_SPEED_1G:
12058 phy->req_line_speed = SPEED_1000;
12060 case PORT_FEATURE_LINK_SPEED_2_5G:
12061 phy->req_line_speed = SPEED_2500;
12063 case PORT_FEATURE_LINK_SPEED_10G_CX4:
12064 phy->req_line_speed = SPEED_10000;
12067 phy->req_line_speed = SPEED_AUTO_NEG;
12071 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
12072 case PORT_FEATURE_FLOW_CONTROL_AUTO:
12073 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
12075 case PORT_FEATURE_FLOW_CONTROL_TX:
12076 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
12078 case PORT_FEATURE_FLOW_CONTROL_RX:
12079 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
12081 case PORT_FEATURE_FLOW_CONTROL_BOTH:
12082 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
12085 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12090 u32 bnx2x_phy_selection(struct link_params *params)
12092 u32 phy_config_swapped, prio_cfg;
12093 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
12095 phy_config_swapped = params->multi_phy_config &
12096 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12098 prio_cfg = params->multi_phy_config &
12099 PORT_HW_CFG_PHY_SELECTION_MASK;
12101 if (phy_config_swapped) {
12102 switch (prio_cfg) {
12103 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
12104 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
12106 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
12107 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
12109 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
12110 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
12112 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
12113 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
12117 return_cfg = prio_cfg;
12123 int bnx2x_phy_probe(struct link_params *params)
12125 u8 phy_index, actual_phy_idx;
12126 u32 phy_config_swapped, sync_offset, media_types;
12127 struct bnx2x *bp = params->bp;
12128 struct bnx2x_phy *phy;
12129 params->num_phys = 0;
12130 DP(NETIF_MSG_LINK, "Begin phy probe\n");
12131 phy_config_swapped = params->multi_phy_config &
12132 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12134 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12136 actual_phy_idx = phy_index;
12137 if (phy_config_swapped) {
12138 if (phy_index == EXT_PHY1)
12139 actual_phy_idx = EXT_PHY2;
12140 else if (phy_index == EXT_PHY2)
12141 actual_phy_idx = EXT_PHY1;
12143 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
12144 " actual_phy_idx %x\n", phy_config_swapped,
12145 phy_index, actual_phy_idx);
12146 phy = ¶ms->phy[actual_phy_idx];
12147 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
12148 params->shmem2_base, params->port,
12150 params->num_phys = 0;
12151 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
12153 for (phy_index = INT_PHY;
12154 phy_index < MAX_PHYS;
12159 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
12162 if (params->feature_config_flags &
12163 FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
12164 phy->flags &= ~FLAGS_TX_ERROR_CHECK;
12166 sync_offset = params->shmem_base +
12167 offsetof(struct shmem_region,
12168 dev_info.port_hw_config[params->port].media_type);
12169 media_types = REG_RD(bp, sync_offset);
12171 /* Update media type for non-PMF sync only for the first time
12172 * In case the media type changes afterwards, it will be updated
12173 * using the update_status function
12175 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
12176 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12177 actual_phy_idx))) == 0) {
12178 media_types |= ((phy->media_type &
12179 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
12180 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12183 REG_WR(bp, sync_offset, media_types);
12185 bnx2x_phy_def_cfg(params, phy, phy_index);
12186 params->num_phys++;
12189 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
12193 void bnx2x_init_bmac_loopback(struct link_params *params,
12194 struct link_vars *vars)
12196 struct bnx2x *bp = params->bp;
12198 vars->line_speed = SPEED_10000;
12199 vars->duplex = DUPLEX_FULL;
12200 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12201 vars->mac_type = MAC_TYPE_BMAC;
12203 vars->phy_flags = PHY_XGXS_FLAG;
12205 bnx2x_xgxs_deassert(params);
12207 /* set bmac loopback */
12208 bnx2x_bmac_enable(params, vars, 1);
12210 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12213 void bnx2x_init_emac_loopback(struct link_params *params,
12214 struct link_vars *vars)
12216 struct bnx2x *bp = params->bp;
12218 vars->line_speed = SPEED_1000;
12219 vars->duplex = DUPLEX_FULL;
12220 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12221 vars->mac_type = MAC_TYPE_EMAC;
12223 vars->phy_flags = PHY_XGXS_FLAG;
12225 bnx2x_xgxs_deassert(params);
12226 /* set bmac loopback */
12227 bnx2x_emac_enable(params, vars, 1);
12228 bnx2x_emac_program(params, vars);
12229 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12232 void bnx2x_init_xmac_loopback(struct link_params *params,
12233 struct link_vars *vars)
12235 struct bnx2x *bp = params->bp;
12237 if (!params->req_line_speed[0])
12238 vars->line_speed = SPEED_10000;
12240 vars->line_speed = params->req_line_speed[0];
12241 vars->duplex = DUPLEX_FULL;
12242 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12243 vars->mac_type = MAC_TYPE_XMAC;
12244 vars->phy_flags = PHY_XGXS_FLAG;
12245 /* Set WC to loopback mode since link is required to provide clock
12246 * to the XMAC in 20G mode
12248 bnx2x_set_aer_mmd(params, ¶ms->phy[0]);
12249 bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0);
12250 params->phy[INT_PHY].config_loopback(
12251 ¶ms->phy[INT_PHY],
12254 bnx2x_xmac_enable(params, vars, 1);
12255 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12258 void bnx2x_init_umac_loopback(struct link_params *params,
12259 struct link_vars *vars)
12261 struct bnx2x *bp = params->bp;
12263 vars->line_speed = SPEED_1000;
12264 vars->duplex = DUPLEX_FULL;
12265 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12266 vars->mac_type = MAC_TYPE_UMAC;
12267 vars->phy_flags = PHY_XGXS_FLAG;
12268 bnx2x_umac_enable(params, vars, 1);
12270 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12273 void bnx2x_init_xgxs_loopback(struct link_params *params,
12274 struct link_vars *vars)
12276 struct bnx2x *bp = params->bp;
12278 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12279 vars->duplex = DUPLEX_FULL;
12280 if (params->req_line_speed[0] == SPEED_1000)
12281 vars->line_speed = SPEED_1000;
12283 vars->line_speed = SPEED_10000;
12285 if (!USES_WARPCORE(bp))
12286 bnx2x_xgxs_deassert(params);
12287 bnx2x_link_initialize(params, vars);
12289 if (params->req_line_speed[0] == SPEED_1000) {
12290 if (USES_WARPCORE(bp))
12291 bnx2x_umac_enable(params, vars, 0);
12293 bnx2x_emac_program(params, vars);
12294 bnx2x_emac_enable(params, vars, 0);
12297 if (USES_WARPCORE(bp))
12298 bnx2x_xmac_enable(params, vars, 0);
12300 bnx2x_bmac_enable(params, vars, 0);
12303 if (params->loopback_mode == LOOPBACK_XGXS) {
12304 /* set 10G XGXS loopback */
12305 params->phy[INT_PHY].config_loopback(
12306 ¶ms->phy[INT_PHY],
12310 /* set external phy loopback */
12312 for (phy_index = EXT_PHY1;
12313 phy_index < params->num_phys; phy_index++) {
12314 if (params->phy[phy_index].config_loopback)
12315 params->phy[phy_index].config_loopback(
12316 ¶ms->phy[phy_index],
12320 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12322 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
12325 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
12327 struct bnx2x *bp = params->bp;
12328 DP(NETIF_MSG_LINK, "Phy Initialization started\n");
12329 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
12330 params->req_line_speed[0], params->req_flow_ctrl[0]);
12331 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
12332 params->req_line_speed[1], params->req_flow_ctrl[1]);
12333 vars->link_status = 0;
12334 vars->phy_link_up = 0;
12336 vars->line_speed = 0;
12337 vars->duplex = DUPLEX_FULL;
12338 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12339 vars->mac_type = MAC_TYPE_NONE;
12340 vars->phy_flags = 0;
12342 /* Disable attentions */
12343 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12344 (NIG_MASK_XGXS0_LINK_STATUS |
12345 NIG_MASK_XGXS0_LINK10G |
12346 NIG_MASK_SERDES0_LINK_STATUS |
12349 bnx2x_emac_init(params, vars);
12351 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
12352 vars->link_status |= LINK_STATUS_PFC_ENABLED;
12354 if (params->num_phys == 0) {
12355 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
12358 set_phy_vars(params, vars);
12360 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
12361 switch (params->loopback_mode) {
12362 case LOOPBACK_BMAC:
12363 bnx2x_init_bmac_loopback(params, vars);
12365 case LOOPBACK_EMAC:
12366 bnx2x_init_emac_loopback(params, vars);
12368 case LOOPBACK_XMAC:
12369 bnx2x_init_xmac_loopback(params, vars);
12371 case LOOPBACK_UMAC:
12372 bnx2x_init_umac_loopback(params, vars);
12374 case LOOPBACK_XGXS:
12375 case LOOPBACK_EXT_PHY:
12376 bnx2x_init_xgxs_loopback(params, vars);
12379 if (!CHIP_IS_E3(bp)) {
12380 if (params->switch_cfg == SWITCH_CFG_10G)
12381 bnx2x_xgxs_deassert(params);
12383 bnx2x_serdes_deassert(bp, params->port);
12385 bnx2x_link_initialize(params, vars);
12387 bnx2x_link_int_enable(params);
12390 bnx2x_update_mng(params, vars->link_status);
12392 bnx2x_update_mng_eee(params, vars->eee_status);
12396 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
12399 struct bnx2x *bp = params->bp;
12400 u8 phy_index, port = params->port, clear_latch_ind = 0;
12401 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
12402 /* Disable attentions */
12403 vars->link_status = 0;
12404 bnx2x_update_mng(params, vars->link_status);
12405 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
12406 SHMEM_EEE_ACTIVE_BIT);
12407 bnx2x_update_mng_eee(params, vars->eee_status);
12408 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
12409 (NIG_MASK_XGXS0_LINK_STATUS |
12410 NIG_MASK_XGXS0_LINK10G |
12411 NIG_MASK_SERDES0_LINK_STATUS |
12414 /* Activate nig drain */
12415 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
12417 /* Disable nig egress interface */
12418 if (!CHIP_IS_E3(bp)) {
12419 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
12420 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
12423 /* Stop BigMac rx */
12424 if (!CHIP_IS_E3(bp))
12425 bnx2x_bmac_rx_disable(bp, port);
12427 bnx2x_xmac_disable(params);
12428 bnx2x_umac_disable(params);
12431 if (!CHIP_IS_E3(bp))
12432 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
12434 usleep_range(10000, 20000);
12435 /* The PHY reset is controlled by GPIO 1
12436 * Hold it as vars low
12438 /* Clear link led */
12439 bnx2x_set_mdio_clk(bp, params->chip_id, port);
12440 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
12442 if (reset_ext_phy) {
12443 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
12445 if (params->phy[phy_index].link_reset) {
12446 bnx2x_set_aer_mmd(params,
12447 ¶ms->phy[phy_index]);
12448 params->phy[phy_index].link_reset(
12449 ¶ms->phy[phy_index],
12452 if (params->phy[phy_index].flags &
12453 FLAGS_REARM_LATCH_SIGNAL)
12454 clear_latch_ind = 1;
12458 if (clear_latch_ind) {
12459 /* Clear latching indication */
12460 bnx2x_rearm_latch_signal(bp, port, 0);
12461 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
12462 1 << NIG_LATCH_BC_ENABLE_MI_INT);
12464 if (params->phy[INT_PHY].link_reset)
12465 params->phy[INT_PHY].link_reset(
12466 ¶ms->phy[INT_PHY], params);
12468 /* Disable nig ingress interface */
12469 if (!CHIP_IS_E3(bp)) {
12471 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
12472 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
12473 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
12474 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
12476 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12477 bnx2x_set_xumac_nig(params, 0, 0);
12478 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12479 MISC_REGISTERS_RESET_REG_2_XMAC)
12480 REG_WR(bp, xmac_base + XMAC_REG_CTRL,
12481 XMAC_CTRL_REG_SOFT_RESET);
12484 vars->phy_flags = 0;
12488 /****************************************************************************/
12489 /* Common function */
12490 /****************************************************************************/
12491 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
12492 u32 shmem_base_path[],
12493 u32 shmem2_base_path[], u8 phy_index,
12496 struct bnx2x_phy phy[PORT_MAX];
12497 struct bnx2x_phy *phy_blk[PORT_MAX];
12500 s8 port_of_path = 0;
12501 u32 swap_val, swap_override;
12502 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12503 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12504 port ^= (swap_val && swap_override);
12505 bnx2x_ext_phy_hw_reset(bp, port);
12506 /* PART1 - Reset both phys */
12507 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12508 u32 shmem_base, shmem2_base;
12509 /* In E2, same phy is using for port0 of the two paths */
12510 if (CHIP_IS_E1x(bp)) {
12511 shmem_base = shmem_base_path[0];
12512 shmem2_base = shmem2_base_path[0];
12513 port_of_path = port;
12515 shmem_base = shmem_base_path[port];
12516 shmem2_base = shmem2_base_path[port];
12520 /* Extract the ext phy address for the port */
12521 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12522 port_of_path, &phy[port]) !=
12524 DP(NETIF_MSG_LINK, "populate_phy failed\n");
12527 /* Disable attentions */
12528 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12530 (NIG_MASK_XGXS0_LINK_STATUS |
12531 NIG_MASK_XGXS0_LINK10G |
12532 NIG_MASK_SERDES0_LINK_STATUS |
12535 /* Need to take the phy out of low power mode in order
12536 * to write to access its registers
12538 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12539 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12542 /* Reset the phy */
12543 bnx2x_cl45_write(bp, &phy[port],
12549 /* Add delay of 150ms after reset */
12552 if (phy[PORT_0].addr & 0x1) {
12553 phy_blk[PORT_0] = &(phy[PORT_1]);
12554 phy_blk[PORT_1] = &(phy[PORT_0]);
12556 phy_blk[PORT_0] = &(phy[PORT_0]);
12557 phy_blk[PORT_1] = &(phy[PORT_1]);
12560 /* PART2 - Download firmware to both phys */
12561 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12562 if (CHIP_IS_E1x(bp))
12563 port_of_path = port;
12567 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12568 phy_blk[port]->addr);
12569 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12573 /* Only set bit 10 = 1 (Tx power down) */
12574 bnx2x_cl45_read(bp, phy_blk[port],
12576 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12578 /* Phase1 of TX_POWER_DOWN reset */
12579 bnx2x_cl45_write(bp, phy_blk[port],
12581 MDIO_PMA_REG_TX_POWER_DOWN,
12585 /* Toggle Transmitter: Power down and then up with 600ms delay
12590 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12591 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12592 /* Phase2 of POWER_DOWN_RESET */
12593 /* Release bit 10 (Release Tx power down) */
12594 bnx2x_cl45_read(bp, phy_blk[port],
12596 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12598 bnx2x_cl45_write(bp, phy_blk[port],
12600 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
12601 usleep_range(15000, 30000);
12603 /* Read modify write the SPI-ROM version select register */
12604 bnx2x_cl45_read(bp, phy_blk[port],
12606 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
12607 bnx2x_cl45_write(bp, phy_blk[port],
12609 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
12611 /* set GPIO2 back to LOW */
12612 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12613 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
12617 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
12618 u32 shmem_base_path[],
12619 u32 shmem2_base_path[], u8 phy_index,
12624 struct bnx2x_phy phy;
12625 /* Use port1 because of the static port-swap */
12626 /* Enable the module detection interrupt */
12627 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12628 val |= ((1<<MISC_REGISTERS_GPIO_3)|
12629 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
12630 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12632 bnx2x_ext_phy_hw_reset(bp, 0);
12633 usleep_range(5000, 10000);
12634 for (port = 0; port < PORT_MAX; port++) {
12635 u32 shmem_base, shmem2_base;
12637 /* In E2, same phy is using for port0 of the two paths */
12638 if (CHIP_IS_E1x(bp)) {
12639 shmem_base = shmem_base_path[0];
12640 shmem2_base = shmem2_base_path[0];
12642 shmem_base = shmem_base_path[port];
12643 shmem2_base = shmem2_base_path[port];
12645 /* Extract the ext phy address for the port */
12646 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12649 DP(NETIF_MSG_LINK, "populate phy failed\n");
12654 bnx2x_cl45_write(bp, &phy,
12655 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
12658 /* Set fault module detected LED on */
12659 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
12660 MISC_REGISTERS_GPIO_HIGH,
12666 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
12667 u8 *io_gpio, u8 *io_port)
12670 u32 phy_gpio_reset = REG_RD(bp, shmem_base +
12671 offsetof(struct shmem_region,
12672 dev_info.port_hw_config[PORT_0].default_cfg));
12673 switch (phy_gpio_reset) {
12674 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
12678 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
12682 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
12686 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
12690 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
12694 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
12698 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
12702 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
12707 /* Don't override the io_gpio and io_port */
12712 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
12713 u32 shmem_base_path[],
12714 u32 shmem2_base_path[], u8 phy_index,
12717 s8 port, reset_gpio;
12718 u32 swap_val, swap_override;
12719 struct bnx2x_phy phy[PORT_MAX];
12720 struct bnx2x_phy *phy_blk[PORT_MAX];
12722 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12723 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12725 reset_gpio = MISC_REGISTERS_GPIO_1;
12728 /* Retrieve the reset gpio/port which control the reset.
12729 * Default is GPIO1, PORT1
12731 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
12732 (u8 *)&reset_gpio, (u8 *)&port);
12734 /* Calculate the port based on port swap */
12735 port ^= (swap_val && swap_override);
12737 /* Initiate PHY reset*/
12738 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
12740 usleep_range(1000, 2000);
12741 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12744 usleep_range(5000, 10000);
12746 /* PART1 - Reset both phys */
12747 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12748 u32 shmem_base, shmem2_base;
12750 /* In E2, same phy is using for port0 of the two paths */
12751 if (CHIP_IS_E1x(bp)) {
12752 shmem_base = shmem_base_path[0];
12753 shmem2_base = shmem2_base_path[0];
12754 port_of_path = port;
12756 shmem_base = shmem_base_path[port];
12757 shmem2_base = shmem2_base_path[port];
12761 /* Extract the ext phy address for the port */
12762 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12763 port_of_path, &phy[port]) !=
12765 DP(NETIF_MSG_LINK, "populate phy failed\n");
12768 /* disable attentions */
12769 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12771 (NIG_MASK_XGXS0_LINK_STATUS |
12772 NIG_MASK_XGXS0_LINK10G |
12773 NIG_MASK_SERDES0_LINK_STATUS |
12777 /* Reset the phy */
12778 bnx2x_cl45_write(bp, &phy[port],
12779 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
12782 /* Add delay of 150ms after reset */
12784 if (phy[PORT_0].addr & 0x1) {
12785 phy_blk[PORT_0] = &(phy[PORT_1]);
12786 phy_blk[PORT_1] = &(phy[PORT_0]);
12788 phy_blk[PORT_0] = &(phy[PORT_0]);
12789 phy_blk[PORT_1] = &(phy[PORT_1]);
12791 /* PART2 - Download firmware to both phys */
12792 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12793 if (CHIP_IS_E1x(bp))
12794 port_of_path = port;
12797 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12798 phy_blk[port]->addr);
12799 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12802 /* Disable PHY transmitter output */
12803 bnx2x_cl45_write(bp, phy_blk[port],
12805 MDIO_PMA_REG_TX_DISABLE, 1);
12811 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
12812 u32 shmem_base_path[],
12813 u32 shmem2_base_path[],
12818 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
12819 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
12821 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
12822 DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
12827 static int bnx2x_84833_pre_init_phy(struct bnx2x *bp,
12828 struct bnx2x_phy *phy)
12831 /* Wait for FW completing its initialization. */
12832 for (cnt = 0; cnt < 1500; cnt++) {
12833 bnx2x_cl45_read(bp, phy,
12835 MDIO_PMA_REG_CTRL, &val);
12836 if (!(val & (1<<15)))
12838 usleep_range(1000, 2000);
12841 DP(NETIF_MSG_LINK, "84833 reset timeout\n");
12845 /* Put the port in super isolate mode. */
12846 bnx2x_cl45_read(bp, phy,
12848 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
12849 val |= MDIO_84833_SUPER_ISOLATE;
12850 bnx2x_cl45_write(bp, phy,
12852 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
12854 /* Save spirom version */
12855 bnx2x_save_848xx_spirom_version(phy, bp, PORT_0);
12859 int bnx2x_pre_init_phy(struct bnx2x *bp,
12865 struct bnx2x_phy phy;
12866 bnx2x_set_mdio_clk(bp, chip_id, PORT_0);
12867 if (bnx2x_populate_phy(bp, EXT_PHY1, shmem_base, shmem2_base,
12869 DP(NETIF_MSG_LINK, "populate_phy failed\n");
12872 switch (phy.type) {
12873 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12874 rc = bnx2x_84833_pre_init_phy(bp, &phy);
12882 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
12883 u32 shmem2_base_path[], u8 phy_index,
12884 u32 ext_phy_type, u32 chip_id)
12888 switch (ext_phy_type) {
12889 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12890 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
12892 phy_index, chip_id);
12894 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12895 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12896 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12897 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
12899 phy_index, chip_id);
12902 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12903 /* GPIO1 affects both ports, so there's need to pull
12904 * it for single port alone
12906 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
12908 phy_index, chip_id);
12910 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12911 /* GPIO3's are linked, and so both need to be toggled
12912 * to obtain required 2us pulse.
12914 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path,
12916 phy_index, chip_id);
12918 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12923 "ext_phy 0x%x common init not required\n",
12929 netdev_err(bp->dev, "Warning: PHY was not initialized,"
12935 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
12936 u32 shmem2_base_path[], u32 chip_id)
12941 u32 ext_phy_type, ext_phy_config;
12942 bnx2x_set_mdio_clk(bp, chip_id, PORT_0);
12943 bnx2x_set_mdio_clk(bp, chip_id, PORT_1);
12944 DP(NETIF_MSG_LINK, "Begin common phy init\n");
12945 if (CHIP_IS_E3(bp)) {
12947 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
12948 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
12950 /* Check if common init was already done */
12951 phy_ver = REG_RD(bp, shmem_base_path[0] +
12952 offsetof(struct shmem_region,
12953 port_mb[PORT_0].ext_phy_fw_version));
12955 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
12960 /* Read the ext_phy_type for arbitrary port(0) */
12961 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12963 ext_phy_config = bnx2x_get_ext_phy_config(bp,
12964 shmem_base_path[0],
12966 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
12967 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
12969 phy_index, ext_phy_type,
12975 static void bnx2x_check_over_curr(struct link_params *params,
12976 struct link_vars *vars)
12978 struct bnx2x *bp = params->bp;
12980 u8 port = params->port;
12983 cfg_pin = (REG_RD(bp, params->shmem_base +
12984 offsetof(struct shmem_region,
12985 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
12986 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
12987 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
12989 /* Ignore check if no external input PIN available */
12990 if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
12994 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
12995 netdev_err(bp->dev, "Error: Power fault on Port %d has"
12996 " been detected and the power to "
12997 "that SFP+ module has been removed"
12998 " to prevent failure of the card."
12999 " Please remove the SFP+ module and"
13000 " restart the system to clear this"
13003 vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
13006 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
13009 /* Returns 0 if no change occured since last check; 1 otherwise. */
13010 static u8 bnx2x_analyze_link_error(struct link_params *params,
13011 struct link_vars *vars, u32 status,
13012 u32 phy_flag, u32 link_flag, u8 notify)
13014 struct bnx2x *bp = params->bp;
13015 /* Compare new value with previous value */
13017 u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
13019 if ((status ^ old_status) == 0)
13022 /* If values differ */
13023 switch (phy_flag) {
13024 case PHY_HALF_OPEN_CONN_FLAG:
13025 DP(NETIF_MSG_LINK, "Analyze Remote Fault\n");
13027 case PHY_SFP_TX_FAULT_FLAG:
13028 DP(NETIF_MSG_LINK, "Analyze TX Fault\n");
13031 DP(NETIF_MSG_LINK, "Analyze UNKOWN\n");
13033 DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up,
13034 old_status, status);
13036 /* a. Update shmem->link_status accordingly
13037 * b. Update link_vars->link_up
13040 vars->link_status &= ~LINK_STATUS_LINK_UP;
13041 vars->link_status |= link_flag;
13043 vars->phy_flags |= phy_flag;
13045 /* activate nig drain */
13046 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
13047 /* Set LED mode to off since the PHY doesn't know about these
13050 led_mode = LED_MODE_OFF;
13052 vars->link_status |= LINK_STATUS_LINK_UP;
13053 vars->link_status &= ~link_flag;
13055 vars->phy_flags &= ~phy_flag;
13056 led_mode = LED_MODE_OPER;
13058 /* Clear nig drain */
13059 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13061 bnx2x_sync_link(params, vars);
13062 /* Update the LED according to the link state */
13063 bnx2x_set_led(params, vars, led_mode, SPEED_10000);
13065 /* Update link status in the shared memory */
13066 bnx2x_update_mng(params, vars->link_status);
13068 /* C. Trigger General Attention */
13069 vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
13071 bnx2x_notify_link_changed(bp);
13076 /******************************************************************************
13078 * This function checks for half opened connection change indication.
13079 * When such change occurs, it calls the bnx2x_analyze_link_error
13080 * to check if Remote Fault is set or cleared. Reception of remote fault
13081 * status message in the MAC indicates that the peer's MAC has detected
13082 * a fault, for example, due to break in the TX side of fiber.
13084 ******************************************************************************/
13085 int bnx2x_check_half_open_conn(struct link_params *params,
13086 struct link_vars *vars,
13089 struct bnx2x *bp = params->bp;
13090 u32 lss_status = 0;
13092 /* In case link status is physically up @ 10G do */
13093 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
13094 (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
13097 if (CHIP_IS_E3(bp) &&
13098 (REG_RD(bp, MISC_REG_RESET_REG_2) &
13099 (MISC_REGISTERS_RESET_REG_2_XMAC))) {
13100 /* Check E3 XMAC */
13101 /* Note that link speed cannot be queried here, since it may be
13102 * zero while link is down. In case UMAC is active, LSS will
13103 * simply not be set
13105 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13107 /* Clear stick bits (Requires rising edge) */
13108 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
13109 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
13110 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
13111 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
13112 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
13115 bnx2x_analyze_link_error(params, vars, lss_status,
13116 PHY_HALF_OPEN_CONN_FLAG,
13117 LINK_STATUS_NONE, notify);
13118 } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
13119 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
13120 /* Check E1X / E2 BMAC */
13121 u32 lss_status_reg;
13123 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
13124 NIG_REG_INGRESS_BMAC0_MEM;
13125 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
13126 if (CHIP_IS_E2(bp))
13127 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
13129 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
13131 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
13132 lss_status = (wb_data[0] > 0);
13134 bnx2x_analyze_link_error(params, vars, lss_status,
13135 PHY_HALF_OPEN_CONN_FLAG,
13136 LINK_STATUS_NONE, notify);
13140 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy,
13141 struct link_params *params,
13142 struct link_vars *vars)
13144 struct bnx2x *bp = params->bp;
13145 u32 cfg_pin, value = 0;
13146 u8 led_change, port = params->port;
13148 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
13149 cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region,
13150 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
13151 PORT_HW_CFG_E3_TX_FAULT_MASK) >>
13152 PORT_HW_CFG_E3_TX_FAULT_SHIFT;
13154 if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) {
13155 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin);
13159 led_change = bnx2x_analyze_link_error(params, vars, value,
13160 PHY_SFP_TX_FAULT_FLAG,
13161 LINK_STATUS_SFP_TX_FAULT, 1);
13164 /* Change TX_Fault led, set link status for further syncs */
13167 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
13168 led_mode = MISC_REGISTERS_GPIO_HIGH;
13169 vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
13171 led_mode = MISC_REGISTERS_GPIO_LOW;
13172 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13175 /* If module is unapproved, led should be on regardless */
13176 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
13177 DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n",
13179 bnx2x_set_e3_module_fault_led(params, led_mode);
13183 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
13186 struct bnx2x *bp = params->bp;
13187 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
13188 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
13189 bnx2x_set_aer_mmd(params, ¶ms->phy[phy_idx]);
13190 if (bnx2x_check_half_open_conn(params, vars, 1) !=
13192 DP(NETIF_MSG_LINK, "Fault detection failed\n");
13197 if (CHIP_IS_E3(bp)) {
13198 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
13199 bnx2x_set_aer_mmd(params, phy);
13200 bnx2x_check_over_curr(params, vars);
13201 if (vars->rx_tx_asic_rst)
13202 bnx2x_warpcore_config_runtime(phy, params, vars);
13204 if ((REG_RD(bp, params->shmem_base +
13205 offsetof(struct shmem_region, dev_info.
13206 port_hw_config[params->port].default_cfg))
13207 & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
13208 PORT_HW_CFG_NET_SERDES_IF_SFI) {
13209 if (bnx2x_is_sfp_module_plugged(phy, params)) {
13210 bnx2x_sfp_tx_fault_detection(phy, params, vars);
13211 } else if (vars->link_status &
13212 LINK_STATUS_SFP_TX_FAULT) {
13213 /* Clean trail, interrupt corrects the leds */
13214 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13215 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
13216 /* Update link status in the shared memory */
13217 bnx2x_update_mng(params, vars->link_status);
13225 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
13228 struct bnx2x_phy phy;
13229 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
13231 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13233 DP(NETIF_MSG_LINK, "populate phy failed\n");
13237 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
13243 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
13248 u8 phy_index, fan_failure_det_req = 0;
13249 struct bnx2x_phy phy;
13250 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13252 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13255 DP(NETIF_MSG_LINK, "populate phy failed\n");
13258 fan_failure_det_req |= (phy.flags &
13259 FLAGS_FAN_FAILURE_DET_REQ);
13261 return fan_failure_det_req;
13264 void bnx2x_hw_reset_phy(struct link_params *params)
13267 struct bnx2x *bp = params->bp;
13268 bnx2x_update_mng(params, 0);
13269 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
13270 (NIG_MASK_XGXS0_LINK_STATUS |
13271 NIG_MASK_XGXS0_LINK10G |
13272 NIG_MASK_SERDES0_LINK_STATUS |
13275 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
13277 if (params->phy[phy_index].hw_reset) {
13278 params->phy[phy_index].hw_reset(
13279 ¶ms->phy[phy_index],
13281 params->phy[phy_index] = phy_null;
13286 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
13287 u32 chip_id, u32 shmem_base, u32 shmem2_base,
13290 u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
13292 u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
13293 if (CHIP_IS_E3(bp)) {
13294 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
13301 struct bnx2x_phy phy;
13302 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13304 if (bnx2x_populate_phy(bp, phy_index, shmem_base,
13305 shmem2_base, port, &phy)
13307 DP(NETIF_MSG_LINK, "populate phy failed\n");
13310 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
13311 gpio_num = MISC_REGISTERS_GPIO_3;
13318 if (gpio_num == 0xff)
13321 /* Set GPIO3 to trigger SFP+ module insertion/removal */
13322 bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
13324 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13325 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13326 gpio_port ^= (swap_val && swap_override);
13328 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
13329 (gpio_num + (gpio_port << 2));
13331 sync_offset = shmem_base +
13332 offsetof(struct shmem_region,
13333 dev_info.port_hw_config[port].aeu_int_mask);
13334 REG_WR(bp, sync_offset, vars->aeu_int_mask);
13336 DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
13337 gpio_num, gpio_port, vars->aeu_int_mask);
13340 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
13342 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
13344 /* Open appropriate AEU for interrupts */
13345 aeu_mask = REG_RD(bp, offset);
13346 aeu_mask |= vars->aeu_int_mask;
13347 REG_WR(bp, offset, aeu_mask);
13349 /* Enable the GPIO to trigger interrupt */
13350 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
13351 val |= 1 << (gpio_num + (gpio_port << 2));
13352 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);