drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c

   1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2012 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/ethtool.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/types.h>
  23 #include <linux/sched.h>
  24 #include <linux/crc32.h>
  25 #include "bnx2x.h"
  26 #include "bnx2x_cmn.h"
  27 #include "bnx2x_dump.h"
  28 #include "bnx2x_init.h"
  29
  30 /* Note: in the format strings below %s is replaced by the queue-name which is
  31  * either its index or 'fcoe' for the fcoe queue. Make sure the format string
  32  * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
  33  */
  34 #define MAX_QUEUE_NAME_LEN      4
  35 static const struct {
  36         long offset;
  37         int size;
  38         char string[ETH_GSTRING_LEN];
  39 } bnx2x_q_stats_arr[] = {
  40 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
  41         { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
  42                                                 8, "[%s]: rx_ucast_packets" },
  43         { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
  44                                                 8, "[%s]: rx_mcast_packets" },
  45         { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
  46                                                 8, "[%s]: rx_bcast_packets" },
  47         { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
  48         { Q_STATS_OFFSET32(rx_err_discard_pkt),
  49                                          4, "[%s]: rx_phy_ip_err_discards"},
  50         { Q_STATS_OFFSET32(rx_skb_alloc_failed),
  51                                          4, "[%s]: rx_skb_alloc_discard" },
  52         { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
  53
  54         { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
  55 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
  56                                                 8, "[%s]: tx_ucast_packets" },
  57         { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
  58                                                 8, "[%s]: tx_mcast_packets" },
  59         { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
  60                                                 8, "[%s]: tx_bcast_packets" },
  61         { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
  62                                                 8, "[%s]: tpa_aggregations" },
  63         { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
  64                                         8, "[%s]: tpa_aggregated_frames"},
  65         { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}
  66 };
  67
  68 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
  69
  70 static const struct {
  71         long offset;
  72         int size;
  73         u32 flags;
  74 #define STATS_FLAGS_PORT                1
  75 #define STATS_FLAGS_FUNC                2
  76 #define STATS_FLAGS_BOTH                (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
  77         char string[ETH_GSTRING_LEN];
  78 } bnx2x_stats_arr[] = {
  79 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
  80                                 8, STATS_FLAGS_BOTH, "rx_bytes" },
  81         { STATS_OFFSET32(error_bytes_received_hi),
  82                                 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
  83         { STATS_OFFSET32(total_unicast_packets_received_hi),
  84                                 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
  85         { STATS_OFFSET32(total_multicast_packets_received_hi),
  86                                 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
  87         { STATS_OFFSET32(total_broadcast_packets_received_hi),
  88                                 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
  89         { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
  90                                 8, STATS_FLAGS_PORT, "rx_crc_errors" },
  91         { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
  92                                 8, STATS_FLAGS_PORT, "rx_align_errors" },
  93         { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
  94                                 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
  95         { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
  96                                 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
  97 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
  98                                 8, STATS_FLAGS_PORT, "rx_fragments" },
  99         { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
 100                                 8, STATS_FLAGS_PORT, "rx_jabbers" },
 101         { STATS_OFFSET32(no_buff_discard_hi),
 102                                 8, STATS_FLAGS_BOTH, "rx_discards" },
 103         { STATS_OFFSET32(mac_filter_discard),
 104                                 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
 105         { STATS_OFFSET32(mf_tag_discard),
 106                                 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
 107         { STATS_OFFSET32(pfc_frames_received_hi),
 108                                 8, STATS_FLAGS_PORT, "pfc_frames_received" },
 109         { STATS_OFFSET32(pfc_frames_sent_hi),
 110                                 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
 111         { STATS_OFFSET32(brb_drop_hi),
 112                                 8, STATS_FLAGS_PORT, "rx_brb_discard" },
 113         { STATS_OFFSET32(brb_truncate_hi),
 114                                 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
 115         { STATS_OFFSET32(pause_frames_received_hi),
 116                                 8, STATS_FLAGS_PORT, "rx_pause_frames" },
 117         { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
 118                                 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
 119         { STATS_OFFSET32(nig_timer_max),
 120                         4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
 121 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
 122                                 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
 123         { STATS_OFFSET32(rx_skb_alloc_failed),
 124                                 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
 125         { STATS_OFFSET32(hw_csum_err),
 126                                 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
 127
 128         { STATS_OFFSET32(total_bytes_transmitted_hi),
 129                                 8, STATS_FLAGS_BOTH, "tx_bytes" },
 130         { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
 131                                 8, STATS_FLAGS_PORT, "tx_error_bytes" },
 132         { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
 133                                 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
 134         { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
 135                                 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
 136         { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
 137                                 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
 138         { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
 139                                 8, STATS_FLAGS_PORT, "tx_mac_errors" },
 140         { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
 141                                 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
 142 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
 143                                 8, STATS_FLAGS_PORT, "tx_single_collisions" },
 144         { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
 145                                 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
 146         { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
 147                                 8, STATS_FLAGS_PORT, "tx_deferred" },
 148         { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
 149                                 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
 150         { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
 151                                 8, STATS_FLAGS_PORT, "tx_late_collisions" },
 152         { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
 153                                 8, STATS_FLAGS_PORT, "tx_total_collisions" },
 154         { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
 155                                 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
 156         { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
 157                         8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
 158         { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
 159                         8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
 160         { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
 161                         8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
 162 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
 163                         8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
 164         { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
 165                         8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
 166         { STATS_OFFSET32(etherstatspktsover1522octets_hi),
 167                         8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
 168         { STATS_OFFSET32(pause_frames_sent_hi),
 169                                 8, STATS_FLAGS_PORT, "tx_pause_frames" },
 170         { STATS_OFFSET32(total_tpa_aggregations_hi),
 171                         8, STATS_FLAGS_FUNC, "tpa_aggregations" },
 172         { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
 173                         8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
 174         { STATS_OFFSET32(total_tpa_bytes_hi),
 175                         8, STATS_FLAGS_FUNC, "tpa_bytes"},
 176         { STATS_OFFSET32(recoverable_error),
 177                         4, STATS_FLAGS_FUNC, "recoverable_errors" },
 178         { STATS_OFFSET32(unrecoverable_error),
 179                         4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
 180         { STATS_OFFSET32(eee_tx_lpi),
 181                         4, STATS_FLAGS_PORT, "Tx LPI entry count"}
 182 };
 183
 184 #define BNX2X_NUM_STATS         ARRAY_SIZE(bnx2x_stats_arr)
 185 static int bnx2x_get_port_type(struct bnx2x *bp)
 186 {
 187         int port_type;
 188         u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
 189         switch (bp->link_params.phy[phy_idx].media_type) {
 190         case ETH_PHY_SFPP_10G_FIBER:
 191         case ETH_PHY_SFP_1G_FIBER:
 192         case ETH_PHY_XFP_FIBER:
 193         case ETH_PHY_KR:
 194         case ETH_PHY_CX4:
 195                 port_type = PORT_FIBRE;
 196                 break;
 197         case ETH_PHY_DA_TWINAX:
 198                 port_type = PORT_DA;
 199                 break;
 200         case ETH_PHY_BASE_T:
 201                 port_type = PORT_TP;
 202                 break;
 203         case ETH_PHY_NOT_PRESENT:
 204                 port_type = PORT_NONE;
 205                 break;
 206         case ETH_PHY_UNSPECIFIED:
 207         default:
 208                 port_type = PORT_OTHER;
 209                 break;
 210         }
 211         return port_type;
 212 }
 213
 214 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 215 {
 216         struct bnx2x *bp = netdev_priv(dev);
 217         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
 218
 219         /* Dual Media boards present all available port types */
 220         cmd->supported = bp->port.supported[cfg_idx] |
 221                 (bp->port.supported[cfg_idx ^ 1] &
 222                  (SUPPORTED_TP | SUPPORTED_FIBRE));
 223         cmd->advertising = bp->port.advertising[cfg_idx];
 224         if (bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type ==
 225             ETH_PHY_SFP_1G_FIBER) {
 226                 cmd->supported &= ~(SUPPORTED_10000baseT_Full);
 227                 cmd->advertising &= ~(ADVERTISED_10000baseT_Full);
 228         }
 229
 230         if ((bp->state == BNX2X_STATE_OPEN) && (bp->link_vars.link_up)) {
 231                 if (!(bp->flags & MF_FUNC_DIS)) {
 232                         ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
 233                         cmd->duplex = bp->link_vars.duplex;
 234                 } else {
 235                         ethtool_cmd_speed_set(
 236                                 cmd, bp->link_params.req_line_speed[cfg_idx]);
 237                         cmd->duplex = bp->link_params.req_duplex[cfg_idx];
 238                 }
 239
 240                 if (IS_MF(bp) && !BP_NOMCP(bp))
 241                         ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
 242         } else {
 243                 cmd->duplex = DUPLEX_UNKNOWN;
 244                 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
 245         }
 246
 247         cmd->port = bnx2x_get_port_type(bp);
 248
 249         cmd->phy_address = bp->mdio.prtad;
 250         cmd->transceiver = XCVR_INTERNAL;
 251
 252         if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
 253                 cmd->autoneg = AUTONEG_ENABLE;
 254         else
 255                 cmd->autoneg = AUTONEG_DISABLE;
 256
 257         /* Publish LP advertised speeds and FC */
 258         if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
 259                 u32 status = bp->link_vars.link_status;
 260
 261                 cmd->lp_advertising |= ADVERTISED_Autoneg;
 262                 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
 263                         cmd->lp_advertising |= ADVERTISED_Pause;
 264                 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
 265                         cmd->lp_advertising |= ADVERTISED_Asym_Pause;
 266
 267                 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
 268                         cmd->lp_advertising |= ADVERTISED_10baseT_Half;
 269                 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
 270                         cmd->lp_advertising |= ADVERTISED_10baseT_Full;
 271                 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
 272                         cmd->lp_advertising |= ADVERTISED_100baseT_Half;
 273                 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
 274                         cmd->lp_advertising |= ADVERTISED_100baseT_Full;
 275                 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
 276                         cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
 277                 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE)
 278                         cmd->lp_advertising |= ADVERTISED_1000baseT_Full;
 279                 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
 280                         cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
 281                 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE)
 282                         cmd->lp_advertising |= ADVERTISED_10000baseT_Full;
 283         }
 284
 285         cmd->maxtxpkt = 0;
 286         cmd->maxrxpkt = 0;
 287
 288         DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
 289            "  supported 0x%x  advertising 0x%x  speed %u\n"
 290            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 291            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 292            cmd->cmd, cmd->supported, cmd->advertising,
 293            ethtool_cmd_speed(cmd),
 294            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 295            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 296
 297         return 0;
 298 }
 299
 300 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 301 {
 302         struct bnx2x *bp = netdev_priv(dev);
 303         u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
 304         u32 speed, phy_idx;
 305
 306         if (IS_MF_SD(bp))
 307                 return 0;
 308
 309         DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
 310            "  supported 0x%x  advertising 0x%x  speed %u\n"
 311            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 312            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 313            cmd->cmd, cmd->supported, cmd->advertising,
 314            ethtool_cmd_speed(cmd),
 315            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 316            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 317
 318         speed = ethtool_cmd_speed(cmd);
 319
 320         /* If recieved a request for an unknown duplex, assume full*/
 321         if (cmd->duplex == DUPLEX_UNKNOWN)
 322                 cmd->duplex = DUPLEX_FULL;
 323
 324         if (IS_MF_SI(bp)) {
 325                 u32 part;
 326                 u32 line_speed = bp->link_vars.line_speed;
 327
 328                 /* use 10G if no link detected */
 329                 if (!line_speed)
 330                         line_speed = 10000;
 331
 332                 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
 333                         DP(BNX2X_MSG_ETHTOOL,
 334                            "To set speed BC %X or higher is required, please upgrade BC\n",
 335                            REQ_BC_VER_4_SET_MF_BW);
 336                         return -EINVAL;
 337                 }
 338
 339                 part = (speed * 100) / line_speed;
 340
 341                 if (line_speed < speed || !part) {
 342                         DP(BNX2X_MSG_ETHTOOL,
 343                            "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
 344                         return -EINVAL;
 345                 }
 346
 347                 if (bp->state != BNX2X_STATE_OPEN)
 348                         /* store value for following "load" */
 349                         bp->pending_max = part;
 350                 else
 351                         bnx2x_update_max_mf_config(bp, part);
 352
 353                 return 0;
 354         }
 355
 356         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 357         old_multi_phy_config = bp->link_params.multi_phy_config;
 358         switch (cmd->port) {
 359         case PORT_TP:
 360                 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
 361                         break; /* no port change */
 362
 363                 if (!(bp->port.supported[0] & SUPPORTED_TP ||
 364                       bp->port.supported[1] & SUPPORTED_TP)) {
 365                         DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
 366                         return -EINVAL;
 367                 }
 368                 bp->link_params.multi_phy_config &=
 369                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 370                 if (bp->link_params.multi_phy_config &
 371                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 372                         bp->link_params.multi_phy_config |=
 373                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 374                 else
 375                         bp->link_params.multi_phy_config |=
 376                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 377                 break;
 378         case PORT_FIBRE:
 379         case PORT_DA:
 380                 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
 381                         break; /* no port change */
 382
 383                 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
 384                       bp->port.supported[1] & SUPPORTED_FIBRE)) {
 385                         DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
 386                         return -EINVAL;
 387                 }
 388                 bp->link_params.multi_phy_config &=
 389                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 390                 if (bp->link_params.multi_phy_config &
 391                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 392                         bp->link_params.multi_phy_config |=
 393                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 394                 else
 395                         bp->link_params.multi_phy_config |=
 396                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 397                 break;
 398         default:
 399                 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
 400                 return -EINVAL;
 401         }
 402         /* Save new config in case command complete successully */
 403         new_multi_phy_config = bp->link_params.multi_phy_config;
 404         /* Get the new cfg_idx */
 405         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 406         /* Restore old config in case command failed */
 407         bp->link_params.multi_phy_config = old_multi_phy_config;
 408         DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
 409
 410         if (cmd->autoneg == AUTONEG_ENABLE) {
 411                 u32 an_supported_speed = bp->port.supported[cfg_idx];
 412                 if (bp->link_params.phy[EXT_PHY1].type ==
 413                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
 414                         an_supported_speed |= (SUPPORTED_100baseT_Half |
 415                                                SUPPORTED_100baseT_Full);
 416                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
 417                         DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
 418                         return -EINVAL;
 419                 }
 420
 421                 /* advertise the requested speed and duplex if supported */
 422                 if (cmd->advertising & ~an_supported_speed) {
 423                         DP(BNX2X_MSG_ETHTOOL,
 424                            "Advertisement parameters are not supported\n");
 425                         return -EINVAL;
 426                 }
 427
 428                 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
 429                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 430                 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
 431                                          cmd->advertising);
 432                 if (cmd->advertising) {
 433
 434                         bp->link_params.speed_cap_mask[cfg_idx] = 0;
 435                         if (cmd->advertising & ADVERTISED_10baseT_Half) {
 436                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 437                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
 438                         }
 439                         if (cmd->advertising & ADVERTISED_10baseT_Full)
 440                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 441                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
 442
 443                         if (cmd->advertising & ADVERTISED_100baseT_Full)
 444                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 445                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
 446
 447                         if (cmd->advertising & ADVERTISED_100baseT_Half) {
 448                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 449                                      PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
 450                         }
 451                         if (cmd->advertising & ADVERTISED_1000baseT_Half) {
 452                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 453                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 454                         }
 455                         if (cmd->advertising & (ADVERTISED_1000baseT_Full |
 456                                                 ADVERTISED_1000baseKX_Full))
 457                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 458                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 459
 460                         if (cmd->advertising & (ADVERTISED_10000baseT_Full |
 461                                                 ADVERTISED_10000baseKX4_Full |
 462                                                 ADVERTISED_10000baseKR_Full))
 463                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 464                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
 465                 }
 466         } else { /* forced speed */
 467                 /* advertise the requested speed and duplex if supported */
 468                 switch (speed) {
 469                 case SPEED_10:
 470                         if (cmd->duplex == DUPLEX_FULL) {
 471                                 if (!(bp->port.supported[cfg_idx] &
 472                                       SUPPORTED_10baseT_Full)) {
 473                                         DP(BNX2X_MSG_ETHTOOL,
 474                                            "10M full not supported\n");
 475                                         return -EINVAL;
 476                                 }
 477
 478                                 advertising = (ADVERTISED_10baseT_Full |
 479                                                ADVERTISED_TP);
 480                         } else {
 481                                 if (!(bp->port.supported[cfg_idx] &
 482                                       SUPPORTED_10baseT_Half)) {
 483                                         DP(BNX2X_MSG_ETHTOOL,
 484                                            "10M half not supported\n");
 485                                         return -EINVAL;
 486                                 }
 487
 488                                 advertising = (ADVERTISED_10baseT_Half |
 489                                                ADVERTISED_TP);
 490                         }
 491                         break;
 492
 493                 case SPEED_100:
 494                         if (cmd->duplex == DUPLEX_FULL) {
 495                                 if (!(bp->port.supported[cfg_idx] &
 496                                                 SUPPORTED_100baseT_Full)) {
 497                                         DP(BNX2X_MSG_ETHTOOL,
 498                                            "100M full not supported\n");
 499                                         return -EINVAL;
 500                                 }
 501
 502                                 advertising = (ADVERTISED_100baseT_Full |
 503                                                ADVERTISED_TP);
 504                         } else {
 505                                 if (!(bp->port.supported[cfg_idx] &
 506                                                 SUPPORTED_100baseT_Half)) {
 507                                         DP(BNX2X_MSG_ETHTOOL,
 508                                            "100M half not supported\n");
 509                                         return -EINVAL;
 510                                 }
 511
 512                                 advertising = (ADVERTISED_100baseT_Half |
 513                                                ADVERTISED_TP);
 514                         }
 515                         break;
 516
 517                 case SPEED_1000:
 518                         if (cmd->duplex != DUPLEX_FULL) {
 519                                 DP(BNX2X_MSG_ETHTOOL,
 520                                    "1G half not supported\n");
 521                                 return -EINVAL;
 522                         }
 523
 524                         if (!(bp->port.supported[cfg_idx] &
 525                               SUPPORTED_1000baseT_Full)) {
 526                                 DP(BNX2X_MSG_ETHTOOL,
 527                                    "1G full not supported\n");
 528                                 return -EINVAL;
 529                         }
 530
 531                         advertising = (ADVERTISED_1000baseT_Full |
 532                                        ADVERTISED_TP);
 533                         break;
 534
 535                 case SPEED_2500:
 536                         if (cmd->duplex != DUPLEX_FULL) {
 537                                 DP(BNX2X_MSG_ETHTOOL,
 538                                    "2.5G half not supported\n");
 539                                 return -EINVAL;
 540                         }
 541
 542                         if (!(bp->port.supported[cfg_idx]
 543                               & SUPPORTED_2500baseX_Full)) {
 544                                 DP(BNX2X_MSG_ETHTOOL,
 545                                    "2.5G full not supported\n");
 546                                 return -EINVAL;
 547                         }
 548
 549                         advertising = (ADVERTISED_2500baseX_Full |
 550                                        ADVERTISED_TP);
 551                         break;
 552
 553                 case SPEED_10000:
 554                         if (cmd->duplex != DUPLEX_FULL) {
 555                                 DP(BNX2X_MSG_ETHTOOL,
 556                                    "10G half not supported\n");
 557                                 return -EINVAL;
 558                         }
 559                         phy_idx = bnx2x_get_cur_phy_idx(bp);
 560                         if (!(bp->port.supported[cfg_idx]
 561                               & SUPPORTED_10000baseT_Full) ||
 562                             (bp->link_params.phy[phy_idx].media_type ==
 563                              ETH_PHY_SFP_1G_FIBER)) {
 564                                 DP(BNX2X_MSG_ETHTOOL,
 565                                    "10G full not supported\n");
 566                                 return -EINVAL;
 567                         }
 568
 569                         advertising = (ADVERTISED_10000baseT_Full |
 570                                        ADVERTISED_FIBRE);
 571                         break;
 572
 573                 default:
 574                         DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
 575                         return -EINVAL;
 576                 }
 577
 578                 bp->link_params.req_line_speed[cfg_idx] = speed;
 579                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 580                 bp->port.advertising[cfg_idx] = advertising;
 581         }
 582
 583         DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
 584            "  req_duplex %d  advertising 0x%x\n",
 585            bp->link_params.req_line_speed[cfg_idx],
 586            bp->link_params.req_duplex[cfg_idx],
 587            bp->port.advertising[cfg_idx]);
 588
 589         /* Set new config */
 590         bp->link_params.multi_phy_config = new_multi_phy_config;
 591         if (netif_running(dev)) {
 592                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 593                 bnx2x_link_set(bp);
 594         }
 595
 596         return 0;
 597 }
 598
 599 #define IS_E1_ONLINE(info)      (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
 600 #define IS_E1H_ONLINE(info)     (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
 601 #define IS_E2_ONLINE(info)      (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
 602 #define IS_E3_ONLINE(info)      (((info) & RI_E3_ONLINE) == RI_E3_ONLINE)
 603 #define IS_E3B0_ONLINE(info)    (((info) & RI_E3B0_ONLINE) == RI_E3B0_ONLINE)
 604
 605 static bool bnx2x_is_reg_online(struct bnx2x *bp,
 606                                 const struct reg_addr *reg_info)
 607 {
 608         if (CHIP_IS_E1(bp))
 609                 return IS_E1_ONLINE(reg_info->info);
 610         else if (CHIP_IS_E1H(bp))
 611                 return IS_E1H_ONLINE(reg_info->info);
 612         else if (CHIP_IS_E2(bp))
 613                 return IS_E2_ONLINE(reg_info->info);
 614         else if (CHIP_IS_E3A0(bp))
 615                 return IS_E3_ONLINE(reg_info->info);
 616         else if (CHIP_IS_E3B0(bp))
 617                 return IS_E3B0_ONLINE(reg_info->info);
 618         else
 619                 return false;
 620 }
 621
 622 /******* Paged registers info selectors ********/
 623 static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
 624 {
 625         if (CHIP_IS_E2(bp))
 626                 return page_vals_e2;
 627         else if (CHIP_IS_E3(bp))
 628                 return page_vals_e3;
 629         else
 630                 return NULL;
 631 }
 632
 633 static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
 634 {
 635         if (CHIP_IS_E2(bp))
 636                 return PAGE_MODE_VALUES_E2;
 637         else if (CHIP_IS_E3(bp))
 638                 return PAGE_MODE_VALUES_E3;
 639         else
 640                 return 0;
 641 }
 642
 643 static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
 644 {
 645         if (CHIP_IS_E2(bp))
 646                 return page_write_regs_e2;
 647         else if (CHIP_IS_E3(bp))
 648                 return page_write_regs_e3;
 649         else
 650                 return NULL;
 651 }
 652
 653 static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
 654 {
 655         if (CHIP_IS_E2(bp))
 656                 return PAGE_WRITE_REGS_E2;
 657         else if (CHIP_IS_E3(bp))
 658                 return PAGE_WRITE_REGS_E3;
 659         else
 660                 return 0;
 661 }
 662
 663 static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
 664 {
 665         if (CHIP_IS_E2(bp))
 666                 return page_read_regs_e2;
 667         else if (CHIP_IS_E3(bp))
 668                 return page_read_regs_e3;
 669         else
 670                 return NULL;
 671 }
 672
 673 static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
 674 {
 675         if (CHIP_IS_E2(bp))
 676                 return PAGE_READ_REGS_E2;
 677         else if (CHIP_IS_E3(bp))
 678                 return PAGE_READ_REGS_E3;
 679         else
 680                 return 0;
 681 }
 682
 683 static int __bnx2x_get_regs_len(struct bnx2x *bp)
 684 {
 685         int num_pages = __bnx2x_get_page_reg_num(bp);
 686         int page_write_num = __bnx2x_get_page_write_num(bp);
 687         const struct reg_addr *page_read_addr = __bnx2x_get_page_read_ar(bp);
 688         int page_read_num = __bnx2x_get_page_read_num(bp);
 689         int regdump_len = 0;
 690         int i, j, k;
 691
 692         for (i = 0; i < REGS_COUNT; i++)
 693                 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
 694                         regdump_len += reg_addrs[i].size;
 695
 696         for (i = 0; i < num_pages; i++)
 697                 for (j = 0; j < page_write_num; j++)
 698                         for (k = 0; k < page_read_num; k++)
 699                                 if (bnx2x_is_reg_online(bp, &page_read_addr[k]))
 700                                         regdump_len += page_read_addr[k].size;
 701
 702         return regdump_len;
 703 }
 704
 705 static int bnx2x_get_regs_len(struct net_device *dev)
 706 {
 707         struct bnx2x *bp = netdev_priv(dev);
 708         int regdump_len = 0;
 709
 710         regdump_len = __bnx2x_get_regs_len(bp);
 711         regdump_len *= 4;
 712         regdump_len += sizeof(struct dump_hdr);
 713
 714         return regdump_len;
 715 }
 716
 717 /**
 718  * bnx2x_read_pages_regs - read "paged" registers
 719  *
 720  * @bp          device handle
 721  * @p           output buffer
 722  *
 723  * Reads "paged" memories: memories that may only be read by first writing to a
 724  * specific address ("write address") and then reading from a specific address
 725  * ("read address"). There may be more than one write address per "page" and
 726  * more than one read address per write address.
 727  */
 728 static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p)
 729 {
 730         u32 i, j, k, n;
 731         /* addresses of the paged registers */
 732         const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
 733         /* number of paged registers */
 734         int num_pages = __bnx2x_get_page_reg_num(bp);
 735         /* write addresses */
 736         const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
 737         /* number of write addresses */
 738         int write_num = __bnx2x_get_page_write_num(bp);
 739         /* read addresses info */
 740         const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
 741         /* number of read addresses */
 742         int read_num = __bnx2x_get_page_read_num(bp);
 743
 744         for (i = 0; i < num_pages; i++) {
 745                 for (j = 0; j < write_num; j++) {
 746                         REG_WR(bp, write_addr[j], page_addr[i]);
 747                         for (k = 0; k < read_num; k++)
 748                                 if (bnx2x_is_reg_online(bp, &read_addr[k]))
 749                                         for (n = 0; n <
 750                                               read_addr[k].size; n++)
 751                                                 *p++ = REG_RD(bp,
 752                                                        read_addr[k].addr + n*4);
 753                 }
 754         }
 755 }
 756
 757 static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
 758 {
 759         u32 i, j;
 760
 761         /* Read the regular registers */
 762         for (i = 0; i < REGS_COUNT; i++)
 763                 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
 764                         for (j = 0; j < reg_addrs[i].size; j++)
 765                                 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
 766
 767         /* Read "paged" registes */
 768         bnx2x_read_pages_regs(bp, p);
 769 }
 770
 771 static void bnx2x_get_regs(struct net_device *dev,
 772                            struct ethtool_regs *regs, void *_p)
 773 {
 774         u32 *p = _p;
 775         struct bnx2x *bp = netdev_priv(dev);
 776         struct dump_hdr dump_hdr = {0};
 777
 778         regs->version = 1;
 779         memset(p, 0, regs->len);
 780
 781         if (!netif_running(bp->dev))
 782                 return;
 783
 784         /* Disable parity attentions as long as following dump may
 785          * cause false alarms by reading never written registers. We
 786          * will re-enable parity attentions right after the dump.
 787          */
 788         bnx2x_disable_blocks_parity(bp);
 789
 790         dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
 791         dump_hdr.dump_sign = dump_sign_all;
 792         dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
 793         dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
 794         dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
 795         dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
 796
 797         if (CHIP_IS_E1(bp))
 798                 dump_hdr.info = RI_E1_ONLINE;
 799         else if (CHIP_IS_E1H(bp))
 800                 dump_hdr.info = RI_E1H_ONLINE;
 801         else if (!CHIP_IS_E1x(bp))
 802                 dump_hdr.info = RI_E2_ONLINE |
 803                 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
 804
 805         memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
 806         p += dump_hdr.hdr_size + 1;
 807
 808         /* Actually read the registers */
 809         __bnx2x_get_regs(bp, p);
 810
 811         /* Re-enable parity attentions */
 812         bnx2x_clear_blocks_parity(bp);
 813         bnx2x_enable_blocks_parity(bp);
 814 }
 815
 816 static void bnx2x_get_drvinfo(struct net_device *dev,
 817                               struct ethtool_drvinfo *info)
 818 {
 819         struct bnx2x *bp = netdev_priv(dev);
 820         u8 phy_fw_ver[PHY_FW_VER_LEN];
 821
 822         strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
 823         strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
 824
 825         phy_fw_ver[0] = '\0';
 826         bnx2x_get_ext_phy_fw_version(&bp->link_params,
 827                                      phy_fw_ver, PHY_FW_VER_LEN);
 828         strlcpy(info->fw_version, bp->fw_ver, sizeof(info->fw_version));
 829         snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
 830                  "bc %d.%d.%d%s%s",
 831                  (bp->common.bc_ver & 0xff0000) >> 16,
 832                  (bp->common.bc_ver & 0xff00) >> 8,
 833                  (bp->common.bc_ver & 0xff),
 834                  ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
 835         strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
 836         info->n_stats = BNX2X_NUM_STATS;
 837         info->testinfo_len = BNX2X_NUM_TESTS(bp);
 838         info->eedump_len = bp->common.flash_size;
 839         info->regdump_len = bnx2x_get_regs_len(dev);
 840 }
 841
 842 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 843 {
 844         struct bnx2x *bp = netdev_priv(dev);
 845
 846         if (bp->flags & NO_WOL_FLAG) {
 847                 wol->supported = 0;
 848                 wol->wolopts = 0;
 849         } else {
 850                 wol->supported = WAKE_MAGIC;
 851                 if (bp->wol)
 852                         wol->wolopts = WAKE_MAGIC;
 853                 else
 854                         wol->wolopts = 0;
 855         }
 856         memset(&wol->sopass, 0, sizeof(wol->sopass));
 857 }
 858
 859 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 860 {
 861         struct bnx2x *bp = netdev_priv(dev);
 862
 863         if (wol->wolopts & ~WAKE_MAGIC) {
 864                 DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n");
 865                 return -EINVAL;
 866         }
 867
 868         if (wol->wolopts & WAKE_MAGIC) {
 869                 if (bp->flags & NO_WOL_FLAG) {
 870                         DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n");
 871                         return -EINVAL;
 872                 }
 873                 bp->wol = 1;
 874         } else
 875                 bp->wol = 0;
 876
 877         return 0;
 878 }
 879
 880 static u32 bnx2x_get_msglevel(struct net_device *dev)
 881 {
 882         struct bnx2x *bp = netdev_priv(dev);
 883
 884         return bp->msg_enable;
 885 }
 886
 887 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
 888 {
 889         struct bnx2x *bp = netdev_priv(dev);
 890
 891         if (capable(CAP_NET_ADMIN)) {
 892                 /* dump MCP trace */
 893                 if (level & BNX2X_MSG_MCP)
 894                         bnx2x_fw_dump_lvl(bp, KERN_INFO);
 895                 bp->msg_enable = level;
 896         }
 897 }
 898
 899 static int bnx2x_nway_reset(struct net_device *dev)
 900 {
 901         struct bnx2x *bp = netdev_priv(dev);
 902
 903         if (!bp->port.pmf)
 904                 return 0;
 905
 906         if (netif_running(dev)) {
 907                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 908                 bnx2x_link_set(bp);
 909         }
 910
 911         return 0;
 912 }
 913
 914 static u32 bnx2x_get_link(struct net_device *dev)
 915 {
 916         struct bnx2x *bp = netdev_priv(dev);
 917
 918         if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
 919                 return 0;
 920
 921         return bp->link_vars.link_up;
 922 }
 923
 924 static int bnx2x_get_eeprom_len(struct net_device *dev)
 925 {
 926         struct bnx2x *bp = netdev_priv(dev);
 927
 928         return bp->common.flash_size;
 929 }
 930
 931 /* Per pf misc lock must be aquired before the per port mcp lock. Otherwise, had
 932  * we done things the other way around, if two pfs from the same port would
 933  * attempt to access nvram at the same time, we could run into a scenario such
 934  * as:
 935  * pf A takes the port lock.
 936  * pf B succeeds in taking the same lock since they are from the same port.
 937  * pf A takes the per pf misc lock. Performs eeprom access.
 938  * pf A finishes. Unlocks the per pf misc lock.
 939  * Pf B takes the lock and proceeds to perform it's own access.
 940  * pf A unlocks the per port lock, while pf B is still working (!).
 941  * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
 942  * acess corrupted by pf B).*
 943  */
 944 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
 945 {
 946         int port = BP_PORT(bp);
 947         int count, i;
 948         u32 val;
 949
 950         /* acquire HW lock: protect against other PFs in PF Direct Assignment */
 951         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
 952
 953         /* adjust timeout for emulation/FPGA */
 954         count = BNX2X_NVRAM_TIMEOUT_COUNT;
 955         if (CHIP_REV_IS_SLOW(bp))
 956                 count *= 100;
 957
 958         /* request access to nvram interface */
 959         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
 960                (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
 961
 962         for (i = 0; i < count*10; i++) {
 963                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
 964                 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
 965                         break;
 966
 967                 udelay(5);
 968         }
 969
 970         if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
 971                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
 972                    "cannot get access to nvram interface\n");
 973                 return -EBUSY;
 974         }
 975
 976         return 0;
 977 }
 978
 979 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
 980 {
 981         int port = BP_PORT(bp);
 982         int count, i;
 983         u32 val;
 984
 985         /* adjust timeout for emulation/FPGA */
 986         count = BNX2X_NVRAM_TIMEOUT_COUNT;
 987         if (CHIP_REV_IS_SLOW(bp))
 988                 count *= 100;
 989
 990         /* relinquish nvram interface */
 991         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
 992                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
 993
 994         for (i = 0; i < count*10; i++) {
 995                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
 996                 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
 997                         break;
 998
 999                 udelay(5);
1000         }
1001
1002         if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1003                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1004                    "cannot free access to nvram interface\n");
1005                 return -EBUSY;
1006         }
1007
1008         /* release HW lock: protect against other PFs in PF Direct Assignment */
1009         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1010         return 0;
1011 }
1012
1013 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1014 {
1015         u32 val;
1016
1017         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1018
1019         /* enable both bits, even on read */
1020         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1021                (val | MCPR_NVM_ACCESS_ENABLE_EN |
1022                       MCPR_NVM_ACCESS_ENABLE_WR_EN));
1023 }
1024
1025 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1026 {
1027         u32 val;
1028
1029         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1030
1031         /* disable both bits, even after read */
1032         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1033                (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1034                         MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1035 }
1036
1037 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1038                                   u32 cmd_flags)
1039 {
1040         int count, i, rc;
1041         u32 val;
1042
1043         /* build the command word */
1044         cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1045
1046         /* need to clear DONE bit separately */
1047         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1048
1049         /* address of the NVRAM to read from */
1050         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1051                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1052
1053         /* issue a read command */
1054         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1055
1056         /* adjust timeout for emulation/FPGA */
1057         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1058         if (CHIP_REV_IS_SLOW(bp))
1059                 count *= 100;
1060
1061         /* wait for completion */
1062         *ret_val = 0;
1063         rc = -EBUSY;
1064         for (i = 0; i < count; i++) {
1065                 udelay(5);
1066                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1067
1068                 if (val & MCPR_NVM_COMMAND_DONE) {
1069                         val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1070                         /* we read nvram data in cpu order
1071                          * but ethtool sees it as an array of bytes
1072                          * converting to big-endian will do the work */
1073                         *ret_val = cpu_to_be32(val);
1074                         rc = 0;
1075                         break;
1076                 }
1077         }
1078         if (rc == -EBUSY)
1079                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1080                    "nvram read timeout expired\n");
1081         return rc;
1082 }
1083
1084 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1085                             int buf_size)
1086 {
1087         int rc;
1088         u32 cmd_flags;
1089         __be32 val;
1090
1091         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1092                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1093                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1094                    offset, buf_size);
1095                 return -EINVAL;
1096         }
1097
1098         if (offset + buf_size > bp->common.flash_size) {
1099                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1100                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1101                    offset, buf_size, bp->common.flash_size);
1102                 return -EINVAL;
1103         }
1104
1105         /* request access to nvram interface */
1106         rc = bnx2x_acquire_nvram_lock(bp);
1107         if (rc)
1108                 return rc;
1109
1110         /* enable access to nvram interface */
1111         bnx2x_enable_nvram_access(bp);
1112
1113         /* read the first word(s) */
1114         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1115         while ((buf_size > sizeof(u32)) && (rc == 0)) {
1116                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1117                 memcpy(ret_buf, &val, 4);
1118
1119                 /* advance to the next dword */
1120                 offset += sizeof(u32);
1121                 ret_buf += sizeof(u32);
1122                 buf_size -= sizeof(u32);
1123                 cmd_flags = 0;
1124         }
1125
1126         if (rc == 0) {
1127                 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1128                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1129                 memcpy(ret_buf, &val, 4);
1130         }
1131
1132         /* disable access to nvram interface */
1133         bnx2x_disable_nvram_access(bp);
1134         bnx2x_release_nvram_lock(bp);
1135
1136         return rc;
1137 }
1138
1139 static int bnx2x_get_eeprom(struct net_device *dev,
1140                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1141 {
1142         struct bnx2x *bp = netdev_priv(dev);
1143         int rc;
1144
1145         if (!netif_running(dev)) {
1146                 DP(BNX2X_MSG_ETHTOOL  | BNX2X_MSG_NVM,
1147                    "cannot access eeprom when the interface is down\n");
1148                 return -EAGAIN;
1149         }
1150
1151         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1152            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1153            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1154            eeprom->len, eeprom->len);
1155
1156         /* parameters already validated in ethtool_get_eeprom */
1157
1158         rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1159
1160         return rc;
1161 }
1162
1163 static int bnx2x_get_module_eeprom(struct net_device *dev,
1164                                    struct ethtool_eeprom *ee,
1165                                    u8 *data)
1166 {
1167         struct bnx2x *bp = netdev_priv(dev);
1168         int rc = 0, phy_idx;
1169         u8 *user_data = data;
1170         int remaining_len = ee->len, xfer_size;
1171         unsigned int page_off = ee->offset;
1172
1173         if (!netif_running(dev)) {
1174                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1175                    "cannot access eeprom when the interface is down\n");
1176                 return -EAGAIN;
1177         }
1178
1179         phy_idx = bnx2x_get_cur_phy_idx(bp);
1180         bnx2x_acquire_phy_lock(bp);
1181         while (!rc && remaining_len > 0) {
1182                 xfer_size = (remaining_len > SFP_EEPROM_PAGE_SIZE) ?
1183                         SFP_EEPROM_PAGE_SIZE : remaining_len;
1184                 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1185                                                   &bp->link_params,
1186                                                   page_off,
1187                                                   xfer_size,
1188                                                   user_data);
1189                 remaining_len -= xfer_size;
1190                 user_data += xfer_size;
1191                 page_off += xfer_size;
1192         }
1193
1194         bnx2x_release_phy_lock(bp);
1195         return rc;
1196 }
1197
1198 static int bnx2x_get_module_info(struct net_device *dev,
1199                                  struct ethtool_modinfo *modinfo)
1200 {
1201         struct bnx2x *bp = netdev_priv(dev);
1202         int phy_idx;
1203         if (!netif_running(dev)) {
1204                 DP(BNX2X_MSG_ETHTOOL  | BNX2X_MSG_NVM,
1205                    "cannot access eeprom when the interface is down\n");
1206                 return -EAGAIN;
1207         }
1208
1209         phy_idx = bnx2x_get_cur_phy_idx(bp);
1210         switch (bp->link_params.phy[phy_idx].media_type) {
1211         case ETH_PHY_SFPP_10G_FIBER:
1212         case ETH_PHY_SFP_1G_FIBER:
1213         case ETH_PHY_DA_TWINAX:
1214                 modinfo->type = ETH_MODULE_SFF_8079;
1215                 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1216                 return 0;
1217         default:
1218                 return -EOPNOTSUPP;
1219         }
1220 }
1221
1222 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1223                                    u32 cmd_flags)
1224 {
1225         int count, i, rc;
1226
1227         /* build the command word */
1228         cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1229
1230         /* need to clear DONE bit separately */
1231         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1232
1233         /* write the data */
1234         REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1235
1236         /* address of the NVRAM to write to */
1237         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1238                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1239
1240         /* issue the write command */
1241         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1242
1243         /* adjust timeout for emulation/FPGA */
1244         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1245         if (CHIP_REV_IS_SLOW(bp))
1246                 count *= 100;
1247
1248         /* wait for completion */
1249         rc = -EBUSY;
1250         for (i = 0; i < count; i++) {
1251                 udelay(5);
1252                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1253                 if (val & MCPR_NVM_COMMAND_DONE) {
1254                         rc = 0;
1255                         break;
1256                 }
1257         }
1258
1259         if (rc == -EBUSY)
1260                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1261                    "nvram write timeout expired\n");
1262         return rc;
1263 }
1264
1265 #define BYTE_OFFSET(offset)             (8 * (offset & 0x03))
1266
1267 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1268                               int buf_size)
1269 {
1270         int rc;
1271         u32 cmd_flags;
1272         u32 align_offset;
1273         __be32 val;
1274
1275         if (offset + buf_size > bp->common.flash_size) {
1276                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1277                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1278                    offset, buf_size, bp->common.flash_size);
1279                 return -EINVAL;
1280         }
1281
1282         /* request access to nvram interface */
1283         rc = bnx2x_acquire_nvram_lock(bp);
1284         if (rc)
1285                 return rc;
1286
1287         /* enable access to nvram interface */
1288         bnx2x_enable_nvram_access(bp);
1289
1290         cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1291         align_offset = (offset & ~0x03);
1292         rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1293
1294         if (rc == 0) {
1295                 val &= ~(0xff << BYTE_OFFSET(offset));
1296                 val |= (*data_buf << BYTE_OFFSET(offset));
1297
1298                 /* nvram data is returned as an array of bytes
1299                  * convert it back to cpu order */
1300                 val = be32_to_cpu(val);
1301
1302                 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1303                                              cmd_flags);
1304         }
1305
1306         /* disable access to nvram interface */
1307         bnx2x_disable_nvram_access(bp);
1308         bnx2x_release_nvram_lock(bp);
1309
1310         return rc;
1311 }
1312
1313 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1314                              int buf_size)
1315 {
1316         int rc;
1317         u32 cmd_flags;
1318         u32 val;
1319         u32 written_so_far;
1320
1321         if (buf_size == 1)      /* ethtool */
1322                 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1323
1324         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1325                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1326                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1327                    offset, buf_size);
1328                 return -EINVAL;
1329         }
1330
1331         if (offset + buf_size > bp->common.flash_size) {
1332                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1333                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1334                    offset, buf_size, bp->common.flash_size);
1335                 return -EINVAL;
1336         }
1337
1338         /* request access to nvram interface */
1339         rc = bnx2x_acquire_nvram_lock(bp);
1340         if (rc)
1341                 return rc;
1342
1343         /* enable access to nvram interface */
1344         bnx2x_enable_nvram_access(bp);
1345
1346         written_so_far = 0;
1347         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1348         while ((written_so_far < buf_size) && (rc == 0)) {
1349                 if (written_so_far == (buf_size - sizeof(u32)))
1350                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1351                 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1352                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1353                 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1354                         cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1355
1356                 memcpy(&val, data_buf, 4);
1357
1358                 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1359
1360                 /* advance to the next dword */
1361                 offset += sizeof(u32);
1362                 data_buf += sizeof(u32);
1363                 written_so_far += sizeof(u32);
1364                 cmd_flags = 0;
1365         }
1366
1367         /* disable access to nvram interface */
1368         bnx2x_disable_nvram_access(bp);
1369         bnx2x_release_nvram_lock(bp);
1370
1371         return rc;
1372 }
1373
1374 static int bnx2x_set_eeprom(struct net_device *dev,
1375                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1376 {
1377         struct bnx2x *bp = netdev_priv(dev);
1378         int port = BP_PORT(bp);
1379         int rc = 0;
1380         u32 ext_phy_config;
1381         if (!netif_running(dev)) {
1382                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1383                    "cannot access eeprom when the interface is down\n");
1384                 return -EAGAIN;
1385         }
1386
1387         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1388            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1389            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1390            eeprom->len, eeprom->len);
1391
1392         /* parameters already validated in ethtool_set_eeprom */
1393
1394         /* PHY eeprom can be accessed only by the PMF */
1395         if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1396             !bp->port.pmf) {
1397                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1398                    "wrong magic or interface is not pmf\n");
1399                 return -EINVAL;
1400         }
1401
1402         ext_phy_config =
1403                 SHMEM_RD(bp,
1404                          dev_info.port_hw_config[port].external_phy_config);
1405
1406         if (eeprom->magic == 0x50485950) {
1407                 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1408                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1409
1410                 bnx2x_acquire_phy_lock(bp);
1411                 rc |= bnx2x_link_reset(&bp->link_params,
1412                                        &bp->link_vars, 0);
1413                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1414                                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1415                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1416                                        MISC_REGISTERS_GPIO_HIGH, port);
1417                 bnx2x_release_phy_lock(bp);
1418                 bnx2x_link_report(bp);
1419
1420         } else if (eeprom->magic == 0x50485952) {
1421                 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1422                 if (bp->state == BNX2X_STATE_OPEN) {
1423                         bnx2x_acquire_phy_lock(bp);
1424                         rc |= bnx2x_link_reset(&bp->link_params,
1425                                                &bp->link_vars, 1);
1426
1427                         rc |= bnx2x_phy_init(&bp->link_params,
1428                                              &bp->link_vars);
1429                         bnx2x_release_phy_lock(bp);
1430                         bnx2x_calc_fc_adv(bp);
1431                 }
1432         } else if (eeprom->magic == 0x53985943) {
1433                 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1434                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1435                                        PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1436
1437                         /* DSP Remove Download Mode */
1438                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1439                                        MISC_REGISTERS_GPIO_LOW, port);
1440
1441                         bnx2x_acquire_phy_lock(bp);
1442
1443                         bnx2x_sfx7101_sp_sw_reset(bp,
1444                                                 &bp->link_params.phy[EXT_PHY1]);
1445
1446                         /* wait 0.5 sec to allow it to run */
1447                         msleep(500);
1448                         bnx2x_ext_phy_hw_reset(bp, port);
1449                         msleep(500);
1450                         bnx2x_release_phy_lock(bp);
1451                 }
1452         } else
1453                 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1454
1455         return rc;
1456 }
1457
1458 static int bnx2x_get_coalesce(struct net_device *dev,
1459                               struct ethtool_coalesce *coal)
1460 {
1461         struct bnx2x *bp = netdev_priv(dev);
1462
1463         memset(coal, 0, sizeof(struct ethtool_coalesce));
1464
1465         coal->rx_coalesce_usecs = bp->rx_ticks;
1466         coal->tx_coalesce_usecs = bp->tx_ticks;
1467
1468         return 0;
1469 }
1470
1471 static int bnx2x_set_coalesce(struct net_device *dev,
1472                               struct ethtool_coalesce *coal)
1473 {
1474         struct bnx2x *bp = netdev_priv(dev);
1475
1476         bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1477         if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1478                 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1479
1480         bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1481         if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1482                 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1483
1484         if (netif_running(dev))
1485                 bnx2x_update_coalesce(bp);
1486
1487         return 0;
1488 }
1489
1490 static void bnx2x_get_ringparam(struct net_device *dev,
1491                                 struct ethtool_ringparam *ering)
1492 {
1493         struct bnx2x *bp = netdev_priv(dev);
1494
1495         ering->rx_max_pending = MAX_RX_AVAIL;
1496
1497         if (bp->rx_ring_size)
1498                 ering->rx_pending = bp->rx_ring_size;
1499         else
1500                 ering->rx_pending = MAX_RX_AVAIL;
1501
1502         ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1503         ering->tx_pending = bp->tx_ring_size;
1504 }
1505
1506 static int bnx2x_set_ringparam(struct net_device *dev,
1507                                struct ethtool_ringparam *ering)
1508 {
1509         struct bnx2x *bp = netdev_priv(dev);
1510
1511         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1512                 DP(BNX2X_MSG_ETHTOOL,
1513                    "Handling parity error recovery. Try again later\n");
1514                 return -EAGAIN;
1515         }
1516
1517         if ((ering->rx_pending > MAX_RX_AVAIL) ||
1518             (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1519                                                     MIN_RX_SIZE_TPA)) ||
1520             (ering->tx_pending > (IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL)) ||
1521             (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1522                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
1523                 return -EINVAL;
1524         }
1525
1526         bp->rx_ring_size = ering->rx_pending;
1527         bp->tx_ring_size = ering->tx_pending;
1528
1529         return bnx2x_reload_if_running(dev);
1530 }
1531
1532 static void bnx2x_get_pauseparam(struct net_device *dev,
1533                                  struct ethtool_pauseparam *epause)
1534 {
1535         struct bnx2x *bp = netdev_priv(dev);
1536         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1537         int cfg_reg;
1538
1539         epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1540                            BNX2X_FLOW_CTRL_AUTO);
1541
1542         if (!epause->autoneg)
1543                 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
1544         else
1545                 cfg_reg = bp->link_params.req_fc_auto_adv;
1546
1547         epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
1548                             BNX2X_FLOW_CTRL_RX);
1549         epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
1550                             BNX2X_FLOW_CTRL_TX);
1551
1552         DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1553            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1554            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1555 }
1556
1557 static int bnx2x_set_pauseparam(struct net_device *dev,
1558                                 struct ethtool_pauseparam *epause)
1559 {
1560         struct bnx2x *bp = netdev_priv(dev);
1561         u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1562         if (IS_MF(bp))
1563                 return 0;
1564
1565         DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1566            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1567            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1568
1569         bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1570
1571         if (epause->rx_pause)
1572                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1573
1574         if (epause->tx_pause)
1575                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1576
1577         if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1578                 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1579
1580         if (epause->autoneg) {
1581                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1582                         DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
1583                         return -EINVAL;
1584                 }
1585
1586                 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1587                         bp->link_params.req_flow_ctrl[cfg_idx] =
1588                                 BNX2X_FLOW_CTRL_AUTO;
1589                 }
1590                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_NONE;
1591                 if (epause->rx_pause)
1592                         bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
1593
1594                 if (epause->tx_pause)
1595                         bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
1596         }
1597
1598         DP(BNX2X_MSG_ETHTOOL,
1599            "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1600
1601         if (netif_running(dev)) {
1602                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1603                 bnx2x_link_set(bp);
1604         }
1605
1606         return 0;
1607 }
1608
1609 static char *bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF] = {
1610         "register_test (offline)    ",
1611         "memory_test (offline)      ",
1612         "int_loopback_test (offline)",
1613         "ext_loopback_test (offline)",
1614         "nvram_test (online)        ",
1615         "interrupt_test (online)    ",
1616         "link_test (online)         "
1617 };
1618
1619 static u32 bnx2x_eee_to_adv(u32 eee_adv)
1620 {
1621         u32 modes = 0;
1622
1623         if (eee_adv & SHMEM_EEE_100M_ADV)
1624                 modes |= ADVERTISED_100baseT_Full;
1625         if (eee_adv & SHMEM_EEE_1G_ADV)
1626                 modes |= ADVERTISED_1000baseT_Full;
1627         if (eee_adv & SHMEM_EEE_10G_ADV)
1628                 modes |= ADVERTISED_10000baseT_Full;
1629
1630         return modes;
1631 }
1632
1633 static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
1634 {
1635         u32 eee_adv = 0;
1636         if (modes & ADVERTISED_100baseT_Full)
1637                 eee_adv |= SHMEM_EEE_100M_ADV;
1638         if (modes & ADVERTISED_1000baseT_Full)
1639                 eee_adv |= SHMEM_EEE_1G_ADV;
1640         if (modes & ADVERTISED_10000baseT_Full)
1641                 eee_adv |= SHMEM_EEE_10G_ADV;
1642
1643         return eee_adv << shift;
1644 }
1645
1646 static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
1647 {
1648         struct bnx2x *bp = netdev_priv(dev);
1649         u32 eee_cfg;
1650
1651         if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1652                 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1653                 return -EOPNOTSUPP;
1654         }
1655
1656         eee_cfg = SHMEM2_RD(bp, eee_status[BP_PORT(bp)]);
1657
1658         edata->supported =
1659                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
1660                                  SHMEM_EEE_SUPPORTED_SHIFT);
1661
1662         edata->advertised =
1663                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
1664                                  SHMEM_EEE_ADV_STATUS_SHIFT);
1665         edata->lp_advertised =
1666                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
1667                                  SHMEM_EEE_LP_ADV_STATUS_SHIFT);
1668
1669         /* SHMEM value is in 16u units --> Convert to 1u units. */
1670         edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
1671
1672         edata->eee_enabled    = (eee_cfg & SHMEM_EEE_REQUESTED_BIT)     ? 1 : 0;
1673         edata->eee_active     = (eee_cfg & SHMEM_EEE_ACTIVE_BIT)        ? 1 : 0;
1674         edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
1675
1676         return 0;
1677 }
1678
1679 static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
1680 {
1681         struct bnx2x *bp = netdev_priv(dev);
1682         u32 eee_cfg;
1683         u32 advertised;
1684
1685         if (IS_MF(bp))
1686                 return 0;
1687
1688         if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1689                 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1690                 return -EOPNOTSUPP;
1691         }
1692
1693         eee_cfg = SHMEM2_RD(bp, eee_status[BP_PORT(bp)]);
1694
1695         if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
1696                 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
1697                 return -EOPNOTSUPP;
1698         }
1699
1700         advertised = bnx2x_adv_to_eee(edata->advertised,
1701                                       SHMEM_EEE_ADV_STATUS_SHIFT);
1702         if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
1703                 DP(BNX2X_MSG_ETHTOOL,
1704                    "Direct manipulation of EEE advertisment is not supported\n");
1705                 return -EINVAL;
1706         }
1707
1708         if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
1709                 DP(BNX2X_MSG_ETHTOOL,
1710                    "Maximal Tx Lpi timer supported is %x(u)\n",
1711                    EEE_MODE_TIMER_MASK);
1712                 return -EINVAL;
1713         }
1714         if (edata->tx_lpi_enabled &&
1715             (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
1716                 DP(BNX2X_MSG_ETHTOOL,
1717                    "Minimal Tx Lpi timer supported is %d(u)\n",
1718                    EEE_MODE_NVRAM_AGGRESSIVE_TIME);
1719                 return -EINVAL;
1720         }
1721
1722         /* All is well; Apply changes*/
1723         if (edata->eee_enabled)
1724                 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
1725         else
1726                 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
1727
1728         if (edata->tx_lpi_enabled)
1729                 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
1730         else
1731                 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
1732
1733         bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
1734         bp->link_params.eee_mode |= (edata->tx_lpi_timer &
1735                                     EEE_MODE_TIMER_MASK) |
1736                                     EEE_MODE_OVERRIDE_NVRAM |
1737                                     EEE_MODE_OUTPUT_TIME;
1738
1739         /* Restart link to propogate changes */
1740         if (netif_running(dev)) {
1741                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1742                 bnx2x_link_set(bp);
1743         }
1744
1745         return 0;
1746 }
1747
1748
1749 enum {
1750         BNX2X_CHIP_E1_OFST = 0,
1751         BNX2X_CHIP_E1H_OFST,
1752         BNX2X_CHIP_E2_OFST,
1753         BNX2X_CHIP_E3_OFST,
1754         BNX2X_CHIP_E3B0_OFST,
1755         BNX2X_CHIP_MAX_OFST
1756 };
1757
1758 #define BNX2X_CHIP_MASK_E1      (1 << BNX2X_CHIP_E1_OFST)
1759 #define BNX2X_CHIP_MASK_E1H     (1 << BNX2X_CHIP_E1H_OFST)
1760 #define BNX2X_CHIP_MASK_E2      (1 << BNX2X_CHIP_E2_OFST)
1761 #define BNX2X_CHIP_MASK_E3      (1 << BNX2X_CHIP_E3_OFST)
1762 #define BNX2X_CHIP_MASK_E3B0    (1 << BNX2X_CHIP_E3B0_OFST)
1763
1764 #define BNX2X_CHIP_MASK_ALL     ((1 << BNX2X_CHIP_MAX_OFST) - 1)
1765 #define BNX2X_CHIP_MASK_E1X     (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
1766
1767 static int bnx2x_test_registers(struct bnx2x *bp)
1768 {
1769         int idx, i, rc = -ENODEV;
1770         u32 wr_val = 0, hw;
1771         int port = BP_PORT(bp);
1772         static const struct {
1773                 u32 hw;
1774                 u32 offset0;
1775                 u32 offset1;
1776                 u32 mask;
1777         } reg_tbl[] = {
1778 /* 0 */         { BNX2X_CHIP_MASK_ALL,
1779                         BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
1780                 { BNX2X_CHIP_MASK_ALL,
1781                         DORQ_REG_DB_ADDR0,              4, 0xffffffff },
1782                 { BNX2X_CHIP_MASK_E1X,
1783                         HC_REG_AGG_INT_0,               4, 0x000003ff },
1784                 { BNX2X_CHIP_MASK_ALL,
1785                         PBF_REG_MAC_IF0_ENABLE,         4, 0x00000001 },
1786                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
1787                         PBF_REG_P0_INIT_CRD,            4, 0x000007ff },
1788                 { BNX2X_CHIP_MASK_E3B0,
1789                         PBF_REG_INIT_CRD_Q0,            4, 0x000007ff },
1790                 { BNX2X_CHIP_MASK_ALL,
1791                         PRS_REG_CID_PORT_0,             4, 0x00ffffff },
1792                 { BNX2X_CHIP_MASK_ALL,
1793                         PXP2_REG_PSWRQ_CDU0_L2P,        4, 0x000fffff },
1794                 { BNX2X_CHIP_MASK_ALL,
1795                         PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1796                 { BNX2X_CHIP_MASK_ALL,
1797                         PXP2_REG_PSWRQ_TM0_L2P,         4, 0x000fffff },
1798 /* 10 */        { BNX2X_CHIP_MASK_ALL,
1799                         PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1800                 { BNX2X_CHIP_MASK_ALL,
1801                         PXP2_REG_PSWRQ_TSDM0_L2P,       4, 0x000fffff },
1802                 { BNX2X_CHIP_MASK_ALL,
1803                         QM_REG_CONNNUM_0,               4, 0x000fffff },
1804                 { BNX2X_CHIP_MASK_ALL,
1805                         TM_REG_LIN0_MAX_ACTIVE_CID,     4, 0x0003ffff },
1806                 { BNX2X_CHIP_MASK_ALL,
1807                         SRC_REG_KEYRSS0_0,              40, 0xffffffff },
1808                 { BNX2X_CHIP_MASK_ALL,
1809                         SRC_REG_KEYRSS0_7,              40, 0xffffffff },
1810                 { BNX2X_CHIP_MASK_ALL,
1811                         XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1812                 { BNX2X_CHIP_MASK_ALL,
1813                         XCM_REG_WU_DA_CNT_CMD00,        4, 0x00000003 },
1814                 { BNX2X_CHIP_MASK_ALL,
1815                         XCM_REG_GLB_DEL_ACK_MAX_CNT_0,  4, 0x000000ff },
1816                 { BNX2X_CHIP_MASK_ALL,
1817                         NIG_REG_LLH0_T_BIT,             4, 0x00000001 },
1818 /* 20 */        { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1819                         NIG_REG_EMAC0_IN_EN,            4, 0x00000001 },
1820                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1821                         NIG_REG_BMAC0_IN_EN,            4, 0x00000001 },
1822                 { BNX2X_CHIP_MASK_ALL,
1823                         NIG_REG_XCM0_OUT_EN,            4, 0x00000001 },
1824                 { BNX2X_CHIP_MASK_ALL,
1825                         NIG_REG_BRB0_OUT_EN,            4, 0x00000001 },
1826                 { BNX2X_CHIP_MASK_ALL,
1827                         NIG_REG_LLH0_XCM_MASK,          4, 0x00000007 },
1828                 { BNX2X_CHIP_MASK_ALL,
1829                         NIG_REG_LLH0_ACPI_PAT_6_LEN,    68, 0x000000ff },
1830                 { BNX2X_CHIP_MASK_ALL,
1831                         NIG_REG_LLH0_ACPI_PAT_0_CRC,    68, 0xffffffff },
1832                 { BNX2X_CHIP_MASK_ALL,
1833                         NIG_REG_LLH0_DEST_MAC_0_0,      160, 0xffffffff },
1834                 { BNX2X_CHIP_MASK_ALL,
1835                         NIG_REG_LLH0_DEST_IP_0_1,       160, 0xffffffff },
1836                 { BNX2X_CHIP_MASK_ALL,
1837                         NIG_REG_LLH0_IPV4_IPV6_0,       160, 0x00000001 },
1838 /* 30 */        { BNX2X_CHIP_MASK_ALL,
1839                         NIG_REG_LLH0_DEST_UDP_0,        160, 0x0000ffff },
1840                 { BNX2X_CHIP_MASK_ALL,
1841                         NIG_REG_LLH0_DEST_TCP_0,        160, 0x0000ffff },
1842                 { BNX2X_CHIP_MASK_ALL,
1843                         NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
1844                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1845                         NIG_REG_XGXS_SERDES0_MODE_SEL,  4, 0x00000001 },
1846                 { BNX2X_CHIP_MASK_ALL,
1847                         NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
1848                 { BNX2X_CHIP_MASK_ALL,
1849                         NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
1850                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1851                         NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1852                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1853                         NIG_REG_SERDES0_CTRL_PHY_ADDR,  16, 0x0000001f },
1854
1855                 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
1856         };
1857
1858         if (!netif_running(bp->dev)) {
1859                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1860                    "cannot access eeprom when the interface is down\n");
1861                 return rc;
1862         }
1863
1864         if (CHIP_IS_E1(bp))
1865                 hw = BNX2X_CHIP_MASK_E1;
1866         else if (CHIP_IS_E1H(bp))
1867                 hw = BNX2X_CHIP_MASK_E1H;
1868         else if (CHIP_IS_E2(bp))
1869                 hw = BNX2X_CHIP_MASK_E2;
1870         else if (CHIP_IS_E3B0(bp))
1871                 hw = BNX2X_CHIP_MASK_E3B0;
1872         else /* e3 A0 */
1873                 hw = BNX2X_CHIP_MASK_E3;
1874
1875         /* Repeat the test twice:
1876            First by writing 0x00000000, second by writing 0xffffffff */
1877         for (idx = 0; idx < 2; idx++) {
1878
1879                 switch (idx) {
1880                 case 0:
1881                         wr_val = 0;
1882                         break;
1883                 case 1:
1884                         wr_val = 0xffffffff;
1885                         break;
1886                 }
1887
1888                 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1889                         u32 offset, mask, save_val, val;
1890                         if (!(hw & reg_tbl[i].hw))
1891                                 continue;
1892
1893                         offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1894                         mask = reg_tbl[i].mask;
1895
1896                         save_val = REG_RD(bp, offset);
1897
1898                         REG_WR(bp, offset, wr_val & mask);
1899
1900                         val = REG_RD(bp, offset);
1901
1902                         /* Restore the original register's value */
1903                         REG_WR(bp, offset, save_val);
1904
1905                         /* verify value is as expected */
1906                         if ((val & mask) != (wr_val & mask)) {
1907                                 DP(BNX2X_MSG_ETHTOOL,
1908                                    "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1909                                    offset, val, wr_val, mask);
1910                                 goto test_reg_exit;
1911                         }
1912                 }
1913         }
1914
1915         rc = 0;
1916
1917 test_reg_exit:
1918         return rc;
1919 }
1920
1921 static int bnx2x_test_memory(struct bnx2x *bp)
1922 {
1923         int i, j, rc = -ENODEV;
1924         u32 val, index;
1925         static const struct {
1926                 u32 offset;
1927                 int size;
1928         } mem_tbl[] = {
1929                 { CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
1930                 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1931                 { CFC_REG_LINK_LIST,        CFC_REG_LINK_LIST_SIZE },
1932                 { DMAE_REG_CMD_MEM,         DMAE_REG_CMD_MEM_SIZE },
1933                 { TCM_REG_XX_DESCR_TABLE,   TCM_REG_XX_DESCR_TABLE_SIZE },
1934                 { UCM_REG_XX_DESCR_TABLE,   UCM_REG_XX_DESCR_TABLE_SIZE },
1935                 { XCM_REG_XX_DESCR_TABLE,   XCM_REG_XX_DESCR_TABLE_SIZE },
1936
1937                 { 0xffffffff, 0 }
1938         };
1939
1940         static const struct {
1941                 char *name;
1942                 u32 offset;
1943                 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
1944         } prty_tbl[] = {
1945                 { "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,
1946                         {0x3ffc0, 0,   0, 0} },
1947                 { "CFC_PRTY_STS",  CFC_REG_CFC_PRTY_STS,
1948                         {0x2,     0x2, 0, 0} },
1949                 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
1950                         {0,       0,   0, 0} },
1951                 { "TCM_PRTY_STS",  TCM_REG_TCM_PRTY_STS,
1952                         {0x3ffc0, 0,   0, 0} },
1953                 { "UCM_PRTY_STS",  UCM_REG_UCM_PRTY_STS,
1954                         {0x3ffc0, 0,   0, 0} },
1955                 { "XCM_PRTY_STS",  XCM_REG_XCM_PRTY_STS,
1956                         {0x3ffc1, 0,   0, 0} },
1957
1958                 { NULL, 0xffffffff, {0, 0, 0, 0} }
1959         };
1960
1961         if (!netif_running(bp->dev)) {
1962                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1963                    "cannot access eeprom when the interface is down\n");
1964                 return rc;
1965         }
1966
1967         if (CHIP_IS_E1(bp))
1968                 index = BNX2X_CHIP_E1_OFST;
1969         else if (CHIP_IS_E1H(bp))
1970                 index = BNX2X_CHIP_E1H_OFST;
1971         else if (CHIP_IS_E2(bp))
1972                 index = BNX2X_CHIP_E2_OFST;
1973         else /* e3 */
1974                 index = BNX2X_CHIP_E3_OFST;
1975
1976         /* pre-Check the parity status */
1977         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1978                 val = REG_RD(bp, prty_tbl[i].offset);
1979                 if (val & ~(prty_tbl[i].hw_mask[index])) {
1980                         DP(BNX2X_MSG_ETHTOOL,
1981                            "%s is 0x%x\n", prty_tbl[i].name, val);
1982                         goto test_mem_exit;
1983                 }
1984         }
1985
1986         /* Go through all the memories */
1987         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1988                 for (j = 0; j < mem_tbl[i].size; j++)
1989                         REG_RD(bp, mem_tbl[i].offset + j*4);
1990
1991         /* Check the parity status */
1992         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1993                 val = REG_RD(bp, prty_tbl[i].offset);
1994                 if (val & ~(prty_tbl[i].hw_mask[index])) {
1995                         DP(BNX2X_MSG_ETHTOOL,
1996                            "%s is 0x%x\n", prty_tbl[i].name, val);
1997                         goto test_mem_exit;
1998                 }
1999         }
2000
2001         rc = 0;
2002
2003 test_mem_exit:
2004         return rc;
2005 }
2006
2007 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
2008 {
2009         int cnt = 1400;
2010
2011         if (link_up) {
2012                 while (bnx2x_link_test(bp, is_serdes) && cnt--)
2013                         msleep(20);
2014
2015                 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
2016                         DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
2017
2018                 cnt = 1400;
2019                 while (!bp->link_vars.link_up && cnt--)
2020                         msleep(20);
2021
2022                 if (cnt <= 0 && !bp->link_vars.link_up)
2023                         DP(BNX2X_MSG_ETHTOOL,
2024                            "Timeout waiting for link init\n");
2025         }
2026 }
2027
2028 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
2029 {
2030         unsigned int pkt_size, num_pkts, i;
2031         struct sk_buff *skb;
2032         unsigned char *packet;
2033         struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2034         struct bnx2x_fastpath *fp_tx = &bp->fp[0];
2035         struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
2036         u16 tx_start_idx, tx_idx;
2037         u16 rx_start_idx, rx_idx;
2038         u16 pkt_prod, bd_prod;
2039         struct sw_tx_bd *tx_buf;
2040         struct eth_tx_start_bd *tx_start_bd;
2041         struct eth_tx_parse_bd_e1x  *pbd_e1x = NULL;
2042         struct eth_tx_parse_bd_e2  *pbd_e2 = NULL;
2043         dma_addr_t mapping;
2044         union eth_rx_cqe *cqe;
2045         u8 cqe_fp_flags, cqe_fp_type;
2046         struct sw_rx_bd *rx_buf;
2047         u16 len;
2048         int rc = -ENODEV;
2049         u8 *data;
2050         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2051                                                        txdata->txq_index);
2052
2053         /* check the loopback mode */
2054         switch (loopback_mode) {
2055         case BNX2X_PHY_LOOPBACK:
2056                 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2057                         DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
2058                         return -EINVAL;
2059                 }
2060                 break;
2061         case BNX2X_MAC_LOOPBACK:
2062                 if (CHIP_IS_E3(bp)) {
2063                         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2064                         if (bp->port.supported[cfg_idx] &
2065                             (SUPPORTED_10000baseT_Full |
2066                              SUPPORTED_20000baseMLD2_Full |
2067                              SUPPORTED_20000baseKR2_Full))
2068                                 bp->link_params.loopback_mode = LOOPBACK_XMAC;
2069                         else
2070                                 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2071                 } else
2072                         bp->link_params.loopback_mode = LOOPBACK_BMAC;
2073
2074                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2075                 break;
2076         case BNX2X_EXT_LOOPBACK:
2077                 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2078                         DP(BNX2X_MSG_ETHTOOL,
2079                            "Can't configure external loopback\n");
2080                         return -EINVAL;
2081                 }
2082                 break;
2083         default:
2084                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2085                 return -EINVAL;
2086         }
2087
2088         /* prepare the loopback packet */
2089         pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2090                      bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
2091         skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
2092         if (!skb) {
2093                 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
2094                 rc = -ENOMEM;
2095                 goto test_loopback_exit;
2096         }
2097         packet = skb_put(skb, pkt_size);
2098         memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2099         memset(packet + ETH_ALEN, 0, ETH_ALEN);
2100         memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2101         for (i = ETH_HLEN; i < pkt_size; i++)
2102                 packet[i] = (unsigned char) (i & 0xff);
2103         mapping = dma_map_single(&bp->pdev->dev, skb->data,
2104                                  skb_headlen(skb), DMA_TO_DEVICE);
2105         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2106                 rc = -ENOMEM;
2107                 dev_kfree_skb(skb);
2108                 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
2109                 goto test_loopback_exit;
2110         }
2111
2112         /* send the loopback packet */
2113         num_pkts = 0;
2114         tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
2115         rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2116
2117         netdev_tx_sent_queue(txq, skb->len);
2118
2119         pkt_prod = txdata->tx_pkt_prod++;
2120         tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2121         tx_buf->first_bd = txdata->tx_bd_prod;
2122         tx_buf->skb = skb;
2123         tx_buf->flags = 0;
2124
2125         bd_prod = TX_BD(txdata->tx_bd_prod);
2126         tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
2127         tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2128         tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2129         tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2130         tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
2131         tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
2132         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2133         SET_FLAG(tx_start_bd->general_data,
2134                  ETH_TX_START_BD_ETH_ADDR_TYPE,
2135                  UNICAST_ADDRESS);
2136         SET_FLAG(tx_start_bd->general_data,
2137                  ETH_TX_START_BD_HDR_NBDS,
2138                  1);
2139
2140         /* turn on parsing and get a BD */
2141         bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
2142
2143         pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2144         pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2145
2146         memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2147         memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2148
2149         wmb();
2150
2151         txdata->tx_db.data.prod += 2;
2152         barrier();
2153         DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
2154
2155         mmiowb();
2156         barrier();
2157
2158         num_pkts++;
2159         txdata->tx_bd_prod += 2; /* start + pbd */
2160
2161         udelay(100);
2162
2163         tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
2164         if (tx_idx != tx_start_idx + num_pkts)
2165                 goto test_loopback_exit;
2166
2167         /* Unlike HC IGU won't generate an interrupt for status block
2168          * updates that have been performed while interrupts were
2169          * disabled.
2170          */
2171         if (bp->common.int_block == INT_BLOCK_IGU) {
2172                 /* Disable local BHes to prevent a dead-lock situation between
2173                  * sch_direct_xmit() and bnx2x_run_loopback() (calling
2174                  * bnx2x_tx_int()), as both are taking netif_tx_lock().
2175                  */
2176                 local_bh_disable();
2177                 bnx2x_tx_int(bp, txdata);
2178                 local_bh_enable();
2179         }
2180
2181         rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2182         if (rx_idx != rx_start_idx + num_pkts)
2183                 goto test_loopback_exit;
2184
2185         cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
2186         cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2187         cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2188         if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
2189                 goto test_loopback_rx_exit;
2190
2191         len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
2192         if (len != pkt_size)
2193                 goto test_loopback_rx_exit;
2194
2195         rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
2196         dma_sync_single_for_cpu(&bp->pdev->dev,
2197                                    dma_unmap_addr(rx_buf, mapping),
2198                                    fp_rx->rx_buf_size, DMA_FROM_DEVICE);
2199         data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
2200         for (i = ETH_HLEN; i < pkt_size; i++)
2201                 if (*(data + i) != (unsigned char) (i & 0xff))
2202                         goto test_loopback_rx_exit;
2203
2204         rc = 0;
2205
2206 test_loopback_rx_exit:
2207
2208         fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2209         fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2210         fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2211         fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2212
2213         /* Update producers */
2214         bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2215                              fp_rx->rx_sge_prod);
2216
2217 test_loopback_exit:
2218         bp->link_params.loopback_mode = LOOPBACK_NONE;
2219
2220         return rc;
2221 }
2222
2223 static int bnx2x_test_loopback(struct bnx2x *bp)
2224 {
2225         int rc = 0, res;
2226
2227         if (BP_NOMCP(bp))
2228                 return rc;
2229
2230         if (!netif_running(bp->dev))
2231                 return BNX2X_LOOPBACK_FAILED;
2232
2233         bnx2x_netif_stop(bp, 1);
2234         bnx2x_acquire_phy_lock(bp);
2235
2236         res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
2237         if (res) {
2238                 DP(BNX2X_MSG_ETHTOOL, "  PHY loopback failed  (res %d)\n", res);
2239                 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2240         }
2241
2242         res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
2243         if (res) {
2244                 DP(BNX2X_MSG_ETHTOOL, "  MAC loopback failed  (res %d)\n", res);
2245                 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2246         }
2247
2248         bnx2x_release_phy_lock(bp);
2249         bnx2x_netif_start(bp);
2250
2251         return rc;
2252 }
2253
2254 static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2255 {
2256         int rc;
2257         u8 is_serdes =
2258                 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2259
2260         if (BP_NOMCP(bp))
2261                 return -ENODEV;
2262
2263         if (!netif_running(bp->dev))
2264                 return BNX2X_EXT_LOOPBACK_FAILED;
2265
2266         bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2267         rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2268         if (rc) {
2269                 DP(BNX2X_MSG_ETHTOOL,
2270                    "Can't perform self-test, nic_load (for external lb) failed\n");
2271                 return -ENODEV;
2272         }
2273         bnx2x_wait_for_link(bp, 1, is_serdes);
2274
2275         bnx2x_netif_stop(bp, 1);
2276
2277         rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2278         if (rc)
2279                 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed  (res %d)\n", rc);
2280
2281         bnx2x_netif_start(bp);
2282
2283         return rc;
2284 }
2285
2286 #define CRC32_RESIDUAL                  0xdebb20e3
2287
2288 static int bnx2x_test_nvram(struct bnx2x *bp)
2289 {
2290         static const struct {
2291                 int offset;
2292                 int size;
2293         } nvram_tbl[] = {
2294                 {     0,  0x14 }, /* bootstrap */
2295                 {  0x14,  0xec }, /* dir */
2296                 { 0x100, 0x350 }, /* manuf_info */
2297                 { 0x450,  0xf0 }, /* feature_info */
2298                 { 0x640,  0x64 }, /* upgrade_key_info */
2299                 { 0x708,  0x70 }, /* manuf_key_info */
2300                 {     0,     0 }
2301         };
2302         __be32 *buf;
2303         u8 *data;
2304         int i, rc;
2305         u32 magic, crc;
2306
2307         if (BP_NOMCP(bp))
2308                 return 0;
2309
2310         buf = kmalloc(0x350, GFP_KERNEL);
2311         if (!buf) {
2312                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
2313                 rc = -ENOMEM;
2314                 goto test_nvram_exit;
2315         }
2316         data = (u8 *)buf;
2317
2318         rc = bnx2x_nvram_read(bp, 0, data, 4);
2319         if (rc) {
2320                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2321                    "magic value read (rc %d)\n", rc);
2322                 goto test_nvram_exit;
2323         }
2324
2325         magic = be32_to_cpu(buf[0]);
2326         if (magic != 0x669955aa) {
2327                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2328                    "wrong magic value (0x%08x)\n", magic);
2329                 rc = -ENODEV;
2330                 goto test_nvram_exit;
2331         }
2332
2333         for (i = 0; nvram_tbl[i].size; i++) {
2334
2335                 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
2336                                       nvram_tbl[i].size);
2337                 if (rc) {
2338                         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2339                            "nvram_tbl[%d] read data (rc %d)\n", i, rc);
2340                         goto test_nvram_exit;
2341                 }
2342
2343                 crc = ether_crc_le(nvram_tbl[i].size, data);
2344                 if (crc != CRC32_RESIDUAL) {
2345                         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2346                            "nvram_tbl[%d] wrong crc value (0x%08x)\n", i, crc);
2347                         rc = -ENODEV;
2348                         goto test_nvram_exit;
2349                 }
2350         }
2351
2352 test_nvram_exit:
2353         kfree(buf);
2354         return rc;
2355 }
2356
2357 /* Send an EMPTY ramrod on the first queue */
2358 static int bnx2x_test_intr(struct bnx2x *bp)
2359 {
2360         struct bnx2x_queue_state_params params = {NULL};
2361
2362         if (!netif_running(bp->dev)) {
2363                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2364                    "cannot access eeprom when the interface is down\n");
2365                 return -ENODEV;
2366         }
2367
2368         params.q_obj = &bp->sp_objs->q_obj;
2369         params.cmd = BNX2X_Q_CMD_EMPTY;
2370
2371         __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2372
2373         return bnx2x_queue_state_change(bp, &params);
2374 }
2375
2376 static void bnx2x_self_test(struct net_device *dev,
2377                             struct ethtool_test *etest, u64 *buf)
2378 {
2379         struct bnx2x *bp = netdev_priv(dev);
2380         u8 is_serdes;
2381         int rc;
2382
2383         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
2384                 netdev_err(bp->dev,
2385                            "Handling parity error recovery. Try again later\n");
2386                 etest->flags |= ETH_TEST_FL_FAILED;
2387                 return;
2388         }
2389         DP(BNX2X_MSG_ETHTOOL,
2390            "Self-test command parameters: offline = %d, external_lb = %d\n",
2391            (etest->flags & ETH_TEST_FL_OFFLINE),
2392            (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
2393
2394         memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
2395
2396         if (!netif_running(dev)) {
2397                 DP(BNX2X_MSG_ETHTOOL,
2398                    "Can't perform self-test when interface is down\n");
2399                 return;
2400         }
2401
2402         is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2403
2404         /* offline tests are not supported in MF mode */
2405         if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
2406                 int port = BP_PORT(bp);
2407                 u32 val;
2408                 u8 link_up;
2409
2410                 /* save current value of input enable for TX port IF */
2411                 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2412                 /* disable input for TX port IF */
2413                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2414
2415                 link_up = bp->link_vars.link_up;
2416
2417                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2418                 rc = bnx2x_nic_load(bp, LOAD_DIAG);
2419                 if (rc) {
2420                         etest->flags |= ETH_TEST_FL_FAILED;
2421                         DP(BNX2X_MSG_ETHTOOL,
2422                            "Can't perform self-test, nic_load (for offline) failed\n");
2423                         return;
2424                 }
2425
2426                 /* wait until link state is restored */
2427                 bnx2x_wait_for_link(bp, 1, is_serdes);
2428
2429                 if (bnx2x_test_registers(bp) != 0) {
2430                         buf[0] = 1;
2431                         etest->flags |= ETH_TEST_FL_FAILED;
2432                 }
2433                 if (bnx2x_test_memory(bp) != 0) {
2434                         buf[1] = 1;
2435                         etest->flags |= ETH_TEST_FL_FAILED;
2436                 }
2437
2438                 buf[2] = bnx2x_test_loopback(bp); /* internal LB */
2439                 if (buf[2] != 0)
2440                         etest->flags |= ETH_TEST_FL_FAILED;
2441
2442                 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
2443                         buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
2444                         if (buf[3] != 0)
2445                                 etest->flags |= ETH_TEST_FL_FAILED;
2446                         etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
2447                 }
2448
2449                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2450
2451                 /* restore input for TX port IF */
2452                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
2453                 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
2454                 if (rc) {
2455                         etest->flags |= ETH_TEST_FL_FAILED;
2456                         DP(BNX2X_MSG_ETHTOOL,
2457                            "Can't perform self-test, nic_load (for online) failed\n");
2458                         return;
2459                 }
2460                 /* wait until link state is restored */
2461                 bnx2x_wait_for_link(bp, link_up, is_serdes);
2462         }
2463         if (bnx2x_test_nvram(bp) != 0) {
2464                 if (!IS_MF(bp))
2465                         buf[4] = 1;
2466                 else
2467                         buf[0] = 1;
2468                 etest->flags |= ETH_TEST_FL_FAILED;
2469         }
2470         if (bnx2x_test_intr(bp) != 0) {
2471                 if (!IS_MF(bp))
2472                         buf[5] = 1;
2473                 else
2474                         buf[1] = 1;
2475                 etest->flags |= ETH_TEST_FL_FAILED;
2476         }
2477
2478         if (bnx2x_link_test(bp, is_serdes) != 0) {
2479                 if (!IS_MF(bp))
2480                         buf[6] = 1;
2481                 else
2482                         buf[2] = 1;
2483                 etest->flags |= ETH_TEST_FL_FAILED;
2484         }
2485
2486 #ifdef BNX2X_EXTRA_DEBUG
2487         bnx2x_panic_dump(bp);
2488 #endif
2489 }
2490
2491 #define IS_PORT_STAT(i) \
2492         ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
2493 #define IS_FUNC_STAT(i)         (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
2494 #define IS_MF_MODE_STAT(bp) \
2495                         (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
2496
2497 /* ethtool statistics are displayed for all regular ethernet queues and the
2498  * fcoe L2 queue if not disabled
2499  */
2500 static int bnx2x_num_stat_queues(struct bnx2x *bp)
2501 {
2502         return BNX2X_NUM_ETH_QUEUES(bp);
2503 }
2504
2505 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
2506 {
2507         struct bnx2x *bp = netdev_priv(dev);
2508         int i, num_stats;
2509
2510         switch (stringset) {
2511         case ETH_SS_STATS:
2512                 if (is_multi(bp)) {
2513                         num_stats = bnx2x_num_stat_queues(bp) *
2514                                                 BNX2X_NUM_Q_STATS;
2515                 } else
2516                         num_stats = 0;
2517                 if (IS_MF_MODE_STAT(bp)) {
2518                         for (i = 0; i < BNX2X_NUM_STATS; i++)
2519                                 if (IS_FUNC_STAT(i))
2520                                         num_stats++;
2521                 } else
2522                         num_stats += BNX2X_NUM_STATS;
2523
2524                 return num_stats;
2525
2526         case ETH_SS_TEST:
2527                 return BNX2X_NUM_TESTS(bp);
2528
2529         default:
2530                 return -EINVAL;
2531         }
2532 }
2533
2534 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
2535 {
2536         struct bnx2x *bp = netdev_priv(dev);
2537         int i, j, k, offset, start;
2538         char queue_name[MAX_QUEUE_NAME_LEN+1];
2539
2540         switch (stringset) {
2541         case ETH_SS_STATS:
2542                 k = 0;
2543                 if (is_multi(bp)) {
2544                         for_each_eth_queue(bp, i) {
2545                                 memset(queue_name, 0, sizeof(queue_name));
2546                                 sprintf(queue_name, "%d", i);
2547                                 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
2548                                         snprintf(buf + (k + j)*ETH_GSTRING_LEN,
2549                                                 ETH_GSTRING_LEN,
2550                                                 bnx2x_q_stats_arr[j].string,
2551                                                 queue_name);
2552                                 k += BNX2X_NUM_Q_STATS;
2553                         }
2554                 }
2555
2556
2557                 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2558                         if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2559                                 continue;
2560                         strcpy(buf + (k + j)*ETH_GSTRING_LEN,
2561                                    bnx2x_stats_arr[i].string);
2562                         j++;
2563                 }
2564
2565                 break;
2566
2567         case ETH_SS_TEST:
2568                 /* First 4 tests cannot be done in MF mode */
2569                 if (!IS_MF(bp))
2570                         start = 0;
2571                 else
2572                         start = 4;
2573                 for (i = 0, j = start; j < (start + BNX2X_NUM_TESTS(bp));
2574                      i++, j++) {
2575                         offset = sprintf(buf+32*i, "%s",
2576                                          bnx2x_tests_str_arr[j]);
2577                         *(buf+offset) = '\0';
2578                 }
2579                 break;
2580         }
2581 }
2582
2583 static void bnx2x_get_ethtool_stats(struct net_device *dev,
2584                                     struct ethtool_stats *stats, u64 *buf)
2585 {
2586         struct bnx2x *bp = netdev_priv(dev);
2587         u32 *hw_stats, *offset;
2588         int i, j, k = 0;
2589
2590         if (is_multi(bp)) {
2591                 for_each_eth_queue(bp, i) {
2592                         hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
2593                         for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2594                                 if (bnx2x_q_stats_arr[j].size == 0) {
2595                                         /* skip this counter */
2596                                         buf[k + j] = 0;
2597                                         continue;
2598                                 }
2599                                 offset = (hw_stats +
2600                                           bnx2x_q_stats_arr[j].offset);
2601                                 if (bnx2x_q_stats_arr[j].size == 4) {
2602                                         /* 4-byte counter */
2603                                         buf[k + j] = (u64) *offset;
2604                                         continue;
2605                                 }
2606                                 /* 8-byte counter */
2607                                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2608                         }
2609                         k += BNX2X_NUM_Q_STATS;
2610                 }
2611         }
2612
2613         hw_stats = (u32 *)&bp->eth_stats;
2614         for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2615                 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2616                         continue;
2617                 if (bnx2x_stats_arr[i].size == 0) {
2618                         /* skip this counter */
2619                         buf[k + j] = 0;
2620                         j++;
2621                         continue;
2622                 }
2623                 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2624                 if (bnx2x_stats_arr[i].size == 4) {
2625                         /* 4-byte counter */
2626                         buf[k + j] = (u64) *offset;
2627                         j++;
2628                         continue;
2629                 }
2630                 /* 8-byte counter */
2631                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2632                 j++;
2633         }
2634 }
2635
2636 static int bnx2x_set_phys_id(struct net_device *dev,
2637                              enum ethtool_phys_id_state state)
2638 {
2639         struct bnx2x *bp = netdev_priv(dev);
2640
2641         if (!netif_running(dev)) {
2642                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2643                    "cannot access eeprom when the interface is down\n");
2644                 return -EAGAIN;
2645         }
2646
2647         if (!bp->port.pmf) {
2648                 DP(BNX2X_MSG_ETHTOOL, "Interface is not pmf\n");
2649                 return -EOPNOTSUPP;
2650         }
2651
2652         switch (state) {
2653         case ETHTOOL_ID_ACTIVE:
2654                 return 1;       /* cycle on/off once per second */
2655
2656         case ETHTOOL_ID_ON:
2657                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2658                               LED_MODE_ON, SPEED_1000);
2659                 break;
2660
2661         case ETHTOOL_ID_OFF:
2662                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2663                               LED_MODE_FRONT_PANEL_OFF, 0);
2664
2665                 break;
2666
2667         case ETHTOOL_ID_INACTIVE:
2668                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2669                               LED_MODE_OPER,
2670                               bp->link_vars.line_speed);
2671         }
2672
2673         return 0;
2674 }
2675
2676 static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
2677 {
2678
2679         switch (info->flow_type) {
2680         case TCP_V4_FLOW:
2681         case TCP_V6_FLOW:
2682                 info->data = RXH_IP_SRC | RXH_IP_DST |
2683                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
2684                 break;
2685         case UDP_V4_FLOW:
2686                 if (bp->rss_conf_obj.udp_rss_v4)
2687                         info->data = RXH_IP_SRC | RXH_IP_DST |
2688                                      RXH_L4_B_0_1 | RXH_L4_B_2_3;
2689                 else
2690                         info->data = RXH_IP_SRC | RXH_IP_DST;
2691                 break;
2692         case UDP_V6_FLOW:
2693                 if (bp->rss_conf_obj.udp_rss_v6)
2694                         info->data = RXH_IP_SRC | RXH_IP_DST |
2695                                      RXH_L4_B_0_1 | RXH_L4_B_2_3;
2696                 else
2697                         info->data = RXH_IP_SRC | RXH_IP_DST;
2698                 break;
2699         case IPV4_FLOW:
2700         case IPV6_FLOW:
2701                 info->data = RXH_IP_SRC | RXH_IP_DST;
2702                 break;
2703         default:
2704                 info->data = 0;
2705                 break;
2706         }
2707
2708         return 0;
2709 }
2710
2711 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2712                            u32 *rules __always_unused)
2713 {
2714         struct bnx2x *bp = netdev_priv(dev);
2715
2716         switch (info->cmd) {
2717         case ETHTOOL_GRXRINGS:
2718                 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2719                 return 0;
2720         case ETHTOOL_GRXFH:
2721                 return bnx2x_get_rss_flags(bp, info);
2722         default:
2723                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2724                 return -EOPNOTSUPP;
2725         }
2726 }
2727
2728 static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
2729 {
2730         int udp_rss_requested;
2731
2732         DP(BNX2X_MSG_ETHTOOL,
2733            "Set rss flags command parameters: flow type = %d, data = %llu\n",
2734            info->flow_type, info->data);
2735
2736         switch (info->flow_type) {
2737         case TCP_V4_FLOW:
2738         case TCP_V6_FLOW:
2739                 /* For TCP only 4-tupple hash is supported */
2740                 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
2741                                   RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2742                         DP(BNX2X_MSG_ETHTOOL,
2743                            "Command parameters not supported\n");
2744                         return -EINVAL;
2745                 } else {
2746                         return 0;
2747                 }
2748
2749         case UDP_V4_FLOW:
2750         case UDP_V6_FLOW:
2751                 /* For UDP either 2-tupple hash or 4-tupple hash is supported */
2752                 if (info->data == (RXH_IP_SRC | RXH_IP_DST |
2753                                  RXH_L4_B_0_1 | RXH_L4_B_2_3))
2754                         udp_rss_requested = 1;
2755                 else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
2756                         udp_rss_requested = 0;
2757                 else
2758                         return -EINVAL;
2759                 if ((info->flow_type == UDP_V4_FLOW) &&
2760                     (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
2761                         bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
2762                         DP(BNX2X_MSG_ETHTOOL,
2763                            "rss re-configured, UDP 4-tupple %s\n",
2764                            udp_rss_requested ? "enabled" : "disabled");
2765                         return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0);
2766                 } else if ((info->flow_type == UDP_V6_FLOW) &&
2767                            (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
2768                         bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
2769                         return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0);
2770                         DP(BNX2X_MSG_ETHTOOL,
2771                            "rss re-configured, UDP 4-tupple %s\n",
2772                            udp_rss_requested ? "enabled" : "disabled");
2773                 } else {
2774                         return 0;
2775                 }
2776         case IPV4_FLOW:
2777         case IPV6_FLOW:
2778                 /* For IP only 2-tupple hash is supported */
2779                 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
2780                         DP(BNX2X_MSG_ETHTOOL,
2781                            "Command parameters not supported\n");
2782                         return -EINVAL;
2783                 } else {
2784                         return 0;
2785                 }
2786         case SCTP_V4_FLOW:
2787         case AH_ESP_V4_FLOW:
2788         case AH_V4_FLOW:
2789         case ESP_V4_FLOW:
2790         case SCTP_V6_FLOW:
2791         case AH_ESP_V6_FLOW:
2792         case AH_V6_FLOW:
2793         case ESP_V6_FLOW:
2794         case IP_USER_FLOW:
2795         case ETHER_FLOW:
2796                 /* RSS is not supported for these protocols */
2797                 if (info->data) {
2798                         DP(BNX2X_MSG_ETHTOOL,
2799                            "Command parameters not supported\n");
2800                         return -EINVAL;
2801                 } else {
2802                         return 0;
2803                 }
2804         default:
2805                 return -EINVAL;
2806         }
2807 }
2808
2809 static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
2810 {
2811         struct bnx2x *bp = netdev_priv(dev);
2812
2813         switch (info->cmd) {
2814         case ETHTOOL_SRXFH:
2815                 return bnx2x_set_rss_flags(bp, info);
2816         default:
2817                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2818                 return -EOPNOTSUPP;
2819         }
2820 }
2821
2822 static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
2823 {
2824         return T_ETH_INDIRECTION_TABLE_SIZE;
2825 }
2826
2827 static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir)
2828 {
2829         struct bnx2x *bp = netdev_priv(dev);
2830         u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2831         size_t i;
2832
2833         /* Get the current configuration of the RSS indirection table */
2834         bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
2835
2836         /*
2837          * We can't use a memcpy() as an internal storage of an
2838          * indirection table is a u8 array while indir->ring_index
2839          * points to an array of u32.
2840          *
2841          * Indirection table contains the FW Client IDs, so we need to
2842          * align the returned table to the Client ID of the leading RSS
2843          * queue.
2844          */
2845         for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
2846                 indir[i] = ind_table[i] - bp->fp->cl_id;
2847
2848         return 0;
2849 }
2850
2851 static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir)
2852 {
2853         struct bnx2x *bp = netdev_priv(dev);
2854         size_t i;
2855
2856         for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
2857                 /*
2858                  * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
2859                  * as an internal storage of an indirection table is a u8 array
2860                  * while indir->ring_index points to an array of u32.
2861                  *
2862                  * Indirection table contains the FW Client IDs, so we need to
2863                  * align the received table to the Client ID of the leading RSS
2864                  * queue
2865                  */
2866                 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
2867         }
2868
2869         return bnx2x_config_rss_eth(bp, false);
2870 }
2871
2872 /**
2873  * bnx2x_get_channels - gets the number of RSS queues.
2874  *
2875  * @dev:                net device
2876  * @channels:           returns the number of max / current queues
2877  */
2878 static void bnx2x_get_channels(struct net_device *dev,
2879                                struct ethtool_channels *channels)
2880 {
2881         struct bnx2x *bp = netdev_priv(dev);
2882
2883         channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
2884         channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
2885 }
2886
2887 /**
2888  * bnx2x_change_num_queues - change the number of RSS queues.
2889  *
2890  * @bp:                 bnx2x private structure
2891  *
2892  * Re-configure interrupt mode to get the new number of MSI-X
2893  * vectors and re-add NAPI objects.
2894  */
2895 static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
2896 {
2897         bnx2x_disable_msi(bp);
2898         BNX2X_NUM_QUEUES(bp) = num_rss + NON_ETH_CONTEXT_USE;
2899         bnx2x_set_int_mode(bp);
2900 }
2901
2902 /**
2903  * bnx2x_set_channels - sets the number of RSS queues.
2904  *
2905  * @dev:                net device
2906  * @channels:           includes the number of queues requested
2907  */
2908 static int bnx2x_set_channels(struct net_device *dev,
2909                               struct ethtool_channels *channels)
2910 {
2911         struct bnx2x *bp = netdev_priv(dev);
2912
2913
2914         DP(BNX2X_MSG_ETHTOOL,
2915            "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
2916            channels->rx_count, channels->tx_count, channels->other_count,
2917            channels->combined_count);
2918
2919         /* We don't support separate rx / tx channels.
2920          * We don't allow setting 'other' channels.
2921          */
2922         if (channels->rx_count || channels->tx_count || channels->other_count
2923             || (channels->combined_count == 0) ||
2924             (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
2925                 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
2926                 return -EINVAL;
2927         }
2928
2929         /* Check if there was a change in the active parameters */
2930         if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
2931                 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
2932                 return 0;
2933         }
2934
2935         /* Set the requested number of queues in bp context.
2936          * Note that the actual number of queues created during load may be
2937          * less than requested if memory is low.
2938          */
2939         if (unlikely(!netif_running(dev))) {
2940                 bnx2x_change_num_queues(bp, channels->combined_count);
2941                 return 0;
2942         }
2943         bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2944         bnx2x_change_num_queues(bp, channels->combined_count);
2945         return bnx2x_nic_load(bp, LOAD_NORMAL);
2946 }
2947
2948 static const struct ethtool_ops bnx2x_ethtool_ops = {
2949         .get_settings           = bnx2x_get_settings,
2950         .set_settings           = bnx2x_set_settings,
2951         .get_drvinfo            = bnx2x_get_drvinfo,
2952         .get_regs_len           = bnx2x_get_regs_len,
2953         .get_regs               = bnx2x_get_regs,
2954         .get_wol                = bnx2x_get_wol,
2955         .set_wol                = bnx2x_set_wol,
2956         .get_msglevel           = bnx2x_get_msglevel,
2957         .set_msglevel           = bnx2x_set_msglevel,
2958         .nway_reset             = bnx2x_nway_reset,
2959         .get_link               = bnx2x_get_link,
2960         .get_eeprom_len         = bnx2x_get_eeprom_len,
2961         .get_eeprom             = bnx2x_get_eeprom,
2962         .set_eeprom             = bnx2x_set_eeprom,
2963         .get_coalesce           = bnx2x_get_coalesce,
2964         .set_coalesce           = bnx2x_set_coalesce,
2965         .get_ringparam          = bnx2x_get_ringparam,
2966         .set_ringparam          = bnx2x_set_ringparam,
2967         .get_pauseparam         = bnx2x_get_pauseparam,
2968         .set_pauseparam         = bnx2x_set_pauseparam,
2969         .self_test              = bnx2x_self_test,
2970         .get_sset_count         = bnx2x_get_sset_count,
2971         .get_strings            = bnx2x_get_strings,
2972         .set_phys_id            = bnx2x_set_phys_id,
2973         .get_ethtool_stats      = bnx2x_get_ethtool_stats,
2974         .get_rxnfc              = bnx2x_get_rxnfc,
2975         .set_rxnfc              = bnx2x_set_rxnfc,
2976         .get_rxfh_indir_size    = bnx2x_get_rxfh_indir_size,
2977         .get_rxfh_indir         = bnx2x_get_rxfh_indir,
2978         .set_rxfh_indir         = bnx2x_set_rxfh_indir,
2979         .get_channels           = bnx2x_get_channels,
2980         .set_channels           = bnx2x_set_channels,
2981         .get_module_info        = bnx2x_get_module_info,
2982         .get_module_eeprom      = bnx2x_get_module_eeprom,
2983         .get_eee                = bnx2x_get_eee,
2984         .set_eee                = bnx2x_set_eee,
2985         .get_ts_info            = ethtool_op_get_ts_info,
2986 };
2987
2988 void bnx2x_set_ethtool_ops(struct net_device *netdev)
2989 {
2990         SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2991 }