1 /* bnx2x_cmn.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2012 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
20 #include <linux/types.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
28 /* This is used as a replacement for an MCP if it's not present */
29 extern int load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */
31 extern int num_queues;
33 /************************ Macros ********************************/
34 #define BNX2X_PCI_FREE(x, y, size) \
37 dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \
43 #define BNX2X_FREE(x) \
51 #define BNX2X_PCI_ALLOC(x, y, size) \
53 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
56 memset((void *)x, 0, size); \
59 #define BNX2X_ALLOC(x, size) \
61 x = kzalloc(size, GFP_KERNEL); \
66 /*********************** Interfaces ****************************
67 * Functions that need to be implemented by each driver version
72 * bnx2x_send_unload_req - request unload mode from the MCP.
75 * @unload_mode: requested function's unload mode
77 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
79 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode);
82 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
86 void bnx2x_send_unload_done(struct bnx2x *bp);
89 * bnx2x_config_rss_pf - configure RSS parameters in a PF.
92 * @rss_obj RSS object to use
93 * @ind_table: indirection table to configure
94 * @config_hash: re-configure RSS hash keys configuration
96 int bnx2x_config_rss_pf(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj,
100 * bnx2x__init_func_obj - init function object
104 * Initializes the Function Object with the appropriate
105 * parameters which include a function slow path driver
108 void bnx2x__init_func_obj(struct bnx2x *bp);
111 * bnx2x_setup_queue - setup eth queue.
114 * @fp: pointer to the fastpath structure
118 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
122 * bnx2x_setup_leading - bring up a leading eth queue.
126 int bnx2x_setup_leading(struct bnx2x *bp);
129 * bnx2x_fw_command - send the MCP a request
133 * @param: request's parameter
135 * block until there is a reply
137 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param);
140 * bnx2x_initial_phy_init - initialize link parameters structure variables.
143 * @load_mode: current mode
145 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode);
148 * bnx2x_link_set - configure hw according to link parameters structure.
152 void bnx2x_link_set(struct bnx2x *bp);
155 * bnx2x_link_test - query link status.
160 * Returns 0 if link is UP.
162 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes);
165 * bnx2x_drv_pulse - write driver pulse to shmem
169 * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox
172 void bnx2x_drv_pulse(struct bnx2x *bp);
175 * bnx2x_igu_ack_sb - update IGU with current SB value
179 * @segment: SB segment
182 * @update: is HW update required
184 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
185 u16 index, u8 op, u8 update);
187 /* Disable transactions from chip to host */
188 void bnx2x_pf_disable(struct bnx2x *bp);
191 * bnx2x__link_status_update - handles link status change.
195 void bnx2x__link_status_update(struct bnx2x *bp);
198 * bnx2x_link_report - report link status to upper layer.
202 void bnx2x_link_report(struct bnx2x *bp);
204 /* None-atomic version of bnx2x_link_report() */
205 void __bnx2x_link_report(struct bnx2x *bp);
208 * bnx2x_get_mf_speed - calculate MF speed.
212 * Takes into account current linespeed and MF configuration.
214 u16 bnx2x_get_mf_speed(struct bnx2x *bp);
217 * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler
220 * @dev_instance: private instance
222 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance);
225 * bnx2x_interrupt - non MSI-X interrupt handler
228 * @dev_instance: private instance
230 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance);
234 * bnx2x_cnic_notify - send command to cnic driver
239 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd);
242 * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information
246 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp);
249 * bnx2x_setup_cnic_info - provides cnic with updated info
253 void bnx2x_setup_cnic_info(struct bnx2x *bp);
258 * bnx2x_int_enable - enable HW interrupts.
262 void bnx2x_int_enable(struct bnx2x *bp);
265 * bnx2x_int_disable_sync - disable interrupts.
268 * @disable_hw: true, disable HW interrupts.
270 * This function ensures that there are no
271 * ISRs or SP DPCs (sp_task) are running after it returns.
273 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw);
276 * bnx2x_nic_init - init driver internals.
279 * @load_code: COMMON, PORT or FUNCTION
286 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code);
289 * bnx2x_alloc_mem - allocate driver's memory.
293 int bnx2x_alloc_mem(struct bnx2x *bp);
296 * bnx2x_free_mem - release driver's memory.
300 void bnx2x_free_mem(struct bnx2x *bp);
303 * bnx2x_set_num_queues - set number of queues according to mode.
307 void bnx2x_set_num_queues(struct bnx2x *bp);
310 * bnx2x_chip_cleanup - cleanup chip internals.
313 * @unload_mode: COMMON, PORT, FUNCTION
315 * - Cleanup MAC configuration.
319 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode);
322 * bnx2x_acquire_hw_lock - acquire HW lock.
325 * @resource: resource bit which was locked
327 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource);
330 * bnx2x_release_hw_lock - release HW lock.
333 * @resource: resource bit which was locked
335 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource);
338 * bnx2x_release_leader_lock - release recovery leader lock
342 int bnx2x_release_leader_lock(struct bnx2x *bp);
345 * bnx2x_set_eth_mac - configure eth MAC address in the HW
350 * Configures according to the value in netdev->dev_addr.
352 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set);
355 * bnx2x_set_rx_mode - set MAC filtering configurations.
359 * called with netif_tx_lock from dev_mcast.c
360 * If bp->state is OPEN, should be called with
361 * netif_addr_lock_bh()
363 void bnx2x_set_rx_mode(struct net_device *dev);
366 * bnx2x_set_storm_rx_mode - configure MAC filtering rules in a FW.
370 * If bp->state is OPEN, should be called with
371 * netif_addr_lock_bh().
373 void bnx2x_set_storm_rx_mode(struct bnx2x *bp);
376 * bnx2x_set_q_rx_mode - configures rx_mode for a single queue.
380 * @rx_mode_flags: rx mode configuration
381 * @rx_accept_flags: rx accept configuration
382 * @tx_accept_flags: tx accept configuration (tx switch)
383 * @ramrod_flags: ramrod configuration
385 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
386 unsigned long rx_mode_flags,
387 unsigned long rx_accept_flags,
388 unsigned long tx_accept_flags,
389 unsigned long ramrod_flags);
391 /* Parity errors related */
392 void bnx2x_set_pf_load(struct bnx2x *bp);
393 bool bnx2x_clear_pf_load(struct bnx2x *bp);
394 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print);
395 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine);
396 void bnx2x_set_reset_in_progress(struct bnx2x *bp);
397 void bnx2x_set_reset_global(struct bnx2x *bp);
398 void bnx2x_disable_close_the_gate(struct bnx2x *bp);
401 * bnx2x_sp_event - handle ramrods completion.
403 * @fp: fastpath handle for the event
404 * @rr_cqe: eth_rx_cqe
406 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe);
409 * bnx2x_ilt_set_info - prepare ILT configurations.
413 void bnx2x_ilt_set_info(struct bnx2x *bp);
416 * bnx2x_dcbx_init - initialize dcbx protocol.
420 void bnx2x_dcbx_init(struct bnx2x *bp);
423 * bnx2x_set_power_state - set power state to the requested value.
426 * @state: required state D0 or D3hot
428 * Currently only D0 and D3hot are supported.
430 int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state);
433 * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW.
438 void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value);
440 void bnx2x_panic_dump(struct bnx2x *bp);
442 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl);
444 /* validate currect fw is loaded */
445 bool bnx2x_test_firmware_version(struct bnx2x *bp, bool is_err);
447 /* dev_close main block */
448 int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode);
450 /* dev_open main block */
451 int bnx2x_nic_load(struct bnx2x *bp, int load_mode);
453 /* hard_xmit callback */
454 netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev);
456 /* setup_tc callback */
457 int bnx2x_setup_tc(struct net_device *dev, u8 num_tc);
459 /* select_queue callback */
460 u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb);
463 int bnx2x_reload_if_running(struct net_device *dev);
465 int bnx2x_change_mac_addr(struct net_device *dev, void *p);
467 /* NAPI poll Rx part */
468 int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget);
470 void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
471 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod);
473 /* NAPI poll Tx part */
474 int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata);
476 /* suspend/resume callbacks */
477 int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state);
478 int bnx2x_resume(struct pci_dev *pdev);
480 /* Release IRQ vectors */
481 void bnx2x_free_irq(struct bnx2x *bp);
483 void bnx2x_free_fp_mem(struct bnx2x *bp);
484 int bnx2x_alloc_fp_mem(struct bnx2x *bp);
485 void bnx2x_init_rx_rings(struct bnx2x *bp);
486 void bnx2x_free_skbs(struct bnx2x *bp);
487 void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw);
488 void bnx2x_netif_start(struct bnx2x *bp);
491 * bnx2x_enable_msix - set msix configuration.
495 * fills msix_table, requests vectors, updates num_queues
496 * according to number of available vectors.
498 int __devinit bnx2x_enable_msix(struct bnx2x *bp);
501 * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly
505 int bnx2x_enable_msi(struct bnx2x *bp);
508 * bnx2x_poll - NAPI callback
510 * @napi: napi structure
514 int bnx2x_poll(struct napi_struct *napi, int budget);
517 * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure
521 int __devinit bnx2x_alloc_mem_bp(struct bnx2x *bp);
524 * bnx2x_free_mem_bp - release memories outsize main driver structure
528 void bnx2x_free_mem_bp(struct bnx2x *bp);
531 * bnx2x_change_mtu - change mtu netdev callback
534 * @new_mtu: requested mtu
537 int bnx2x_change_mtu(struct net_device *dev, int new_mtu);
539 #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
541 * bnx2x_fcoe_get_wwn - return the requested WWN value for this port
544 * @wwn: output buffer
545 * @type: WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port)
548 int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type);
551 netdev_features_t bnx2x_fix_features(struct net_device *dev,
552 netdev_features_t features);
553 int bnx2x_set_features(struct net_device *dev, netdev_features_t features);
556 * bnx2x_tx_timeout - tx timeout netdev callback
560 void bnx2x_tx_timeout(struct net_device *dev);
562 /*********************** Inlines **********************************/
563 /*********************** Fast path ********************************/
564 static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
566 barrier(); /* status block is written to by the chip */
567 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
570 static inline void bnx2x_update_rx_prod_gen(struct bnx2x *bp,
571 struct bnx2x_fastpath *fp, u16 bd_prod,
572 u16 rx_comp_prod, u16 rx_sge_prod, u32 start)
574 struct ustorm_eth_rx_producers rx_prods = {0};
577 /* Update producers */
578 rx_prods.bd_prod = bd_prod;
579 rx_prods.cqe_prod = rx_comp_prod;
580 rx_prods.sge_prod = rx_sge_prod;
583 * Make sure that the BD and SGE data is updated before updating the
584 * producers since FW might read the BD/SGE right after the producer
586 * This is only applicable for weak-ordered memory model archs such
587 * as IA-64. The following barrier is also mandatory since FW will
588 * assumes BDs must have buffers.
592 for (i = 0; i < sizeof(rx_prods)/4; i++)
593 REG_WR(bp, start + i*4, ((u32 *)&rx_prods)[i]);
595 mmiowb(); /* keep prod updates ordered */
597 DP(NETIF_MSG_RX_STATUS,
598 "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n",
599 fp->index, bd_prod, rx_comp_prod, rx_sge_prod);
602 static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id,
603 u8 segment, u16 index, u8 op,
604 u8 update, u32 igu_addr)
606 struct igu_regular cmd_data = {0};
608 cmd_data.sb_id_and_flags =
609 ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
610 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
611 (update << IGU_REGULAR_BUPDATE_SHIFT) |
612 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
614 DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n",
615 cmd_data.sb_id_and_flags, igu_addr);
616 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags);
618 /* Make sure that ACK is written */
623 static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id,
624 u8 storm, u16 index, u8 op, u8 update)
626 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
627 COMMAND_REG_INT_ACK);
628 struct igu_ack_register igu_ack;
630 igu_ack.status_block_index = index;
631 igu_ack.sb_id_and_flags =
632 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
633 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
634 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
635 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
637 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
639 /* Make sure that ACK is written */
644 static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm,
645 u16 index, u8 op, u8 update)
647 if (bp->common.int_block == INT_BLOCK_HC)
648 bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update);
652 if (CHIP_INT_MODE_IS_BC(bp))
654 else if (igu_sb_id != bp->igu_dsb_id)
655 segment = IGU_SEG_ACCESS_DEF;
656 else if (storm == ATTENTION_ID)
657 segment = IGU_SEG_ACCESS_ATTN;
659 segment = IGU_SEG_ACCESS_DEF;
660 bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update);
664 static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp)
666 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
667 COMMAND_REG_SIMD_MASK);
668 u32 result = REG_RD(bp, hc_addr);
674 static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp)
676 u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8);
677 u32 result = REG_RD(bp, igu_addr);
679 DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n",
686 static inline u16 bnx2x_ack_int(struct bnx2x *bp)
689 if (bp->common.int_block == INT_BLOCK_HC)
690 return bnx2x_hc_ack_int(bp);
692 return bnx2x_igu_ack_int(bp);
695 static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata)
697 /* Tell compiler that consumer and producer can change */
699 return txdata->tx_pkt_prod != txdata->tx_pkt_cons;
702 static inline u16 bnx2x_tx_avail(struct bnx2x *bp,
703 struct bnx2x_fp_txdata *txdata)
709 prod = txdata->tx_bd_prod;
710 cons = txdata->tx_bd_cons;
712 /* NUM_TX_RINGS = number of "next-page" entries
713 It will be used as a threshold */
714 used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS;
716 #ifdef BNX2X_STOP_ON_ERROR
718 WARN_ON(used > bp->tx_ring_size);
719 WARN_ON((bp->tx_ring_size - used) > MAX_TX_AVAIL);
722 return (s16)(bp->tx_ring_size) - used;
725 static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata)
729 /* Tell compiler that status block fields can change */
731 hw_cons = le16_to_cpu(*txdata->tx_cons_sb);
732 return hw_cons != txdata->tx_pkt_cons;
735 static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
738 for_each_cos_in_tx_queue(fp, cos)
739 if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos]))
744 static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
748 /* Tell compiler that status block fields can change */
750 rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb);
751 if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
753 return (fp->rx_comp_cons != rx_cons_sb);
757 * bnx2x_tx_disable - disables tx from stack point of view
761 static inline void bnx2x_tx_disable(struct bnx2x *bp)
763 netif_tx_disable(bp->dev);
764 netif_carrier_off(bp->dev);
767 static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
768 struct bnx2x_fastpath *fp, u16 index)
770 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
771 struct page *page = sw_buf->page;
772 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
774 /* Skip "next page" elements */
778 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping),
779 SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE);
780 __free_pages(page, PAGES_PER_SGE_SHIFT);
787 static inline void bnx2x_add_all_napi(struct bnx2x *bp)
791 /* Add NAPI objects */
792 for_each_rx_queue(bp, i)
793 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
794 bnx2x_poll, BNX2X_NAPI_WEIGHT);
797 static inline void bnx2x_del_all_napi(struct bnx2x *bp)
801 for_each_rx_queue(bp, i)
802 netif_napi_del(&bnx2x_fp(bp, i, napi));
805 static inline void bnx2x_disable_msi(struct bnx2x *bp)
807 if (bp->flags & USING_MSIX_FLAG) {
808 pci_disable_msix(bp->pdev);
809 bp->flags &= ~(USING_MSIX_FLAG | USING_SINGLE_MSIX_FLAG);
810 } else if (bp->flags & USING_MSI_FLAG) {
811 pci_disable_msi(bp->pdev);
812 bp->flags &= ~USING_MSI_FLAG;
816 static inline int bnx2x_calc_num_queues(struct bnx2x *bp)
819 min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) :
820 min_t(int, num_online_cpus(), BNX2X_MAX_QUEUES(bp));
823 static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
827 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
828 int idx = RX_SGE_CNT * i - 1;
830 for (j = 0; j < 2; j++) {
831 BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx);
837 static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
839 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
840 memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask));
842 /* Clear the two last indices in the page to 1:
843 these are the indices that correspond to the "next" element,
844 hence will never be indicated and should be removed from
846 bnx2x_clear_sge_mask_next_elems(fp);
849 /* note that we are not allocating a new buffer,
850 * we are just moving one from cons to prod
851 * we are not creating a new mapping,
852 * so there is no need to check for dma_mapping_error().
854 static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp,
857 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
858 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
859 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
860 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
862 dma_unmap_addr_set(prod_rx_buf, mapping,
863 dma_unmap_addr(cons_rx_buf, mapping));
864 prod_rx_buf->data = cons_rx_buf->data;
868 /************************* Init ******************************************/
870 /* returns func by VN for current port */
871 static inline int func_by_vn(struct bnx2x *bp, int vn)
873 return 2 * vn + BP_PORT(bp);
876 static inline int bnx2x_config_rss_eth(struct bnx2x *bp, bool config_hash)
878 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, config_hash);
882 * bnx2x_func_start - init function
886 * Must be called before sending CLIENT_SETUP for the first client.
888 static inline int bnx2x_func_start(struct bnx2x *bp)
890 struct bnx2x_func_state_params func_params = {NULL};
891 struct bnx2x_func_start_params *start_params =
892 &func_params.params.start;
894 /* Prepare parameters for function state transitions */
895 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
897 func_params.f_obj = &bp->func_obj;
898 func_params.cmd = BNX2X_F_CMD_START;
900 /* Function parameters */
901 start_params->mf_mode = bp->mf_mode;
902 start_params->sd_vlan_tag = bp->mf_ov;
904 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp))
905 start_params->network_cos_mode = STATIC_COS;
906 else /* CHIP_IS_E1X */
907 start_params->network_cos_mode = FW_WRR;
909 return bnx2x_func_state_change(bp, &func_params);
914 * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format
916 * @fw_hi: pointer to upper part
917 * @fw_mid: pointer to middle part
918 * @fw_lo: pointer to lower part
919 * @mac: pointer to MAC address
921 static inline void bnx2x_set_fw_mac_addr(u16 *fw_hi, u16 *fw_mid, u16 *fw_lo,
924 ((u8 *)fw_hi)[0] = mac[1];
925 ((u8 *)fw_hi)[1] = mac[0];
926 ((u8 *)fw_mid)[0] = mac[3];
927 ((u8 *)fw_mid)[1] = mac[2];
928 ((u8 *)fw_lo)[0] = mac[5];
929 ((u8 *)fw_lo)[1] = mac[4];
932 static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
933 struct bnx2x_fastpath *fp, int last)
940 for (i = 0; i < last; i++)
941 bnx2x_free_rx_sge(bp, fp, i);
944 static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp)
948 for (i = 1; i <= NUM_RX_RINGS; i++) {
949 struct eth_rx_bd *rx_bd;
951 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
953 cpu_to_le32(U64_HI(fp->rx_desc_mapping +
954 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
956 cpu_to_le32(U64_LO(fp->rx_desc_mapping +
957 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
961 /* Statistics ID are global per chip/path, while Client IDs for E1x are per
964 static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp)
966 struct bnx2x *bp = fp->bp;
967 if (!CHIP_IS_E1x(bp)) {
969 /* there are special statistics counters for FCoE 136..140 */
971 return bp->cnic_base_cl_id + (bp->pf_num >> 1);
975 return fp->cl_id + BP_PORT(bp) * FP_SB_MAX_E1x;
978 static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp,
979 bnx2x_obj_type obj_type)
981 struct bnx2x *bp = fp->bp;
983 /* Configure classification DBs */
984 bnx2x_init_mac_obj(bp, &bnx2x_sp_obj(bp, fp).mac_obj, fp->cl_id,
985 fp->cid, BP_FUNC(bp), bnx2x_sp(bp, mac_rdata),
986 bnx2x_sp_mapping(bp, mac_rdata),
987 BNX2X_FILTER_MAC_PENDING,
988 &bp->sp_state, obj_type,
993 * bnx2x_get_path_func_num - get number of active functions
997 * Calculates the number of active (not hidden) functions on the
1000 static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp)
1004 /* 57710 has only one function per-port */
1008 /* Calculate a number of functions enabled on the current
1011 if (CHIP_REV_IS_SLOW(bp)) {
1017 for (i = 0; i < E1H_FUNC_MAX / 2; i++) {
1020 func_mf_config[BP_PORT(bp) + 2 * i].
1023 ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1);
1032 static inline void bnx2x_init_bp_objs(struct bnx2x *bp)
1034 /* RX_MODE controlling object */
1035 bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj);
1037 /* multicast configuration controlling object */
1038 bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid,
1039 BP_FUNC(bp), BP_FUNC(bp),
1040 bnx2x_sp(bp, mcast_rdata),
1041 bnx2x_sp_mapping(bp, mcast_rdata),
1042 BNX2X_FILTER_MCAST_PENDING, &bp->sp_state,
1045 /* Setup CAM credit pools */
1046 bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp),
1047 bnx2x_get_path_func_num(bp));
1049 /* RSS configuration object */
1050 bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id,
1051 bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp),
1052 bnx2x_sp(bp, rss_rdata),
1053 bnx2x_sp_mapping(bp, rss_rdata),
1054 BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state,
1058 static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
1060 if (CHIP_IS_E1x(fp->bp))
1061 return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H;
1066 static inline u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
1068 struct bnx2x *bp = fp->bp;
1070 if (!CHIP_IS_E1x(bp))
1071 return USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
1073 return USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
1076 static inline void bnx2x_init_txdata(struct bnx2x *bp,
1077 struct bnx2x_fp_txdata *txdata, u32 cid,
1078 int txq_index, __le16 *tx_cons_sb,
1079 struct bnx2x_fastpath *fp)
1082 txdata->txq_index = txq_index;
1083 txdata->tx_cons_sb = tx_cons_sb;
1084 txdata->parent_fp = fp;
1086 DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n",
1087 txdata->cid, txdata->txq_index);
1091 static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx)
1093 return bp->cnic_base_cl_id + cl_idx +
1094 (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX;
1097 static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp)
1100 /* the 'first' id is allocated for the cnic */
1101 return bp->base_fw_ndsb;
1104 static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp)
1106 return bp->igu_base_sb;
1110 static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp)
1112 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
1113 unsigned long q_type = 0;
1115 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
1116 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
1117 BNX2X_FCOE_ETH_CL_ID_IDX);
1118 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
1119 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
1120 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
1121 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
1122 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
1123 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
1126 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
1128 /* qZone id equals to FW (per path) client id */
1129 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
1131 bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
1132 bnx2x_rx_ustorm_prods_offset(fp);
1134 /* Configure Queue State object */
1135 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
1136 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
1138 /* No multi-CoS for FCoE L2 client */
1139 BUG_ON(fp->max_cos != 1);
1141 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
1142 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
1143 bnx2x_sp_mapping(bp, q_rdata), q_type);
1146 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
1147 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
1152 static inline int bnx2x_clean_tx_queue(struct bnx2x *bp,
1153 struct bnx2x_fp_txdata *txdata)
1157 while (bnx2x_has_tx_work_unload(txdata)) {
1159 BNX2X_ERR("timeout waiting for queue[%d]: txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n",
1160 txdata->txq_index, txdata->tx_pkt_prod,
1161 txdata->tx_pkt_cons);
1162 #ifdef BNX2X_STOP_ON_ERROR
1170 usleep_range(1000, 1000);
1176 int bnx2x_get_link_cfg_idx(struct bnx2x *bp);
1178 static inline void __storm_memset_struct(struct bnx2x *bp,
1179 u32 addr, size_t size, u32 *data)
1182 for (i = 0; i < size/4; i++)
1183 REG_WR(bp, addr + (i * 4), data[i]);
1187 * bnx2x_wait_sp_comp - wait for the outstanding SP commands.
1189 * @bp: driver handle
1190 * @mask: bits that need to be cleared
1192 static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask)
1194 int tout = 5000; /* Wait for 5 secs tops */
1198 netif_addr_lock_bh(bp->dev);
1199 if (!(bp->sp_state & mask)) {
1200 netif_addr_unlock_bh(bp->dev);
1203 netif_addr_unlock_bh(bp->dev);
1205 usleep_range(1000, 1000);
1210 netif_addr_lock_bh(bp->dev);
1211 if (bp->sp_state & mask) {
1212 BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, mask 0x%lx\n",
1213 bp->sp_state, mask);
1214 netif_addr_unlock_bh(bp->dev);
1217 netif_addr_unlock_bh(bp->dev);
1223 * bnx2x_set_ctx_validation - set CDU context validation values
1225 * @bp: driver handle
1226 * @cxt: context of the connection on the host memory
1227 * @cid: SW CID of the connection to be configured
1229 void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt,
1232 void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id,
1233 u8 sb_index, u8 disable, u16 usec);
1234 void bnx2x_acquire_phy_lock(struct bnx2x *bp);
1235 void bnx2x_release_phy_lock(struct bnx2x *bp);
1238 * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration.
1240 * @bp: driver handle
1241 * @mf_cfg: MF configuration
1244 static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg)
1246 u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
1247 FUNC_MF_CFG_MAX_BW_SHIFT;
1249 DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL,
1250 "Max BW configured to 0 - using 100 instead\n");
1256 /* checks if HW supports GRO for given MTU */
1257 static inline bool bnx2x_mtu_allows_gro(int mtu)
1259 /* gro frags per page */
1260 int fpp = SGE_PAGE_SIZE / (mtu - ETH_MAX_TPA_HEADER_SIZE);
1263 * 1. number of frags should not grow above MAX_SKB_FRAGS
1264 * 2. frag must fit the page
1266 return mtu <= SGE_PAGE_SIZE && (U_ETH_SGL_SIZE * fpp) <= MAX_SKB_FRAGS;
1270 * bnx2x_get_iscsi_info - update iSCSI params according to licensing info.
1272 * @bp: driver handle
1275 void bnx2x_get_iscsi_info(struct bnx2x *bp);
1279 * bnx2x_link_sync_notify - send notification to other functions.
1281 * @bp: driver handle
1284 static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
1289 /* Set the attention towards other drivers on the same port */
1290 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
1291 if (vn == BP_VN(bp))
1294 func = func_by_vn(bp, vn);
1295 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
1296 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
1301 * bnx2x_update_drv_flags - update flags in shmem
1303 * @bp: driver handle
1304 * @flags: flags to update
1305 * @set: set or clear
1308 static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set)
1310 if (SHMEM2_HAS(bp, drv_flags)) {
1312 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS);
1313 drv_flags = SHMEM2_RD(bp, drv_flags);
1316 SET_FLAGS(drv_flags, flags);
1318 RESET_FLAGS(drv_flags, flags);
1320 SHMEM2_WR(bp, drv_flags, drv_flags);
1321 DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags);
1322 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS);
1326 static inline bool bnx2x_is_valid_ether_addr(struct bnx2x *bp, u8 *addr)
1328 if (is_valid_ether_addr(addr))
1331 if (is_zero_ether_addr(addr) &&
1332 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp)))
1338 #endif /* BNX2X_CMN_H */