1 /* bnx2x.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2012 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
17 #include <linux/pci.h>
18 #include <linux/netdevice.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/types.h>
21 #include <linux/pci_regs.h>
23 /* compilation time flags */
25 /* define this to make the driver freeze on error to allow getting debug info
26 * (you will need to reboot afterwards) */
27 /* #define BNX2X_STOP_ON_ERROR */
29 #define DRV_MODULE_VERSION "1.78.00-0"
30 #define DRV_MODULE_RELDATE "2012/09/27"
31 #define BNX2X_BC_VER 0x040200
33 #if defined(CONFIG_DCB)
38 #include "bnx2x_hsi.h"
40 #include "../cnic_if.h"
43 #define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt)
45 #include <linux/mdio.h>
47 #include "bnx2x_reg.h"
48 #include "bnx2x_fw_defs.h"
49 #include "bnx2x_mfw_req.h"
50 #include "bnx2x_link.h"
52 #include "bnx2x_dcb.h"
53 #include "bnx2x_stats.h"
54 #include "bnx2x_vfpf.h"
62 /* error/debug prints */
64 #define DRV_MODULE_NAME "bnx2x"
66 /* for messages that are currently off */
67 #define BNX2X_MSG_OFF 0x0
68 #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */
69 #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */
70 #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */
71 #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */
72 #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */
73 #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */
74 #define BNX2X_MSG_IOV 0x0800000
75 #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/
76 #define BNX2X_MSG_ETHTOOL 0x4000000
77 #define BNX2X_MSG_DCB 0x8000000
79 /* regular debug print */
80 #define DP(__mask, fmt, ...) \
82 if (unlikely(bp->msg_enable & (__mask))) \
83 pr_notice("[%s:%d(%s)]" fmt, \
85 bp->dev ? (bp->dev->name) : "?", \
89 #define DP_CONT(__mask, fmt, ...) \
91 if (unlikely(bp->msg_enable & (__mask))) \
92 pr_cont(fmt, ##__VA_ARGS__); \
95 /* errors debug print */
96 #define BNX2X_DBG_ERR(fmt, ...) \
98 if (unlikely(netif_msg_probe(bp))) \
99 pr_err("[%s:%d(%s)]" fmt, \
100 __func__, __LINE__, \
101 bp->dev ? (bp->dev->name) : "?", \
105 /* for errors (never masked) */
106 #define BNX2X_ERR(fmt, ...) \
108 pr_err("[%s:%d(%s)]" fmt, \
109 __func__, __LINE__, \
110 bp->dev ? (bp->dev->name) : "?", \
114 #define BNX2X_ERROR(fmt, ...) \
115 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__)
118 /* before we have a dev->name use dev_info() */
119 #define BNX2X_DEV_INFO(fmt, ...) \
121 if (unlikely(netif_msg_probe(bp))) \
122 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \
125 #ifdef BNX2X_STOP_ON_ERROR
126 void bnx2x_int_disable(struct bnx2x *bp);
127 #define bnx2x_panic() \
130 BNX2X_ERR("driver assert\n"); \
131 bnx2x_int_disable(bp); \
132 bnx2x_panic_dump(bp); \
135 #define bnx2x_panic() \
138 BNX2X_ERR("driver assert\n"); \
139 bnx2x_panic_dump(bp); \
143 #define bnx2x_mc_addr(ha) ((ha)->addr)
144 #define bnx2x_uc_addr(ha) ((ha)->addr)
146 #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
147 #define U64_HI(x) (u32)(((u64)(x)) >> 32)
148 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
151 #define REG_ADDR(bp, offset) ((bp->regview) + (offset))
153 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
154 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
155 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
157 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
158 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
159 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
161 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
162 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
164 #define REG_RD_DMAE(bp, offset, valp, len32) \
166 bnx2x_read_dmae(bp, offset, len32);\
167 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
170 #define REG_WR_DMAE(bp, offset, valp, len32) \
172 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
173 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
177 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
178 REG_WR_DMAE(bp, offset, valp, len32)
180 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
182 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
183 bnx2x_write_big_buf_wb(bp, addr, len32); \
186 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
187 offsetof(struct shmem_region, field))
188 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
189 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
191 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
192 offsetof(struct shmem2_region, field))
193 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
194 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
195 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
196 offsetof(struct mf_cfg, field))
197 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \
198 offsetof(struct mf2_cfg, field))
200 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
201 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
202 MF_CFG_ADDR(bp, field), (val))
203 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
205 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \
206 (SHMEM2_RD((bp), size) > \
207 offsetof(struct shmem2_region, field)))
209 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
210 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
214 /* General SP events - stats query, cfc delete, etc */
215 #define HC_SP_INDEX_ETH_DEF_CONS 3
218 #define HC_SP_INDEX_EQ_CONS 7
220 /* FCoE L2 connection completions */
221 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
222 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
224 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
225 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
227 /* Special clients parameters */
231 #define BNX2X_FCOE_L2_RX_INDEX \
232 (&bp->def_status_blk->sp_sb.\
233 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
235 #define BNX2X_FCOE_L2_TX_INDEX \
236 (&bp->def_status_blk->sp_sb.\
237 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
241 * CLIDs below is a CLID for func 0, then the CLID for other
242 * functions will be calculated by the formula:
244 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
248 BNX2X_ISCSI_ETH_CL_ID_IDX,
249 BNX2X_FCOE_ETH_CL_ID_IDX,
250 BNX2X_MAX_CNIC_ETH_CL_ID_IDX,
253 #define BNX2X_CNIC_START_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) *\
256 #define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp))
258 #define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1)
260 #define CNIC_SUPPORT(bp) ((bp)->cnic_support)
261 #define CNIC_ENABLED(bp) ((bp)->cnic_enabled)
262 #define CNIC_LOADED(bp) ((bp)->cnic_loaded)
263 #define FCOE_INIT(bp) ((bp)->fcoe_init)
265 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
266 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
271 /* defines for multiple tx priority indices */
272 #define FIRST_TX_ONLY_COS_INDEX 1
273 #define FIRST_TX_COS_INDEX 0
275 /* rules for calculating the cids of tx-only connections */
276 #define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp))
277 #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \
278 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
280 /* fp index inside class of service range */
281 #define FP_COS_TO_TXQ(fp, cos, bp) \
282 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
284 /* Indexes for transmission queues array:
285 * txdata for RSS i CoS j is at location i + (j * num of RSS)
286 * txdata for FCoE (if exist) is at location max cos * num of RSS
287 * txdata for FWD (if exist) is one location after FCoE
288 * txdata for OOO (if exist) is one location after FWD
295 #define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos)
296 #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET)
300 * This driver uses new build_skb() API :
301 * RX ring buffer contains pointer to kmalloc() data only,
302 * skb are built only after Hardware filled the frame.
306 DEFINE_DMA_UNMAP_ADDR(mapping);
313 /* Set on the first BD descriptor when there is a split BD */
314 #define BNX2X_TSO_SPLIT_BD (1<<0)
319 DEFINE_DMA_UNMAP_ADDR(mapping);
323 struct doorbell_set_prod data;
327 /* dropless fc FW/HW related params */
328 #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512)
329 #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \
330 ETH_MAX_AGGREGATION_QUEUES_E1 :\
331 ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
332 #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp))
333 #define FW_PREFETCH_CNT 16
334 #define DROPLESS_FC_HEADROOM 100
337 #define BCM_PAGE_SHIFT 12
338 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
339 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
340 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
342 #define PAGES_PER_SGE_SHIFT 0
343 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
344 #define SGE_PAGE_SIZE PAGE_SIZE
345 #define SGE_PAGE_SHIFT PAGE_SHIFT
346 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
347 #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE)
348 #define TPA_AGG_SIZE min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \
351 /* SGE ring related macros */
352 #define NUM_RX_SGE_PAGES 2
353 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
354 #define NEXT_PAGE_SGE_DESC_CNT 2
355 #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)
356 /* RX_SGE_CNT is promised to be a power of 2 */
357 #define RX_SGE_MASK (RX_SGE_CNT - 1)
358 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
359 #define MAX_RX_SGE (NUM_RX_SGE - 1)
360 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
361 (MAX_RX_SGE_CNT - 1)) ? \
362 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \
364 #define RX_SGE(x) ((x) & MAX_RX_SGE)
367 * Number of required SGEs is the sum of two:
368 * 1. Number of possible opened aggregations (next packet for
369 * these aggregations will probably consume SGE immidiatelly)
370 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
371 * after placement on BD for new TPA aggregation)
373 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page
375 #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \
376 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2)
377 #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \
379 #define SGE_TH_LO(bp) (NUM_SGE_REQ + \
380 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT)
381 #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM)
383 /* Manipulate a bit vector defined as an array of u64 */
385 /* Number of bits in one sge_mask array element */
386 #define BIT_VEC64_ELEM_SZ 64
387 #define BIT_VEC64_ELEM_SHIFT 6
388 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1)
391 #define __BIT_VEC64_SET_BIT(el, bit) \
393 el = ((el) | ((u64)0x1 << (bit))); \
396 #define __BIT_VEC64_CLEAR_BIT(el, bit) \
398 el = ((el) & (~((u64)0x1 << (bit)))); \
402 #define BIT_VEC64_SET_BIT(vec64, idx) \
403 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
404 (idx) & BIT_VEC64_ELEM_MASK)
406 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \
407 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
408 (idx) & BIT_VEC64_ELEM_MASK)
410 #define BIT_VEC64_TEST_BIT(vec64, idx) \
411 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
412 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
414 /* Creates a bitmask of all ones in less significant bits.
415 idx - index of the most significant bit in the created mask */
416 #define BIT_VEC64_ONES_MASK(idx) \
417 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
418 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0))
420 /*******************************************************/
424 /* Number of u64 elements in SGE mask array */
425 #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ)
426 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
427 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
429 union host_hc_status_block {
430 /* pointer to fp status block e1x */
431 struct host_hc_status_block_e1x *e1x_sb;
432 /* pointer to fp status block e2 */
433 struct host_hc_status_block_e2 *e2_sb;
436 struct bnx2x_agg_info {
438 * First aggregation buffer is a data buffer, the following - are pages.
439 * We will preallocate the data buffer for each aggregation when
440 * we open the interface and will replace the BD at the consumer
441 * with this one when we receive the TPA_START CQE in order to
442 * keep the Rx BD ring consistent.
444 struct sw_rx_bd first_buf;
446 #define BNX2X_TPA_START 1
447 #define BNX2X_TPA_STOP 2
448 #define BNX2X_TPA_ERROR 3
459 #define Q_STATS_OFFSET32(stat_name) \
460 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
462 struct bnx2x_fp_txdata {
464 struct sw_tx_bd *tx_buf_ring;
466 union eth_tx_bd_types *tx_desc_ring;
467 dma_addr_t tx_desc_mapping;
478 unsigned long tx_pkt;
483 struct bnx2x_fastpath *parent_fp;
487 enum bnx2x_tpa_mode_t {
492 struct bnx2x_fastpath {
493 struct bnx2x *bp; /* parent */
495 #define BNX2X_NAPI_WEIGHT 128
496 struct napi_struct napi;
497 union host_hc_status_block status_blk;
498 /* chip independed shortcuts into sb structure */
499 __le16 *sb_index_values;
500 __le16 *sb_running_index;
501 /* chip independed shortcut into rx_prods_offset memory */
502 u32 ustorm_rx_prods_offset;
505 u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */
506 dma_addr_t status_blk_mapping;
508 enum bnx2x_tpa_mode_t mode;
510 u8 max_cos; /* actual number of active tx coses */
511 struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS];
513 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
514 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
516 struct eth_rx_bd *rx_desc_ring;
517 dma_addr_t rx_desc_mapping;
519 union eth_rx_cqe *rx_comp_ring;
520 dma_addr_t rx_comp_mapping;
523 struct eth_rx_sge *rx_sge_ring;
524 dma_addr_t rx_sge_mapping;
526 u64 sge_mask[RX_SGE_MASK_LEN];
532 u8 index; /* number in fp array */
533 u8 rx_queue; /* index for skb_record */
534 u8 cl_id; /* eth client id */
536 u8 fw_sb_id; /* status block number in FW */
537 u8 igu_sb_id; /* status block number in HW */
544 /* The last maximal completed SGE */
547 unsigned long rx_pkt,
551 struct bnx2x_agg_info *tpa_info;
553 #ifdef BNX2X_STOP_ON_ERROR
556 /* The size is calculated using the following:
557 sizeof name field from netdev structure +
559 4 (for the digits and to make it DWORD aligned) */
560 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
561 char name[FP_NAME_SIZE];
564 #define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var)
565 #define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index])
566 #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index]))
567 #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats))
569 /* Use 2500 as a mini-jumbo MTU for FCoE */
570 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500
572 #define FCOE_IDX_OFFSET 0
574 #define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \
576 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)])
577 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var)
578 #define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)])
579 #define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var)
580 #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \
581 txdata_ptr[FIRST_TX_COS_INDEX] \
585 #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp))
586 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp))
587 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp))
591 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
592 #define RX_COPY_THRESH 92
594 #define NUM_TX_RINGS 16
595 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
596 #define NEXT_PAGE_TX_DESC_CNT 1
597 #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT)
598 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
599 #define MAX_TX_BD (NUM_TX_BD - 1)
600 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
601 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
602 (MAX_TX_DESC_CNT - 1)) ? \
603 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \
605 #define TX_BD(x) ((x) & MAX_TX_BD)
606 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
608 /* number of NEXT_PAGE descriptors may be required during placement */
609 #define NEXT_CNT_PER_TX_PKT(bds) \
610 (((bds) + MAX_TX_DESC_CNT - 1) / \
611 MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT)
612 /* max BDs per tx packet w/o next_pages:
613 * START_BD - describes packed
614 * START_BD(splitted) - includes unpaged data segment for GSO
615 * PARSING_BD - for TSO and CSUM data
616 * Frag BDs - decribes pages for frags
618 #define BDS_PER_TX_PKT 3
619 #define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT)
620 /* max BDs per tx packet including next pages */
621 #define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \
622 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT))
624 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
625 #define NUM_RX_RINGS 8
626 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
627 #define NEXT_PAGE_RX_DESC_CNT 2
628 #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT)
629 #define RX_DESC_MASK (RX_DESC_CNT - 1)
630 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
631 #define MAX_RX_BD (NUM_RX_BD - 1)
632 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
634 /* dropless fc calculations for BDs
636 * Number of BDs should as number of buffers in BRB:
637 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT
638 * "next" elements on each page
640 #define NUM_BD_REQ BRB_SIZE(bp)
641 #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \
643 #define BD_TH_LO(bp) (NUM_BD_REQ + \
644 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \
646 #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM)
648 #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128)
650 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \
651 ETH_MIN_RX_CQES_WITH_TPA_E1 : \
652 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
653 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
654 #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
655 #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
658 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
659 (MAX_RX_DESC_CNT - 1)) ? \
660 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \
662 #define RX_BD(x) ((x) & MAX_RX_BD)
665 * As long as CQE is X times bigger than BD entry we have to allocate X times
666 * more pages for CQ ring in order to keep it balanced with BD ring
668 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
669 #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL)
670 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
671 #define NEXT_PAGE_RCQ_DESC_CNT 1
672 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT)
673 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
674 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
675 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
676 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
677 (MAX_RCQ_DESC_CNT - 1)) ? \
678 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \
680 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
682 /* dropless fc calculations for RCQs
684 * Number of RCQs should be as number of buffers in BRB:
685 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT
686 * "next" elements on each page
688 #define NUM_RCQ_REQ BRB_SIZE(bp)
689 #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \
691 #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \
692 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \
694 #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM)
697 /* This is needed for determining of last_max */
698 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
699 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b))
702 #define BNX2X_SWCID_SHIFT 17
703 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
705 /* used on a CID received from the HW */
706 #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK)
707 #define CQE_CMD(x) (le32_to_cpu(x) >> \
708 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
710 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
711 le32_to_cpu((bd)->addr_lo))
712 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
714 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
715 #define BNX2X_DB_SHIFT 7 /* 128 bytes*/
716 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
717 #error "Min DB doorbell stride is 8"
719 #define DPM_TRIGER_TYPE 0x40
720 #define DOORBELL(bp, cid, val) \
722 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \
727 /* TX CSUM helpers */
728 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
730 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
733 #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
736 #define XMIT_CSUM_V4 0x1
737 #define XMIT_CSUM_V6 0x2
738 #define XMIT_CSUM_TCP 0x4
739 #define XMIT_GSO_V4 0x8
740 #define XMIT_GSO_V6 0x10
742 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
743 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
746 /* stuff added to make the code fit 80Col */
747 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
748 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
749 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
750 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
751 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
753 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
755 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
756 (((le16_to_cpu(flags) & \
757 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
758 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
759 == PRS_FLAG_OVERETH_IPV4)
760 #define BNX2X_RX_SUM_FIX(cqe) \
761 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
764 #define FP_USB_FUNC_OFF \
765 offsetof(struct cstorm_status_block_u, func)
766 #define FP_CSB_FUNC_OFF \
767 offsetof(struct cstorm_status_block_c, func)
769 #define HC_INDEX_ETH_RX_CQ_CONS 1
771 #define HC_INDEX_OOO_TX_CQ_CONS 4
773 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
775 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
777 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
779 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
781 #define BNX2X_RX_SB_INDEX \
782 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
784 #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0
786 #define BNX2X_TX_SB_INDEX_COS0 \
787 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0])
789 /* end of fast path */
793 struct bnx2x_common {
796 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
797 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
799 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
800 #define CHIP_NUM_57710 0x164e
801 #define CHIP_NUM_57711 0x164f
802 #define CHIP_NUM_57711E 0x1650
803 #define CHIP_NUM_57712 0x1662
804 #define CHIP_NUM_57712_MF 0x1663
805 #define CHIP_NUM_57713 0x1651
806 #define CHIP_NUM_57713E 0x1652
807 #define CHIP_NUM_57800 0x168a
808 #define CHIP_NUM_57800_MF 0x16a5
809 #define CHIP_NUM_57810 0x168e
810 #define CHIP_NUM_57810_MF 0x16ae
811 #define CHIP_NUM_57811 0x163d
812 #define CHIP_NUM_57811_MF 0x163e
813 #define CHIP_NUM_57840_OBSOLETE 0x168d
814 #define CHIP_NUM_57840_MF_OBSOLETE 0x16ab
815 #define CHIP_NUM_57840_4_10 0x16a1
816 #define CHIP_NUM_57840_2_20 0x16a2
817 #define CHIP_NUM_57840_MF 0x16a4
818 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
819 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
820 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
821 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
822 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF)
823 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800)
824 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF)
825 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810)
826 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF)
827 #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811)
828 #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF)
829 #define CHIP_IS_57840(bp) \
830 ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \
831 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \
832 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE))
833 #define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \
834 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE))
835 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
837 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
838 CHIP_IS_57712_MF(bp))
839 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \
840 CHIP_IS_57800_MF(bp) || \
841 CHIP_IS_57810(bp) || \
842 CHIP_IS_57810_MF(bp) || \
843 CHIP_IS_57811(bp) || \
844 CHIP_IS_57811_MF(bp) || \
845 CHIP_IS_57840(bp) || \
846 CHIP_IS_57840_MF(bp))
847 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
848 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp))
849 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp))
851 #define CHIP_REV_SHIFT 12
852 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
853 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK)
854 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
855 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
856 /* assume maximum 5 revisions */
857 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000)
858 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
859 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
860 !(CHIP_REV_VAL(bp) & 0x00001000))
861 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
862 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
863 (CHIP_REV_VAL(bp) & 0x00001000))
865 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
866 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
868 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
869 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
870 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
871 (CHIP_REV_SHIFT + 1)) \
873 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \
876 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \
877 (CHIP_REV(bp) == CHIP_REV_Bx))
878 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \
879 (CHIP_REV(bp) == CHIP_REV_Ax))
880 /* This define is used in two main places:
881 * 1. In the early stages of nic_load, to know if to configrue Parser / Searcher
882 * to nic-only mode or to offload mode. Offload mode is configured if either the
883 * chip is E1x (where MIC_MODE register is not applicable), or if cnic already
884 * registered for this port (which means that the user wants storage services).
885 * 2. During cnic-related load, to know if offload mode is already configured in
886 * the HW or needs to be configrued.
887 * Since the transition from nic-mode to offload-mode in HW causes traffic
888 * coruption, nic-mode is configured only in ports on which storage services
889 * where never requested.
891 #define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp))
894 #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
895 #define BNX2X_NVRAM_TIMEOUT_COUNT 30000
896 #define BNX2X_NVRAM_PAGE_SIZE 256
908 #define INT_BLOCK_HC 0
909 #define INT_BLOCK_IGU 1
910 #define INT_BLOCK_MODE_NORMAL 0
911 #define INT_BLOCK_MODE_BW_COMP 2
912 #define CHIP_INT_MODE_IS_NBC(bp) \
913 (!CHIP_IS_E1x(bp) && \
914 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
915 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
918 #define CHIP_4_PORT_MODE 0x0
919 #define CHIP_2_PORT_MODE 0x1
920 #define CHIP_PORT_MODE_NONE 0x2
921 #define CHIP_MODE(bp) (bp->common.chip_port_mode)
922 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
927 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
928 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
929 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
931 #define MAX_IGU_ATTN_ACK_TO 100
939 u32 link_config[LINK_CONFIG_SIZE];
941 u32 supported[LINK_CONFIG_SIZE];
942 /* link settings - missing defines */
943 #define SUPPORTED_2500baseX_Full (1 << 15)
945 u32 advertising[LINK_CONFIG_SIZE];
946 /* link settings - missing defines */
947 #define ADVERTISED_2500baseX_Full (1 << 15)
951 /* used to synchronize phy accesses */
952 struct mutex phy_mutex;
956 struct nig_stats old_nig_stats;
961 #define STATS_OFFSET32(stat_name) \
962 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
966 /* slow path work-queue */
967 extern struct workqueue_struct *bnx2x_wq;
969 #define BNX2X_MAX_NUM_OF_VFS 64
970 #define BNX2X_VF_CID_WND 0
971 #define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND)
972 #define BNX2X_FIRST_VF_CID 256
973 #define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF)
974 #define BNX2X_VF_ID_INVALID 0xFF
977 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
978 * control by the number of fast-path status blocks supported by the
979 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
980 * status block represents an independent interrupts context that can
981 * serve a regular L2 networking queue. However special L2 queues such
982 * as the FCoE queue do not require a FP-SB and other components like
983 * the CNIC may consume FP-SB reducing the number of possible L2 queues
985 * If the maximum number of FP-SB available is X then:
986 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
987 * regular L2 queues is Y=X-1
988 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
989 * c. If the FCoE L2 queue is supported the actual number of L2 queues
991 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
992 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
993 * FP interrupt context for the CNIC).
994 * e. The number of HW context (CID count) is always X or X+1 if FCoE
995 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
998 /* fast-path interrupt contexts E1x */
999 #define FP_SB_MAX_E1x 16
1000 /* fast-path interrupt contexts E2 */
1001 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
1004 struct eth_context eth;
1008 /* CDU host DB constants */
1009 #define CDU_ILT_PAGE_SZ_HW 2
1010 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
1011 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
1013 #define CNIC_ISCSI_CID_MAX 256
1014 #define CNIC_FCOE_CID_MAX 2048
1015 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
1016 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
1018 #define QM_ILT_PAGE_SZ_HW 0
1019 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
1020 #define QM_CID_ROUND 1024
1022 /* TM (timers) host DB constants */
1023 #define TM_ILT_PAGE_SZ_HW 0
1024 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
1025 /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
1026 #define TM_CONN_NUM 1024
1027 #define TM_ILT_SZ (8 * TM_CONN_NUM)
1028 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
1030 /* SRC (Searcher) host DB constants */
1031 #define SRC_ILT_PAGE_SZ_HW 0
1032 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
1033 #define SRC_HASH_BITS 10
1034 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
1035 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
1036 #define SRC_T2_SZ SRC_ILT_SZ
1037 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
1039 #define MAX_DMAE_C 8
1041 /* DMA memory not used in fastpath */
1042 struct bnx2x_slowpath {
1044 struct mac_configuration_cmd e1x;
1045 struct eth_classify_rules_ramrod_data e2;
1050 struct tstorm_eth_mac_filter_config e1x;
1051 struct eth_filter_rules_ramrod_data e2;
1055 struct mac_configuration_cmd e1;
1056 struct eth_multicast_rules_ramrod_data e2;
1059 struct eth_rss_update_ramrod_data rss_rdata;
1061 /* Queue State related ramrods are always sent under rtnl_lock */
1063 struct client_init_ramrod_data init_data;
1064 struct client_update_ramrod_data update_data;
1068 struct function_start_data func_start;
1069 /* pfc configuration for DCBX ramrod */
1070 struct flow_control_configuration pfc_config;
1073 /* afex ramrod can not be a part of func_rdata union because these
1074 * events might arrive in parallel to other events from func_rdata.
1075 * Therefore, if they would have been defined in the same union,
1076 * data can get corrupted.
1078 struct afex_vif_list_ramrod_data func_afex_rdata;
1080 /* used by dmae command executer */
1081 struct dmae_command dmae[MAX_DMAE_C];
1084 union mac_stats mac_stats;
1085 struct nig_stats nig_stats;
1086 struct host_port_stats port_stats;
1087 struct host_func_stats func_stats;
1092 union drv_info_to_mcp drv_info_to_mcp;
1095 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
1096 #define bnx2x_sp_mapping(bp, var) \
1097 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
1100 /* attn group wiring */
1101 #define MAX_DYNAMIC_ATTN_GRPS 8
1116 union cdu_context *vcxt;
1117 dma_addr_t cxt_mapping;
1126 enum bnx2x_recovery_state {
1127 BNX2X_RECOVERY_DONE,
1128 BNX2X_RECOVERY_INIT,
1129 BNX2X_RECOVERY_WAIT,
1130 BNX2X_RECOVERY_FAILED,
1131 BNX2X_RECOVERY_NIC_LOADING
1135 * Event queue (EQ or event ring) MC hsi
1136 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
1138 #define NUM_EQ_PAGES 1
1139 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1140 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1141 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1142 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1143 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1145 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1146 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
1147 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
1149 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1150 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1152 #define BNX2X_EQ_INDEX \
1153 (&bp->def_status_blk->sp_sb.\
1154 index_values[HC_SP_INDEX_EQ_CONS])
1156 /* This is a data that will be used to create a link report message.
1157 * We will keep the data used for the last link report in order
1158 * to prevent reporting the same link parameters twice.
1160 struct bnx2x_link_report_data {
1161 u16 line_speed; /* Effective line speed */
1162 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */
1166 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */
1167 BNX2X_LINK_REPORT_LINK_DOWN,
1168 BNX2X_LINK_REPORT_RX_FC_ON,
1169 BNX2X_LINK_REPORT_TX_FC_ON,
1173 BNX2X_PORT_QUERY_IDX,
1175 BNX2X_FCOE_QUERY_IDX,
1176 BNX2X_FIRST_QUEUE_QUERY_IDX,
1179 struct bnx2x_fw_stats_req {
1180 struct stats_query_header hdr;
1181 struct stats_query_entry query[FP_SB_MAX_E1x+
1182 BNX2X_FIRST_QUEUE_QUERY_IDX];
1185 struct bnx2x_fw_stats_data {
1186 struct stats_counter storm_counters;
1187 struct per_port_stats port;
1188 struct per_pf_stats pf;
1189 struct fcoe_statistics_params fcoe;
1190 struct per_queue_stats queue_stats[1];
1193 /* Public slow path states */
1195 BNX2X_SP_RTNL_SETUP_TC,
1196 BNX2X_SP_RTNL_TX_TIMEOUT,
1197 BNX2X_SP_RTNL_AFEX_F_UPDATE,
1198 BNX2X_SP_RTNL_FAN_FAILURE,
1199 BNX2X_SP_RTNL_VFPF_MCAST,
1200 BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
1204 struct bnx2x_prev_path_list {
1208 struct list_head list;
1212 struct bnx2x_sp_objs {
1214 struct bnx2x_vlan_mac_obj mac_obj;
1216 /* Queue State object */
1217 struct bnx2x_queue_sp_obj q_obj;
1220 struct bnx2x_fp_stats {
1221 struct tstorm_per_queue_stats old_tclient;
1222 struct ustorm_per_queue_stats old_uclient;
1223 struct xstorm_per_queue_stats old_xclient;
1224 struct bnx2x_eth_q_stats eth_q_stats;
1225 struct bnx2x_eth_q_stats_old eth_q_stats_old;
1229 /* Fields used in the tx and intr/napi performance paths
1230 * are grouped together in the beginning of the structure
1232 struct bnx2x_fastpath *fp;
1233 struct bnx2x_sp_objs *sp_objs;
1234 struct bnx2x_fp_stats *fp_stats;
1235 struct bnx2x_fp_txdata *bnx2x_txq;
1236 void __iomem *regview;
1237 void __iomem *doorbells;
1240 u8 pf_num; /* absolute PF number */
1241 u8 pfid; /* per-path PF number */
1242 int base_fw_ndsb; /**/
1243 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
1244 #define BP_PORT(bp) (bp->pfid & 1)
1245 #define BP_FUNC(bp) (bp->pfid)
1246 #define BP_ABS_FUNC(bp) (bp->pf_num)
1247 #define BP_VN(bp) ((bp)->pfid >> 1)
1248 #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4)
1249 #define BP_L_ID(bp) (BP_VN(bp) << 2)
1250 #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\
1251 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1))
1252 #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp))
1254 /* vf pf channel mailbox contains request and response buffers */
1255 struct bnx2x_vf_mbx_msg *vf2pf_mbox;
1256 dma_addr_t vf2pf_mbox_mapping;
1258 /* we set aside a copy of the acquire response */
1259 struct pfvf_acquire_resp_tlv acquire_resp;
1261 struct net_device *dev;
1262 struct pci_dev *pdev;
1264 const struct iro *iro_arr;
1265 #define IRO (bp->iro_arr)
1267 enum bnx2x_recovery_state recovery_state;
1269 struct msix_entry *msix_table;
1273 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1274 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
1275 #define ETH_MIN_PACKET_SIZE 60
1276 #define ETH_MAX_PACKET_SIZE 1500
1277 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
1278 /* TCP with Timestamp Option (32) + IPv6 (40) */
1279 #define ETH_MAX_TPA_HEADER_SIZE 72
1281 /* Max supported alignment is 256 (8 shift) */
1282 #define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT)
1284 /* FW uses 2 Cache lines Alignment for start packet and size
1286 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes
1287 * at the end of skb->data, to avoid wasting a full cache line.
1288 * This reduces memory use (skb->truesize).
1290 #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT)
1292 #define BNX2X_FW_RX_ALIGN_END \
1293 max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \
1294 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
1296 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
1298 struct host_sp_status_block *def_status_blk;
1299 #define DEF_SB_IGU_ID 16
1300 #define DEF_SB_ID HC_SP_SB_ID
1304 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1306 /* slow path ring */
1307 struct eth_spe *spq;
1308 dma_addr_t spq_mapping;
1310 struct eth_spe *spq_prod_bd;
1311 struct eth_spe *spq_last_bd;
1312 __le16 *dsb_sp_prod;
1313 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */
1314 /* used to synchronize spq accesses */
1315 spinlock_t spq_lock;
1318 union event_ring_elem *eq_ring;
1319 dma_addr_t eq_mapping;
1323 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */
1327 /* Counter for marking that there is a STAT_QUERY ramrod pending */
1329 /* Counter for completed statistics ramrods */
1332 /* End of fields used in the performance code paths */
1338 #define PCIX_FLAG (1 << 0)
1339 #define PCI_32BIT_FLAG (1 << 1)
1340 #define ONE_PORT_FLAG (1 << 2)
1341 #define NO_WOL_FLAG (1 << 3)
1342 #define USING_DAC_FLAG (1 << 4)
1343 #define USING_MSIX_FLAG (1 << 5)
1344 #define USING_MSI_FLAG (1 << 6)
1345 #define DISABLE_MSI_FLAG (1 << 7)
1346 #define TPA_ENABLE_FLAG (1 << 8)
1347 #define NO_MCP_FLAG (1 << 9)
1348 #define GRO_ENABLE_FLAG (1 << 10)
1349 #define MF_FUNC_DIS (1 << 11)
1350 #define OWN_CNIC_IRQ (1 << 12)
1351 #define NO_ISCSI_OOO_FLAG (1 << 13)
1352 #define NO_ISCSI_FLAG (1 << 14)
1353 #define NO_FCOE_FLAG (1 << 15)
1354 #define BC_SUPPORTS_PFC_STATS (1 << 17)
1355 #define BC_SUPPORTS_FCOE_FEATURES (1 << 19)
1356 #define USING_SINGLE_MSIX_FLAG (1 << 20)
1357 #define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21)
1358 #define IS_VF_FLAG (1 << 22)
1360 #define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG)
1361 #define IS_VF(bp) ((bp)->flags & IS_VF_FLAG)
1362 #define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG))
1364 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
1365 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
1366 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
1371 struct cnic_eth_dev *(*cnic_probe)(struct net_device *);
1373 /* Flag that indicates that we can start looking for FCoE L2 queue
1374 * completions in the default status block.
1381 struct delayed_work sp_task;
1382 struct delayed_work sp_rtnl_task;
1384 struct delayed_work period_task;
1385 struct timer_list timer;
1386 int current_interval;
1389 u16 fw_drv_pulse_wr_seq;
1392 struct link_params link_params;
1393 struct link_vars link_vars;
1395 struct bnx2x_link_report_data last_reported_link;
1397 struct mdio_if_info mdio;
1399 struct bnx2x_common common;
1400 struct bnx2x_port port;
1402 struct cmng_init cmng;
1404 u32 mf_config[E1HVN_MAX];
1406 u32 path_has_ovlan; /* E3 */
1409 #define IS_MF(bp) (bp->mf_mode != 0)
1410 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI)
1411 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD)
1412 #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX)
1418 u16 tx_quick_cons_trip_int;
1419 u16 tx_quick_cons_trip;
1423 u16 rx_quick_cons_trip_int;
1424 u16 rx_quick_cons_trip;
1427 /* Maximal coalescing timeout in us */
1428 #define BNX2X_MAX_COALESCE_TOUT (0xf0*12)
1433 #define BNX2X_STATE_CLOSED 0
1434 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
1435 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
1436 #define BNX2X_STATE_OPEN 0x3000
1437 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
1438 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1440 #define BNX2X_STATE_DIAG 0xe000
1441 #define BNX2X_STATE_ERROR 0xf000
1443 #define BNX2X_MAX_PRIORITY 8
1444 #define BNX2X_MAX_ENTRIES_PER_PRI 16
1445 #define BNX2X_MAX_COS 3
1446 #define BNX2X_MAX_TX_COS 2
1448 uint num_ethernet_queues;
1449 uint num_cnic_queues;
1450 int num_napi_queues;
1454 #define BNX2X_RX_MODE_NONE 0
1455 #define BNX2X_RX_MODE_NORMAL 1
1456 #define BNX2X_RX_MODE_ALLMULTI 2
1457 #define BNX2X_RX_MODE_PROMISC 3
1458 #define BNX2X_MAX_MULTICAST 64
1463 u8 min_msix_vec_cnt;
1466 dma_addr_t def_status_blk_mapping;
1468 struct bnx2x_slowpath *slowpath;
1469 dma_addr_t slowpath_mapping;
1471 /* Total number of FW statistics requests */
1475 * This is a memory buffer that will contain both statistics
1476 * ramrod request and data.
1479 dma_addr_t fw_stats_mapping;
1482 * FW statistics request shortcut (points at the
1483 * beginning of fw_stats buffer).
1485 struct bnx2x_fw_stats_req *fw_stats_req;
1486 dma_addr_t fw_stats_req_mapping;
1487 int fw_stats_req_sz;
1490 * FW statistics data shortcut (points at the beginning of
1491 * fw_stats buffer + fw_stats_req_sz).
1493 struct bnx2x_fw_stats_data *fw_stats_data;
1494 dma_addr_t fw_stats_data_mapping;
1495 int fw_stats_data_sz;
1497 /* For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB
1498 * context size we need 8 ILT entries.
1500 #define ILT_MAX_L2_LINES 8
1501 struct hw_context context[ILT_MAX_L2_LINES];
1503 struct bnx2x_ilt *ilt;
1504 #define BP_ILT(bp) ((bp)->ilt)
1505 #define ILT_MAX_LINES 256
1507 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes
1510 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp))
1513 * Maximum CID count that might be required by the bnx2x:
1514 * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI
1516 #define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \
1517 + 2 * CNIC_SUPPORT(bp))
1518 #define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \
1519 + 2 * CNIC_SUPPORT(bp))
1520 #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\
1528 dma_addr_t t2_mapping;
1529 struct cnic_ops __rcu *cnic_ops;
1532 struct cnic_eth_dev cnic_eth_dev;
1533 union host_hc_status_block cnic_sb;
1534 dma_addr_t cnic_sb_mapping;
1535 struct eth_spe *cnic_kwq;
1536 struct eth_spe *cnic_kwq_prod;
1537 struct eth_spe *cnic_kwq_cons;
1538 struct eth_spe *cnic_kwq_last;
1539 u16 cnic_kwq_pending;
1540 u16 cnic_spq_pending;
1541 u8 fip_mac[ETH_ALEN];
1542 struct mutex cnic_mutex;
1543 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj;
1545 /* Start index of the "special" (CNIC related) L2 cleints */
1549 /* used to synchronize dmae accesses */
1550 spinlock_t dmae_lock;
1552 /* used to protect the FW mail box */
1553 struct mutex fw_mb_mutex;
1555 /* used to synchronize stats collecting */
1558 /* used for synchronization of concurrent threads statistics handling */
1559 spinlock_t stats_lock;
1561 /* used by dmae command loader */
1562 struct dmae_command stats_dmae;
1566 struct bnx2x_eth_stats eth_stats;
1567 struct host_func_stats func_stats;
1568 struct bnx2x_eth_stats_old eth_stats_old;
1569 struct bnx2x_net_stats_old net_stats_old;
1570 struct bnx2x_fw_port_stats_old fw_stats_old;
1573 struct z_stream_s *strm;
1575 dma_addr_t gunzip_mapping;
1577 #define FW_BUF_SIZE 0x8000
1578 #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1579 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1580 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1582 struct raw_op *init_ops;
1583 /* Init blocks offsets inside init_ops */
1584 u16 *init_ops_offsets;
1585 /* Data blob - has 32 bit granularity */
1587 u32 init_mode_flags;
1588 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags)
1589 /* Zipped PRAM blobs - raw data */
1590 const u8 *tsem_int_table_data;
1591 const u8 *tsem_pram_data;
1592 const u8 *usem_int_table_data;
1593 const u8 *usem_pram_data;
1594 const u8 *xsem_int_table_data;
1595 const u8 *xsem_pram_data;
1596 const u8 *csem_int_table_data;
1597 const u8 *csem_pram_data;
1598 #define INIT_OPS(bp) (bp->init_ops)
1599 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1600 #define INIT_DATA(bp) (bp->init_data)
1601 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1602 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1603 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1604 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1605 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1606 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1607 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1608 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1610 #define PHY_FW_VER_LEN 20
1612 const struct firmware *firmware;
1614 struct bnx2x_vfdb *vfdb;
1615 #define IS_SRIOV(bp) ((bp)->vfdb)
1617 /* DCB support on/off */
1619 #define BNX2X_DCB_STATE_OFF 0
1620 #define BNX2X_DCB_STATE_ON 1
1622 /* DCBX engine mode */
1624 #define BNX2X_DCBX_ENABLED_OFF 0
1625 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1626 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1627 #define BNX2X_DCBX_ENABLED_INVALID (-1)
1629 bool dcbx_mode_uset;
1631 struct bnx2x_config_dcbx_params dcbx_config_params;
1632 struct bnx2x_dcbx_port_params dcbx_port_params;
1635 /* CAM credit pools */
1637 /* used only in sriov */
1638 struct bnx2x_credit_pool_obj vlans_pool;
1640 struct bnx2x_credit_pool_obj macs_pool;
1642 /* RX_MODE object */
1643 struct bnx2x_rx_mode_obj rx_mode_obj;
1646 struct bnx2x_mcast_obj mcast_obj;
1648 /* RSS configuration object */
1649 struct bnx2x_rss_config_obj rss_conf_obj;
1651 /* Function State controlling object */
1652 struct bnx2x_func_sp_obj func_obj;
1654 unsigned long sp_state;
1656 /* operation indication for the sp_rtnl task */
1657 unsigned long sp_rtnl_state;
1659 /* DCBX Negotation results */
1660 struct dcbx_features dcbx_local_feat;
1664 struct dcbx_features dcbx_remote_feat;
1665 u32 dcbx_remote_flags;
1667 /* AFEX: store default vlan used */
1668 int afex_def_vlan_tag;
1669 enum mf_cfg_afex_vlan_mode afex_vlan_mode;
1672 /* multiple tx classes of service */
1675 /* priority to cos mapping */
1679 /* Tx queues may be less or equal to Rx queues */
1680 extern int num_queues;
1681 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1682 #define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues)
1683 #define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \
1684 (bp)->num_cnic_queues)
1685 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp)
1687 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1689 #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp)
1690 /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */
1692 #define RSS_IPV4_CAP_MASK \
1693 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1695 #define RSS_IPV4_TCP_CAP_MASK \
1696 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1698 #define RSS_IPV6_CAP_MASK \
1699 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1701 #define RSS_IPV6_TCP_CAP_MASK \
1702 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1704 /* func init flags */
1705 #define FUNC_FLG_RSS 0x0001
1706 #define FUNC_FLG_STATS 0x0002
1707 /* removed FUNC_FLG_UNMATCHED 0x0004 */
1708 #define FUNC_FLG_TPA 0x0008
1709 #define FUNC_FLG_SPQ 0x0010
1710 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1713 struct bnx2x_func_init_params {
1715 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */
1716 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */
1719 u16 func_id; /* abs fid */
1721 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */
1724 #define for_each_cnic_queue(bp, var) \
1725 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1727 if (skip_queue(bp, var)) \
1731 #define for_each_eth_queue(bp, var) \
1732 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1734 #define for_each_nondefault_eth_queue(bp, var) \
1735 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1737 #define for_each_queue(bp, var) \
1738 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1739 if (skip_queue(bp, var)) \
1743 /* Skip forwarding FP */
1744 #define for_each_valid_rx_queue(bp, var) \
1746 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
1747 BNX2X_NUM_ETH_QUEUES(bp)); \
1749 if (skip_rx_queue(bp, var)) \
1753 #define for_each_rx_queue_cnic(bp, var) \
1754 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1756 if (skip_rx_queue(bp, var)) \
1760 #define for_each_rx_queue(bp, var) \
1761 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1762 if (skip_rx_queue(bp, var)) \
1767 #define for_each_valid_tx_queue(bp, var) \
1769 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
1770 BNX2X_NUM_ETH_QUEUES(bp)); \
1772 if (skip_tx_queue(bp, var)) \
1776 #define for_each_tx_queue_cnic(bp, var) \
1777 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1779 if (skip_tx_queue(bp, var)) \
1783 #define for_each_tx_queue(bp, var) \
1784 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1785 if (skip_tx_queue(bp, var)) \
1789 #define for_each_nondefault_queue(bp, var) \
1790 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1791 if (skip_queue(bp, var)) \
1795 #define for_each_cos_in_tx_queue(fp, var) \
1796 for ((var) = 0; (var) < (fp)->max_cos; (var)++)
1799 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1801 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1804 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1806 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1808 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1814 * bnx2x_set_mac_one - configure a single MAC address
1816 * @bp: driver handle
1817 * @mac: MAC to configure
1818 * @obj: MAC object handle
1819 * @set: if 'true' add a new MAC, otherwise - delete
1820 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list)
1821 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT)
1823 * Configures one MAC according to provided parameters or continues the
1824 * execution of previously scheduled commands if RAMROD_CONT is set in
1827 * Returns zero if operation has successfully completed, a positive value if the
1828 * operation has been successfully scheduled and a negative - if a requested
1829 * operations has failed.
1831 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
1832 struct bnx2x_vlan_mac_obj *obj, bool set,
1833 int mac_type, unsigned long *ramrod_flags);
1835 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object
1837 * @bp: driver handle
1838 * @mac_obj: MAC object handle
1839 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC)
1840 * @wait_for_comp: if 'true' block until completion
1842 * Deletes all MACs of the specific type (e.g. ETH, UC list).
1844 * Returns zero if operation has successfully completed, a positive value if the
1845 * operation has been successfully scheduled and a negative - if a requested
1846 * operations has failed.
1848 int bnx2x_del_all_macs(struct bnx2x *bp,
1849 struct bnx2x_vlan_mac_obj *mac_obj,
1850 int mac_type, bool wait_for_comp);
1852 /* Init Function API */
1853 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
1854 u32 bnx2x_get_pretend_reg(struct bnx2x *bp);
1855 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1856 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1857 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
1858 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1859 void bnx2x_read_mf_cfg(struct bnx2x *bp);
1861 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val);
1864 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1865 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1867 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
1868 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
1869 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
1870 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
1871 bool with_comp, u8 comp_type);
1873 u8 bnx2x_is_pcie_pending(struct pci_dev *dev);
1875 void bnx2x_calc_fc_adv(struct bnx2x *bp);
1876 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
1877 u32 data_hi, u32 data_lo, int cmd_type);
1878 void bnx2x_update_coalesce(struct bnx2x *bp);
1879 int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
1881 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1887 val = REG_RD(bp, reg);
1888 if (val == expected)
1898 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id,
1901 #define BNX2X_ILT_ZALLOC(x, y, size) \
1903 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
1905 memset(x, 0, size); \
1908 #define BNX2X_ILT_FREE(x, y, size) \
1911 dma_free_coherent(&bp->pdev->dev, size, x, y); \
1917 #define ILOG2(x) (ilog2((x)))
1919 #define ILT_NUM_PAGE_ENTRIES (3072)
1920 /* In 57710/11 we use whole table since we have 8 func
1921 * In 57712 we have only 4 func, but use same size per func, then only half of
1924 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
1926 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
1928 * the phys address is shifted right 12 bits and has an added
1929 * 1=valid bit added to the 53rd bit
1930 * then since this is a wide register(TM)
1931 * we split it into two 32 bit writes
1933 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
1934 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
1936 /* load/unload mode */
1937 #define LOAD_NORMAL 0
1940 #define LOAD_LOOPBACK_EXT 3
1941 #define UNLOAD_NORMAL 0
1942 #define UNLOAD_CLOSE 1
1943 #define UNLOAD_RECOVERY 2
1946 /* DMAE command defines */
1947 #define DMAE_TIMEOUT -1
1948 #define DMAE_PCI_ERROR -2 /* E2 and onward */
1949 #define DMAE_NOT_RDY -3
1950 #define DMAE_PCI_ERR_FLAG 0x80000000
1952 #define DMAE_SRC_PCI 0
1953 #define DMAE_SRC_GRC 1
1955 #define DMAE_DST_NONE 0
1956 #define DMAE_DST_PCI 1
1957 #define DMAE_DST_GRC 2
1959 #define DMAE_COMP_PCI 0
1960 #define DMAE_COMP_GRC 1
1962 /* E2 and onward - PCI error handling in the completion */
1964 #define DMAE_COMP_REGULAR 0
1965 #define DMAE_COM_SET_ERR 1
1967 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \
1968 DMAE_COMMAND_SRC_SHIFT)
1969 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \
1970 DMAE_COMMAND_SRC_SHIFT)
1972 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \
1973 DMAE_COMMAND_DST_SHIFT)
1974 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \
1975 DMAE_COMMAND_DST_SHIFT)
1977 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \
1978 DMAE_COMMAND_C_DST_SHIFT)
1979 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \
1980 DMAE_COMMAND_C_DST_SHIFT)
1982 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1984 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1985 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1986 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1987 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1989 #define DMAE_CMD_PORT_0 0
1990 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1992 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1993 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1994 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1996 #define DMAE_SRC_PF 0
1997 #define DMAE_SRC_VF 1
1999 #define DMAE_DST_PF 0
2000 #define DMAE_DST_VF 1
2002 #define DMAE_C_SRC 0
2003 #define DMAE_C_DST 1
2005 #define DMAE_LEN32_RD_MAX 0x80
2006 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
2008 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
2011 #define MAX_DMAE_C_PER_PORT 8
2012 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
2014 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
2017 /* PCIE link and speed */
2018 #define PCICFG_LINK_WIDTH 0x1f00000
2019 #define PCICFG_LINK_WIDTH_SHIFT 20
2020 #define PCICFG_LINK_SPEED 0xf0000
2021 #define PCICFG_LINK_SPEED_SHIFT 16
2023 #define BNX2X_NUM_TESTS_SF 7
2024 #define BNX2X_NUM_TESTS_MF 3
2025 #define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \
2028 #define BNX2X_PHY_LOOPBACK 0
2029 #define BNX2X_MAC_LOOPBACK 1
2030 #define BNX2X_EXT_LOOPBACK 2
2031 #define BNX2X_PHY_LOOPBACK_FAILED 1
2032 #define BNX2X_MAC_LOOPBACK_FAILED 2
2033 #define BNX2X_EXT_LOOPBACK_FAILED 3
2034 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
2035 BNX2X_PHY_LOOPBACK_FAILED)
2038 #define STROM_ASSERT_ARRAY_SIZE 50
2041 /* must be used on a CID before placing it on a HW ring */
2042 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
2043 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \
2046 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
2047 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
2051 #define MAX_SPQ_PENDING 8
2053 /* CMNG constants, as derived from system spec calculations */
2054 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
2055 #define DEF_MIN_RATE 100
2056 /* resolution of the rate shaping timer - 400 usec */
2057 #define RS_PERIODIC_TIMEOUT_USEC 400
2058 /* number of bytes in single QM arbitration cycle -
2059 * coefficient for calculating the fairness timer */
2060 #define QM_ARB_BYTES 160000
2061 /* resolution of Min algorithm 1:100 */
2063 /* how many bytes above threshold for the minimal credit of Min algorithm*/
2064 #define MIN_ABOVE_THRESH 32768
2065 /* Fairness algorithm integration time coefficient -
2066 * for calculating the actual Tfair */
2067 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
2068 /* Memory of fairness algorithm . 2 cycles */
2072 #define ATTN_NIG_FOR_FUNC (1L << 8)
2073 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
2074 #define GPIO_2_FUNC (1L << 10)
2075 #define GPIO_3_FUNC (1L << 11)
2076 #define GPIO_4_FUNC (1L << 12)
2077 #define ATTN_GENERAL_ATTN_1 (1L << 13)
2078 #define ATTN_GENERAL_ATTN_2 (1L << 14)
2079 #define ATTN_GENERAL_ATTN_3 (1L << 15)
2080 #define ATTN_GENERAL_ATTN_4 (1L << 13)
2081 #define ATTN_GENERAL_ATTN_5 (1L << 14)
2082 #define ATTN_GENERAL_ATTN_6 (1L << 15)
2084 #define ATTN_HARD_WIRED_MASK 0xff00
2085 #define ATTENTION_ID 4
2088 /* stuff added to make the code fit 80Col */
2090 #define BNX2X_PMF_LINK_ASSERT \
2091 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
2093 #define BNX2X_MC_ASSERT_BITS \
2094 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2095 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2096 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2097 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
2099 #define BNX2X_MCP_ASSERT \
2100 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
2102 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
2103 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
2104 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
2105 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
2106 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
2107 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
2108 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
2110 #define HW_INTERRUT_ASSERT_SET_0 \
2111 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
2112 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
2113 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
2114 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
2115 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
2116 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
2117 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
2118 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
2119 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
2120 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
2121 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
2122 #define HW_INTERRUT_ASSERT_SET_1 \
2123 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
2124 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
2125 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
2126 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
2127 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
2128 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
2129 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
2130 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
2131 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
2132 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
2133 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
2134 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
2135 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
2136 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
2137 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
2138 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
2139 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
2140 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
2141 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
2142 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
2143 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
2144 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
2145 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
2146 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
2147 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
2148 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
2149 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
2150 #define HW_INTERRUT_ASSERT_SET_2 \
2151 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
2152 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
2153 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
2154 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
2155 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
2156 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
2157 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
2158 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
2159 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
2160 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
2161 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
2162 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
2163 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
2165 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
2166 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
2167 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
2168 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
2170 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
2171 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
2173 #define MULTI_MASK 0x7f
2176 #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func)
2177 #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func)
2178 #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func)
2179 #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func)
2181 #define DEF_USB_IGU_INDEX_OFF \
2182 offsetof(struct cstorm_def_status_block_u, igu_index)
2183 #define DEF_CSB_IGU_INDEX_OFF \
2184 offsetof(struct cstorm_def_status_block_c, igu_index)
2185 #define DEF_XSB_IGU_INDEX_OFF \
2186 offsetof(struct xstorm_def_status_block, igu_index)
2187 #define DEF_TSB_IGU_INDEX_OFF \
2188 offsetof(struct tstorm_def_status_block, igu_index)
2190 #define DEF_USB_SEGMENT_OFF \
2191 offsetof(struct cstorm_def_status_block_u, segment)
2192 #define DEF_CSB_SEGMENT_OFF \
2193 offsetof(struct cstorm_def_status_block_c, segment)
2194 #define DEF_XSB_SEGMENT_OFF \
2195 offsetof(struct xstorm_def_status_block, segment)
2196 #define DEF_TSB_SEGMENT_OFF \
2197 offsetof(struct tstorm_def_status_block, segment)
2199 #define BNX2X_SP_DSB_INDEX \
2200 (&bp->def_status_blk->sp_sb.\
2201 index_values[HC_SP_INDEX_ETH_DEF_CONS])
2203 #define SET_FLAG(value, mask, flag) \
2205 (value) &= ~(mask);\
2206 (value) |= ((flag) << (mask##_SHIFT));\
2209 #define GET_FLAG(value, mask) \
2210 (((value) & (mask)) >> (mask##_SHIFT))
2212 #define GET_FIELD(value, fname) \
2213 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
2215 #define CAM_IS_INVALID(x) \
2216 (GET_FLAG(x.flags, \
2217 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
2218 (T_ETH_MAC_COMMAND_INVALIDATE))
2220 /* Number of u32 elements in MC hash array */
2221 #define MC_HASH_SIZE 8
2222 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
2223 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
2226 #ifndef PXP2_REG_PXP2_INT_STS
2227 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
2230 #ifndef ETH_MAX_RX_CLIENTS_E2
2231 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
2234 #define BNX2X_VPD_LEN 128
2235 #define VENDOR_ID_LEN 4
2237 #define VF_ACQUIRE_THRESH 3
2238 #define VF_ACQUIRE_MAC_FILTERS 1
2239 #define VF_ACQUIRE_MC_FILTERS 10
2241 #define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \
2242 (!((me_reg) & ME_REG_VF_ERR)))
2243 int bnx2x_get_vf_id(struct bnx2x *bp, u32 *vf_id);
2244 int bnx2x_send_msg2pf(struct bnx2x *bp, u8 *done, dma_addr_t msg_mapping);
2245 int bnx2x_vfpf_acquire(struct bnx2x *bp, u8 tx_count, u8 rx_count);
2246 int bnx2x_vfpf_release(struct bnx2x *bp);
2247 int bnx2x_vfpf_init(struct bnx2x *bp);
2248 void bnx2x_vfpf_close_vf(struct bnx2x *bp);
2249 int bnx2x_vfpf_setup_q(struct bnx2x *bp, int fp_idx);
2250 int bnx2x_vfpf_teardown_queue(struct bnx2x *bp, int qidx);
2251 int bnx2x_vfpf_set_mac(struct bnx2x *bp);
2252 int bnx2x_vfpf_set_mcast(struct net_device *dev);
2253 int bnx2x_vfpf_storm_rx_mode(struct bnx2x *bp);
2255 int bnx2x_nic_load_analyze_req(struct bnx2x *bp, u32 load_code);
2256 /* Congestion management fairness mode */
2257 #define CMNG_FNS_NONE 0
2258 #define CMNG_FNS_MINMAX 1
2260 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
2261 #define HC_SEG_ACCESS_ATTN 4
2262 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
2264 static const u32 dmae_reg_go_c[] = {
2265 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
2266 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
2267 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
2268 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
2271 void bnx2x_set_ethtool_ops(struct net_device *netdev);
2272 void bnx2x_notify_link_changed(struct bnx2x *bp);
2275 #define BNX2X_MF_SD_PROTOCOL(bp) \
2276 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK)
2278 #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \
2279 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI)
2281 #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \
2282 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE)
2284 #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp))
2285 #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))
2287 #define BNX2X_MF_EXT_PROTOCOL_FCOE(bp) ((bp)->mf_ext_config & \
2288 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2290 #define IS_MF_FCOE_AFEX(bp) (IS_MF_AFEX(bp) && BNX2X_MF_EXT_PROTOCOL_FCOE(bp))
2291 #define IS_MF_STORAGE_SD(bp) (IS_MF_SD(bp) && \
2292 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \
2293 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
2302 #endif /* bnx2x.h */