1 /* Altera TSE SGDMA and MSGDMA Linux driver
2 * Copyright (C) 2014 Altera Corporation. All rights reserved
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/list.h>
18 #include "altera_utils.h"
19 #include "altera_tse.h"
20 #include "altera_sgdmahw.h"
21 #include "altera_sgdma.h"
23 static void sgdma_setup_descrip(struct sgdma_descrip *desc,
24 struct sgdma_descrip *ndesc,
25 dma_addr_t ndesc_phys,
33 static int sgdma_async_write(struct altera_tse_private *priv,
34 struct sgdma_descrip *desc);
36 static int sgdma_async_read(struct altera_tse_private *priv);
39 sgdma_txphysaddr(struct altera_tse_private *priv,
40 struct sgdma_descrip *desc);
43 sgdma_rxphysaddr(struct altera_tse_private *priv,
44 struct sgdma_descrip *desc);
46 static int sgdma_txbusy(struct altera_tse_private *priv);
48 static int sgdma_rxbusy(struct altera_tse_private *priv);
51 queue_tx(struct altera_tse_private *priv, struct tse_buffer *buffer);
54 queue_rx(struct altera_tse_private *priv, struct tse_buffer *buffer);
56 static struct tse_buffer *
57 dequeue_tx(struct altera_tse_private *priv);
59 static struct tse_buffer *
60 dequeue_rx(struct altera_tse_private *priv);
62 static struct tse_buffer *
63 queue_rx_peekhead(struct altera_tse_private *priv);
65 int sgdma_initialize(struct altera_tse_private *priv)
67 priv->txctrlreg = SGDMA_CTRLREG_ILASTD |
70 priv->rxctrlreg = SGDMA_CTRLREG_IDESCRIP |
74 priv->sgdmadesclen = sizeof(struct sgdma_descrip);
76 INIT_LIST_HEAD(&priv->txlisthd);
77 INIT_LIST_HEAD(&priv->rxlisthd);
79 priv->rxdescphys = (dma_addr_t) 0;
80 priv->txdescphys = (dma_addr_t) 0;
82 priv->rxdescphys = dma_map_single(priv->device, priv->rx_dma_desc,
83 priv->rxdescmem, DMA_BIDIRECTIONAL);
85 if (dma_mapping_error(priv->device, priv->rxdescphys)) {
86 sgdma_uninitialize(priv);
87 netdev_err(priv->dev, "error mapping rx descriptor memory\n");
91 priv->txdescphys = dma_map_single(priv->device, priv->tx_dma_desc,
92 priv->txdescmem, DMA_TO_DEVICE);
94 if (dma_mapping_error(priv->device, priv->txdescphys)) {
95 sgdma_uninitialize(priv);
96 netdev_err(priv->dev, "error mapping tx descriptor memory\n");
100 /* Initialize descriptor memory to all 0's, sync memory to cache */
101 memset(priv->tx_dma_desc, 0, priv->txdescmem);
102 memset(priv->rx_dma_desc, 0, priv->rxdescmem);
104 dma_sync_single_for_device(priv->device, priv->txdescphys,
105 priv->txdescmem, DMA_TO_DEVICE);
107 dma_sync_single_for_device(priv->device, priv->rxdescphys,
108 priv->rxdescmem, DMA_TO_DEVICE);
113 void sgdma_uninitialize(struct altera_tse_private *priv)
115 if (priv->rxdescphys)
116 dma_unmap_single(priv->device, priv->rxdescphys,
117 priv->rxdescmem, DMA_BIDIRECTIONAL);
119 if (priv->txdescphys)
120 dma_unmap_single(priv->device, priv->txdescphys,
121 priv->txdescmem, DMA_TO_DEVICE);
124 /* This function resets the SGDMA controller and clears the
125 * descriptor memory used for transmits and receives.
127 void sgdma_reset(struct altera_tse_private *priv)
129 u32 *ptxdescripmem = priv->tx_dma_desc;
130 u32 txdescriplen = priv->txdescmem;
131 u32 *prxdescripmem = priv->rx_dma_desc;
132 u32 rxdescriplen = priv->rxdescmem;
133 struct sgdma_csr *ptxsgdma = priv->tx_dma_csr;
134 struct sgdma_csr *prxsgdma = priv->rx_dma_csr;
136 /* Initialize descriptor memory to 0 */
137 memset(ptxdescripmem, 0, txdescriplen);
138 memset(prxdescripmem, 0, rxdescriplen);
140 iowrite32(SGDMA_CTRLREG_RESET, &ptxsgdma->control);
141 iowrite32(0, &ptxsgdma->control);
143 iowrite32(SGDMA_CTRLREG_RESET, &prxsgdma->control);
144 iowrite32(0, &prxsgdma->control);
147 /* For SGDMA, interrupts remain enabled after initially enabling,
148 * so no need to provide implementations for abstract enable
152 void sgdma_enable_rxirq(struct altera_tse_private *priv)
156 void sgdma_enable_txirq(struct altera_tse_private *priv)
160 void sgdma_disable_rxirq(struct altera_tse_private *priv)
164 void sgdma_disable_txirq(struct altera_tse_private *priv)
168 void sgdma_clear_rxirq(struct altera_tse_private *priv)
170 struct sgdma_csr *csr = priv->rx_dma_csr;
171 tse_set_bit(&csr->control, SGDMA_CTRLREG_CLRINT);
174 void sgdma_clear_txirq(struct altera_tse_private *priv)
176 struct sgdma_csr *csr = priv->tx_dma_csr;
177 tse_set_bit(&csr->control, SGDMA_CTRLREG_CLRINT);
180 /* transmits buffer through SGDMA. Returns number of buffers
181 * transmitted, 0 if not possible.
183 * tx_lock is held by the caller
185 int sgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *buffer)
188 struct sgdma_descrip *descbase = priv->tx_dma_desc;
190 struct sgdma_descrip *cdesc = &descbase[0];
191 struct sgdma_descrip *ndesc = &descbase[1];
193 /* wait 'til the tx sgdma is ready for the next transmit request */
194 if (sgdma_txbusy(priv))
197 sgdma_setup_descrip(cdesc, /* current descriptor */
198 ndesc, /* next descriptor */
199 sgdma_txphysaddr(priv, ndesc),
200 buffer->dma_addr, /* address of packet to xmit */
201 0, /* write addr 0 for tx dma */
202 buffer->len, /* length of packet */
203 SGDMA_CONTROL_EOP, /* Generate EOP */
205 SGDMA_CONTROL_WR_FIXED); /* Generate SOP */
207 pktstx = sgdma_async_write(priv, cdesc);
209 /* enqueue the request to the pending transmit queue */
210 queue_tx(priv, buffer);
216 /* tx_lock held to protect access to queued tx list
218 u32 sgdma_tx_completions(struct altera_tse_private *priv)
221 struct sgdma_descrip *desc = priv->tx_dma_desc;
223 if (!sgdma_txbusy(priv) &&
224 ((desc->control & SGDMA_CONTROL_HW_OWNED) == 0) &&
225 (dequeue_tx(priv))) {
232 void sgdma_start_rxdma(struct altera_tse_private *priv)
234 sgdma_async_read(priv);
237 void sgdma_add_rx_desc(struct altera_tse_private *priv,
238 struct tse_buffer *rxbuffer)
240 queue_rx(priv, rxbuffer);
243 /* status is returned on upper 16 bits,
244 * length is returned in lower 16 bits
246 u32 sgdma_rx_status(struct altera_tse_private *priv)
248 struct sgdma_csr *csr = priv->rx_dma_csr;
249 struct sgdma_descrip *base = priv->rx_dma_desc;
250 struct sgdma_descrip *desc = NULL;
252 unsigned int rxstatus = 0;
253 unsigned int pktlength = 0;
254 unsigned int pktstatus = 0;
255 struct tse_buffer *rxbuffer = NULL;
257 u32 sts = ioread32(&csr->status);
260 if (sts & SGDMA_STSREG_EOP) {
261 dma_sync_single_for_cpu(priv->device,
266 pktlength = desc->bytes_xferred;
267 pktstatus = desc->status & 0x3f;
268 rxstatus = pktstatus;
269 rxstatus = rxstatus << 16;
270 rxstatus |= (pktlength & 0xffff);
275 rxbuffer = dequeue_rx(priv);
276 if (rxbuffer == NULL)
277 netdev_info(priv->dev,
278 "sgdma rx and rx queue empty!\n");
281 iowrite32(0, &csr->control);
283 iowrite32(0xf, &csr->status);
285 /* kick the rx sgdma after reaping this descriptor */
286 pktsrx = sgdma_async_read(priv);
289 /* If the SGDMA indicated an end of packet on recv,
290 * then it's expected that the rxstatus from the
291 * descriptor is non-zero - meaning a valid packet
292 * with a nonzero length, or an error has been
293 * indicated. if not, then all we can do is signal
294 * an error and return no packet received. Most likely
295 * there is a system design error, or an error in the
296 * underlying kernel (cache or cache management problem)
298 netdev_err(priv->dev,
299 "SGDMA RX Error Info: %x, %x, %x\n",
300 sts, desc->status, rxstatus);
302 } else if (sts == 0) {
303 pktsrx = sgdma_async_read(priv);
310 /* Private functions */
311 static void sgdma_setup_descrip(struct sgdma_descrip *desc,
312 struct sgdma_descrip *ndesc,
313 dma_addr_t ndesc_phys,
321 /* Clear the next descriptor as not owned by hardware */
322 u32 ctrl = ndesc->control;
323 ctrl &= ~SGDMA_CONTROL_HW_OWNED;
324 ndesc->control = ctrl;
327 ctrl = SGDMA_CONTROL_HW_OWNED;
328 ctrl |= generate_eop;
332 /* Channel is implicitly zero, initialized to 0 by default */
336 desc->next = lower_32_bits(ndesc_phys);
337 desc->control = ctrl;
341 desc->bytes = length;
342 desc->bytes_xferred = 0;
345 /* If hardware is busy, don't restart async read.
346 * if status register is 0 - meaning initial state, restart async read,
347 * probably for the first time when populating a receive buffer.
348 * If read status indicate not busy and a status, restart the async
351 static int sgdma_async_read(struct altera_tse_private *priv)
353 struct sgdma_csr *csr = priv->rx_dma_csr;
354 struct sgdma_descrip *descbase = priv->rx_dma_desc;
355 struct sgdma_descrip *cdesc = &descbase[0];
356 struct sgdma_descrip *ndesc = &descbase[1];
358 struct tse_buffer *rxbuffer = NULL;
360 if (!sgdma_rxbusy(priv)) {
361 rxbuffer = queue_rx_peekhead(priv);
362 if (rxbuffer == NULL) {
363 netdev_err(priv->dev, "no rx buffers available\n");
367 sgdma_setup_descrip(cdesc, /* current descriptor */
368 ndesc, /* next descriptor */
369 sgdma_rxphysaddr(priv, ndesc),
370 0, /* read addr 0 for rx dma */
371 rxbuffer->dma_addr, /* write addr for rx dma */
372 0, /* read 'til EOP */
373 0, /* EOP: NA for rx dma */
374 0, /* read fixed: NA for rx dma */
375 0); /* SOP: NA for rx DMA */
377 dma_sync_single_for_device(priv->device,
382 iowrite32(lower_32_bits(sgdma_rxphysaddr(priv, cdesc)),
385 iowrite32((priv->rxctrlreg | SGDMA_CTRLREG_START),
394 static int sgdma_async_write(struct altera_tse_private *priv,
395 struct sgdma_descrip *desc)
397 struct sgdma_csr *csr = priv->tx_dma_csr;
399 if (sgdma_txbusy(priv))
402 /* clear control and status */
403 iowrite32(0, &csr->control);
404 iowrite32(0x1f, &csr->status);
406 dma_sync_single_for_device(priv->device, priv->txdescphys,
407 priv->sgdmadesclen, DMA_TO_DEVICE);
409 iowrite32(lower_32_bits(sgdma_txphysaddr(priv, desc)),
412 iowrite32((priv->txctrlreg | SGDMA_CTRLREG_START),
419 sgdma_txphysaddr(struct altera_tse_private *priv,
420 struct sgdma_descrip *desc)
422 dma_addr_t paddr = priv->txdescmem_busaddr;
423 uintptr_t offs = (uintptr_t)desc - (uintptr_t)priv->tx_dma_desc;
424 return (dma_addr_t)((uintptr_t)paddr + offs);
428 sgdma_rxphysaddr(struct altera_tse_private *priv,
429 struct sgdma_descrip *desc)
431 dma_addr_t paddr = priv->rxdescmem_busaddr;
432 uintptr_t offs = (uintptr_t)desc - (uintptr_t)priv->rx_dma_desc;
433 return (dma_addr_t)((uintptr_t)paddr + offs);
436 #define list_remove_head(list, entry, type, member) \
439 if (!list_empty(list)) { \
440 entry = list_entry((list)->next, type, member); \
441 list_del_init(&entry->member); \
445 #define list_peek_head(list, entry, type, member) \
448 if (!list_empty(list)) { \
449 entry = list_entry((list)->next, type, member); \
453 /* adds a tse_buffer to the tail of a tx buffer list.
454 * assumes the caller is managing and holding a mutual exclusion
455 * primitive to avoid simultaneous pushes/pops to the list.
458 queue_tx(struct altera_tse_private *priv, struct tse_buffer *buffer)
460 list_add_tail(&buffer->lh, &priv->txlisthd);
464 /* adds a tse_buffer to the tail of a rx buffer list
465 * assumes the caller is managing and holding a mutual exclusion
466 * primitive to avoid simultaneous pushes/pops to the list.
469 queue_rx(struct altera_tse_private *priv, struct tse_buffer *buffer)
471 list_add_tail(&buffer->lh, &priv->rxlisthd);
474 /* dequeues a tse_buffer from the transmit buffer list, otherwise
475 * returns NULL if empty.
476 * assumes the caller is managing and holding a mutual exclusion
477 * primitive to avoid simultaneous pushes/pops to the list.
479 static struct tse_buffer *
480 dequeue_tx(struct altera_tse_private *priv)
482 struct tse_buffer *buffer = NULL;
483 list_remove_head(&priv->txlisthd, buffer, struct tse_buffer, lh);
487 /* dequeues a tse_buffer from the receive buffer list, otherwise
488 * returns NULL if empty
489 * assumes the caller is managing and holding a mutual exclusion
490 * primitive to avoid simultaneous pushes/pops to the list.
492 static struct tse_buffer *
493 dequeue_rx(struct altera_tse_private *priv)
495 struct tse_buffer *buffer = NULL;
496 list_remove_head(&priv->rxlisthd, buffer, struct tse_buffer, lh);
500 /* dequeues a tse_buffer from the receive buffer list, otherwise
501 * returns NULL if empty
502 * assumes the caller is managing and holding a mutual exclusion
503 * primitive to avoid simultaneous pushes/pops to the list while the
504 * head is being examined.
506 static struct tse_buffer *
507 queue_rx_peekhead(struct altera_tse_private *priv)
509 struct tse_buffer *buffer = NULL;
510 list_peek_head(&priv->rxlisthd, buffer, struct tse_buffer, lh);
514 /* check and return rx sgdma status without polling
516 static int sgdma_rxbusy(struct altera_tse_private *priv)
518 struct sgdma_csr *csr = priv->rx_dma_csr;
519 return ioread32(&csr->status) & SGDMA_STSREG_BUSY;
522 /* waits for the tx sgdma to finish it's current operation, returns 0
523 * when it transitions to nonbusy, returns 1 if the operation times out
525 static int sgdma_txbusy(struct altera_tse_private *priv)
528 struct sgdma_csr *csr = priv->tx_dma_csr;
530 /* if DMA is busy, wait for current transactino to finish */
531 while ((ioread32(&csr->status) & SGDMA_STSREG_BUSY) && (delay++ < 100))
534 if (ioread32(&csr->status) & SGDMA_STSREG_BUSY) {
535 netdev_err(priv->dev, "timeout waiting for tx dma\n");