drivers/net/ethernet/3com/typhoon.c

   1 /* typhoon.c: A Linux Ethernet device driver for 3Com 3CR990 family of NICs */
   2 /*
   3         Written 2002-2004 by David Dillow <dave@thedillows.org>
   4         Based on code written 1998-2000 by Donald Becker <becker@scyld.com> and
   5         Linux 2.2.x driver by David P. McLean <davidpmclean@yahoo.com>.
   6
   7         This software may be used and distributed according to the terms of
   8         the GNU General Public License (GPL), incorporated herein by reference.
   9         Drivers based on or derived from this code fall under the GPL and must
  10         retain the authorship, copyright and license notice.  This file is not
  11         a complete program and may only be used when the entire operating
  12         system is licensed under the GPL.
  13
  14         This software is available on a public web site. It may enable
  15         cryptographic capabilities of the 3Com hardware, and may be
  16         exported from the United States under License Exception "TSU"
  17         pursuant to 15 C.F.R. Section 740.13(e).
  18
  19         This work was funded by the National Library of Medicine under
  20         the Department of Energy project number 0274DD06D1 and NLM project
  21         number Y1-LM-2015-01.
  22
  23         This driver is designed for the 3Com 3CR990 Family of cards with the
  24         3XP Processor. It has been tested on x86 and sparc64.
  25
  26         KNOWN ISSUES:
  27         *) Cannot DMA Rx packets to a 2 byte aligned address. Also firmware
  28                 issue. Hopefully 3Com will fix it.
  29         *) Waiting for a command response takes 8ms due to non-preemptable
  30                 polling. Only significant for getting stats and creating
  31                 SAs, but an ugly wart never the less.
  32
  33         TODO:
  34         *) Doesn't do IPSEC offloading. Yet. Keep yer pants on, it's coming.
  35         *) Add more support for ethtool (especially for NIC stats)
  36         *) Allow disabling of RX checksum offloading
  37         *) Fix MAC changing to work while the interface is up
  38                 (Need to put commands on the TX ring, which changes
  39                 the locking)
  40         *) Add in FCS to {rx,tx}_bytes, since the hardware doesn't. See
  41                 http://oss.sgi.com/cgi-bin/mesg.cgi?a=netdev&i=20031215152211.7003fe8e.rddunlap%40osdl.org
  42 */
  43
  44 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
  45  * Setting to > 1518 effectively disables this feature.
  46  */
  47 static int rx_copybreak = 200;
  48
  49 /* Should we use MMIO or Port IO?
  50  * 0: Port IO
  51  * 1: MMIO
  52  * 2: Try MMIO, fallback to Port IO
  53  */
  54 static unsigned int use_mmio = 2;
  55
  56 /* end user-configurable values */
  57
  58 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
  59  */
  60 static const int multicast_filter_limit = 32;
  61
  62 /* Operational parameters that are set at compile time. */
  63
  64 /* Keep the ring sizes a power of two for compile efficiency.
  65  * The compiler will convert <unsigned>'%'<2^N> into a bit mask.
  66  * Making the Tx ring too large decreases the effectiveness of channel
  67  * bonding and packet priority.
  68  * There are no ill effects from too-large receive rings.
  69  *
  70  * We don't currently use the Hi Tx ring so, don't make it very big.
  71  *
  72  * Beware that if we start using the Hi Tx ring, we will need to change
  73  * typhoon_num_free_tx() and typhoon_tx_complete() to account for that.
  74  */
  75 #define TXHI_ENTRIES            2
  76 #define TXLO_ENTRIES            128
  77 #define RX_ENTRIES              32
  78 #define COMMAND_ENTRIES         16
  79 #define RESPONSE_ENTRIES        32
  80
  81 #define COMMAND_RING_SIZE       (COMMAND_ENTRIES * sizeof(struct cmd_desc))
  82 #define RESPONSE_RING_SIZE      (RESPONSE_ENTRIES * sizeof(struct resp_desc))
  83
  84 /* The 3XP will preload and remove 64 entries from the free buffer
  85  * list, and we need one entry to keep the ring from wrapping, so
  86  * to keep this a power of two, we use 128 entries.
  87  */
  88 #define RXFREE_ENTRIES          128
  89 #define RXENT_ENTRIES           (RXFREE_ENTRIES - 1)
  90
  91 /* Operational parameters that usually are not changed. */
  92
  93 /* Time in jiffies before concluding the transmitter is hung. */
  94 #define TX_TIMEOUT  (2*HZ)
  95
  96 #define PKT_BUF_SZ              1536
  97 #define FIRMWARE_NAME           "3com/typhoon.bin"
  98
  99 #define pr_fmt(fmt)             KBUILD_MODNAME " " fmt
 100
 101 #include <linux/module.h>
 102 #include <linux/kernel.h>
 103 #include <linux/sched.h>
 104 #include <linux/string.h>
 105 #include <linux/timer.h>
 106 #include <linux/errno.h>
 107 #include <linux/ioport.h>
 108 #include <linux/interrupt.h>
 109 #include <linux/pci.h>
 110 #include <linux/netdevice.h>
 111 #include <linux/etherdevice.h>
 112 #include <linux/skbuff.h>
 113 #include <linux/mm.h>
 114 #include <linux/init.h>
 115 #include <linux/delay.h>
 116 #include <linux/ethtool.h>
 117 #include <linux/if_vlan.h>
 118 #include <linux/crc32.h>
 119 #include <linux/bitops.h>
 120 #include <asm/processor.h>
 121 #include <asm/io.h>
 122 #include <asm/uaccess.h>
 123 #include <linux/in6.h>
 124 #include <linux/dma-mapping.h>
 125 #include <linux/firmware.h>
 126
 127 #include "typhoon.h"
 128
 129 MODULE_AUTHOR("David Dillow <dave@thedillows.org>");
 130 MODULE_VERSION("1.0");
 131 MODULE_LICENSE("GPL");
 132 MODULE_FIRMWARE(FIRMWARE_NAME);
 133 MODULE_DESCRIPTION("3Com Typhoon Family (3C990, 3CR990, and variants)");
 134 MODULE_PARM_DESC(rx_copybreak, "Packets smaller than this are copied and "
 135                                "the buffer given back to the NIC. Default "
 136                                "is 200.");
 137 MODULE_PARM_DESC(use_mmio, "Use MMIO (1) or PIO(0) to access the NIC. "
 138                            "Default is to try MMIO and fallback to PIO.");
 139 module_param(rx_copybreak, int, 0);
 140 module_param(use_mmio, int, 0);
 141
 142 #if defined(NETIF_F_TSO) && MAX_SKB_FRAGS > 32
 143 #warning Typhoon only supports 32 entries in its SG list for TSO, disabling TSO
 144 #undef NETIF_F_TSO
 145 #endif
 146
 147 #if TXLO_ENTRIES <= (2 * MAX_SKB_FRAGS)
 148 #error TX ring too small!
 149 #endif
 150
 151 struct typhoon_card_info {
 152         const char *name;
 153         const int capabilities;
 154 };
 155
 156 #define TYPHOON_CRYPTO_NONE             0x00
 157 #define TYPHOON_CRYPTO_DES              0x01
 158 #define TYPHOON_CRYPTO_3DES             0x02
 159 #define TYPHOON_CRYPTO_VARIABLE         0x04
 160 #define TYPHOON_FIBER                   0x08
 161 #define TYPHOON_WAKEUP_NEEDS_RESET      0x10
 162
 163 enum typhoon_cards {
 164         TYPHOON_TX = 0, TYPHOON_TX95, TYPHOON_TX97, TYPHOON_SVR,
 165         TYPHOON_SVR95, TYPHOON_SVR97, TYPHOON_TXM, TYPHOON_BSVR,
 166         TYPHOON_FX95, TYPHOON_FX97, TYPHOON_FX95SVR, TYPHOON_FX97SVR,
 167         TYPHOON_FXM,
 168 };
 169
 170 /* directly indexed by enum typhoon_cards, above */
 171 static struct typhoon_card_info typhoon_card_info[] __devinitdata = {
 172         { "3Com Typhoon (3C990-TX)",
 173                 TYPHOON_CRYPTO_NONE},
 174         { "3Com Typhoon (3CR990-TX-95)",
 175                 TYPHOON_CRYPTO_DES},
 176         { "3Com Typhoon (3CR990-TX-97)",
 177                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
 178         { "3Com Typhoon (3C990SVR)",
 179                 TYPHOON_CRYPTO_NONE},
 180         { "3Com Typhoon (3CR990SVR95)",
 181                 TYPHOON_CRYPTO_DES},
 182         { "3Com Typhoon (3CR990SVR97)",
 183                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
 184         { "3Com Typhoon2 (3C990B-TX-M)",
 185                 TYPHOON_CRYPTO_VARIABLE},
 186         { "3Com Typhoon2 (3C990BSVR)",
 187                 TYPHOON_CRYPTO_VARIABLE},
 188         { "3Com Typhoon (3CR990-FX-95)",
 189                 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
 190         { "3Com Typhoon (3CR990-FX-97)",
 191                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
 192         { "3Com Typhoon (3CR990-FX-95 Server)",
 193                 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
 194         { "3Com Typhoon (3CR990-FX-97 Server)",
 195                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
 196         { "3Com Typhoon2 (3C990B-FX-97)",
 197                 TYPHOON_CRYPTO_VARIABLE | TYPHOON_FIBER},
 198 };
 199
 200 /* Notes on the new subsystem numbering scheme:
 201  * bits 0-1 indicate crypto capabilities: (0) variable, (1) DES, or (2) 3DES
 202  * bit 4 indicates if this card has secured firmware (we don't support it)
 203  * bit 8 indicates if this is a (0) copper or (1) fiber card
 204  * bits 12-16 indicate card type: (0) client and (1) server
 205  */
 206 static DEFINE_PCI_DEVICE_TABLE(typhoon_pci_tbl) = {
 207         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990,
 208           PCI_ANY_ID, PCI_ANY_ID, 0, 0,TYPHOON_TX },
 209         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_95,
 210           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX95 },
 211         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_97,
 212           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX97 },
 213         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
 214           PCI_ANY_ID, 0x1000, 0, 0, TYPHOON_TXM },
 215         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
 216           PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FXM },
 217         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
 218           PCI_ANY_ID, 0x2000, 0, 0, TYPHOON_BSVR },
 219         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 220           PCI_ANY_ID, 0x1101, 0, 0, TYPHOON_FX95 },
 221         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 222           PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FX97 },
 223         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 224           PCI_ANY_ID, 0x2101, 0, 0, TYPHOON_FX95SVR },
 225         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 226           PCI_ANY_ID, 0x2102, 0, 0, TYPHOON_FX97SVR },
 227         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR95,
 228           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR95 },
 229         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR97,
 230           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR97 },
 231         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR,
 232           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR },
 233         { 0, }
 234 };
 235 MODULE_DEVICE_TABLE(pci, typhoon_pci_tbl);
 236
 237 /* Define the shared memory area
 238  * Align everything the 3XP will normally be using.
 239  * We'll need to move/align txHi if we start using that ring.
 240  */
 241 #define __3xp_aligned   ____cacheline_aligned
 242 struct typhoon_shared {
 243         struct typhoon_interface        iface;
 244         struct typhoon_indexes          indexes                 __3xp_aligned;
 245         struct tx_desc                  txLo[TXLO_ENTRIES]      __3xp_aligned;
 246         struct rx_desc                  rxLo[RX_ENTRIES]        __3xp_aligned;
 247         struct rx_desc                  rxHi[RX_ENTRIES]        __3xp_aligned;
 248         struct cmd_desc                 cmd[COMMAND_ENTRIES]    __3xp_aligned;
 249         struct resp_desc                resp[RESPONSE_ENTRIES]  __3xp_aligned;
 250         struct rx_free                  rxBuff[RXFREE_ENTRIES]  __3xp_aligned;
 251         u32                             zeroWord;
 252         struct tx_desc                  txHi[TXHI_ENTRIES];
 253 } __packed;
 254
 255 struct rxbuff_ent {
 256         struct sk_buff *skb;
 257         dma_addr_t      dma_addr;
 258 };
 259
 260 struct typhoon {
 261         /* Tx cache line section */
 262         struct transmit_ring    txLoRing        ____cacheline_aligned;
 263         struct pci_dev *        tx_pdev;
 264         void __iomem            *tx_ioaddr;
 265         u32                     txlo_dma_addr;
 266
 267         /* Irq/Rx cache line section */
 268         void __iomem            *ioaddr         ____cacheline_aligned;
 269         struct typhoon_indexes *indexes;
 270         u8                      awaiting_resp;
 271         u8                      duplex;
 272         u8                      speed;
 273         u8                      card_state;
 274         struct basic_ring       rxLoRing;
 275         struct pci_dev *        pdev;
 276         struct net_device *     dev;
 277         struct napi_struct      napi;
 278         struct basic_ring       rxHiRing;
 279         struct basic_ring       rxBuffRing;
 280         struct rxbuff_ent       rxbuffers[RXENT_ENTRIES];
 281
 282         /* general section */
 283         spinlock_t              command_lock    ____cacheline_aligned;
 284         struct basic_ring       cmdRing;
 285         struct basic_ring       respRing;
 286         struct net_device_stats stats;
 287         struct net_device_stats stats_saved;
 288         struct typhoon_shared * shared;
 289         dma_addr_t              shared_dma;
 290         __le16                  xcvr_select;
 291         __le16                  wol_events;
 292         __le32                  offload;
 293
 294         /* unused stuff (future use) */
 295         int                     capabilities;
 296         struct transmit_ring    txHiRing;
 297 };
 298
 299 enum completion_wait_values {
 300         NoWait = 0, WaitNoSleep, WaitSleep,
 301 };
 302
 303 /* These are the values for the typhoon.card_state variable.
 304  * These determine where the statistics will come from in get_stats().
 305  * The sleep image does not support the statistics we need.
 306  */
 307 enum state_values {
 308         Sleeping = 0, Running,
 309 };
 310
 311 /* PCI writes are not guaranteed to be posted in order, but outstanding writes
 312  * cannot pass a read, so this forces current writes to post.
 313  */
 314 #define typhoon_post_pci_writes(x) \
 315         do { if(likely(use_mmio)) ioread32(x+TYPHOON_REG_HEARTBEAT); } while(0)
 316
 317 /* We'll wait up to six seconds for a reset, and half a second normally.
 318  */
 319 #define TYPHOON_UDELAY                  50
 320 #define TYPHOON_RESET_TIMEOUT_SLEEP     (6 * HZ)
 321 #define TYPHOON_RESET_TIMEOUT_NOSLEEP   ((6 * 1000000) / TYPHOON_UDELAY)
 322 #define TYPHOON_WAIT_TIMEOUT            ((1000000 / 2) / TYPHOON_UDELAY)
 323
 324 #if defined(NETIF_F_TSO)
 325 #define skb_tso_size(x)         (skb_shinfo(x)->gso_size)
 326 #define TSO_NUM_DESCRIPTORS     2
 327 #define TSO_OFFLOAD_ON          TYPHOON_OFFLOAD_TCP_SEGMENT
 328 #else
 329 #define NETIF_F_TSO             0
 330 #define skb_tso_size(x)         0
 331 #define TSO_NUM_DESCRIPTORS     0
 332 #define TSO_OFFLOAD_ON          0
 333 #endif
 334
 335 static inline void
 336 typhoon_inc_index(u32 *index, const int count, const int num_entries)
 337 {
 338         /* Increment a ring index -- we can use this for all rings execept
 339          * the Rx rings, as they use different size descriptors
 340          * otherwise, everything is the same size as a cmd_desc
 341          */
 342         *index += count * sizeof(struct cmd_desc);
 343         *index %= num_entries * sizeof(struct cmd_desc);
 344 }
 345
 346 static inline void
 347 typhoon_inc_cmd_index(u32 *index, const int count)
 348 {
 349         typhoon_inc_index(index, count, COMMAND_ENTRIES);
 350 }
 351
 352 static inline void
 353 typhoon_inc_resp_index(u32 *index, const int count)
 354 {
 355         typhoon_inc_index(index, count, RESPONSE_ENTRIES);
 356 }
 357
 358 static inline void
 359 typhoon_inc_rxfree_index(u32 *index, const int count)
 360 {
 361         typhoon_inc_index(index, count, RXFREE_ENTRIES);
 362 }
 363
 364 static inline void
 365 typhoon_inc_tx_index(u32 *index, const int count)
 366 {
 367         /* if we start using the Hi Tx ring, this needs updateing */
 368         typhoon_inc_index(index, count, TXLO_ENTRIES);
 369 }
 370
 371 static inline void
 372 typhoon_inc_rx_index(u32 *index, const int count)
 373 {
 374         /* sizeof(struct rx_desc) != sizeof(struct cmd_desc) */
 375         *index += count * sizeof(struct rx_desc);
 376         *index %= RX_ENTRIES * sizeof(struct rx_desc);
 377 }
 378
 379 static int
 380 typhoon_reset(void __iomem *ioaddr, int wait_type)
 381 {
 382         int i, err = 0;
 383         int timeout;
 384
 385         if(wait_type == WaitNoSleep)
 386                 timeout = TYPHOON_RESET_TIMEOUT_NOSLEEP;
 387         else
 388                 timeout = TYPHOON_RESET_TIMEOUT_SLEEP;
 389
 390         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
 391         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
 392
 393         iowrite32(TYPHOON_RESET_ALL, ioaddr + TYPHOON_REG_SOFT_RESET);
 394         typhoon_post_pci_writes(ioaddr);
 395         udelay(1);
 396         iowrite32(TYPHOON_RESET_NONE, ioaddr + TYPHOON_REG_SOFT_RESET);
 397
 398         if(wait_type != NoWait) {
 399                 for(i = 0; i < timeout; i++) {
 400                         if(ioread32(ioaddr + TYPHOON_REG_STATUS) ==
 401                            TYPHOON_STATUS_WAITING_FOR_HOST)
 402                                 goto out;
 403
 404                         if(wait_type == WaitSleep)
 405                                 schedule_timeout_uninterruptible(1);
 406                         else
 407                                 udelay(TYPHOON_UDELAY);
 408                 }
 409
 410                 err = -ETIMEDOUT;
 411         }
 412
 413 out:
 414         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
 415         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
 416
 417         /* The 3XP seems to need a little extra time to complete the load
 418          * of the sleep image before we can reliably boot it. Failure to
 419          * do this occasionally results in a hung adapter after boot in
 420          * typhoon_init_one() while trying to read the MAC address or
 421          * putting the card to sleep. 3Com's driver waits 5ms, but
 422          * that seems to be overkill. However, if we can sleep, we might
 423          * as well give it that much time. Otherwise, we'll give it 500us,
 424          * which should be enough (I've see it work well at 100us, but still
 425          * saw occasional problems.)
 426          */
 427         if(wait_type == WaitSleep)
 428                 msleep(5);
 429         else
 430                 udelay(500);
 431         return err;
 432 }
 433
 434 static int
 435 typhoon_wait_status(void __iomem *ioaddr, u32 wait_value)
 436 {
 437         int i, err = 0;
 438
 439         for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
 440                 if(ioread32(ioaddr + TYPHOON_REG_STATUS) == wait_value)
 441                         goto out;
 442                 udelay(TYPHOON_UDELAY);
 443         }
 444
 445         err = -ETIMEDOUT;
 446
 447 out:
 448         return err;
 449 }
 450
 451 static inline void
 452 typhoon_media_status(struct net_device *dev, struct resp_desc *resp)
 453 {
 454         if(resp->parm1 & TYPHOON_MEDIA_STAT_NO_LINK)
 455                 netif_carrier_off(dev);
 456         else
 457                 netif_carrier_on(dev);
 458 }
 459
 460 static inline void
 461 typhoon_hello(struct typhoon *tp)
 462 {
 463         struct basic_ring *ring = &tp->cmdRing;
 464         struct cmd_desc *cmd;
 465
 466         /* We only get a hello request if we've not sent anything to the
 467          * card in a long while. If the lock is held, then we're in the
 468          * process of issuing a command, so we don't need to respond.
 469          */
 470         if(spin_trylock(&tp->command_lock)) {
 471                 cmd = (struct cmd_desc *)(ring->ringBase + ring->lastWrite);
 472                 typhoon_inc_cmd_index(&ring->lastWrite, 1);
 473
 474                 INIT_COMMAND_NO_RESPONSE(cmd, TYPHOON_CMD_HELLO_RESP);
 475                 wmb();
 476                 iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
 477                 spin_unlock(&tp->command_lock);
 478         }
 479 }
 480
 481 static int
 482 typhoon_process_response(struct typhoon *tp, int resp_size,
 483                                 struct resp_desc *resp_save)
 484 {
 485         struct typhoon_indexes *indexes = tp->indexes;
 486         struct resp_desc *resp;
 487         u8 *base = tp->respRing.ringBase;
 488         int count, len, wrap_len;
 489         u32 cleared;
 490         u32 ready;
 491
 492         cleared = le32_to_cpu(indexes->respCleared);
 493         ready = le32_to_cpu(indexes->respReady);
 494         while(cleared != ready) {
 495                 resp = (struct resp_desc *)(base + cleared);
 496                 count = resp->numDesc + 1;
 497                 if(resp_save && resp->seqNo) {
 498                         if(count > resp_size) {
 499                                 resp_save->flags = TYPHOON_RESP_ERROR;
 500                                 goto cleanup;
 501                         }
 502
 503                         wrap_len = 0;
 504                         len = count * sizeof(*resp);
 505                         if(unlikely(cleared + len > RESPONSE_RING_SIZE)) {
 506                                 wrap_len = cleared + len - RESPONSE_RING_SIZE;
 507                                 len = RESPONSE_RING_SIZE - cleared;
 508                         }
 509
 510                         memcpy(resp_save, resp, len);
 511                         if(unlikely(wrap_len)) {
 512                                 resp_save += len / sizeof(*resp);
 513                                 memcpy(resp_save, base, wrap_len);
 514                         }
 515
 516                         resp_save = NULL;
 517                 } else if(resp->cmd == TYPHOON_CMD_READ_MEDIA_STATUS) {
 518                         typhoon_media_status(tp->dev, resp);
 519                 } else if(resp->cmd == TYPHOON_CMD_HELLO_RESP) {
 520                         typhoon_hello(tp);
 521                 } else {
 522                         netdev_err(tp->dev,
 523                                    "dumping unexpected response 0x%04x:%d:0x%02x:0x%04x:%08x:%08x\n",
 524                                    le16_to_cpu(resp->cmd),
 525                                    resp->numDesc, resp->flags,
 526                                    le16_to_cpu(resp->parm1),
 527                                    le32_to_cpu(resp->parm2),
 528                                    le32_to_cpu(resp->parm3));
 529                 }
 530
 531 cleanup:
 532                 typhoon_inc_resp_index(&cleared, count);
 533         }
 534
 535         indexes->respCleared = cpu_to_le32(cleared);
 536         wmb();
 537         return resp_save == NULL;
 538 }
 539
 540 static inline int
 541 typhoon_num_free(int lastWrite, int lastRead, int ringSize)
 542 {
 543         /* this works for all descriptors but rx_desc, as they are a
 544          * different size than the cmd_desc -- everyone else is the same
 545          */
 546         lastWrite /= sizeof(struct cmd_desc);
 547         lastRead /= sizeof(struct cmd_desc);
 548         return (ringSize + lastRead - lastWrite - 1) % ringSize;
 549 }
 550
 551 static inline int
 552 typhoon_num_free_cmd(struct typhoon *tp)
 553 {
 554         int lastWrite = tp->cmdRing.lastWrite;
 555         int cmdCleared = le32_to_cpu(tp->indexes->cmdCleared);
 556
 557         return typhoon_num_free(lastWrite, cmdCleared, COMMAND_ENTRIES);
 558 }
 559
 560 static inline int
 561 typhoon_num_free_resp(struct typhoon *tp)
 562 {
 563         int respReady = le32_to_cpu(tp->indexes->respReady);
 564         int respCleared = le32_to_cpu(tp->indexes->respCleared);
 565
 566         return typhoon_num_free(respReady, respCleared, RESPONSE_ENTRIES);
 567 }
 568
 569 static inline int
 570 typhoon_num_free_tx(struct transmit_ring *ring)
 571 {
 572         /* if we start using the Hi Tx ring, this needs updating */
 573         return typhoon_num_free(ring->lastWrite, ring->lastRead, TXLO_ENTRIES);
 574 }
 575
 576 static int
 577 typhoon_issue_command(struct typhoon *tp, int num_cmd, struct cmd_desc *cmd,
 578                       int num_resp, struct resp_desc *resp)
 579 {
 580         struct typhoon_indexes *indexes = tp->indexes;
 581         struct basic_ring *ring = &tp->cmdRing;
 582         struct resp_desc local_resp;
 583         int i, err = 0;
 584         int got_resp;
 585         int freeCmd, freeResp;
 586         int len, wrap_len;
 587
 588         spin_lock(&tp->command_lock);
 589
 590         freeCmd = typhoon_num_free_cmd(tp);
 591         freeResp = typhoon_num_free_resp(tp);
 592
 593         if(freeCmd < num_cmd || freeResp < num_resp) {
 594                 netdev_err(tp->dev, "no descs for cmd, had (needed) %d (%d) cmd, %d (%d) resp\n",
 595                            freeCmd, num_cmd, freeResp, num_resp);
 596                 err = -ENOMEM;
 597                 goto out;
 598         }
 599
 600         if(cmd->flags & TYPHOON_CMD_RESPOND) {
 601                 /* If we're expecting a response, but the caller hasn't given
 602                  * us a place to put it, we'll provide one.
 603                  */
 604                 tp->awaiting_resp = 1;
 605                 if(resp == NULL) {
 606                         resp = &local_resp;
 607                         num_resp = 1;
 608                 }
 609         }
 610
 611         wrap_len = 0;
 612         len = num_cmd * sizeof(*cmd);
 613         if(unlikely(ring->lastWrite + len > COMMAND_RING_SIZE)) {
 614                 wrap_len = ring->lastWrite + len - COMMAND_RING_SIZE;
 615                 len = COMMAND_RING_SIZE - ring->lastWrite;
 616         }
 617
 618         memcpy(ring->ringBase + ring->lastWrite, cmd, len);
 619         if(unlikely(wrap_len)) {
 620                 struct cmd_desc *wrap_ptr = cmd;
 621                 wrap_ptr += len / sizeof(*cmd);
 622                 memcpy(ring->ringBase, wrap_ptr, wrap_len);
 623         }
 624
 625         typhoon_inc_cmd_index(&ring->lastWrite, num_cmd);
 626
 627         /* "I feel a presence... another warrior is on the mesa."
 628          */
 629         wmb();
 630         iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
 631         typhoon_post_pci_writes(tp->ioaddr);
 632
 633         if((cmd->flags & TYPHOON_CMD_RESPOND) == 0)
 634                 goto out;
 635
 636         /* Ugh. We'll be here about 8ms, spinning our thumbs, unable to
 637          * preempt or do anything other than take interrupts. So, don't
 638          * wait for a response unless you have to.
 639          *
 640          * I've thought about trying to sleep here, but we're called
 641          * from many contexts that don't allow that. Also, given the way
 642          * 3Com has implemented irq coalescing, we would likely timeout --
 643          * this has been observed in real life!
 644          *
 645          * The big killer is we have to wait to get stats from the card,
 646          * though we could go to a periodic refresh of those if we don't
 647          * mind them getting somewhat stale. The rest of the waiting
 648          * commands occur during open/close/suspend/resume, so they aren't
 649          * time critical. Creating SAs in the future will also have to
 650          * wait here.
 651          */
 652         got_resp = 0;
 653         for(i = 0; i < TYPHOON_WAIT_TIMEOUT && !got_resp; i++) {
 654                 if(indexes->respCleared != indexes->respReady)
 655                         got_resp = typhoon_process_response(tp, num_resp,
 656                                                                 resp);
 657                 udelay(TYPHOON_UDELAY);
 658         }
 659
 660         if(!got_resp) {
 661                 err = -ETIMEDOUT;
 662                 goto out;
 663         }
 664
 665         /* Collect the error response even if we don't care about the
 666          * rest of the response
 667          */
 668         if(resp->flags & TYPHOON_RESP_ERROR)
 669                 err = -EIO;
 670
 671 out:
 672         if(tp->awaiting_resp) {
 673                 tp->awaiting_resp = 0;
 674                 smp_wmb();
 675
 676                 /* Ugh. If a response was added to the ring between
 677                  * the call to typhoon_process_response() and the clearing
 678                  * of tp->awaiting_resp, we could have missed the interrupt
 679                  * and it could hang in the ring an indeterminate amount of
 680                  * time. So, check for it, and interrupt ourselves if this
 681                  * is the case.
 682                  */
 683                 if(indexes->respCleared != indexes->respReady)
 684                         iowrite32(1, tp->ioaddr + TYPHOON_REG_SELF_INTERRUPT);
 685         }
 686
 687         spin_unlock(&tp->command_lock);
 688         return err;
 689 }
 690
 691 static inline void
 692 typhoon_tso_fill(struct sk_buff *skb, struct transmit_ring *txRing,
 693                         u32 ring_dma)
 694 {
 695         struct tcpopt_desc *tcpd;
 696         u32 tcpd_offset = ring_dma;
 697
 698         tcpd = (struct tcpopt_desc *) (txRing->ringBase + txRing->lastWrite);
 699         tcpd_offset += txRing->lastWrite;
 700         tcpd_offset += offsetof(struct tcpopt_desc, bytesTx);
 701         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 702
 703         tcpd->flags = TYPHOON_OPT_DESC | TYPHOON_OPT_TCP_SEG;
 704         tcpd->numDesc = 1;
 705         tcpd->mss_flags = cpu_to_le16(skb_tso_size(skb));
 706         tcpd->mss_flags |= TYPHOON_TSO_FIRST | TYPHOON_TSO_LAST;
 707         tcpd->respAddrLo = cpu_to_le32(tcpd_offset);
 708         tcpd->bytesTx = cpu_to_le32(skb->len);
 709         tcpd->status = 0;
 710 }
 711
 712 static netdev_tx_t
 713 typhoon_start_tx(struct sk_buff *skb, struct net_device *dev)
 714 {
 715         struct typhoon *tp = netdev_priv(dev);
 716         struct transmit_ring *txRing;
 717         struct tx_desc *txd, *first_txd;
 718         dma_addr_t skb_dma;
 719         int numDesc;
 720
 721         /* we have two rings to choose from, but we only use txLo for now
 722          * If we start using the Hi ring as well, we'll need to update
 723          * typhoon_stop_runtime(), typhoon_interrupt(), typhoon_num_free_tx(),
 724          * and TXHI_ENTRIES to match, as well as update the TSO code below
 725          * to get the right DMA address
 726          */
 727         txRing = &tp->txLoRing;
 728
 729         /* We need one descriptor for each fragment of the sk_buff, plus the
 730          * one for the ->data area of it.
 731          *
 732          * The docs say a maximum of 16 fragment descriptors per TCP option
 733          * descriptor, then make a new packet descriptor and option descriptor
 734          * for the next 16 fragments. The engineers say just an option
 735          * descriptor is needed. I've tested up to 26 fragments with a single
 736          * packet descriptor/option descriptor combo, so I use that for now.
 737          *
 738          * If problems develop with TSO, check this first.
 739          */
 740         numDesc = skb_shinfo(skb)->nr_frags + 1;
 741         if (skb_is_gso(skb))
 742                 numDesc++;
 743
 744         /* When checking for free space in the ring, we need to also
 745          * account for the initial Tx descriptor, and we always must leave
 746          * at least one descriptor unused in the ring so that it doesn't
 747          * wrap and look empty.
 748          *
 749          * The only time we should loop here is when we hit the race
 750          * between marking the queue awake and updating the cleared index.
 751          * Just loop and it will appear. This comes from the acenic driver.
 752          */
 753         while(unlikely(typhoon_num_free_tx(txRing) < (numDesc + 2)))
 754                 smp_rmb();
 755
 756         first_txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
 757         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 758
 759         first_txd->flags = TYPHOON_TX_DESC | TYPHOON_DESC_VALID;
 760         first_txd->numDesc = 0;
 761         first_txd->len = 0;
 762         first_txd->tx_addr = (u64)((unsigned long) skb);
 763         first_txd->processFlags = 0;
 764
 765         if(skb->ip_summed == CHECKSUM_PARTIAL) {
 766                 /* The 3XP will figure out if this is UDP/TCP */
 767                 first_txd->processFlags |= TYPHOON_TX_PF_TCP_CHKSUM;
 768                 first_txd->processFlags |= TYPHOON_TX_PF_UDP_CHKSUM;
 769                 first_txd->processFlags |= TYPHOON_TX_PF_IP_CHKSUM;
 770         }
 771
 772         if(vlan_tx_tag_present(skb)) {
 773                 first_txd->processFlags |=
 774                     TYPHOON_TX_PF_INSERT_VLAN | TYPHOON_TX_PF_VLAN_PRIORITY;
 775                 first_txd->processFlags |=
 776                     cpu_to_le32(htons(vlan_tx_tag_get(skb)) <<
 777                                 TYPHOON_TX_PF_VLAN_TAG_SHIFT);
 778         }
 779
 780         if (skb_is_gso(skb)) {
 781                 first_txd->processFlags |= TYPHOON_TX_PF_TCP_SEGMENT;
 782                 first_txd->numDesc++;
 783
 784                 typhoon_tso_fill(skb, txRing, tp->txlo_dma_addr);
 785         }
 786
 787         txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
 788         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 789
 790         /* No need to worry about padding packet -- the firmware pads
 791          * it with zeros to ETH_ZLEN for us.
 792          */
 793         if(skb_shinfo(skb)->nr_frags == 0) {
 794                 skb_dma = pci_map_single(tp->tx_pdev, skb->data, skb->len,
 795                                        PCI_DMA_TODEVICE);
 796                 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
 797                 txd->len = cpu_to_le16(skb->len);
 798                 txd->frag.addr = cpu_to_le32(skb_dma);
 799                 txd->frag.addrHi = 0;
 800                 first_txd->numDesc++;
 801         } else {
 802                 int i, len;
 803
 804                 len = skb_headlen(skb);
 805                 skb_dma = pci_map_single(tp->tx_pdev, skb->data, len,
 806                                          PCI_DMA_TODEVICE);
 807                 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
 808                 txd->len = cpu_to_le16(len);
 809                 txd->frag.addr = cpu_to_le32(skb_dma);
 810                 txd->frag.addrHi = 0;
 811                 first_txd->numDesc++;
 812
 813                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
 814                         const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 815                         void *frag_addr;
 816
 817                         txd = (struct tx_desc *) (txRing->ringBase +
 818                                                 txRing->lastWrite);
 819                         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 820
 821                         len = skb_frag_size(frag);
 822                         frag_addr = skb_frag_address(frag);
 823                         skb_dma = pci_map_single(tp->tx_pdev, frag_addr, len,
 824                                          PCI_DMA_TODEVICE);
 825                         txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
 826                         txd->len = cpu_to_le16(len);
 827                         txd->frag.addr = cpu_to_le32(skb_dma);
 828                         txd->frag.addrHi = 0;
 829                         first_txd->numDesc++;
 830                 }
 831         }
 832
 833         /* Kick the 3XP
 834          */
 835         wmb();
 836         iowrite32(txRing->lastWrite, tp->tx_ioaddr + txRing->writeRegister);
 837
 838         /* If we don't have room to put the worst case packet on the
 839          * queue, then we must stop the queue. We need 2 extra
 840          * descriptors -- one to prevent ring wrap, and one for the
 841          * Tx header.
 842          */
 843         numDesc = MAX_SKB_FRAGS + TSO_NUM_DESCRIPTORS + 1;
 844
 845         if(typhoon_num_free_tx(txRing) < (numDesc + 2)) {
 846                 netif_stop_queue(dev);
 847
 848                 /* A Tx complete IRQ could have gotten between, making
 849                  * the ring free again. Only need to recheck here, since
 850                  * Tx is serialized.
 851                  */
 852                 if(typhoon_num_free_tx(txRing) >= (numDesc + 2))
 853                         netif_wake_queue(dev);
 854         }
 855
 856         return NETDEV_TX_OK;
 857 }
 858
 859 static void
 860 typhoon_set_rx_mode(struct net_device *dev)
 861 {
 862         struct typhoon *tp = netdev_priv(dev);
 863         struct cmd_desc xp_cmd;
 864         u32 mc_filter[2];
 865         __le16 filter;
 866
 867         filter = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
 868         if(dev->flags & IFF_PROMISC) {
 869                 filter |= TYPHOON_RX_FILTER_PROMISCOUS;
 870         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
 871                   (dev->flags & IFF_ALLMULTI)) {
 872                 /* Too many to match, or accept all multicasts. */
 873                 filter |= TYPHOON_RX_FILTER_ALL_MCAST;
 874         } else if (!netdev_mc_empty(dev)) {
 875                 struct netdev_hw_addr *ha;
 876
 877                 memset(mc_filter, 0, sizeof(mc_filter));
 878                 netdev_for_each_mc_addr(ha, dev) {
 879                         int bit = ether_crc(ETH_ALEN, ha->addr) & 0x3f;
 880                         mc_filter[bit >> 5] |= 1 << (bit & 0x1f);
 881                 }
 882
 883                 INIT_COMMAND_NO_RESPONSE(&xp_cmd,
 884                                          TYPHOON_CMD_SET_MULTICAST_HASH);
 885                 xp_cmd.parm1 = TYPHOON_MCAST_HASH_SET;
 886                 xp_cmd.parm2 = cpu_to_le32(mc_filter[0]);
 887                 xp_cmd.parm3 = cpu_to_le32(mc_filter[1]);
 888                 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
 889
 890                 filter |= TYPHOON_RX_FILTER_MCAST_HASH;
 891         }
 892
 893         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
 894         xp_cmd.parm1 = filter;
 895         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
 896 }
 897
 898 static int
 899 typhoon_do_get_stats(struct typhoon *tp)
 900 {
 901         struct net_device_stats *stats = &tp->stats;
 902         struct net_device_stats *saved = &tp->stats_saved;
 903         struct cmd_desc xp_cmd;
 904         struct resp_desc xp_resp[7];
 905         struct stats_resp *s = (struct stats_resp *) xp_resp;
 906         int err;
 907
 908         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_STATS);
 909         err = typhoon_issue_command(tp, 1, &xp_cmd, 7, xp_resp);
 910         if(err < 0)
 911                 return err;
 912
 913         /* 3Com's Linux driver uses txMultipleCollisions as it's
 914          * collisions value, but there is some other collision info as well...
 915          *
 916          * The extra status reported would be a good candidate for
 917          * ethtool_ops->get_{strings,stats}()
 918          */
 919         stats->tx_packets = le32_to_cpu(s->txPackets) +
 920                         saved->tx_packets;
 921         stats->tx_bytes = le64_to_cpu(s->txBytes) +
 922                         saved->tx_bytes;
 923         stats->tx_errors = le32_to_cpu(s->txCarrierLost) +
 924                         saved->tx_errors;
 925         stats->tx_carrier_errors = le32_to_cpu(s->txCarrierLost) +
 926                         saved->tx_carrier_errors;
 927         stats->collisions = le32_to_cpu(s->txMultipleCollisions) +
 928                         saved->collisions;
 929         stats->rx_packets = le32_to_cpu(s->rxPacketsGood) +
 930                         saved->rx_packets;
 931         stats->rx_bytes = le64_to_cpu(s->rxBytesGood) +
 932                         saved->rx_bytes;
 933         stats->rx_fifo_errors = le32_to_cpu(s->rxFifoOverruns) +
 934                         saved->rx_fifo_errors;
 935         stats->rx_errors = le32_to_cpu(s->rxFifoOverruns) +
 936                         le32_to_cpu(s->BadSSD) + le32_to_cpu(s->rxCrcErrors) +
 937                         saved->rx_errors;
 938         stats->rx_crc_errors = le32_to_cpu(s->rxCrcErrors) +
 939                         saved->rx_crc_errors;
 940         stats->rx_length_errors = le32_to_cpu(s->rxOversized) +
 941                         saved->rx_length_errors;
 942         tp->speed = (s->linkStatus & TYPHOON_LINK_100MBPS) ?
 943                         SPEED_100 : SPEED_10;
 944         tp->duplex = (s->linkStatus & TYPHOON_LINK_FULL_DUPLEX) ?
 945                         DUPLEX_FULL : DUPLEX_HALF;
 946
 947         return 0;
 948 }
 949
 950 static struct net_device_stats *
 951 typhoon_get_stats(struct net_device *dev)
 952 {
 953         struct typhoon *tp = netdev_priv(dev);
 954         struct net_device_stats *stats = &tp->stats;
 955         struct net_device_stats *saved = &tp->stats_saved;
 956
 957         smp_rmb();
 958         if(tp->card_state == Sleeping)
 959                 return saved;
 960
 961         if(typhoon_do_get_stats(tp) < 0) {
 962                 netdev_err(dev, "error getting stats\n");
 963                 return saved;
 964         }
 965
 966         return stats;
 967 }
 968
 969 static int
 970 typhoon_set_mac_address(struct net_device *dev, void *addr)
 971 {
 972         struct sockaddr *saddr = (struct sockaddr *) addr;
 973
 974         if(netif_running(dev))
 975                 return -EBUSY;
 976
 977         memcpy(dev->dev_addr, saddr->sa_data, dev->addr_len);
 978         return 0;
 979 }
 980
 981 static void
 982 typhoon_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
 983 {
 984         struct typhoon *tp = netdev_priv(dev);
 985         struct pci_dev *pci_dev = tp->pdev;
 986         struct cmd_desc xp_cmd;
 987         struct resp_desc xp_resp[3];
 988
 989         smp_rmb();
 990         if(tp->card_state == Sleeping) {
 991                 strcpy(info->fw_version, "Sleep image");
 992         } else {
 993                 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
 994                 if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
 995                         strcpy(info->fw_version, "Unknown runtime");
 996                 } else {
 997                         u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
 998                         snprintf(info->fw_version, 32, "%02x.%03x.%03x",
 999                                  sleep_ver >> 24, (sleep_ver >> 12) & 0xfff,
1000                                  sleep_ver & 0xfff);
1001                 }
1002         }
1003
1004         strcpy(info->driver, KBUILD_MODNAME);
1005         strcpy(info->bus_info, pci_name(pci_dev));
1006 }
1007
1008 static int
1009 typhoon_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1010 {
1011         struct typhoon *tp = netdev_priv(dev);
1012
1013         cmd->supported = SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
1014                                 SUPPORTED_Autoneg;
1015
1016         switch (tp->xcvr_select) {
1017         case TYPHOON_XCVR_10HALF:
1018                 cmd->advertising = ADVERTISED_10baseT_Half;
1019                 break;
1020         case TYPHOON_XCVR_10FULL:
1021                 cmd->advertising = ADVERTISED_10baseT_Full;
1022                 break;
1023         case TYPHOON_XCVR_100HALF:
1024                 cmd->advertising = ADVERTISED_100baseT_Half;
1025                 break;
1026         case TYPHOON_XCVR_100FULL:
1027                 cmd->advertising = ADVERTISED_100baseT_Full;
1028                 break;
1029         case TYPHOON_XCVR_AUTONEG:
1030                 cmd->advertising = ADVERTISED_10baseT_Half |
1031                                             ADVERTISED_10baseT_Full |
1032                                             ADVERTISED_100baseT_Half |
1033                                             ADVERTISED_100baseT_Full |
1034                                             ADVERTISED_Autoneg;
1035                 break;
1036         }
1037
1038         if(tp->capabilities & TYPHOON_FIBER) {
1039                 cmd->supported |= SUPPORTED_FIBRE;
1040                 cmd->advertising |= ADVERTISED_FIBRE;
1041                 cmd->port = PORT_FIBRE;
1042         } else {
1043                 cmd->supported |= SUPPORTED_10baseT_Half |
1044                                         SUPPORTED_10baseT_Full |
1045                                         SUPPORTED_TP;
1046                 cmd->advertising |= ADVERTISED_TP;
1047                 cmd->port = PORT_TP;
1048         }
1049
1050         /* need to get stats to make these link speed/duplex valid */
1051         typhoon_do_get_stats(tp);
1052         ethtool_cmd_speed_set(cmd, tp->speed);
1053         cmd->duplex = tp->duplex;
1054         cmd->phy_address = 0;
1055         cmd->transceiver = XCVR_INTERNAL;
1056         if(tp->xcvr_select == TYPHOON_XCVR_AUTONEG)
1057                 cmd->autoneg = AUTONEG_ENABLE;
1058         else
1059                 cmd->autoneg = AUTONEG_DISABLE;
1060         cmd->maxtxpkt = 1;
1061         cmd->maxrxpkt = 1;
1062
1063         return 0;
1064 }
1065
1066 static int
1067 typhoon_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1068 {
1069         struct typhoon *tp = netdev_priv(dev);
1070         u32 speed = ethtool_cmd_speed(cmd);
1071         struct cmd_desc xp_cmd;
1072         __le16 xcvr;
1073         int err;
1074
1075         err = -EINVAL;
1076         if (cmd->autoneg == AUTONEG_ENABLE) {
1077                 xcvr = TYPHOON_XCVR_AUTONEG;
1078         } else {
1079                 if (cmd->duplex == DUPLEX_HALF) {
1080                         if (speed == SPEED_10)
1081                                 xcvr = TYPHOON_XCVR_10HALF;
1082                         else if (speed == SPEED_100)
1083                                 xcvr = TYPHOON_XCVR_100HALF;
1084                         else
1085                                 goto out;
1086                 } else if (cmd->duplex == DUPLEX_FULL) {
1087                         if (speed == SPEED_10)
1088                                 xcvr = TYPHOON_XCVR_10FULL;
1089                         else if (speed == SPEED_100)
1090                                 xcvr = TYPHOON_XCVR_100FULL;
1091                         else
1092                                 goto out;
1093                 } else
1094                         goto out;
1095         }
1096
1097         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1098         xp_cmd.parm1 = xcvr;
1099         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1100         if(err < 0)
1101                 goto out;
1102
1103         tp->xcvr_select = xcvr;
1104         if(cmd->autoneg == AUTONEG_ENABLE) {
1105                 tp->speed = 0xff;       /* invalid */
1106                 tp->duplex = 0xff;      /* invalid */
1107         } else {
1108                 tp->speed = speed;
1109                 tp->duplex = cmd->duplex;
1110         }
1111
1112 out:
1113         return err;
1114 }
1115
1116 static void
1117 typhoon_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1118 {
1119         struct typhoon *tp = netdev_priv(dev);
1120
1121         wol->supported = WAKE_PHY | WAKE_MAGIC;
1122         wol->wolopts = 0;
1123         if(tp->wol_events & TYPHOON_WAKE_LINK_EVENT)
1124                 wol->wolopts |= WAKE_PHY;
1125         if(tp->wol_events & TYPHOON_WAKE_MAGIC_PKT)
1126                 wol->wolopts |= WAKE_MAGIC;
1127         memset(&wol->sopass, 0, sizeof(wol->sopass));
1128 }
1129
1130 static int
1131 typhoon_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1132 {
1133         struct typhoon *tp = netdev_priv(dev);
1134
1135         if(wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC))
1136                 return -EINVAL;
1137
1138         tp->wol_events = 0;
1139         if(wol->wolopts & WAKE_PHY)
1140                 tp->wol_events |= TYPHOON_WAKE_LINK_EVENT;
1141         if(wol->wolopts & WAKE_MAGIC)
1142                 tp->wol_events |= TYPHOON_WAKE_MAGIC_PKT;
1143
1144         return 0;
1145 }
1146
1147 static void
1148 typhoon_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
1149 {
1150         ering->rx_max_pending = RXENT_ENTRIES;
1151         ering->tx_max_pending = TXLO_ENTRIES - 1;
1152
1153         ering->rx_pending = RXENT_ENTRIES;
1154         ering->tx_pending = TXLO_ENTRIES - 1;
1155 }
1156
1157 static const struct ethtool_ops typhoon_ethtool_ops = {
1158         .get_settings           = typhoon_get_settings,
1159         .set_settings           = typhoon_set_settings,
1160         .get_drvinfo            = typhoon_get_drvinfo,
1161         .get_wol                = typhoon_get_wol,
1162         .set_wol                = typhoon_set_wol,
1163         .get_link               = ethtool_op_get_link,
1164         .get_ringparam          = typhoon_get_ringparam,
1165 };
1166
1167 static int
1168 typhoon_wait_interrupt(void __iomem *ioaddr)
1169 {
1170         int i, err = 0;
1171
1172         for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
1173                 if(ioread32(ioaddr + TYPHOON_REG_INTR_STATUS) &
1174                    TYPHOON_INTR_BOOTCMD)
1175                         goto out;
1176                 udelay(TYPHOON_UDELAY);
1177         }
1178
1179         err = -ETIMEDOUT;
1180
1181 out:
1182         iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1183         return err;
1184 }
1185
1186 #define shared_offset(x)        offsetof(struct typhoon_shared, x)
1187
1188 static void
1189 typhoon_init_interface(struct typhoon *tp)
1190 {
1191         struct typhoon_interface *iface = &tp->shared->iface;
1192         dma_addr_t shared_dma;
1193
1194         memset(tp->shared, 0, sizeof(struct typhoon_shared));
1195
1196         /* The *Hi members of iface are all init'd to zero by the memset().
1197          */
1198         shared_dma = tp->shared_dma + shared_offset(indexes);
1199         iface->ringIndex = cpu_to_le32(shared_dma);
1200
1201         shared_dma = tp->shared_dma + shared_offset(txLo);
1202         iface->txLoAddr = cpu_to_le32(shared_dma);
1203         iface->txLoSize = cpu_to_le32(TXLO_ENTRIES * sizeof(struct tx_desc));
1204
1205         shared_dma = tp->shared_dma + shared_offset(txHi);
1206         iface->txHiAddr = cpu_to_le32(shared_dma);
1207         iface->txHiSize = cpu_to_le32(TXHI_ENTRIES * sizeof(struct tx_desc));
1208
1209         shared_dma = tp->shared_dma + shared_offset(rxBuff);
1210         iface->rxBuffAddr = cpu_to_le32(shared_dma);
1211         iface->rxBuffSize = cpu_to_le32(RXFREE_ENTRIES *
1212                                         sizeof(struct rx_free));
1213
1214         shared_dma = tp->shared_dma + shared_offset(rxLo);
1215         iface->rxLoAddr = cpu_to_le32(shared_dma);
1216         iface->rxLoSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1217
1218         shared_dma = tp->shared_dma + shared_offset(rxHi);
1219         iface->rxHiAddr = cpu_to_le32(shared_dma);
1220         iface->rxHiSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1221
1222         shared_dma = tp->shared_dma + shared_offset(cmd);
1223         iface->cmdAddr = cpu_to_le32(shared_dma);
1224         iface->cmdSize = cpu_to_le32(COMMAND_RING_SIZE);
1225
1226         shared_dma = tp->shared_dma + shared_offset(resp);
1227         iface->respAddr = cpu_to_le32(shared_dma);
1228         iface->respSize = cpu_to_le32(RESPONSE_RING_SIZE);
1229
1230         shared_dma = tp->shared_dma + shared_offset(zeroWord);
1231         iface->zeroAddr = cpu_to_le32(shared_dma);
1232
1233         tp->indexes = &tp->shared->indexes;
1234         tp->txLoRing.ringBase = (u8 *) tp->shared->txLo;
1235         tp->txHiRing.ringBase = (u8 *) tp->shared->txHi;
1236         tp->rxLoRing.ringBase = (u8 *) tp->shared->rxLo;
1237         tp->rxHiRing.ringBase = (u8 *) tp->shared->rxHi;
1238         tp->rxBuffRing.ringBase = (u8 *) tp->shared->rxBuff;
1239         tp->cmdRing.ringBase = (u8 *) tp->shared->cmd;
1240         tp->respRing.ringBase = (u8 *) tp->shared->resp;
1241
1242         tp->txLoRing.writeRegister = TYPHOON_REG_TX_LO_READY;
1243         tp->txHiRing.writeRegister = TYPHOON_REG_TX_HI_READY;
1244
1245         tp->txlo_dma_addr = le32_to_cpu(iface->txLoAddr);
1246         tp->card_state = Sleeping;
1247
1248         tp->offload = TYPHOON_OFFLOAD_IP_CHKSUM | TYPHOON_OFFLOAD_TCP_CHKSUM;
1249         tp->offload |= TYPHOON_OFFLOAD_UDP_CHKSUM | TSO_OFFLOAD_ON;
1250         tp->offload |= TYPHOON_OFFLOAD_VLAN;
1251
1252         spin_lock_init(&tp->command_lock);
1253
1254         /* Force the writes to the shared memory area out before continuing. */
1255         wmb();
1256 }
1257
1258 static void
1259 typhoon_init_rings(struct typhoon *tp)
1260 {
1261         memset(tp->indexes, 0, sizeof(struct typhoon_indexes));
1262
1263         tp->txLoRing.lastWrite = 0;
1264         tp->txHiRing.lastWrite = 0;
1265         tp->rxLoRing.lastWrite = 0;
1266         tp->rxHiRing.lastWrite = 0;
1267         tp->rxBuffRing.lastWrite = 0;
1268         tp->cmdRing.lastWrite = 0;
1269         tp->respRing.lastWrite = 0;
1270
1271         tp->txLoRing.lastRead = 0;
1272         tp->txHiRing.lastRead = 0;
1273 }
1274
1275 static const struct firmware *typhoon_fw;
1276
1277 static int
1278 typhoon_request_firmware(struct typhoon *tp)
1279 {
1280         const struct typhoon_file_header *fHdr;
1281         const struct typhoon_section_header *sHdr;
1282         const u8 *image_data;
1283         u32 numSections;
1284         u32 section_len;
1285         u32 remaining;
1286         int err;
1287
1288         if (typhoon_fw)
1289                 return 0;
1290
1291         err = request_firmware(&typhoon_fw, FIRMWARE_NAME, &tp->pdev->dev);
1292         if (err) {
1293                 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
1294                            FIRMWARE_NAME);
1295                 return err;
1296         }
1297
1298         image_data = (u8 *) typhoon_fw->data;
1299         remaining = typhoon_fw->size;
1300         if (remaining < sizeof(struct typhoon_file_header))
1301                 goto invalid_fw;
1302
1303         fHdr = (struct typhoon_file_header *) image_data;
1304         if (memcmp(fHdr->tag, "TYPHOON", 8))
1305                 goto invalid_fw;
1306
1307         numSections = le32_to_cpu(fHdr->numSections);
1308         image_data += sizeof(struct typhoon_file_header);
1309         remaining -= sizeof(struct typhoon_file_header);
1310
1311         while (numSections--) {
1312                 if (remaining < sizeof(struct typhoon_section_header))
1313                         goto invalid_fw;
1314
1315                 sHdr = (struct typhoon_section_header *) image_data;
1316                 image_data += sizeof(struct typhoon_section_header);
1317                 section_len = le32_to_cpu(sHdr->len);
1318
1319                 if (remaining < section_len)
1320                         goto invalid_fw;
1321
1322                 image_data += section_len;
1323                 remaining -= section_len;
1324         }
1325
1326         return 0;
1327
1328 invalid_fw:
1329         netdev_err(tp->dev, "Invalid firmware image\n");
1330         release_firmware(typhoon_fw);
1331         typhoon_fw = NULL;
1332         return -EINVAL;
1333 }
1334
1335 static int
1336 typhoon_download_firmware(struct typhoon *tp)
1337 {
1338         void __iomem *ioaddr = tp->ioaddr;
1339         struct pci_dev *pdev = tp->pdev;
1340         const struct typhoon_file_header *fHdr;
1341         const struct typhoon_section_header *sHdr;
1342         const u8 *image_data;
1343         void *dpage;
1344         dma_addr_t dpage_dma;
1345         __sum16 csum;
1346         u32 irqEnabled;
1347         u32 irqMasked;
1348         u32 numSections;
1349         u32 section_len;
1350         u32 len;
1351         u32 load_addr;
1352         u32 hmac;
1353         int i;
1354         int err;
1355
1356         image_data = (u8 *) typhoon_fw->data;
1357         fHdr = (struct typhoon_file_header *) image_data;
1358
1359         /* Cannot just map the firmware image using pci_map_single() as
1360          * the firmware is vmalloc()'d and may not be physically contiguous,
1361          * so we allocate some consistent memory to copy the sections into.
1362          */
1363         err = -ENOMEM;
1364         dpage = pci_alloc_consistent(pdev, PAGE_SIZE, &dpage_dma);
1365         if(!dpage) {
1366                 netdev_err(tp->dev, "no DMA mem for firmware\n");
1367                 goto err_out;
1368         }
1369
1370         irqEnabled = ioread32(ioaddr + TYPHOON_REG_INTR_ENABLE);
1371         iowrite32(irqEnabled | TYPHOON_INTR_BOOTCMD,
1372                ioaddr + TYPHOON_REG_INTR_ENABLE);
1373         irqMasked = ioread32(ioaddr + TYPHOON_REG_INTR_MASK);
1374         iowrite32(irqMasked | TYPHOON_INTR_BOOTCMD,
1375                ioaddr + TYPHOON_REG_INTR_MASK);
1376
1377         err = -ETIMEDOUT;
1378         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
1379                 netdev_err(tp->dev, "card ready timeout\n");
1380                 goto err_out_irq;
1381         }
1382
1383         numSections = le32_to_cpu(fHdr->numSections);
1384         load_addr = le32_to_cpu(fHdr->startAddr);
1385
1386         iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1387         iowrite32(load_addr, ioaddr + TYPHOON_REG_DOWNLOAD_BOOT_ADDR);
1388         hmac = le32_to_cpu(fHdr->hmacDigest[0]);
1389         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_0);
1390         hmac = le32_to_cpu(fHdr->hmacDigest[1]);
1391         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_1);
1392         hmac = le32_to_cpu(fHdr->hmacDigest[2]);
1393         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_2);
1394         hmac = le32_to_cpu(fHdr->hmacDigest[3]);
1395         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_3);
1396         hmac = le32_to_cpu(fHdr->hmacDigest[4]);
1397         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_4);
1398         typhoon_post_pci_writes(ioaddr);
1399         iowrite32(TYPHOON_BOOTCMD_RUNTIME_IMAGE, ioaddr + TYPHOON_REG_COMMAND);
1400
1401         image_data += sizeof(struct typhoon_file_header);
1402
1403         /* The ioread32() in typhoon_wait_interrupt() will force the
1404          * last write to the command register to post, so
1405          * we don't need a typhoon_post_pci_writes() after it.
1406          */
1407         for(i = 0; i < numSections; i++) {
1408                 sHdr = (struct typhoon_section_header *) image_data;
1409                 image_data += sizeof(struct typhoon_section_header);
1410                 load_addr = le32_to_cpu(sHdr->startAddr);
1411                 section_len = le32_to_cpu(sHdr->len);
1412
1413                 while(section_len) {
1414                         len = min_t(u32, section_len, PAGE_SIZE);
1415
1416                         if(typhoon_wait_interrupt(ioaddr) < 0 ||
1417                            ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1418                            TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1419                                 netdev_err(tp->dev, "segment ready timeout\n");
1420                                 goto err_out_irq;
1421                         }
1422
1423                         /* Do an pseudo IPv4 checksum on the data -- first
1424                          * need to convert each u16 to cpu order before
1425                          * summing. Fortunately, due to the properties of
1426                          * the checksum, we can do this once, at the end.
1427                          */
1428                         csum = csum_fold(csum_partial_copy_nocheck(image_data,
1429                                                                    dpage, len,
1430                                                                    0));
1431
1432                         iowrite32(len, ioaddr + TYPHOON_REG_BOOT_LENGTH);
1433                         iowrite32(le16_to_cpu((__force __le16)csum),
1434                                         ioaddr + TYPHOON_REG_BOOT_CHECKSUM);
1435                         iowrite32(load_addr,
1436                                         ioaddr + TYPHOON_REG_BOOT_DEST_ADDR);
1437                         iowrite32(0, ioaddr + TYPHOON_REG_BOOT_DATA_HI);
1438                         iowrite32(dpage_dma, ioaddr + TYPHOON_REG_BOOT_DATA_LO);
1439                         typhoon_post_pci_writes(ioaddr);
1440                         iowrite32(TYPHOON_BOOTCMD_SEG_AVAILABLE,
1441                                         ioaddr + TYPHOON_REG_COMMAND);
1442
1443                         image_data += len;
1444                         load_addr += len;
1445                         section_len -= len;
1446                 }
1447         }
1448
1449         if(typhoon_wait_interrupt(ioaddr) < 0 ||
1450            ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1451            TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1452                 netdev_err(tp->dev, "final segment ready timeout\n");
1453                 goto err_out_irq;
1454         }
1455
1456         iowrite32(TYPHOON_BOOTCMD_DNLD_COMPLETE, ioaddr + TYPHOON_REG_COMMAND);
1457
1458         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1459                 netdev_err(tp->dev, "boot ready timeout, status 0x%0x\n",
1460                            ioread32(ioaddr + TYPHOON_REG_STATUS));
1461                 goto err_out_irq;
1462         }
1463
1464         err = 0;
1465
1466 err_out_irq:
1467         iowrite32(irqMasked, ioaddr + TYPHOON_REG_INTR_MASK);
1468         iowrite32(irqEnabled, ioaddr + TYPHOON_REG_INTR_ENABLE);
1469
1470         pci_free_consistent(pdev, PAGE_SIZE, dpage, dpage_dma);
1471
1472 err_out:
1473         return err;
1474 }
1475
1476 static int
1477 typhoon_boot_3XP(struct typhoon *tp, u32 initial_status)
1478 {
1479         void __iomem *ioaddr = tp->ioaddr;
1480
1481         if(typhoon_wait_status(ioaddr, initial_status) < 0) {
1482                 netdev_err(tp->dev, "boot ready timeout\n");
1483                 goto out_timeout;
1484         }
1485
1486         iowrite32(0, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_HI);
1487         iowrite32(tp->shared_dma, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_LO);
1488         typhoon_post_pci_writes(ioaddr);
1489         iowrite32(TYPHOON_BOOTCMD_REG_BOOT_RECORD,
1490                                 ioaddr + TYPHOON_REG_COMMAND);
1491
1492         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_RUNNING) < 0) {
1493                 netdev_err(tp->dev, "boot finish timeout (status 0x%x)\n",
1494                            ioread32(ioaddr + TYPHOON_REG_STATUS));
1495                 goto out_timeout;
1496         }
1497
1498         /* Clear the Transmit and Command ready registers
1499          */
1500         iowrite32(0, ioaddr + TYPHOON_REG_TX_HI_READY);
1501         iowrite32(0, ioaddr + TYPHOON_REG_CMD_READY);
1502         iowrite32(0, ioaddr + TYPHOON_REG_TX_LO_READY);
1503         typhoon_post_pci_writes(ioaddr);
1504         iowrite32(TYPHOON_BOOTCMD_BOOT, ioaddr + TYPHOON_REG_COMMAND);
1505
1506         return 0;
1507
1508 out_timeout:
1509         return -ETIMEDOUT;
1510 }
1511
1512 static u32
1513 typhoon_clean_tx(struct typhoon *tp, struct transmit_ring *txRing,
1514                         volatile __le32 * index)
1515 {
1516         u32 lastRead = txRing->lastRead;
1517         struct tx_desc *tx;
1518         dma_addr_t skb_dma;
1519         int dma_len;
1520         int type;
1521
1522         while(lastRead != le32_to_cpu(*index)) {
1523                 tx = (struct tx_desc *) (txRing->ringBase + lastRead);
1524                 type = tx->flags & TYPHOON_TYPE_MASK;
1525
1526                 if(type == TYPHOON_TX_DESC) {
1527                         /* This tx_desc describes a packet.
1528                          */
1529                         unsigned long ptr = tx->tx_addr;
1530                         struct sk_buff *skb = (struct sk_buff *) ptr;
1531                         dev_kfree_skb_irq(skb);
1532                 } else if(type == TYPHOON_FRAG_DESC) {
1533                         /* This tx_desc describes a memory mapping. Free it.
1534                          */
1535                         skb_dma = (dma_addr_t) le32_to_cpu(tx->frag.addr);
1536                         dma_len = le16_to_cpu(tx->len);
1537                         pci_unmap_single(tp->pdev, skb_dma, dma_len,
1538                                        PCI_DMA_TODEVICE);
1539                 }
1540
1541                 tx->flags = 0;
1542                 typhoon_inc_tx_index(&lastRead, 1);
1543         }
1544
1545         return lastRead;
1546 }
1547
1548 static void
1549 typhoon_tx_complete(struct typhoon *tp, struct transmit_ring *txRing,
1550                         volatile __le32 * index)
1551 {
1552         u32 lastRead;
1553         int numDesc = MAX_SKB_FRAGS + 1;
1554
1555         /* This will need changing if we start to use the Hi Tx ring. */
1556         lastRead = typhoon_clean_tx(tp, txRing, index);
1557         if(netif_queue_stopped(tp->dev) && typhoon_num_free(txRing->lastWrite,
1558                                 lastRead, TXLO_ENTRIES) > (numDesc + 2))
1559                 netif_wake_queue(tp->dev);
1560
1561         txRing->lastRead = lastRead;
1562         smp_wmb();
1563 }
1564
1565 static void
1566 typhoon_recycle_rx_skb(struct typhoon *tp, u32 idx)
1567 {
1568         struct typhoon_indexes *indexes = tp->indexes;
1569         struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1570         struct basic_ring *ring = &tp->rxBuffRing;
1571         struct rx_free *r;
1572
1573         if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1574                                 le32_to_cpu(indexes->rxBuffCleared)) {
1575                 /* no room in ring, just drop the skb
1576                  */
1577                 dev_kfree_skb_any(rxb->skb);
1578                 rxb->skb = NULL;
1579                 return;
1580         }
1581
1582         r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1583         typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1584         r->virtAddr = idx;
1585         r->physAddr = cpu_to_le32(rxb->dma_addr);
1586
1587         /* Tell the card about it */
1588         wmb();
1589         indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1590 }
1591
1592 static int
1593 typhoon_alloc_rx_skb(struct typhoon *tp, u32 idx)
1594 {
1595         struct typhoon_indexes *indexes = tp->indexes;
1596         struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1597         struct basic_ring *ring = &tp->rxBuffRing;
1598         struct rx_free *r;
1599         struct sk_buff *skb;
1600         dma_addr_t dma_addr;
1601
1602         rxb->skb = NULL;
1603
1604         if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1605                                 le32_to_cpu(indexes->rxBuffCleared))
1606                 return -ENOMEM;
1607
1608         skb = dev_alloc_skb(PKT_BUF_SZ);
1609         if(!skb)
1610                 return -ENOMEM;
1611
1612 #if 0
1613         /* Please, 3com, fix the firmware to allow DMA to a unaligned
1614          * address! Pretty please?
1615          */
1616         skb_reserve(skb, 2);
1617 #endif
1618
1619         skb->dev = tp->dev;
1620         dma_addr = pci_map_single(tp->pdev, skb->data,
1621                                   PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
1622
1623         /* Since no card does 64 bit DAC, the high bits will never
1624          * change from zero.
1625          */
1626         r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1627         typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1628         r->virtAddr = idx;
1629         r->physAddr = cpu_to_le32(dma_addr);
1630         rxb->skb = skb;
1631         rxb->dma_addr = dma_addr;
1632
1633         /* Tell the card about it */
1634         wmb();
1635         indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1636         return 0;
1637 }
1638
1639 static int
1640 typhoon_rx(struct typhoon *tp, struct basic_ring *rxRing, volatile __le32 * ready,
1641            volatile __le32 * cleared, int budget)
1642 {
1643         struct rx_desc *rx;
1644         struct sk_buff *skb, *new_skb;
1645         struct rxbuff_ent *rxb;
1646         dma_addr_t dma_addr;
1647         u32 local_ready;
1648         u32 rxaddr;
1649         int pkt_len;
1650         u32 idx;
1651         __le32 csum_bits;
1652         int received;
1653
1654         received = 0;
1655         local_ready = le32_to_cpu(*ready);
1656         rxaddr = le32_to_cpu(*cleared);
1657         while(rxaddr != local_ready && budget > 0) {
1658                 rx = (struct rx_desc *) (rxRing->ringBase + rxaddr);
1659                 idx = rx->addr;
1660                 rxb = &tp->rxbuffers[idx];
1661                 skb = rxb->skb;
1662                 dma_addr = rxb->dma_addr;
1663
1664                 typhoon_inc_rx_index(&rxaddr, 1);
1665
1666                 if(rx->flags & TYPHOON_RX_ERROR) {
1667                         typhoon_recycle_rx_skb(tp, idx);
1668                         continue;
1669                 }
1670
1671                 pkt_len = le16_to_cpu(rx->frameLen);
1672
1673                 if(pkt_len < rx_copybreak &&
1674                    (new_skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1675                         skb_reserve(new_skb, 2);
1676                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr,
1677                                                     PKT_BUF_SZ,
1678                                                     PCI_DMA_FROMDEVICE);
1679                         skb_copy_to_linear_data(new_skb, skb->data, pkt_len);
1680                         pci_dma_sync_single_for_device(tp->pdev, dma_addr,
1681                                                        PKT_BUF_SZ,
1682                                                        PCI_DMA_FROMDEVICE);
1683                         skb_put(new_skb, pkt_len);
1684                         typhoon_recycle_rx_skb(tp, idx);
1685                 } else {
1686                         new_skb = skb;
1687                         skb_put(new_skb, pkt_len);
1688                         pci_unmap_single(tp->pdev, dma_addr, PKT_BUF_SZ,
1689                                        PCI_DMA_FROMDEVICE);
1690                         typhoon_alloc_rx_skb(tp, idx);
1691                 }
1692                 new_skb->protocol = eth_type_trans(new_skb, tp->dev);
1693                 csum_bits = rx->rxStatus & (TYPHOON_RX_IP_CHK_GOOD |
1694                         TYPHOON_RX_UDP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD);
1695                 if(csum_bits ==
1696                    (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD) ||
1697                    csum_bits ==
1698                    (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_UDP_CHK_GOOD)) {
1699                         new_skb->ip_summed = CHECKSUM_UNNECESSARY;
1700                 } else
1701                         skb_checksum_none_assert(new_skb);
1702
1703                 if (rx->rxStatus & TYPHOON_RX_VLAN)
1704                         __vlan_hwaccel_put_tag(new_skb,
1705                                                ntohl(rx->vlanTag) & 0xffff);
1706                 netif_receive_skb(new_skb);
1707
1708                 received++;
1709                 budget--;
1710         }
1711         *cleared = cpu_to_le32(rxaddr);
1712
1713         return received;
1714 }
1715
1716 static void
1717 typhoon_fill_free_ring(struct typhoon *tp)
1718 {
1719         u32 i;
1720
1721         for(i = 0; i < RXENT_ENTRIES; i++) {
1722                 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1723                 if(rxb->skb)
1724                         continue;
1725                 if(typhoon_alloc_rx_skb(tp, i) < 0)
1726                         break;
1727         }
1728 }
1729
1730 static int
1731 typhoon_poll(struct napi_struct *napi, int budget)
1732 {
1733         struct typhoon *tp = container_of(napi, struct typhoon, napi);
1734         struct typhoon_indexes *indexes = tp->indexes;
1735         int work_done;
1736
1737         rmb();
1738         if(!tp->awaiting_resp && indexes->respReady != indexes->respCleared)
1739                         typhoon_process_response(tp, 0, NULL);
1740
1741         if(le32_to_cpu(indexes->txLoCleared) != tp->txLoRing.lastRead)
1742                 typhoon_tx_complete(tp, &tp->txLoRing, &indexes->txLoCleared);
1743
1744         work_done = 0;
1745
1746         if(indexes->rxHiCleared != indexes->rxHiReady) {
1747                 work_done += typhoon_rx(tp, &tp->rxHiRing, &indexes->rxHiReady,
1748                                         &indexes->rxHiCleared, budget);
1749         }
1750
1751         if(indexes->rxLoCleared != indexes->rxLoReady) {
1752                 work_done += typhoon_rx(tp, &tp->rxLoRing, &indexes->rxLoReady,
1753                                         &indexes->rxLoCleared, budget - work_done);
1754         }
1755
1756         if(le32_to_cpu(indexes->rxBuffCleared) == tp->rxBuffRing.lastWrite) {
1757                 /* rxBuff ring is empty, try to fill it. */
1758                 typhoon_fill_free_ring(tp);
1759         }
1760
1761         if (work_done < budget) {
1762                 napi_complete(napi);
1763                 iowrite32(TYPHOON_INTR_NONE,
1764                                 tp->ioaddr + TYPHOON_REG_INTR_MASK);
1765                 typhoon_post_pci_writes(tp->ioaddr);
1766         }
1767
1768         return work_done;
1769 }
1770
1771 static irqreturn_t
1772 typhoon_interrupt(int irq, void *dev_instance)
1773 {
1774         struct net_device *dev = dev_instance;
1775         struct typhoon *tp = netdev_priv(dev);
1776         void __iomem *ioaddr = tp->ioaddr;
1777         u32 intr_status;
1778
1779         intr_status = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
1780         if(!(intr_status & TYPHOON_INTR_HOST_INT))
1781                 return IRQ_NONE;
1782
1783         iowrite32(intr_status, ioaddr + TYPHOON_REG_INTR_STATUS);
1784
1785         if (napi_schedule_prep(&tp->napi)) {
1786                 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
1787                 typhoon_post_pci_writes(ioaddr);
1788                 __napi_schedule(&tp->napi);
1789         } else {
1790                 netdev_err(dev, "Error, poll already scheduled\n");
1791         }
1792         return IRQ_HANDLED;
1793 }
1794
1795 static void
1796 typhoon_free_rx_rings(struct typhoon *tp)
1797 {
1798         u32 i;
1799
1800         for(i = 0; i < RXENT_ENTRIES; i++) {
1801                 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1802                 if(rxb->skb) {
1803                         pci_unmap_single(tp->pdev, rxb->dma_addr, PKT_BUF_SZ,
1804                                        PCI_DMA_FROMDEVICE);
1805                         dev_kfree_skb(rxb->skb);
1806                         rxb->skb = NULL;
1807                 }
1808         }
1809 }
1810
1811 static int
1812 typhoon_sleep(struct typhoon *tp, pci_power_t state, __le16 events)
1813 {
1814         struct pci_dev *pdev = tp->pdev;
1815         void __iomem *ioaddr = tp->ioaddr;
1816         struct cmd_desc xp_cmd;
1817         int err;
1818
1819         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_ENABLE_WAKE_EVENTS);
1820         xp_cmd.parm1 = events;
1821         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1822         if(err < 0) {
1823                 netdev_err(tp->dev, "typhoon_sleep(): wake events cmd err %d\n",
1824                            err);
1825                 return err;
1826         }
1827
1828         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_GOTO_SLEEP);
1829         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1830         if(err < 0) {
1831                 netdev_err(tp->dev, "typhoon_sleep(): sleep cmd err %d\n", err);
1832                 return err;
1833         }
1834
1835         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_SLEEPING) < 0)
1836                 return -ETIMEDOUT;
1837
1838         /* Since we cannot monitor the status of the link while sleeping,
1839          * tell the world it went away.
1840          */
1841         netif_carrier_off(tp->dev);
1842
1843         pci_enable_wake(tp->pdev, state, 1);
1844         pci_disable_device(pdev);
1845         return pci_set_power_state(pdev, state);
1846 }
1847
1848 static int
1849 typhoon_wakeup(struct typhoon *tp, int wait_type)
1850 {
1851         struct pci_dev *pdev = tp->pdev;
1852         void __iomem *ioaddr = tp->ioaddr;
1853
1854         pci_set_power_state(pdev, PCI_D0);
1855         pci_restore_state(pdev);
1856
1857         /* Post 2.x.x versions of the Sleep Image require a reset before
1858          * we can download the Runtime Image. But let's not make users of
1859          * the old firmware pay for the reset.
1860          */
1861         iowrite32(TYPHOON_BOOTCMD_WAKEUP, ioaddr + TYPHOON_REG_COMMAND);
1862         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0 ||
1863                         (tp->capabilities & TYPHOON_WAKEUP_NEEDS_RESET))
1864                 return typhoon_reset(ioaddr, wait_type);
1865
1866         return 0;
1867 }
1868
1869 static int
1870 typhoon_start_runtime(struct typhoon *tp)
1871 {
1872         struct net_device *dev = tp->dev;
1873         void __iomem *ioaddr = tp->ioaddr;
1874         struct cmd_desc xp_cmd;
1875         int err;
1876
1877         typhoon_init_rings(tp);
1878         typhoon_fill_free_ring(tp);
1879
1880         err = typhoon_download_firmware(tp);
1881         if(err < 0) {
1882                 netdev_err(tp->dev, "cannot load runtime on 3XP\n");
1883                 goto error_out;
1884         }
1885
1886         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1887                 netdev_err(tp->dev, "cannot boot 3XP\n");
1888                 err = -EIO;
1889                 goto error_out;
1890         }
1891
1892         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAX_PKT_SIZE);
1893         xp_cmd.parm1 = cpu_to_le16(PKT_BUF_SZ);
1894         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1895         if(err < 0)
1896                 goto error_out;
1897
1898         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
1899         xp_cmd.parm1 = cpu_to_le16(ntohs(*(__be16 *)&dev->dev_addr[0]));
1900         xp_cmd.parm2 = cpu_to_le32(ntohl(*(__be32 *)&dev->dev_addr[2]));
1901         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1902         if(err < 0)
1903                 goto error_out;
1904
1905         /* Disable IRQ coalescing -- we can reenable it when 3Com gives
1906          * us some more information on how to control it.
1907          */
1908         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_IRQ_COALESCE_CTRL);
1909         xp_cmd.parm1 = 0;
1910         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1911         if(err < 0)
1912                 goto error_out;
1913
1914         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1915         xp_cmd.parm1 = tp->xcvr_select;
1916         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1917         if(err < 0)
1918                 goto error_out;
1919
1920         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_VLAN_TYPE_WRITE);
1921         xp_cmd.parm1 = cpu_to_le16(ETH_P_8021Q);
1922         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1923         if(err < 0)
1924                 goto error_out;
1925
1926         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_OFFLOAD_TASKS);
1927         xp_cmd.parm2 = tp->offload;
1928         xp_cmd.parm3 = tp->offload;
1929         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1930         if(err < 0)
1931                 goto error_out;
1932
1933         typhoon_set_rx_mode(dev);
1934
1935         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_ENABLE);
1936         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1937         if(err < 0)
1938                 goto error_out;
1939
1940         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_ENABLE);
1941         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1942         if(err < 0)
1943                 goto error_out;
1944
1945         tp->card_state = Running;
1946         smp_wmb();
1947
1948         iowrite32(TYPHOON_INTR_ENABLE_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
1949         iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_MASK);
1950         typhoon_post_pci_writes(ioaddr);
1951
1952         return 0;
1953
1954 error_out:
1955         typhoon_reset(ioaddr, WaitNoSleep);
1956         typhoon_free_rx_rings(tp);
1957         typhoon_init_rings(tp);
1958         return err;
1959 }
1960
1961 static int
1962 typhoon_stop_runtime(struct typhoon *tp, int wait_type)
1963 {
1964         struct typhoon_indexes *indexes = tp->indexes;
1965         struct transmit_ring *txLo = &tp->txLoRing;
1966         void __iomem *ioaddr = tp->ioaddr;
1967         struct cmd_desc xp_cmd;
1968         int i;
1969
1970         /* Disable interrupts early, since we can't schedule a poll
1971          * when called with !netif_running(). This will be posted
1972          * when we force the posting of the command.
1973          */
1974         iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
1975
1976         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_DISABLE);
1977         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1978
1979         /* Wait 1/2 sec for any outstanding transmits to occur
1980          * We'll cleanup after the reset if this times out.
1981          */
1982         for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
1983                 if(indexes->txLoCleared == cpu_to_le32(txLo->lastWrite))
1984                         break;
1985                 udelay(TYPHOON_UDELAY);
1986         }
1987
1988         if(i == TYPHOON_WAIT_TIMEOUT)
1989                 netdev_err(tp->dev, "halt timed out waiting for Tx to complete\n");
1990
1991         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_DISABLE);
1992         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1993
1994         /* save the statistics so when we bring the interface up again,
1995          * the values reported to userspace are correct.
1996          */
1997         tp->card_state = Sleeping;
1998         smp_wmb();
1999         typhoon_do_get_stats(tp);
2000         memcpy(&tp->stats_saved, &tp->stats, sizeof(struct net_device_stats));
2001
2002         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_HALT);
2003         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2004
2005         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_HALTED) < 0)
2006                 netdev_err(tp->dev, "timed out waiting for 3XP to halt\n");
2007
2008         if(typhoon_reset(ioaddr, wait_type) < 0) {
2009                 netdev_err(tp->dev, "unable to reset 3XP\n");
2010                 return -ETIMEDOUT;
2011         }
2012
2013         /* cleanup any outstanding Tx packets */
2014         if(indexes->txLoCleared != cpu_to_le32(txLo->lastWrite)) {
2015                 indexes->txLoCleared = cpu_to_le32(txLo->lastWrite);
2016                 typhoon_clean_tx(tp, &tp->txLoRing, &indexes->txLoCleared);
2017         }
2018
2019         return 0;
2020 }
2021
2022 static void
2023 typhoon_tx_timeout(struct net_device *dev)
2024 {
2025         struct typhoon *tp = netdev_priv(dev);
2026
2027         if(typhoon_reset(tp->ioaddr, WaitNoSleep) < 0) {
2028                 netdev_warn(dev, "could not reset in tx timeout\n");
2029                 goto truly_dead;
2030         }
2031
2032         /* If we ever start using the Hi ring, it will need cleaning too */
2033         typhoon_clean_tx(tp, &tp->txLoRing, &tp->indexes->txLoCleared);
2034         typhoon_free_rx_rings(tp);
2035
2036         if(typhoon_start_runtime(tp) < 0) {
2037                 netdev_err(dev, "could not start runtime in tx timeout\n");
2038                 goto truly_dead;
2039         }
2040
2041         netif_wake_queue(dev);
2042         return;
2043
2044 truly_dead:
2045         /* Reset the hardware, and turn off carrier to avoid more timeouts */
2046         typhoon_reset(tp->ioaddr, NoWait);
2047         netif_carrier_off(dev);
2048 }
2049
2050 static int
2051 typhoon_open(struct net_device *dev)
2052 {
2053         struct typhoon *tp = netdev_priv(dev);
2054         int err;
2055
2056         err = typhoon_request_firmware(tp);
2057         if (err)
2058                 goto out;
2059
2060         err = typhoon_wakeup(tp, WaitSleep);
2061         if(err < 0) {
2062                 netdev_err(dev, "unable to wakeup device\n");
2063                 goto out_sleep;
2064         }
2065
2066         err = request_irq(dev->irq, typhoon_interrupt, IRQF_SHARED,
2067                                 dev->name, dev);
2068         if(err < 0)
2069                 goto out_sleep;
2070
2071         napi_enable(&tp->napi);
2072
2073         err = typhoon_start_runtime(tp);
2074         if(err < 0) {
2075                 napi_disable(&tp->napi);
2076                 goto out_irq;
2077         }
2078
2079         netif_start_queue(dev);
2080         return 0;
2081
2082 out_irq:
2083         free_irq(dev->irq, dev);
2084
2085 out_sleep:
2086         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2087                 netdev_err(dev, "unable to reboot into sleep img\n");
2088                 typhoon_reset(tp->ioaddr, NoWait);
2089                 goto out;
2090         }
2091
2092         if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2093                 netdev_err(dev, "unable to go back to sleep\n");
2094
2095 out:
2096         return err;
2097 }
2098
2099 static int
2100 typhoon_close(struct net_device *dev)
2101 {
2102         struct typhoon *tp = netdev_priv(dev);
2103
2104         netif_stop_queue(dev);
2105         napi_disable(&tp->napi);
2106
2107         if(typhoon_stop_runtime(tp, WaitSleep) < 0)
2108                 netdev_err(dev, "unable to stop runtime\n");
2109
2110         /* Make sure there is no irq handler running on a different CPU. */
2111         free_irq(dev->irq, dev);
2112
2113         typhoon_free_rx_rings(tp);
2114         typhoon_init_rings(tp);
2115
2116         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0)
2117                 netdev_err(dev, "unable to boot sleep image\n");
2118
2119         if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2120                 netdev_err(dev, "unable to put card to sleep\n");
2121
2122         return 0;
2123 }
2124
2125 #ifdef CONFIG_PM
2126 static int
2127 typhoon_resume(struct pci_dev *pdev)
2128 {
2129         struct net_device *dev = pci_get_drvdata(pdev);
2130         struct typhoon *tp = netdev_priv(dev);
2131
2132         /* If we're down, resume when we are upped.
2133          */
2134         if(!netif_running(dev))
2135                 return 0;
2136
2137         if(typhoon_wakeup(tp, WaitNoSleep) < 0) {
2138                 netdev_err(dev, "critical: could not wake up in resume\n");
2139                 goto reset;
2140         }
2141
2142         if(typhoon_start_runtime(tp) < 0) {
2143                 netdev_err(dev, "critical: could not start runtime in resume\n");
2144                 goto reset;
2145         }
2146
2147         netif_device_attach(dev);
2148         return 0;
2149
2150 reset:
2151         typhoon_reset(tp->ioaddr, NoWait);
2152         return -EBUSY;
2153 }
2154
2155 static int
2156 typhoon_suspend(struct pci_dev *pdev, pm_message_t state)
2157 {
2158         struct net_device *dev = pci_get_drvdata(pdev);
2159         struct typhoon *tp = netdev_priv(dev);
2160         struct cmd_desc xp_cmd;
2161
2162         /* If we're down, we're already suspended.
2163          */
2164         if(!netif_running(dev))
2165                 return 0;
2166
2167         /* TYPHOON_OFFLOAD_VLAN is always on now, so this doesn't work */
2168         if(tp->wol_events & TYPHOON_WAKE_MAGIC_PKT)
2169                 netdev_warn(dev, "cannot do WAKE_MAGIC with VLAN offloading\n");
2170
2171         netif_device_detach(dev);
2172
2173         if(typhoon_stop_runtime(tp, WaitNoSleep) < 0) {
2174                 netdev_err(dev, "unable to stop runtime\n");
2175                 goto need_resume;
2176         }
2177
2178         typhoon_free_rx_rings(tp);
2179         typhoon_init_rings(tp);
2180
2181         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2182                 netdev_err(dev, "unable to boot sleep image\n");
2183                 goto need_resume;
2184         }
2185
2186         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
2187         xp_cmd.parm1 = cpu_to_le16(ntohs(*(__be16 *)&dev->dev_addr[0]));
2188         xp_cmd.parm2 = cpu_to_le32(ntohl(*(__be32 *)&dev->dev_addr[2]));
2189         if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2190                 netdev_err(dev, "unable to set mac address in suspend\n");
2191                 goto need_resume;
2192         }
2193
2194         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
2195         xp_cmd.parm1 = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
2196         if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2197                 netdev_err(dev, "unable to set rx filter in suspend\n");
2198                 goto need_resume;
2199         }
2200
2201         if(typhoon_sleep(tp, pci_choose_state(pdev, state), tp->wol_events) < 0) {
2202                 netdev_err(dev, "unable to put card to sleep\n");
2203                 goto need_resume;
2204         }
2205
2206         return 0;
2207
2208 need_resume:
2209         typhoon_resume(pdev);
2210         return -EBUSY;
2211 }
2212 #endif
2213
2214 static int __devinit
2215 typhoon_test_mmio(struct pci_dev *pdev)
2216 {
2217         void __iomem *ioaddr = pci_iomap(pdev, 1, 128);
2218         int mode = 0;
2219         u32 val;
2220
2221         if(!ioaddr)
2222                 goto out;
2223
2224         if(ioread32(ioaddr + TYPHOON_REG_STATUS) !=
2225                                 TYPHOON_STATUS_WAITING_FOR_HOST)
2226                 goto out_unmap;
2227
2228         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2229         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2230         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
2231
2232         /* Ok, see if we can change our interrupt status register by
2233          * sending ourselves an interrupt. If so, then MMIO works.
2234          * The 50usec delay is arbitrary -- it could probably be smaller.
2235          */
2236         val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2237         if((val & TYPHOON_INTR_SELF) == 0) {
2238                 iowrite32(1, ioaddr + TYPHOON_REG_SELF_INTERRUPT);
2239                 ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2240                 udelay(50);
2241                 val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2242                 if(val & TYPHOON_INTR_SELF)
2243                         mode = 1;
2244         }
2245
2246         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2247         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2248         iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
2249         ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2250
2251 out_unmap:
2252         pci_iounmap(pdev, ioaddr);
2253
2254 out:
2255         if(!mode)
2256                 pr_info("%s: falling back to port IO\n", pci_name(pdev));
2257         return mode;
2258 }
2259
2260 static const struct net_device_ops typhoon_netdev_ops = {
2261         .ndo_open               = typhoon_open,
2262         .ndo_stop               = typhoon_close,
2263         .ndo_start_xmit         = typhoon_start_tx,
2264         .ndo_set_rx_mode        = typhoon_set_rx_mode,
2265         .ndo_tx_timeout         = typhoon_tx_timeout,
2266         .ndo_get_stats          = typhoon_get_stats,
2267         .ndo_validate_addr      = eth_validate_addr,
2268         .ndo_set_mac_address    = typhoon_set_mac_address,
2269         .ndo_change_mtu         = eth_change_mtu,
2270 };
2271
2272 static int __devinit
2273 typhoon_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2274 {
2275         struct net_device *dev;
2276         struct typhoon *tp;
2277         int card_id = (int) ent->driver_data;
2278         void __iomem *ioaddr;
2279         void *shared;
2280         dma_addr_t shared_dma;
2281         struct cmd_desc xp_cmd;
2282         struct resp_desc xp_resp[3];
2283         int err = 0;
2284         const char *err_msg;
2285
2286         dev = alloc_etherdev(sizeof(*tp));
2287         if(dev == NULL) {
2288                 err_msg = "unable to alloc new net device";
2289                 err = -ENOMEM;
2290                 goto error_out;
2291         }
2292         SET_NETDEV_DEV(dev, &pdev->dev);
2293
2294         err = pci_enable_device(pdev);
2295         if(err < 0) {
2296                 err_msg = "unable to enable device";
2297                 goto error_out_dev;
2298         }
2299
2300         err = pci_set_mwi(pdev);
2301         if(err < 0) {
2302                 err_msg = "unable to set MWI";
2303                 goto error_out_disable;
2304         }
2305
2306         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2307         if(err < 0) {
2308                 err_msg = "No usable DMA configuration";
2309                 goto error_out_mwi;
2310         }
2311
2312         /* sanity checks on IO and MMIO BARs
2313          */
2314         if(!(pci_resource_flags(pdev, 0) & IORESOURCE_IO)) {
2315                 err_msg = "region #1 not a PCI IO resource, aborting";
2316                 err = -ENODEV;
2317                 goto error_out_mwi;
2318         }
2319         if(pci_resource_len(pdev, 0) < 128) {
2320                 err_msg = "Invalid PCI IO region size, aborting";
2321                 err = -ENODEV;
2322                 goto error_out_mwi;
2323         }
2324         if(!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
2325                 err_msg = "region #1 not a PCI MMIO resource, aborting";
2326                 err = -ENODEV;
2327                 goto error_out_mwi;
2328         }
2329         if(pci_resource_len(pdev, 1) < 128) {
2330                 err_msg = "Invalid PCI MMIO region size, aborting";
2331                 err = -ENODEV;
2332                 goto error_out_mwi;
2333         }
2334
2335         err = pci_request_regions(pdev, KBUILD_MODNAME);
2336         if(err < 0) {
2337                 err_msg = "could not request regions";
2338                 goto error_out_mwi;
2339         }
2340
2341         /* map our registers
2342          */
2343         if(use_mmio != 0 && use_mmio != 1)
2344                 use_mmio = typhoon_test_mmio(pdev);
2345
2346         ioaddr = pci_iomap(pdev, use_mmio, 128);
2347         if (!ioaddr) {
2348                 err_msg = "cannot remap registers, aborting";
2349                 err = -EIO;
2350                 goto error_out_regions;
2351         }
2352
2353         /* allocate pci dma space for rx and tx descriptor rings
2354          */
2355         shared = pci_alloc_consistent(pdev, sizeof(struct typhoon_shared),
2356                                       &shared_dma);
2357         if(!shared) {
2358                 err_msg = "could not allocate DMA memory";
2359                 err = -ENOMEM;
2360                 goto error_out_remap;
2361         }
2362
2363         dev->irq = pdev->irq;
2364         tp = netdev_priv(dev);
2365         tp->shared = shared;
2366         tp->shared_dma = shared_dma;
2367         tp->pdev = pdev;
2368         tp->tx_pdev = pdev;
2369         tp->ioaddr = ioaddr;
2370         tp->tx_ioaddr = ioaddr;
2371         tp->dev = dev;
2372
2373         /* Init sequence:
2374          * 1) Reset the adapter to clear any bad juju
2375          * 2) Reload the sleep image
2376          * 3) Boot the sleep image
2377          * 4) Get the hardware address.
2378          * 5) Put the card to sleep.
2379          */
2380         if (typhoon_reset(ioaddr, WaitSleep) < 0) {
2381                 err_msg = "could not reset 3XP";
2382                 err = -EIO;
2383                 goto error_out_dma;
2384         }
2385
2386         /* Now that we've reset the 3XP and are sure it's not going to
2387          * write all over memory, enable bus mastering, and save our
2388          * state for resuming after a suspend.
2389          */
2390         pci_set_master(pdev);
2391         pci_save_state(pdev);
2392
2393         typhoon_init_interface(tp);
2394         typhoon_init_rings(tp);
2395
2396         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2397                 err_msg = "cannot boot 3XP sleep image";
2398                 err = -EIO;
2399                 goto error_out_reset;
2400         }
2401
2402         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_MAC_ADDRESS);
2403         if(typhoon_issue_command(tp, 1, &xp_cmd, 1, xp_resp) < 0) {
2404                 err_msg = "cannot read MAC address";
2405                 err = -EIO;
2406                 goto error_out_reset;
2407         }
2408
2409         *(__be16 *)&dev->dev_addr[0] = htons(le16_to_cpu(xp_resp[0].parm1));
2410         *(__be32 *)&dev->dev_addr[2] = htonl(le32_to_cpu(xp_resp[0].parm2));
2411
2412         if(!is_valid_ether_addr(dev->dev_addr)) {
2413                 err_msg = "Could not obtain valid ethernet address, aborting";
2414                 goto error_out_reset;
2415         }
2416
2417         /* Read the Sleep Image version last, so the response is valid
2418          * later when we print out the version reported.
2419          */
2420         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
2421         if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
2422                 err_msg = "Could not get Sleep Image version";
2423                 goto error_out_reset;
2424         }
2425
2426         tp->capabilities = typhoon_card_info[card_id].capabilities;
2427         tp->xcvr_select = TYPHOON_XCVR_AUTONEG;
2428
2429         /* Typhoon 1.0 Sleep Images return one response descriptor to the
2430          * READ_VERSIONS command. Those versions are OK after waking up
2431          * from sleep without needing a reset. Typhoon 1.1+ Sleep Images
2432          * seem to need a little extra help to get started. Since we don't
2433          * know how to nudge it along, just kick it.
2434          */
2435         if(xp_resp[0].numDesc != 0)
2436                 tp->capabilities |= TYPHOON_WAKEUP_NEEDS_RESET;
2437
2438         if(typhoon_sleep(tp, PCI_D3hot, 0) < 0) {
2439                 err_msg = "cannot put adapter to sleep";
2440                 err = -EIO;
2441                 goto error_out_reset;
2442         }
2443
2444         /* The chip-specific entries in the device structure. */
2445         dev->netdev_ops         = &typhoon_netdev_ops;
2446         netif_napi_add(dev, &tp->napi, typhoon_poll, 16);
2447         dev->watchdog_timeo     = TX_TIMEOUT;
2448
2449         SET_ETHTOOL_OPS(dev, &typhoon_ethtool_ops);
2450
2451         /* We can handle scatter gather, up to 16 entries, and
2452          * we can do IP checksumming (only version 4, doh...)
2453          *
2454          * There's no way to turn off the RX VLAN offloading and stripping
2455          * on the current 3XP firmware -- it does not respect the offload
2456          * settings -- so we only allow the user to toggle the TX processing.
2457          */
2458         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
2459                 NETIF_F_HW_VLAN_TX;
2460         dev->features = dev->hw_features |
2461                 NETIF_F_HW_VLAN_RX | NETIF_F_RXCSUM;
2462
2463         if(register_netdev(dev) < 0) {
2464                 err_msg = "unable to register netdev";
2465                 goto error_out_reset;
2466         }
2467
2468         pci_set_drvdata(pdev, dev);
2469
2470         netdev_info(dev, "%s at %s 0x%llx, %pM\n",
2471                     typhoon_card_info[card_id].name,
2472                     use_mmio ? "MMIO" : "IO",
2473                     (unsigned long long)pci_resource_start(pdev, use_mmio),
2474                     dev->dev_addr);
2475
2476         /* xp_resp still contains the response to the READ_VERSIONS command.
2477          * For debugging, let the user know what version he has.
2478          */
2479         if(xp_resp[0].numDesc == 0) {
2480                 /* This is the Typhoon 1.0 type Sleep Image, last 16 bits
2481                  * of version is Month/Day of build.
2482                  */
2483                 u16 monthday = le32_to_cpu(xp_resp[0].parm2) & 0xffff;
2484                 netdev_info(dev, "Typhoon 1.0 Sleep Image built %02u/%02u/2000\n",
2485                             monthday >> 8, monthday & 0xff);
2486         } else if(xp_resp[0].numDesc == 2) {
2487                 /* This is the Typhoon 1.1+ type Sleep Image
2488                  */
2489                 u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
2490                 u8 *ver_string = (u8 *) &xp_resp[1];
2491                 ver_string[25] = 0;
2492                 netdev_info(dev, "Typhoon 1.1+ Sleep Image version %02x.%03x.%03x %s\n",
2493                             sleep_ver >> 24, (sleep_ver >> 12) & 0xfff,
2494                             sleep_ver & 0xfff, ver_string);
2495         } else {
2496                 netdev_warn(dev, "Unknown Sleep Image version (%u:%04x)\n",
2497                             xp_resp[0].numDesc, le32_to_cpu(xp_resp[0].parm2));
2498         }
2499
2500         return 0;
2501
2502 error_out_reset:
2503         typhoon_reset(ioaddr, NoWait);
2504
2505 error_out_dma:
2506         pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2507                             shared, shared_dma);
2508 error_out_remap:
2509         pci_iounmap(pdev, ioaddr);
2510 error_out_regions:
2511         pci_release_regions(pdev);
2512 error_out_mwi:
2513         pci_clear_mwi(pdev);
2514 error_out_disable:
2515         pci_disable_device(pdev);
2516 error_out_dev:
2517         free_netdev(dev);
2518 error_out:
2519         pr_err("%s: %s\n", pci_name(pdev), err_msg);
2520         return err;
2521 }
2522
2523 static void __devexit
2524 typhoon_remove_one(struct pci_dev *pdev)
2525 {
2526         struct net_device *dev = pci_get_drvdata(pdev);
2527         struct typhoon *tp = netdev_priv(dev);
2528
2529         unregister_netdev(dev);
2530         pci_set_power_state(pdev, PCI_D0);
2531         pci_restore_state(pdev);
2532         typhoon_reset(tp->ioaddr, NoWait);
2533         pci_iounmap(pdev, tp->ioaddr);
2534         pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2535                             tp->shared, tp->shared_dma);
2536         pci_release_regions(pdev);
2537         pci_clear_mwi(pdev);
2538         pci_disable_device(pdev);
2539         pci_set_drvdata(pdev, NULL);
2540         free_netdev(dev);
2541 }
2542
2543 static struct pci_driver typhoon_driver = {
2544         .name           = KBUILD_MODNAME,
2545         .id_table       = typhoon_pci_tbl,
2546         .probe          = typhoon_init_one,
2547         .remove         = __devexit_p(typhoon_remove_one),
2548 #ifdef CONFIG_PM
2549         .suspend        = typhoon_suspend,
2550         .resume         = typhoon_resume,
2551 #endif
2552 };
2553
2554 static int __init
2555 typhoon_init(void)
2556 {
2557         return pci_register_driver(&typhoon_driver);
2558 }
2559
2560 static void __exit
2561 typhoon_cleanup(void)
2562 {
2563         if (typhoon_fw)
2564                 release_firmware(typhoon_fw);
2565         pci_unregister_driver(&typhoon_driver);
2566 }
2567
2568 module_init(typhoon_init);
2569 module_exit(typhoon_cleanup);